ANALOG DEVICES CMOS y.P-Compatible 8-Bit, 8-Channel DAS AD7581 FEATURES 8-Bit Resolution On-Chip 8 X 8 Dual-Port Memory No Missed Codes Over Full Temperature Range Interfaces Directly to 280/8085/6800 CMOS, TTL Compatible Digital Inputs Three-State Data Drivers Ratiometric Capability Interleaved DMA Operation Fast Conversion A/D Process Totally Transparent to uP Low Cost GENERAL DESCRIPTION The AD7581 is a microprocessor compatible 8 bit, 8 channel, memory buffered, data-acquisition system on a monolithic CMOS chip. It consists of an 8 bit successive approximation A/D converter, an 8 channel multiplexer, 8 X 8 dual-port RAM, three-state DATA drivers (for interface), address latches and microprocessor compatible control logic. The device inter- faces directly to 8080, 8085, Z80, 6800 and other micro- processor systems. The successive approximation conversion takes place on a continuous, channel sequencing, basis using microprocessor control signals for the clock. Data is automatically transferred to its proper location in the 8 X 8 dual-port RAM at the end of each conversion. When under microprocessor control, a READ DATA operation is allowed at any time for any channel since on-chip logic provides interleaved DMA. The facility to latch the address inputs (Ag - Az) with ALE enables the AD7581 to interface with uP systems which feature either shared or separate address and data buses. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Von Vrer Bors 1 AIN AIN AD7581 AIN AIN AIN AIN AIN 8.BIT DAC AIN THREE STATE ORIVERS DB7 - OBO SUCCESSIVE DATA OUT APPROXIMATION {20 - 27) REGISTER INTERFACE AND ADDRESS CONTROL LOGIC LATCHES cs DGNO CLK STAT ALE AO Al AZ One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Telex: 924491 Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASSAD7581SPECIFICATIONS DC SPECIFICATIONS (,. = +5V, Vice = 10V, Unipolar Operation, unless otherwise stated.) Typical at Limit Over Parameter Version | +25C Temperature Units Conditions/Comments ACCURACY Resolution All 8 8 Bits Relative Accuracy JN, AQ +1 7/8 +1 7/8 max LSB KN, BQ | +3/4 +3/4 max LSB LN, CQ | +1/2 +1/2 max LSB Differential Nonlinearity JN, AQ +1 7/8 +1 7/8 max LSB KN, BQ | +7/8 +7/8 max LSB LN, CQ | +3/4 +3/4 max LSB Offset Error JN, AQ 200 200 max mV Adjustable to zero, See Figure 7a. KN, BQ | 80 80 max mV LN, CQ | 50 50 max mV Gain Error Worst Channel JN, AQ +3 +6 max LSB Adjustable to zero, See Figure 7a. KN, BQ | +2 +4 max LSB Gain Error Is Measured After Offset LN, CQ | +1 +2 max LSB Calibration. Max Full Scale Change for Any Channel from +25C to Trin OF Trax Is +Z2LSB. Gain Match Between Channels JN, AQ | 2 3 max LSB Adjustable to zero, See Figure 7a. KN, BQ | 11/2 2 max LSB LN, CQ | 1 1 max LSB Bors Gain Error All 2 1/2 - LSB ANALOG INPUTS Input Resistance At Veer (Pin 10) All 10/20/30 10/20/30 kQ min/typ/max At Bogs (Pin 1)? All 10/20/30 10/20/30 kQ, min/typ/max At Any Analog Input (Pins 2-9) All 10/20/30 10/20/30 kQ min/typ/max Varer (For Specified Performance) All 10 -10 Vv 45% Veer Range* All 5 to -15 5 to -15 Vv Nominal Analog Input Range Unipolar Mode All 0 to + Veer 0 to +Vper Vv See Figure 7 and 8. 0 to Vper 0 to Veer Vv : Bipolar Mode All VBors= VAw=!Vper!VBors See Figure 9 DIGITAL INPUTS CS (Pin 13), ALE (Pin 16) Ay - A, (Pin 17-19), CLK (Pin 15) Vinu Logic HIGH Input Voltage All +2.2 +2.4 min v Vint Logic LOW Input Voltage All +1.2 +0.8 max Vv Tpy Input Current All 0.01 1 max pA Vin = 0V; Vop Cyy Input Capacitance* All 4 5 max pF DIGITAL OUTPUTS STAT (Pin 12), DB, to DB, (Pins 20-27) Vou Output HIGH Voltage All +4.8 +4.5 min v Tsource = 40pA Vo. Output LOW Voltage All +0.4 +0.6 max Vv Ig~_ex = L6mA ILxg DB; to DBy Floating State Leakage All 0.3 10 max pA Floating State Output Capacitance (DB,-DB,) All 5 10 max pF Vout = 0V to Vpp Output Code All Unipolar Binary Figure 7 Complementary Binary Figure 8 Offset Binary Figure 9 POWER REQUIREMENTS Vop All +5 +5 Vv Ipp Static All 3 typ 5 max mA Ipp Dynamic All 3 typ 8 max mA fork =1MHz NOTES Temperature range as follows: JN, KN, LN (0 to +70C); AQ, BQ, CQ (25C to +85C). ?Typical offset temperature coefficient is +150uV/C. 3Rgors/Ram (0-7) mismatch causes transfer function rotation about positive full scale. The effect is an offset and a gain term when using the circuits of Figure 8a and Figure 9a. Typical value, not guaranteed or subject to test. Guaranteed but not tested. Typical change in Boys gain from +25C to Tj, to Trex 18 +2LSBs. Specifications subject to change without notice. REV. AAD7581 GENERAL CIRCUIT INFORMATION BASIC CIRCUIT DESCRIPTION The AD7581 accepts eight analog inputs and sequentially con- verts each input into an eight-bit binary word using the succes- sive approximation technique. The conversion results are stored in an 8 X 8 bit dual-port RAM. The device runs either directly from the microprocessor clock (in 6800 type systems) or from some suitable signal (e.g. ALE in 8085 type systems). Most applications require only a -10V reference and a +5V supply. Start-up logic is included on the device to establish the correct sequences on power-up. A maximum of 800 clock pulses are required for this period. Figure 1 shows the AD7581 functional diagram. Vop VaEF Bors 1 AIN AIN AIN AIN AIN AIN AIN B.BIT DAC AIN THREE 8x8 STATE OATA DRIVERS MEMORY 0B? - DBO DATA OUT (20 - 27) SUCCESSIVE APPROXIMATION REGISTER ADDRESS INTERFACE AND LATCHES CONTROL LOGIC os OGND CLK STAT ALE AO Al A2 Figure 1. AD7581 Functional Diagram Conversion of a single channel requires 80 input clock periods and a complete scan through all channels requires 640 input clock periods. When a channel conversion is complete, the suc- cessive approximation register contents are loaded into the proper channel location of the 8 X 8 RAM. At this time a status signal output, STAT (pin 12), gives a short negative going pulse (8 clock periods). This negative going STAT pulse is extended to 72 clock periods when channel 1 conversion is complete. An external pulse-width detector connected to the status pin can be used to derive conversion-related timing sig- nals for microprocessor interrupts (see Channel Identification opposite page). Simultaneous with STAT going low, the MUX address is decremented. Eight clock periods later the next con- version is started, Automatic interleaved DMA is provided by on-chip logic to ensure that memory updates take place at instants when the microprocessor is not addressing memory. Memory locations are addressed by Ag, Ay and Az. This address may be latched by ALE for systems which feature a multiplexed address/data bus or alternatively, for systems which have separate address and data buses, the address latches can be made transparent by tying ALE (pin 16) HIGH. CS (pin 13) activates three-state buffers to place addressed data on the DBg - DB7 data out- put pins. A/D CIRCUIT DETAILS In the successive approximation technique, successive bits, starting with the most significant bit (DB7), are applied to the input of the D/A converter. The DAC output is then compared to the unknown analog input voltage, Apy (n), using a com- parator. If the DAC output is greater than Ayn(n), the data latch for the trial bit is reset to zero, and the next smaller data bit is tried. If the DAC output is less than Ayy(n), the trial data bit stays in the 1 state, and the next smaller data bit is tried. Each successive bit is tried, compared to Ayy(n), and set or reset in this manner until the least significant bit (DBg) decision is made. The successive approximation register now contains a valid digital representation of Ayy(n). Apy(n) is assumed to be stable during conversion. The current weighting D/A converter is a precision multiplying DAC. Figure 2 shows the functional diagram of the DAC as used in the AD7581. It consists of a precision Silicon Chromi- um thin film R/2R ladder network and 8 N-channel MOSFET switches operated in single-pole-double-throw. The currents in each 2R shunt arm are binarily weighted i.e., the current in the MSB arm is Vpgr divided by 2R, in the second arm is Vyrr divided by 4R, etc. Depending on the D/A logic input (A/D output) from the successive approxima- tion register, the current in the individual shunt arms is steered either to AGnp or to the comparator summing point. AIN (0) AIN(7) Bors 4 4 } SUMMING POINT 9 9 + +t LSB 1 ( l { | I a) | ! ' ! I I 1 MSB | DB? ,DB6 | DBS SUCCESSIVE APPROXIMATION REGISTER COMPARATOR AGND ] CONTROL LoGIc Figure 2. D/A Converter as Used in AD7581 REV. AAD7581 AC SPECIFICATIONS vy, = +5, Veer = 10, Unipotar Operation, unless otherwise stated.) Typical at Limit Over Symbol Specification +25C Temperature Units Conditions ty ALE pulse width 50 80 min ns See Switching Terminology TALS Address valid to latch set-up time 45 70 min ns tatH Address valid to latch hold time 10 20 min ns tucs Address latch to CS set-up time 10 20 min ns tacc CS to output propagation delay 200 250 max ns Cy = 100pF tcw CS pulse width 250 280 min ns tcr CS to output float propagation delay 50 80 max ns tcLz CS to low impedance bus 100 150 max ns fcoLk Clock frequency for stated accuracy 1600 1200 max! kHz Guaranteed conversion time of 66.6us/channel with 1200kHz clock. ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION VpptoAGND ........ 000. eee eee ees +7V Bors Uw ean Vpp to DGND SS +7V AIN 7{2] 27 ) DBO {LSB} AGNDtwDGND................ 0.3V, Vop AIN 63] [26] DB1 Digital Input Voltage to DGND ans [4 Eapcs (Pins 13, 16-19) ........... -0.3V, Vpp +0.3V ain a(s | [24] DB3 Digital Output Voltage to DGND ains(] AD7581 [23] ppa (Pins 12, 20-27) ........... -0.3V, Vpp +0.3V ain2Cz] TOP VIEW [35] pes CLK (Pin 15) Input Voltage to DGND . 0.3V, Vpp +0.3V antGe] Fr one Vrer (Pin 10)toAGND .........0..00200. +25V AIN o[e] [20] 0B7 (MSB) Veors (Pin 1)toAGND .........0 0.20508 +17V Vcr (90) ia] a2 AIN (0-7)(Pin 9-2) 2. ee ee +17V acno [it] ia] ai Operating Temperature Range stat [2| 17] a0 Commercial (J, K, L Versions) ......... 0 to +70C cs [13 Te] ALE Industrial (A, B, C Versions) ........ 25C to + 85C ponp [14 15) CLK Storage Temperature ............ 65C to + 150C Lead Temperature (Soldering, 10secs) ........ + 300C Power Dissipation (Any Package) to+75C 2. ee es 1,000mW Derate above +75C by ............4. 10mW/C CAUTION WARNING! eae ESD SENSITIVE DEVICE ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- ed; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The pro- tective foam should be discharged to the destination socket before devices are removed. ORDERING GUIDE Temperature Differential Package Model Range Nonlinearity (LSB) | Option* AD7581JN | 0 to +70C +1 7/8 max N-28 AD7581KN | 0 to +70C +7/8 max N-28 AD7581LN | 0 to +70C +3/4 max N-28 AD7581AQ | 25C to +85C | +1 7/8 max Q-28 AD7581BQ | 25C to +85C | +7/8 max Q-28 AD7581CQ | 25C to +85C | +3/4 max Q-28 NOTE *N = Plastic DIP; Q = Cerdip. For outline information see Package Information section. REV. A 3.AD7581 TIMING AND CONTROL OF THE AD7581 CHANNEL SELECTION Table I shows the truth table for the address inputs. The input address is latched when ALE goes LOW. When ALE is HIGH the address input latch is transparent. Channel Data A2 Al AO ALE To Be Read 0 0 0 1 Channel 0 0 0 1 1 Channel 1 0 1 0 1 Channel 2 0 1 1 1 Channel 3 1 0 0 1 Channel 4 1 0 1 1 Channel 5 1 1 0 1 Channel 6 1 1 1 1 Channel 7 Table |. Channel Selection Truth Table TIMING AND CONTROL A typical timing diagram is shown in Figure 3. When CS is HIGH, the three-state data drivers are in the high-impedance state. When CS goes LOW the data drivers switch to the low- impedance state (i.e., low impedance to DGND or to Vpp). Output data is valid after time tacc. pu atat Nh / \ tas} | tALH AO, A1, AZ ADDR (PINS 17, 18,19) VALID. [ae oN 13) \ / a tor NON BUS FLOATING VAL VALID BATA, (DATA Figure 3. Timing Diagram for the AD7581 OB? - DBO (PINS 20-27) m| tcLz SWITCHING TERMINOLOGY ty: ALE pulse width requirement. taLy:Address Valid to latch hold time. tars: Address Valid to latch set-up time. tics: Address latch to Chip Select set-up time. tcw: Chip Select pulse width requirement. tacc:Chip Select to valid data propagation delay. tcr: Chip Select to output data float propagation delay. tcLz: Chip Select to low impedance data bus. CHANNEL IDENTIFICATION In some real-time applications, it may be necessary to provide an interrupt signal when a particular channel receives updated data. To achieve this, it is necessary to identify which channel is currently under conversion. The STAT output provides an REV. A identifying signal by staying low for an additional 64 clock periods over normal (8 clock periods) when channel 0 is active. This is illustrated in Figure 4. Memory update takes place on a rising edge of a clock pulse and is completed in 200ns, This occurs 6 clock periods before STAT goes low. -- 80 CLOCK PERIODS | FOR CHANNELS 1TO7 4 5 STAT a@cCLOcK 8 CLOCK PERIODS PERIODS URRENT PREVIOUS CHANNEL START NEXT CHANEL DATA UPDATE CONVERSION COMPLETE, WITH MSB DATA MUX ADDRESS TRIAL UPDATE DECREMENTED COMPLETE FOR CHANNEL 6 $ > STAT | scrock 64 CLOCK PERIODS | bet Bes 8 CLOCK a clock | .- PERIODS PERIODS CHANNEL 1 START CHANNEL 0 CHANNEL 0 UPDATE PDATE TRIAL U IA COMPLETE, MUX ADDRESS RESET TO CHANNEL ? Figure 4. STAT Output for Channel Identification One simple circuit using the STAT output is shown in Figure 5. The time constant RC is chosen such that Xz ignores the normal STAT low pulse width (8 clock periods wide) but respond to the much wider STAT low pulse width (72 clock periods wide) occurring during channel 0 conversion. Typically for a 1s clock period C = 0,022uF, R = 1.8kQ. 1/6 CD40039A 1/6 CD4009A STAT ey x2 1/6 CD4009A GOES HIGH WHEN CHANNEL 0 IS ACTIVE c Figure . Hardware Channel Identification Another possibility is to use the microprocessor to interrogate the STAT output and hence determine channel identity. A simple routine is shown in Figure 6. STAT Figure 6. Software Channel IdentificationAD7581 OPERATING THE AD7581 UNIPOLAR BINARY OPERATION Figures 7a and 7b show the analog circuit connections and typical transfer characteristic for unipolar operation (OV to +10V). An AD584 is used for the -10V reference. Calibration is as follows (device clocked i.e., continuous conversions); OFFSET: Comparator offset is trimmed out via the bipolar offset pin Bors. R10, R11 and R12 comprise a simple voltage tap buffered by A1 and feeding into Bogs. 1, Since comparator offset will be the same regardless of which channel is active, take Ap, Ay and Az LOW and and exercise ALE to latch the address. . With AIN 0 = 19.5mV (1/2LSB) adjust R11, ie., the offset voltage on Bors, until DB7 - DB; are LOW and DBg (LSB) flickers. +5V +5V -10Vper. RIG! 27% 5% R11" 3 > Ri? 2 o yet] AD7581 TOP VIEW AIN? AIN 6 R12" 56x 5% OFFSET ADJUST REFERENCE ADSa4 FEEEREEEEEwESE ANALOG DIGITAL SUPPLY RETURN SUPPLY RETURN NOTE: AI, 0, R11 AND R12 CAN BE OMITTED IF OF FSET TRIM IS NOT REQUIRED AND Bors CAN BE TIED TO AGND. 7R1-RB AND RO CAN BE OMITTED IF GAIN TRIM IS NOT REQUIRED. Figure 7a. AD7581 Unipolar (OV to +10V) Operation (Output Code is Straight Binary) GAIN (FULL SCALE) In many applications gain adjustment is not required thus removing the need for trimmers in the analog channels. For channels requiring gain trim, the following procedure is recom- mended. Offset adjustment must be performed before gain adjustment. 1. Apply +9.941V (FS - 3/2LSB) to all input channels AIN (0-7). . Select required channel n via Ag, Ay, Az and latch the Address using ALE. . Adjust trimmer RN of selected channel until DB? - DB, are HIGH and the LSB (DBo) flickers. . Select next channel requiring gain trim and repeat steps 2 and 3. OUTPUT CODE FULL SCALE TRANSITION 11799711 11111110 11111101 s 00000011 oao000010 00000001 00000000 0 0.400.80 1.20 9,92 9,96'10.00 INPUT VOLTAGE, VOLTS (REFERRED TO ANALOG GROUND} APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION. BIT WEIGHT FOR A -10V REFERENCE IS ~39,1mvV. NOTE: Figure 7b, Transfer Characteristic for Unipolar Circuit of Figure 7a UNIPOLAR (COMPLEMENTARY BINARY) OPERATION Figures 8a and 8b show the analog circuit connections and typical transfer characteristic for unipolar (complementary binary) operation. Calibration is as follows (continuous conversions); OFFSET: Comparator offset is trimmed out via the bipolar offset pin Bors. R10, R11 and R12 comprise a simple voltage tap buf- fered by Al and feeding into Bors. 1. Since comparator offset will be the same regardless of which channel is active, take Ag, Ay and Ay LOW and exercise ALE to latch the address. . With AIN 0 = -9.98V (-FS + 1/2LSB) adjust R11, ie., the offset voltage on Bors, until DB7 - DB, are LOW and the LSB (DBo) flickers. A115 10k 0.1% Rito! Ae av 27k 5% a - VS ' | Al 7 at Ru RI? 2k 20k OFFSET AINT OWwaf Z| [27] 40V ADJUST | AING 3 26) R12) > R14 10k R22 2k 56k 5% ae F 01K 1 4 [25] Rie? $ 68k ANALOG ' G [23] INPUT -10v TOov | (2) = apzsst [23] -15V ' @ TOP VIEW [22] 1 lo & 21] R13 R82 2k 1 1.2k AINO Q [20] ADS584 4 mwaSiol REFERENCE TOV WA 118 3) RS? 1k 10% Fa] 7 : 16] 15] ANALOG DIGITAL SUPPLY RETURN SUPPLY RETURN NOTES: R10, R11 AND R12 CAN BE OMITTED IF OFFSET TRIM IS NOT REQUIRED. 71 - R8 AND R9 CAN BE OMITTED IF GAIN TRIM IS NOT REQUIRED. 3R16/R10/R12= 5k&. IF R10, R11 AND R12 ARE NOT USED, MAKE R16=5k&. Figure 8a, AD7581 (OV to -10V) Operation (Output Code is Complementary Binary) REV. AAD7581 GAIN (FULL SCALE) In many applications gain adjustment is not required thus removing the need for trimmers in the analog channels. For channels requiring gain trim, the following procedure is recom- mended. Offset adjustment must be performed before gain adjustment. 1) Apply -58.6mV (3/2LSB) to all input channels AIN (0-7). 2) Select required channel n via Ag, Ai, Az and exercise ALE to latch the address. 3) Adjust trimmer RN of selected channel until DB7 - DB1 are HIGH and the LSB (DBg) flickers. 4) Select next channel requiring gain trim and repeat step 2 and 3. OUTPUT CODE 111191111 11111110: 11411101 I ? ! ' s ! ! 4 00000011 00000010 oaoco0at 00000000 Ly seotameto -10 -9.6 9.2 0.160 | -0.08 0 INPUT VOLTAGE, VOLTS (REFERRED TO ANALOG GROUND) NOTE: APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION. BIT WEIGHT FOR A -10V REFERENCE IS ~ 39. 1mvV. Figure 8b. Transfer Characteristic for Unipolar Circuit of Figure 8a BIPOLAR (OFFSET BINARY) OPERATION Figures 9a and 9b illustrate the analog circuitry and transfer characteristic for +5V bipolar operation. Output coding is of f- set binary. Comparator offset correction is again applied to the Bors pin. Calibration is as follows (continuous conversions); OFFSET: 1. Apply -4.980V (-FS/2 + 1/2LSB) to all input channels AIN (0-7). 2. Trim R11 of the comparator offset circuit until DB7-DBy are LOW and the LSB (DBg) flickers. GAIN (FULL SCALE) 1. Apply +4.941V (+FS/2 -3/2LSB) to all input channels, Aw (0-7). 2. Select required channel n via Ag, Ay, Az, and latch the address using ALE. 3. Adjust trimmer RN of selected channel until DB7 - DB; are HIGH and the LSB (DBo) flickers. REV. A 4, Select next channel requiring gain trim and repeat steps 2 and 3. 5. Apply -19.5mV to each gain-trimmed channel. If the ADC output code does not flicker between 01111111 and 10000000 repeat the calibration procedure, R15 10k 0.1% 27k 5% +5V QA nano is Al R11 + Ri? 2k 20k = OFFSET AIN7 2 ST -10V ow] ADIU | AIN6 O- par | R12! $ R14 20k R22 2 B6k 5% > 0.1% 1 4 AD7581 R1G* 2 ! fe TOP VIEW 10k ANALOG =, INPUT -vTO+Bv ! Kk -15V ' wa | 8 R13 ' 8? 2k & 4 10k AINDO 9 4 AMA {70 R9? 1k 10% ADS84 REFERENCE -10V VAEF 8 +4 = Es EEEEEESEERESE 1 ANALOG SUPPLY RETURN DIGITAL RN UPR: ETU NOTES: SUPPLY R 1R10, R11 AND R12 CAN BE OMITTED IF OFFSET TAIM IS NOT REQUIRED. 2R1-R8 AND RS CAN BE OMITTED IF GAIN TRIM (S NOT REQUIRED. 3R16/R10/R12 = 6.8k22. IF R10, R11 AND'R12 ARE NOT USED, MAKE R16 =6.8k2.. Figure 9a, AD7581 Bipolar (-5V to +5V) Operation (Output Code is Offset Binary) 100001004 T 100000114 100000104 t 10000001 10000000 011111114 011111104 01111701 01111100 1 1 i 4 Tt T q v +40 +80 +120 +160 +200 01411011 +_+_+_++ T T T -200 -160 -120 -80 -40 INPUT VOLTAGE, MILLIVOLTS (REFERRED TO ANALOG GROUND) NOTE: APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION. BIT WEIGHT FOR 10V FULL SCALE IS ~ 39.1mV. Figure 9b. Transfer Characteristic Around Major Carry for. Bipolar Circuit of Figure 9aAD7581 INTERFACING THE AD7581 ADDRESS BUS (16} AO - AZ A0- A15 | A13 - A1S -~_- - AQ) Al AZ AOD Al A2 VMA EN as 74LS138 AD7581 ea00 +5V Ome] ALE 1 CLK DBO - DB? Do -07 DAT A BUS {8} ) Figure 10. AD7581/6800 Interface NOTES: 1, ANALOG AND DIGITAL GROUND It is recommended that AGNp and Dgnp be connected locally to prevent the possibility of injecting noise into the AD7581. In systems where the AgNp - Dgnp intertie is not local, connect back-to-back diodes (1N914 or equiv- alent) between the AD7581 Acnp and Denp pins. A13 - A1S ADDRESS BUS (8) ) ADO - AD? | ADDRESS/DATA BUS Figure 11, AD7581/8085 Interface 2. LOGIC DEGLITCHING IN pP APPLICATIONS Unspecified states on the address bus (due to different rise and fall times on the address bus) can cause glitches at the AD7581 CS terminal. These glitches can cause unwanted reads. The best way to avoid glitches is to gate the address decoding logic, e.g., with RD (8080), RD (8085) or VMA (6800). MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-PIN CERAMIC DIP (D-28) 0.698 116.19) ) 0.568 (14.43) on SS Ps SS 0.08 (3.05) (4.32) | 1.414 (35.92) 2 2 1153) max [ 1.38 (35.06) _ _. 0.012 (0.308) ~| T 0.008 (0.203) be 0.606 06.4) 0.75 (4.45) I ose 04.74) 0.065 {1.66} 0.02 (0.508) _0.105 (2.67) 0125 (3.18) 0.045 (1.15) 0.015 (0.381) -0.095 (2.42) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS WILL BE EITHER GOLD OR TIN FLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS CAVITY LID |: IS ELECTRICALLY ISOLATED 28-PIN PLASTIC DIP (N-28) LAS AAAAAAALAALA > 0.55 (13.97) 0.53 113.47) VV TU A 0.16 (4.07) 0.606 (15.4) 0.14 (3.56) - 0.594 (15.09) { VA AS 1.45 (36.83) 1.44 (36.58) 0.2 (5.08) MAX = 0.065 (1.66) 0.045 (1.15) 0.02 (0.508) 0.105 0.M5 (0.381) 0.096 poy 0.012 (0.305) 0.008 (0.203) 0.175 (4.45) 0.12 (3.05) (2.67) (2.42) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER PLATED KOVAR OR ALLOY 42 3. REV. A C575c2-5/89 PRINTED IN U.S.A.