VDD
INA_0+
INA_0-
AD0
AD1
AD2
AD3 ENSMB
SCL(2)
READ_EN
ALL_DONE
SDA(2)
OUTA_0+
OUTA_0-
.
.
.
.
.
.
GND
.
.
.
(1) Schematic requires different connections for SMBus Master Mode and Pin Mode
(2) SMBus signals need to be pulled up elsewhere in the system.
(3) Schematic requires different connections for 3.3 V mode
.
.
.
VDD
To system
SMBus
Address
straps
(pull-up or
pull-down)
1F 0.1F
(5x)
SMBus
Slave Mode(1)
2.5V
.
.
.
INA_3+
INA_3- OUTA_3+
OUTA_3-
SMBus
Slave Mode(1)
VDD_SEL
VIN
2.5 V
Mode(3)
INB_0+
INB_0- OUTB_0+
OUTB_0-
.
.
.
.
.
.
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.
.
.
.
.
.
.
.
INB_3+
INB_3- OUTB_3+
OUTB_3-
10F
System Board
Root Complex
ASIC
or
PCIe EP
DS80PCI810
Board
Trace
Connector
Connector
TX
RX
RX
TX 8
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DS80PCI810
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DS80PCI810 Low-Power 8 Gbps 8-Channel Linear Repeater
1 Features 3 Description
The DS80PCI810 is an extremely low-power high-
1• Low 70 mW/Channel (Typ) Power Consumption, performance repeater/redriver designed to support
With Option to Power Down Unused Channels eight channels carrying high speed interface up to 8
• Seamless Link Training Support Gbps, such as PCIe Gen-1, 2, and 3. The receiver's
• Advanced Configurable Signal Conditioning I/O continuous time linear equalizer (CTLE) provides high
frequency boost that is programmable from 2.7 to 9.5
– Receive CTLE up to ~10 dB at 4 GHz dB at 4 GHz (8 Gbps) followed by a linear output
– Linear Output Driver driver. The CTLE receiver is capable of opening an
– Variable Output Voltage Range up to 1200 input eye that is completely closed due to inter
mVp-p symbol interference (ISI) induced by interconnect
medium such as board traces or twin axial-copper
• Automatic Receiver Detect (Hot-Plug) cables. The programmable equalization maximizes
• Ultra-Low Input-to-Output Latency: 80 ps (Typ) the flexibility of physical placement within the
• Programmable via Pin Selection, EEPROM, or interconnect channel and improves overall channel
SMBus Interface performance.
• Single Supply Voltage: 2.5 V or 3.3 V When operating in PCIe applications, the
• 4 kV HBM ESD Rating DS80PCI810 preserves transmit signal
characteristics, thereby allowing the host controller
•−40°C to 85°C Operating Temperature Range and the end point to negotiate transmit equalizer
• Flow-Thru Layout in 10 mm x 5.5 mm 54-Pin coefficients. This transparency in the link training
Leadless WQFN Package protocol facilitates system level interoperability and
• Pin Compatible with DS80PCI800 minimizes latency.
The programmable settings can be applied easily via
2 Applications pin control, software (SMBus or I2C), or direct loading
from an external EEPROM. In EEPROM mode, the
• PCI Express Gen-1, 2, and 3 configuration information is automatically loaded on
• Other Proprietary High Speed Interfaces Up to 8 power up, thereby eliminating the need for an
Gbps external microprocessor or software driver.
Simplified Functional Block Diagram Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DS80PCI810 WQFN (54) 10 mm x 5.5 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS80PCI810
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
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Table of Contents
7.3 Feature Description................................................. 15
1 Features.................................................................. 17.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 17.5 Programming........................................................... 18
3 Description............................................................. 17.6 Writing a Register ................................................... 26
4 Revision History..................................................... 27.7 Reading a Register ................................................. 27
5 Pin Configuration and Functions......................... 37.8 Register Maps......................................................... 28
6 Specifications......................................................... 78 Applications and Implementation ...................... 41
6.1 Absolute Maximum Ratings ...................................... 78.1 Application Information............................................ 41
6.2 ESD Ratings.............................................................. 78.2 Typical Applications ................................................ 42
6.3 Handling Ratings ...................................................... 79 Power Supply Recommendations...................... 50
6.4 Recommended Operating Conditions....................... 710 Layout................................................................... 51
6.5 Thermal Information ................................................. 810.1 Layout Guidelines ................................................. 51
6.6 Electrical Characteristics........................................... 810.2 Layout Example .................................................... 51
6.7 Electrical Characteristics — Serial Management Bus
Interface .................................................................. 11 11 Device and Documentation Support................. 52
6.8 Timing Requirements Serial Bus Interface ............. 11 11.1 Trademarks........................................................... 52
6.9 Typical Characteristics............................................ 13 11.2 Electrostatic Discharge Caution............................ 52
11.3 Glossary................................................................ 52
7 Detailed Description............................................ 14
7.1 Overview................................................................. 14 12 Mechanical, Packaging, and Orderable
Information........................................................... 52
7.2 Functional Block Diagram....................................... 14
4 Revision History
Changes from Original (September 2014) to Revision A Page
• Changed pin assignment numbers for OUTB_2+/- and OUTB_3+/- to correct typo ............................................................. 4
• Changed ENSMB pin type to 4-level LVCMOS per input pin behavior.................................................................................. 4
• Changed Handling Ratings table to ESD Ratings table. Moved Tstg and Tsolder parameters into Absolute Maximum
Ratings table........................................................................................................................................................................... 7
• Changed register map rows to combine multiple consecutive registers with a value of all zeros and no EEPROM-
relevant bits ......................................................................................................................................................................... 29
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OUTB_0+
OUTB_0-
OUTB_1+
RESERVED1
RXDET
ALL_DONE
1
2
3
4
26
25
DAP = GND
OUTB_1-
OUTB_2+
OUTB_2-
5
6
7
24
21
20
23
INA_3-
8
INA_0+
INA_0-
VDD
INA_1+
9
10
11
12
INA_1-
EQA
INA_2+
INA_2-
13
18
14
15
INA_3+
16
17
OUTA_1+
OUTA_1-
RESERVED3
OUTA_2+
36
34
35
OUTA_2-
OUTA_3+
OUTA_3-
33
31
32
VIN
VDD_SEL
INB_3+
INB_3-
41
40
39
RESERVED2
OUTA_0+
OUTA_0-
37
38
INB_0+
INB_0-
INB_1+
INB_1-
INB_2-
INB_2+
44
42
43
VDD
VODA1/SCL
50
48
47
49 VODA0/SDA
ENSMB
46
51
OUTB_3+
OUTB_3-
SMBUS AND CONTROL
VODB1/AD0
VODB0/AD1
30
29
28
SD_TH/READ_EN
52
AD2
EQB/AD3
19
22
PWDN
27
45
53
54
VDD
VDD
VDD
DS80PCI810
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SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
5 Pin Configuration and Functions
54-Pin WQFN
Package NJY
Top View
NOTE: Above 54-lead WQFN graphic is a TOP VIEW, looking down through the package.
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Pin Functions(1)
PIN NAME PIN NUMBER I/O, TYPE DESCRIPTION
DIFFERENTIAL HIGH SPEED I/O
INB_0+, INB_0- , 1, 2 Inverting and non-inverting CML differential inputs to the equalizer.
INB_1+, INB_1-, 3, 4 On-chip 50 Ωtermination resistor connects INB_n+ to VDD and INB_n-
I, CML
INB_2+, INB_2-, 5, 6 to VDD depending on the state of RXDET. See Table 2.
INB_3+, INB_3- 7, 8 AC coupling required on high-speed I/O
OUTB_0+, OUTB_0-, 45, 44 Inverting and non-inverting 50 Ωdriver outputs. Compatible with AC
OUTB_1+, OUTB_1-, 43, 42 O, CML coupled CML inputs.
OUTB_2+, OUTB_2-, 40, 39 AC coupling required on high-speed I/O
OUTB_3+, OUTB_3- 38, 37
INA_0+, INA_0- , 10, 11 Inverting and non-inverting CML differential inputs to the equalizer.
INA_1+, INA_1-, 12, 13 On-chip 50 Ωtermination resistor connects INA_n+ to VDD and INA_n-
I, CML
INA_2+, INA_2-, 15, 16 to VDD depending on the state of RXDET. See Table 2.
INA_3+, INA_3- 17, 18 AC coupling required on high-speed I/O
OUTA_0+, OUTA_0-, 35, 34 Inverting and non-inverting 50 Ωdriver outputs. Compatible with AC
OUTA_1+, OUTA_1-, 33, 32 O, CML coupled CML inputs.
OUTA_2+, OUTA_2-, 31, 30 AC coupling required on high-speed I/O
OUTA_3+, OUTA_3- 29, 28
CONTROL PINS — SHARED (LVCMOS)
System Management Bus (SMBus) Enable Pin
Tie 1 kΩto VDD (2.5 V mode) or VIN (3.3 V mode) = Register Access
I, 4-LEVEL,
ENSMB 48 SMBus Slave Mode
LVCMOS FLOAT = Read External EEPROM (SMBus Master Mode)
Tie 1 kΩto GND = Pin Mode
ENSMB = 1 (SMBus SLAVE MODE)
In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or
I, LVCMOS, open drain output.
SCL 50 O, OPEN Drain External 2 kΩto 5 kΩpull-up resistor required as per SMBus interface
standards(2)
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
I, LVCMOS, open drain output.
SDA 49 O, OPEN Drain External 2 kΩto 5 kΩpull-up resistor required as per SMBus interface
standards(2)
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
AD0-AD3 54, 53, 47, 46 I, LVCMOS External 1 kΩpull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩto GND.
Reserved
For applications requiring Signal Detect status register read-back:
I, 4-LEVEL, ●Leave Pin 21 floating.
RESERVED2 21 LVCMOS ●Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩto GND (External 1 kΩto VDD
(2.5 V mode) or VIN (3.3 V mode) is also acceptable).
Reserved
I, 4-LEVEL,
RESERVED3 19 This input may be left floating, tied via 1 kΩto VDD (2.5 V mode) or VIN
LVCMOS (3.3 V mode), or tied via 1 kΩto GND.
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3 V mode operation, VIN pin input = 3.3 V and the logic "1" or "high" reference for the 4-level input is 3.3 V.
For 2.5 V mode operation, VDD pin output= 2.5 V and the logic "1" or "high" reference for the 4-level input is 2.5 V.
(2) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.
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Pin Functions(1) (continued)
PIN NAME PIN NUMBER I/O, TYPE DESCRIPTION
ENSMB = Float (SMBus MASTER MODE)
Clock output when loading EEPROM configuration, reverting to SMBus
I, LVCMOS, clock input when EEPROM load is complete (ALL_DONE = 0).
SCL 50 O, OPEN Drain External 2 kΩto 5 kΩpull-up resistor required as per SMBus interface
standards(2)
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
I, LVCMOS, open drain output.
SDA 49 O, OPEN Drain External 2 kΩto 5 kΩpull-up resistor required as per SMBus interface
standards(2)
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
AD0-AD3 54, 53, 47, 46 I, LVCMOS External 1 kΩpull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩto GND.
A logic low on this pin starts the load from the external EEPROM(3).
READ_EN 26 I, LVCMOS Once EEPROM load is complete (ALL_DONE = 0), this pin functionality
remains as READ_EN. It does not revert to an SD_TH input.
Reserved
For applications requiring Signal Detect status register read-back:
I, 4-LEVEL, ●Leave Pin 21 floating.
RESERVED2 21 LVCMOS ●Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩto GND (External 1 kΩto VDD
(2.5 V mode) or VIN (3.3 V mode) is also acceptable).
Reserved
I, 4-LEVEL,
RESERVED3 19 This input may be left floating, tied via 1 kΩto VDD (2.5 V mode) or VIN
LVCMOS (3.3 V mode), or tied via 1 kΩto GND.
ENSMB = 0 (PIN MODE)
EQA and EQB pins control the level of equalization for the A-channels
and B-channels, respectively. The pins are defined as EQA and EQB
only when ENSMB is de-asserted (low). Each of the four A-channels
have the same level unless controlled by the SMBus control registers.
EQA 20 I, 4-LEVEL, Likewise, each of the four B-channels have the same level unless
EQB 46 LVCMOS controlled by the SMBus control registers.
When the device operates in Slave or Master Mode, the SMBus registers
independently control each lane, and the EQB pin is converted to an
AD3 input. See Table 4.
VODB[1:0] controls the output amplitude of the B-channels. The pins are
defined as VODB[1:0] only when ENSMB is de-asserted (low). Each of
VODB0 53 I, 4-LEVEL, the four B-channels have the same level unless controlled by the SMBus
VODB1 54 LVCMOS control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane, and
VODB[1:0] pins are converted to AD0, AD1 inputs. See Table 5.
VODA[1:0] controls the output amplitude of the A-channels. The pins are
defined as VODA[1:0] only when ENSMB is de-asserted (low). Each of
VODA0 49 I, 4-LEVEL, the four A-channels have the same level unless controlled by the SMBus
VODA1 50 LVCMOS control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane and the
VODA[1:0] pins are converted to SCL and SDA. See Table 5.
Reserved in Pin Mode (ENSMB = 0)
AD2 47 I, LVCMOS This input must be tied via external 1 kΩto GND.
Controls the internal Signal Detect Status Threshold value when in Pin
Mode and SMBus Slave Mode. This pin is to be used for system
I, 4-LEVEL, debugging only, as the signal detect threshold has no impact on the data
SD_TH 26 LVCMOS path. See Table 3 for more information.
For final designs, input can be left floating, tied via 1 kΩto VDD (2.5 V
mode) or VIN (3.3 V mode), or tied via 1 kΩto GND.
Reserved
I, 4-LEVEL,
RESERVED2 21 Tie via external 1 kΩto GND (External 1 kΩto VDD (2.5 V mode) or VIN
LVCMOS (3.3 V mode) is also acceptable).
(3) When READ_EN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to
an invalid or blank hex file, the DS80PCI810 waits indefinitely in an unknown state where SMBus access is not possible. ALL_DONE pin
remains high in this situation.
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Pin Functions(1) (continued)
PIN NAME PIN NUMBER I/O, TYPE DESCRIPTION
I, 4-LEVEL, Reserved
RESERVED3 19 LVCMOS This input must be tied via external 1 kΩto GND.
CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)
The RXDET pin controls the RX detection function. Depending on the
I, 4-LEVEL, input level, a 50 Ωor >50 kΩtermination to the power rail is enabled.
RXDET 22 LVCMOS Keep this input floating for normal PCIe operation.
See Table 2.
I, 4-LEVEL, Reserved
RESERVED1 23 LVCMOS This input must be left floating.
Controls the internal regulator
Float = 2.5 V mode
VDD_SEL 25 I, FLOAT Tie to GND = 3.3 V mode
See Figure 31.
Tie High = Low power - Power Down
PWDN 52 I, LVCMOS Tie to GND = Normal Operation
See Table 2.
Valid Register Load Status Output
ALL_DONE 27 O, LVCMOS HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
POWER
In 3.3 V mode, feed 3.3 V to VIN
VIN 24 Power In 2.5 V mode, leave floating.
Power Supply for CML and Analog Pins
In 2.5 V mode, connect to 2.5 V
VDD 9, 14, 36, 41, 51 Power In 3.3 V mode, connect 0.1 µF cap to each VDD Pin and GND
See Figure 31 for proper power supply decoupling .
GND DAP Power Ground pad (DAP - die attach pad).
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Supply Voltage (VDD to GND, 2.5 V Mode) -0.5 +2.75 V
Supply Voltage (VIN to GND, 3.3 V Mode) -0.5 +4.0 V
LVCMOS Input/Output Voltage -0.5 +4.0 V
CML Input Voltage -0.5 VDD + 0.5 V
CML Input Current -30 +30 mA
Storage temperature, Tstg -40 125 °C
Tsolder Lead Temperature Range Soldering (4 sec.)(2) 260 °C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other
conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions
indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum
Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.
(2) For soldering specifications: See application note SNOA549.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1000
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
6.3 Handling Ratings MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all -4000 4000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification -1000 1000
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 4000-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Supply Voltage (2.5 V mode)(1) 2.375 2.5 2.625 V
Supply Voltage (3.3 V mode)(1) 3.0 3.3 3.6 V
Ambient Temperature -40 +85 °C
SMBus (SDA, SCL) 3.6 V
Supply Noise up to 50 MHz(2) 100 mVp-p
(1) DC plus AC power should not exceed these limits.
(2) Allowed supply noise (mVp-p sine wave) under typical conditions.
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6.5 Thermal Information NJY
THERMAL METRIC(1) UNIT
54 PINS
RθJA Junction-to-ambient thermal resistance 26.6
RθJCtop Junction-to-case (top) thermal resistance 10.8
RθJB Junction-to-board thermal resistance 4.4 °C/W
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 4.3
RθJCbot Junction-to-case (bottom) thermal resistance 1.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
EQ = Level 4, VOD = Level 6
Current Consumption, 2.5 V Mode 220 280 mA
RXDET = 1, PWDN = 0
IDD EQ = Level 4, VOD = Level 6
Current Consumption, 3.3 V Mode 220 280 mA
RXDET = 1, PWDN = 0
Power Down Current Consumption PWDN = 1 14 27 mA
VDD Integrated LDO Regulator VIN = 3.0 - 3.6 V 2.375 2.5 2.625 V
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25 High Level Input Voltage 2.5 V Supply Mode 1.7 VDD V
VIH33 High Level Input Voltage 3.3 V Supply Mode 1.7 VIN V
VIL Low Level Input Voltage 0 0.7 V
High Level Output Voltage
VOH IOH =−4mA 2.0 V
(ALL_DONE pin)
Low Level Output Voltage
VOL IOL = 4mA 0.4 V
(ALL_DONE pin) VIN = 3.6 V,
IIH Input High Current (PWDN pin) -15 +15 µA
LVCMOS = 3.6 V
VIN = 3.6 V,
IIL Input Low Current (PWDN pin) -15 +15 µA
LVCMOS = 0 V
4-LEVEL INPUT DC SPECIFICATIONS
Input High Current with internal VIN = 3.6 V,
IIH resistors +20 +150 µA
LVCMOS = 3.6 V
(4–level input pin)
Input Low Current with internal VIN = 3.6 V,
IIL resistors -160 -40 µA
LVCMOS = 0 V
(4–level input pin)
Voltage Threshold from Pin Mode 0.50
Level 0 to R VDD = 2.5 V (2.5 V supply mode)
Voltage Threshold from Pin Mode Internal LDO Disabled 1.25 V
Level R to F See Table 1 for details
Voltage Threshold from Pin Mode 2.00
Level F to 1
VTH Voltage Threshold from Pin Mode 0.66
Level 0 to R VIN = 3.3 V (3.3 V supply mode)
Voltage Threshold from Pin Mode Internal LDO Enabled 1.65 V
Level R to F See Table 1 for details.
Voltage Threshold from Pin Mode 2.64
Level F to 1
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Electrical Characteristics (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CML RECEIVER INPUTS (IN_n+, IN_n-)
ZRx-DIFF-DC Rx DC differential mode impedance Tested at VDD = 2.5 V 80 100 120 Ω
ZRx-DC Rx DC single ended impedance Tested at VDD = 2.5 V 40 50 60 Ω
SDD11 10 MHz -19
RLRx-DIFF Rx Differential Input return loss SDD11 2 GHz -14 dB
SDD11 6-11.1 GHz -8
RLRx-CM Rx Common mode return loss SCC11 0.05 - 5 GHz -10 dB
Signal detect assert level for active SD_TH = F (float),
VRx-ASSERT-DIFF-PP 57 mVp-p
data signal 1010 pattern at 12 Gbps
VRx-DEASSERT-DIFF- Signal detect de-assert for inactive SD_TH = F (float), 44 mVp-p
PP signal level 1010 pattern at 12 Gbps
HIGH SPEED OUTPUTS
SDD22 10 MHz - 2 GHz -15 dB
RLTx-DIFF Tx Differential return loss SDD22 5.5 GHz -12
SDD22 11.1 GHz -10 dB
RLTx-CM Tx Common mode return loss SCC22 50 MHz- 2.5 GHz -8 dB
ZTx-DIFF-DC DC differential Tx impedance 100 Ω
Total current when output is
ITx-SHORT Transmitter short circuit current limit 20 mA
shorted to VDD or GND
VTx-CM-DC-LINE- Absolute delta of DC common mode 25 mV
DELTA voltage between Tx+ and Tx- Differential measurement with
OUT_n+ and OUT_n-,
AC-Coupled and terminated by
50 Ωto GND,
VTx-DIFF1-PP Output Voltage Differential Swing Inputs AC-Coupled, 615 mVp-p
Measured with 8T Pattern at 12
Gbps(1)
VID = 600 mVp-p
VOD = Level 6(2)(3)
Differential measurement with
OUT_n+ and OUT_n-,
AC-Coupled and terminated by
50 Ωto GND,
VTx-DIFF2-PP Output Voltage Differential Swing Inputs AC-Coupled, 950 mVp-p
Measured with 8T Pattern at 12
Gbps(1)
VID = 1000 mVp-p
VOD = Level 6(2)(3)
Differential measurement with
OUT_n+ and OUT_n-,
AC-Coupled and terminated by
50 Ωto GND,
VTx-DIFF3-PP Output Voltage Differential Swing Inputs AC-Coupled, 1100 mVp-p
Measured with 8T Pattern at 12
Gbps(1)
VID = 1200 mVp-p
VOD = Level 6(2)(3)
(1) 8T pattern is defined as a 1111111100000000'b pattern bit sequence.
(2) ATE measurements for production are tested at DC.
(3) In PCIe applications, the output VOD level is not fixed. It adjusts automatically based on the VID input amplitude level. The output VOD
level set by VODA/B[1:0] depends on the VID level and the frequency content. The DS80PCI810 repeater is designed to be transparent
in this mode, so the Tx-FIR (de-emphasis) is passed to the Rx to support the handshake negotiation link training.
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Electrical Characteristics (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPDEQ Differential propagation delay EQ = Level 1 to Level 4 80 ps
EQ = Level 4, VOD = Level 6,
PRBS-7, 8 Gbps
VTx-CM-AC-PP AC common mode voltage Measured over >106bits using a 20 mVp-p
low pass filter with a -3 dB corner
frequency at 4 GHz(4)
VDISABLE-OUT Tx disable output voltage Driver disabled via PWDN 1 mVp-p
Driver enabled, EQ = Level 4,
VTx-IDLE-DIFF-AC-p Tx idle differential peak output voltage 8 mV
VOD = Level 7 (Max)(5)
TTx-IDLE-SET-TO- Time to transition to idle after VID = 1.0 Vp-p, 1.5 Gbps 0.70 ns
IDLE differential signal
TTx-IDLE-TO-DIFF- Time to transition to valid differential VID = 1.0 Vp-p, 1.5 Gbps 0.04 ns
DATA signal after idle Evaluation Module (EVM) Only,
FR4,
VID = 800 mVp-p, EQ = Level 1
RJADD Additive Random Jitter 0.36 ps rms
PRBS15, 12 Gbps
VOD = Level 6
All other channels active(6)
EQUALIZATION
5” Differential Stripline, 5mil trace
width, FR4,
DJE1 Residual deterministic jitter at 6 Gbps VID = 800 mVp-p, 0.06 UIp-p
PRBS15, EQ = Level 2,
VOD = Level 6
5” Differential Stripline, 5mil trace
width, FR4,
Residual deterministic jitter at 12
DJE2 VID = 800 mVp-p, 0.12 UIp-p
Gbps PRBS15, EQ = Level 2,
VOD = Level 6
(4) Tx Common Mode AC noise decreases at lower levels of EQ gain.
(5) Tested with a valid idle signal on the input with peak differential voltage of 6 mV.
(6) Additive random jitter is given in RMS value by the following equation: RJADD =√[(Output Jitter)2- (Input Jitter)2]. Typical input jitter for
these measurements is 150 fs rms.
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6.7 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL Data, Clock Input Low Voltage 0.8 V
VIH Data, Clock Input High Voltage 2.1 3.6 V
VOL Output Low Voltage SDA or SCL, IOL = 1.25 mA 0 0.36 V
VDD Nominal Bus Voltage 2.375 3.6 V
IIH-Pin Input Leakage Per Device Pin +20 +150 µA
IIL-Pin Input Leakage Per Device Pin -160 -40 µA
CICapacitance for SDA and SCL See(1)(2) < 5 pF
External Termination Resistance Pullup VDD = 3.3 V(1)(2)(3) 2000 Ω
RTERM pull to VDD = 2.5 V ± 5% OR 3.3 V Pullup VDD = 2.5 V(1)(2)(3) 1000 Ω
± 10%
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
6.8 Timing Requirements Serial Bus Interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
ENSMB = VDD (Slave Mode) 400 kHz
FSMB Bus Operating Frequency ENSMB = FLOAT (Master Mode) 280 400 520 kHz
Read operation
tFALL SCL or SDA Fall Time 60 ns
RPU = 4.7 kΩ, Cb < 50 pF
Read operation
tRISE SCL or SDA Rise Time 140 ns
RPU = 4.7 kΩ, Cb < 50 pF
tFClock/Data Fall Time See(1) 300 ns
tRClock/Data Rise Time See(1) 1000 ns
Time in which a device must be
tPOR See(1) 500 ms
operational after power-on reset
(1) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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SP
tBUF tHD:STA
tLOW
tR
tHD:DAT
tHIGH
tFtSU:DAT tSU:STA
ST SP
tSU:STO
SCL
SDA
ST
IN
OUT
+
-tIDLE-DATA
+
-
tDATA-IDLE
DATA
IDLE
0V
0V
DATA
IDLE
IN 0V
tPLHD
OUT 0V
tPHLD
0V
20%
80%
20%
80%
tFALL
tRISE
VOD = [Out+ - Out-]
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Figure 1. Output Rise And Fall Transition Time
Figure 2. Propagation Delay Timing Diagram
Figure 3. Transmit Idle-Data and Data-Idle Response Time
Figure 4. SMBus Timing Parameters
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0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40 -15 10 35 60 85
Output Differential Voltage (Vpp)
Temperature (C)
VID = 0.6Vpp
VID = 0.8Vpp
VID = 1.0Vpp
VID = 1.2Vpp
C001
0.2
0.4
0.6
0.8
1
1.2
1.4
0.2 0.4 0.6 0.8 1 1.2 1.4
Output Differential Voltage (Vpp)
Input Differential Voltage (Vpp)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
C005
350
370
390
410
430
450
470
490
510
530
550
570
590
1 2 3 4 5 6
Power Dissipation (mW)
VOD Level
VDD = 2.5 V
C006
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
2.325 2.5 2.675
Output Differential Voltage (Vpp)
VDD (V)
VID = 0.6Vpp
VID = 0.8Vpp
VID = 1.0Vpp
VID = 1.2Vpp
C003
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6.9 Typical Characteristics
Test Conditions
Test Conditions Data Rate, Test Pattern 1.5625 Gbps, 1010 Pattern
EQ Level 4 VOD Level 6
VOD_DB 000'b EQ Level 1
T 25°C T 25°C
Figure 5. Typical Power Dissipation vs. VOD Figure 6. Typical VOD vs. VDD
Test Conditions Test Conditions
Data Rate, Test Pattern 1.5625 Gbps, 1010 Pattern Data Rate, Test Pattern 1.5625 Gbps, 1010 Pattern
VOD Level 6 EQ Level 1
EQ Level 1 T 25°C
VDD 2.5 V VDD 2.5 V
Figure 7. Typical VOD vs. Temperature Figure 8. Typical VOD vs. VID
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INA_n+
INA_n- EQ OUTA_n+
OUTA_n-
One channel of four A Channels
Term
Driver
EQA
EN_SMB
RXDET
VODA[1:0]
Digital Core and SMBus Registers
SCL
SDA
PWDN
VIN
VDD_SEL
AD[3:0]
Internal voltage
regulator
READ_EN ALL_DONE
INB_n+
INB_n- EQ OUTB_n+
OUTB_n-
One channel of four B Channels
Term
Driver
EQB
EN_SMB
RXDET
VODB[1:0]
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7 Detailed Description
7.1 Overview
The DS80PCI810 provides linear equalization for lossy printed circuit board backplanes and balanced cables.
The DS80PCI810 operates in three modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1),
and SMBus Master Mode (ENSMB = Float) to load register information from external EEPROM.
7.2 Functional Block Diagram
7.2.1 Functional Datapath Blocks
In an increasing number of high speed applications, transparency between Tx and Rx endpoints is essential to
ensure high signal integrity. The DS80PCI810 channel datapath uses one gain stage input equalization coupled
with a linear output driver. This combination provides a high level of transparency, thereby achieving greater
drive distance in PCIe applications where Rx-Tx auto-negotiation and link-training are required. Refer to the
Typical Applications section for more application information regarding recommended settings and placement.
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7.3 Feature Description
The 4-level input pins use a resistor divider to set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30 kΩpull-up and a 60 kΩpull-down connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1 kΩpull-down, 20 kΩpull-down, no connect, and 1 kΩpull-up, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
Resulting Pin Voltage
LEVEL SETTING 3.3-V MODE 2.5-V MODE
0 Tie 1 kΩto GND 0.10 V 0.08 V
R Tie 20 kΩto GND 1/3 x VIN 1/3 x VDD
F Float (leave pin open) 2/3 x VIN 2/3 x VDD
1 Tie 1 kΩto VIN or VDD VIN - 0.05 V VDD - 0.04 V
7.3.1 Typical 4-Level Input Thresholds
• Internal Threshold between 0 and R = 0.2 * VIN or VDD
• Internal Threshold between R and F = 0.5 * VIN or VDD
• Internal Threshold between F and 1 = 0.8 * VIN or VDD
In order to minimize the startup current associated with the integrated 2.5 V regulator, the 1 kΩpull-up / pull-
down resistors are recommended. If several 4-level inputs require the same setting, it is possible to combine two
or more 1 kΩresistors into a single lower value resistor. As an example, combining two inputs with a single 500
Ωresistor is a valid way to save board space.
7.4 Device Functional Modes
7.4.1 Pin Control Mode:
When in Pin Mode (ENSMB = 0), equalization and VOD (output amplitude) can be selected via pin control for
both the A-channels and B-channels per Table 4 and Table 5. The RXDET pin provides either automatic or
manual control for input termination (50 Ωor > 50 kΩto VDD). The receiver electrical signal detect status
threshold is adjustable via the SD_TH pin. By setting signal-detect threshold level via the SD_TH pin, status
information about a valid signal detect assert/de-assert can be read back via SMBus registers. Pin control mode
is ideal in situations where neither MCU or EEPROM is available to access the device via SMBus SDA/SCL
lines.
7.4.2 Slave SMBus Mode:
When in Slave SMBus Mode (ENSMB = 1), the VOD (output amplitude), equalization, and termination disable
features are all programmable on an individual channel basis, rather than in collective A-channel and B-channel
groups. Upon assertion of ENSMB, the EQx and VODx settings are controlled by SMBus immediately. It is
important to note that SMBus settings can only be changed from their defaults after asserting Register Enable by
setting Reg 0x06[3] = 1. The EQx and VODx pins are subsequently converted to AD0-AD3 SMBus address
inputs. The other external control pins (RXDET and SD_TH) remain active unless their respective registers are
written to and the appropriate override bit is set. If the user overrides a pin control, the input voltage level of that
control pin is ignored until ENSMB is driven low (Pin Mode). In the event that channels are powered down via the
PWDN pin, the state of all register settings are not affected.
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Device Functional Modes (continued)
Table 2. RX Detect Settings
PWDN(1) RXDET SMBus REG INPUT RECOMMENDED COMMENTS
(Pin 52) (Pin 22) Bit[3:2] TERMINATION USE
0 0 00 Hi-Z Manual Rx-Detect, input is Hi-Z
Auto Rx-Detect, outputs test every 12 ms for 600
ms then stops; termination is Hi-Z until Rx
Pre Detect: Hi-Z
0 R 01 PCIe detection; once detected input termination is 50 Ω
Post Detect: 50 ΩReset function by pulsing PWDN high for 5 µs then
low again
Auto Rx-Detect, outputs test every 12 ms until
F Pre Detect: Hi-Z
0 10 PCIe detection occurs; termination is Hi-Z until Rx
(Default) Post Detect: 50 Ωdetection; once detected input termination is 50 Ω
0 1 11 50 ΩManual Rx-Detect, input is 50 Ω
Power Down mode, input is Hi-Z, output drivers
are disabled
1 X X Hi-Z Used to reset Rx-Detect State Machine when held
high for 5 µs
(1) In SMBus Slave Mode, the Rx Detect State Machine can be manually reset in software by overriding the device PRSNT function. This is
accomplished by setting the Override PRSNT bit (Reg 0x02[7]) and then toggling the PRSNT value bit (Reg 0x02[6]). See Table 9 for
more information about resetting the Rx Detect State Machine.
Table 3. Signal Detect Status Threshold Level(1)(2)
SD_TH SMBus REG BIT[3:2] [3:2] ASSERT LEVEL [1:0] DE-ASSERT LEVEL
LEVEL (PIN 26) and[1:0] (mVp-p) (mVp-p)
3 Gbps 12 Gbps 3 Gbps 12 Gbps
1 0 10 18 75 14 55
2 R 01 12 40 8 22
3 F (default) 00 15 50 11 37
4 1 11 16 58 12 45
(1) VDD = 2.5 V, 25°C, 1010 pattern at 1.5 Gbps and 101010 pattern at 12 Gbps
(2) Signal detect status threshold sets the value at which a signal detect status is flagged via SMBus Reg 0x0A. Regardless of the threshold
level, the output always remains enabled unless manually powered down.
7.4.3 SMBus Master Mode
When in SMBus Master Mode (ENSMB = Float), the VOD (output amplitude), equalization, and termination
disable features for multiple devices can be loaded via external EEPROM. By asserting a Float condition on the
ENSMB pin, an external EEPROM writes register settings to each device in accordance with its SMBus slave
address. The settings programmable by external EEPROM provide only a subset of all the register bits available
via SMBus Slave Mode, and the bit-mapping between SMBus Slave Mode registers and EEPROM addresses
can be referenced in Table 6. Once the EEPROM successfully finishes loading each device's register settings,
the device reverts back to SMBus Slave Mode and releases SDA/SCL control to an external master MCU. If the
EEPROM fails to load settings to a particular device, for example due to an invalid or blank hex file, the device
waits indefinitely in an unknown state where access to the SMBus lines is not possible.
7.4.4 Signal Conditioning Settings
Equalization and VOD settings accessible via the pin controls are chosen to meet the needs of most high speed
applications. These settings can also be controlled via the SMBus registers. Each pin input has a total of four
possible voltage level settings. Table 4 and Table 5 show both the Pin Mode and SMBus Mode settings that are
used in order to program the equalization and VOD gain for each DS80PCI810 channel.
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Table 4. Equalizer Settings(1)(2)
EQUALIZATION BOOST RELATIVE TO DC
EQA(3) dB at dB at dB at
LEVEL EQ – 8 bits[7:0]
EQB 1.5 GHz 2.5 GHz 4 GHz
1 0 xxxx xx00 = 0x00 2.1 2.5 2.7
2 R xxxx xx01 = 0x01 4.0 5.1 6.4
3 F xxxx xx10 = 0x02 5.5 7.0 8.3
4 1 xxxx xx11 = 0x03 6.8 8.3 9.5
(1) Optimal EQ setting should be determined via simulation and prototype verification.
(2) Equalization boost values are inclusive of package loss.
(3) To program EQ Level 1-4 correctly in Pin Mode, RESERVED3 and AD2 pins must be tied via 1 kΩresistor to GND.
Table 5. Output Voltage Settings(1)
VODA1 VODA0 VOD_DB - 3
LEVEL VOD - 3 bits[2:0] VID Vp-p VOD/VID Ratio(1)
VODB1 VODB0 bits[2:0]
-- -- -- 000'b 000'b 1.2 0.57(2)
1 0 0 001'b 000'b 1.2 0.65
2 0 R 010'b 000'b 1.2 0.71
3 0 1 011'b 000'b 1.2 0.77
4 R F 100'b 000'b 1.2 0.83
5 F R 101'b 000'b 1.2 0.90
6 1 0 110'b 000'b 1.2 1.00
-- -- -- 111'b 000'b 1.2 1.04(2)(3)
(1) For PCIe operation, it is important to keep the output amplitude and dynamic range as large as possible. When operating in Pin Mode, it
is recommended to use VODA[1:0] = VODB[1:0] = Level 6. In SMBus Mode, it is also recommended to use Level 6 (that is, VOD =
110'b and VOD_DB = 000'b).
(2) These VOD settings are only accessible via SMBus Modes.
(3) VOD = 111'b setting in SMBus Mode is not recommended.
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7.5 Programming
The DS80PCI810 device supports reading directly from an external EEPROM device by implementing SMBus
Master Mode. When using SMBus Master Mode, the DS80PCI810 reads directly from specific location in the
external EEPROM. When designing a system for using the external EEPROM, the user must follow these
specific guidelines.
• Maximum EEPROM size is 8K (1024 x 8-bit).
• Set ENSMB = Float — enable the SMBus Master Mode.
• The external EEPROM device address byte must be 0xA0 and capable of 1 MHz operation at 2.5 V and 3.3
V supply.
• Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
When tying multiple DS80PCI810 devices to the SDA and SCL bus, use these guidelines to configure the
devices:
• Use SMBus AD[3:0] address bits so that each device can load its configuration from the EEPROM. Example
below is for four devices. The first device in the sequence is conventionally address 0xB0, while subsequent
devices follow the address order listed below.
– U1: AD[3:0] = 0000 = 0xB0,
– U2: AD[3:0] = 0001 = 0xB2,
– U3: AD[3:0] = 0010 = 0xB4,
– U4: AD[3:0] = 0011 = 0xB6
• Use a pull-up resistor on SDA and SCL; value = 2 kΩto 5 kΩ
• Daisy-chain READ_EN (Pin 26) and ALL_DONE (Pin 27) from one device to the next device in the sequence
so that they do not compete for the EEPROM at the same time.
1. Tie READ_EN of the first device in the chain (U1) to GND.
2. Tie ALL_DONE of U1 to READ_EN of U2.
3. Tie ALL_DONE of U2 to READ_EN of U3.
4. Tie ALL_DONE of U3 to READ_EN of U4.
5. Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully.
Once the ALL_DONE status pin of the last device is flagged to indicate that all devices sharing the SMBus line
have been successfully programmed, control of the SMBus line is released by the repeater and the device
reverts back to SMBus Slave Mode. At this point, an external MCU can perform any additional Read or Write
operations.
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS80PCI810 device. The first three
bytes of the EEPROM always contain a base header common and necessary to control initialization of all
devices connected to the I2C bus. The CRC enable flag is used to enable or disable CRC checking. If CRC
checking is disabled, the CRC byte in each device's address map header is ignored to simplify control. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start address in the
EEPROM. If the MAP bit is not present, the configuration data start address is assumed to follow the base
header directly. Lastly, one bit in the base header is used to indicate whether EEPROM size > 256 bytes. This bit
ensures that EEPROM slot addresses are formatted properly as one byte (EEPROM ≤256 bytes) or two bytes
(EEPROM > 256 bytes) for subsequent address map headers. There are 37 bytes of data for each DS80PCI810
device.
:2000000000001000000407002FAD4002FAD4002FAD4002FAD409805F5A8005F5A8005F5AD0
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
Note: The maximum EEPROM size supported is 8 kbits (1024 x 8 bits).
7.5.1 EEPROM Address Map for Single Device
A detailed EEPROM Address Map for a single device is shown in Table 6. For instances where multiple devices
are written to EEPROM, the device starting address definitions align starting with Table 6 Address 0x03.
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Table 6. EEPROM Address Map - Single Device With Default Value
EEPROM Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address Map EEPROM > 256 DEVICE DEVICE DEVICE DEVICE
Description CRC_EN Reserved
Present Bytes COUNT[3] COUNT[2] COUNT[1] COUNT[0]
0x00
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0x01
Default 0x00 0 0 0 0 0 0 0 0
Value
Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM Max EEPROM
Description Burst size[7] Burst size[6] Burst size[5] Burst size[4] Burst size[3] Burst size[2] Burst size[1] Burst size[0]
0x02
Default 0x00 0 0 0 0 0 0 0 0
Value
Description PWDN_CH7 PWDN_CH6 PWDN_CH5 PWDN_CH4 PWDN_CH3 PWDN_CH2 PWDN_CH1 PWDN_CH0
SMBus Register 0x01[7] 0x01[6] 0x01[5] 0x01[4] 0x01[3] 0x01[2] 0x01[1] 0x01[0]
0x03
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Ovrd_PWDN Reserved Reserved Reserved
SMBus Register 0x02[5] 0x02[4] 0x02[3] 0x02[2] 0x02[0] 0x04[7] 0x04[6] 0x04[5]
0x04
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved Ovrd_SD_TH Reserved
SMBus Register 0x04[4] 0x04[3] 0x04[2] 0x04[1] 0x04[0] 0x06[4] 0x08[6] 0x08[5]
0x05
Default 0x04 0 0 0 0 0 1 0 0
Value
Description Reserved Ovrd_RXDET Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x08[4] 0x08[3] 0x08[2] 0x08[1] 0x08[0] 0x0B[6] 0x0B[5] 0x0B[4]
0x06
Default 0x07 0 0 0 0 0 1 1 1
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved CH0_RXDET_1 CH0_RXDET_0
SMBus Register 0x0B[3] 0x0B[2] 0x0B[1] 0x0B[0] 0x0E[5] 0x0E[4] 0x0E[3] 0x0E[2]
0x07
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved CH0_EQ_1 CH0_EQ_0
SMBus Register 0x0F[7] 0x0F[6] 0x0F[5] 0x0F[4] 0x0F[3] 0x0F[2] 0x0F[1] 0x0F[0]
0x08
Default 0x2F 0 0 1 0 1 1 1 1
Value
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Table 6. EEPROM Address Map - Single Device With Default Value (continued)
EEPROM Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Description CH0_SCP Reserved Reserved Reserved Reserved CH0_VOD_2 CH0_VOD_1 CH0_VOD_0
SMBus Register 0x10[7] 0x10[6] 0x10[5] 0x10[4] 0x10[3] 0x10[2] 0x10[1] 0x10[0]
0x09
Default 0xAD 1 0 1 0 1 1 0 1
Value
Description CH0_VOD_DB_2 CH0_VOD_DB_1 CH0_VOD_DB_0 Reserved CH0_THa_1 CH0_THa_0 CH0_THd_1 CH0_THd_0
SMBus Register 0x11[2] 0x11[1] 0x11[0] 0x12[7] 0x12[3] 0x12[2] 0x12[1] 0x12[0]
0x0A
Default 0x40 0 1 0 0 0 0 0 0
Value
Description Reserved Reserved CH1_RXDET_1 CH1_RXDET_0 Reserved Reserved Reserved Reserved
SMBus Register 0x15[5] 0x15[4] 0x15[3] 0x15[2] 0x16[7] 0x16[6] 0x16[5] 0x16[4]
0x0B
Default 0x02 0 0 0 0 0 0 1 0
Value
Description Reserved Reserved CH1_EQ_1 CH1_EQ_0 CH1_SCP Reserved Reserved Reserved
SMBus Register 0x16[3] 0x16[2] 0x16[1] 0x16[0] 0x17[7] 0x17[6] 0x17[5] 0x17[4]
0x0C
Default 0xFA 1 1 1 1 1 0 1 0
Value
Description Reserved CH1_VOD_2 CH1_VOD_1 CH1_VOD_0 CH1_VOD_DB_2 CH1_VOD_DB_1 CH1_VOD_DB_0 Reserved
SMBus Register 0x17[3] 0x17[2] 0x17[1] 0x17[0] 0x18[2] 0x18[1] 0x18[0] 0x19[7]
0x0D
Default 0xD4 1 1 0 1 0 1 0 0
Value
Description CH1_THa_1 CH1_THa_0 CH1_THd_1 CH1_THd_0 Reserved Reserved CH2_RXDET_1 CH2_RXDET_0
SMBus Register 0x19[3] 0x19[2] 0x19[1] 0x19[0] 0x1C[5] 0x1C[4] 0x1C[3] 0x1C[2]
0x0E
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved CH2_EQ_1 CH2_EQ_0
SMBus Register 0x1D[7] 0x1D[6] 0x1D[5] 0x1D[4] 0x1D[3] 0x1D[2] 0x1D[1] 0x1D[0]
0x0F
Default 0x2F 0 0 1 0 1 1 1 1
Value
Description CH2_SCP Reserved Reserved Reserved Reserved CH2_VOD_2 CH2_VOD_1 CH2_VOD_0
SMBus Register 0x1E[7] 0x1E[6] 0x1E[5] 0x1E[4] 0x1E[3] 0x1E[2] 0x1E[1] 0x1E[0]
0x10
Default 0xAD 1 0 1 0 1 1 0 1
Value
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Table 6. EEPROM Address Map - Single Device With Default Value (continued)
EEPROM Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Description CH2_VOD_DB_2 CH2_VOD_DB_1 CH2_VOD_DB_0 Reserved CH2_THa_1 CH2_THa_0 CH2_THd_1 CH2_THd_0
SMBus Register 0x1F[2] 0x1F[1] 0x1F[0] 0x20[7] 0x20[3] 0x20[2] 0x20[1] 0x20[0]
0x11
Default 0x40 0 1 0 0 0 0 0 0
Value
Description Reserved Reserved CH3_RXDET_1 CH3_RXDET_0 Reserved Reserved Reserved Reserved
SMBus Register 0x23[5] 0x23[4] 0x23[3] 0x23[2] 0x24[7] 0x24[6] 0x24[5] 0x24[4]
0x12
Default 0x02 0 0 0 0 0 0 1 0
Value
Description Reserved Reserved CH3_EQ_1 CH3_EQ_0 CH3_SCP Reserved Reserved Reserved
SMBus Register 0x24[3] 0x24[2] 0x24[1] 0x24[0] 0x25[7] 0x25[6] 0x25[5] 0x25[4]
0x13
Default 0xFA 1 1 1 1 1 0 1 0
Value
Description Reserved CH3_VOD_2 CH3_VOD_1 CH3_VOD_0 CH3_VOD_DB_2 CH3_VOD_DB_1 CH3_VOD_DB_0 Reserved
SMBus Register 0x25[3] 0x25[2] 0x25[1] 0x25[0] 0x26[2] 0x26[1] 0x26[0] 0x27[7]
0x14
Default 0xD4 1 1 0 1 0 1 0 0
Value
Description CH3_THa_1 CH3_THa_0 CH3_THd_1 CH3_THd_0 Reserved hi_idle_SD CH0-3 hi_idle_SD CH4-7 fast_SD CH0-3
SMBus Register 0x27[3] 0x27[2] 0x27[1] 0x27[0] 0x28[6] 0x28[5] 0x28[4] 0x28[3]
0x15
Default 0x09 0 0 0 0 1 0 0 1
Value
Description fast_SD CH4-7 lo_gain_SD CH0-3 lo_gain_SD CH4-7 Reserved Reserved CH4_RXDET_1 CH4_RXDET_0 Reserved
SMBus Register 0x28[2] 0x28[1] 0x28[0] 0x2B[5] 0x2B[4] 0x2B[3] 0x2B[2] 0x2C[7]
0x16
Default 0x80 1 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved CH4_EQ_1 CH4_EQ_0 CH4_SCP
SMBus Register 0x2C[6] 0x2C[5] 0x2C[4] 0x2C[3] 0x2C[2] 0x2C[1] 0x2C[0] 0x2D[7]
0x17
Default 0x5F 0 1 0 1 1 1 1 1
Value
Description Reserved Reserved Reserved Reserved CH4_VOD_2 CH4_VOD_1 CH4_VOD_0 CH4_VOD_DB_2
SMBus Register 0x2D[6] 0x2D[5] 0x2D[4] 0x2D[3] 0x2D[2] 0x2D[1] 0x2D[0] 0x2E[2]
0x18
Default 0x5A 0 1 0 1 1 0 1 0
Value
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Table 6. EEPROM Address Map - Single Device With Default Value (continued)
EEPROM Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Description CH4_VOD_DB_1 CH4_VOD_DB_0 Reserved CH4_THa_1 CH4_THa_0 CH4_THd_1 CH4_THd_0 Reserved
SMBus Register 0x2E[1] 0x2E[0] 0x2F[7] 0x2F[3] 0x2F[2] 0x2F[1] 0x2F[0] 0x32[5]
0x19
Default 0x80 1 0 0 0 0 0 0 0
Value
Description Reserved CH5_RXDET_1 CH5_RXDET_0 Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x32[4] 0x32[3] 0x32[2] 0x33[7] 0x33[6] 0x33[5] 0x33[4] 0x33[3]
0x1A
Default 0x05 0 0 0 0 0 1 0 1
Value
Description Reserved CH5_EQ_1 CH5_EQ_0 CH5_SCP Reserved Reserved Reserved Reserved
SMBus Register 0x33[2] 0x33[1] 0x33[0] 0x34[7] 0x34[6] 0x34[5] 0x34[4] 0x34[3]
0x1B
Default 0xF5 1 1 1 1 0 1 0 1
Value
Description CH5_VOD_2 CH5_VOD_1 CH5_VOD_0 CH5_VOD_DB_2 CH5_VOD_DB_1 CH5_VOD_DB_0 Reserved CH5_THa_1
SMBus Register 0x34[2] 0x34[1] 0x34[0] 0x35[2] 0x35[1] 0x35[0] 0x36[7] 0x36[3]
0x1C
Default 0xA8 1 0 1 0 1 0 0 0
Value
Description CH5_THa_0 CH5_THd_1 CH5_THd_0 Reserved Reserved CH6_RXDET_1 CH6_RXDET_0 Reserved
SMBus Register 0x36[2] 0x36[1] 0x36[0] 0x39[5] 0x39[4] 0x39[3] 0x39[2] 0x3A[7]
0x1D
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved CH6_EQ_1 CH6_EQ_0 CH6_SCP
SMBus Register 0x3A[6] 0x3A[5] 0x3A[4] 0x3A[3] 0x3A[2] 0x3A[1] 0x3A[0] 0x3B[7]
0x1E
Default 0x5F 0 1 0 1 1 1 1 1
Value
Description Reserved Reserved Reserved Reserved CH6_VOD_2 CH6_VOD_1 CH6_VOD_0 CH6_VOD_DB_2
SMBus Register 0x3B[6] 0x3B[5] 0x3B[4] 0x3B[3] 0x3B[2] 0x3B[1] 0x3B[0] 0x3C[2]
0x1F
Default 0x5A 0 1 0 1 1 0 1 0
Value
Description CH6_VOD_DB_1 CH6_VOD_DB_0 Reserved CH6_THa_1 CH6_THa_0 CH6_THd_1 CH6_THd_0 Reserved
SMBus Register 0x3C[1] 0x3C[0] 0x3D[7] 0x3D[3] 0x3D[2] 0x3D[1] 0x3D[0] 0x40[5]
0x20
Default 0x80 1 0 0 0 0 0 0 0
Value
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Table 6. EEPROM Address Map - Single Device With Default Value (continued)
EEPROM Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Description Reserved CH7_RXDET_1 CH7_RXDET_0 Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x40[4] 0x40[3] 0x40[2] 0x41[7] 0x41[6] 0x41[5] 0x41[4] 0x41[3]
0x21
Default 0x05 0 0 0 0 0 1 0 1
Value
Description Reserved CH7_EQ_1 CH7_EQ_0 CH7_SCP Reserved Reserved Reserved Reserved
SMBus Register 0x41[2] 0x41[1] 0x41[0] 0x42[7] 0x42[6] 0x42[5] 0x42[4] 0x42[3]
0x22
Default 0xF5 1 1 1 1 0 1 0 1
Value
Description CH7_VOD_2 CH7_VOD_1 CH7_VOD_0 CH7_VOD_DB_2 CH7_VOD_DB_1 CH7_VOD_DB_0 Reserved CH7_THa_1
SMBus Register 0x42[2] 0x42[1] 0x42[0] 0x43[2] 0x43[1] 0x43[0] 0x44[7] 0x44[3]
0x23
Default 0xA8 1 0 1 0 1 0 0 0
Value
Description CH7_THa_0 CH7_THd_1 CH7_THd_0 Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x44[2] 0x44[1] 0x44[0] 0x47[3] 0x47[2] 0x47[1] 0x47[0] 0x48[7]
0x24
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x48[6] 0x4C[7] 0x4C[6] 0x4C[5] 0x4C[4] 0x4C[3] 0x4C[0] 0x59[0]
0x25
Default 0x00 0 0 0 0 0 0 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x5A[7] 0x5A[6] 0x5A[5] 0x5A[4] 0x5A[3] 0x5A[2] 0x5A[1] 0x5A[0]
0x26
Default 0x54 0 1 0 1 0 1 0 0
Value
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x5B[7] 0x5B[6] 0x5B[5] 0x5B[4] 0x5B[3] 0x5B[2] 0x5B[1] 0x5B[0]
0x27
Default 0x54 0 1 0 1 0 1 0 0
Value
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Table 7. Example Of EEPROM For Four Devices Using Two Address Maps
EEPROM Address (Hex) EEPROM Data Comments
Address
0 00 0x43 CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3
1 01 0x00
2 02 0x10 EEPROM Burst Size
3 03 0x00 CRC not used
4 04 0x0B Device 0 Address Location
5 05 0x00 CRC not used
6 06 0x0B Device 1 Address Location
7 07 0x00 CRC not used
8 08 0x30 Device 2 Address Location
9 09 0x00 CRC not used
10 0A 0x30 Device 3 Address Location
11 0B 0x00 Begin Device 0, 1 - Address Offset 3
12 0C 0x00
13 0D 0x04
14 0E 0x07
15 0F 0x00
16 10 0x01 EQ CHB0 = 0x01
17 11 0xAD VOD CHB0 = 101'b
18 12 0x00 VOD_DB CHB0 = 000'b
19 13 0x00
20 14 0x1A EQ CHB1 = 0x01
21 15 0xD0 VOD CHB1 = 101'b, VOD_DB CHB1 = 000'b
22 16 0x00
23 17 0x01 EQ CHB2 = 0x01
24 18 0xAD VOD CHB2 = 101'b
25 19 0x00 VOD_DB CHB2 = 000'b
26 1A 0x00
27 1B 0x1A EQ CHB3 = 0x01
28 1C 0xD0 VOD CHB3 = 101'b, VOD_DB CHB3 = 000'b
29 1D 0x09 Signal Detect Status Threshold Control
30 1E 0x80 Signal Detect Status Threshold Control
31 1F 0x07 EQ CHA0 = 0x03
32 20 0x5C VOD CHA0 = 110'b
33 21 0x00 VOD_DB CHA0 = 000'b
34 22 0x00
35 23 0x15 EQ CHA1 = 0x00
36 24 0xC0 VOD CHA1 = 110'b, VOD_DB CHA1 = 000'b
37 25 0x00
38 26 0x07 EQ CHA2 = 0x03
39 27 0x5C VOD CHA2 = 110'b
40 28 0x00 VOD_DB CHA2 = 000'b
41 29 0x00
42 2A 0x75 EQ CHA3 = 0x00
43 2B 0xC0 VOD CHA3 = 110'b, VOD_DB CHA3 = 000'b
44 2C 0x00
45 2D 0x00
46 2E 0x54
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Table 7. Example Of EEPROM For Four Devices Using Two Address Maps (continued)
EEPROM Address (Hex) EEPROM Data Comments
Address
47 2F 0x54 End Device 0, 1 - Address Offset 39
48 30 0x00 Begin Device 2, 3 - Address Offset 3
49 31 0x00
50 32 0x04
51 33 0x07
52 34 0x00
53 35 0x01 EQ CHB0 = 0x01
54 36 0xAB VOD CHB0 = 011'b
55 37 0x00 VOD_DB CHB0 = 000'b
56 38 0x00
57 39 0x1A EQ CHB1 = 0x01
58 3A 0xB0 VOD CHB1 = 011'b, VOD_DB CHB1 = 000'b
59 3B 0x00
60 3C 0x01 EQ CHB2 = 0x01
61 3D 0xAB VOD CHB2 = 011'b
62 3E 0x00 VOD_DB CHB2 = 000'b
63 3F 0x00
64 40 0x1A EQ CHB3 = 0x01
65 41 0xB0 VOD CHB3 = 011'b, VOD_DB CHB3 = 000'b
66 42 0x09 Signal Detect Status Threshold Control
67 43 0x80 Signal Detect Status Threshold Control
68 44 0x07 EQ CHA0 = 0x03
69 45 0x5C VOD CHA0 = 110'b
70 46 0x00 VOD_DB CHA0 = 000'b
71 47 0x00
72 48 0x15 EQ CHA1 = 0x00
73 49 0xA0 VOD CHA1 = 101'b, VOD_DB CHA1 = 000'b
74 4A 0x00
75 4B 0x07 EQ CHA2 = 0x03
76 4C 0x5C VOD CHA2 = 110'b
77 4D 0x00 VOD_DB CHA2 = 000'b
78 4E 0x00
79 4F 0x15 EQ CHA3 = 0x00
80 50 0xA0 VOD CHA3 = 101'b, VOD_DB CHA3 = 000'b
81 51 0x00
82 52 0x00
83 53 0x54
84 54 0x54 End Device 2, 3 - Address Offset 39
Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. Multiple devices can point to the
same address map. Maximum EEPROM size is 8 kbits (1024 x 8-bits).
7.5.2 SMBus
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. Tie ENSMB = 1
kΩto VDD (2.5 V mode) or VIN (3.3 V mode) to enable SMBus Slave Mode and allow access to the
configuration registers.
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The DS80PCI810 uses AD[3:0] inputs in both SMBus Modes. These AD[3:0] pins are the user set SMBus slave
address inputs and have internal pull-downs. Based on the SMBus 2.0 specification, the DS80PCI810 has a 7-bit
slave address. The LSB is set to 0'b (for a WRITE). When AD[3:0] pins are left floating or pulled low, AD[3:0] =
0000'b, and the device default address byte is 0xB0. The device supports up to 16 address bytes, as shown in
Table 8:
Table 8. Device Slave Address Bytes
Full Slave Address Byte 7-Bit Slave Address
AD[3:0] Settings (7-Bit Address + Write Bit) (Hex)
0000 B0 58
0001 B2 59
0010 B4 5A
0011 B6 5B
0100 B8 5C
0101 BA 5D
0110 BC 5E
0111 BE 5F
1000 C0 60
1001 C2 61
1010 C4 62
1011 C6 63
1100 C8 64
1101 CA 65
1110 CC 66
1111 CE 67
The SDA/SCL pins are 3.3 V tolerant, but are not 5 V tolerant. An external pull-up resistor is required on the SDA
and SCL line. The resistor value can be from 2 kΩto 5 kΩdepending on the voltage, loading, and speed.
7.5.3 Transfer Of Data Via The SMBus
During normal operation, the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH, then the bus transfers to the IDLE state.
7.5.4 SMBus Transactions
The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read
Only), default value, and function information.
7.6 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
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Writing a Register (continued)
The WRITE transaction is completed, the bus goes IDLE, and communication with other SMBus devices may
now occur.
7.7 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE, and communication with other SMBus devices may now
occur.
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7.8 Register Maps
Table 9. SMBus Slave Mode Register Map
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7 Reserved R/W Set bit to 0
Observation of AD[3:0] bits
[6]: AD3
Address Bit
6:3 R [5]: AD2
AD[3:0] [4]: AD1
0x00 Observation 0x00 [3]: AD0
EEPROM
2 R 1 = Device completed the read from external EEPROM
Read Done
1 Reserved R/W Set bit to 0
0 Reserved R/W Set bit to 0
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
PWDN
0x01 7:0 PWDN CHx R/W 0x00 Yes [2]: CH2 – CHB_2
Channels [1]: CH1 – CHB_1
[0]: CH0 – CHB_0
0x00 = all channels enabled
0xFF = all channels disabled
Note: Override PWDN pin and enable register control
via Reg 0x02[0]
Override
7 1 = Override Automatic Rx Detect State Machine Reset
PRSNT 1 = Set Rx Detect State Machine Reset
6 PRSNT Value 0 = Clear Rx Detect State Machine Reset
Override
0x02 R/W 0x00
PWDN, PRSNT 5:2 Reserved Yes Set bits to 0
1 Reserved Set bit to 0
Override 1 = Block PWDN pin control (Register control enabled)
0 Yes
PWDN 0 = Allow PWDN pin control (Register control disabled)
0x03 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x04 Reserved 7:0 Reserved R/W 0x00 Yes Set bits to 0
0x05 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
7:5 Reserved Set bits to 0
4 Reserved Yes Set bit to 1
1 = Enable SMBus Slave Mode Register Control
Slave Register
0x06 R/W 0x10
Register Note: In order to change VOD, VOD_DB, and EQ of
Control 3Enable the channels in slave mode, this bit must be set to
1.
2:0 Reserved Set bits to 0
7 Reserved Set bit to 0
Reset 1 = Self clearing reset for SMBus registers (register
6Registers settings return to default values)
Digital Reset
0x07 R/W 0x01
and Control Reset SMBus
5 1 = Self clearing reset to SMBus master state machine
Master
4:0 Reserved Set bits to 0 0001'b
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7 Reserved Set bit to 0
Override 1 = Block SD_TH pin control (Register control enabled)
6 Yes
SD_TH 0 = Allow SD_TH pin control (Register control disabled)
Override
0x08 5:4 Reserved R/W 0x00 Yes Set bits to 0
Pin Control Override 1 = Block RXDET pin control (Register control enabled)
3 Yes
RXDET 0 = Allow RXDET pin control (Register control disabled)
2:0 Reserved Yes Set bits to 0
0x09 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
CH7 - CH0 Internal Signal Detect Indicator
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
Signal Detect
0x0A 7:0 SD_TH Status R 0x00 [2]: CH2 – CHB_2
Monitor [1]: CH1 – CHB_1
[0]: CH0 – CHB_0
0 = Signal detected at input
1 = Signal not detected at input
Note: These bits only function when RESERVED2 pin =
FLOAT
7 Reserved R/W 0x00 Set bit to 0
0x0B Reserved 6:0 Reserved R/W 0x70 Yes Set bits to 111 0000'b
0x0C- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x0D 7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH0 - CHB_0
0x0E R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH0 - CHB_0 INB_0 EQ Control - total of four levels.
0x0F 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTB_0 VOD Control: VOD / VID Ratio
000'b = 0.57
CH0 - CHB_0 001'b = 0.65
0x10 R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
Observation bit for RXDET CH0 - CHB_0
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTB_0 VOD_DB Control
000'b = 0 dB (recommended)
CH0 - CHB_0 001'b = –1.5 dB
0x11 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH0 - CHB_0 Note: Override SD_TH pin and enable register control
0x12 R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x13- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x14 7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH1 - CHB_1
0x15 R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH1 - CHB_1 INB_1 EQ Control - total of four levels.
0x16 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTB_1 VOD Control: VOD / VID Ratio
000'b = 0.57
CH1 - CHB_1 001'b = 0.65
0x17 R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
Observation bit for RXDET CH1 - CHB_1
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTB_1 VOD_DB Control
000'b = 0 dB (recommended)
CH1 - CHB_1 001'b = –1.5 dB
0x18 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH1 - CHB_1 Note: Override SD_TH pin and enable register control
0x19 R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x1A- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x1B
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH2 - CHB_2
0x1C R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH2 - CHB_2 INB_2 EQ Control - total of four levels.
0x1D 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTB_2 VOD Control: VOD / VID Ratio
000'b = 0.57
CH2 - CHB_2 001'b = 0.65
0x1E R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
Observation bit for RXDET CH2 - CHB_2
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTB_2 VOD_DB Control
000'b = 0 dB (recommended)
CH2 - CHB_2 001'b = –1.5 dB
0x1F 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH2 - CHB_2 Note: Override SD_TH pin and enable register control
0x20 R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x21- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x22 7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH3 - CHB_3
0x23 R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH3 - CHB_3 INB_3 EQ Control - total of four levels.
0x24 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTB_3 VOD Control: VOD / VID Ratio
000'b = 0.57
CH3 - CHB_3 001'b = 0.65
0x25 R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
Observation bit for RXDET CH3 - CHB_3
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTB_3 VOD_DB Control
000'b = 0 dB (recommended)
CH3 - CHB_3 001'b = –1.5 dB
0x26 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH3 - CHB_3 Note: Override SD_TH pin and enable register control
0x27 R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
7 Reserved Set bit to 0
6 Reserved Yes Set bit to 1
Enable Higher Range of Signal Detect Status
High SD_TH Thresholds
5:4 Yes
Status [5]: CH0 - CH3
[4]: CH4 - CH7
Signal Detect Enable Fast Signal Detect Status
0x28 R/W 0x4C
Status Control [3]: CH0 - CH3
Fast Signal
3:2 Yes [2]: CH4 - CH7
Detect Status Note: In Fast Signal Detect, assert/de-assert response
occurs after approximately 3-4 ns
Enable Reduced Signal Detect Status Gain
Reduced SD
1:0 Yes [1]: CH0 - CH3
Status Gain [0]: CH4 - CH7
0x29- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x2A
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH4 - CHA_0
0x2B R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH4 - CHA_0 INA_0 EQ Control - total of four levels.
0x2C 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTA_0 VOD Control: VOD / VID Ratio
000'b = 0.57
CH4 - CHA_0 001'b = 0.65
0x2D R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
Observation bit for RXDET CH4 - CHA_0
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTA_0 VOD_DB Control
000'b = 0 dB (recommended)
CH4 - CHA_0 001'b = –1.5 dB
0x2E 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH4 - CHA_0 Note: Override SD_TH pin and enable register control
0x2F R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x30- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x31 7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH5 - CHA_1
0x32 R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH5 - CHA_1 INA_1 EQ Control - total of four levels.
0x33 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTA_1 VOD Control: VOD / VID Ratio
000'b = 0.57
CH5 - CHA_1 001'b = 0.65
0x34 R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
Observation bit for RXDET CH5 - CHA1
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTA_1 VOD_DB Control
000'b = 0 dB (recommended)
CH5 - CHA_1 001'b = –1.5 dB
0x35 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH5 - CHA_1 Note: Override SD_TH pin and enable register control
0x36 R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x37- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x38 7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH6 - CHA_2
0x39 R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH6 - CHA_2 INA_2 EQ Control - total of four levels.
0x3A 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTA_2 VOD Control: VOD / VID Ratio
000'b = 0.57
CH6 - CHA_2 001'b = 0.65
0x3B R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
Observation bit for RXDET CH6 - CHA_2
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTA_2 VOD_DB Control
000'b = 0 dB (recommended)
CH6 - CHA_2 001'b = –1.5 dB
0x3C 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH6 - CHA_2 Note: Override SD_TH pin and enable register control
0x3D R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x3E- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x3F
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7:6 Reserved Set bits to 0
5:4 Reserved Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
CH7 - CHA_3
0x40 R/W 0x00 10'b = Auto Rx-Detect,
RXDET 3:2 RXDET Yes outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
1:0 Reserved Set bits to 0
CH7 - CHA_3 INA_3 EQ Control - total of four levels.
0x41 7:0 EQ Control R/W 0x2F Yes
EQ See Table 4.
Short Circuit 1 = Enable the short circuit protection
7 Yes
Protection 0 = Disable the short circuit protection
6:3 Reserved Yes Set bits to 0101'b
OUTA_3 VOD Control: VOD / VID Ratio
000'b = 0.57
CH7 - CHA_3 001'b = 0.65
0x42 R/W 0xAD
VOD 010'b = 0.71
2:0 VOD Control Yes 011'b = 0.77
100'b = 0.83
101'b = 0.90 (default)
110'b = 1.00 (recommended)
111'b = 1.04
Observation bit for RXDET CH7 - CHA_3
7 RXDET Status 1 = Input 50 Ωterminated to VDD
R0 = Input is Hi-Z
6:5 Reserved Set bits to 0
4:3 Reserved Set bits to 0
OUTA_3 VOD_DB Control
000'b = 0 dB (recommended)
CH7 - CHA_3 001'b = –1.5 dB
0x43 0x02
VOD_DB 010'b = –3.5 dB (default)
011'b = –5 dB
R/W
VOD_DB 100'b = –6 dB
2:0 Yes
Control 101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
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Register Maps (continued)
Table 9. SMBus Slave Mode Register Map (continued)
Register EEPROM
Address Bit Field Type Default Description
Name Reg Bit
7 Reserved Yes Set bit to 0
6:4 Reserved Set bits to 0
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
Signal Detect 01'b = 40 mVp-p
3:2 Status Assert Yes 10'b = 75 mVp-p
Threshold 11'b = 58 mVp-p
CH7 - CHA_3 Note: Override SD_TH pin and enable register control
0x44 R/W 0x00
SD_TH via Reg 0x08[6]
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
Signal Detect 01'b = 22 mVp-p
Status
1:0 Yes 10'b = 55 mVp-p
De-assert 11'b = 45 mVp-p
Threshold Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
0x45 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x46 Reserved 7:0 Reserved R/W 0x38 Set bits to 0x38
7:4 Reserved Set bits to 0
0x47 Reserved R/W 0x00
3:0 Reserved Yes Set bits to 0
7:6 Reserved R/W Yes Set bits to 0
0x48 Reserved 0x05
5:0 Reserved R/W Set bits to 00 0101'b
0x49- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4B 7:3 Reserved R/W Yes Set bits to 0
0x4C Reserved 2:1 Reserved R/W 0x00 Set bits to 0
0 Reserved R/W Yes Set bits to 0
0x4D- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x50 7:5 VERSION 100'b
0x51 Device ID R 0x85
4:0 ID 0 0101'b
0x52- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x55
0x56 Reserved 7:0 Reserved R/W 0x10 Set bits to 0x10
0x57 Reserved 7:0 Reserved R/W 0x64 Set bits to 0x64
0x58 Reserved 7:0 Reserved R/W 0x21 Set bits to 0x21
7:1 Reserved Set bits to 0
0x59 Reserved R/W 0x00
0 Reserved Yes Set bit to 0
0x5A Reserved 7:0 Reserved R/W 0x54 Yes Set bits to 0x54
0x5B Reserved 7:0 Reserved R/W 0x54 Yes Set bits to 0x54
0x5C- Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x61
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 DS80PCI810 versus DS80PCI800
The DS80PCI810 and DS80PCI800 are pin compatible, and both can be used for PCIe Gen-1, 2, and 3
applications. The DS80PCI810 features several design enhancements to improve PCIe system interoperability
and performance over the previous generation DS80PCI800 design. The DS80PCI810 has a more linear input
equalizer and output driver to enhance signal transparency for protocols requiring link training. This transparency
is important, because it preserves subtle pre-cursor and post-cursor information from the Tx signal prior to the
repeater. As a result of these enhancements, the DS80PCI810 is easier to tune and increases flexibility of IC
placement along the signal path. The DS80PCI810 is ideal for open PCIe systems. An open system is defined as
an environment where a PCIe connector accepts any compliant PCIe Add-In Card (AIC). The DS80PCI810 can
extend the reach of a PCIe system by up to 10 dB beyond the max allowable PCIe channel loss.
The DS80PCI800 may still be used for closed PCIe systems where significant insertion losses (> 35 dB at 4
GHz) are expected in the signal path. In contrast to open PCIe systems, a closed system is defined as a PCIe
environment with a limited number of possible Host-to-Endpoint combinations. Due to larger CTLE gain, the
DS80PCI800 is able to compensate insertion loss over longer transmission lines before the repeater. In addition,
the DS80PCI800 is able to produce de-emphasis levels up to -12 dB to support significant trace losses after the
repeater (-15 dB at 4 GHz).
8.1.2 Signal Integrity in PCIe Applications
In PCIe Gen-3 applications, specifications require Rx-Tx link training to establish and optimize signal conditioning
settings at 8 Gbps. In link training, the Rx partner requests a series of FIR coefficients from the Tx partner at
speed. This training sequence is designed to pre-condition the signal path with an optimized link between the
endpoints. Note that there is no link training with Tx FIR coefficients for PCIe Gen-1 (2.5 Gbps) or PCIe Gen-2
(5.0 Gbps) applications.
The DS80PCI810 works to extend the reach possible by using active linear equalization on the channel, boosting
attenuated signals so that they can be more easily recovered at the Rx. The repeater outputs are specially
designed to be transparent to Tx FIR signaling in order to pass information critical for optimal link training to the
Rx. Suggested settings for the A-channels and B-channels are given in Table 10 and Table 11. Further
adjustments to EQx and VODx settings may optimize signal margin on the link for different system applications:
Table 10. Suggested Device Settings in Pin Mode
CHANNEL SETTINGS PIN MODE
EQx Level 4
VODx[1:0] Level 6 (1, 0)
Table 11. Suggested Device Settings in SMBus Modes
CHANNEL SETTINGS SMBus MODES
EQx 0x03
VODx 110'b
VOD_DB 000'b
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The SMBus Slave Mode code example in Table 12 may be used to program the DS80PCI810 with the
recommended device settings.
Table 12. SMBus Example Sequence
REGISTER WRITE VALUE COMMENTS
0x06 0x18 Set SMBus Slave Mode Register Enable.
0x0F 0x03 Set CHB_0 EQ to 0x03.
0x10 0xAE Set CHB_0 VOD to 110'b.
0x11 0x00 Set CHB_0 VOD_DB to 000'b.
0x16 0x03 Set CHB_1 EQ to 0x03.
0x17 0xAE Set CHB_1 VOD to 110'b.
0x18 0x00 Set CHB_1 VOD_DB to 000'b.
0x1D 0x03 Set CHB_2 EQ to 0x03.
0x1E 0xAE Set CHB_2 VOD to 110'b.
0x1F 0x00 Set CHB_2 VOD_DB to 000'b.
0x24 0x03 Set CHB_3 EQ to 0x03.
0x25 0xAE Set CHB_3 VOD to 110'b.
0x26 0x00 Set CHB_3 VOD_DB to 000'b.
0x2C 0x03 Set CHA_0 EQ to 0x03.
0x2D 0xAE Set CHA_0 VOD to 110'b.
0x2E 0x00 Set CHA_0 VOD_DB to 000'b.
0x33 0x03 Set CHA_1 EQ to 0x03.
0x34 0xAE Set CHA_1 VOD to 110'b.
0x35 0x00 Set CHA_1 VOD_DB to 000'b.
0x3A 0x03 Set CHA_2 EQ to 0x03.
0x3B 0xAE Set CHA_2 VOD to 110'b.
0x3C 0x00 Set CHA_2 VOD_DB to 000'b.
0x41 0x03 Set CHA_3 EQ to 0x03.
0x42 0xAE Set CHA_3 VOD to 110'b.
0x43 0x00 Set CHA_3 VOD_DB to 000'b.
8.1.3 Rx Detect Functionality in PCIe Applications
In PCIe systems, specifications require the Tx to implement Rx detection in order to determine whether an Rx
endpoint is present. Since the DS80PCI810 is designed for placement between an ASIC Tx and endpoint Rx, the
DS80PCI810 implements automatic polling for valid Rx detection when the RXDET pin is left floating or tied low
via 20 kΩto GND. If 50 Ωimpedances are seen on both positive and negative outputs of a DS80PCI810
channel, the Rx detect state machine asserts Rx detection, and a 50 Ωtermination to VDD is provided at the
respective channel's positive and negative input. For open PCIe systems where users may swap multiple cards
in and out of a given PCIe slot, it is recommended to keep the RXDET pin floating. For closed systems where an
endpoint Rx is present in a PCIe slot at all times, the RXDET pin may be left floating or tied high via 1 kΩto VDD
(2.5 V mode) or VIN (3.3 V mode).
For more details about DS80PCI810 Rx detection, refer to Table 2.
8.2 Typical Applications
8.2.1 Generic High Speed Repeater
The DS80PCI810 extends PCB and cable reach in multiple applications by using active linear equalization. The
high linearity of this device aids specifically in protocols requiring link training and can be used in line cards,
backplanes, and motherboards, thereby improving margin and overall eye performance. The capability of the
repeater can be explored across a range of data rates and ASIC-to-link-partner signaling, as shown in the
following two test setup connections.
42 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Pattern
Generator
VOD = 1.0 Vp-p,
DE = -6 dB
PRBS15
Scope
BW = 60 GHz
DS80PCI810
TL1
Lossy Channel IN OUT TL2
Lossy Channel
Pattern
Generator
VOD = 1.0 Vp-p,
DE = 0 dB
PRBS15
Scope
BW = 60 GHz
DS80PCI810
IN OUT
TL
Lossy Channel
DS80PCI810
www.ti.com
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
Typical Applications (continued)
Figure 9. Test Setup Connections Diagram
Figure 10. Test Setup Connections Diagram
8.2.1.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Below are a list of
critical areas for consideration and study during design.
• Use 100 Ωimpedance traces. Generally these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
The DS80PCI810 is designed to be placed at an offset location with respect to the overall channel attenuation. In
order to optimize performance, the repeater requires tuning to extend the reach of the cable or trace length while
also recovering a solid eye opening. To tune the repeater, the settings mentioned in Table 10 (for Pin Mode) and
Table 11 (for SMBus Modes) are recommended as a default starting point for most applications. Once these
settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may be required to optimize the
repeater performance for each specific application environment.
Examples of the repeater performance as a generic high speed datapath repeater are illustrated in the
performance curves in the next section.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 43
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(89.35 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(106.35 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(91.9 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(109.75 mV/DIV)
CML Serializer Data Throughput
(93.7 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(106.3 mV/DIV)
Time (20.83 ps/DIV)
DS80PCI810
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
Typical Applications (continued)
8.2.1.3 Application Performance Plots
8.2.1.3.1 Pre-Channel Only Setup
No Repeater Used DS80PCI810 Settings: EQA = Level 2, VODA = Level 6
TJ (1.0E-12) = 21.6 ps TJ (1.0E-12) = 13.6 ps
Figure 11. TL = 5 Inch 5–Mil FR4 Trace, Figure 12. TL = 5 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps DS80PCI810 CHA_0, 8 Gbps
No Repeater Used DS80PCI810 Settings: EQA = Level 3, VODA = Level 6
TJ (1.0E-12) = 43.7 ps TJ (1.0E-12) = 18.1 ps
Figure 13. TL = 10 Inch 5–Mil FR4 Trace, Figure 14. TL= 10 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps DS80PCI810 CHA_0, 8 Gbps
No Repeater Used DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = Not Available Due to Closed Eye TJ (1.0E-12) = 35.5 ps
Figure 15. TL = 20 Inch 5–Mil FR4 Trace, Figure 16. TL = 20 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps DS80PCI810 CHA_0, 8 Gbps
44 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(46.05 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(63.7 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(73.25 mV/DIV)
Time (20.83 ps/DIV)
CML Serializer Data Throughput
(89.95 mV/DIV)
DS80PCI810
www.ti.com
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
Typical Applications (continued)
No Repeater DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = Not Available Due to Closed Eye TJ (1.0E-12) = 41.4 ps
Figure 17. TL = 5-Meter 30-AWG 100 ΩTwin-Axial Cable, Figure 18. TL = 5-Meter 30-AWG 100 ΩTwin-Axial Cable,
No Repeater, 8 Gbps DS80PCI810 CHA_0, 8 Gbps
8.2.1.3.2 Pre-Channel and Post-Channel Setup
No Repeater Used DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = Not Available Due to Closed Eye TJ (1.0E-12) = 33.0 ps
Figure 19. TL1 = 15 Inch 5–Mil FR4 Trace, Figure 20. TL1 = 15 Inch 5–Mil FR4 Trace,
TL2 = 10 Inch 5–Mil FR4 Trace, TL2 = 10 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps DS80PCI810 CHA_0, 8 Gbps
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 45
System Board
Root Complex
ASIC
or
PCIe EP
DS80PCI810
Board
Trace
Connector
Connector
TX
RX
RX
TX 8
8
DS80PCI810
8
8
DS80PCI810
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
Typical Applications (continued)
8.2.2 PCIe Board Applications (PCIe Gen-3)
The DS80PCI810 can be used to extend trace length on motherboards and line cards in PCIe Gen-3
applications. The high linearity of the DS80PCI810 aids in the link training protocol required by PCIe Gen-3 at 8
Gbps in accordance with PCI-SIG standards. For PCIe Gen-3, preservation of the pre-cursor and post-cursor Tx
FIR presets (P0-P10) is crucial to successful signal transmission from motherboard system root complex to line
card ASIC or Embedded Processor. Below is a typical example of the DS80PCI810 used in a PCIe application:
Figure 21. Typical PCIe Gen-3 Configuration Diagram
8.2.2.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Please reference
Design Requirements in the Generic High Speed Repeater application section for a list of critical areas for
consideration and study during design.
8.2.2.2 Design Procedure
In PCIe Gen-3 applications, there is a large range of flexibility regarding the placement of the DS80PCI810 in the
signal path due to the high linearity of the device. If the PCIe slot must also support lower speeds like PCIe Gen-
1 (2.5 Gbps) and Gen-2 (5.0 Gbps), it is recommended to place the DS80PCI810 closer to the endpoint Rx.
Once the DS80PCI810 is placed on the signal path, the repeater must be tuned. To tune the repeater, the
settings mentioned in Table 10 (for Pin Mode) and Table 11 (for SMBus Modes) are recommended as a default
starting point for most applications. Once these settings are configured, additional tuning of the EQ and, to a
lesser extent, VOD may be required to optimize the repeater performance to pass link training preset
requirements for PCIe Gen-3.
An example of a test configuration used to evaluate the DS80PCI810 in this application can be seen in
Figure 22. For more information about DS80PCI810 PCIe applications, please refer to application note SNLA227.
46 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
PCIe Gen 3.0 (x16 Lane)
^<v}Áv'}}_
Golden Graphics Card
TX: Front Side
RX: Back Side
DS80PCI810EVM
PCIe Connector
Scope
Tektronix
DSA71604
Preset Configuration Control
Preset Configuration
Control
PC Testing
Signal Test 3.2.0
Software
Data Flow
TL1
TL2
FR4 Trace
FR4 Trace
PCIe Gen-3
Compliance
Base Board
(CBB)
PCIe Gen-3
Compliance
Base Board Riser
PCIe Gen-3 Preset
Configuration Control
Lane Under
Test TX
Lane Under
Test RX
DS80PCI810
www.ti.com
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
Typical Applications (continued)
Figure 22. Typical PCIe Gen-3 Add-In Card Test Diagram
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 47
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
DS80PCI810
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
Typical Applications (continued)
8.2.2.3 Application Performance Plots
No Repeater Used DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
Composite Eye Height: 50.39 mV Composite Eye Height: 112.2 mV
Minimum Eye Width: 49.87 ps Minimum Eye Width: 83.82 ps
Overall SigTest Result: Fail Overall SigTest Result: Pass
Figure 23. PCIe Gen-3, Preset 7, Transition Eye Figure 24. PCIe Gen-3, Preset 7, Transition Eye
TL1 = 10 Inch 4-Mil FR4 Trace, No TL2 TL1 = 10 Inch 4-Mil FR4 Trace, No TL2
No Repeater, 8 Gbps DS80PCI810, 8 Gbps
No Repeater Used DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
Composite Eye Height: 50.39 mV Composite Eye Height: 112.2 mV
Minimum Eye Width: 49.87 ps Minimum Eye Width: 83.82 ps
Overall SigTest Result: Fail Overall SigTest Result: Pass
Figure 25. PCIe Gen-3, Preset 7, Non-Transition Eye Figure 26. PCIe Gen-3, Preset 7, Non-Transition Eye
TL1 = 10 Inch 4-Mil FR4 Trace, No TL2 TL1 = 10 Inch 4-Mil FR4 Trace, No TL2
No Repeater, 8 Gbps DS80PCI810, 8 Gbps
48 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
Differential Signal (V)
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Unit Intervals
DS80PCI810
www.ti.com
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
Typical Applications (continued)
No Repeater Used DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
Composite Eye Height: 0.057 mV Composite Eye Height: 77.26 mV
Minimum Eye Width: 37.66 ps Minimum Eye Width: 78.24 ps
Overall SigTest Result: Fail Overall SigTest Result: Pass
Figure 27. PCIe Gen-3, Preset 7, Transition Eye Figure 28. PCIe Gen-3, Preset 7, Transition Eye
TL1 = 10 Inch 4-Mil FR4 Trace, TL1 = 10 Inch 4-Mil FR4 Trace,
TL2 = 5 Inch 4-Mil FR4 Trace TL2 = 5 Inch 4-Mil FR4 Trace
No Repeater, 8 Gbps DS80PCI810, 8 Gbps
No Repeater Used DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
Composite Eye Height: 0.057 mV Composite Eye Height: 77.26 mV
Minimum Eye Width: 37.66 ps Minimum Eye Width: 78.24 ps
Overall SigTest Result: Fail Overall SigTest Result: Pass
Figure 29. PCIe Gen-3, Preset 7, Non-Transition Eye Figure 30. PCIe Gen-3, Preset 7, Non-Transition Eye
TL1 = 10 Inch 4-Mil FR4 Trace, TL1 = 10 Inch 4-Mil FR4 Trace,
TL2 = 5 Inch 4-Mil FR4 Trace TL2 = 5 Inch 4-Mil FR4 Trace
No Repeater, 8 Gbps DS80PCI810, 8 Gbps
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 49
VDD_SEL
VIN
VDD
VDD
VDD
VDD
VDD
3.3 V
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Internal
voltage
regulator
Enable
2.5 V
VDD_SEL
VIN
VDD
VDD
VDD
VDD
VDD
Internal
voltage
regulator
Disable
Place 0.1 µF close to VDD Pin
Total capacitance should be 7 0.5 µF
1 µF
10 µF
2.5 V
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Place capacitors close to VDD Pin
open
open
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
3.3 V mode 2.5 V mode
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
DS80PCI810
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
9 Power Supply Recommendations
Two approaches are recommended to ensure that the DS80PCI810 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS80PCI810. Smaller
body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in
the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These
capacitors can be either tantalum or an ultra-low ESR ceramic.
The DS80PCI810 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V
mode operation, the VIN pin = 3.3 V is used to supply power to the device. The internal regulator then provides
the 2.5 V to the VDD pins of the device, and a 0.1 μF cap is needed at each of the five VDD pins for power
supply de-coupling (total capacitance should equal 0.5 μF). The VDD_SEL pin must be tied to GND to enable the
internal regulator. In 2.5 V mode operation, the VIN pin should be left open and 2.5 V supply must be applied to
the five VDD pins to power the device. The VDD_SEL pin must be left open (no connect) to disable the internal
regulator.
Figure 31. 3.3 V or 2.5 V Supply Connection Diagram
50 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
46
47
48
49
50
51
52
53
54
43
42
41
4039
38
37
36
22
27
26
25
24
23
21
20
19
45
44
3
4
5
6
7
89
10 1
2
GND
BOTTOM OF PKG
13
14
15
16
17
18 11
12
33
32
3130
29
28 35
34
VDD
VDD
VDD
VDD
100 mils
20 mils
20 mils
VDD
INTERNAL STRIPLINE
EXTERNAL MICROSTRIP
DS80PCI810
www.ti.com
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
10 Layout
10.1 Layout Guidelines
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used
sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias
are used, the layout must also provide for a low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources on the printed circuit board. To minimize the
effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair and intra-pair spacing. See
AN-1187 “Leadless Leadframe Package (LLP) Application Report” (literature number SNOA401) for additional
information on QFN (WQFN) packages.
10.2 Layout Example
Figure 32 depicts different transmission line topologies which can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and by providing for a low inductance return current path. When the via
structure is associated with a thick backplane PCB, further optimization such as back drilling is often used to
reduce the detrimental high frequency effects of stubs on the signal path.
Figure 32. Typical Routing Options
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 51
DS80PCI810
SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
52 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS80PCI810NJYR ACTIVE WQFN NJY 54 2000 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 80PCI810A0
DS80PCI810NJYT ACTIVE WQFN NJY 54 250 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 80PCI810A0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2015
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS80PCI810NJYR WQFN NJY 54 2000 330.0 16.4 5.8 10.3 1.0 12.0 16.0 Q1
DS80PCI810NJYT WQFN NJY 54 250 178.0 16.4 5.8 10.3 1.0 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS80PCI810NJYR WQFN NJY 54 2000 367.0 367.0 38.0
DS80PCI810NJYT WQFN NJY 54 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
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PACKAGE OUTLINE
C
54X 0.3
0.2
3.51±0.1
50X 0.5
54X 0.5
0.3
0.8 MAX
2X
8.5
7.5±0.1
2X 4
A
10.1
9.9
B5.6
5.4
0.3
0.2
0.5
0.3
(0.1)
4214993/A 07/2013
WQFNNJY0054A
WQFN
PIN 1 INDEX AREA
SEATING PLANE
1
18 28
45
19 27
54 46
0.1 C A B
0.05 C
(OPTIONAL)
PIN 1 ID
DETAIL
SEE TERMINAL
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 2.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
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EXAMPLE BOARD LAYOUT
(3.51)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
54X (0.6)
54X (0.25)
(9.8)
(5.3)
() TYP
VIA
0.2
50X (0.5)
2X
(1.16)
(1) TYP
(7.5)
(1.17)
TYP
4214993/A 07/2013
WQFNNJY0054A
WQFN
SYMM SEE DETAILS
1
18
19 27
28
45
46
54
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
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EXAMPLE STENCIL DESIGN
(1.17)
TYP
(5.3)
54X (0.6)
54X (0.25)
12X (1.51)
(9.8)
(0.855) TYP
12X (0.97)
50X (0.5)
4214993/A 07/2013
WQFNNJY0054A
WQFN
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
TYP
METAL
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
1
18
19 27
28
45
46
54
SYMM
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