SI8642BC-B-IS1 - Silicon Labs - Datasheet.Technology

Si8640/41/42/45

LOW-POWER QUAD-CHANNEL DIGITAL ISOLATOR

Features

Applications

Safety Regulatory Approvals

Description

Silicon Lab's family of ultra-low-power digital isolators are CMOS devices

offering substantial data rate, propagation delay, power, size, reliability, and

external BOM advantages over legacy isolation technologies. The operating

parameters of these products remain stable across wide temperature ranges

and throughout device service life for ease of design and highly uniform

performance. All device versions have Schmitt trigger inputs for high noise

immunity and only require VDD bypass capacitors.

Data rates up to 150 Mbps are supported, and all devices achieve propagation

delays of less than 10 ns. Enable inputs provide a single point control for

enabling and disabling output drive. Ordering options include a choice of

isolation ratings (3.75 and 5 kV) and a selectable fail-safe operating mode to

control the default output state during power loss. All products >1 kVRMS are

safety certified by UL, CSA, and VDE, and products in wide-body packages

support reinforced insul ation withstanding up to 5 kVRMS.

High-speed operation

DC to 150 Mbps

No start-up initialization required

Wide Operating Supply Voltage

2.5–5.5 V

Up to 5000 VRMS isolation

60-year life at rated working voltage

High electromagnetic immunity

Ultra low power (typical)

5 V Operation

1.6 mA per channel at 1 Mbps

5.5 mA per channel at 100 Mbps

2.5 V Operation

1.5 mA per channel at 1 Mbps

3.5 mA per channel at 100 Mbps

Tri-state outputs with ENABLE

Schmitt trigger inputs

Selectable fail-safe mode

Default high or low output

(ordering option)

Precise timing (typical)

10 ns propagation delay

1.5 ns pulse width distortion

0.5 ns channel-channel skew

2 ns propagation delay skew

5 ns minimum pulse width

Transient Immunity 50 kV/µs

AEC-Q100 qualification

Wide temperature range

–40 to 125 °C

RoHS-compliant packages

SOIC-16 wide body

SOIC-16 narrow body

QSOP-16

Industrial automation systems

Medical electronics

Hybrid electric vehicles

Isolated switch mode supplies

Isolated ADC, DAC

Motor control

Power inverters

Communications systems

UL 1577 recognized

Up to 5000 VRMS for 1 minute

CSA component notice 5A approval

IEC 60950-1, 61010-1, 60601-1

(reinforced insulation)

VDE certification conformity

IEC 60747-5-2

(VDE0884 Part 2)

EN60950-1

(reinforced insulation)

Ordering Information:

See page 26.

2 Rev. 1.4

Si8640/41/42/45

Rev. 1.4 3

Si8640/41/42/45

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

10. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

11. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

12.1. Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

12.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .36

12.3. Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

12.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . .37

12.5. Top Marking (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.6. Top Marking Explanation (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4 Rev. 1.4

Si8640/41/42/45

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 ºC

Supply Voltage VDD1 2.5 — 5.5 V

VDD2 2.5 — 5.5 V

*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,

and supply voltage.

Table 2. Electrical Characteristics

(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)

Parameter Symbol Test Condition Min Typ Max Unit

VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V

VDD Undervoltage Threshold VDDU V– VDD1, VDD2 falling 1.88 2.16 2.325 V

VDD Negative-Going Locko ut

Hysteresis VDDHYS 50 70 95 mV

Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V

Negative-Going Input

Threshold VT– All inputs falling 1.0 1.23 1.4 V

Input Hysteres is VHYS 0.38 0.44 0.50 V

High Level Input Voltage VIH 2.0 — — V

Low Level Input Voltage VIL ——0.8V

High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakag e Curr en t IL——±10µA

Output Impedance1ZO—50—

Enable Input High Current IENH VENx =V

IH —2.0—µA

Enable Input Low Current IENL VENx =V

IL —2.0—µA

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.4 5

Si8640/41/42/45

DC Supply Current (All inputs 0 V or at Supply)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

VDD1

VDD2

VI= 0(Bx), 1(Ex)

VI= 1(Bx), 0(Ex)

—

1.0

2.4

6.1

2.5

1.6

3.8

9.2

4.0

Si8641Bx, Ex

VDD1

VDD2

VDD1

VDD2

VI= 0(Bx), 1(Ex)

VI= 1(Bx), 0(Ex)

—

1.4

2.3

5.2

3.6

2.2

3.7

7.8

5.4

Si8642Bx, Ex

VDD1

VDD2

VDD1

VDD2

VI= 0(Bx), 1(Ex)

VI= 1(Bx), 0(Ex)

—

1.8

4.4

2.9

6.6

1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

2.9 5.0

4.0 mA

Si8641Bx, Ex

VDD1

VDD2

—

—3.4

3.3 4.8

4.6 mA

Si8642Bx, Ex

VDD1

VDD2

—

—3.3

3.3 4.6

4.6 mA

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

4.0 5.0

5.6 mA

Si8641Bx, Ex

VDD1

VDD2

—

—3.7

4.1 5.2

5.8 mA

Si8642Bx, Ex

VDD1

VDD2

—

—3.9

3.9 5.4

5.4 mA

Table 2. Electrical Characteristics (Continued)

(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

6 Rev. 1.4

Si8640/41/42/45

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

17.5 5.0

22.8 mA

Si8641Bx, Ex

VDD1

VDD2

—

—7.3

14.3 9.8

18.5 mA

Si8642Bx, Ex

VDD1

VDD2

—

—11

11 14.3

14.3 mA

Timing Characteristics

Si864xBx, Ex

Maximum Data Rate 0 — 150 Mbps

Minimum Pulse Width — — 5.0 ns

Propagation Delay tPHL, tPLH See Figure 2 5.0 8.0 13 ns

Pulse Width Distortion

|tPLH – tPHL|PWD See Fig ure 2 — 0.2 4.5 ns

Propagation Delay Skew2tPSK(P-P) —2.04.5ns

Channel-Channel Skew tPSK —0.42.5ns

All Models

Output Rise Time trCL=15pF

See Figure 2 —2.5 4.0 ns

Output Fall Time tfCL=15pF

See Figure 2 —2.5 4.0 ns

Peak Eye Diagram Jitter tJIT(PK) See Figure 7 — 350 — ps

Common Mode

Transient Immunity CMTI VI=V

DD or 0 V 35 50 — kV/µs

Enable to Data Valid ten1 See Figure 1 — 6.0 11 ns

Enable to Data Tri-State ten2 See Figure 1 — 8.0 12 ns

Startup T ime3tSU —1540µs

Table 2. Electrical Characteristics (Continued)

(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.4 7

Si8640/41/42/45

Figure 1. ENABLE Timing Diagram

Figure 2. Propagation Delay Timing

ENABLE

OUTPUTS

ten1 ten2

Typical

Input tPLH tPHL

Typical

Output trtf

90%

10%

90%

10%

1.4 V

8 Rev. 1.4

Si8640/41/42/45

Table 3. Electrical Characteristics

(VDD1 =3.3V ±10%, V

DD2 = 3.3 V ±10%, TA= –40 to 125 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V

VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V

VDD Negative-Going Lockout

Hysteresis VDDHYS 50 70 95 mV

Positive-Goin g In pu t Th re sh o ld VT+ All inputs rising 1.4 1.67 1.9 V

Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V

Input Hysteresis VHYS 0.38 0.44 0.50 V

High Level Input Voltage VIH 2.0 — — V

Low Level Input Voltage VIL ——0.8V

High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakage Current IL——±10µA

Output Impedance1ZO—50—

Enable Input High Current IENH VENx =V

IH —2.0—µA

Enable Input Low Current IENL VENx =V

IL —2.0—µA

DC Supply Current (All inputs 0 V or at supply)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

VDD1

VDD2

VI=0(Bx), 1(Ex)

VI=1(Bx), 0(Ex)

—

1.0

2.4

6.1

2.5

1.6

3.8

9.2

4.0

Si8641Bx, Ex

VDD1

VDD2

VDD1

VDD2

VI=0(Bx), 1(Ex)

VI=1(Bx), 0(Ex)

—

1.4

2.3

5.2

3.6

2.2

3.7

7.8

5.4

Si8642Bx, Ex

VDD1

VDD2

VDD1

VDD2

VI=0(Bx), 1(Ex)

VI=1(Bx), 0(Ex)

—

1.8

4.4

2.9

6.6

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the differe nce in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.4 9

Si8640/41/42/45

1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

2.9 5.0

4.0 mA

Si8641Bx, Ex

VDD1

VDD2

—

—3.4

3.3 4.8

4.6 mA

Si8642Bx, Ex

VDD1

VDD2

—

—3.3

3.3 4.6

4.6 mA

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

3.4 5.0

4.7 mA

Si8641Bx, Ex

VDD1

VDD2

—

—3.5

3.6 4.9

5.1 mA

Si8642Bx, Ex

VDD1

VDD2

—

—3.6

3.6 5.0

5.0 mA

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

12.3 5.0

15.9 mA

Si8641Bx, Ex

VDD1

VDD2

—

—5.9

10.3 7.9

13.4 mA

Si8642Bx, Ex

VDD1

VDD2

—

—8.2

8.2 10.7

10.7 mA

Table 3. Electrical Characteristics (Continued)

(VDD1 =3.3V ±10%, V

DD2 = 3.3 V ±10%, TA= –40 to 125 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the differe nce in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

10 Rev. 1.4

Si8640/41/42/45

Timing Characteristics

Si864xBx, Ex

Maximum Data Rate 0 — 150 Mbps

Minimum Pulse Width — — 5.0 ns

Propagation Delay tPHL, tPLH See Figure 2 5.0 8.0 13 ns

Pulse Width Distortion

|tPLH – tPHL|PWD See Figure 2 — 0.2 4.5 ns

Propagation Delay Skew2tPSK(P-P) —2.04.5ns

Channel-Channel Skew tPSK —0.42.5ns

All Models

Output Rise Time trCL=15pF

See Figure 2 —2.5 4.0 ns

Output Fall Time tfCL=15pF

See Figure 2 —2.5 4.0 ns

Peak eye diagram jitter tJIT(PK) See Figure 7 — 3 50 — ps

Common Mode Transient

Immunity at Logic Low Output CMTI VI=V

DD or 0 V 35 50 — kV/µs

Enable to Data Valid ten1 See Figure 1 — 6.0 11 ns

Enable to Data Tri-State ten2 See Figure 1 — 8.0 12 ns

Startup Time3tSU —1540µs

Table 3. Electrical Characteristics (Continued)

(VDD1 =3.3V ±10%, V

DD2 = 3.3 V ±10%, TA= –40 to 125 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the differe nce in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.4 11

Si8640/41/42/45

Table 4. Electrical Characteristics

(VDD1 =2.5V ±5%, V

DD2 = 2.5 V ±5%, TA= –40 to 125 ºC)

Parameter Symbol Test Cond i tio n Min Typ Max Unit

VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V

VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V

VDD Negative-Going Locko ut

Hysteresis VDDHYS 50 70 95 mV

Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V

Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V

Input Hysteres is VHYS 0.38 0.44 0.50 V

High Level Input Voltage VIH 2.0 — — V

Low Level Input Voltage VIL ——0.8V

High Level Output Voltage VOH loh = –4 mA VDD1,

VDD2 –0.4 2.3 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakag e Curr en t IL——±10µA

Output Impedance1ZO—50—

Enable Input High Current IENH VENx =V

IH —2.0—µA

Enable Input Low Current IENL VENx =V

IL —2.0—µA

DC Supply Current (All inputs 0 V or at supply)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

VDD1

VDD2

VI= 0(Bx), 1(Ex)

VI= 1(Bx), 0(Ex)

—

1.0

2.4

6.1

2.5

1.6

3.8

9.2

4.0

Si8641Bx, Ex

VDD1

VDD2

VDD1

VDD2

VI= 0(Bx), 1(Ex)

VI= 1(Bx), 0(Ex)

—

1.4

2.3

5.2

3.6

2.2

3.7

7.8

5.4

Si8642Bx, Ex

VDD1

VDD2

VDD1

VDD2

VI= 0(Bx), 1(Ex)

VI= 1(Bx), 0(Ex)

—

1.8

4.4

2.9

6.6

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

12 Rev. 1.4

Si8640/41/42/45

1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

2.9 5.0

4.0 mA

Si8641Bx, Ex

VDD1

VDD2

—

—3.4

3.3 4.8

4.6 mA

Si8642Bx, Ex

VDD1

VDD2

—

—3.3

3.3 4.6

4.6 mA

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Si8645Bx

VDD1

VDD2

—

—3.6

3.1 5.0

4.3 mA

Si8641Bx, Ex

VDD1

VDD2

—

—3.5

3.4 4.8

4.8 mA

Si8642Bx, Ex

VDD1

VDD2

—

—3.4

3.4 4.8

4.8 mA

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8640Bx, Ex, Si8645Bx

VDD1

VDD2

—

—3.6

9.9 5.0

12.8 mA

Si8641Bx, Ex

VDD1

VDD2

—

—5.2

8.5 7.0

11.1 mA

Si8642Bx, Ex

VDD1

VDD2

—

—6.9

6.9 9.0

9.0 mA

Table 4. Electrical Characteristics (Continued)

(VDD1 =2.5V ±5%, V

DD2 = 2.5 V ±5%, TA= –40 to 125 ºC)

Parameter Symbol Test Cond i tio n Min Typ Max Unit

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.4 13

Si8640/41/42/45

Timing Characteristics

Si864xBx, Ex

Maximum Data Rate 0 — 150 Mbps

Minimum Pulse Width — — 5.0 ns

Propagation Delay tPHL, tPLH See Figure 2 5.0 8.0 14 ns

Pulse Width Distortion

|tPLH – tPHL|PWD See Figure 2 — 0.2 5.0 ns

Propagation Delay Skew2tPSK(P-P) —2.05.0ns

Channel-Channel Skew tPSK —0.42.5ns

All Models

Output Rise Time trCL=15pF

See Figure 2 —2.5 4.0 ns

Output Fall Time tfCL=15pF

See Figure 2 —2.5 4.0 ns

Peak Eye Diagram Jitter tJIT(PK) See Figure 7 — 350 — ps

Common Mode Transient

Immunity at Logic Low Output CMTI VI=V

DD or 0 V 35 50 — kV/µs

Enable to Data Valid ten1 See Figure 1 — 6.0 11 ns

Enable to Data Tri-State ten2 See Figure 1 — 8.0 12 ns

Startup T ime3tSU —1540µs

Table 4. Electrical Characteristics (Continued)

(VDD1 =2.5V ±5%, V

DD2 = 2.5 V ±5%, TA= –40 to 125 ºC)

Parameter Symbol Test Cond i tio n Min Typ Max Unit

1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

14 Rev. 1.4

Si8640/41/42/45

Table 5. Regulatory Information*

CSA

The Si864x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.

61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.

60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working volt-

age.

60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.

VDE

The Si864x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.

60747-5-2: Up to 1200 Vpeak for basic insulation working voltage.

60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working volt-

age.

The Si864x is certified under UL1577 component recognition program. For more details, see File E257455.

Rated up to 5000 VRMS isolation voltage for basic protection.

*Note: Regu latory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kV RMS for 1 sec.

Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.

For more information, see "5. Ordering Guide" on page 26.

Table 6. Insulation and Safety-Related Specifications

Parameter Symbol Test Condition Value Unit

SOIC-16 NB

SOIC-16 QSOP-16

Nominal Air Gap (Clearance)1L(IO1) 8.0 4.9 3.6 mm

Nominal External Tracking

(Creepage)1L(IO2) 8.0 4.01 3.6 mm

Minimum Internal Gap

(Internal Clearance) 0.014 0.011 0.008 mm

Tracking Resistance

(Proof Tracking Index) PTI IEC60112 600 600 600 VRMS

Erosion Depth ED 0.019 0.019 0.031 mm

Resistance (Input-Output)2RIO 1012 1012 1012 

Capacitance (Input-Output)2CIO f = 1 MHz 2.0 2.0 2.0 pF

Input Capacitance3CI4.0 4.0 4.0 pF

Notes:

1. The values in this table correspond to the nominal creepage and clearance values. VDE certifie s the clearance and

creepage limits as 4.7 mm minimum for the NB SOIC-16 and QSOP-16 packages and 8.5 mm minimum for the WB

SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA

certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16, 3.6 mm for QSOP-16 packages

and 7.6 mm minimum for the WB SOIC-16 package.

2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted

together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are

then measured between these two terminals.

3. Measured from input pin to ground.

Rev. 1.4 15

Si8640/41/42/45

Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings

Parameter Test Conditions Specification

NB SOIC-16 WB SOIC-16

Basic Isolation Group Material Group I I

Installation Classification

Rated Mains Volt ages < 150 VRMS I-IV I-IV

Rated Mains Volt ages < 300 VRMS I-III I-IV

Rated Mains Volt ages < 400 VRMS I-II I-III

Rated Mains Volt ages < 600 VRMS I-II I-III

Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*

Parameter Symbol Test Condition Characteristic Unit

SOIC-16 NB

SOIC-16

Maximum Working

Insulation Voltage VIORM 1200 630 Vpeak

Input to Output Test Voltage VPR

Method b1

(VIORM x1.875=V

PR, 100%

Production Test, tm= 1 sec,

Partial Discharge < 5 pC)

2250 1182

Transient Overvoltage VIOTM t = 60 sec 6000 6000 Vpeak

Pollution Degree

(DIN VDE 0110, Table 1) 22

Insulation Resistance at TS,

VIO =500V RS>109>109

*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of

40/125/21.

Table 9. IEC Safety Limiting Values1

Parameter Symbol Test Condition Min Typ Max Unit

SOIC-16 NB

SOIC-16

Case Temperature TS— — 150 150 °C

Safety Input,

Output, or Supply

Current IS

JA = 100 °C/W (WB SOIC-16),

105 °C/W (NB SOIC-16, QSOP-16),

VI= 5.5 V, TJ=150°C, T

A=25°C — — 220 210 mA

Device Power

Dissipation2PD— — 275 275 mW

Notes:

1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4.

2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square

wave.

16 Rev. 1.4

Si8640/41/42/45

Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Te mperature per DIN EN 60747-5-2

Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Te mperature per DIN EN 60747-5-2

Table 10. Thermal Characteristics

Parameter Symbol Test Condition WB SOIC-16 NB SOIC-16

QSOP-16 Unit

IC Junction-to- Air T herm a l

Resistance JA 100 105 ºC/W

0 20015010050

500

400

200

100

Temperature (ºC)

Safety-Limiting Current (mA)

450

300

370

220

VDD1, VDD2 = 2.70 V

VDD1, VDD2 = 3.6 V

VDD1, VDD2 = 5.5 V

0 20015010050

500

400

200

100

Temperature (ºC)

Safety-Limiting Current (mA)

430

300

360

210

VDD1, VDD2 = 2.70 V

VDD1, VDD2 = 3.6 V

VDD1, VDD2 = 5.5 V

Rev. 1.4 17

Si8640/41/42/45

Table 11. Absolute Maximum Ratings1

Parameter Symbol Min Typ Max Unit

Storage Temperature2TSTG –65 — 150 ºC

Ambient Temper a tur e Unde r Bia s TA–40 — 125 ºC

Junction Temperature TJ——150°C

Supply Voltage VDD1, VDD2 –0.5 — 7.0 V

Input Voltage VI–0.5 — VDD + 0.5 V

Output Voltage VO–0.5 — VDD + 0.5 V

Output Current Drive Channel IO——10mA

Lead Solder Temperature (10 s) — — 260 ºC

Maximum Isolation (Input to Output) (1 sec)

NB SOIC-16, QSOP-16 — — 4500 VRMS

Maximum Isolation (Input to Output) (1 sec)

WB SOIC-16 — — 6500 VRMS

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute

maximum ratings for extended period s may degrade performance.

2. VDE certifies storage temperature from –40 to 150 °C.

18 Rev. 1.4

Si8640/41/42/45

2. Functional Description

2.1. Theory of Operation

The operation of an Si864x channel is analogous to that of an opto coupler, except an RF carrier is modulated

instead of light. This simple architecture provides a robust isolated data path and requires no special

considerations or initialization at start-up. A simplified block diagram for a single Si864x channel is shown in

Figure 5.

Figure 5. Simplified Channel Diagram

A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.

Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The

Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the

result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it

provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See

Figure 6 for more details.

Figure 6. Modulation Scheme

OSCILLATOR

MODULATOR DEMODULATOR

A B

Semiconductor-

Based Isolation

Barrier

Transmitter Receiver

Input Signal

Output Signal

Modulation Signal

Rev. 1.4 19

Si8640/41/42/45

2.2. Eye Diagram

Figure 7 illustrates an eye-diagram taken on an Si8640. For the data source, the test used an Anritsu (MP1763C)

Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8640 were

captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of

150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.

Figure 7. Eye Diagram

20 Rev. 1.4

Si8640/41/42/45

3. Device Operation

Device behavior during start-up, normal operation, and shutdown is shown in Figure 8, where UVLO+ and UVLO-

are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when

power supply (VDD) is not present. Additionally, refer to Table 13 for logic conditions when enable pins are used.

Table 12. Si86xx Logic Operation

Input1,2 EN

Input1,2,3,4 VDDI

State1,5,6 VDDO

State1,5,6 VO Output1,2 Comments

HH or NC P P H Enabled, normal operation.

LH or NC P P L

X7L P P Hi-Z8Disabled.

X7H or NC UP P L9

H9Upon transition of VDDI from unpowered to pow-

ered, VO returns to the same state as VI in less

than 1 µs.

X7L UP P Hi-Z8Disabled.

X7X7P UP Undetermined

Upon transition of VDDO from unpowered to p ow-

ered, VO returns to the same state as VI within

1 µs, if EN is in either the H or NC state. Upon

transition of VDDO from unpowered to powered,

VO returns to Hi-Z within 1 µs if EN is L.

Notes:

1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN

is the enable control input located on the same output side.

2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.

3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is

operating in noisy environments.

4. No Connect (NC) replaces EN1 on Si8640/45. No Connect replaces EN2 on the Si8645. No Connects are not internally

connected and can be left floating, tied to VDD, or tied to GND.

5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.

6. “Unpowered” state (UP) is defined as VDD = 0 V.

7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.

8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is

disabled (EN = 0).

9. See "5. Ordering Guide" on page 26 for details. This is the selectable fail-safe operating mode (ordering option). Some

devices have default output state = H, and some have default output state = L, depending on the ordering part number

(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data

channels have pull-downs on inputs/outputs.

Rev. 1.4 21

Si8640/41/42/45

Table 13. Enable Input Truth1

P/N EN11,2 EN21,2 Operation

Si8640 — H Outputs B1, B2, B3, B4 are enabled and follow the input state.

— L Outputs B1, B2, B3, B4 are disabled and in high impedance state.3

Si8641 H X Output A4 enabled and follows the input state.

L X Output A4 disabled and in high impedance state.3

X H Outputs B1, B2, B3 are enabled and follow the input state.

X L Outputs B1, B2, B3 are disabled and in high impedance state.3

Si8642 H X Outputs A3 and A4 are enabled and follow the input state.

L X Outputs A3 and A4 are disabled and in high impedance state.3

X H Outputs B1 and B2 are enabled and follow the input state.

X L Outputs B1 and B2 are disabled and in high impedance state.3

Si8645 — — Outputs B1, B2, B3, B4 are enabled and follow the input state.

Notes:

1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic

operation is summarized for each isolator product in Table 13. Thes e inputs are internally pulled-up to local VDD by a

2 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize

noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is

recommended they be connected to an external logic level, especially if the Si86xx is operating in a noisy environment.

2. X = not applicable; H = Logic High; L = Logic Low.

3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is

disabled (EN = 0).

22 Rev. 1.4

Si8640/41/42/45

3.1. Device Startup

Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following

this, the outputs follow the states of inputs.

3.2. Undervoltage Lockout

Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or

when VDD is below its specified operating circuits range. Both Side A and Side B each have their own

undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A

unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above

VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.

Figure 8. Device Behavior during Normal Operation

INPUT

VDD1

UVLO-

VDD2

UVLO+

UVLO-

UVLO+

OUTPUT

tSTART tSTART tSTART tPHL tPLH

tSD

Rev. 1.4 23

Si8640/41/42/45

3.3. Layout Recommendations

To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically

separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance

(creepage/clear ance). I f a com ponent, such as a digital isolator, straddles this isolation barrier, it must meet those

creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating

(commonly referred to as working voltage protection). Table 5 on page 14 and Table 6 on page 14 detail the

working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component

standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for

end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)

requirements before starting an y des ign tha t uses a digital isolator.

3.3.1. Supply Bypass

The Si864x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The

capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user

may also include resistors (50–300  ) in series with the inputs and outputs if the system is excessively noisy.

3.3.2. Output Pin Termination

The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination

of the value of the on-chip series termination resistor and cha nnel resist ance of the output driver FET. When driving

loads where transmission line effect s will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

3.4. Fail-Safe Operating Mode

Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input

supply is unpowered) can either be a logic high or logic lo w when the outp ut supply is powere d. See Table 12 on

page 20 and "5. Ordering Guide" on page 26 for more information.

24 Rev. 1.4

Si8640/41/42/45

3.5. Typical Performance Characteristics

The typical performance ch ar acteristics depicted in the following diag ra ms are for info rmatio n p urpose s only. Refer

to Tables 2, 3, and 4 for actual specification limits.

Figure 9. Si8640/45 Typical VDD1 Supply

Current vs. Data Rate 5, 3.3, and 2.5 V

Operation

Figure 10. Si8641 Typical VDD1 Supply Current

vs. Data Rate 5, 3.3, and 2.5 V Operation

Figure 11. Si8642 Typical VDD1 or VDD2 Supply

Current vs. Data Rate 5, 3.3, and 2.5 V

Operation (15 pF Load)

Figure 12. Si8640/45 Typical VDD2 Supply

Current vs. Data Rate 5, 3.3, and 2.5 V

Figure 13. Si8641 Typical VDD2 Supply Current

vs. Data Rate 5, 3.3, and 2.5 V Operation

(15 pF Load)

Figure 14. Propagation Delay vs. Temperature

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Current (mA)

Data Rate (Mbps)

3.3V

2.5V

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Current (mA)

Data Rate (Mbps)

3.3V

2.5V

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Current (mA)

Data Rate (Mbps)

3.3V

2.5V

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Current (mA)

Data Rate (Mbps)

3.3V

2.5V

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Current (mA)

Data Rate (Mbps)

3.3V

2.5V

5.0

6.0

7.0

8.0

9.0

10.0

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120

Delay (ns)

Temperature (Degrees C)

Rev. 1.4 25

Si8640/41/42/45

4. Pin Descriptions

Name SOIC-16 Pin# Type Description

VDD1 1 Supply Side 1 power supply.

GND1 21Ground Side 1 ground.

A1 3 Digital Input Side 1 digital input.

A2 4 Digital Input Side 1 digital input.

A3 5 Digital I/O Side 1 digital input or output.

A4 6 Digital I/O Side 1 digital input or output.

EN1/NC27 Digital Input Side 1 active high enable. NC on Si8640/45.

GND1 81Ground Side 1 ground.

GND2 91Ground Side 2 ground.

EN2/NC210 Digital Input Side 2 active high enable. NC on Si8645.

B4 11 Digital I/O Side 2 digital input or output.

B3 12 Digital I/O Side 2 digital input or output.

B2 13 Digital Output Side 2 digital output.

B1 14 Digital Output Side 2 digital output.

GND2 151Ground Side 2 ground.

VDD2 16 Supply Side 2 power supply.

Notes:

1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pi n 15

must also be connected to external ground.

2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.

VDD1

GND1

EN1

GND1

VDD2

GND2

EN2

XMITR RF

RCVR

XMITR RF

RCVR

XMITR RF

RCVR

XMITR

RCVR

Si8641

VDD1

GND1

VDD2

GND2

EN2/NC

XMITR RF

RCVR

XMITR RF

RCVR

XMITR RF

RCVR

XMITR RF

RCVR

Si8640/45

VDD1

GND1

EN1

GND1

VDD2

GND2

EN2

XMITR RF

RCVR

XMITR RF

RCVR

XMITR

RCVR

XMITR

RCVR

Si8642

26 Rev. 1.4

Si8640/41/42/45

5. Ordering Guide

Table 14. Ordering Guide for Valid OPNs1,2

Ordering Part

Number (OPN) Number

of Inputs

VDD1

Side

Number

of Inputs

VDD2

Side

Max Data

Rate

(Mbps)

Default

Output

State

Isolation

rating (kV) Temp (°C) Package

Si8640BC-B-IS1 4 0 150 Low 3.75 –40 to 125 °C NB SOIC-16

Si8640EC-B-IS1 4 0 150 High 3.75 –40 to 125 °C NB SOIC-16

Si8641BC-B-IS1 3 1 150 Low 3.75 –40 to 125 °C NB SOIC-16

Si8641EC-B-IS1 3 1 150 High 3.75 –40 to 125 °C NB SOIC-16

Si8642BC-B-IS1 2 2 150 Low 3.75 –40 to 125 °C NB SOIC-16

Si8642EC-B-IS1 2 2 150 High 3.75 –40 to 125 °C NB SOIC-16

Si8642BA-C-IU 2 2 150 Low 1.0 –40 to 125 °C QSOP-16

Si8645BA-C-IU 4 0 150 Low 1.0 –40 to 125 °C QSOP-16

Si8641BA-C-IU 3 1 150 Low 1.0 –40 to 125 °C QSOP-16

Si8645BC-B-IS1 4 0 150 Low 3.75 –40 to 125 °C NB SOIC-16

Si8640BD-B-IS 4 0 150 Low 5.0 –40 to 125 °C WB SOIC-16

Si8640ED-B-IS 4 0 150 High 5.0 –40 to 125 °C WB SOIC-16

Si8641BD-B-IS 3 1 150 Low 5.0 –40 to 125 °C WB SOIC-16

Si8641ED-B-IS 3 1 150 High 5.0 –40 to 125 °C WB SOIC-16

Si8642BD-B-IS 2 2 150 Low 5.0 –40 to 125 °C WB SOIC-16

Si8642ED-B-IS 2 2 150 High 5.0 –40 to 125 °C WB SOIC-16

Si8645BD-B-IS 4 0 150 Low 5.0 –40 to 125 °C WB SOIC-16

Notes:

1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard

classifications and peak so lder temperatures.

Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages.

Moisture sensitivity level is MSL2A for narrow-body SOIC-16 packages.

Moisture sensitivity level is MSL2A for QSOP-16 packages.

2. All devices >1 kVRMS are AEC-Q100 qualified.

Rev. 1.4 27

Si8640/41/42/45

6. Package Outline: 16-Pin Wide Body SOIC

Figure 15 illustrates the package details for the Si864x Digital Isolator. Table 15 lists the values for the dimensions

shown in the illustration.

Figure 15. 16-Pin Wide Body SOIC

28 Rev. 1.4

Si8640/41/42/45

Table 15. Package Diagram Dimensions

Dimension Min Max

A — 2.65

A1 0.10 0.30

A2 2.05 —

b 0.31 0.51

c 0.20 0.33

D 10.30 BSC

E 10.30 BSC

E1 7.50 BSC

e1.27 BSC

L 0.40 1.27

h 0.25 0.75

0° 8°

aaa —0.10

bbb — 0.33

ccc —0.10

ddd — 0.25

eee —0.10

fff —0.20

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Outline MS-013, Variation AA.

4. Recommended reflow profile per JEDEC J-STD-020C specification for

small body, lead-free components.

Rev. 1.4 29

Si8640/41/42/45

7. Land Pattern: 16-Pin Wide-Body SOIC

Figure 16 illustrates the recommended land pattern details for the Si864x in a 16-pin wide-body SOIC. Table 16

lists the values for the dimensions shown in the illustration.

Figure 16. 16-Pin SOIC Land Pattern

Table 16. 16-Pin Wide Body SOIC Land Pattern Dimensions

Dimension Feature (mm)

C1 Pad Column Spacing 9.40

E Pad Row Pitch 1.27

X1 Pad Width 0.60

Y1 Pad Length 1.90

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN

for Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card

fabrication tolerance of 0.05 mm is assumed.

30 Rev. 1.4

Si8640/41/42/45

8. Package Outline: 16-Pin Narrow Body SOIC

Figure 17 illustrates the package details for the Si864x in a 16-pin narrow-body SOIC (SO-16). Table 17 lists the

values for the dimensions shown in the illustration.

Figure 17. 16-pin Small Outline Integrated Circuit (SOIC) Package

Rev. 1.4 31

Si8640/41/42/45

Table 17. Package Diagram Dimensions

Dimension Min Max

A — 1.75

A1 0.10 0.25

A2 1.25 —

b0.310.51

c0.170.25

D 9.90 BSC

E 6.00 BSC

E1 3.90 BSC

e 1.27 BSC

L0.401.27

L2 0.25 BSC

h0.250.50

θ0° 8°

aaa 0.10

bbb 0.20

ccc 0.10

ddd 0.25

Notes:

1. All dimensions shown are in millimeters (mm) unl ess otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation

AC.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

32 Rev. 1.4

Si8640/41/42/45

9. Land Pattern: 16-Pin Narrow Body SOIC

Figure 18 illustrates the recommended land pattern details for the Si864x in a 16-pin narrow-body SOIC. Table 18

lists the values for the dimensions shown in the illustration.

Figure 18. 16-Pin Narrow Body SOIC PCB Land Pattern

Table 18. 16-Pin Narrow Body SOIC Land Pattern Dimensions

Dimension Feature (mm)

C1 Pad Column Spacing 5.40

E Pad Row Pitch 1.27

X1 Pad Width 0.60

Y1 Pad Length 1.55

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N

for Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card

fabrication tolerance of 0.05 mm is assumed.

Rev. 1.4 33

Si8640/41/42/45

10. Package Outline: 16-Pin QSOP

Figure 19 illustrates the package details for the Si864x in a 16-pin QSOP package. Table 19 lists the values for the

dimensions shown in the illustration.

Figure 19. 16-pin QSOP Package



34 Rev. 1.4

Si8640/41/42/45

Table 19. Package Diagram Dimensions

Dimension Min Max

A — 1.75

A1 0.10 0.25

A2 1.25 —

b 0.20 0.30

c 0.17 0.25

D 4.89 BSC

E 6.00 BSC

E1 3.90 BSC

e 0.635 BSC

L 0.40 1.27

L2 0.25 BSC

h 0.25 0.50

θ0° 8°

aaa 0.10

bbb 0.20

ccc 0.10

ddd 0.25

Notes:

1. All dimensions shown are in millimeters (mm) unl ess otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification

for Small Body Components.

Rev. 1.4 35

Si8640/41/42/45

11. Land Pattern: 16-Pin QSOP

Figure 20 illustrates the recommended land pattern details for the Si864x in a 16-pin narrow-body SOIC. Table 20

lists the values for the dimensions shown in the illustration.

Figure 20. 16-Pin QSOP PCB Land Pattern

Table 20. 16-Pin QSOP Land Pattern Dimensions

Dimension Feature (mm)

C1 Pad Column Spacing 5.40

E Pad Row Pitch 0.635

X1 Pad Width 0.40

Y1 Pad Length 1.55

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for

Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card

fabrication tolerance of 0.05mm is assumed.



36 Rev. 1.4

Si8640/41/42/45

12. Top Markings

12.1. Top Marking (16-Pin Wide Body SOIC)

12.2. Top Marking Explanation (16-Pin Wide Body SOIC)

Line 1 Marking: Base Pa rt Number

Ordering Options

(See Ordering Gui de fo r mo re

information).

Si86 = Isolator product series

XY = Channel Configuration

X = # of data channels (4, 3, 2, 1)

Y = # of reverse channels (2, 1, 0)*

S = Speed Grade (max data rate) and operating mode:

A = 1 Mbps (default output = low)

B = 150 Mbps (default ou tp ut = low)

D = 1 Mbps (default output = high)

E = 150 Mbps (default ou tp ut = high)

V = Insulation rating

A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV

Line 2 Marking: YY = Year

WW = Workweek Assigned by assembly subcontractor. Corresponds to the

year and workweek of the mold date.

RTTTTT = Mfg Code Manufacturing code from assembly house

“R” indicates revision

Line 3 Marking: Circle = 1.5 mm Diameter

(Center-Justified) “e3” Pb-Free Symbol

Country of Origin ISO Code

Abbreviation TW = Taiwan

*Note: Si8645 has 0 reverse channels.

Si86XYSV

YYWWRTTTTT

Rev. 1.4 37

Si8640/41/42/45

12.3. Top Marking (16-Pin Narrow Body SOIC)

12.4. Top Marking Explanation (16-Pin Narrow Body SOIC)

Line 1 Marking: Base Part Number

Ordering Options

(See Ordering Guide for more

information).

Si86 = Isolator product series

XY = Channel Configuration

X = # of data channels (4 , 3, 2, 1)

Y = # of reverse channels (2, 1, 0)*

S = Speed Grade (max data rate) and operating mode:

A = 1 Mbps (default output = low)

B = 150 Mbps (default output = low)

D = 1 Mbps (default output = high)

E = 150 Mbp s (default output = high)

V = Insulation rating

A = 1 kV; B = 2.5 kV; C = 3. 75 kV

Line 2 Marking: Circle = 1.2 mm Diameter “e3” Pb-Free Symbol

YY = Year

WW = Work Week Assigned by th e Assembly House. Corresponds to the year

and work week of the mold date.

RTTTTT = Mfg Code Manufacturing code from assembly house

“R” indicates revision

Circle = 1.2 mm diameter “e3” Pb-Free Symbol.

*Note: Si8645 has 0 reverse channels.

Si86XYSV

YYWWRTTTTT

38 Rev. 1.4

Si8640/41/42/45

12.5. Top Marking (16-Pin QSOP)

12.6. Top Marking Explanation (16-Pin QSOP)

Line 1 Marking: Base Part Number

Ordering Options

(See Ordering Guide for more

information).

Si86 = Isolator product series

XY = Channel Configuration

X = # of data channels (4, 3, 2, 1)

Y = # of reverse channels (2, 1, 0)*

S = Speed Grade (max data rate) and operating mode:

A = 1 Mbps (default output = low)

B = 150 Mbps (default ou tp ut = low)

D = 1 Mbps (default output = high)

E = 150 Mbps (default ou tp ut = high)

V = Insulation rating

A=1kV; B=2.5kV; C=3.75kV

Line 2 Marking: Circle = 1.2 mm Diameter “e3” Pb-Free Symbol

YY = Year

WW = Work Week Assigned by the Assembly House. Correspo nds to the year

and work week of the mold date.

RTTTTT = Mfg Code Manufacturing code from assembly house

“R” indicates revision

Circle = 1.2 mm diameter “e3” Pb-Free Symbol.

*Note: Si8645 has 0 reverse channels.

Si86XYSV

YYWWRTTTTT

Rev. 1.4 39

Si8640/41/42/45

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

Added chip graphics on page 1.

Moved Tables 1 and 11 to page 17.

Updated Table 6, “Insulation and Safety-Related

Specifications,” on page 14.

Updated Table 8, “IEC 60747-5-2 Insulation

Characteristics for Si86xxxx*,” on page 15.

Moved Table 12 to page 20.

Moved Table 13 to page 21.

Moved “Typical Performance Characteristics” to

page 24.

Updated "4. Pin Descriptions" on page 25.

Updated "5. Ordering Guide" on page 26.

Revision 0.2 to Revision 1.0

Reordered spec tables to conform to new

convention.

Removed “pending” throughout document.

Revision 1.0 to Revision 1.1

Updated High Leve l Out pu t Voltage VOH to 3.1 V in

Table 3, “Electrical Characteristics,” on page 8.

Updated High Leve l Out pu t Voltage VOH to 2.3 V in

Table 4, “Electrical Characteristics,” on page 11.

Revision 1.1 to Revision 1.2

Updated Table 14, “Ordering Guide for Valid

OPNs1,2,” on page 26.

Updated Note 1 with MSL2A.

Updated Current Revision Devices.

Revision 1.2 to Revision 1.3

Updated "5. Ordering Guide" on page 26 to include

MSL2A.

Revision 1.3 to Revision 1.4

Updated Table 11 on page 17.

Added junction temperature spec.

Updated "3.3.1. Supply Bypass" on page 23.

Removed “3.3.2 Pin Connections” on page 23.

Updated "4. Pin Descriptions" on page 25.

Updated table notes.

Updated "5. Ordering Guide" on page 26.

Removed Rev A devices.

Updated "6. Package Outline: 16-Pin Wide Body

SOIC" on page 27.

Updated Top Marks.

Added revision description.

40 Rev. 1.4

Si8640/41/42/45

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