ADS1286
DESCRIPTION
The ADS1286 is a 12-bit, 20kHz analog-to-digital
converter with a differential input and sample and hold
amplifier and consumes only 250µA of supply cur-
rent. The ADS1286 offers an SPI and SSI compatible
serial interface for communications over a two or three
wire interface. The combination of a serial two wire
interface and micropower consumption makes the
ADS1286 ideal for remote applications and for those
requiring isolation.
The ADS1286 is available in a 8-pin plastic mini DIP
and a 8-lead SOIC.
12-Bit Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
®
FEATURES
●SERIAL INTERFACE
●GUARANTEED NO MISSING CODES
●20kHz SAMPLING RATE
●LOW SUPPLY CURRENT: 250µA
SAR Control
Serial
Interface
D
OUT
Comparator
S/H Amp CS/SHDN
DCLOCK
+In
V
REF
–In CDAC
ADS1286
ADS1286
APPLICATIONS
●REMOTE DATA ACQUISITION
●ISOLATED DATA ACQUISITION
●TRANSDUCER INTERFACE
●BATTERY OPERATED SYSTEMS
©1996 Burr-Brown Corporation PDS-1335B Printed in U.S.A. October, 1998
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
SBAS053
2
®
ADS1286
SPECIFICATIONS
At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, , fCLK = 16 • fSAMPLE, unless otherwise specified.
TIMING CHARACTERISTICS
fCLK = 200kHz, TA = TMIN to TMAX.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSMPL Analog Input Sample Time See Operating Sequence 1.5 2.0 Clk Cycles
tSMPL (MAX) Maximum Sampling Frequency ADS1286 20 kHz
tCONV Conversion Time See Operating Sequence 12 Clk Cycles
tdDO Delay TIme, DCLOCK↓ to DOUT Data Valid See Test Circuits 85 150 ns
tdis Delay TIme, CS↑ to DOUT Hi-Z See Test Circuits 25 50 ns
ten Delay TIme, DCLOCK↓ to DOUT Enable See Test Circuits 50 100 ns
thDO Output Data Remains Valid After DCLOCK↓CLOAD = 100pF 15 30 ns
tfDOUT Fall Time See Test Circuits 70 100 ns
trDOUT Rise Time See Test Circuits 60 100 ns
tCSD Delay Time, CS↓ to DCLOCK↓See Operating Sequence 0 ns
tSUCS Delay Time, CS↓ to DCLOCK↑See Operating Sequence 30 ns
ADS1286, ADS1286A ADS1286K, ADS1286B ADS1286C, ADS1286L
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Range +In – (–In) 0 VREF ✻✻✻✻V
Absolute Input Voltage +In –0.2 VCC +0.2 ✻✻✻✻V
–In –0.2 +0.2 ✻✻✻✻V
Capacitance 25 ✻✻pF
Leakage Current ±1✻✻µA
SYSTEM PERFORMANCE
Resolution 12 ✻✻Bits
No Missing Codes 12 ✻✻Bits
Integral Linearity ±1±2✻✻ ±0.5 ±1 LSB
Differential Linearity ±0.5 ±1.0 ✻±0.75 ±0.25 ±0.75 LSB
Offset Error 0.75 ±3✻✻ ✻✻LSB
Gain Error ±2±8✻✻ ✻✻LSB
Noise 50 ✻✻µVrms
Power Supply Rejection 82 ✻✻dB
SAMPLING DYNAMICS
Conversion Time 12 ✻✻
Clk Cycles
Acquisition Time 1.5 ✻✻
Clk Cycles
Small Signal Bandwidth 500 ✻✻kHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion VIN = 5.0Vp-p at 1kHz –85 ✻✻dB
VIN = 5.0Vp-p at 5kHz –83 ✻✻dB
SINAD VIN = 5.0Vp-p at 1kHz 72 ✻✻dB
Spurious Free Dynamic Range VIN = 5.0Vp-p at 1kHz 90 ✻✻dB
REFERENCE INPUT
REF Input Range 1.25 2.5
VCC+0.05V
✻✻✻✻✻✻V
Input Resistance CS = VCC 5000 ✻✻MΩ
CS = GND, fCLK = 0Hz 5000 ✻✻MΩ
Current Drain CS = VCC 0.01
2.5
✻✻ ✻✻µA
tCYC ≥ 640µs, fCLK ≤ 25kHz
2.4
20
✻✻ ✻✻µA
tCYC = 80µs, fCLK = 200kHz
2.4
20
✻✻ ✻✻µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻✻
Logic Levels:
VIH IIH = +5µA3 +V
CC ✻✻✻✻V
VIL IIL = +5µA 0.0 0.8 ✻✻✻✻V
VOH IOH = 250µA3 +V
CC ✻✻✻✻V
VOL IOL = 250µA 0.0 0.4 ✻✻✻✻V
Data Format Straight Binary ✻✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
VCC +4.50 5 5.25 ✻✻✻✻✻✻V
Quiescent Current, VANA
tCYC ≥ 640µS, fCLK ≤ 25kHz
200 400 ✻✻ ✻✻µA
tCYC = 90µS, fCLK = 200kHz
250 500 ✻✻ ✻✻µA
Power Down CS = VCC 3✻✻µA
TEMPERATURE RANGE
Specified Performance ADS1286, K, L 0 +70 ✻✻✻✻°C
ADS1286A, B, C –40 +85 ✻✻✻✻°C
✻ Specifications same as grade to the left.
3
®
ADS1286
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
+VCC .....................................................................................................+6V
Analog Input.......................................................–0.3V to (+VCC + 300mV)
Logic Input .........................................................–0.3V to (+VCC + 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
NOTE: (1) Stresses above these ratings may permanently damage the device.
PIN CONFIGURATION
1
2
3
4
8
7
6
5
+V
CC
DCLOCK
D
OUT
CS/SHDN
V
REF
+In
–In
GND
ADS1286
8-Pin Mini PDIP
8-Lead SOIC
PIN ASSIGNMENTS
PIN NAME DESCRIPTION
1V
REF Reference Input.
2 +In Non Inverting Input.
3 –In Inverting Input. Connect to ground or remote ground sense point.
4 GND Ground.
5 CS/SHDN Chip Select when low, Shutdown Mode when high.
6D
OUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed.
8+V
CC Power Supply.
PACKAGE
INTEGRAL TEMPERATURE DRAWING
PRODUCT LINEARITY RANGE PACKAGE NUMBER(1)
ADS1286P ±20°C to +70°C Plastic DIP 006
ADS1286PK ±20°C to +70°C Plastic DIP 006
ADS1286PL ±10°C to +70°C Plastic DIP 006
ADS1286U ±20°C to +70°C SOIC 182
ADS1286UK ±20°C to +70°C SOIC 182
ADS1286UL ±10°C to +70°C SOIC 182
ADS1286PA ±2 –40°C to +85°C Plastic DIP 006
ADS1286PB ±2 –40°C to +85°C Plastic DIP 006
ADS1286PC ±1 –40°C to +85°C Plastic DIP 006
ADS1286UA ±2 –40°C to +85°C SOIC 182
ADS1286UB ±2 –40°C to +85°C SOIC 182
ADS1286UC ±1 –40°C to +85°C SOIC 182
PACKAGE/ORDERING INFORMATION
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix
C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
4
®
ADS1286
TYPICAL PERFORMANCE CURVES
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
REFERENCE CURRENT vs TEMPERATURE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Reference Current (µA)
–55 –40 –25 0 25 70 85
Temperature (°C)
CHANGE IN OFFSET vs REFERENCE VOLTAGE
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Change in Offset (LSB)
12345
Reference Voltage (V)
CHANGE IN OFFSET vs TEMPERATURE
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Delta from 25°C (LSB)
–55 –40 –25 0 25 70 85
Temperature (°C)
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
0.10
0.05
0.00
–0.05
–0.10
–0.15
–0.20
Delta from +5V Reference (LSB)
12345
Reference Voltage (V)
Change in Differential
Linearity (LSB)
Change in Integral
Linearity (LSB)
CHANGE IN GAIN vs REFERENCE VOLTAGE
4
3.5
3
2.5
2
1.5
1
0.5
0
Change in Gain (LSB)
12345
Reference Voltage (V)
REFERENCE CURRENT vs SAMPLE RATE
2.5
2.0
1.5
1.0
0.5
0
Reference Current (µA)
024681012
Sample Rate (kHz)
5
®
ADS1286
DIFFERENTIAL LINEARITY ERROR vs CODE
3.0
2.0
1.0
0
–1.0
–2.0
–3.0
Differential Linearity Error (LSB)
0 2048 4095
Code
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
12
11.75
11.5
11.25
11
10.75
10.5
10.25
10
Effective Number of Bits (rms)
0.1 1 10
Reference Voltage (V)
SPURIOUS FREE DYNAMIC RANGE
AND SIGNAL-TO-NOISE RATIO vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
Spurious Free Dynamic Range
and Signal-to-Noise Ratio (dB)
0.1 1 10
Frequency (kHz)
Spurious Free Dynamic Range
Signal-to-Noise Ratio
TOTAL HARMONIC DISTORTION vs FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Total Harmonic Distortion (dB)
0.1 1 10
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION)
vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
Signal-to-(Noise + Distortion) (dB)
0.1 1 10
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
80
70
60
50
40
30
20
10
0
Signal-to-(Noise + Distortion) (dB)
–40 –35 –30 –25 –20 –15 –10 –5 0
Input Level (dB)
6
®
ADS1286
4096 POINT FFT
0
–25
–50
–75
–100
–125
Magnitude (dB)
0246
Frequency (kHz)
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
Peak-to-Peak Noise (LSB)
0.1 1 10
Reference Voltage (V)
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
Power Supply Rejection (dB)
1 10 100 1000 10000
Ripple Frequency (kHz)
VRIPPLE = 20mV
CHANGE GAIN vs TEMPERATURE
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
Delta from 25°C (LSB)
–55 –40 –25 0 25 70 85
Temperature (°C)
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
3
2.5
2
1.5
1
0.5
0
Supply Current (µA)
–55 –40 –25 0 25 70 85
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
400
350
300
250
200
150
100
Supply Current (µA)
–55 –40 –25 0 25 70 85
Temperature (°C)
f
SAMPLE
= 1.6kHz
f
SAMPLE
= 12.5kHz
7
®
ADS1286
INTEGRAL LINEARITY ERROR vs CODE
3.0
2.0
1.0
0
–1.0
–2.0
–3.0
Integral Linearity Error (LSB)
0 2048 4095
Code
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
DIGITAL INPUT LINE THRESHOLD
vs SUPPLY VOLTAGE
3
2.5
2
1.5
1
0.5
0
Digital Input Threshold Voltage (V)
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Supply Voltage (V)
INPUT LEAKAGE CURRENT vs TEMPERATURE
10
1
0.1
0.01
Leakage Current (nA)
–55 –40 –25 0 25 70 85
Temperature (°C)
8
®
ADS1286
TIMING DIAGRAMS AND TEST CIRCUITS
D
OUT
1.4V
Test Point
3kΩ
100pF
C
LOAD
t
r
D
OUT
V
OH
V
OL
t
f
t
dDO
t
hDO
D
OUT
DCLOCK
V
OH
V
OL
V
IL
D
OUT
Test Point
t
dis
Waveform 2, t
en
t
dis
Waveform 1
100pF
C
LOAD
3kΩ
t
dis
CS/SHDN
D
OUT
Waveform 1
(1)
D
OUT
Waveform 2
(2)
90%
10%
V
IH
1
B11
2
t
en
CS/SHDN
DCLOCK
V
OL
D
OUT
V
CC
Load Circuit for tdDO, tr, and tfVoltage Waveforms for DOUT Rise and Fall Times tr, and tf
Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden
Voltage Waveforms for ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
9
®
ADS1286
CS/SHDN
DOUT
DCLOCK
tDATA
tSUCS
tCSD
tCYC
tCONV
POWER
DOWN
tSMPL
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
B11
(MSB)B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
NULL
BIT
HI-ZHI-Z B11 B10 B9 B8
NULL
BIT
CS/SHDN
DOUT
DCLOCK
tCONV tDATA
tSUCS
tCYC
POWER DOWN
tSMPL
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
B11
(MSB)B10 B9 B8 B7 B6 B5 B4 B4B3 B3B2 B2B1 B1B0
NULL
BIT
HI-Z HI-Z
B5 B6 B7 B8 B9 B10 B11
(2)
tCSD
leaving the DCLOCK running to clock out the LSB first
data or zeroes. If the CS input is not running rail-to-rail, the
input logic buffer will draw current. This current may be
large compared to the typical supply current. To obtain the
lowest supply current, bring the CS pin to ground when it is
low and to supply voltage when it is high.
SERIAL INTERFACE
The ADS1286 communicates with microprocessors and other
external digital systems via a synchronous 3-wire serial inter-
face. DCLOCK synchronizes the data transfer with each bit
being transmitted on the falling DCLOCK edge and captured
on the rising DCLOCK edge in the receiving system. A falling
CS initiates data transfer as shown in Figure 1. After CS falls,
the second DCLOCK pulse enables DOUT. After one null bit,
the A/D conversion result is output on the DOUT line. Bringing
CS high resets the ADS1286 for the next data exchange.
MICROPOWER OPERA TION
With typical operating currents of 250µA and automatic
shutdown between conversions, the ADS1286 achieves ex-
tremely low power consumption over a wide range of
sample rates (see Figure 2). The auto-shutdown allows the
supply current to drop with sample rate.
SHUTDOWN
The ADS1286 is equipped with automatic shutdown fea-
tures. The device draws power when the CS pin is LOW and
shuts down completely when the pin is HIGH. The bias
circuit and comparator powers down and the reference input
becomes high impedance at the end of each conversion
1000
100
10
1
Supply Current (µA)
0.1k 1k 10k 100k
Sample Rate (kHz)
T
A
= 25°C
V
CC
= 5V
V
REF
= 5V
f
CLK
= 16 • f
SAMPLE
FIGURE 2. Automatic Power Shutdown Between Conver-
sions Allows Power Consumption to Drop with
Sample Rate.
FIGURE 1. ADS1286 Operating Sequence.
10
®
ADS1286
MINIMIZING POWER DISSIPATION
In systems that have significant time between conversions,
the lowest power drain will occur with the minimum CS
LOW time. Bringing CS LOW, transferring data as quickly
as possible, and then bringing it back HIGH will result in the
lowest current drain. This minimizes the amount of time the
device draws power. After a conversion the A/D automati-
cally shuts down even if CS is held LOW. If the clock is left
running to clock out LSB-data or zero, the logic will draw a
small amount of current (see Figure 3).
REDUCED REFERENCE
OPERATION
The effective resolution of the ADS1286 can be increased
by reducing the input span of the converter. The ADS1286
exhibits good linearity and gain over a wide range of
reference voltages (see Typical Performance Curves “ Change
in Linearity vs Reference Voltage” and “Change in Gain vs
Reference Voltage”). However, care must be taken when
operating at low values of VREF because of the reduced LSB
size and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low VREF values:
1. Offset
2. Noise
OFFSET WITH REDUCED VREF
The offset of the ADS1286 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The Typical Performance Curve “Change in
Offset vs Reference Voltage” shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example, a VOS of 122µV which is 0.1 LSB with a 5V
reference becomes 0.5LSB with a 1V reference and 2.5LSBs
with a 0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the negative input of the ADS1286.
NOISE WITH REDUCED VREF
The total input referred noise of the ADS1286 can be
reduced to approximately 200µV peak-to-peak using a ground
plane, good bypassing, good layout techniques and minimiz-
ing noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of an
LSB as the size of the LSB is reduced.
For operation with a 5V reference, the 200µV noise is only
0.15LSB peak-to-peak. In this case, the ADS1286 noise will
contribute virtually no uncertainty to the output code. How-
ever, for reduced references, the noise may become a signifi-
cant fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 2.5V reference this same
200µV noise is 0.3LSB peak-to-peak. If the reference is
further reduced to 1V, the 200µV noise becomes equal to
0.8LSBs and a stable code may be difficult to achieve. In
this case averaging multiple readings may be necessary.
FIGURE 3. Shutdown Current with CS HIGH is Lower than
with CS LOW.
RC INPUT FILTERING
It is possible to filter the inputs with an RC network as
shown in Figure 4. For large values of CFILTER (e.g., 1µF),
the capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops across
the resistor. The magnitude of the DC current is approxi-
mately IDC = 20pF x VIN/tCYC and is roughly proportional to
VIN. When running at the minimum cycle time of 64µs, the
input current equals 1.56µA at VIN = 5V. In this case, a filter
resistor of 75Ω will cause 0.1LSB of full-scale error. If a
larger filter resistor must be used, errors can be eliminated
by increasing the cycle time.
FIGURE 4. RC Input Filtering.
R
FILTER
I
DC
ADS1286
C
FILTER
V
IN
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Supply Current (µA)
0.1 1 10 100
Sample Rate (kHz)
T
A
= 25°C
V
CC
= +5V
V
REF
= +5V
f
CLK
= 16 • f
SAMPLE
CS = LOW
(GND)
CS HIGH
(V
CC
)
11
®
ADS1286
ADS1286
µP
DCLOCK
D
OUT
CS/SHDN A
0
A
1
U
3
U
4
U
1
U
2
Thermocouple
ISO Thermal Block
MUX
OPA237 0.3V
0.4V
0.2V
0.1V
+5V
R
2
59kΩ
R
4
1kΩ
R
3
500kΩ
R
5
500Ω
R
7
10Ω
C
3
0.1µF
C
4
10µF C
5
0.1µF
R
6
1MΩ
R
1
150kΩ
D
1
TC
2
TC
1
TC
3
+5V
C
2
0.1µF C
1
10µF
+5V R
8
46kΩ
R
9
1kΩ
R
10
1kΩ
R
11
1kΩ
R
12
1kΩ
V
REF
3-Wire
Interface
FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286.
ADS1286
REF200
(100µA)
µP
D
OUT
RTD
DCLOCK
CS/SHDN
+V
CC
V
REF
81
2
34
0.1µF
FIGURE 6. ADS1286 with RTD Sensor.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS1286P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PA ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PAG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PC ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PCG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PK ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PKG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PL ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286PLG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1286U ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UA ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UAG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS1286UB ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UBG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UC ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS1286UCG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS1286UG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UK ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UKG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UL ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UL/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286UL/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1286ULG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1286U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS1286UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS1286UL/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1286U/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS1286UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS1286UL/2K5 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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