74LVC823APW,112 - NEXPERIA - Datasheet.Technology

74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs;

positive edge-trigger; 3-state

Rev. 5 — 1 May 2019 Product data sheet

1. General description

The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE),

master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops

stores the state of their individual D-inputs that meet the set-up and hold times requirements on the

LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their

data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops

are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied

to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V

applications.

2. Features and benefits

•5 V tolerant inputs/outputs for interfacing with 5 V logic

•Wide supply voltage range from 1.2 V to 3.6 V

•CMOS low power consumption

•Direct interface with TTL levels

•Flow-through pinout architecture

•9-bit positive edge-triggered register

•Independent register and 3-state buffer operation

•Complies with JEDEC standard:

•JESD8-7A (1.65 V to 1.95 V)

•JESD8-5A (2.3 V to 2.7 V)

•JESD8-C/JESD36 (2.7 V to 3.6 V)

•ESD protection:

•HBM JESD22-A114F exceeds 2000 V

•MM JESD22-A115-B exceeds 200 V

•CDM JESD22-C101E exceeds 1000 V

•Specified from -40 °C to +85 °C and -40 °C to +125 °C.

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74LVC823AD -40 °C to +125 °C SO24 plastic small outline package; 24 leads;

body width 7.5 mm

SOT137-1

74LVC823APW -40 °C to +125 °C TSSOP24 plastic thin shrink small outline package;

24 leads; body width 4.4 mm

SOT355-1

74LVC823ABQ -40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

24 terminals; body 3.5 × 5.5 × 0.85 mm

SOT815-1

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

4. Functional diagram

001aaa849

FF0

FF8

3-STATE

OUTPUTS

D8 Q8

Fig. 1. Functional diagram

001aaa847

Q8 15

Fig. 2. Logic symbol

001aaa848

14 G1

2D 23

169

1510

13 1C2

11 R

1EN

Fig. 3. IEC logic symbol

Product data sheet Rev. 5 — 1 May 2019 2 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

001aaa850

FF0

FF1

FF2

FF3

FF4

FF5

FF6

FF8

FF7

R R R R R

R R RR

Fig. 4. Logic diagram

Product data sheet Rev. 5 — 1 May 2019 3 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

5. Pinning information

5.1. Pinning

74LVC823A

OE VCC

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

D8 Q8

MR CE

GND CP

001aaa845

Fig. 5. Pin configuration SO24 (SOT137-1) and

TSSOP24 (SOT355-1)

001aaa846

74LVC823A

Transparent top view

D7 Q7

D6 Q6

D5 Q5

D4 Q4

D3 Q3

D2 Q2

D1 Q1

D0 Q0

GND

11 14

10 15

9 16

8 17

7 18

6 19

5 20

4 21

3 22

2 23

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 6. Pin configuration SOT815-1 (DHVQFN24)

5.2. Pin description

Table 2. Pin description

Pin Name Description

OE 1 output enable input (active LOW)

MR 11 master reset input (active LOW)

D0, D1, D2, D3, D4, D5, D6, D7, D8 2, 3, 4, 5, 6, 7, 8, 9, 10 data input

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 23, 22, 21, 20, 19, 18, 17, 16, 15 3-state flip-flop output

CP 13 clock input (LOW to HIGH;

edge-triggered)

CE 14 clock enable input (active LOW)

GND 12 ground (0 V)

VCC 24 supply voltage

Product data sheet Rev. 5 — 1 May 2019 4 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition

↑ = LOW to HIGH level transition

Z = high-impedance OFF-state; X = don’t care; NC = no change

Input OutputOperating mode

OE MR CE CP Dn

Internal

flip-flop Qn

Clear L L X X X L L

L H L ↑ l L LLoad and read register

L H L ↑ h H H

H H L ↑ l L ZLoad register and

disable outputs H H L ↑ h H Z

Hold L H H NC X NC NC

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +6.5 V

IIK input clamping current VI < 0 V -50 - mA

VIinput voltage [1] -0.5 +6.5 V

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

HIGH or LOW state [2] -0.5 VCC + 0.5 VVOoutput voltage

3-state [2] -0.5 +6.5 V

IOoutput current VO = 0 V to VCC - ±50 mA

ICC supply current - 100 mA

IGND ground current -100 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [3] - 500 mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SO24 packages: Ptot derates linearly with 8 mW/K above 70 °C.

For TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.

For DHVQFN24 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.

Product data sheet Rev. 5 — 1 May 2019 5 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

1.65 - 3.6 VVCC supply voltage

functional 1.2 - - V

VIinput voltage 0 - 5.5 V

HIGH or LOW state 0 - VCC VVOoutput voltage

3-state 0 - 5.5 V

Tamb ambient temperature in free air -40 - +125 °C

VCC = 1.65 V to 2.7 V 0 - 20 ns/VΔt/ΔV input transition rise and fall rate

VCC = 2.7 V to 3.6 V 0 - 10 ns/V

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ [1] Max Min Max

Unit

VCC = 1.2 V 1.08 - - 1.08 - V

VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC - V

VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V

VIH HIGH-level

input voltage

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VCC = 1.2 V - - 0.12 - 0.12 V

VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V

VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V

VIL LOW-level input

voltage

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VI = VIH or VIL

IO = -100 μA;

VCC = 1.65 V to 3.6 V

VCC - 0.2 - - VCC - 0.3 - V

IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V

IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V

IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V

IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V

VOH HIGH-level

output voltage

IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V

VI = VIH or VIL

IO = 100 μA;

VCC = 1.65 V to 3.6 V

- - 0.2 - 0.3 V

IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V

IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V

IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V

VOL LOW-level

output voltage

IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V

IIinput leakage

current

VCC = 3.6 V; VI = 5.5 V or GND - ±0.1 ±5 - ±20 μA

IOZ OFF-state

output current

VI = VIH or VIL; VCC = 3.6 V;

VO = 5.5 V or GND

- 0.1 ±5 - ±20 μA

Product data sheet Rev. 5 — 1 May 2019 6 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ [1] Max Min Max

Unit

IOFF power-off

leakage current

VCC = 0 V; VI or VO = 5.5 V - 0.1 ±10 - ±20 μA

ICC supply current VCC = 3.6 V; VI = VCC or GND;

IO = 0 A

- 0.1 10 - 40 μA

ΔICC additional

supply current

per input pin; VCC = 2.7 V to 3.6 V;

VI = VCC - 0.6 V; IO = 0 A

- 5 500 - 5000 μA

CIinput

capacitance

VCC = 0 V to 3.6 V;

VI = GND to VCC

- 5.0 - - - pF

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 11.

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ [1] Max Min Max

Unit

CP to Qn; see Fig. 7 [2]

VCC = 1.2 V - 20 - - - ns

VCC = 1.65 V to 1.95 V 2.4 8.4 18.7 2.4 21.5 ns

VCC = 2.3 V to 2.7 V 1.7 4.4 9.6 1.7 11.1 ns

VCC = 2.7 V 1.5 4.1 8.9 1.5 11.5 ns

tpd propagation

delay

VCC = 3.0 V to 3.6 V 1.5 3.7 8.0 1.5 10.0 ns

MR to Qn; see Fig. 9

VCC = 1.2 V - 15 - - - ns

VCC = 1.65 V to 1.95 V 2.1 9.5 21.4 2.1 24.7 ns

VCC = 2.3 V to 2.7 V 1.5 4.9 10.5 1.5 12.1 ns

VCC = 2.7 V 1.5 4.7 8.8 1.5 11.0 ns

tPHL HIGH to LOW

propagation

delay

VCC = 3.0 V to 3.6 V 1.5 4.1 7.9 1.5 10.0 ns

OE to Qn; see Fig. 10 [2]

VCC = 1.2 V - 18 - - - ns

VCC = 1.65 V to 1.95 V 1.7 7.4 16.5 1.7 19.0 ns

VCC = 2.3 V to 2.7 V 1.5 4.2 9.1 1.5 10.5 ns

VCC = 2.7 V 1.5 4.3 8.3 1.5 10.5 ns

ten enable time

VCC = 3.0 V to 3.6 V 1.5 3.4 7.2 1.5 9.0 ns

OE to Qn; see Fig. 10 [2]

VCC = 1.2 V - 8.0 - - - ns

VCC = 1.65 V to 1.95 V 2.3 4.2 10.0 2.3 11.5 ns

VCC = 2.3 V to 2.7 V 1.0 2.3 5.6 1.0 6.5 ns

VCC = 2.7 V 1.5 3.2 7.1 1.5 9.0 ns

tdis disable time

VCC = 3.0 V to 3.6 V 1.5 2.9 6.0 1.5 7.5 ns

Product data sheet Rev. 5 — 1 May 2019 7 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ [1] Max Min Max

Unit

CP HIGH or LOW; see Fig. 7

VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns

VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns

VCC = 2.7 V 3.3 - - 3.3 - ns

VCC = 3.0 V to 3.6 V 3.3 1.7 - 3.3 - ns

MR HIGH or LOW; see Fig. 9

VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns

VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns

VCC = 2.7 V 3.3 - - 3.3 - ns

tWpulse width

VCC = 3.0 V to 3.6 V 3.3 1.7 - 3.3 - ns

Dn to CP; see Fig. 8

VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns

VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns

VCC = 2.7 V 1.0 - - 1.0 - ns

VCC = 3.0 V to 3.6 V +1.8 -0.8 - +1.8 - ns

CE to CP; see Fig. 8

VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns

VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns

VCC = 2.7 V 1.8 - - 1.8 - ns

tsu set-up time

VCC = 3.0 V to 3.6 V 1.3 0.0 - 1.3 - ns

MR; see Fig. 9

VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns

VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns

VCC = 2.7 V 2.0 - - 2.0 - ns

trec recovery time

VCC = 3.0 V to 3.6 V +1.0 -0.5 - +1.0 - ns

Dn to CP; see Fig. 8

VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns

VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns

VCC = 2.7 V 2.0 - - 2.0 - ns

VCC = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns

CE to CP; see Fig. 8

VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns

VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns

VCC = 2.7 V 1.3 - - 1.3 - ns

thhold time

VCC = 3.0 V to 3.6 V 1.3 0.0 - 1.3 - ns

CP; see Fig. 7

VCC = 1.65 V to 1.95 V 100 - - 80 - MHz

VCC = 2.3 V to 2.7 V 125 - - 100 - MHz

VCC = 2.7 V 150 - - 120 - MHz

fmax maximum

frequency

VCC = 3.0 V to 3.6 V 150 200 - 120 - MHz

tsk(o) output skew

time

Qn; VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns

Product data sheet Rev. 5 — 1 May 2019 8 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ [1] Max Min Max

Unit

per input; VI = GND to VCC [4]

VCC = 1.65 V to 1.95 V - 12.4 - - - pF

VCC = 2.3 V to 2.7 V - 14.5 - - - pF

CPD power

dissipation

capacitance

VCC = 3.0 V to 3.6 V - 16.4 - - - pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL.

ten is the same as tPZL and tPZH.

tdis is the same as tPLZ and tPHZ.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC

2 × fi × N + Σ(CL × VCC

2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL × VCC

2 × fo) = sum of the outputs

10.1. Waveforms and test circuit

mna894

CP input

Qn output

tPHL tPLH

1/fmax

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 7. Clock to output propagation delays, clock pulse width, and maximum frequency

Product data sheet Rev. 5 — 1 May 2019 9 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

001aaa851

GND

tsu

VOH

VOL

Qn output

CP input

Dn, CE input

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predicable output performance.

Fig. 8. Data set-up and hold times for data and clock enable inputs to clock input

001aaa852

GND

trec

VOH

VOL

Qn output

CP input

MR input VMVM

tPHL

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 9. Master reset pulse width, master reset to clock removal time and master reset to output propagation delay

Product data sheet Rev. 5 — 1 May 2019 10 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

mgu775

tPLZ

tPHZ

outputs

disabled

outputs

enabled

outputs

enabled

Qn output

LOW-to-OFF

OFF-to-LOW

Qn output

HIGH-to-OFF

OFF-to-HIGH

OE input

VOL

VOH

VCC

VMVM

GND

tPZL

tPZH

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage drops that occur with the output load.

Fig. 10. 3-state outputs enable and disable times

Table 8. Measurement points

Supply voltage Input Output

VCC VIVMVMVXVY

1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V

1.65 V to 1.95 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V

2.3 V to 2.7 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V

2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

Product data sheet Rev. 5 — 1 May 2019 11 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aae331

VEXT

VCC

VIVO

DUT

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig. 11. Test circuit for measuring switching times

Table 9. Test data

Input Load VEXT

Supply voltage

VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND

1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND

2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND

Product data sheet Rev. 5 — 1 May 2019 12 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

11. Package outline

UNIT A

max. A

1 A

2 A

3 b

p c D

(1) E

(1) (1)

e H

E L L

p Q Z

y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4 1.27 10.65

10.00

1.1

1.0

0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT137-1

w M

detail X

v M A

(A )

0.25

075E05 MS-013

pin 1 index

0.1 0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.61

0.60

0.30

0.29 0.05

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

99-12-27

03-02-19

Fig. 12. Package outline SOT137-1 (SO24)

Product data sheet Rev. 5 — 1 May 2019 13 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

UNIT A

1 A

2 A

3 b

p c D

(1) E

(2) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.13 0.1 0.2 1

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

w M

1 12

24 13

pin 1 index

detail X

(A )

v M A

A D

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Fig. 13. Package outline SOT355-1 (TSSOP24)

Product data sheet Rev. 5 — 1 May 2019 14 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

SOT815-1 - - - - - - - - - 03-04-29

SOT815-1

0 2.5 5 mm

scale

b y

y1 C

A C

v M

w M

terminal 1

index area

terminal 1

index area

UNIT A(1)

max. A1 b c e Eh L e1 y w v

mm 1 0.05

0.00

0.30

0.18 0.5 4.5

1.5 0.2 2.25

1.95

4.25

3.95 0.05 0.05

0.1 0.1

DIMENSIONS (mm are the original dimensions)

0.5

0.3

D(1)

5.6

5.4

E(1)

3.6

3.4

B A

DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;

no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm

A A1

detail X

Fig. 14. Package outline SOT815-1 (DHVQFN24)

Product data sheet Rev. 5 — 1 May 2019 15 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC823A v.5 20190501 Product data sheet - 74LVC823A v.4

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Type number 74LVC823ADB (SOT340-1) removed.

74LVC823A v.4 20130408 Product data sheet - 74LVC823A v.3

Modifications: •Features corrected (errata).

74LVC823A v.3 20130327 Product data sheet - 74LVC823A v.2

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage

ranges.

74LVC823A v.2 20040510 Product specification - 74LVC823A v.1

74LVC823A v.1 19980924 Product specification - -

Product data sheet Rev. 5 — 1 May 2019 16 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 5 — 1 May 2019 17 / 18

Nexperia 74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

Contents

1. General description...................................................... 1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................4

5.1. Pinning.........................................................................4

5.2. Pin description............................................................. 4

6. Functional description................................................. 5

7. Limiting values............................................................. 5

8. Recommended operating conditions..........................6

9. Static characteristics....................................................6

10. Dynamic characteristics............................................ 7

10.1. Waveforms and test circuit........................................ 9

11. Package outline........................................................ 13

12. Abbreviations............................................................ 16

13. Revision history........................................................16

14. Legal information......................................................17

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 1 May 2019

Product data sheet Rev. 5 — 1 May 2019 18 / 18