Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DHigh-Performance Static CMOS Technology
DIncludes the T320C2xLP Core CPU
– Object Compatible With the TMS320C2xx
– Source Code Compatible With
TMS320C25
– Upwardly Compatible With TMS320C5x
– 132-Pin Plastic Quad Flat Package
(PQ Suffix)
– 50-ns Instruction Cycle Time
DIndustrial and Automotive Temperature
Available
DMemory
– 544 Words × 16 Bits of On-Chip
Data/Program Dual-Access RAM
– 16K Words × 16 Bits of On-Chip Program
Flash EEPROM
– 224K Words × 16 Bits of Total Memory
Address Reach (64K Data, 64K Program
and 64K I/O, and 32K Global Memory
Space)
DEvent-Manager Module
– 12 Compare/Pulse-Width Modulation
(PWM) Channels
– Three 16-Bit General-Purpose Timers
With Six Modes, Including Continuous
Upand Up/Down Counting
– Three 16-Bit Full-Compare Units With
Deadband
– Three 16-Bit Simple-Compare Units
– Four Capture Units (Two With
Quadrature Encoder-Pulse Interface
Capability)
DDual 10-Bit Analog-to-Digital Conversion
Module
D28 Individually Programmable, Multiplexed
I/O Pins
DPhase-Locked-Loop (PLL)-Based Clock
Module
DWatchdog Timer Module (With Real-Time
Interrupt)
DSerial Communications Interface (SCI)
Module
DSerial Peripheral Interface (SPI) Module
DSix External Interrupts (Power Drive
Protect, Reset, NMI, and Three Maskable
Interrupts)
DFour Power-Down Modes for Low-Power
Operation
DScan-Based Emulation
DDevelopment Tools Available:
– Texas Instruments (TI) ANSI
C Compiler, Assembler/Linker, and
C-Source Debugger
– Scan-Based Self-Emulation (XDS510)
– Third-Party Digital Motor Control and
Fuzzy-Logic Development Support
description
The TMS320F240 (F240) device is a member of a family of DSP controllers based on the TMS320C2xx
generation of 16-bit fixed-point digital signal processors (DSPs). This family is optimized for digital motor/motion
control applications. The DSP controllers combine the enhanced TMS320 architectural design of the C2xLP
core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized
for motor/motion control applications. These peripherals include the event manager module, which provides
general-purpose timers and compare registers to generate up to 12 PWM outputs, and a dual10-bit
analog-to-digital converter (ADC), which can perform two simultaneous conversions within 6.1 µs. See the
functional block diagram.
Copyright 2002, Texas Instruments Incorporated
XDS510 is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Description 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PQ Package (Top View) 4. . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram 11. . . . . . . . . . . . . . . . . . . . . . .
Architectural Overview 12. . . . . . . . . . . . . . . . . . . . . . . . . .
System-Level Functions 12. . . . . . . . . . . . . . . . . . . . . . . . .
Device Memory Map 12. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory Map 14. . . . . . . . . . . . . . . . . . . . . . . .
Digital I/O and Shared Pin Functions 15. . . . . . . . . . . . .
Digital I/O Control Registers 17. . . . . . . . . . . . . . . . . . . .
Device Reset and Interrupts 17. . . . . . . . . . . . . . . . . . . .
Clock Generation 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes 28. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram of the
TMS320F240 DSP CPU 29. . . . . . . . . . . . . . . . . . . . .
F240 DSP Core CPU 32. . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Memory 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Interface 38. . . . . . . . . . . . . . . . . . . . .
Event-Manager (EV) Module 39. . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) Module 42. . . . . . . .
Serial Peripheral Interface (SPI) Module 44. . . . . . . . . .
Serial Communications Interface (SCI) Module 46. . . .
Watchdog (WD) and Real-Time
Interrupt (RTI) Module 48. . . . . . . . . . . . . . . . . . . . .
Scan-Based Emulation 50. . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320F240 Instruction Set 50. . . . . . . . . . . . . . . . . . . . .
Development Support 57. . . . . . . . . . . . . . . . . . . . . . . . . . .
Device and Development-Support Tool Nomenclature 58
Documentation Support 59. . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 60. . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 60. . . . . . . . . . . . .
Electrical Characteristics Over Recommended
Operating Free-Air Temperature Range 61. . . . . . . .
Register File Compilation 96. . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
REVISION HISTORY
REVISION DATE PRODUCT STATUS HIGHLIGHTS
Removed TMS320C240 as it is an obsolete device.
Updated descriptions of the following pins in the Terminal Functions
table:
–PWM1/CMP1–PWM6/CMP6
–OSCBYP
–TRST
Updated the following figures:
–Figure 3, Shared Pin Configuration
–Figure 6, System Module Interrupt Structure
–Figure 12, Analog-to-Digital Converter Module
–Figure 16, TMS320 Device Nomenclature
–Figure 20, Recommended Crystal/Clock Connection
ENovember 2002 Production Data
Added the following figures:
–Figure 31, Case With Crystal
–Figure 32, Case With External Oscillator
Updated the following tables:
–Table 15, Development Support Tools
–Table 16, TMS320F240-Specific Development Tools
–Table 20, Register File Compilation
[ADCTRL1 and ADCTRL2]
Updated the following sections:
–Low-Power Modes
–Flash EEPROM
–Capture Unit
–Analog-to-Digital Converter (ADC) Module
[Digital Value equation]
–Development Support
–External Reference Crystal With PLL-Circuit-Enabled Clock
Option
–10-Bit Dual Analog-to-Digital Converter (ADC)
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PQ PACKAGE
(TOP VIEW)
WE
W/R
D7
D8
VSS
DVDD
D9
D10
D11
D12
D13
D14
D15
VSS
TCK
TDI
TRST
TMS
TDO
RS
READY
MP/MC
EMU0
EMU1/OFF
NMI
PORESET
RESERVED
SCIRXD/IO
SCITXD/IO
SPISIMO/IO
VSS
DVDD
SPISOMI/IO
SPICLK/IO
VCCP/WDDIS
D5
D4
D3
D6
D2
STRB
BR
R/W
V
DV
PS
D1
SS
DD
A5
A4
A3
VSS
A2
A1
A0
TMRCLK/IOPB7
TMRDIR/IOPB6
T3PWM/T3CMP/IOPB5
T2PWM/T2CMP/IOPB4
T1PWM/T1CMP/IOPB3
VSS
DVDD
PWM9/CMP9/IOPB2
PWM8/CMP8/IOPB1
PWM7/CMP7/IOPB0
PWM6/CMP6
PWM5/CMP5
PWM4/CMP4
PWM3/CMP3
PWM2/CMP2
PWM1/CMP1
DVDD
VSS
ADCIN8/IOPA3
ADCIN9/IOPA2
ADCIN10
ADCIN11
VSSA
VREFLO
VREFHI
VCCA
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
10
8
6
7
VSS
D0
CVSS
CVDD
IS
DS
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
VSS
58
52
53
54
55
51
56
59
60
67
62
63
61
64
69
57
68
65
66
70
71
72
73
74
75
76
77
78
79
80
81
82
83
9
11
12
13
14
15
16
17
1
131
129
130
132
2
3
4
5
124
122
120
121
123
125
126
127
128
119
117
118
XTAL1/CLKIN
XTAL2
OSCBYP
XINT3/IO
XINT2/IO
XINT1
SPISTE/IO
C
AP1/QEP1/IOPC4
CAP3/IOPC6
CAP4/IOPC7
C
AP2/QEP2/IOPC5
BIO/IOPC3
XF/IOPC2
CLKOUT/IOPC1
ADCSOC/IOPC0
ADCIN5
ADCIN7
ADCIN15
ADCIN6
ADCIN4
ADCIN3
ADCIN1/IOPA1
ADCIN0/IOPA0
ADCIN14
ADCIN12
ADCIN13
ADCIN2
VSS
VSS
VSS
PDPINT
DVDD
DVDD
DVDD
CVDD
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Terminal Functions
TERMINAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
EXTERNAL INTERFACE DATA/ADDRESS SIGNALS
A0 (LSB)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15 (MSB)
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
O/Z
Parallel address bus A0 [least significant bit (LSB)] through A15 [most significant bit (MSB)]. A 1 5–A0
are multiplexed to address external data/program memory or I/O. A15–A0 are placed in
high-impedance state when EMU1/OFF is active low and hold their previous states in power-down
modes.
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
I/O/Z
Parallel d a t a bus D0 (LSB) through D15 (MSB). D15–D0 are multiplexed to transfer data between the
TMS320F240 and external data/program memory and I/O space (devices). D15–D0 are placed in the
high-impedance state when not outputting, when in power-down mode, when reset (RS) is asserted,
or when EMU1/OFF is active low.
EXTERNAL INTERFACE CONTROL SIGNALS
DS
PS
IS
129
131
130 O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless low-level asserted
for communication to a particular external space. They are placed in the high-impedance state during
reset, power down, and when EMU1/OFF is active low.
READY 36 I Data ready. READY indicates that an external device is prepared for the bus transaction to be
completed. If the device is not ready (READY is low), the processor waits one cycle and checks
READY again.
R/W 4 O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. It is
normally in read mode (high), unless low level is asserted for performing a write operation. It is placed
in the high-impedance state during reset, power down, and when EMU1/OFF is active low.
STRB 6 O/Z Strobe. STRB is always high unless asserted low to indicate an external bus cycle. It is placed in the
high-impedance state during reset, power down, and when EMU1/OFF is active low.
WE 1 O/Z
Write enable. The falling edge of WE indicates that the device is driving the external data bus
(D15–D0). Data can be latched by an external device on the rising edge of WE. WE is active on all
external program, data, and I/O writes. WE goes in the high-impedance state following reset and when
EMU1/OFF is active low.
W/R 132 O/Z Write/read. W/R is an inverted form of R/W and can connect directly to the output enable of external
devices. W/ R is placed in the high-impedance state following reset and when EMU1/OFF is active low.
†I = input, O = output, Z = high impedance
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
EXTERNAL INTERFACE CONTROL SIGNALS (CONTINUED)
BR 5 O/Z Bus request. BR is asserted during access of external global data memory space. BR can be
used to extend the data memory address space by up to 32K words. BR goes in the
high-impedance state during reset, power down, and when EMU1/OFF is active low.
VCCP/WDDIS 50 I
Flash-programming voltage supply. If VCCP = 5 V, then WRITE/ERASE can be made to the
ENTIRE on-chip flash memory block—that is, for programming the flash. If VCCP = 0 V, then
WRITE/ERASE of the flash memory is not allowed, thereby protecting the entire memory block
from being overwritten. VCCP/WDDIS also functions as a hardware watchdog disable. The
watchdog timer is disabled when VCCP/WDDIS = 5 V and bit 6 in WDCR is set to 1.
ADC INPUTS (UNSHARED)
ADCIN2 74 I
ADCIN3 75 I
ADCIN4 76 I
Analog inp ts to the first ADC
ADCIN5 77 I Analog inputs to the first ADC
ADCIN6 78 I
ADCIN7 79 I
ADCIN10 89 I
ADCIN11 88 I
ADCIN12 83 I
Analog inp ts to the second ADC
ADCIN13 82 I Analog inputs to the second ADC
ADCIN14 81 I
ADCIN15 80 I
BIT I/O AND SHARED FUNCTIONS PINS
ADCIN0/IOPA0 72 I/O Bidirectional digital I/O.
Analog input to the first ADC.
ADCIN0/IOPA0 is configured as a digital input by all device resets.
ADCIN1/IOPA1 73 I/O Bidirectional digital I/O.
Analog input to the first ADC.
ADCIN1/IOPA1 is configured as a digital input by all device resets.
ADCIN9/IOPA2 90 I/O Bidirectional digital I/O.
Analog input to the second ADC.
ADCIN9/IOPA2 is configured as a digital input by all device resets.
ADCIN8/IOPA3 91 I/O Bidirectional digital I/O.
Analog input to the second ADC.
ADCIN8/IOPA3 is configured as a digital input by all device resets.
PWM7/CMP7/IOPB0 100 I/O/Z
Bidirectional digital I/O. Simple compare/PWM 1 output. The state of PWM7/CMP7/IOPB0 is
determined by the simple compare/PWM and the simple action control register (SACTR). It
goes to the high-impedance state when unmasked PDPINT goes active low.
PWM7/CMP7/IOPB0 is configured as a digital input by all device resets.
PWM8/CMP8/IOPB1 101 I/O/Z
Bidirectional digital I/O. Simple compare/PWM 2 output. The state of PWM8/CMP8/IOPB1 is
determined b y the simple compare/PWM and the SACTR. It goes to the high-impedance state
when unmasked PDPINT goes active low. PWM8/CMP8/IOPB1 is configured as a digital input
by all device resets.
PWM9/CMP9/IOPB2 102 I/O/Z
Bidirectional digital I/O. Simple compare/PWM 3 output. The state of PWM9/CMP9/IOPB2 is
determined by the simple compare/PWM and SACTR. It goes to the high-impedance state
when unmasked PDPINT goes active low. PWM9/CMP9/IOPB2 is configured as a digital input
by all device resets.
†I = input, O = output, Z = high impedance
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
BIT I/O AND SHARED FUNCTIONS PINS (CONTINUED)
T1PWM/T1CMP/
IOPB3 105 I/O/Z Bidirectional digital I/O. Timer 1 compare output. T1PWM/T1CMP/IOPB3 goes to the high-
impedance state when unmasked PDPINT goes active low. This pin is configured as a digital
input by all device resets.
T2PWM/T2CMP/
IOPB4 106 I/O/Z Bidirectional digital I/O. Timer 2 compare output. T2PWM/T2CMP/IOPB4 goes to the high-
impedance state when unmasked PDPINT goes active low. This pin is configured as a digital
input by all device resets.
T3PWM/T3CMP/
IOPB5 107 I/O/Z Bidirectional digital I/O. Timer 3 compare output. T3PWM/T3CMP/IOPB5 goes to the high-
impedance state when unmasked PDPINT goes active low. This pin is configured as a digital
input by all device resets.
TMRDIR/IOPB6 108 I/O Bidirectional digital I/O. Direction signal for the timers. Up-counting direction if TMRDIR/IOPB6
is low, down-counting direction if this pin is high.
This pin is configured as a digital input by all device resets.
TMRCLK/IOPB7 109 I/O Bidirectional digital I/O.
External clock input for general-purpose timers.
This pin is configured as a digital input by all device resets.
ADCSOC/IOPC0 63 I/O Bidirectional digital I/O.
External start of conversion input for ADC.
This pin is configured as a digital input by all device resets.
CAP1/QEP1/IOPC4 67 I/O Bidirectional digital I/O.
Capture 1 or QEP 1 input.
This pin is configured as a digital input by all device resets.
CAP2/QEP2/IOPC5 68 I/O Bidirectional digital I/O.
Capture 2 or QEP 2 input.
This pin is configured as a digital input by all device resets.
CAP3/IOPC6 69 I/O Bidirectional digital I/O.
Capture 3 input.
This pin is configured as a digital input by all device resets.
CAP4/IOPC7 70 I/O Bidirectional digital I/O.
Capture 4 input.
This pin is configured as a digital input by all device resets.
XF/IOPC2 65 I/O Bidirectional digital I/O. External flag output (latched software-programmable signal). XF is
used for signaling other processors in multiprocessing configurations or as a general-purpose
output pin. This pin is configured as an external flag output by all device resets.
BIO/IOPC3 66 I/O Bidirectional digital I/O. Branch control input. BIO is polled by the BIOZ instruction. If BIO is low,
the CPU executes a branch. If BIO is not used , it should be pulled high. This pin is configured
as a branch-control input by all device resets.
CLKOUT/IOPC1 64 I/O Bidirectional digital I/O. Clock output. Clock output is selected by the CLKSRC bits in the
SYSCR register. This pin is configured as a DSP clock output by a power-on reset.
SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS
SCITXD/IO 44 I/O SCI asynchronous serial port transmit data, or general-purpose bidirectional I/O. This pin is
configured as a digital input by all device resets.
SCIRXD/IO 43 I/O SCI asynchronous serial port receive data, or general-purpose bidirectional I/O. This pin is
configured as a digital input by all device resets.
†I = input, O = output, Z = high impedance
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
TYPE†
DESCRIPTION
NAME NO. TYPE†DESCRIPTION
SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS
SPISIMO/IO 45 I/O SPI slave in, master out , or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPISOMI/IO 48 I/O SPI slave out, master in, or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPICLK/IO 49 I/O SPI clock, or general-purpose bidirectional I/O. This pin is configured as a digital input by all
device resets.
SPISTE/IO 51 I/O SPI slave transmit enable (optional), or general-purpose bidirectional I/O. This pin is configured
as a digital input by all device resets.
COMPARE SIGNALS
PWM1/CMP1
PWM2/CMP2
PWM3/CMP3
PWM4/CMP4
PWM5/CMP5
PWM6/CMP6
94
95
96
97
98
99
O/Z
Compare or PWM outputs. The state of these pins is determined by the compare/PWM and
the full action control register (ACTR). CMP1–CMP6 go to the high-impedance state when un-
masked PDPINT goes active low.
After power up and PORESET is high, the PWM/CMP pins are high-impedance once the
internal clock is stable (see Figure 31 and Figure 32).
INTERRUPT AND MISCELLANEOUS SIGNALS
RS 35 I/O Reset input. RS causes the TMS320F240 to terminate execution and sets PC = 0. When RS
is brought to a high level, execution begins at location zero of program memory. RS affects (or
sets to zero) various registers and status bits.
MP/MC 37 I MP/MC (microprocessor/microcomputer) select. If MP/MC is lo w, internal program memory is
selected. If it is high, external program memory is selected.
NMI 40 I Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state
of the INTM bit of the status register. NMI has programmable polarity.
PORESET 41 I
Power-on reset. PORESET causes the TMS320F240 to terminate execution and sets PC = 0.
When PORESET is brought to a high level, execution begins at location zero of program
memory. PORESET a ffects (or sets to zero) the same registers and status bits as RS. In addi-
tion, PORESET initializes the PLL control registers.
XINT1 53 I External user interrupt no. 1
XINT2/IO 54 I/O External user interrupt no. 2. General-purpose bidirectional I/O. This pin is configured as a
digital input by all device resets.
XINT3/IO 55 I/O External user interrupt no. 3. General-purpose bidirectional I/O. This pin is configured as a
digital input by all device resets.
PDPINT 52 I Maskable power-drive protection interrupt. If PDPINT is unmasked and it goes active low , the
timer compare outputs immediately go to the high-impedance state.
CLOCK SIGNALS
XTAL2 57 O
PLL oscillator output. XTAL2 is tied to one side of a reference crystal when the device is in PLL
mode (CLKMD[1:0] = 1x, CKCR0.7–6). This pin can be left unconnected in oscillator bypass
mode (OSCBYP ≤ VIL). This pin goes in the high-impedance state when EMU1/OFF is active
low.
XTAL1/CLKIN 58 I/Z PLL oscillator input. XTAL1/CLKIN is tied to one side of a reference crystal in PLL mode
(CLKMD[1:0] = 1x, CKCR0.7–6), or is connected to an external clock source in oscillator
bypass mode (OSCBYP ≤ VIL).
OSCBYP 56 I Bypass on-chip oscillator if low
†I = input, O = output, Z = high impedance
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
SUPPLY SIGNALS
CVSS 8 I Digital core logic ground reference
VSS
3
14
20
29
46
59
I
Digital logic gro nd reference
VSS
59
61
71
92
104
113
120
IDigital logic ground reference
VSSA 87 I Analog ground reference
DV
2
13
21
47
I
Digital I/O logic supply voltage
DVDD
47
62
93
103
121
IDigital I/O logic supply voltage
CV
7
I
Digital core logic s ppl oltage
CVDD 60 IDigital core logic supply voltage
VCCA 84 I Analog supply voltage
VREFHI 85 I ADC analog voltage reference high
VREFLO 86 I ADC analog voltage reference low
TEST SIGNALS
TCK 30 I
JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on
test-access port (TAP) input signals (TMS and TDI) are clocked into the T AP controller, instruction reg-
ister, or selected test data register of the C2xx core on the rising edge of TCK. Changes at the TAP
output signal (TDO) occur on the falling edge of TCK.
TDI 31 I JTAG test data input (TDI). TDI is clocked into the selected register (instruction or data) on a rising
edge of TCK.
TDO 34 O/Z JT AG test data output (TDO). The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state when OFF is active low.
TMS 33 I JTAG test mode select. This serial control input is clocked into the TAP controller on the rising edge
of TCK.
†I = input, O = output, Z = high impedance
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
TYPE†
DESCRIPTION
NAME NO. TYPE†DESCRIPTION
TEST SIGNALS (CONTINUED)
TRST 32 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the
operations o f the device. If this signal is not connected or driven low, the device operates in its function-
al mode, and the test reset signals are ignored.
EMU0 38 I/O/Z Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the /OFF condition.
When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as input/output through the scan.
EMU1/OFF 39 I/O/Z
Emulator pin 1/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to
or from the emulator system and is defined as input/output through JTAG scan. When TRST is driven
low, this pin is configured as OFF. When EMU1/OFF is active low, it puts all output drivers in the
high-impedance state. OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications); therefore, for OFF condition, the following conditions apply:
TRST = low, EMU0 = high, EMU1/OFF = low
RESERVED 42 I Reserved for test. This pin has an internal pulldown and must be left unconnected.
†I = input, O = output, Z = high impedance
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
Á
4
Á
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ÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
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216
ÁÁ
ÁÁ
ÁÁ
PDPINT
Á
Á
4
Á
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4
9
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41
7
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ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Quadrature
Encoder
Pulse (QEP)
Capture/
Units
Compare
Timers
Purpose
General-
Manager
Event
Software
Wait-State
Generation
External
Memory
Interface
Emulation
Test/
Peripheral Bus
Á
Á
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Timer
Watchdog
Interface
Communications
Serial-
Interface
Peripheral
Serial-
Converter
to-Digital
Analog-
Dual 10-Bit
Data Bus
Á
Á
Á
Á
Á
Á
Á
3
ÁÁ
Á
Reset
Digital Input/Output
Interrupts
20
4
Á
Á
Á
Á
Á
Á
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Á
ÁÁ
ÁÁ
Module
System-Interface
Module
Clock
Program Bus
Á
Á
Á
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Á
Á
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
B1/B2
DARAM
B0
DARAMFlash
EEPROM
Initialization
Interrupts
Control
Memory
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Controller
Program
CPU
C2xx
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Shifter
Product
PREG
TREG
Multiplier
Shifter
Output
Accumulator
ALU
Shifter
Input
Registers
Mapped
Memory-
Registers
Auxiliary
Registers
Control
Status/
ARAU
Register
Instruction
Á
Á
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
Table 1. Characteristics of the TMS320F240 DSP Controller
ON-CHIP MEMORY (WORDS)
RAM FLASH
EEPROM
POWER
SUPPLY
(V)
CYCLE
TIME
(ns)
PACKAGE
TYPE
PIN COUNT
DATA DATA/PROG PROG
(V)
(
ns
)
PIN
COUNT
288 256 16K 5 50 PQ 132–P
architectural overview
The functional block diagram provides a high-level description of each component in the F240 DSP controller.
The TMS320F240 device is composed of three main functional units: a C2xx DSP core, internal memory, and
peripherals. In addition to these three functional units, there are several system-level features of the F240 that
are distributed. These system features include the memory map, device reset, interrupts, digital input/ output
(I/O), clock generation, and low-power operation.
system-level functions
device memory map
The TMS320F240 implements three separate address spaces for program memory, data memory, and I/ O.
Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to
32K words at the top of the address range can be defined to be external global memory in increments of powers
of two, as specified by the contents of the global memory allocation register (GREG). Access to global memory
is arbitrated using the global memory bus request (BR) signal.
On the F240, the first 96 (0–5Fh) data memory locations are either allocated for memory-mapped registers or
are reserved. This memory-mapped register space contains various control and status registers including those
for the CPU.
All the on-chip peripherals of the F240 device are mapped into data memory space. Access to these registers
is made by the CPU instructions addressing their data-memory locations. Figure 1 shows the memory map.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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device memory map (continued)
0000 Interrupts
(External)
003F
0040
External
FDFF
0000 Interrupts
(On-Chip)
003F
0040
0000
005F
0060
01FF
FE00
FFFF
02FF
0300
FEFF
FF00
0200
03FF
0400
07FF Reserved
7000 Peripheral Memory-
Mapped Registers
(System, WD,
ADC, SPI, SCI,
Interrupts, I/O)
73FF
7400
743F
7440
77FF
0000
External
FF0E
FEFF
FF00 Reserved
Reserved
4000
External
3FFF
FDFF
FE00
FFFF
FEFF
FF00 Reserved
I/O
Hex
†ROM/Flash memory includes
address range 0000h–003Fh
Hex
Data
Hex
007F
0080
Reserved
Hex
8000 External
FFFF
7800
7FFF
FF0F
On-Chip DARAM B0
(CNF = 1)
or
External (CNF = 0)
On-Chip ROM†
(Flash EEPROM)
(8 x 2K Segments)
MP/MC = 1
Microprocessor
Mode
MP/MC = 0
Microcomputer
Mode
Program Program
Wait-state Generator
Control Register
Memory-Mapped
Registers and
Reserved
On-Chip
DARAM B2
On-Chip DARAM B0
(CNF = 0)
or
Reserved (CNF = 1)
On-Chip
DARAM B1
0800
6FFF Illegal
Peripheral
Memory-Mapped
Registers
(Event Manager)
On-Chip DARAM B0
(CNF = 1)
or
External (CNF = 0)
Reserved
Illegal
Flash Control
Mode Register
Reserved
FF10
FFFF
FFFE
Figure 1. TMS320F240 Memory Map
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14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
peripheral memory map
The TMS320F240 system and peripheral control register frame contains all the data, status, and control bits
to operate the system and peripheral modules on the device (excluding the event manager).
Global-Memory Allocation
Register
0000
0003
0004
0005
0000 Memory-Mapped Registers
and Reserved
005F
0060 On-Chip DARAM B2
02FF
0300
01FF
0200
03FF
On-Chip
DARAM B1
0400
Reserved
73FF Peripheral Frame 1
7400
77FF
7800
External
FFFF
7000–700F
Reserved
0007
Emulation Registers
and Reserved
Peripheral Frame 2
Reserved
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
Interrupt-Mask Register
Illegal
System Configuration and
Control Registers
Watchdog Timer and
PLL Control Registers
Illegal
Digital-I/O Control Registers
Illegal
Reserved
Reserved
Interrupt Mask, Vector and
Flag Registers
0006
005F
007F
0080
07FF
7000
743F
7440
7010–701F
7020–702F
7030–703F
7040–704F
7050–705F
7060–706F
7070–707F
7080–708F
7090–709F
7400–740C
7411–741C
7420–7426
7427–742B
742C–7434
7435–743F
Interrupt Flag Register
SPI
SCI
Illegal
External-Interrupt Registers
ADC
General-Purpose
Timer Registers
Capture & QEP Registers
Compare, PWM, and
Deadband Registers
Reserved
7FFF
8000
Illegal
0800
6FFF Illegal
Hex
Hex
70A0–73FF
Reserved
Reserved
741D–741F
740D–7410
Figure 2. Peripheral Memory Map
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digital I/O and shared pin functions
A total of 28 pins are shared between primary functions and I/Os. These pins are divided into two groups:
DGroup1 — Primary functions shared with I/Os belonging to dedicated I/O ports, Port A, Port B, and Port C.
DGroup2 — Primary functions belonging to peripheral modules which also have a built-in I/O feature as a
secondary function (for example, SCI, SPI, external interrupts, and PLL clock modules).
description of group1 shared I/O pins
The control structure for Group1 type shared I/O pins is shown in Figure 3. The only exception to this
configuration is the CLKOUT/IOPC1 pin. In Figure 3, each pin has three bits that define its operation:
DMux control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
DI/O direction bit — if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
DI/O data bit — if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
Pin
(Read/Write)
IOP Data Bit
In Out
0 = Input
1 = Output
01 MUX Control Bit
0 = I/O Function
1 = Primary Function
IOP DIR Bit
Primary
Function
or I/O Pin
Pullup
or
Pulldown
(Internal)
Primary
Function
(Output Section)
Primary
Function
(Input Section)
When the MUX control bit = 1,
the primary function is selected
in all cases except for the
following pins:
1. XF/IOPC2 (0 = Primary Function)
2. BIO/IOPC3 (0 = Primary Function)
Note:
Figure 3. Shared Pin Configuration
A summary of Group1 pin configurations and associated bits is shown in Table 2.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description of group1 shared I/O pins (continued)
Table 2. Group1 Shared Pin Configurations
PIN #
MUX CONTROL
REGISTER
PIN FUNCTION SELECTED I/O PORT DATA AND DIRECTION†
PIN # REGISTER
(name.bit #) (CRx.n = 1) (CRx.n = 0) REGISTER DATA BIT # DIR BIT #
72 OCRA.0 ADCIN0 IOPA0 PADATDIR 0 8
73 OCRA.1 ADCIN1 IOPA1 PADATDIR 1 9
90 OCRA.2 ADCIN9 IOPA2 PADATDIR 2 10
91 OCRA.3 ADCIN8 IOPA3 PADATDIR 3 11
100 OCRA.8 PWM7/CMP7 IOPB0 PBDATDIR 0 8
101 OCRA.9 PWM8/CMP8 IOPB1 PBDATDIR 1 9
102 OCRA.10 PWM9/CMP9 IOPB2 PBDATDIR 2 10
105 OCRA.11 T1PWM/T1CMP IOPB3 PBDATDIR 3 11
106 OCRA.12 T2PWM/T2CMP IOPB4 PBDATDIR 4 12
107 OCRA.13 T3PWM/T3CMP IOPB5 PBDATDIR 5 13
108 OCRA.14 TMRDIR IOPB6 PBDATDIR 6 14
109 OCRA.15 TMRCLK IOPB7 PBDATDIR 7 15
63 OCRB.0 ADCSOC IOPC0 PCDATDIR 0 8
64 SYSCR.7–6
0 0 IOPC1 PCDATDIR 1 9
0 1 WDCLK — — —
1 0 SYSCLK — — —
1 1 CPUCLK — — —
65 OCRB.2 IOPC2 XF PCDATDIR 2 10
66 OCRB.3 IOPC3 BIO PCDATDIR 3 11
67 OCRB.4 CAP1/QEP1 IOPC4 PCDATDIR 4 12
68 OCRB.5 CAP2/QEP2 IOPC5 PCDATDIR 5 13
69 OCRB.6 CAP3 IOPC6 PCDATDIR 6 14
70 OCRB.7 CAP4 IOPC7 PCDATDIR 7 15
†Valid only if the I/O function is selected on the pin.
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description of group2 shared I/O pins
Group2 shared pins belong to peripherals that have built-in general-purpose I/O capability. Control and
configuration for these pins are achieved by setting the appropriate bits within the control and configuration
registers of the peripherals. Table 3 lists the Group2 shared pins.
Table 3. Group2 Shared Pin Configurations
PIN # PRIMARY FUNCTION REGISTER ADDRESS PERIPHERAL MODULE
43 SCIRXD SCIPC2 705Eh SCI
44 SCITXD SCIPC2 705Eh SCI
45 SPISIMO SPIPC2 704Eh SPI
48 SPISOMI SPIPC2 704Eh SPI
49 SPICLK SPIPC1 704Dh SPI
51 SPISTE SPIPC1 704Dh SPI
54 XINT2 XINT2CR 7078h External Interrupts
55 XINT3 XINT3CR 707Ah External Interrupts
digital I/O control registers
Table 4 lists the registers available to the digital I/O module. As with other F240 peripherals, the registers are
memory-mapped to the data space.
Table 4. Addresses of Digital I/O Control Registers
ADDRESS REGISTER NAME
7090h OCRA I/O mux control register A
7092h OCRB I/O mux control register B
7098h PADATDIR I/O port A data and direction register
709Ah PBDATDIR I/O port B data and direction register
709Ch PCDATDIR I/O port C data and direction register
device reset and interrupts
The TMS320F240 software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The F240 recognizes three types of
interrupt sources:
DReset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
DHardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
–External interrupts are generated by one of five external pins corresponding to the interrupts XINT1,
XINT2, XINT3, PDPINT, and NMI. The first four can be masked both by dedicated enable bits and b y the
CPU’s i nterrupt m ask r egister ( IMR), w hich can m ask e ach m askable i nterrupt l ine a t t he D SP c ore. NMI,
which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It c a n
be locked out only by an already executing NMI or a reset.
–Peripheral interrupts are initiated internally by these on-chip peripheral modules: the event manager,
SPI, SC I , watchdog/real-time interrupt (WD/RTI), and ADC. They can be masked both by enable bits for
each e vent i n e ach p eripheral a nd b y t he C PU ’s IMR, which can mask each maskable interrupt l ine at the
DSP core.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device reset and interrupts (continued)
DSoftware-generated interrupts for the F240 device include:
–The INTR instruction. This instruction allows initialization of any F240 interrupt with software. Its
operand indicates to which interrupt vector location the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
–The NMI instruction. This instruction forces a branch to interrupt vector location 24h, the same location
used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI pin low or by
executing an NMI instruction. This instruction globally disables maskable interrupts.
–The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
–An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
resetThe reset operation ensures an orderly startup sequence for the device. There are five possible causes of a
reset, as shown in Figure 4. Three of these causes are internally generated; the other two causes, the RS and
PORESET pins, are controlled externally.
Signal
Reset
To Reset Out
To Device
Watchdog Timer Reset
Software-Generated Reset
Illegal Address Reset
Reset (RS) Pin Active
Power-On Reset (PORESET) Pin
Active
Figure 4. Reset Signals
The five possible reset signals are generated as follows:
DWatchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an
improper value is written to either the watchdog key register or the watchdog control register. (Note that
when the device is powered on, the watchdog timer is automatically active.)
DSoftware-generated reset. This is implemented with the system control register (SYSCR). Clearing the
RESET0 bit (bit 14) or setting the RESET1 bit (bit 15) causes a system reset.
DIllegal address reset. The system and peripheral module control register frame address map contains
unimplemented address locations in the ranges labeled illegal. Any access to an address located in the
Illegal ranges generate an illegal-address reset.
DReset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of as little
as a few nanoseconds is usually effective; however, pulses of one SYSCLK cycle are necessary to ensure
that the device recognizes the reset signal.
DPower-on reset pin active. To generate a power-on reset pulse on the PORESET pin, a low-level pulse
of one SYSCLK cycle is necessary to ensure that the device recognizes the reset signal.
Once a reset source is activated, the external RS pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the TMS320F240 device to reset external system components. Additionally, if a brown-out
condition (V CC < VCCmin for several microseconds causing PORESET to go low) occurs or the RS pin is held
low, then the reset logic holds the device in a reset state for as long as these actions are active.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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reset (continued)
The occurrence of a reset condition causes the TMS320F240 to terminate program execution and affects
various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are
affected by a reset are initialized to their reset state. In the case of a power-on reset, the PLL control registers
are initialized to zero. The program needs to recognize power-on resets and configure the PLL for correct
operation.
After a reset, the program can check the power-on reset flag (PORST flag, SYSSR.15), the illegal address flag
(ILLADR flag, SYSSR.12), the software reset flag (SWRST flag, SYSSR.10), and the watchdog reset flag
(WDRST flag, SYSSR.9) to determine the source of the reset. A reset does not clear these flags.
RS and PORESET must be held low until the clock signal is valid and VCC is within the operating range. In
addition, PORESET must be driven low when VCC drops below the minimum operating voltage.
hardware-generated interrupts
All the hardware interrupt lines of the DSP core are given a priority rank from 1 to 10 (1 being highest). When
more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets
acknowledged first. The others are acknowledged in order after that. Of those ten lines, six are for maskable
interrupt lines (INT1–INT6) and one is for the nonmaskable interrupt (NMI) line. INT1–INT6 and NMI have the
priorities shown in Table 5.
Table 5. Interrupt Priorities at the Level of the DSP Core
INTERRUPT PRIORITY AT THE
DSP CORE
RESET 1
TI RESERVED†2
NMI 3
INT1 4
INT2 5
INT3 6
INT4 7
INT5 8
INT6 9
TI RESERVED†10
†TI Reserved means that the address space is
reserved for Texas Instruments.
The inputs to these lines are controlled by the system module and the event manager as summarized in Table 6
and shown in Figure 5.
Table 6. Interrupt Lines Controlled by the System Module and Event Manager
PERIPHERAL INTERRUPT LINES
System Module INT1
INT5
INT6 NMI
Event Manager INT2
INT3
INT4
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20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
hardware-generated interrupts (continued)
DSP Core
5
INTC INTB INTA
Address
Lines 5–1
INT6 INT5 INT4 INT3 INT2 INT1 NMI
Address
Lines 5–1
System Module Event Manager
IACK
INT6 INT5 INT4 INT3 INT2 INT1 NMIIACK
NC NC NC
Figure 5. DSP Interrupt Structure
At the level of the system module and the event manager, each of the maskable interrupt lines (INT1–INT6) is
connected to multiple maskable interrupt sources. Sources connected to interrupt line INT1 are called Level 1
interrupts; sources connected to interrupt line INT2 are called Level 2 interrupts; and so on. For each interrupt
line, the multiple sources also have a set priority ranking. The source with the highest priority has its interrupt
request responded to by the DSP core first.
Figure 6 shows the sources and priority ranking for the interrupts controlled by the system module. For each
interrupt chain, the interrupt source of highest priority is at the top. Priority decreases from the top of the chain
to the bottom. Figure 7 shows the interrupt sources and priority ranking for the event manager interrupts.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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hardware-generated interrupts (continued)
IACK1IRQ1IACK5IRQ5IACK6IRQ6
NMIINT1INT6
System-Module
External Interrupt
NMI
To DSP INT6 To DSP INT1 To DSP NMI
NC = No connection
IACK = interrupt acknowledge
IRQ = interrupt request
Legend:
System-Module
External Interrupt
XINT1
(high priority)
System-Module
External Interrupt
XINT2
(high priority)
System-Module
External Interrupt
XINT3
(high priority)
SPI
Interrupt
(high priority)
SCI
Receiver
Interrupt
(low priority)
SPI
Interrupt
(low priority)
System-Module
External Interrupt
XINT1
(low priority)
System-Module
External Interrupt
XINT2
(low priority)
System-Module
External Interrupt
XINT3
(low priority)
Dual ADC
Interrupt
IACK_NMIIRQ_NMIIACK2IRQ2IACK3IRQ3IACK4IRQ4
NCNCNCNCNCNC
INT5
To DSP INT5
INT2INT3INT4
NCNCNC
SCI
Transmitter
Interrupt
(high priority)
SCI
Transmitter
Interrupt
(low priority)
SCI
Receiver
Interrupt
(high priority)
Watchdog
Timer
Interrupt
System Module
Figure 6. System Module Interrupt Structure
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
hardware-generated interrupts (continued)
IACKAIRQAIACKBIRQBIACKCIRQC
INTAINTBINTC
Power-Drive
Protection
Interrupt
Compare1
Interrupt
Compare 2
Interrupt
Compare 3
Interrupt
Simple-
Compare 1
Interrupt
Simple-
Compare 2
Interrupt
Simple-
Compare 3
Interrupt
Timer 1
Period
Interrupt
Timer 1
Compare
Interrupt
Timer 1
Underflow
Interrupt
Timer 1
Overflow
Interrupt
Timer 2
Period
Interrupt
Timer 2
Compare
Interrupt
Timer 2
Underflow
Interrupt
Timer 2
Overflow
Interrupt
Timer 3
Period
Interrupt
Timer 3
Compare
Interrupt
Timer 3
Underflow
Interrupt
Timer 3
Overflow
Interrupt
Capture 1
Interrupt
Capture 2
Interrupt
Capture 3
Interrupt
Capture 4
Interrupt
To DSP INT4 To DSP INT3 To DSP INT2
IACK = Interrupt acknowledge
IRQ = Interrupt request
Legend:
Event Manager
Figure 7. Event-Manager Interrupt Structure
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hardware-generated interrupts (continued)
Each of the interrupt sources has its own control register with a flag bit and an enable bit. When an interrupt
request is received, the flag bit in the corresponding control register is set. If the enable bit is also set, a signal
is sent to arbitration logic, which can simultaneously receive similar signals from one or more of the other control
registers. The arbitration logic compares the priority level of competing interrupt requests, and it passes the
interrupt of highest priority to the CPU. The corresponding flag is set in the interrupt flag register (IFR), indicating
that the interrupt is pending. The CPU then must decide whether to acknowledge the request. Maskable
hardware interrupts are acknowledged only after certain conditions are met:
DPriority is highest. When more than one hardware interrupt is requested at the same time, the F240
services them according to the set priority ranking.
DINTM bi t i s 0 . The interrupt mode (INTM) bit, bit 9 of status register ST0, enables or disables all maskable
interrupts:
–When INTM = 0, all unmasked interrupts are enabled.
–When INTM = 1, all unmasked interrupts are disabled.
INTM is set to 1 automatically when the CPU acknowledges an interrupt (except when initiated by the TRAP
instruction) and at reset. It can be set and cleared by software.
DIMR mask bit is 1. Each of the maskable interrupt lines has a mask bit in the interrupt mask register (IMR).
To unmask an interrupt line, set its IMR bit to 1.
When the CPU acknowledges a maskable hardware interrupt, it jams the instruction bus with the INTR
instruction. This instruction forces the PC to the appropriate address from which the CPU fetches the software
vector. This vector leads to an interrupt service routine.
Usually, the interrupt service routine reads the peripheral-vector-address offset from the peripheral-vector-
address register (see Table 7) to branch to code that is meant for the specific interrupt source that initiated the
interrupt request. The F240 includes a phantom-interrupt vector offset (0000h), which is a system interrupt
integrity feature that allows a controlled exit from an improper interrupt sequence. If the CPU acknowledges a
request from a peripheral when, in fact, no peripheral has requested an interrupt, the phantom-interrupt vector
is read from the interrupt-vector register.
Table 7 summarizes the interrupt sources, overall priority, vector address/offset, source, and function of each
interrupt available on the TMS320F240.
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hardware-generated interrupts (continued)
Table 7. Interrupt Locations and Priorities
INTERRUPT
NAME OVERALL
PRIORITY
DSP-CORE
INTERRUPT,
AND
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
OFFSET
MASKABLE? SOURCE
PERIPHERAL
MODULE
FUNCTION
INTERRUPT
RS 1
Highest RS
0000h N/A N Core, SD External, system reset
(RESET)
RESERVED 2 INT7
0026h N/A N/A N DSP Core Emulator trap
NMI 3 NMI
0024h N/A 0002h N Core, SD External user interrupt
XINT1
XINT2
XINT3
4
5
6
0001h
0011h
001Fh Y SD High-priority external user
interrupts
SPIINT 7 INT1 0005h Y SPI High-priority SPI interrupt
RXINT 8 0002h
(System)
SYSIVR
(701Eh) 0006h Y SCI SCI receiver interrupt
(high priority)
TXINT 9
(S
ystem
)
0007h Y SCI SCI transmitter interrupt
(high priority)
WDTINT 10 0010h Y WDT Watchdog timer interrupt
PDPINT 11 0020h Y External Power-drive protection Int.
CMP1INT 12 0021h Y EV.CMP1 Full Compare 1 interrupt
CMP2INT 13 0022h Y EV.CMP2 Full Compare 2 interrupt
CMP3INT 14 0023h Y EV.CMP3 Full Compare 3 interrupt
SCMP1INT 15 INT2
0004h
0024h Y EV.CMP4 Simple compare 1
interrupt
SCMP2INT 16
0004h
(Event EVIVRA
(7432h) 0025h Y EV.CMP5 Simple compare 2
interrupt
SCMP3INT 17
(e
Manager
Group A)
(7432h)
0026h Y EV.CMP6 Simple compare 3
interrupt
TPINT1 18 0027h Y EV.GPT1 Timer1-period interrupt
TCINT1 19 0028h Y EV.GPT1 Timer1-compare interrupt
TUFINT1 20 0029h Y EV.GPT1 Timer1-underflow interrupt
TOFINT1 21 002Ah Y EV.GPT1 Timer1-overflow interrupt
TPINT2 22 002Bh Y EV.GPT2 Timer2-period interrupt
TCINT2 23 002Ch Y EV.GPT2 Timer2-compare interrupt
TUFINT2 24 INT3
0006h
002Dh Y EV.GPT2 Timer2-underflow interrupt
TOFINT2 25 0006h EVIVRB 002Eh Y EV.GPT2 Timer2-overflow interrupt
TPINT3 26 (Event
M
EVIVRB
(7433h) 002Fh Y EV.GPT3 Timer3-period interrupt
TCINT3 27
(
Manager
Grou
p
B)
0030h Y EV.GPT3 Timer3-compare interrupt
TUFINT3 28
G
roup
B)
0031h Y EV.GPT3 Timer3-underflow interrupt
TOFINT3 29 0032h Y EV.GPT3 Timer3-overflow interrupt
CAPINT1 30 INT4 0033h Y EV.CAP1 Capture 1 interrupt
CAPINT2 31 0008h EVIVRC 0034h Y EV.CAP2 Capture 2 interrupt
CAPINT3 32 (Event
Manager
EVIVRC
(7434h) 0035h Y EV.CAP3 Capture 3 interrupt
CAPINT4 33 Manager
Group C) 0036h Y EV.CAP4 Capture 4 interrupt
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hardware-generated interrupts (continued)
Table 7. Interrupt Locations and Priorities (Continued)
INTERRUPT
NAME OVERALL
PRIORITY
DSP-CORE
INTERRUPT,
AND
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
OFFSET
MASKABLE? SOURCE
PERIPHERAL
MODULE
FUNCTION
INTERRUPT
SPIINT 34 INT5
SYSIVR
0005h Y SPI Low-priority SPI interrupt
RXINT 35 000Ah
SYSIVR
(701Eh) 0006h Y SCI SCI receiver interrupt
(low priority)
TXINT 36
000Ah
(System) 0007h Y SCI SCI transmitter interrupt
(low priority)
ADCINT 37 INT6 SYSIVR 0004h Y ADC Analog-to-digital interrupt
XINT1
XINT2
38
39
000Ch
(701Eh)
0001h
0011h
Y
Y
External Low-priorit
y
external
XINT2
XINT3 39
40
000Ch
(System) (701Eh) 0011h
001Fh Y
Y
External
pins
Low riority
external
user interrupts
RESERVED 41 000Eh N/A Y DSP Core Used for analysis
TRAP N/A 0022h N/A N/A TRAP instruction vector
external interrupts
The F240 has five external interrupts. These interrupts include:
DXINT1. Type A interrupt. The XINT1 control register (at 7070h) provides control and status for this interrupt.
XINT1 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a
general-purpose input pin. XINT1 can also be programmed to trigger an interrupt on either the rising or th e
falling edge.
DNMI. Type A interrupt. The NMI control register (at 7072h) provides control and status for this interrupt. NMI
is a nonmaskable external interrupt or a general-purpose input pin. NMI can also be programmed to trigger
an interrupt on either the rising or the falling edge.
DXINT2. Type C interrupt. The XINT2 control register (at 7078h) provides control and status for this interrupt.
XINT2 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a
general-purpose I/O pin. XINT2 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
DXINT3. Type C interrupt. The XINT3 control register (at 707Ah) provides control and status for this interrupt.
XINT3 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a
general-purpose I/O pin. XINT3 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
DPDPINT. This interrupt is provided for safe operation of the power converter and motor drive. This maskable
interrupt can put the timers and PWM output pins in the high-impedance state and inform the CPU in case
of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. PD PINT is
a Level 2 interrupt.
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external interrupts (continued)
Table 8 is a summary of the external interrupt capability of the F240.
Table 8. External Interrupt Types and Functions
EXTERNAL
INTERRUPT
CONTROL
REGISTER
NAME
CONTROL
REGISTER
ADDRESS
INTERRUPT
TYPE CAN DO
NMI? DIGITAL
I/O PIN MASKABLE?
XINT1 XINT1CR 7070h A No Input only Yes
(Level 1 or 6)
NMI NMICR 7072h A Yes Input only No
XINT2 XINT2CR 7078h C No I/O Yes
(Level 1 or 6)
XINT3 XINT3CR 707Ah C No I/O Yes
(Level 1 or 6)
PDPINT EVIMRA 742Ch N/A N/A N/A Yes
(Level 2)
clock generation
The TMS320F240 has an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The only external component necessary for
this module is an external fundamental crystal, or oscillator.
The PLL-based clock module provides two basic modes of operation: oscillator mode and clock-in mode.
Doscillator mode
This mode allows the use of a 4-, 6-, or 8-MHz external reference crystal to provide the time base to the
device. The internal oscillator circuitry is initialized by software to select the desired CPUCLK frequency,
which can be the input clock frequency, the input clock frequency divided by 2 (default), or a clock frequency
determined by the PLL.
DClock-in mode
This mode allows the internal crystal oscillator circuitry to be bypassed. The device clocks are generated
from an external clock source input on the XTAL1/CLKIN pin. The device can be configured by software
to operate on the input clock frequency, the input clock frequency divided by 2, or a clock frequency
determined by the PLL.
The F240 runs on two clock frequencies: the CPU clock (CPUCLK) frequency, and the system clock (SYSCLK)
frequency. The CPU, memories, external memory interface, and event manager run at the CPUCLK frequency.
All other peripherals run at the SYSCLK frequency. The CPUCLK runs at 2x or 4x the frequency of the SYSCLK;
for example, for 2x, CPUCLK = 20 MHz and SYSCLK = 10 MHz. There is also a clock for the watchdog timer,
WDCLK. This clock has a nominal frequency of 16384 Hz (214 Hz) when XTAL1/CLKIN is a power of two or
a sum of two powers of two; for example, 4194304 Hz (222 Hz), 6291456 (222 + 221 Hz), or 8388608 Hz
(223 Hz).
The clock module includes three external pins:
1. XTAL1/CLKIN clock source/crystal input
2. XTAL2 output to crystal
3. OSCBYP oscillator bypass
For the external pins, if OSCBYP ≥ VIH, then the oscillator is enabled and if OSCBYP ≤ VIL, then the oscillator
is bypassed and the device is in clock-in mode. In clock-in mode, an external TTL clock must be applied to the
XTAL1/CLKIN pin. The XTAL2 pin can be left unconnected.
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clock generation (continued)
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
CPUCLK
Synchronizing
Clock Switch
VCO
ACLK
WDCLK
SYSCLK
Clock Mode Bits
(CKCR0.7–6)
Div 2
MUXMUX
Div 2
XTAL
OSC
PLL
1-MHz Clock Prescaler
SYSCLK Prescaler Div 2 or 4
Prescale Bit (CKCR0.0)
Phase
Detector
Feedback
Divider
Div 1, 2, 3, 4, 5,
or 9
Watchdog Clock Prescaler
Clock Frequency and PLL Multiply Bits (CKCR1.7–4)
XTAL2
XTAL1/CLKIN
OSCBYP
PLL divide-by-2 bit
(CKCR1.3)
PLL multiply ratio
(CKCR1.2–0)
Figure 8. PLL Clock Module Block Diagram
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low-power modes
The TMS320F240 has four low-power modes (IDLE 1, IDLE 2, PLL power down, and oscillator power down).
The low-power modes reduce the operating power by reducing or stopping the activity of various modules (by
stopping their clocks). The two PLLPM bits of the clock module control register, CKCR0, select which of the
low-power modes the device enters when executing an IDLE instruction. Reset or an unmasked interrupt from
any source causes the device to exit from IDLE 1 low-power mode. A real-time interrupt from the watchdog timer
module causes the device to exit from all low-power modes except oscillator power down. This is a wake-up
interrupt. When enabled, reset or any of the four external interrupts (NMI, XINT1, XINT2, or XINT3) causes the
device to exit from any of the low-power modes (IDLE 1, IDLE 2, PLL power down, and oscillator power down).
The external interrupts are all wake-up interrupts. The maskable external interrupts (XINT1, XINT2, and XINT3)
must be enabled individually and globally to bring the device out of a low-power mode properly. It is, therefore,
important to ensure that the desired low-power-mode exit path is enabled before entering a low-power mode.
Figure 9 shows the wake-up sequence from a power down. Table 9 summarizes the low-power modes.
Watchdog Timer
and
Real-Time Interrupt
Module
NMI
XINT1
XINT2
XINT3
External-Interrupt Logic
Reset Logic
Reset
Signal
Wake-up Signal
to CPU
Wake-up
Signal
System Module
Figure 9. Waking Up the Device From Power Down
Table 9. Low-Power Modes
LOW-
POWER
MODE
PLLPM(x)
BITS IN
CKCR0[2:3]
CPUCLK
STATUS SYSCLK
STATUS WDCLK
STATUS PLL
STATUS OSC
STATUS EXIT
CONDITION TYPICAL
POWER
Run XX On On On On On –80 mA
Idle 1 00 Off On On On On Any interrupt
or reset 50 mA
Idle 2 01 Off Off On On On Wake-up
interrupt or
reset 7 mA
PLL Power
Down 10 Off Off On Off On Wake-up
interrupt or
reset 1 mA
OSC Power
Down 11 Off Off Off Off Off Wake-up
interrupt or
reset 400 mA
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functional block diagram of the TMS320F240 DSP CPU
32
16
Data Bus
16
OSCALE (0–7)
D15–D0
A15–A0
16
1616
32
32
ACCL(16)ACCH(16)C
32
CALU(32)
3232
MUX
ISCALE (0–16)
16
MUX
PREG(32)
Multiplier
TREG0(16)
MUX
16
16
MUX
B1 (256 ×16)
B2 (32 ×16)
DARAM
B0 (256 ×16)
DARAM
7
LSB
from
IR
MUX
DP(9)
9
9
MUX
1616
ARAU(16)
16
3
33
3
ARB(3)
ARP(3)
Program Bus
16
16
16
16
AR7(16)
AR6(16)
AR5(16)
AR3(16)
AR2(16)
AR1(16)
AR0(16)
Stack 8 ×16
PC
MUX
NMI
WE
W/R
16
CLKIN/X2
CLKOUT1
X1
3
XINT[1–3]
MP/MC
RS
XF
BR
READY
STRB
R/W
PS
DS
IS
Control
Data Bus
Program Bus
Data Bus
AR4(16)
16
MUXMUX
Data/Prog
16
PSCALE (–6,ā0,ā1,ā4)
16
Data
32
16
16
16
16
16
FLASH EEPROM
MUX
MUX
NPAR
PAR MSTACK
Program Control
(PCTRL)
Memory Map
Register
IMR (16)
IFR (16)
GREG (16)
16
Program Bus
NOTES: A. Symbol descriptions appear in Table 10.
B. For clarity the data and program buses are shown as single buses although they include address and data bits.
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Table 10. Legend for the F240 Internal Hardware Functional Block Diagram
SYMBOL NAME DESCRIPTION
ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities
ARAU Auxiliary Register
Arithmetic Unit An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs
AUX
REGS Auxiliary Registers
0–7
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
BR Bus Request
Signal
BR is asserted during access of the external global data memory space. READY is asserted to the device
when the global data memory is available for the bus transaction. BR can be used to extend the data memory
address space by up to 32K words.
C Carry Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
CALU Central Arithmetic
Logic Unit
32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.
DARAM Dual Access RAM
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 0300–03FF and 0060–007F, respectively. Blocks 0
and 1 contain 256 words, while Block 2 contains 32 words.
DP Data Memory
Page Pointer The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct memory
address of 16 bits. DP can be modified by the LST and LDP instructions.
GREG Global Memory
Allocation
Register GREG specifies the size of the global data memory space.
IMR Interrupt Mask
Register IMR individually masks or enables the seven interrupts.
IFR Interrupt Flag
Register The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable
interrupts.
INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available.
ISCALE Input Data-Scaling
Shifter 16 to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
MPY Multiplier 16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MSTACK Micro Stack MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
MUX Multiplexer Multiplexes buses to a common input
NPAR Next Program
Address Register NPAR holds the program address to be driven out on the PAB on the next cycle.
OSCALE Output
Data-Scaling
Shifter
16 to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the Data-Write Data
Bus (DWEB).
PAR Program Address
Register PAR holds the address currently being driven on P AB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PC Program Counter PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PCTRL Program
Controller PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
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Table 10. Legend for the F240 Internal Hardware Functional Block Diagram (Continued)
SYMBOL NAME DESCRIPTION
PREG Product Register 32-bit register holds results of 16 × 16 multiply.
PSCALE Product-Scaling
Shifter
0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the Data-Write Data Bus (DWEB), and requires no cycle
overhead.
STACK Stack STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The C20x stack is 16-bit wide and eight-level deep.
TREG Temporary
Register 16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
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F240 DSP core CPU
The TMS320F240 device uses an advanced Harvard-type architecture that maximizes processing power by
maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple
bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM, thereby eliminating the need for a separate coefficient that are ROM. This, coupled
with a four-deep pipeline, allows the F240 device to execute most instructions in a single cycle.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thereby allowing the status of the machine to be
saved and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 10 shows the organization of status registers ST0 and ST1, indicating all status bits
contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 1 1 lists status
register field definitions.
15 131211109876543210
ST0 ARP OV OVM 1 INTM DP
15 13121110987654321 0
ST1 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM
Figure 10. Status and Control Register Organization
Table 11. Status Register Field Definitions
FIELD FUNCTION
ARB Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.
ARP Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.
C
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C i s reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
cases, the ADD can only set and the SUB only reset the carry bit, but cannot affect it otherwise. The single bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.
CNF On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.
DP Data memory page pointer. The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct
memory address of 16 bits. DP can be modified by the LST and LDP instructions.
INTM
Interrupt m ode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS and IACK also set INTM. INTM has no effect on the
unmaskable R S and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set
to 1 when a maskable interrupt trap is taken.
OV Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an
overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instructions clear OV.
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status and control registers (continued)
Table 11. Status Register Field Definitions (Continued)
FIELD FUNCTION
OVM Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator
is set to either its most positive or negative value upon encountering an overflow . The SETC and CLRC instructions set and rese t
this bit, respectively. LST can also be used to modify the OVM.
PM
Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG
output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, PREG output is left-shifted by four
bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of six bits, sign-extended. Note that the PREG
contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the
SPM and LST #1 instructions. PM is cleared by RS.
SXM
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.
SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction
suppresses sign extension regardless of SXM. SXM is set by the SETC SXM and reset by the CLRC SXM instructions, and can
be loaded by the LST #1. SXM is set to 1 by reset.
TC
Test/control flag bit. TC is af fected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT
or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the two
MSBs of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return instructions can
execute based on the condition of TC.
XF XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF and reset by the
CLRC XF instructions. XF is set to 1 by reset.
central processing unit
The TMS320F240 central processing unit (CPU) contains a 16-bit scaling shifter , a 16 x 16-bit parallel multiplier,
a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both
the accumulator and the multiplier. This section describes the CPU components and their functions. The
functional block diagram shows the components of the CPU.
input scaling shifter
The TMS320F240 provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction wor d o r b y a v a l u e i n TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.
multiplier
The TMS320F240 device uses a 16 x 16-bit hardware multiplier that is capable of computing a signed or an
unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned)
instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number. Two registers are associated with
the multiplier:
D16-bit temporary register (TREG) that holds one of the operands for the multiplier
D32-bit product register (PREG) that holds the product
Four product shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 12.
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multiplier (continued)
Table 12. PSCALE Product Shift Modes
PM SHIFT DESCRIPTION
00 No shift Product feed to CALU or data bus with no shift
01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
10 Left 4 Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product
when using the multiply by a 13-bit constant
11 Right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with
a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number
by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication also can be
performed with a 13-bit immediate operand when using the MPY instruction. Then a product is obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. The pipeline operations that
run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG
to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN) logic, while the data addresses are
generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values
from the coefficient table sequentially and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throw away the oldest sample.
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits
to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store
product high) and SPL (store product low). Note: the transfer of PREG to either the CALU or data bus passes
through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important
when saving PREG in an interrupt-service-routine context save as the PSCALE shift ef fects cannot be modeled
in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can
be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then,
is loaded using the LPH instruction.
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central arithmetic logic unit
The TMS320F240 central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical
functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to d ifferentiate
it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU).
Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional
operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming
from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or
derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform
Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the
CALU is always provided from the accumulator, and the other input can be provided from the product register
(PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the
ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320F240 device supports floating-point operations for applications requiring a large dynamic range.
The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator
by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to /subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is,
floating-point to fixed-point conversion. They are also useful in execution of an automatic gain control (AGC)
going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based
on the value contained in the four LSBs of TREG.
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Logical operations cannot result in
overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and the
accumulator. These instructions can be executed conditionally based on any meaningful combination of these
status bits. For overflow management, these conditions include the OV (branch on overflow) and EQ (branch
on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides
the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It also is useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
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central arithmetic logic unit (continued)
Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing,
based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the
carry bit. The carry bit is set to one on a hardware reset.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16–31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0–15). When the post-scaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The
SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not af fected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The F240 provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register
addressing allows placement of the data memory address of an instruction operand into one of the auxiliary
registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value
from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded
from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The
contents of these registers also can be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0–AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary
register while the data memory location is being addressed. Indexing either by ±1 or by the contents of the AR0
register can be performed. As a result, accessing tables of information does not require the CALU for address
manipulation; therefore, the CALU is free for other operations in parallel.
internal memory
The TMS320F240 device is configured with the following memory modules:
DDual-access random-access memory (DARAM)
DFlash EEPROM
dual-access RAM (DARAM)
There are 544 words × 16 bits of DARAM on the F240 device. The F240 DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space.
The SETC CNF (configure B0 as data memory) and CLRC CNF (configure B0 as program memory) instructions
allow dynamic configuration of the memory maps through software. When using block 0 as program memory,
instructions can be downloaded from external program memory into on-chip RAM and then executed. When
using on-chip RAM, or high-speed external memory, the F240 runs at full speed with no wait states. The ability
of the DARAM to allow two accesses to be performed in one cycle coupled with the parallel nature of the F240
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dual-access RAM (DARAM) (continued)
architecture enables the device to perform three concurrent memory accesses in any given machine cycle.
Externally, the READY line can be used to interface the F240 to slower, less expensive external memory.
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.
flash EEPROM
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is nonvolatile;
however, it has the advantage of “in-target” reprogrammability. The TMS320F240 incorporates one 16K
16-bit flash EEPROM module in program space. This type of memory expands the capabilities of the
TMS320F240 in the areas of prototyping, early field-testing, and single-chip applications.
Unlike most discrete flash memory, the F240 flash does not require a dedicated state machine, because the
algorithms for programming and erasing the flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1† (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V
power supply.
An erased bit in the TMS320F240 flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash
requires a block-erase of the entire 16K module; however, any combination of bits can be programmed. The
following four algorithms are required for flash operations: clear, erase, flash-write, and program. For an
explanation of these algorithms and a complete description of the flash EEPROM, see the TMS320F20x/F24x
DSP Embedded Flash Memory Technical Reference (literature number SPRU282).
flash serial loader
The on-chip flash is shipped with a serial bootloader code programmed at the following addresses:
0x0000–0x00FFh. All other flash addresses are in an erased state. The serial bootloader can be used to
program the on-chip Flash memory with user’s code. During the Flash programming sequence, the on-chip data
RAM is used to load and execute the clear, erase, and program algorithms.
flash control mode register
The flash control mode register is located at I/O address FF0Fh. This register offers two options: register access
mode and array access mode. Register access mode gives access to the four control registers in the memory
space decoded for the flash module. These registers are used to control erasing, programming, and testing of
the flash array. Register access mode is enabled by activating an OUT command with dummy data.
The OUT xxxx, FF0Fh instruction makes the flash registers accessible for reads and/or writes. After
executing OUT xxxx, FF0Fh, the flash control registers are accessed in the memory space decoded for the
flash module and the flash array cannot be accessed. The four registers are repeated every four address
locations within the flash module’s decoded range.
After completing all the necessary reads and/or writes to the control registers, an IN xxxx, FF0Fh instruction
(with dummy data) is executed to place the flash array back in array access mode. After executing the
IN xxxx, FF0Fh instruction, the flash array is accessed in the decoded space and the flash registers are
not available. Switching between the register access mode and the array access mode is done by issuing the
IN and OUT instructions. The memory content in these instructions (denoted by xxxx) is not relevant. Refer to
the TMS320F20x/F24x DSP Embedded Flash Memory Technical Reference (literature number SPRU282) for
a detailed description of the flash programming algorithms.
†IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port
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peripherals
The integrated peripherals of the TMS320F240 are described in the following subsections:
DExternal memory interface
DEvent manager (EV)
DDual analog-to-digital converter (ADC)
DSerial peripheral interface (SPI)
DSerial communications interface (SCI)
DWatchdog timer (WD)
external memory interface
The TMS320F240 can address up to 64K words × 16 bits of memory or registers in each of the program, data,
and I/O spaces. On-chip memory, when enabled, removes some of this off-chip range. In data space, the high
32K words can be mapped dynamically as either local or global using the GREG register. A data-memory
access mapped as global asserts BR low (with timing similar to the address bus).
The CPU of the TMS320F240 schedules a program fetch, data read, and data write on the same machine cycle.
This is because, from on-chip memory, the CPU can execute all three of these operations in the same cycle.
However, the external interface multiplexes the internal buses to one address and one data bus. The external
interface sequences these operations to complete the data write first, then the data read, and finally the program
read.
The F240 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces
provide in t e r f ace to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along
with the PS, DS, and IS space-select signals allow addressing of 64K 16-bit words in program and I/O space.
Due to the on-chip peripherals, external data space is addressable to 32K 16-bit words.
I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O
address space using the processor’s external address and data buses in the same manner as memory-mapped
devices.
The F240 external parallel interface provides control signals to facilitate interfacing to the device. The R/W
output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles.
Interface to memory and I/O devices of varying speeds is accomplished by using the READY input. When
transactions are made with slower devices, the F240 processor waits until the other device completes its
function and signals the processor by way of the READY input. Once a ready indication is provided from the
external device, execution continues. On the F240 device, the READY input must be driven (active high) to
complete reads or writes to internal data I/O-memory-mapped registers and all external addresses.
The bus request (BR) signal is used in conjunction with the other F240 interface signals to arbitrate external
global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted
at the beginning of the access. When an external global-memory device receives the bus request, it responds
by asserting the ready signal after the global-memory access is arbitrated and the global access is completed.
The TMS320F240 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the F240 to buf fer the transition of the data bus from input to output (or output
to input) by a half cycle. In most systems, TMS320F240 ratio of reads to writes is significantly large to minimize
the overhead of the extra cycle on writes.
Wait states can be generated when accessing slower external resources. The wait states operate on
machine-cycle boundaries and are initiated either by using the ready signal or using the software wait-state
generator. Ready can be used to generate any number of wait states.
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event-manager (EV) module
The event-manager module includes general-purpose (GP) timers, full compare units, capture units, and
quadrature-encoder pulse (QEP) circuits. Figure 11 shows the functions of the event manager.
general-purpose (GP) timers
There are three GP timers on the TMS320F240. The GP timer x (for x = 1, 2, 3) includes:
DA 16-bit timer up-, up/down-counter, TxCNT for reads or writes
DA 16-bit timer-compare register (double-buffered with shadow register), TxCMPR for reads or writes
DA 16-bit timer-period register (double-buffered with shadow register), TxPR for reads or writes
DA 16-bit timer-control register,TxCON for reads or writes
DSelectable internal or external input clocks
DA programmable prescalar for internal or external clock inputs
DControl and interrupt logic for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
DA timer-compare output pin with configurable active-low and active-high states, as well as forced-low and
forced-high states.
DA selectable direction (TMRDIR) input pin (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. A 32-bit GP timer also can be
configured using GP timer 2 and 3. The compare register associated with each GP timer can be used for
compare function and PWM-waveform generation. There are two single and three continuous modes of
operation for each GP timer in up- or up/down-counting operations. Internal or external input clocks with
programmable prescaler is used for each GP timer. The state of each GP timer/compare output is configurable
by the general-purpose timer-control register (GPTCON). GP timers also provide the time base for the other
event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 1 or 2 for the simple
compares to generate additional compare or PWMs, GP timer 2 or 3 for the capture units and the
quadrature-pulse counting operations.
Double buffering of the period and compare registers allows programmable change of the timer (PWM) period
and the compare/PWM pulse width as needed.
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16
DSP core
Data bus ADDR bus
EV control registers
and control logic
GP timer 1 compare
Full compare units
GP timer 2 compare
GP timer 2
MUX
Simple compare units
GP timer 3 compare
MUX
Capture units
16
16
16
16
16
16
GP timer 1
GP timer 3
3
INT2, 3, 4
2TMRCLK
TMRDIR
ADC start
T1PWM/T1CMP
SVPWM
state
machine
Dead
band
units
Output
logic
33
PWM1/CMP1
3
PWM6/CMP6
Output
logic
3T2PWM/T2CMP
Output
logic
3PWM8/CMP8
PWM7/CMP7
PWM9/CMP9
Output
logic T3PWM/T3CMP
2
2
2
QEP
circuit
To Control logic
ClockDir
CAP1/QEP1
CAP2/QEP2
CAP3, 4
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Internal clock
RESET
Output
logic
Figure 11. Event-Manager Block Diagram
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full compare units
There are three full compare units on TMS320F240. These compare units use GP timer1 as the timebase and
generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The
state of each of the six outputs is configured independently. The compare registers of the compare units are
double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
programmable-deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
value (from 0 to 102 ms) can be programmed into the compare register for the outputs of the three compare units.
The deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way of the
double-buffered ACTR register.
simple compares
TMS320F240 is equipped with three simple compares that can be used to generate three additional
independent compare or high-precision PWM waveforms. GP timer1 or 2 can be selected as the timebase for
the three simple compares. The states of the outputs of the three simple compares are configurable as
low-active, high-active, forced-low, or forced-high independently. Simple compare registers are
double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. The state of
the simple-compare outputs is configurable and changeable as needed by way of the double-buffered SACTR
register.
compare/PWM waveform generation
Up to 12 compare and/or PWM waveforms (outputs) can be generated simultaneously by TMS320F240: three
independent pairs (six outputs) by the three full compare units with programmable deadbands, three
independent compares or PWMs (three outputs) by the simple compares, and three independent compare and
PWMs (three outputs) by the GP-timer compares.
compare/PWMs characteristics
Characteristics of the compare/PWMs are as follow:
D16-bit, 50-ns resolutions
DProgrammable deadband for the PWM output pairs, from 0 to 102 ms
DMinimum deadband width of 50 ns
DChange of the PWM carrier frequency for PWM frequency wobbling as needed
DChange of the PWM pulse widths within and after each PWM period as needed
DExternal maskable power and drive-protection interrupts
DPulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
DMinimized CPU overhead using auto-reload of the compare and period registers
capture unit
The capture unit provides a logging function for different events or transitions. The values of the GP timer 2
counter and/or GP timer 3 counter are captured and stored in the two-level first-in first-out (FIFO) stacks when
selected transitions are detected on capture input pins, CAPx for x = 1, 2, 3, or 4. The capture unit of the
TMS320F240 consists of four capture circuits.
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capture unit (continued)
DThe capture unit includes the following features:
–One 16-bit capture-control register, CAPCON, for reads or writes
–One 16-bit capture-FIFO status register, CAPFIFO, with eight MSBs for read-only operations, and eight
LSBs for write-only operations
–Optional selection of GP timer 2 and/or GP timer 3 through two 16-bit multiplexers (MUXs). One MUX
selects a GP timer for capture circuits 3 and 4, and the other MUX selects a GP timer for capture
circuits 1 and 2.
–Four 16 bit x 2 FIFO stack registers, one two-level FIFO stack register per capture circuit. The top
register of each stack is a read-only register, FIFOx, where x = 1, 2, 3, or 4.
–Four capture-input pins (CAPx, x = 1 to 4) with one input pin per capture unit
–The input pins CAP1 and CAP2 also can be used as inputs to the QEP circuit.
–User-specified edge-detection mode at the input pins
–Four maskable interrupts/flags, CAPINTx, where x = 1, 2, 3, or 4
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2) can be used to interface the on-chip QEP circuit with a quadrature
encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse
sequence is detected, and GP timer 2 or 3 is incremented or decremented by the rising and falling edges of the
two input signals (four times the frequency of either input pulse).
analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 12. The ADC module consists of
two 10-bit ADCs with two built-in sample-and-hold (S/H) circuits. A total of 16 analog input channels is available
on the TMS320F240. Eight analog inputs are provided for each ADC unit by way of an 8-to-1 analog multiplexer .
Minimum total conversion time for each ADC unit is 6.1 ms. Total accuracy for each converter is ±1.5 LSB.
Reference voltage for the ADC module needs to be supplied externally through the two reference pins, VREFHI
and VREFLO. The digital result is expressed as:
Digital Value +1023 Input Analog Voltage *VREFLO
VREFHI *VREFLO
Functions of the ADC module include:
DTwo input channels (one for each ADC unit) that can be sampled and converted simultaneously
DEach ADC unit can perform single or continuous S/H and conversion operations.
DTwo 2-level-deep FIFO result registers for ADC units 1 and 2
DADC module (both A/D converters) can start operation by software instruction, external signal transition on
a device pin, or by event-manager events on each of the GP timer/compare output and the
capture 4 pins.
DThe ADC control register is double-buffered (with shadow register) and can be written to at any time. A new
conversion of ADC can start immediately or when the previous conversion process is completed according
to the control register bits.
DAt the end of each conversion, an interrupt flag is set and an interrupt is generated if it is unmasked/enabled.
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analog-to-digital converter (ADC) module (continued)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
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ÁÁÁÁÁ
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ÁÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Control Register
(1)
Control Register
(2)
Control Register
Sample-
and-
Hold (S/H)
Circuit
8/1
MUX
Control Logic
Single/Continues/Event Operations
VREF
VREF
VREFHI
Interrupts Sleep Mode
External (I/O) Start Pin
Internal (EV Module) Start Signal
10-Bit
A/D
Converter
Converter
A/D
10-Bit
Program Clock
Prescaler
Internal Bus
Sample-
and-
Hold (S/H)
Circuit
8/1
MUX
ADC0/IO
ADC1/IO
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8/IO
ADC9/IO
ADC10
ADC11
ADC12
ADC13
ADC14
ADC15
VREFLO
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Supply Voltage
VSSA VCCA
Figure 12. Analog-to-Digital Converter Module
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial peripheral interface (SPI) module
The TMS320F240 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed
synchronous serial-I/O port that allows a serial bit stream of programmed length (one to eight bits) to be shifted
into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSP controller and external peripherals or another processor. Typical applications include external
I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include the following:
DFour external pins:
–SPISOMI: SPI slave-output/master-input pin, or general-purpose bidirectional I/O pin
–SPISIMO: SPI slave-input/master-output pin, or general-purpose bidirectional I/O pin
–SPISTE: SPI slave-transmit-enable pin, or general-purpose bidirectional I/O pin
–SPICLK: SPI serial-clock pin, or general-purpose bidirectional I/O pin
DTwo operational modes: master and slave
DBaud rate: 125 different programmable rates / 2.5 Mbps at 10-MHz SYSCLK
DData word format: one to eight data bits
DFour clocking schemes controlled by clock polarity and clock-phase bits include:
–Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
–Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
–Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
–Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
DSimultaneous receive and transmit operations (transmit function can be disabled in software)
DTransmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
DTen SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register
data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
Figure 13 is a block diagram of the SPI in slave mode.
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serial peripheral Interface (SPI) module (continued)
S
S
SPIPC1.3–0
CLOCK
POLARITY
TALK
SYSCLK
456
012
SPI BIT RATE
State Control
SPIBUF
Buffer Register
8
CLOCK
PHASE
1230
RECEIVER
OVERRUN
SPICTL.4
OVERRUN
INT ENA
SPICCR.2–0
SPIBRR.6–0 SPICCR.6 SPICTL.3
SPIBUF.7–0
SPIDAT.7–0
SPICTL.1
M
S
M
MASTER/SLAVE†
SPI INT FLAG
SPICTL.0
SPI INT
ENA
SPIPC2.7–4
SPIPC2.3–0
SPISTS.7
SPIDAT
Data Register
SPISTS.6
M
S
SPIPC1.5
SPICTL.2
SPI CHAR
External
Connections
SPISIMO
SPISOMI
SPIPC1.7–4
SPISTE
SPICLK
SW2
S
M
M
S
SW3
To CPU
SPISTE
FUNCTION‡
M
SW1
SPIPRI.6
SPI Priority
Level 1
INT
1
0
Level 6
INT
†The diagram is shown in the slave mode.
‡The SPISTE pin is shown as being disabled, meaning that data cannot be transmitted in this mode. Note that SW1, SW2, and SW3 are closed
in this configuration.
Figure 13. Four-Pin Serial Peripheral Interface Module Block Diagram†
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial communications interface (SCI) module
The TMS320F240 device includes a serial communications interface (SCI) module. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate (baud) is programmable to over 65000 different speeds through a 16-bit baud-select register .
Features of the SCI module include:
DTwo external pins
–SCITXD: SCI transmit-output pin or general-purpose bidirectional I/O pin
–SCIRXD: SCI receive-input pin or general-purpose bidirectional I/O pin
DBaud rate programmable to 64K different rates
–Up to 625 Kbps at 10-MHz SYSCLK
DData word format
–One start bit
–Data word length programmable from one to eight bits
–Optional even/odd/no parity bit
–One or two stop bits
DFour error-detection flags: parity, overrun, framing, and break detection
DTwo wake-up multiprocessor modes: idle-line and address bit
DHalf- or full-duplex operation
DDouble-buffered receive and transmit functions
DTransmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
–Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
–Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR (monitoring four interrupt conditions)
DSeparate enable bits for transmitter and receiver interrupts (except BRKDT)
DNRZ (non return-to-zero) format
DEleven SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are interfaced to the 16-bit peripheral bus. When a register is accessed, the register
data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
Figure 14 shows the SCI module block diagram.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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serial communications interface (SCI) module (continued)
SYSCLK
WUT
Frame Format and Mode
EVEN/ODD ENABLE
PARITY
SCI RX Interrupt
BRKDT
SCICTL1.1
RXRDY
SCIRXST.6
SCICTL1.3 External
Connections
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCIPC2.7–4
SCITXD
RXENA
SCIPC2.3–0
SCIRXD
CLOCK ENA
SCICTL1.4
RXWAKE
SCICTL1.0
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
TXINT
SCICCR.6 SCICCR.5
SCITXBUF.7–0
SCIHBAUD. 15–8
Baud Rate
Register
(MSbyte)
SCILBAUD. 7–0
SCIRXBUF.7–0
Receiver-Data
Buffer
Register
SCIRXST.7
PEFE OE
RX ERROR
RX ERROR
SCIRXST.4–2
Transmitter-Data
Buffer Register
8SCICTL2.6
SCICTL2.7
Baud Rate
Register
(LSbyte)
RXSHF
Register
TXSHF
Register
SCIRXST.5
RXINT
1
SCIPRI.5
SCIPRI.6
SCI PRIORITY LEVEL
Level 2 Int.
Level 1 Int.
Level 2 Int.
Level 1 Int.
1
0
1
0
SCI TX
PRIORITY
SCI RX
PRIORITY
Figure 14. Serial Communications Interface (SCI) Module Block Diagram
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
watchdog (WD) and real-time interrupt (RTI) module
The TMS320F240 device includes a watchdog (WD) timer and a real-time interrupt (RTI) module. The WD
function of this module monitors software and hardware operation by generating a system reset if it is not
periodically serviced by software by having the correct key written. The RTI function provides interrupts at
programmable intervals. See Figure 15 for a block diagram of the WD/RTI module. The WD/RTI module
features include the following:
DWD Timer
–Seven different WD overflow rates ranging from 15.63 ms to 1 s
–A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and
generates a system reset if an incorrect value is written to the register
–A WD flag (WD FLAG) that indicates whether the WD timer initiated a system reset
–WD check bits that initiate a system reset if an incorrect value is written to the WD control register
(WDCR)
DAutomatic activation of the WD timer, once system reset is released
–Three WD control registers located in control register frame beginning at address 7020h.
DReal-time interrupt (RTI):
–Interrupt generation at a programmable frequency of 1 to 4096 interrupts per second
–Interrupt or polled operation
–Two RTI control registers located in control register frame beginning at address 7020h.
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register
data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
Figure 15 shows the WD/RTI block diagram.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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watchdog (WD) and real-time interrupt (RTI) module (continued)
55 + AA
Detector
D
CLR
System
Reset
Request
WDCNTR.7–0
QINT Request
(Level 1 Only)
/16384
/2048
/512
/256
111
110
101
100
011
010
000
001
CLR
8-Bit
Real-Time
Counter
7-Bit
Free-
Running
Counter
/128
/64
/32
/16
/8
/4
/2
111110
101
100
011
010
001
000
Any
Write
16-kHz
WDCLK
System
Reset
System Reset
CLR
CLR
One-Cycle
Delay
Watchdog
Reset Key
Register
8-Bit Watchdog
Counter
CLR
RTICNTR.7–0
D
CLR
Q
INT Acknowledge
Bad WDCR Key
Good Key
Bad Key
WDPS
WDCR.2–0
210
WDKEY.7–0
WDCHK2–0
WDCR.5–3†
WDCR.7
WD FLAG Reset Flag
RTIPS
RTICR.2–0
210
RTICR.7
RTI FLAG
Clear
RTI Flag
RTICR.7
RTI FLAG
Read
RTI Flag
RTICR.7
RTI FLAG Clear
RTI Flag
RTICR.6
RTI ENA
PS/257
WDDIS
WDCR.6
101
(Constant
Value)
3
3
†Writing to bits WDCR.5–3 with anything but the correct pattern (101) generates a system reset.
Figure 15. WD/RTI Module Block Diagram
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
scan-based emulation
TMS320F240 device uses scan-based emulation for code- and hardware-development support. Serial scan
interface is provided by the test-access port. Scan-based emulation allows the emulator to control the processor
in the system without the use of intrusive cables to the full pinout of the device.
TMS320F240 instruction set
The F240 microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the C1x and C2x DSPs is upwardly compatible with the x2xx devices.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The TMS320F240 instruction set provides four basic memory-addressing modes: direct, indirect, immediate,
and register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged e ffectively with a total of 512 pages, each page
containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by adding or
subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed
addressing [used in Fast Fourier Transforms (FFTs)] with increment or decrement. All operations are performed
on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary
register and ARP can be modified.
In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There
are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained
in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the
second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need
to be stored or used more than once during the course of program execution (for example, initialization values
or constants).
The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference
to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case,
operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand
address or immediate value.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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repeat feature
The repeat function can be used with instructions (as defined in Table 14) such as multiply/accumulates (MAC
and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW).
These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they
effectively become single-cycle instructions. For example, the table-read instruction can take three or more
cycles to execute, but when the instruction is repeated, a table location can be read every cycle.
The repeat counter (RPTC) is loaded with the addressed data-memory location if direct or indirect addressing
is used, and with an 8-bit immediate value if short-immediate addressing is used. The RPTC register is loaded
by the RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC is cleared
by reset. Once a repeat instruction (RPT) is decoded, all interrupts, including NMI (but excluding reset), are
masked until the completion of the repeat loop.
instruction set summary
This section summarizes the operation codes (opcodes) of the instruction set for the F240 digital signal
processors. This instruction set is a superset of the C1x and C2x instruction sets. The instructions are arranged
according to function and are alphabetized by mnemonic within each category. The symbols in Table 13 are
used in the instruction set summary table (Table 14). The TI C2xx assembler accepts C2x instructions.
The number of words that an instruction occupies in program memory is specified in column 3 of Table 14.
Several instructions specify two values separated by a slash mark (/) for the number of words. In these cases,
different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies
one word when the operand is a short-immediate value or two words if the operand is a long-immediate value.
The number of cycles that an instruction requires to execute is also in column 3 of Table 14. All instructions are
assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The
cycle timings are for single-instruction execution, not for repeat mode.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
instruction set summary (continued)
Table 13. TMS320F240 Opcode Symbols
SYMBOL DESCRIPTION
A Address
ACC Accumulator
ACCB Accumulator buffer
ARx Auxiliary register value (0–7)
BITx 4-bit field that specifies which bit to test for the BIT instruction
BMAR Block-move address register
DBMR Dynamic bit-manipulation register
IAddressing-mode bit
II...II Immediate operand value
INTM Interrupt-mode flag bit
INTR# Interrupt vector number
K Constant
PREG Product register
PROG Program memory
RPTC Repeat counter
SHF, SHFT 3/4-bit shift value
TC Test-control bit
T P
Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO.
T P Meaning
0 0 BIO low
0 1 TC=1
1 0 TC=0
1 1 None of the above conditions
TREGn Temporary register n (n = 0, 1, or 2)
Z L V C
4-bit field representing the following conditions:
Z: ACC = 0
L: ACC < 0
V: Overflow
C: Carry
A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the
corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4–7) indicates the state of
the conditions designated by the mask bits as being tested. For example, to test for ACC ≥ 0, the Z and L fields are set while
the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate
testing of the condition ACC = 0, and the L field is reset to indicate testing of the condition ACC ≥ 0. The conditions possible
with these 8 bits are shown in the BCND and CC instructions. To determine if the conditions are met, the 4-LSB bit mask
is ANDed with the conditions. If any bits are set, the conditions are met.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
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instruction set summary (continued)
Table 14. TMS320F240 Instruction Set Summary
F240
DESCRIPTION
WORDS/ OPCODE
F240
MNEMONIC DESCRIPTION
WORDS/
CYCLES MSB LSB
ABS Absolute value of accumulator 1/1 1011 1110 0000 0000
Add to accumulator with shift 1/1 0010 SHFT IADD RESS
ADD
Add to high accumulator 1/1 0110 0001 IADD RESS
ADD Add to accumulator short immediate 1/1 1011 1000 KKKK KKKK
Add to accumulator long immediate with shift 2/2 1011 1111 1001 SHFT
ADDC Add to accumulator with carry 1/1 0110 0000 IADD RESS
ADDS Add to low accumulator with sign extension suppressed 1/1 0110 0010 IADD RESS
ADDT Add to accumulator with shift specified by T register 1/1 0110 0011 IADD RESS
ADRK Add to auxiliary register short immediate 1/1 0111 1000 KKKK KKKK
AND with accumulator 1/1 0110 1110 IADD RESS
AND immediate with accumulator with shift
2/2
1011 1111 1011 SHFT
AND
AND
i
mme
di
ate w
i
t
h
accumu
l
ator w
i
t
h
s
hif
t
2/2
16-Bit Constant
AND
AND immediate with accumulator with shift of 16
2/2
1011 1110 1000 0001
AND
i
mme
di
ate w
i
t
h
accumu
l
ator w
i
t
h
s
hif
t o
f
16
2/2
16-Bit Constant
APAC Add P register to accumulator 1/1 1011 1110 0000 0100
B
Branch unconditionally
2/4
0111 1001 IADD RESS
B
B
ranc
h
uncon
di
t
i
ona
ll
y
2/4
Branch Address
BACC Branch to address specified by accumulator 1/4 1011 1110 0010 0000
BANZ
Branch on auxiliary register not zero
2/4/2
0111 1011 IADD RESS
BANZ
B
ranc
h
on aux
ili
ary reg
i
ster not zero
2/4/2
Branch Address
Branch if TC bit ≠0
2/4/2
1110 0001 0000 0000
B
ranc
h
if
TC
bi
t ≠
0
2/4/2
Branch Address
Branch if TC bit = 0
2/4/2
1110 0010 0000 0000
B
ranc
h
if
TC
bi
t =
0
2/4/2
Branch Address
Branch on carry
2/4/2
1110 0011 0001 0001
B
ranc
h
on carry
2/4/2
Branch Address
Branch if accumulator ≥0
2/4/2
1110 0011 1000 1100
B
ranc
h
if
accumu
l
ator ≥
0
2/4/2
Branch Address
Branch if accumulator >0
2/4/2
1110 0011 0000 0100
B
ranc
h
if
accumu
l
ator >
0
2/4/2
Branch Address
BCND
Branch on I/O status low
2/4/3
1110 0000 0000 0000
B
ranc
h
on
I/O
status
l
ow
2/4/3
Branch Address
Branch if accumulator ≤0
2/4/2
1110 0011 1100 1100
B
ranc
h
if
accumu
l
ator ≤
0
2/4/2
Branch Address
Branch if acc m lator 0
2/4/2
1110 0011 0100 0100
Branch if accumulator < 0 2/4/2 Branch Address
Branch on no carr
2/4/2
1110 0011 0000 0001
Branch on no carry 2/4/2 Branch Address
Branch if no o erflo
2/4/2
1110 0011 0000 0010
Branch if no overflow 2/4/2 Branch Address
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instruction set summary (continued)
Table 14. TMS320F240 Instruction Set Summary (Continued)
F240
DESCRIPTION
WORDS/ OPCODE
F240
MNEMONIC DESCRIPTION
WORDS/
CYCLES MSB LSB
Branch if acc m lator ≠0
2/4/2
1110 0011 0000 1000
Branch if accumulator ≠ 0 2/4/2 Branch Address
BCND
Branch on o erflo
2/4/2
1110 0011 0010 0010
BCND Branch on overflow 2/4/2 Branch Address
Branch if acc m lator 0
2/4/2
1110 0011 1000 1000
Branch if accumulator = 0 2/4/2 Branch Address
BIT Test bit 1/1 0100 BITx IADD RESS
BITT Test bit specified by TREG 1/1 0110 1111 IADD RESS
Block mo e from data memor to data memor so rce immediate
2/3
1010 1000 IADD RESS
BLDD†
Block move from data memory to data memory source immediate 2/3 Branch Address
BLDD
†
Block mo e from data memor to data memor destination immediate
2/3
1010 1001 IADD RESS
Block move from data memory to data memory destination immediate 2/3 Branch Address
BLPD
Block move from program memory to data memory
2/3
1010 0101 IADD RESS
BLPD Block move from program memory to data memory 2/3 Branch Address
CALA Call subroutine indirect 1/4 1011 1110 0011 0000
CALL
Call s bro tine
2/4
0111 1010 IADD RESS
CALL Call subroutine 2/4 Routine Address
CC
Conditional call subroutine
2/4/2
1110 10TP ZLVC ZLVC
CC Conditional call subroutine 2/4/2 Routine Address
Configure block as data memory 1/1 1011 1110 0100 0100
Enable interrupt 1/1 1011 1110 0100 0000
Reset carry bit 1/1 1011 1110 0100 1110
CLRC Reset overflow mode 1/1 1011 1110 0100 0010
CLRC
Reset sign-extension mode 1/1 1011 1110 0100 0110
Reset test/control flag 1/1 1011 1110 0100 1010
Reset external flag 1/1 1011 1110 0100 1100
CMPL Complement accumulator 1/1 1011 1110 0000 0001
CMPR Compare auxiliary register with auxiliary register AR0 1/1 1011 1111 0100 01CM
DMOV Data move in data memory 1/1 0111 0111 IADD RESS
IDLE Idle until interrupt 1/1 1011 1110 0010 0010
IN
Inp t data from port
2/2
1010 1111 IADD RESS
IN Input data from port 2/2 16BIT I/O PORT ADRS
INTR Software-interrupt 1/4 1011 1110 011K KKKK
Load accumulator with shift 1/1 0001 SHFT IADD RESS
LACC
Load acc m lator long immediate ith shift
2/2
1011 1111 1000 SHFT
LACC Load accumulator long immediate with shift 2/2 16-Bit Constant
Zero low accumulator and load high accumulator 1/1 0110 1010 IADD RESS
†In x240 devices, the BLDD instruction does not work with memory-mapped registers IMR, IFR, and GREG.
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instruction set summary (continued)
Table 14. TMS320F240 Instruction Set Summary (Continued)
F240
DESCRIPTION
WORDS/ OPCODE
F240
MNEMONIC DESCRIPTION
WORDS/
CYCLES MSB LSB
Load accumulator immediate short 1/1 1011 1001 KKKK KKKK
LACL
Zero accumulator 1/1 1011 1001 0000 0000
LACL Zero low accumulator and load high accumulator 1/1 0110 1010 IADD RESS
Zero low accumulator and load low accumulator with no sign extension 1/1 0110 1001 IADD RESS
LACT Load accumulator with shift specified by T register 1/1 0110 1011 IADD RESS
Load auxiliary register 1/2 0000 0ARx IADD RESS
LAR
Load auxiliary register short immediate 1/2 1011 0ARx KKKK KKKK
LAR
Load auxiliary register long immediate
2/2
1011 1111 0000 1ARx
Load auxiliary register long immediate 2/2 16-Bit Constant
LDP
Load data-memory page pointer 1/2 0000 1101 IADD RESS
LDP Load data-memory page pointer immediate 1/2 1011 110P AGEP OINT
LPH Load high-P register 1/1 0111 0101 IADD RESS
LST
Load status register ST0 1/2 0000 1110 IADD RESS
LST Load status register ST1 1/2 0000 1111 IADD RESS
LT Load TREG 1/1 0111 0011 IADD RESS
LTA Load TREG and accumulate previous product 1/1 0111 0000 IADD RESS
LTD Load TREG, accumulate previous product, and move data 1/1 0111 0010 IADD RESS
LTP Load TREG and store P register in accumulator 1/1 0111 0001 IADD RESS
LTS Load TREG and subtract previous product 1/1 0111 0100 IADD RESS
MAC
Multiply and accumulate
2/3
1010 0010 IADD RESS
MAC Multiply and accumulate 2/3 16-Bit Constant
MACD
M ltipl and acc m late ith data mo e
2/3
1010 0011 IADD RESS
MACD Multiply and accumulate with data move 2/3 16-Bit Constant
MAR
Load auxiliary register pointer 1/1 1000 1011 1000 1ARx
MAR Modify auxiliary register 1/1 1000 1011 IADD RESS
MPY
Multiply (with TREG, store product in P register) 1/1 0101 0100 IADD RESS
MPY Multiply immediate 1/1 110C KKKK KKKK KKKK
MPYA Multiply and accumulate previous product 1/1 0101 0000 IADD RESS
MPYS Multiply and subtract previous product 1/1 0101 0001 IADD RESS
MPYU Multiply unsigned 1/1 0101 0101 IADD RESS
NEG Negate accumulator 1/1 1011 1110 0000 0010
NMI Nonmaskable interrupt 1/4 1011 1110 0101 0010
NOP No operation 1/1 1000 1011 0000 0000
NORM Normalize contents of accumulator 1/1 1010 0000 IADD RESS
OR with accumulator 1/1 0110 1101 IADD RESS
OR immediate ith acc m lator ith shift
2/2
1011 1111 1100 SHFT
OR OR immediate with accumulator with shift 2/2 16-Bit Constant
OR
OR immediate with accumulator with shift of 16
2/2
1011 1110 1000 0010
OR immediate with accumulator with shift of 16 2/2 16-Bit Constant
OUT Output data to port 2/3 0000
16BIT 1100
I/O IADD
PORT RESS
ADRS
PAC Load accumulator with P register 1/1 1011 1110 0000 0011
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instruction set summary (continued)
Table 14. TMS320F240 Instruction Set Summary (Continued)
F240
DESCRIPTION
WORDS/ OPCODE
F240
MNEMONIC DESCRIPTION
WORDS/
CYCLES MSB LSB
POP Pop top of stack to low accumulator 1/1 1011 1110 0011 0010
POPD Pop top of stack to data memory 1/1 1000 1010 IADD RESS
PSHD Push data-memory value onto stack 1/1 0111 0110 IADD RESS
PUSH Push low accumulator onto stack 1/1 1011 1110 0011 1100
RET Return from subroutine 1/4 1110 1111 0000 0000
RETC Conditional return from subroutine 1/4/2 1110 11TP ZLVC ZLVC
ROL Rotate accumulator left 1/1 1011 1110 0000 1100
ROR Rotate accumulator right 1/1 1011 1110 0000 1101
RPT
Repeat instruction as specified by data-memory value 1/1 0000 1011 IADD RESS
RPT Repeat instruction as specified by immediate value 1/1 1011 1011 KKKK KKKK
SACH Store high accumulator with shift 1/1 1001 1SHF IADD RESS
SACL Store low accumulator with shift 1/1 1001 0SHF IADD RESS
SAR Store auxiliary register 1/1 1000 0ARx IADD RESS
SBRK Subtract from auxiliary register short immediate 1/1 0111 1100 KKKK KKKK
Set carry bit 1/1 1011 1110 0100 1111
Configure block as program memory 1/1 1011 1110 0100 0101
Disable interrupt 1/1 1011 1110 0100 0001
SETC Set overflow mode 1/1 1011 1110 0100 0011
SETC
Set test/control flag 1/1 1011 1110 0100 1011
Set external flag XF 1/1 1011 1110 0100 1101
Set sign-extension mode 1/1 1011 1110 0100 0111
SFL Shift accumulator left 1/1 1011 1110 0000 1001
SFR Shift accumulator right 1/1 1011 1110 0000 1010
SPAC Subtract P register from accumulator 1/1 1011 1110 0000 0101
SPH Store high-P register 1/1 1000 1101 IADD RESS
SPL Store low-P register 1/1 1000 1100 IADD RESS
SPM Set P register output shift mode 1/1 1011 1111 IADD RESS
SQRA Square and accumulate 1/1 0101 0010 IADD RESS
SQRS Square and subtract previous product from accumulator 1/1 0101 0011 IADD RESS
SST
Store status register ST0 1/1 1000 1110 IADD RESS
SST Store status register ST1 1/1 1000 1111 IADD RESS
SPLK
Store long immediate to data memor
2/2
1010 1110 IADD RESS
SPLK Store long immediate to data memory 2/2 16-Bit Constant
S btract from acc m lator long immediate ith shift
2/2
1011 1111 1010 SHFT
Subtract from accumulator long immediate with shift 2/2 16-Bit Constant
SUB Subtract from accumulator with shift 1/1 0011 SHFT IADD RESS
SUB
Subtract from high accumulator 1/1 0110 0101 IADD RESS
Subtract from accumulator short immediate 1/1 1011 1010 KKKK KKKK
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instruction set summary (continued)
Table 14. TMS320F240 Instruction Set Summary (Continued)
F240
DESCRIPTION
WORDS/ OPCODE
F240
MNEMONIC DESCRIPTION
WORDS/
CYCLES MSB LSB
SUBB Subtract from accumulator with borrow 1/1 0110 0100 IADD RESS
SUBC Conditional subtract 1/1 0000 1010 IADD RESS
SUBS Subtract from low accumulator with sign extension suppressed 1/1 0110 0110 IADD RESS
SUBT Subtract from accumulator with shift specified by TREG 1/1 0110 0111 IADD RESS
TBLR Table read 1/3 1010 0110 IADD RESS
TBLW Table write 1/3 1010 0111 IADD RESS
TRAP Software interrupt 1/4 1011 1110 0101 0001
Exclusive-OR with accumulator 1/1 0110 1100 IADD RESS
E cl si e OR immediate ith acc m lator ith shift
2/2
1011 1111 1101 SHFT
XOR Exclusive-OR immediate with accumulator with shift 2/2 16-Bit Constant
XOR
E cl si e OR immediate ith acc m lator ith shift of 16
2/2
1011 1110 1000 0011
Exclusive-OR immediate with accumulator with shift of 16 2/2 16-Bit Constant
ZALR Zero low accumulator and load high accumulator with rounding 1/1 0110 1000 IADD RESS
development support
Texas Instruments offers an extensive line of development tools for the x240 generation of DSPs, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of x240-based applications:
Software Development Tools:
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Emulator XDS510 (supports x240 multiprocessor system debug)
See Table 15 and Table 16 for complete listings of development-support tools for the F240. For information on
pricing and availability, contact the nearest TI field sales office or authorized distributor.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
development support (continued)
Table 15. Development Support Tools
DEVELOPMENT TOOL PLATFORM PART NUMBER
Software – Code Generation Tools
Assembler/Linker PC, Windows 95 TMDS3242850-02
C Compiler/Assembler/Linker PC, Windows 95 TMDS3242855-02
Software – Emulation Debug Tools
LF2407 eZdspPC TMDS3P761119
Code Composer 4.12, Code Generation 7.0 PC TMDS324012xx
Hardware – Emulation Debug Tools
XDS510XL Board (ISA card), w/JTAG cable PC TMDS00510
XDS510PP Pod (Parallel Port) w/JTAG cable PC TMDS00510PP
Table 16. TMS320F240-Specific Development Tools
DEVELOPMENT TOOL PLATFORM PART NUMBER
Hardware – Evaluation/Starter Kits
TMS320LF2407A EVM PC, Windows 95, Windows 98 TMDX3P701016
TMS320F240 EVM PC TMDX326P124X
TMS320F243 EVM PC, Windows 95 TMDS3P604030
device and development-support tool nomenclature
To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part
numbers of all TMS320 DSP devices and support tools. Each TMS320 member has one of three prefixes:
TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This
development flow is defined below.
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development support product that has not completed TI’s internal qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
XDS510XL, XDS510PP, and TMS320 are trademarks of Texas Instruments.
PC is a trademark of International Business Machines Corp.
Windows is a registered trademark of Microsoft Corporation.
eZdsp is a trademark of Spectrum Digital, Inc.
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device and development-support tool nomenclature (continued)
TMS devices and TMDS development-support tools have been fully characterized, and the quality and reliability
of the device have been fully demonstrated. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate is still undefined. Only qualified production devices are to be used.
TI device nomenclature also i n c l udes a suffix with the device family name. This suffix indicates the package type
(for example, PN, PQ, and PZ) and temperature range (for example, L). Figure 16 provides a legend for reading
the complete device name for any TMS320x2xx family member.
PREFIX TEMPERATURE RANGE (DEFAULT: 0°C TO 70°C)
TMS 320 C 240 PQ (L)
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
DEVICE FAMILY
320 = TMS320 Family
TECHNOLOGY
L=0°C to 70°C
A=–40°C to 85°C
S=–40°C to 125°C
Q=–40°C to 125°C, Q 100 Fault Grading
PACKAGE TYPE†
PN = 80-pin plastic TQFP
PQ = 132-pin plastic bumpered QFP
PZ = 100-pin plastic TQFP
C = ROM
F = Flash EEPROM
DEVICE
C2xx DSP209
203
241
242
F2xx DSP206
240
241
243
†TQFP = Thin Quad Flat Package
Figure 16. TMS320 Device Nomenclature
documentation support
Extensive documentation supports all of the TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include: data sheets, such as this
document, with design specifications; complete user’s guides for all devices and development-support tools;
and hardware and software applications. To receive copies of TMS320 literature, contact the Literature
Response Center at 800/477-8924.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to
update TMS320 customers on product information. The TMS320 DSP bulletinboard service (BBS) provides
access to a wealth of information pertaining to the TMS320 family, including documentation, source code, and
object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD‡–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A version –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S, Q versions –40°C to125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VDD Supply voltage 4.5 5 5.5 V
VSS Supply ground 0 V
XTAL1/CLKIN 3 VDD + 0.3
VIH High-level input voltage PORESET, NMI, RS, and TRST 2.2 VDD + 0.3 V
IH
gg
All other inputs 2 VDD + 0.3
V
Low level input voltage
XTAL1/CLKIN –0.3 0.7
V
VIL Low-level input voltage All other inputs –0.3 0.8 V
RS –19
IOH High-level output current, VOH = 2.4 V See complete listing of pin names§–16 mA
IOH
High level
out ut
current,
VOH
2.4
V
All other outputs –23
mA
RS 8
IOL Low-level output current, VOL = 0.6 V See complete listing of pin names§7.5 mA
IOL
Low level
out ut
current,
VOL
0.6
V
All other outputs 14.5
mA
L version 0 70
TAOperating free-air temperature A version –40 85 °C
A
g
S, Q versions –40 125
TFP Flash programming operating temperature L, A, S, Q versions –40 85 °C
ΘJA Thermal resistance, junction-to-ambient 40 °C/W
ΘJC Thermal resistance, junction-to-case 9.9 °C/W
§IOPA[0:3], SCIRXD/IO, SCITXD/IO, XINT2/IO, XINT3/IO, ADCSOC/IOPC0, TMRDIR/IOPB6, TMRCLK/IOPB7 EMU0, EMU1/OFF
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output current variation with output voltage: SPICE simulation results
Condition: Temperature
Voltage : 150° C
: 4.5 V
Table 17. Typical Output Source Current vs. Output Voltage High
24V
30V
35V
40V
2.4 V 3.0 V 3.5 V 4.0 V
RS –19 mA –16 mA –12 mA –6 mA
See complete listing of pin names†–16 mA –13.5 mA –9.5 mA –5.0 mA
All other inputs –23 mA –18.5 mA –13 mA –6.5 mA
†IOPA[0:3], SCIRXD/IO, SCITXD/IO, XINT2/IO, XINT3/IO, ADCSOC/IOPC0, TMRDIR/IOPB6, TMRCLK/IOPB7 EMU0, EMU1/OFF
Table 18. Typical Output Sink Current vs. Output Voltage Low
06V
04V
02V
0.6 V 0.4 V 0.2 V
RS 8 mA 6 mA 3 mA
See complete listing of pin names†7.5 mA 5 mA 2.5 mA
All other inputs 14.5 mA 10 mA 5.0 mA
†IOPA[0:3], SCIRXD/IO, SCITXD/IO, XINT2/IO, XINT3/IO, ADCSOC/IOPC0, TMRDIR/IOPB6, TMRCLK/IOPB7 EMU0, EMU1/OFF
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage 5-V operation, IOH = MAX 2.4 V
VOL Low-level output voltage 5-V operation, IOL = MAX 0.6 V
TRST pin with internal pulldown –10 500
IIInput current (VI = VSS or VDD)EMU0, EMU1/OFF, TMS, TCK, and TDI,
with internal pullup –500 10 µA
All other input pins –10 10
IOZ Output current, high-impedance state (off-state) VO = VDD or 0 V –5 5 µA
Supply current, operating mode 5-V operation, tc(CO) = 50 ns 80
Supply current, Idle 1 low-power mode 5-V operation, tc(CO) = 50 ns 50
mA
IDD Supply current, Idle 2 low-power mode 5-V operation, tc(CO) = 50 ns 7mA
IDD
Supply current, PLL power-down mode 5-V operation, tc(CO) = 50 ns 1
Supply current, OSC power-down mode 5-V operation, tc(CO) = 50 ns 400 µA
CiInput capacitance 15 pF
CoOutput capacitance 15 pF
IDDP Flash programming supply current 5-V operation, tc(CO) = 50 ns 10 mA
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PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50 Ω
Where: IOL = 2 mA (all outputs)
IOH = 300 µA (all outputs)
VLOAD = 1.5 V
CT= 110-pF typical load-circuit capacitance
Figure 17. Test Load Circuit
signal transition levels
The data in this section is shown for the 5-V version (C2xx). Note that some of the signals use different reference
voltages, see the recommended operating conditions table. TTL-output levels are driven to a minimum
logic-high level of 2.4 V and to a maximum logic-low level of 0.7 V.
Figure 18 shows the TTL-level outputs.
0.7 V
20%
2.4 V
80%
Figure 18. TTL-Level Outputs
TTL-compatible output transition times are specified as follows:
DFor a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower, and the level at which the output is said to be low is 20% of the total voltage
range and lower.
DFor a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher, and the level at which the output is said to be high is 80% of the total voltage range and
higher.
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PARAMETER MEASUREMENT INFORMATION
Figure 19 shows the TTL-level inputs.
0.7 V
10%
2.0 V
90%
Figure 19. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
DFor a high-to-low transition on a n input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower, and the level at which the input is said to be low is 10% of the total
voltage range and lower.
DFor a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher, and the level at which the input is said to be high is 90% of the total
voltage range and higher.
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PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
T iming parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
A A[15:0] MS Memory strobe pins IS, DS, or PS
Cl XTAL1/CLKIN R READY
CO CLKOUT/IOPC1 RD Read cycle or W/R
D D[15:0] RS RS or PORESET
INT NMI, XINT1, XINT2/IO, and XINT3/IO W Write cycle or WE
Lowercase subscripts and their meanings: Letters and symbols and their meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don’t care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
general notes on timing parameters
All output signals from the TMS320F240 device (including CLKOUT) are derived from an internal clock such
that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this data sheet.
External
Clock Signal
(toggling 0–5 V)
C2
(see Note A)
C1
(see Note A) Crystal
XTAL2XTAL1/CLKIN XTAL1/CLKIN XTAL2
NC
See Note B
NOTES: A. For the values of C1 and C2, see the crystal manufacturer’s specification.
B. Use this configuration in conjunction with OSCBYP pin pulled low.
C. Texas Instruments recommends that customers have the resonator/crystal vendor characterize the operation of their device with
the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise
the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 20. Recommended Crystal/Clock Connection
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CLOCK OPTIONS
clock options
PARAMETER CLKMD[1:0]
Clock-in mode, divide-by-2 00
Clock-in mode, divide-by-1 01
PLL enabled, divide-by-2 before PLL lock 10
PLL enabled, divide-by-1 before PLL lock 11
timings with the PLL circuit disabled
PARAMETER TEST CONDITIONS MIN MAX UNIT
fxInput clock frequency, divide-by-2 mode TA = –40°C to 125°C 0†40 MHz
fxInput clock frequency, divide-by-1 mode TA = –40°C to 125°C 0†20 MHz
†This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]
(see Note 1 and Figure 21)
PARAMETER CLOCK MODE MIN TYP MAX UNIT
t
C cle time CPUCLK
CLKIN divide by 2 2tc(Cl) †
ns
tc(CPU) Cycle time, CPUCLK CLKIN divide by 1 tc(Cl) ns
t
C cle time SYSCLK
CPUCLK divide by 2 2tc(CPU) †
ns
tc(SYS) Cycle time, SYSCLK CPUCLK divide by 4‡4tc(CPU) ns
t
C cle time CLKOUT
CLKIN divide by 2 2tc(Cl) †
ns
tc(CO) Cycle time, CLKOUT CLKIN divide by 1 tc(Cl) †ns
td(CIH-CO) Delay time, XTAL1/CLKIN high to CLKOUT high/low 3 18 32 ns
tf(CO) Fall time, CLKOUT 5 ns
tr(CO) Rise time, CLKOUT 5 ns
tw(COL) Pulse duration, CLKOUT low H–10 H–6 H–1 ns
tw(COH) Pulse duration, CLKOUT high H+0 H+4 H+8 ns
†This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
‡SYSCLK is initialized to divide-by-4 mode by any device reset.
NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
timing requirements over recommended operating conditions (see Figure 21)
CLOCK-IN MODE MIN MAX UNIT
t
C cle time XTAL1/CLKIN
Divide by 2 25 †
ns
tc(Cl) Cycle time, XTAL1/CLKIN Divide by 1 50 †ns
tf(Cl) Fall time, XTAL1/CLKIN 5 ns
tr(Cl) Rise time, XTAL1/CLKIN 5 ns
tw(CIL) Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl) 45 55 %
tw(CIH) Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl) 45 55 %
†This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
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CLOCK OPTIONS (CONTINUED)
tr(CO)
tf(CO)
tw(COH)
CLKOUT/IOPC1
XTAL1/CLKIN
tw(COL)
td(CIH–CO)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
tc(CO)
tc(CI)
Figure 21. External Divide-by-Two Clock Timings
external reference crystal with PLL-circuit-enabled clock option
The internal oscillator is enabled by connecting OSCBYP to VDD and connecting a crystal across XTAL1/CLKIN
and XTAL2 pins as shown in Figure 20. The crystal should be in either fundamental or overtone operation and
parallel resonant, with an effective series resistance of 30 W and a power dissipation of 1 mW; it should be
specified at a load capacitance of 20 pF.
timings with the PLL circuit enabled
PARAMETER EXTERNAL REFERENCE
CRYSTAL MIN TYP MAX UNIT
4 MHz 4
fxInput clock frequency 6 MHz 6MHz
fx
In ut
clock
frequency
8 MHz 8
MHz
C1, C2 Load capacitance 10 pF
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switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 22)
PARAMETER CLOCK MODE MIN TYP MAX UNIT
before PLL lock,
CLKIN divide by 2 2tc(Cl) †
tc(CPU) Cycle time, CPUCLK before PLL lock,
CLKIN divide by 1 tc(Cl) ns
after PLL lock 50
t
C cle time SYSCLK
CPUCLK divide by 2 2tc(CPU) †
ns
tc(SYS) Cycle time, SYSCLK CPUCLK divide by 4‡4tc(CPU) ns
tc(CO) Cycle time, CLKOUT 50 †ns
tf(CO) Fall time, CLKOUT 5 ns
tr(CO) Rise time, CLKOUT 5 ns
tw(COL) Pulse duration, CLKOUT low H–10 H–6 H–1 ns
tw(COH) Pulse duration, CLKOUT high H+0 H+4 H+8 ns
t
Transition time
,
PLL s
y
nchronized after before PLL lock,
CLKIN divide by 2 2000tc(Cl)
ns
tp
Transition
time
,
PLL
synchronized
after
PLL enabled before PLL lock,
CLKIN divide by 1 1000tc(Cl) ns
†This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
‡SYSCLK is initialized to divide-by-4 mode by any device reset.
timing requirements over recommended operating conditions (see Note 1 and Figure 22)
EXTERNAL REFERENCE
CRYSTAL MIN MAX UNIT
4 MHz 250 †
tc
(
Cl
)
Cycle time, XTAL1/CLKIN 6 MHz 167 ns
tc(Cl)
Cycle
time
,
XTAL1/CLKIN
8 MHz 125
ns
tf(Cl) Fall time, XTAL1/CLKIN 5 ns
tr(Cl) Rise time, XTAL1/CLKIN 5 ns
tw(CIL) Pulse duration, XTAL1/CLKIN low as a percentage of tc(CI) 40 60 %
tw(CIH) Pulse duration, XTAL1/CLKIN high as a percentage of tc(CI) 40 60 %
†This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
XTAL1/CLKIN
tc(CI)
tw(CIL)
tw(CIH)
tw(COL)
tw(COH)
tc(CO)
tf(Cl) tr(Cl)
tr(CO) tf(CO)
CLKOUT
Figure 22. CLKIN-to-CLKOUT Timings for PLL Oscillator Mode, Multiply-by-5 Option With 4-MHz Crystal
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low-power mode timings
switching characteristics over recommended operating conditions (see Figure 23, Figure 24,
Figure 25, and Figure 26)
PARAMETER LOW-POWER MODES MIN TYP MAX UNIT
t
Dela
y
time
,
CLKOUT switchin
g
to Idle 1 and Idle 2 15 X tc(CO)
ns
td(WAKE-A)
Delay
time
,
CLKOUT
switching
to
program execution resume (see Note 1) PLL or OSC power down 15 X tc(CI) ns
td(IDLE-COH) Delay time, Idle instruction executed to
CLKOUT high (see Note 1) Idle 2, PLL power down, OSC
power down 500 ns
td(WAKE-LOCK) Delay time, CLKOUT switching to PLL
synchronized (see Note 1) PLL or OSC power down 100 µs
td(WAKE-OSC) Delay time, wakeup interrupt asserted
to oscillator running OSC power down 10 ms
td(IDLE-OSC) Delay time, Idle instruction executed to
oscillator power off OSC power down 60 µs
NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
WAKE INT
CLKOUT/IOPC1
A0–A15
td(WAKE–A)
Figure 23. IDLE1 Entry and Exit Timings
td(WAKE–A)
td(IDLE–COH)
WAKE INT
CLKOUT/IOPC1
A0–A15
Figure 24. IDLE2 Entry and Exit Timings
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low-power mode timings (continued)
WAKE INT
CLKOUT/IOPC1
A0–A15
td(IDLE–COH) td(WAKE–LOCK)
td(WAKE–A)
Figure 25. PLL Power-Down Entry and Exit Timings
td(WAKE–A)
td(WAKE–LOCK)
td(WAKE–OSC)
td(IDLE–COH)
td(IDLE–OSC)
ÁÁ
ÁÁ
WAKE INT
CLKOUT/IOPC1
A0–A15
Figure 26. OSC Power-Down Entry and Exit Timings
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memory and parallel I/O interface read timings
switching characteristics over recommended operating conditions for a memory read @ 5 V
(see Figure 27)
PARAMETER MIN MAX UNIT
td(CO-A)RD Delay time, CLKOUT/IOPC1 low to address valid 17 ns
td(CO-SL)RD Delay time, CLKOUT/IOPC1 low to STRB low 10 ns
td(CO-SH)RD Delay time, CLKOUT/IOPC1 low to STRB high 6 ns
td(CO-ACTL)RD Delay time, CLKOUT/IOPC1 low to PS, DS, IS, and BR low 10 ns
td(CO-ACTH)RD Delay time, CLKOUT/IOPC1 low to PS, DS, IS, and BR high 10 ns
timing requirements over recommended operating conditions for a memory read @ 5 V
[H = 0.5tc(CO)]† (see Figure 27)
MIN MAX UNIT
t
Access time from address alid to read data
0 wait state 2H – 32
ns
ta(A) Access time, from address valid to read data 1 wait state 4H – 32 ns
tsu(D-COL)RD Setup time, data read before CLKOUT/IOPC1 low 15 ns
th(COL-D)RD Hold time, data read after CLKOUT/IOPC1 low 2 ns
†All timings with respect to CLKOUT/IOPC1 assume CLKSRC[1:0] bits are set to select CPUCLK for output.
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memory and parallel I/O interface read timings (continued)
PS, DS, IS,
or BR
td(CO–A)RD td(CO–A)RD
ta(A)
tsu(D-COL)RD
th(COL-D)RD
CLKOUT/IOPC1
A0–A15
W/R
D0–D15
WE
READY
STRB
td(CO–ACTL)RD
td(CO–SL)RD td(CO–SH)RD
td(CO–ACTH)RD
Figure 27. Memory Interface Read Timings
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memory and parallel I/O interface write timings
switching characteristics over recommended operating conditions for a memory write
@ 5 V [H = 0.5tc(CO)]† (see Figure 28)
PARAMETER MIN MAX UNIT
td(CO-A)W Delay time, CLKOUT/IOPC1 high to address valid 17 ns
td(CO-D) Delay time, CLKOUT/IOPC1 low to data bus driven 15 ns
th(WH-A) Hold time, address valid after WE high H – 8 ns
tw(WH) Pulse duration, WE high 2H – 11 ns
tw(WL) Pulse duration, WE low 2H – 11
td(CO-WL) Delay time, CLKOUT/IOPC1 low to WE low 9 ns
td(CO-WH) Delay time, CLKOUT/IOPC1 low to WE high 9 ns
tsu(D-WH) Setup time, write data valid before WE high 2H – 8 ns
thz(WH-D) High-impedance time, WE high to data bus Hi-Z 0 5 ns
td(CO-SL)W Delay time, CLKOUT/IOPC1 low to STRB low 10 ns
td(CO-SH)W Delay time, CLKOUT/IOPC1 low to STRB high 6 ns
td(CO-ACTL)W Delay time, CLKOUT/IOPC1 high to PS, DS, IS, and BR low 10 ns
td(CO-ACTH)W Delay time, CLKOUT/IOPC1 high to PS, DS, IS, and BR high 10 ns
td(CO-RWL) Delay time, CLKOUT/IOPC1 high to R/W low 10 ns
td(CO-RWH) Delay time, CLKOUT/IOPC1 high to R/W high 10 ns
†All timings with respect to CLKOUT/IOPC1 assume CLKSRC[1:0] bits are set to select CPUCLK for output.
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memory and parallel I/O interface write timings (continued)
PS, DS, IS,
or BR
CLKOUT/IOPC1
A0–A15
R/W
D0–D15
WE
READY
STRB
td(CO–A)W
td(CO–ACTH)W
th(WH-A)
td(CO–WH)
thz(WH-D)
td(CO–D)
td(CO–SL)W
tw(WH)
tsu(D-WH)
td(CO–ACTL)W
td(CO–WL)
td(CO–SH)W
td(CO–RWL) td(CO–RWH)
W/R
Figure 28. Memory Interface Write Timings
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I/O timing variation with load capacitance: SPICE simulation results
2.2 V
0.8 V
Condition: Temperature
Capacitance
Voltage
: – 40 to 150° C
: 5–125pF
: 5.0 V
Figure 29. Rise and Fall Time Diagram
Table 19. Timing Variation With Load Capacitance: [VCC = 5 V, VOH = 2.2 V, VOL = 0.8 V]
– 40°C 27°C 150°C
RISE FALL RISE FALL RISE FALL
5 pF 2.5 ns 3.6 ns 3.1 ns 4.5 ns 4.3 ns 6.2 ns
25 pF 3.1 ns 4.6 ns 4.0 ns 5.7 ns 5.6 ns 7.8 ns
50 pF 3.9 ns 5.9 ns 5.0 ns 7.3 ns 7.2 ns 9.9 ns
75 pF 4.7 ns 7.3 ns 6.1 ns 8.9 ns 8.8 ns 11.7 ns
100 pF 5.4 ns 8.9 ns 7.2 ns 10.6 ns 10.5 ns 13.8 ns
125 pF 6.2 ns 10.4 ns 8.3 ns 12.2 ns 12.1 ns 15.8 ns
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READY timings
timing requirements over recommended operating conditions [H = 0.5tc(CO)]† (see Figure 30)
MIN MAX UNIT
tsu(R-CO) Setup time, READY low before CLKOUT/IOPC1 high 14 ns
th(CO-R) Hold time, READY low after CLKOUT/IOPC1 high 0 ns
tv(R)ARD Valid time, READY after address valid on read 3H – 31 ns
tv(R)AW Valid time, READY after address valid on write 4H – 31 ns
†The READY timings are based on one software wait state. At full speed operation, the F240 does not allow for single READY-based wait states.
PS, DS, or IS
CLKOUT/IOPC1
A0–A15
W/R
D0–D15
WE
READY
STRB
tv(R)AW
th(CO–R)
tsu(R–CO)
tv(R)ARD
Figure 30. READY Timings
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RS and PORESET timings
switching characteristics over recommended operating conditions for a reset [H = 0.5tc(CO)]
(see Figure 31, Figure 32, and Figure 33)
PARAMETER MIN MAX UNIT
tw(RSL1) Pulse duration, RS low†8tc(SYS) ns
td(RS) Delay time, RS low to program address at reset vector 4H ns
td(EX) Delay time, RS high to reset vector executed 32H ns
†The parameter tw(RSL1) refers to the time RS is an output.
timing requirements over recommended operating conditions for a reset (see Figure 31, Figure 32,
and Figure 33)
MIN MAX UNIT
tw(RSL) Pulse duration, RS or PORESET low‡5 ns
‡The parameter tw(RSL) refers to the time RS is an input.
Start–up PLL Lock PLL Stable
txtal§tp
tHi-Z¶
Hi-Z
VDD
PORESET†
RS‡
XTAL1#
I/O Pins
†PORESET is required to be driven low during power up to ensure all clock/PLL registers are reset to a known state.
‡RS is a bidirectional (open-drain output) pin and can be optionally pulled low through an open-drain or open-collector drive circuit, or through
a 2.7-kΩ resistor in series with a totem pole drive circuit. If RS is left undriven, then a 20-kΩ pullup resistor should be used.
§The start-up time of the on-chip oscillator depends on the crystal parameters, bypass capacitors, and board layout. Typical start-up time is
about 10 ms.
¶After PO RESET is high and oscillator starts up, it takes few clock edges (typically 4–8 oscillator cycles) for the I/Os to assume high-impedance
state.
#CLKOUT using on-chip oscillator.
Figure 31. Case With Crystal
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RS and PORESET timings (continued)
Start–up PLL Lock PLL Stable
Hi-Z
VDD
PORESET†
RS‡
CLKIN¶
I/O Pins
tHi-Z§
tlock
†PORESET is required to be driven low during power up to ensure all clock/PLL registers are reset to a known state.
‡RS is a bidirectional (open-drain output) pin and can be optionally pulled low through an open-drain or open-collector drive circuit, or through
a 2.7-kΩ resistor in series with a totem pole drive circuit. If RS is left undriven, then a 20-kΩ pullup resistor should be used.
§If external clock is used, after PORESET is high, it takes few valid clock edges (typically 4–8 clock-in cycles) for the I/Os to assume
high-impedance state.
¶CLKOUT using external oscillator.
Figure 32. Case With External Oscillator
0000h 0001h
tw(RSL1)
td(RS) td(EX)
tw(RSL)
A0–A15
RS†
PORESET
†RS is driven low by any device reset, which includes asserting PORESET, RS, access to an illegal address, execution of a software
reset, or a watchdog timer reset.
Figure 33. Power-On Reset Timings
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XF, BIO, and MP/MC timings
switching characteristics over recommended operating conditions (see Figure 34)
PARAMETER MIN MAX UNIT
td(XF) Delay time, CLKOUT high to XF high/low 11 ns
timing requirements over recommended operating conditions [H = 0.5tc(CO)] (see Figure 34)
MIN MAX UNIT
tw(BIOL) Pulse duration, BIO low 2H + 16 ns
tw(MPMCV) Pulse duration, MP/MC valid†2H + 24 ns
†This is the minimum time the MP/MC pin needs to be stable in order to be recognized by internal logic; however, for proper operation, the user
must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip.
td(XF)
XF
BIO
CLKOUT/IOPC1
tw(BIOL)
MP/MC
tw(MPMCV)†
†This is the minimum time the MP/MC pin needs to be stable in order to be recognized by internal logic; however, for proper
operation, the user must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip.
Valid
Figure 34. XF, BIO, and MP/MC Timings
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TIMING EVENT MANAGER INTERFACE
PWM/CMP timings
PWM refers to PWM1/CMP1, PWM2/CMP2, PWM3/CMP3, PWM4/CMP4, PWM5/CMP5, PWM6/CMP6,
T1PWM/T1CMP, T2PWM/T2CMP, T3PWM/T3CMP, PWM7/CMP7, PWM8/CMP8, and PWM9/CMP9.
switching characteristics over recommended operating conditions for PWM timing (see Figure 35)
PARAMETER MIN MAX UNIT
td(PWM)CO Delay time, CLKOUT high to PWM output switching 12 ns
timing requirements over recommended operating conditions for PWM timing [H = 0.5tc(CO)]
(see Figure 36 and Figure 37)
MIN MAX UNIT
tw(TMRDIR) Pulse duration, TMRDIR low/high 4H + 12 ns
tw(TMRCLKL) Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time 40 60 %
tw(TMRCLKH) Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time 40 60 %
tc(TMRCLK) Cycle time, TMRCLK 4 tc(CPU) ns
td(PWM)CO
PWM
CLKOUT/IOPC1
Figure 35. PWM and Compare Output Timings
tw(TMRCLKL)
TMRCLK
tc(TMRCLK)
tw(TMRCLKH)
Figure 36. External Timer Clock Input Timings
tw(TMRDIR)
TMRDIR
Figure 37. External Timer Direction Input Timings
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capture and QEP timings
CAP refers to CAP1/QEP1/IOPC4, CAP2/QEP2/IOPC5, CAP3/IOPC6, and CAP4/IOPC7.
timing requirements over recommended operating conditions for CAP [H = 0.5tc(CO)]
(see Figure 38)
MIN MAX UNIT
tw(CAP) Pulse duration, CAP input low/high 4H + 12 ns
CAP
tw(CAP)
Figure 38. Capture and QEP Input Timings
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interrupt timings
PWM refers to PWM1/CMP1, PWM2/CMP2, PWM3/CMP3, PWM4/CMP4, PWM5/CMP5, PWM6/CMP6,
T1PWM/T1CMP, T2PWM/T2CMP, T3PWM/T3CMP, PWM7/CMP7, PWM8/CMP8, and PWM9/CMP9.
INT refers to NMI, XINT1, XINT2/IO, and XINT3/IO. PDP refers to PDPINT.
switching characteristics over recommended operating conditions for interrupts (see Figure 40)
PARAMETER MIN MAX UNIT
td(PWM)PDP Delay time, PDPINT low to PWM to high-impedance state 0 15 ns
timing requirements over recommended operating conditions for interrupts [H = 0.5tc(CO)]
(see Figure 39 and Figure 40)
MIN MAX UNIT
tw(INT) Pulse duration, INT input low/high tc(SYS) + 12 ns
tw(PDP) Pulse duration, PDPINT input low 2H + 18 ns
td(INT) Delay time, INT low/high to interrupt-vector fetch 2tc(SYS) + 4tc(CPU) ns
tw(INT)
INT
Figure 39. External Interrupt Timings
PWM
PDPINT
tw(PDP)
td(PWM)PDP
Figure 40. Power-Drive Protection Interrupt Timings
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general-purpose input/output timings
GPO refers to the digital output function of shared pins IOPA0–3, IOPB0–7, IOPC0–7, XINT2/IO, XINT3/IO.
GPI refers to the digital input function of shared pins IOPA0–3, IOPB0–7, IOPC0–7, XINT2/IO, XINT3/IO.
switching characteristics over recommended operating conditions for a GPI/O (see Figure 41)
PARAMETER MIN MAX UNIT
t
d(GPO)CO
Dela
y
time
,
CLKOUT low to GPO low/hi
g
hXINT2/IO, XINT3/IO, IOPB6,
IOPB7, and IOPC0 33 ns
td(GPO)CO
Delay
time
,
CLKOUT
low
to
GPO
low/high
All other GPOs 25
ns
timing requirements over recommended operating conditions for a GPI/O (see Figure 42)
MIN MAX UNIT
tw(GPI) Pulse duration, GPI high/low tc(SYS) + 12 ns
td(GPO)CO
GPO
CLKOUT/IOPC1
Figure 41. General-Purpose Output Timings
GPI
tw(GPI)
Figure 42. General-Purpose Input Timings
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SERIAL COMMUNICATIONS INTERFACE (SCI) I/O TIMINGS
timing characteristics for SCI (see Note 2 and Figure 43)
PARAMETER (BRR + 1)
IS EVEN AND BRR = 0 (BRR + 1)
IS ODD AND BRR ≠ 0 UNIT
PARAMETER
MIN MAX MIN MAX
UNIT
tc(SCC) Cycle time, SCICLK 16tc65536tc24tc65535tcns
tv(TXD) Valid time, SCITXD data tc(SCC)–70 tc(SCC)+70 tc(SCC)–70 tc(SCC)+70 ns
tv(RXD) Valid time, SCIRXD data 16tc24tcns
NOTE 2: tc = system clock cycle time = 1/SYSCLK = tc(SYS)
tv(TXD)
tv(RXD)
Data Valid
Data Valid
SCITXD
SCIRXD
Figure 43. SCI Timings
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•
SPI MASTER MODE TIMING PARAMETERS
SPI master mode timing information is listed in the following tables.
SPI master mode external timing parameters (clock phase = 0)† (see Figure 44)
WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2 WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3 UNIT
MIN MAX MIN MAX
UNIT
tc(SPC)M Cycle time, SPICLK 4tc‡128tc‡5tc‡127tc‡ns
tw(SPCH)M§Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M–0.5tc–70 0.5tc(SPC)M –0.5tc
ns
tw(SPCL)M§Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M–0.5tc–70 0.5tc(SPC)M –0.5tcns
tw(SPCL)M§Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M+0.5tc–70 0.5tc(SPC)M + 0.5tc
ns
tw(SPCH)M§Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M+0.5tc–70 0.5tc(SPC)M + 0.5tcns
td(SPCH-SIMO)M§Delay time, SPICLK high (clock polarity = 0) to
SPISIMO valid – 10 10 – 10 10
ns
td(SPCL-SIMO)M§Delay time, SPICLK low (clock polarity = 1) to
SPISIMO valid – 10 10 – 10 10 ns
tv(SPCL-SIMO)M§Valid time, SPISIMO data valid after SPICLK low
(clock polarity =0) 0.5tc(SPC)M–70 0.5tc(SPC)M+0.5tc–70
ns
tv(SPCH-SIMO)M§Valid time, SPISIMO data valid after SPICLK high
(clock polarity =1) 0.5tc(SPC)M–70 0.5tc(SPC)M+0.5tc–70 ns
tsu(SOMI-SPCL)M§Setup time, SPISOMI before SPICLK low
(clock polarity = 0) 0 0
ns
tsu(SOMI-SPCH)M§Setup time, SPISOMI before SPICLK high
(clock polarity = 1) 0 0 ns
tv(SPCL-SOMI)M§Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0) 0.25tc(SPC)M–70 0.5tc(SPC)M–0.5tc–70
ns
tv(SPCH-SOMI)M§Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1) 0.25tc(SPC)M–70 0.5tc(SPC)M–0.5tc–70 ns
†The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
‡tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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PARAMETER MEASUREMENT INFORMATION
td(SPCH-SIMO)M
td(SPCL-SIMO)M
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
tw(SPCL)M
tw(SPCL)M
tc(SPC)M
SPISTE†
†The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active
until the SPI communication stream is complete.
tw(SPCH)M
tw(SPCH)M
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
Figure 44. SPI Master Mode External Timings (Clock Phase = 0)
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•
SPI master mode external timing parameters (clock phase = 1)† (see Figure 45)
WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2 WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3 UNIT
MIN MAX MIN MAX
UNIT
tc(SPC)M Cycle time, SPICLK 4tc‡128tc‡5tc‡127tc‡ns
tw(SPCH)M§Pulse duration, SPICLK high
(clock polarity = 0) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M–0.5tc–70 0.5tc(SPC)M –0.5tcns
tw(SPCL)M§Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M–0.5tc–70 0.5tc(SPC)M –0.5tc
ns
tw(SPCL)M§Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M+0.5tc–70 0.5tc(SPC)M + 0.5tc
tw(SPCH)M§Pulse duration, SPICLK high
(clock polarity = 1) 0.5tc(SPC)M–70 0.5tc(SPC)M 0.5tc(SPC)M+0.5tc–70 0.5tc(SPC)M + 0.5tcns
tsu(SIMO-SPCH)M§Setup time, SPISIMO data valid before SPICLK high
(clock polarity = 0) 0.5tc(SPC)M–70 0.5tc(SPC)M –70
ns
tsu(SIMO-SPCL)M§Setup time, SPISIMO data valid before SPICLK low
(clock polarity = 1) 0.5tc(SPC)M–70 0.5tc(SPC)M –70 ns
tv(SPCH-SIMO)M§Valid time, SPISIMO data valid after SPICLK high
(clock polarity =0) 0.5tc(SPC)M–70 0.5tc(SPC)M –70
ns
tv(SPCL-SIMO)M§Valid time, SPISIMO data valid after SPICLK low
(clock polarity =1) 0.5tc(SPC)M–70 0.5tc(SPC)M –70 ns
tsu(SOMI-SPCH)M§Setup time, SPISOMI before SPICLK high
(clock polarity = 0) 0 0
ns
tsu(SOMI-SPCL)M§Setup time, SPISOMI before SPICLK low
(clock polarity = 1) 0 0 ns
tv(SPCH-SOMI)M§Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0) 0.25tc(SPC)M–70 0.5tc(SPC)M–70
ns
tv(SPCL-SOMI)M§Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1) 0.25tc(SPC)M–70 0.5tc(SPC)M–70 ns
†The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
‡tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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PARAMETER MEASUREMENT INFORMATION
Data Valid
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
tc(SPC)M
tw(SPCH)M
tw(SPCL)M
SPISTE†
†The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
tsu(SIMO-SPCH)M
tsu(SIMO-SPCL)M tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tw(SPCH)M tw(SPCL)M
Figure 45. SPI Master Mode External Timings (Clock Phase = 1)
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SPI SLAVE MODE TIMING PARAMETERS
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0)† (see Figure 46)
MIN MAX UNIT
tc(SPC)S Cycle time, SPICLK 8tc‡ns
tw(SPCH)S§Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S–70 0.5tc(SPC)S
ns
tw(SPCL)S§Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S–70 0.5tc(SPC)S ns
tw(SPCL)S§Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S–70 0.5tc(SPC)S
ns
tw(SPCH)S§Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S–70 0.5tc(SPC)S ns
td(SPCH-SOMI)S§Delay time, SPICLK high (clock polarity = 0) to SPISOMI valid 0.375tc(SPC)S–70
ns
td(SPCL-SOMI)S§Delay time, SPICLK low (clock polarity = 1) to SPISOMI valid 0.375tc(SPC)S–70 ns
tv(SPCL-SOMI)S§Valid time, SPISOMI data valid after SPICLK low (clock polarity =0) 0.75tc(SPC)S
ns
tv(SPCH-SOMI)S§Valid time, SPISOMI data valid after SPICLK high (clock polarity =1) 0.75tc(SPC)S ns
tsu(SIMO-SPCL)S§Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0
ns
tsu(SIMO-SPCH)S§Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0ns
tv(SPCL-SIMO)S§Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S
ns
tv(SPCH-SIMO)S§Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S ns
†The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
‡tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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PARAMETER MEASUREMENT INFORMATION
td(SPCH-SOMI)S
td(SPCL-SOMI)S
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
tw(SPCH)S
tw(SPCL)S
tc(SPC)S
SPISTE†
†The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
tv(SPCL-SOMI)S
tv(SPCH-SOMI)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
tw(SPCH)S tw(SPCL)S
Figure 46. SPI Slave Mode External Timing (Clock Phase = 0)
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SPI slave mode external timing parameters (clock phase = 1)† (see Figure 47)
MIN MAX UNIT
tc(SPC)S Cycle time, SPICLK 8tc‡ns
tw(SPCH)S§Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S–70 0.5tc(SPC)S
ns
tw(SPCL)S§Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S–70 0.5tc(SPC)S ns
tw(SPCL)S§Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S–70 0.5tc(SPC)S
ns
tw(SPCH)S§Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S–70 0.5tc(SPC)S ns
tsu(SOMI-SPCH)S§Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S
ns
tsu(SOMI-SPCL)S§Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S ns
tv(SPCH-SOMI)S§Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0.75tc(SPC)S
ns
tv(SPCL-SOMI)S§Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0.75tc(SPC)S ns
tsu(SIMO-SPCH)S§Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0
ns
tsu(SIMO-SPCL)S§Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0ns
tv(SPCH-SIMO)S§Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S
ns
tv(SPCL-SIMO)S§Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S ns
†The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
‡tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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PARAMETER MEASUREMENT INFORMATION
Data Valid
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
tc(SPC)S
tw(SPCH)S
tw(SPCL)S
SPISTE†
†The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S tv(SPCH-SOMI)S
tv(SPCL-SOMI)S
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S tv(SPCH-SIMO)S
tv(SPCL-SIMO)S
tw(SPCH)S tw(SPCL)S
Figure 47. SPI Slave Mode External Timing (Clock Phase = 1)
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10-bit dual analog-to-digital converter (ADC)
The 10-bit dual ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and
VSSA. The purpose is to enhance ADC performance by preventing digital switching noise of the logic circuitry
that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications are given
with respect to VSSA unless otherwise noted.
Resolution 10-bit (1024 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic Assured. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode 000h to 3FFh (000h for VI ≤ VSSA; 3FFh for VI ≥ VCCA). . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
VCCA Analog supply voltage 4.5 5 5.5 V
VSSA Analog ground 0 V
VREFHI Analog supply reference source†VREFLO VCCA V
VREFLO Analog ground reference source†VSSA VREFHI V
VAI Analog input voltage, ADCIN0–ADCIN15 VSSA VCCA V
†VREFHI and VREFLO must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.
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operating characteristics over recommended operating condition ranges†
PARAMETER DESCRIPTION MIN MAX UNIT
V55V
converting 5
ICCA
Analog su
pp
ly current
VCCA = 5.5 V non-converting 2
mA
I
CCA
A
na
l
og supp
l
y current VCCA = VREFHI = 5.5 V PLL or OSC power
down 1m
A
Iref Input charge current, VREFHI or VREFLO VCCA = VCCD = VREFHI = 5.5 V, VREFLO = 0 V 5 mA
C
Analog input capacitance
T
y
pical capacitive load on non-sampling 6
pF
Cai Analog input capacitance
Ty ical
ca acitive
load
on
analog input pin sampling 8 pF
ZAI Analog input source impedance Analog input source impedance for conversions to
remain within specifications. 9 kΩ
EDNL Differential nonlinearity error Difference between the actual step width and the ideal
value – 1 1.5 LSB
EINL Integral nonlinearity error Maximum deviation from the best straight line through
the ADC transfer characteristics, excluding the
quantization error "1.5 LSB
td(PU) Delay time, power-up to ADC valid Time to stabilize analog stage after power-up 10 ms
†Absolute resolution = 4.89 mV. At VREFHI = 5 V and VREFLO = 0 V , this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB sizes
decrease. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
The ADC module allows complete freedom in the design of the sources for the analog inputs. The period of the
sample time is independent of the source impedance. The sample-and-hold period occurs in the first ADC clock
after the ADCIMSTART bit or the ADCSOC bit of the ADC control register 1 (ADCTRL1, bits 13 and 0,
respectively) is set to 1. The conversion then occurs during the next six ADC clock cycles. The digital result
registers are updated on the next ADC clock cycle once the conversion is completed.
ADC input pin circuit
One of the most common A/D application errors is inappropriate source impedance. In practice, minimum
source impedance should be used to limit the error as well as minimize the required sampling time; however,
the source impedance must be smaller than ZAI. A typical ADC input pin circuit is shown in Figure 48.
VIN R1
Requiv
VAI (to ADCINx input)
R1 = 9 kΩ typical
Figure 48. Typical ADC Input Pin Circuit
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ADC timing requirements (see Figure 49)
MIN MAX UNIT
tc(AD) Cycle time, ADC prescaled clock 1ms
tw(SHC) Pulse duration, total sample/hold and conversion time (see Note 3) 6.1 ms
tw(SH) Pulse duration, sample and hold time tc(AD) ms
tsu(SH) Setup time, analog input stable before sample/hold start 0 ns
th(SH) Hold time, analog input stable after sample/hold complete 0 ns
tw(C) Pulse duration, total conversion time 4.5tc(AD) ms
td(SOC-SH) Delay time, start of conversion† to beginning of sample and hold 3tc(SYS) ns
td(EOC-FIFO) Delay time, end of conversion to data loaded into result FIFO 3tc(SYS) ns
†Start o f conversion is signaled by the ADCIMSTART bit or the ADCSOC bit set in software, the external start signal active (ADCSOC), or i nternal
EVSOC signal active.
NOTE 3: The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC-FIFO).
0324
51
tw(C)
td(EOC–FIFO)
6789
th(SH)
tw(SH)
tsu(SH)
tc(AD)
ADC Clock
Analog Input
Bit Converted
td(SOC–SH)
Convert
Internal Start
Start of Convert
XFR to FIFO
Sample/Hold
tw(SHC)
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 49. Analog-to-Digital Timing
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flash EEPROM
switching characteristics over recommended operating conditions
PARAMETER MIN TYP MAX UNIT
Program-erase endurance 10K Cycles
Program pulses per word†1 10 150 Pulses
Erase pulses per array†1 20 1000 Pulses
Flash-write pulses per array†1 20 6000 Pulses
†These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSP
Embedded Flash Memory Technical Reference (literature number SPRU282).
timing requirements over recommended operating conditions
MIN MAX UNIT
td(BUSY) Delay time, after mode deselect to stabilization†10 µs
td(RD-VERIFY) Delay time, verify read mode select to stabilization†10 µs
†These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSP
Embedded Flash Memory Technical Reference (literature number SPRU282).
programming operation
PARAMETER MIN NOM MAX UNIT
tw(PGM) Pulse duration, programming algorithm†95 100 105 µs
td(PGM-MODE) Delay time, program mode select to stabilization†10 µs
†These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSP
Embedded Flash Memory Technical Reference (literature number SPRU282).
erase operation
PARAMETER MIN NOM MAX UNIT
tw(ERASE) Pulse duration, erase algorithm†6.65 7 7.35 ms
td(ERASE-MODE) Delay time, erase mode select to stabilization†10 µs
†These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSP
Embedded Flash Memory Technical Reference (literature number SPRU282).
flash-write operation
PARAMETER MIN NOM MAX UNIT
tw(FLW) Pulse duration, flash-write algorithm†‡ 13.3 14 14.7 ms
td(FLW-MODE) Delay time, flash-write mode select to stabilization†‡ 10 µs
†These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSP
Embedded Flash Memory Technical Reference (literature number SPRU282).
‡Refer to the recommended operating conditions section for the flash programming operating temperature range when programming flash.
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register file compilation
Table 20 is a collec tion o f a ll the programmable registers of the TMS320F240 (provided for a quick reference).
Table 20. Register File Compilation
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DATA MEMORY SPACE
CPU STATUS REGISTERS
ARP OV OVM 1 INTM DP(8)
ST0
DP(7) DP(6) DP(5) DP(4) DP(3) DP(2) DP(1) DP(0) ST0
ARB CNF TC SXM C 1
ST1
1 1 1 XF 1 1 PM ST1
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
00004h
— — — — — — — —
IMR
00004h ——INT6 MASK INT5 MASK INT4 MASK INT3 MASK INT2 MASK INT1 MASK IMR
00005h
— — — — — — — —
GREG
00005h Global Data Memory Configuration Bits (7–0) GREG
00006h
— — — — — — — —
IFR
00006h ——INT6 FLAG INT5 FLAG INT4 FLAG INT3 FLAG INT2 FLAG INT1 FLAG IFR
SYSTEM CONFIGURATION REGISTERS
07018h
RESET1 RESET0 — — — — — —
SYSCR
07018h CLKSRC1 CLKSRC0 — — — — — — SYSCR
07019h Reserved
0701Ah
PORST — — ILLADR —SWRST WDRST —
SYSSR
0701Ah ——HPO —VCCAOR — — VECRD SYSSR
0701Bh
to
0701Dh Reserved
0701Eh
0 0 0 0 0 0 0 0
SYSIVR
0701Eh D7 D6 D5 D4 D3 D2 D1 D0 SYSIVR
0701Fh Reserved
WD/RTI CONTROL REGISTERS
07020h Reserved
07021h D7 D6 D5 D4 D3 D2 D1 D0 RTICNTR
07022h Reserved
07023h D7 D6 D5 D4 D3 D2 D1 D0 WDCNTR
07024h Reserved
07025h D7 D6 D5 D4 D3 D2 D1 D0 WDKEY
07026h Reserved
07027h RTI FLAG RTI ENA ———RTIPS2 RTIPS1 RTIPS0 RTICR
07028h Reserved
07029h WD FLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 WDCR
PLL CLOCK CONTROL REGISTERS
0702Ah Reserved
0702Bh CLKMD(1) CLKMD(0) PLLOCK(1) PLLOCK(0) PLLPM(1) PLLPM(0) ACLKENA PLLPS CKCR0
0702Ch Reserved
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register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PLL CLOCK CONTROL REGISTERS (CONTINUED)
0702Dh CKINF(3) CKINF(2) CKINF(1) CKINF(0) PLLDIV(2) PLLFB(2) PLLFB(1) PLLFB(0) CKCR1
0702Eh
to
07031h Reserved
A-to-D MODULE CONTROL REGISTERS
07032h SUSPEND-
SOFT SUSPEND-
FREE ADCIM-
START ADC2EN ADC1EN ADCCON-
RUN ADCINTEN ADCINTFLAG ADCTRL1
07032h
ADCEOC ADC2CHSEL ADC1CHSEL ADCSOC
ADCTRL1
07033h Reserved
07034h
— — —— — ADCEVSOC ADCEXTSOC —
ADCTRL2
07034h ADCFIFO2 —ADCFIFO1 ADCPSCALE ADCTRL2
07035h Reserved
07036h
D9 D8 D7 D6 D5 D4 D3 D2
ADCFIFO1
07036h D1 D0 0 0 0 0 0 0 ADCFIFO1
07037h Reserved
07038h
D9 D8 D7 D6 D5 D4 D3 D2
ADCFIFO2
07038h D1 D0 0 0 0 0 0 0 ADCFIFO2
07039h
to
0703Fh Reserved
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS
07040h SPI SW
RESET CLOCK
POLARITY ———SPI
CHAR2 SPI
CHAR1 SPI
CHAR0 SPICCR
07041h — — — OVERRUN
INT ENA CLOCK
PHASE MASTER/
SLAVE TALK SPI INT
ENA SPICTL
07042h RECEIVER
OVERRUN SPI INT
FLAG — — — — — — SPISTS
07043h Reserved
07044h —SPI BIT
RATE 6 SPI BIT
RATE 5 SPI BIT
RATE 4 SPI BIT
RATE 3 SPI BIT
RATE 2 SPI BIT
RATE 1 SPI BIT
RATE 0 SPIBRR
07045h Reserved
07046h ERCVD7 ERCVD6 ERCVD5 ERCVD4 ERCVD3 ERCVD2 ERCVD1 ERCVD0 SPIEMU
07047h RCVD7 RCVD6 RCVD5 RCVD4 RCVD3 RCVD2 RCVD1 RCVD0 SPIBUF
07048h Reserved
07049h SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 SPIDAT
0704Ah
to
0704Ch Reserved
0704Dh SPISTE
DATA IN SPISTE
DATA OUT SPISTE
FUNCTION SPISTE
DATA DIR SPICLK
DATA IN SPICLK
DATA OUT SPICLK
FUNCTION SPICLK
DATA DIR SPIPC1
0704Eh SPISIMO
DATA IN SPISIMO
DATA OUT SPISIMO
FUNCTION SPISIMO
DATA DIR SPISOMI
DATA IN SPISOMI
DATA OUT SPISOMI
FUNCTION SPISOMI
DATA DIR SPIPC2
0704Fh —SPI
PRIORITY SPI
ESPEN — — — — — SPIPRI
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
07050h STOP
BITS EVEN/ODD
PARITY PARITY
ENABLE SCI ENA ADDR/IDLE
MODE SCI
CHAR2 SCI
CHAR1 SCI
CHAR0 SCICCR
07051h —RX ERR
INT ENA SW RESET CLOCK ENA TXWAKE SLEEP TXENA RXENA SCICTL1
07052h BAUD15
(MSB) BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 SCIHBAUD
07053h BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0
(LSB) SCILBAUD
07054h TXRDY TX EMPTY — — — — RX/BK
INT ENA TX
INT ENA SCICTL2
07055h RX ERROR RXRDY BRKDT FE OE PE RXWAKE —SCIRXST
07056h ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0 SCIRXEMU
07057h RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 SCIRXBUF
07058h Reserved
07059h TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 SCITXBUF
0705Ah
to
0705Dh Reserved
0705Eh SCITXD
DATA IN SCITXD
DATA OUT SCITXD
FUNCTION SCITXD
DATA DIR SCIRXD
DATA IN SCIRXD
DATA OUT SCIRXD
FUNCTION SCIRXD
DATA DIR SCIPC2
0705Fh —SCITX
PRIORITY SCIRX
PRIORITY SCI
ESPEN — — — — SCIPRI
07060h
to
0706Fh Reserved
EXTERNAL INTERRUPT CONTROL REGISTERS
07070h
XINT1
FLAG — — — — — — —
XINT1CR
07070h —XINT1
PIN DATA 0— — XINT1
POLARITY XINT1
PRIORITY XINT1
ENA
XINT1CR
07071h Reserved
07072h
NMI
FLAG — — — — — — —
NMICR
07072h —NMI
PIN DATA 1— — NMI
POLARITY — — NMICR
07073h
to
07077h Reserved
07078h
XINT2
FLAG — — — — — — —
XINT2CR
07078h —XINT2
PIN DATA —XINT2
DATA DIR XINT2
DATA OUT XINT2
POLARITY XINT2
PRIORITY XINT2
ENA
XINT2CR
07079h Reserved
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EXTERNAL INTERRUPT CONTROL REGISTERS (CONTINUED)
0707Ah
XINT3
FLAG — — — — — — —
XINT3CR
0707Ah —XINT3
PIN DATA —XINT3
DATA DIR XINT3
DATA OUT XINT3
POLARITY XINT3
PRIORITY XINT3
ENA
XINT3CR
0707Bh
to
0708Fh Reserved
DIGITAL I/O CONTROL REGISTERS
07090h
CRA.15 CRA.14 CRA.13 CRA.12 CRA.11 CRA.10 CRA.9 CRA.8
OCRA
07090h —— — — CRA.3 CRA.2 CRA.1 CRA.0 OCRA
07091h Reserved
07092h
— — — — — — — —
OCRB
07092h CRB.7 CRB.6 CRB.5 CRB.4 CRB.3 CRB.2 CRB.1 CRB.0 OCRB
07093h
to
07097h Reserved
07098h
— — — — A3DIR A2DIR A1DIR A0DIR
PADATDIR
07098h —— — — IOPA3 IOPA2 IOPA1 IOPA0 PADATDIR
07099h Reserved
0709Ah
B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR
PBDATDIR
0709Ah IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0 PBDATDIR
0709Bh Reserved
0709Ch
C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR
PCDATDIR
0709Ch IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0 PCDATDIR
0709Dh
to
073FFh Reserved
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS
07400h
T3STAT T2STAT T1STAT T3TOADC T2TOADC T1TOADC(1)
GPTCON
07400h T1TOADC(0) TCOMPOE T3PIN T2PIN T1PIN GPTCON
07401h
D15 D14 D13 D12 D11 D10 D9 D8
T1CNT
07401h D7 D6 D5 D4 D3 D2 D1 D0 T1CNT
07402h
D15 D14 D13 D12 D11 D10 D9 D8
T1CMPR
07402h D7 D6 D5 D4 D3 D2 D1 D0 T1CMPR
07403h
D15 D14 D13 D12 D11 D10 D9 D8
T1PR
07403h D7 D6 D5 D4 D3 D2 D1 D0 T1PR
07404h
FREE SOFT TMODE2 TMODE1 TMODE0 TPS2 TPS1 TPS0
T1CON
07404h TSWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR T1CON
07405h
D15 D14 D13 D12 D11 D10 D9 D8
T2CNT
07405h D7 D6 D5 D4 D3 D2 D1 D0 T2CNT
07406h
D15 D14 D13 D12 D11 D10 D9 D8
T2CMPR
07406h D7 D6 D5 D4 D3 D2 D1 D0 T2CMPR
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS (CONTINUED)
07407h
D15 D14 D13 D12 D11 D10 D9 D8
T2PR
07407h D7 D6 D5 D4 D3 D2 D1 D0 T2PR
07408h
FREE SOFT TMODE2 TMODE1 TMODE0 TPS2 TPS1 TPS0
T2CON
07408h TSWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR T2CON
07409h
D15 D14 D13 D12 D11 D10 D9 D8
T3CNT
07409h D7 D6 D5 D4 D3 D2 D1 D0 T3CNT
0740Ah
D15 D14 D13 D12 D11 D10 D9 D8
T3CMPR
0740Ah D7 D6 D5 D4 D3 D2 D1 D0 T3CMPR
0740Bh
D15 D14 D13 D12 D11 D10 D9 D8
T3PR
0740Bh D7 D6 D5 D4 D3 D2 D1 D0 T3PR
0740Ch
FREE SOFT TMODE2 TMODE1 TMODE0 TPS2 TPS1 TPS0
T3CON
0740Ch TSWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR T3CON
0740Dh
to
07410h Reserved
FULL AND SIMPLE COMPARE UNIT REGISTERS
07411h
CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE SCOMPOE
COMCON
07411h SELTMR SCLD1 SCLD0 SACTRLD1 SACTRLD0 SELCMP3 SELCMP2 SELCMP1 COMCON
07412h Reserved
07413h
SVRDIR D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0
ACTR
07413h CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0 ACTR
— — — — — — — —
07414h ——SCMP3-
ACT1 SCMP3-
ACT0 SCMP2-
ACT1 SCMP2-
ACT0 SCMP1-
ACT1 SCMP1-
ACT0 SACTR
07415h
DBT7 DBT6 DBT5 DBT4 DBT3 DBT2 DBT1 DBT0
DBTCON
07415h EDBT3 EDBT2 EDBT1 DBTPS1 DBTPS0 — — — DBTCON
07416h Reserved
07417h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR1
07417h D7 D6 D5 D4 D3 D2 D1 D0 CMPR1
07418h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR2
07418h D7 D6 D5 D4 D3 D2 D1 D0 CMPR2
07419h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR3
07419h D7 D6 D5 D4 D3 D2 D1 D0 CMPR3
0741Ah
D15 D14 D13 D12 D11 D10 D9 D8
SCMPR1
0741Ah D7 D6 D5 D4 D3 D2 D1 D0 SCMPR1
0741Bh
D15 D14 D13 D12 D11 D10 D9 D8
SCMPR2
0741Bh D7 D6 D5 D4 D3 D2 D1 D0 SCMPR2
0741Ch
D15 D14 D13 D12 D11 D10 D9 D8
SCMPR3
0741Ch D7 D6 D5 D4 D3 D2 D1 D0 SCMPR3
0741Dh
to
0741Fh Reserved
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CAPTURE UNIT REGISTERS
07420h
CAPRES CAPQEPN CAP3EN CAP4EN CAP34TSEL CAP12TSEL CAP4TOADC
CAPCON
07420h CAP1EDGE CAP2EDGE CAP3EDGE CAP4EDGE CAPCON
07421h Reserved
07422h
CAP4FIFO CAP3FIFO CAP2FIFO CAP1FIFO
CAPFIFO
07422h CAPFIFO15 CAPFIFO14 CAPFIFO13 CAPFIFO12 CAPFIFO11 CAPFIFO10 CAPFIFO9 CAPFIFO8 CAPFIFO
07423h
D15 D14 D13 D12 D11 D10 D9 D8
CAP1FIFO
07423h D7 D6 D5 D4 D3 D2 D1 D0 CAP1FIFO
07424h
D15 D14 D13 D12 D11 D10 D9 D8
CAP2FIFO
07424h D7 D6 D5 D4 D3 D2 D1 D0 CAP2FIFO
07425h
D15 D14 D13 D12 D11 D10 D9 D8
CAP3FIFO
07425h D7 D6 D5 D4 D3 D2 D1 D0 CAP3FIFO
07426h
D15 D14 D13 D12 D11 D10 D9 D8
CAP4FIFO
07426h D7 D6 D5 D4 D3 D2 D1 D0 CAP4FIFO
07427h
to
0742Bh Reserved
EVENT MANAGER (EV) INTERRUPT CONTROL REGISTERS
0742Ch
— — — — — T1OFINT
ENA T1UFINT
ENA T1CINT
ENA
EVIMRA
0742Ch T1PINT
ENA SCMP3INT
ENA SCMP2INT
ENA SCMP1INT
ENA CMP3INT
ENA CMP2INT
ENA CMP1INT
ENA PDPINT
ENA
EVIMRA
— — — — — — — —
0742Dh T3OFINT
ENA T3UFINT
ENA T3CINT
ENA T3PINT
ENA T2OFINT
ENA T2UFINT
ENA T2CINT
ENA T2PINT
ENA EVIMRB
— — — — — — — —
0742Eh —— — — CAP4INT
ENA CAP3INT
ENA CAP2INT
ENA CAP1INT
ENA EVIMRC
0742Fh
— — — — — T1OFINT
FLAG T1UFINT
FLAG T1CINT
FLAG
EVIFRA
0742Fh T1PINT
FLAG SCMP3INT
FLAG SCMP2INT
FLAG SCMP1INT
FLAG CMP3INT
FLAG CMP2INT
FLAG CMP1INT
FLAG PDPINT
FLAG
EVIFRA
— — — — — — — —
07430h T3OFINT
FLAG T3UFINT
FLAG T3CINT
FLAG T3PINT
FLAG T2OFINT
FLAG T2UFINT
FLAG T2CINT
FLAG T2PINT
FLAG EVIFRB
— — — — — — — —
07431h —— — — CAP4INT
FLAG CAP3INT
FLAG CAP2INT
FLAG CAP1INT
FLAG EVIFRC
07432h
0 0 0 0 0 0 0 0
EVIVRA
07432h 00 D5 D4 D3 D2 D1 D0 EVIVRA
07433h
0 0 0 0 0 0 0 0
EVIVRB
07433h 00 D5 D4 D3 D2 D1 D0 EVIVRB
07434h
0 0 0 0 0 0 0 0
EVIVRC
07434h 00 D5 D4 D3 D2 D1 D0 EVIVRC
07435h
to
0743Fh Reserved
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 20. Register File Compilation (Continued)
ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
I/O MEMORY SPACE
FLASH CONTROL MODE REGISTER†
0FF0Fh
— — — — — — — —
FCMR
0FF0Fh —— — — — — — — FCMR
WAIT-STATE GENERATOR CONTROL REGISTER
0FFFFh
— — — — — — — —
WSGR
0FFFFh —— — — AVIS ISWS DSWS PSWS WSGR
†See the flash control mode register section.
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
103
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK
100 LEAD SHOWN
88
0.012 (0,30)
0.008 (0,20)
64
0.025 (0,635)
Seating Plane
132
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
4040045/C 11/95
100113
6339
”D2” SQ
”D1” SQ
”D” SQ
14
”D3” SQ
38
DIM
”D”
”D2”
”D3”
”D1”
NOM
MIN
MAX
MIN
MAX
MIN
MAX
LEADS ***
0.180 (4,57) MAX
100
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
0.004 (0,10)
M
0.006 (0,15)
0.010 (0,25)
0.020 (0,51) MIN
0.130 (3,30)
0.150 (3,81)
0.006 (0,16) NOM
Gage Plane
0.036 (0,91)
0.046 (1,17)
0°–ā8°
89
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
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