10 V Precision
Voltage Reference
REF01
Rev. H
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
10 V output, ±0.3% maximum
Adjustment range, ±3% minimum
Excellent temperature stability, 8.5 ppm/°C maximum
Low noise, 30 µV p-p maximum
Low supply current, 1.4 mA maximum
Wide input voltage range, 12 V to 40 V
High load driving capability, 10 mA
No external components
Short-circuit proof
GENERAL DESCRIPTION
The REF01 precision voltage reference provides a stable 10 V
output that can be adjusted over a 3% range with minimal effect
on temperature stability. Single-supply operation over an input
voltage range of 12 V to 40 V, a low current drain of 1 mA, and
excellent temperature stability are achieved with an improved
band gap design. Low cost, low noise, and low power make the
REF01 an excellent choice whenever a stable voltage reference is
required. Applications include DACs and ADCs, portable
instrumentation, and digital voltmeters. Full military
temperature range devices with screening to MIL-STD-883 are
available. For new designs, refer to ADR01.
PIN CONFIGURATIONS
00373-F-001
1
2
345
6
7
8
NC
GROUND
(CASE)
NC
V
IN
V
OUT
NC
NC TRIM
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 1. TO-99 (J Suffix)
00373-F-002
REF01
TOP VIEW
(Not to Scale)
NC
1
V
IN 2
NC
3
GND
4
NC
NC
V
OUT
TRIM
8
7
6
5
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead CERDIP (Z-Suffix)
8-Lead SOIC (S-Suffix)
00373-F-003
REF01 OPTION R9 R11 R12
P AND S PACKAGES 18kΩ4.5kΩ33.3kΩ
J AND Z PACKAGES, 50kΩ2kΩ16.7kΩ
AND 883C PRODUCT
OUTPUT RESISTORS
C1
R3
R6
R4
R5
R1
Q1
R2
R10
OUTPUT
GROUND
R12*
TRIM
Q19
R15
INPUT
Q15
Q18
Q16
Q13
Q21
Q17
R13
Q20
Q4 Q3
Q5
Q6
Q9
Q7 Q14
Q12
Q11
Q8
R8 R7 R14
Q10
Q2
R11*
R9*
4
5
6
≈1.23V
2
*SEE OUTPUT RESISTORS
Figure 3. Simplified Schematic
REF01
Rev. H | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Applications........................................................................................8
Precision Current Source .......................................................... 10
Supply Bypassing ........................................................................ 10
Reference Stack with Excellent Line Regulation .................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 12
REVISION HISTORY
12/05—Rev. G to Rev. H
Changes to Figure 12........................................................................ 8
Changes to Ordering Guide .......................................................... 12
2/05—Rev. F to Rev. G
Changes to Electrical Specifications .............................................. 3
Changes to Electrical Specifications .............................................. 4
7/04—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Simplified Schematic ................................................... 1
Changes to Specifications................................................................ 3
Changes to Specifications................................................................ 4
Changes to Applications .................................................................. 8
Changes to Ordering Guide ............................................................ 9
2/04—Rev. D to Rev. E
Changes to Simplified Schematic .................................................. 1
Changes to Ordering Guide ............................................................ 4
Replaced Figure 6 ............................................................................. 5
Replaced Figure 7 ............................................................................. 5
10/03—Rev. C to Rev. D
Changes to Features ..........................................................................1
Changes to Electrical Specifications ...............................................2
Deleted Figure 13...............................................................................3
Deleted Wafer Test Limits ................................................................4
Deleted Typical Electrical Characteristics......................................4
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions..........................................................8
10/02—Rev. B to Rev. C
Edits to Features.................................................................................1
Delete RC-Suffix................................................................................1
Edits to Absolute Maximum Ratings..............................................5
Edits to Ordering Guide ...................................................................5
Edits to Package Type .......................................................................5
Delete CP-20 ......................................................................................9
Updated Outline Dimensions..........................................................9
REF01
Rev. H | Page 3 of 12
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 1.
REF01A/REF01E REF01H
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Output Voltage VO IL = 0 mA 9.97 10.00 10.03 9.95 10.00 10.05 V
Output Adjustment Range ∆VTRIM RP = 10 kΩ ±3.0 ±3.3 ±3.0 ±3.3 %
Output Voltage Noise1
S, Z, P Packages
J, 883 Parts
en p-p
en p-p
0.1 Hz to 10 Hz
0.1 Hz to 10 Hz
30
35
30
35
µV p-p
µV p-p
Line Regulation2 VIN = 13 V to 33 V 0.006 0.010 0.006 0.010 %/V
Load Regulation2 IL = 0 mA to 10 mA 0.005 0.008 0.006 0.010 %/mA
Turn-On Settling Time3 tON To ± 0.1% of final value 5 5 µs
Quiescent Supply Current ISY No load 1.0 1.4 1.0 1.4 mA
Load Current IL 10 10 mA
Sink Current4 IS −0.3 −0.5 −0.3 −0.5 mA
Short-Circuit Current ISC VO = 0 30 30 mA
1 Sample tested.
2 Line and load regulation specifications include the effect of self-heating.
3 Guaranteed by design, not production tested.
4 During sink current test, the device meets the output voltage specified.
@ VIN = 15 V, −55°C ≤ TA ≤ +125°C for REF01A/REF01E, and 0°C ≤ TA ≤ 70°C for REF01H, and IL = 0 mA, unless otherwise noted.
Table 2.
REF01A/REF01E REF01H
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Output Voltage Change ∆VOT 0°C ≤ TA ≤ 70°C 0.02 0.06 0.07 0.17 %
with Temperature1, 2 −55°C ≤ TA ≤+ 125°C 0.06 0.15 0.18 0.45 %
Output Voltage TCVO 3.0 8.5 10.0 25.0 ppm/°C
Temperature Coefficient3
Change in VO Temperature Coefficient RP = 10 kΩ 0.7 0.7 ppm/%
with Output Adjustment
Line Regulation 0°C ≤ TA ≤ 70°C 0.007 0.012 0.007 0.012 %/V
(VIN = 13 V to 33 V)4 −55°C ≤ TA ≤ + 125°C 0.009 0.015 0.009 0.015 %/V
Load Regulation 0°C ≤ TA ≤ 70°C 0.006 0.010 0.007 0.012 %/mA
(IL = 0 mA to 8 mA)4 −55°C ≤ TA ≤ + 125°C 0.007 0.012 0.009 0.015 %/mA
1 ∆VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as
a percentage of 10 V:
100
V10 ×
−
=∆ MINMAX
OT VV
V
2 ∆VOT specification applies trimmed to 10000 V or untrimmed.
3 TCVO is defined as ∆Var divided by the temperature range; therefore,
()
()
C70
C70C0
C70C0 °
°+°∆
=°+° toV
toTCV OT
O
and
()
()
C180
C125C55
C125C55 °
°+°−∆
=°+°− toV
toTCV OT
O
4 Line and load regulation specifications include the effect of self-heating.
REF01
Rev. H | Page 4 of 12
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 3.
REF01C
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage VO IL = 0 mA 9.90 10.00 10.10 V
Output Adjustment Range ∆VTRIM RP = 10 kΩ ±2.7 ±3.3 %
Output Voltage Noise1
S, Z, P Packages
J, 883 Parts
e n p-p
e n p-p
0.1 Hz to 10 Hz
0.1 Hz to 10 Hz
30
35
µV p-p
µV p-p
Line Regulation2 V
IN = 13 V to 33 V 0.009 0.015 %/V
Load Regulation2 IL = 0 mA to 8 mA 0.006 0.015 %/mA
Turn-On Settling Time3 tON To ±0.1% of final value 5 µs
Quiescent Supply Current ISY No load 1.0 1.6 mA
Load Current IL 8 mA
Sink Current4 IS −0.3 −0.5 mA
Short-Circuit Current ISC VO = 0 30 mA
1 Sample tested.
2 Line and load regulation specifications include the effect of self-heating.
3 Guaranteed by design, not production tested.
4 During sink current test, the device meets the output voltage specified.
@ VIN = 15 V, 0°C ≤ TA ≤ +70°C for REF01CJ, REF01CZ, and −40°C ≤ TA ≤ +85°C for REF01CP and REF01CS, unless otherwise noted.
Table 4.
REF01C
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage Change ∆VOT 0.14 0.45 %
with Temperature1, 2
Output Voltage TCVO 20 65 ppm/°C
Temperature Coefficient3
Change in VO Temperature
Coefficient with Output
Adjustment RP = 10 kΩ 0.7 ppm/°C
Line Regulation4 VIN =13 V to 30 V 0.011 0.018 %/V
Load Regulation4 IL = 0 to 5 mV 0.008 0.018 %/mA
1 ∆VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as
a percentage of 10 V:
100
10 ×
−
=∆ V
VV
VMINMAX
OT
2 ∆VOT specification applies trimmed to +10,000 V or untrimmed.
3 TCVO is defined as ∆Var divided by the temperature range; therefore,
()
()
C70
C70C0
C70C0 °
°+°∆
=°+° toV
toTCV OT
O
and
()
()
C180
C125C55
C125C55 °
°+°−∆
=°+°− toV
toTCV OT
O
4 Line and load regulation specifications include the effect of self-heating.
REF01
Rev. H | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating1
Input Voltage 40 V
Output Short-Circuit Duration
(to Ground or VIN) Indefinite
Storage Temperature Range
J, S, and Z Packages −65°C to +150°C
P Package −65°C to +125°C
Operating Temperature Range
REF01A −55°C to +125°C
REF01CJ 0°C to 70°C
REF01CP, REF01CS, REF01E, REF01H −40°C to +85°C
Junction Temperature (TJ) −65°C to +150°C
Lead Temperature (Soldering @ 60 sec) 300°C
1 Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type θJA1 θJC Unit
TO-99 (J) 170 24 °C/W
8-Lead CERDIP (Z) 162 26 °C/W
8-Lead PDIP (P) 110 50 °C/W
8-Pin SOIC (S) 160 44 °C/W
1 θJA is specified for worst-case mounting conditions; that is, θJA is specified for
device in socket for TO, CERDIP, and PDIP packages. θJA is specified for device
soldered to printed circuit board for SOIC package.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REF01
Rev. H | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
76
0
16
26
36
46
56
66
10 100 1k 10k 100k 1M
00373-F-006
FREQUENCY (Hz)
LINE REGULATION (dB)
LINE REGULATION (%/V)
V
IN
= 15V
T
A
= 25°C
0.0031
0.0100
0.0310
0.1000
0.3100
1.0000
3.1000
10.0000
Figure 4. Line Regulation vs. Frequency
10k
1k
100
1010 100 1k 10k 100k 1M
00373-F-007
FREQUENCY (Hz)
OUTPUT NOISE (µV p-p)
V
IN
= 15V
T
A
= 25°C
Figure 5. Output Wideband Noise vs. Bandwidth
(0.1 Hz to Frequency Indicated)
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
–10 0 10 20 30 40 50
00373-F-008
TIME (s)
PERCENT CHANGE IN OUTPUT VOLTAGE (%)
V
IN
= 15V
25°CDEVICE IMMERSED
IN 75°C OIL BATH
Figure 6. Output Change due to Thermal Shock
20
15
16
17
18
19
1410 15 20 25 30 35 40
00373-F-009
INPUT VOLTAGE (V)
MAXIMUM LOAD CURRENT (mA)
T
A
= 25°C
Figure 7. Maximum Load Current vs. Input Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
–60 –40 –20 0 20 40 60 80 100 120 140
00373-F-010
TEMPERATURE (°C)
LOAD REG–T/LOAD REG (25°C)
V
IN
= 15V
Figure 8. Normalized Load Regulation (∆IL = 10 mA) vs. Temperature
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
–60 –40 –20 0 20 40 60 80 100 120 140
00373-F-011
TEMPERATURE (°C)
LINE REG–T/LINE REG (25°C)
Figure 9. Normalized Line Regulation vs. Temperature
REF01
Rev. H | Page 7 of 12
30
25
20
15
10
5
0
–60 –40 –20 0 20 40 60 80 100 120 140
00373-F-012
TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (mA)
V
IN
= 15V
Figure 10. Maximum Load Current vs. Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
–60 –40 –20 0 20 40 60 80 100 120 140
00373-F-013
TEMPERATURE (°C)
QUIESCENT CURRENT (mA)
V
IN
= 15V
Figure 11. Quiescent Current vs. Temperature
REF01
Rev. H | Page 8 of 12
APPLICATIONS
U1
REF01
V
IN
V
OUT
TEMP TRIM
GND
V
IN
V
O
pot
10kΩ
R2
1kΩ
R1
470kΩ
00373-022
Figure 12. Output Adjustment
The REF01 trim terminal can be used to adjust the output
voltage over a 10 V ± 300 mV range. This feature lets the
system designer trim system errors by setting the reference
to a voltage other than 10 V. The output also can be set exactly
to 10.000 V or to 10.240 V for binary applications.
Adjustment of the output does not significantly affect the
temperature performance of the device. The temperature
coefficient change is approximately 0.7 ppm/°C for 100 mV
of output adjustment.
00373-F-005
V
IN
GND
–18V
+18V
REF01
Figure 13. Burn-In Circuit
00373-F-014
REF01
DAC08 OP02
0.1µF
+15V
4
6
5
10kΩ
5kΩ
5kΩ
5kΩ
+15V –15V –15V
+15V
E
O
LSB
MSB
2B1 B2 B3 B4 B5 B6 B7 B8
V+ V– C
C
V
LC
l
O
2
4
l
O
B1 B2 B3 B4 B5 B6 B7 B8 E
POS. FULL SCALE –1LSB 1 1 1 1 1 1 1 1 +4.960
ZERO SCALE 1 0 0 0 0 0 0 0 0.000
NEG. FULL SCALE +1LSB 0 0 0 0 0 0 0 1 –4.960
NEG. FULL SCALE 0 0 0 0 0 0 0 0 –5.000
V
IN
V
O
GND
Figure 14. Burn-In Circuit
00373-F-015
GND
REF01
V
O
V
IN
TRIM
+
–
10V
100kΩ
1.1mA
2
6
5
4
9V
9V
0.1µF
Figure 15. Precision Calibration Standard
00373-F-016
V
IN
GND
TRIM
V
O
REF01
15V
2
6
5
4
R
I
OUT
I
OUT
=10V
R+ 1mA
VOLTAGE COMPLIANCE: –25V TO +3V
Figure 16. Current Source
00373-F-017
2
+15V
4
DAC08
+15V
3.9MΩ5kΩ
REF01
5kΩ
5kΩ
1kΩ
–15V +15V
–15V
SERIAL
OUTPUT
START
CONVERSION
COMPLETE TTL CLOCK
INPUT 2.25MHz
CONNECT START TO
CONVERSION COMPLETE
FOR CONTINUOUS
CONVERSION
0.1µF
0.01µF
B1
B2
B3
B4
B5
B6
B7
B8
5
6
14
15 7658
910 11 12 1
345611121314
1
10
29
7
2
4
3
2
1
4
7
8
16
GND
V
IN
V
O
C
C
I
O
I
O
313
CMP01C
TRIM
ANALOG
INPUT
0V TO +10V
AM2592
SUCCESSIVE-
APPROXIMATION
REGISTER
Figure 17. DAC Reference
REF01
Rev. H | Page 9 of 12
00373-F-018
VIN
GND
REF01
VO
TRIM
0.1µF
5kΩOP02
10kΩ±0.1%
10kΩ±0.1%
+15V
–15V
+15V
+10V
–10V
4
5
6
2
Figure 18. ±10 V Reference
00373-F-019
V
IN
GND
TRIM
V
O
REF01
–15V
2
6
5
4
R
I
OUT
I
OUT
=10V
R+ 1mA
VOLTAGE COMPLIANCE: –3V TO +25V
Figure 19. Current Sink
REF01
Rev. H | Page 10 of 12
PRECISION CURRENT SOURCE
A current source with 25 V output compliance and excellent
output impedance can be obtained using this circuit. REF01
keeps the line voltage and power dissipation constant in the
device; the only important error consideration at room
temperature is the negative supply rejection of the op amp.
The typical 3 µV/V PSRR of the OP02E creates an 8 ppm
change (3 µV/V × 25 V/10 V) in output current over a 25 V
range. For example, a 10 mA current source can be built
(R = 1 kΩ) with 300 MΩ output impedance.
mA10108 V25
6××
=−
O
R
00373-F-020
GND
REF01
GND
REF01
OP02E
C
C
R
2
2
2
6
6
7
3
4
6
4
4
+50V
–5V I
O
= 10V
R
RC = 10
–5
SEC
R
(TRIM FOR
CALIBRATION)
V
IN
V
O
V
IN
V
O
V
O
= 0V
TO 25V
1
2
Figure 20. Precision Current Source
SUPPLY BYPASSING
For best results, it is recommended that the power supply pin be
bypassed with a 0.1 µF disc ceramic capacitor.
REFERENCE STACK WITH EXCELLENT LINE
REGULATION
Three REF01s can be stacked to yield 10 V, 20 V, and 30 V
outputs. An additional advantage is near-perfect line regulation
of the 10.0 V and 20.0 V output. A 32 V to 60 V input change
produces an output change that is less than the noise voltage of
the devices. A load bypass resistor (RB) provides a path for the
supply current (ISY) of the 20 V regulator.
In general, any number of REF01s can be stacked this way.
For example, 10 devices will yield outputs of 10 V, 20 V,
30 V . . . 100 V. The line voltage can change from 105 V to
130 V. However, care must be taken to ensure that the total
load currents do not exceed the maximum usable current
(typically 21 mA).
00373-F-021
GND
REF01
GND
REF01
GND
REF01
TRIM
TRIM
10kΩ
10kΩ
R
B
6.8kΩ
10kΩ
2
6
5
4
2
6
5
4
2
6
5
4
30V
20V
10V
TRIM
32V TO 60V
TRIMMED
OUTPUTS
V
IN
V
O
V
IN
V
O
V
IN
V
O
Figure 21. Reference Stack
REF01
Rev. H | Page 11 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
58
Figure 22. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Z-Suffix
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-002-AK
0.2500 (6.35) MIN
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFERENCE PLANE
0.0500 (1.27) MAX
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
0.0400 (1.02) MAX 0.0340 (0.86)
0.0280 (0.71)
0.0450 (1.14)
0.0270 (0.69)
0.1600 (4.06)
0.1400 (3.56)
0.1000 (2.54)
BSC
6
28
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
45° BSC
BASE & SEATING PLANE
Figure 23. 8-Lead Metal Header [TO-99]
(H-08)
J-Suffix
Dimensions shown in inches and (millimeters)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 24. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
S-Suffix
Dimensions shown in millimeters and (inches
COMPLIANT TO JEDEC STANDARDS MS-001-BA
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210
(5.33)
MAX
PIN 1
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 25. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
P-Suffix
Dimensions shown in inches and (millimeters)
REF01
Rev. H | Page 12 of 12
ORDERING GUIDE
T
A = 25° C
Model ∆VOS Max (mV) Temperature Range (°C) Package Description1Package Option
REF01AJ/883C ±30 −55 to +125 8-Lead TO-99 J-Suffix (H-08)
REF01EJ ±30 −40 to +85 8-Lead TO-99 J-Suffix (H-08)
REF01CJ ±100 0 to 70 8-Lead TO-99 J-Suffix (H-08)
REF01EZ ±30 −40 to +85 8-Lead CERDIP Z-Suffix (Q-8)
REF01HZ ±50 −40 to +85 8-Lead CERDIP Z-Suffix (Q-8)
REF01AZ/883C ±30 −55 to +125 8-Lead CERDIP Z-Suffix (Q-8)
REF01CP ±100 −40 to +85 8-Lead PDIP P-Suffix (N-8)
REF01CPZ2±100 −40 to +85 8-Lead PDIP P-Suffix (N-8)
REF01HPZ2 ±50 −40 to +85 8-Lead PDIP P-Suffix (N-8)
REF01HP ±50 −40 to +85 8-Lead PDIP P-Suffix (N-8)
REF01HS3±50 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01HS-REEL3 ±50 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01HSZ2, 3 ±50 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01HSZ-REEL2, 3 ±50 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01CS3 ±100 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01CS-REEL3 ±100 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01CS-REEL73 ±100 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01CSZ-REEL2, 3 ±100 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01CSZ-REEL72, 3 ±100 −40 to +85 8-Lead SOIC S-Suffix (R-8)
REF01CSZ2, 3 ±100 −40 to +85 8-Lead SOIC S-Suffix (R-8)
1 Burn-in is available on commercial and industrial temperature range parts in CERDIP, PDIP, and TO-99 packages.
2 Z = Pb-free part.
3 For availability and burn-in information on SOIC packages, contact your local Sales office.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00373-0-12/05(H)
