MSP430F1111AIDWR - Texas Instruments

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DLow Supply Voltage Range 1.8 V to 3.6 V

DUltralow Power Consumption

− Active Mode: 160 μA at 1 MHz, 2.2 V

− Standby Mode: 0.7 μA

− Off Mode (RAM Retention): 0.1 μA

DWake-Up From Standby Mode in

Less Than 6 μs

D16-Bit RISC Architecture, 125 ns

Instruction Cycle Time

DBasic Clock Module Configurations:

− Various Internal Resistors

− Single External Resistor

− 32-kHz Crystal

− High-Frequency Crystal

− Resonator

− External Clock Source

D16-Bit Timer_A With Three

Capture/Compare Registers

DOn-Chip Comparator for Analog Signal

Compare Function or Slope

Analog-to-Digital (A/D) Conversion

DSerial Onboard Programming,

No External Programming Voltage Needed,

Programmable Code Protection by

Security Fuse

DFamily Members Include

MSP430C1101: 1KB ROM, 128B RAM

MSP430C1111: 2KB ROM, 128B RAM

MSP430C1121: 4KB ROM, 256B RAM

MSP430F1101A: 1KB + 128B Flash Memory

128B RAM

MSP430F1111A: 2KB + 256B Flash Memory

128B RAM

MSP430F1121A: 4KB + 256B Flash Memory

256B RAM

DAvailable in a 20-Pin Plastic Small-Outline

Wide Body (SOWB) Package, 20-Pin Plastic

Small-Outline Thin Package, 20-Pin TVSOP

(F11x1A only), and 24-Pin QFN

DFor Complete Module Descriptions, Refer

to the MSP430x1xx Family User’s Guide,

Literature Number SLAU049

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 6 μs.

The MSP430x11x1(A) series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer,

versatile analog comparator and fourteen I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand alone radio frequency (RF) sensor front

end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive

sensors.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range

from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage

because very small parametric changes could cause the device not to meet its published specifications. These devices have limited

built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

TAPLASTIC

20-PIN SOWB

(DW)

PLASTIC

20-PIN TSSOP

(PW)

PLASTIC

20-PIN TVSOP

(DGV)

PLASTIC

24-PIN QFN

(RGE)

40°Cto85°C

MSP430C1101IDW

MSP430C1111IDW

MSP430C1121IDW

MSP430C1101IPW

MSP430C1111IPW

MSP430C1121IPW

MSP430F1101AIDGV

MSP430F1111AIDGV

MSP430C1101IRGE

MSP430C1111IRGE

MSP430C1121IRGE

−40°C to 85°C

MSP430C1121IDW

MSP430F1101AIDW

MSP430F1111AIDW

MSP430F1121AIDW

MSP430C1121IPW

MSP430F1101AIPW

MSP430F1111AIPW

MSP430F1121AIPW

MSP430F1111AIDGV

MSP430F1121AIDGV

MSP430C1121IRGE

MSP430F1101AIRGE

MSP430F1111AIRGE

MSP430F1121AIRGE

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RGE PACKAGE

(TOP VIEW)

TEST

VCC

P2.5/Rosc

VSS

XOUT

XIN

RST/NMI

P2.0/ACLK

P2.1/INCLK

P2.2/CAOUT/TA0

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI/TCLK

P1.5/TA0/TMS

P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

P1.1/TA0

P1.0/TACLK

P2.4/CA1/TA2

P2.3/CA0/TA1

DW, PW, or DGV PACKAGE

(TOP VIEW)

VSS

P2.5/ROSC

XOUT

VCC

XIN

TEST

RST/NMI

P1.7/TA2/TDO/TDI

P2.0/ACLK

P1.6/TA1/TDI/TCLK

P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

P1.1/TA0

P1.0/TACLK

P1.5/TA0/TMS

Note: NC pins not internally connected

P2.1/INCLK

P2.2/CAOUT/TA0

P2.3/CA0/TA1

P2.4/CA1/TA2

891011

20212223

Power Pad connection to VSS recommended

functional block diagram

Oscillator ACLK

SMCLK

CPU

Incl. 16 Reg.

Bus

Conv

MCB

XIN XOUT P2

MDB, 16 Bit

MAB, 16 Bit

MCLK

MAB,

4 Bit

VCC VSS RST/NMI

System

Clock

ROSC

P1/JTAG

Flash/ROM

4KB

2KB

1KB

RAM

256B

128B

Watchdog

Timer

15/16-Bit

Timer_A3

3 CC Reg

I/O Port 1

8 I/Os, with

Interrupt

Capability

I/O Port 2

6 I/Os, with

Interrupt

Capability

POR

MDB, 16-Bit

MAB, 16-Bit

TEST

Test

JTAG

8 6

Comparator

MDB, 8 Bit

Emulation

Module

(F versions only)

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

DESCRIPTION

NAME DW, PW,

OR DGV

RGE I/O DESCRIPTION

P1.0/TACLK 13 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input

P1.1/TA0 14 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0

output/BSL transmit

P1.2/TA1 15 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1

output

P1.3/TA2 16 16 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2

output

P1.4/SMCLK/TCK 17 17 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for

device programming and test

P1.5/TA0/TMS 18 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select,

input terminal for device programming and test

P1.6/TA1/TDI/TCLK 19 20 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input or

test clock input

P1.7/TA2/TDO/TDI†20 21 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output

terminal or data input during programming

P2.0/ACLK 8 6 I/O General-purpose digital I/O pin/ACLK output

P2.1/INCLK 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK

P2.2/CAOUT/TA0 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/ comparator_A,

output/BSL receive

P2.3/CA0/TA1 11 10 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/ comparator_A,

input

P2.4/CA1/TA2 12 11 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/ comparator_A,

input

P2.5/ROSC 3 24 I/O General-purpose digital I/O pin/input for external resistor that defines the DCO

nominal frequency

RST/NMI 7 5 I Reset or nonmaskable interrupt input

TEST 1 22 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected

to TEST.

VCC 2 23 Supply voltage

VSS 4 2 Ground reference

XIN 6 4 I Input terminal of crystal oscillator

XOUT 5 3 O Output terminal of crystal oscillator

QFN Pad NA Package

Pad

NA QFN package pad connection to VSS recommended.

†TDO or TDI is selected via JTAG instruction.

General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator, respectively. The

remaining registers are general-purpose

registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

instruction set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; Table 2 shows the address

modes.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5

Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) −−> M(TONI)

Absolute F F MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)

Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)

Indirect

autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11

R10 + 2−−> R10

Immediate FMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)

NOTE: S = source D = destination

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request, and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

DActive mode (AM)

− All clocks are active.

DLow-power mode 0 (LPM0)

− CPU is disabled.

− ACLK and SMCLK remain active. MCLK is disabled.

DLow-power mode 1 (LPM1)

− CPU is disabled.

− ACLK and SMCLK remain active. MCLK is disabled.

− DCO’s dc generator is disabled if DCO not used in active mode.

DLow-power mode 2 (LPM2)

− CPU is disabled.

− MCLK and SMCLK are disabled.

− DCO’s dc generator remains enabled.

− ACLK remains active.

DLow-power mode 3 (LPM3)

− CPU is disabled.

− MCLK and SMCLK are disabled.

− DCO’s dc generator is disabled.

− ACLK remains active.

DLow-power mode 4 (LPM4)

− CPU is disabled.

− ACLK is disabled.

− MCLK and SMCLK are disabled.

− DCO’s dc generator is disabled.

− Crystal oscillator is stopped.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog

Flash Memory

WDTIFG

KEYV

(see Note 1) Reset 0FFFEh 15, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

ACCVIFG

(see Notes 1 and 4)

(non)-maskable,

(non)-maskable

0FFFCh 14

0FFFAh 13

0FFF8h 12

Comparator_A CAIFG maskable 0FFF6h 11

Watchdog Timer WDTIFG maskable 0FFF4h 10

Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9

Timer_A3

TACCR1 CCIFG.

TACCR2 CCIFG

TAIFG (see Notes 1 and 2)

maskable 0FFF0h 8

0FFEEh 7

0FFECh 6

0FFEAh 5

0FFE8h 4

I/O Port P2

(eight flags; see Note 3)

P2IFG.0 to P2IFG.7

(see Notes 1 and 2) maskable 0FFE6h 3

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(see Notes 1 and 2) maskable 0FFE4h 2

0FFE2h 1

0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module

3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) implemented on the ’C11x1 and ’F11x1A devices.

4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

interrupt enable 1 and 2

7654 0

OFIE WDTIE

32 1

rw-0 rw-0 rw-0

Address

0h NMIIEACCVIE

rw-0

WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer

is configured in interval timer mode.

OFIE: Oscillator fault enable

NMIIE: (Non)maskable interrupt enable

ACCVIE: Flash access violation interrupt enable

7654 032 1

Address

01h

interrupt flag register 1 and 2

7654 0

OFIFG WDTIFG

32 1

rw-0 rw-1 rw-(0)

Address

02h NMIIFG

WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCC power up or a reset condition at RST/NMI pin in reset mode.

OFIFG: Flag set on oscillator fault

NMIIFG: Set via RST/NMI pin

7654 032 1

Address

03h

Legend rw:

rw-0,1:

Bit can be read and written.

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

rw-(0,1):

SFR bit is not present in device

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

memory organization

MSP430C1101 MSP430C1111 MSP430C1121

Memory

Main: interrupt vector

Main: code memory

Size

ROM

1KB ROM

0FFFFh−0FFE0h

0FFFFh−0FC00h

2KB ROM

0FFFFh−0FFE0h

0FFFFh−0F800h

4KB ROM

0FFFFh−0FFE0h

0FFFFh−0F000h

Information memory Size

Flash Not applicable Not applicable Not applicable

Boot memory Size

ROM Not applicable Not applicable Not applicable

RAM Size 128 Byte

027Fh − 0200h

128 Byte

027Fh − 0200h

256 Byte

02FFh − 0200h

Peripherals 16-bit

8-bit

8-bit SFR

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

MSP430F1101A MSP430F1111A MSP430F1121A

Memory

Main: interrupt vector

Main: code memory

Size

Flash

1KB Flash

0FFFFh−0FFE0h

0FFFFh−0FC00h

2KB Flash

0FFFFh−0FFE0h

0FFFFh−0F800h

4KB Flash

0FFFFh−0FFE0h

0FFFFh−0F000h

Information memory Size

Flash

128 Byte

010FFh − 01080h

256 Byte

010FFh − 01000h

256 Byte

010FFh − 01000h

Boot memory Size

ROM

1KB

0FFFh − 0C00h

1KB

0FFFh − 0C00h

1KB

0FFFh − 0C00h

RAM Size 128 Byte

027Fh − 0200h

128 Byte

027Fh − 0200h

256 Byte

02FFh − 0200h

Peripherals 16-bit

8-bit

8-bit SFR

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access

to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the

features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap

Loader, Literature Number SLAA089.

BSL FUNCTION DW, PW, AND DGV PACKAGE PINS RGE PACKAGE PINS

Data Transmit 14 - P1.1 14 - P1.1

Data Receive 10 - P2.2 8 - P2.2

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

DFlash memory has n segments of main memory and two segments of information memory (A and B) of

128 bytes each. Each segment in main memory is 512 bytes in size.

DSegments 0 to n may be erased in one step, or each segment may be individually erased.

DSegments A and B can be erased individually, or as a group with segments 0 to n.

Segments A and B are also called information memory.

DNew devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

Segment0 w/

Interrupt Vectors

0FFFFh

0FE00h

Information

Memory

Flash Main Memory

Segment1

Segment2

Segment3

Segment4

Segment5

Segment6

Segment7

SegmentA

SegmentB

0FDFFh

0FC00h

0FBFFh

0FA00h

0F9FFh

0F800h

0F7FFh

0F600h

0F5FFh

0F400h

0F3FFh

0F200h

0F1FFh

0F000h

010FFh

01080h

0107Fh

01000h

NOTE: All segments not implemented on all devices.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number

SLAU049.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic

clock module is designed to meet the requirements of both low system cost and low power consumption. The

internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic clock module

provides the following clock signals:

DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal

DMain clock (MCLK), the system clock used by the CPU

DSub-Main clock (SMCLK), the subsystem clock used by the peripheral modules

digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external

pins):

DAll individual I/O bits are independently programmable.

DAny combination of input, output, and interrupt conditions is possible.

DEdge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2.

DRead/write access to port-control registers is supported by all instructions.

NOTE:

Only six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits

for port P2 are implemented.

watchdog timer (WDT)

The primary function of the WDT module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals.

Comparator_A

The primary function of the Comparator_A module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN NUMBER DEVICE INPUT MODULE MODULE MODULE

OUTPUT

OUTPUT PIN NUMBER

DW, PW, DGV RGE

DEVICE

INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK OUTPUT

SIGNAL DW, PW, DGV RGE

13 - P1.0 13 - P1.0 TACLK TACLK

ACLK ACLK

Timer

SMCLK SMCLK Timer NA

9 - P2.1 7 - P2.1 INCLK INCLK

14 - P1.1 14 - P1.1 TA0 CCI0A 14 - P1.1 14 - P1.1

10 - P2.2 8 - P2.2 TA0 CCI0B

CCR0

TA0

18 - P1.5 18 - P1.5

VSS GND CCR0 TA0

VCC VCC

15 - P1.2 15 - P1.2 TA1 CCI1A 11 - P2.3 10 - P2.3

CAOUT

(internal) CCI1B CCR1 TA1 15 - P1.2 15 - P1.2

VSS GND

CCR1

TA1

19 - P1.6 20 - P1.6

VCC VCC

16 - P1.3 16 - P1.3 TA2 CCI2A 12 - P2.4 11 - P2.4

ACLK (internal) CCI2B

CCR2

TA2

16 - P1.3 16 - P1.3

VSS GND CCR2 TA2 20 - P1.7 21 - P1.7

VCC VCC

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral file map

PERIPHERALS WITH WORD ACCESS

Timer_A Reserved

Reserved

Capture/compare register

Timer_A register

Reserved

Capture/compare control

Timer_A control

Timer_A interrupt vector

TACCR2

TACCR1

TACCR0

TAR

TACCTL2

TACCTL1

TACCTL0

TACTL

TAIV

017Eh

017Ch

017Ah

0178h

0176h

0174h

0172h

0170h

016Eh

016Ch

016Ah

0168h

0166h

0164h

0162h

0160h

012Eh

Flash Memory Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog Watchdog/timer control WDTCTL 0120h

PERIPHERALS WITH BYTE ACCESS

Comparator_A Comparator_A port disable

Comparator_A control 2

Comparator_A control 1

CAPD

CACTL2

CACTL1

05Bh

05Ah

059h

Basic Clock Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

BCSCTL2

BCSCTL1

DCOCTL

058h

057h

056h

Port P2 Port P2 selection

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

Port P2 output

Port P2 input

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P1 Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

Port P1 output

Port P1 input

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

026h

025h

024h

023h

022h

021h

020h

Special Function SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

IE1

003h

002h

001h

000h

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings†

Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (see Note) −0.3 V to VCC+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, Tstg (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, Tstg (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied

to the TEST pin when blowing the JTAG fuse.

recommended operating conditions

MIN NOM MAX UNITS

MSP430C11x1

Supply voltage during program execution V (see Note 1)

MSP430C11x1 1.8 3.6

Supply voltage during program execution, VCC (see Note 1) MSP430F11x1A 1.8 3.6 V

Supply voltage during program/erase flash memory, VCC MSP430F11x1A 2.7 3.6 V

Supply voltage, VSS 0 V

Operating free-air temperature range, TAMSP430x11x1(A) −40 85 °C

LFXT1 t l f f

LF mode selected, XTS=0 Watch crystal 32768 Hz

LFXT1 crystal frequency, f(LFXT1)

(see Notes 1 and 2)

XT1 mode selected XTS 1

Ceramic resonator 450 8000

kHz

(

see

XT1 mode selected, XTS=1 Crystal 1000 8000 kHz

Processor frequency f (MCLK signal)

VCC = 1.8 V,

MSP430x11x1(A) dc 4.15

MHz

Processor frequency f(system) (MCLK signal) VCC = 3.6 V,

MSP430x11x1(A) dc 8

MHz

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1MΩ resistor from XOUT to VSS is recommended when

VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at VCC ≥ 2.2 V. In

XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8 MHz at VCC ≥ 2.8 V.

2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

1.8 V 3.6 V2.7 V 3 V

ÎÎÎÎÎ

4.15 MHz

8.0 MHz

Supply Voltage − V

Supply voltage range, ’F11x1A,

during flash memory programming

Supply voltage range,

’x11x1(A), during

program execution

NOTE: Minimum processor frequency is defined by system clock. Flash

program or erase operations require a minimum VCC of 2.7 V.

fSYSTEM (MHz)

Figure 1. Frequency vs Supply Voltage

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

supply current (into VCC) excluding external current

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

TA = −40°C to 85°C,

f f 1 MHz

2.2 V 160 200

C11x1

f(MCLK) = f(SMCLK) = 1 MHz,

(

ACLK

)

= 32,768 Hz 3 V 240 300

C11x1

TA = −40°C to 85°C, 2.2 V 1.3 2

40 C

85 C

f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz 3 V 2.5 3.2

I(AM) Active mode TA = −40°C to 85°C,

MCLK

= f

(SMCLK)

= 1 MHz, 2.2 V 200 250 μA

F11x1A

fMCLK

f(SMCLK)

MHz

f(ACLK) = 32,768 Hz,

Program executes in flash 3 V 300 350

F11x1A

TA = −40°C to 85°C,

Program executes in flash

2.2 V 3 5

Program executes in flash

(

MCLK

)

= f

(

SMCLK

)

= f

(

ACLK

)

= 4096 Hz 3 V 11 18

C11x1

TA = −40°C to 85°C,

f0f 1 MHz

2.2 V 30 40

Low-power mode

C11x1 f(MCLK) = 0, f(SMCLK) = 1 MHz,

(

ACLK

)

= 32,768 Hz 3 V 51 60

μA

I(CPUOff)

Low power

mode

(LPM0)

F11x1A

TA = −40°C to 85°C,

f0f 1 MHz

2.2 V 32 45

μA

F11x1A f(MCLK) = 0, f(SMCLK) = 1 MHz,

(

ACLK

)

= 32,768 Hz 3 V 55 70

Low power mode (LPM2)

TA = −40°C to 85°C,

f f 0 MHz

2.2 V 11 14

μA

I(LPM2) Low-power mode (LPM2) f(MCLK) = f(SMCLK) = 0 MHz,

(

ACLK

)

= 32,768 Hz, SCG0 = 0 3 V 17 22

μA

C11x1

TA = −40°C to 85°C,

f f 0 MHz

2.2 V 1.2 1.7

C11x1 f(MCLK) = f(SMCLK) = 0 MHz,

(

ACLK

)

= 32,768 Hz, SCG0 = 1 3 V 2 2.7

Low power mode

TA = −40°C 0.8 1.2

I(LPM3)

Low-power mode

(LPM3)

TA = 25°C

f(MCLK) = 0 MHz

2.2 V 0.7 1

μA

(LPM3)

F11x1A

TA = 85°C

(MCLK) =

(SMCLK)

= 0 MHz, 1.6 2.3

μA

F11x1A TA = −40°C

f(SMCLK)

MHz

f(ACLK) = 32,768 Hz,

SCG0 1

1.8 2.2

TA = 25°C

(ACLK)

SCG0 = 1 3 V 1.6 1.9

TA = 85°C 2.3 3.4

TA = −40°C 0.1 0.5

C11x1 TA = 25°C2.2 V/3 V 0.1 0.5

Low-power mode TA = 85°Cf(MCLK) = 0 MHz,

f(SMCLK) = 0 MHz

0.4 0.8

μA

I(LPM4)

Low power

mode

(LPM4) TA = −40°Cf(SMCLK) = 0 MHz,

(ACLK)

= 0 Hz

SCG0 = 1 0.1 0.5 μA

F11x1A TA = 25°C

f(ACLK)

SCG0

2.2 V/3 V 0.1 0.5

TA = 85°C 0.8 1.9

NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.

current consumption of active mode versus system frequency, C version, F version

IAM = IAM[1 MHz] × fsystem [MHz]

current consumption of active mode versus supply voltage, C version

IAM = IAM[3 V] + 105 μA/V × (VCC−3 V)

current consumption of active mode versus supply voltage, F version

IAM = IAM[3 V] + 120 μA/V × (VCC−3 V)

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs − Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5)

PARAMETER VCC MIN TYP MAX UNIT

Positive going input threshold voltage

2.2 V 1.1 1.5

VIT+ Positive-going input threshold voltage 3 V 1.5 1.9 V

Negative going input threshold voltage

2.2 V 0.4 0.9

VIT− Negative-going input threshold voltage 3 V 0.9 1.3 V

Input voltage hysteresis (V V )

2.2 V 0.3 1.1

Vhys Input voltage hysteresis (VIT+ − VIT−)3 V 0.5 1 V

standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK)

PARAMETER VCC MIN TYP MAX UNIT

VIL Low-level input voltage

22V/3V

VSS VSS+0.6 V

VIH High-level input voltage 2.2 V / 3 V 0.8×VCC VCC V

inputs Px.x, TAx

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

P t P1 P2 P1 t P2 E t l t i i l

2.2 V/3 V 1.5 cycle

t(int) External interrupt timing Port P1, P2: P1.x to P2.x, External trigger signal

for the interrupt flag (see Note 1)

2.2 V 62

(int)

for

the

interrupt

flag

(see

Note

3 V 50 ns

t()

Timer A capture timing

TA0 TA1 TA2

2.2 V 62

t(cap) Timer_A, capture timing TA0, TA1, TA2 3 V 50 ns

Timer_A clock frequenc

TACLK INCLK t=t

2.2 V 8

MHz

f(TAext)

Timer

clock

frequency

externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz

Timer A clock frequency

SMCLK or ACLK signal selected

2.2 V 8

MHz

f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected 3 V 10 MHz

NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in

MCLK cycles.

leakage current

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

High impedance leakage current

Port P1: P1.x, 0 ≤ ×≤ 7

(see Notes 1 and 2) 2.2 V/3 V ±50

Ilkg(Px.x) High-impedance leakage current Port P2: P2.x, 0 ≤ ×≤ 5

(see Notes 1 and 2) 2.2 V/3 V ±50

NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional

pullup or pulldown resistor.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I(OHmax) = −1.5 mA

V22V

See Note 1 VCC−0.25 VCC

High-level output voltage

Port 1 and Port 2 (C11x1)

I(OHmax) = −6 mA VCC = 2.2 V See Note 2 VCC−0.6 VCC

VOH Port 1 and Port 2 (C11x1)

rt 1

(

F11x1A

)

I(OHmax) = −1.5 mA

V3V

See Note 1 VCC−0.25 VCC

Port

(F11x1A)

I(OHmax) = −6 mA VCC = 3 V See Note 2 VCC−0.6 VCC

I(OHmax) = −1 mA

V22V

See Note 3 VCC−0.25 VCC

h-level output volta

eI(OHmax) = −3.4 mA VCC = 2.2 V See Note 3 VCC−0.6 VCC

VOH

High level

output

voltage

Port 2 (F11x1A) I(OHmax) = −1 mA

V3V

See Note 3 VCC−0.25 VCC

I(OHmax) = −3.4 mA VCC = 3 V See Note 3 VCC−0.6 VCC

I(OLmax) = 1.5 mA

V22V

See Note 1 VSS VSS+0.25

Low-level output voltage

Port 1 and Port 2 (C11x1

I(OLmax) = 6 mA VCC = 2.2 V See Note 2 VSS VSS+0.6

VOL Port 1 and Port 2 (C11x1,

F11x1A

)

I(OLmax) = 1.5 mA

V=3V

See Note 1 VSS VSS+0.25 V

F11x1A)

I(OLmax) = 6 mA VCC = 3 V See Note 2 VSS VSS+0.6

NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage

drop specified.

2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

3. One output loaded at a time.

output frequency

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fP20 P2.0/ACLK, CL = 20 pF 2.2 V/3 V fSystem

fTAx

Output frequency TA0, TA1, TA2, CL = 20 pF

Internal clock source, SMCLK signal applied (see Note 1) 2.2 V/3 V dc fSystem

MHz

fSMCLK = fLFXT1 = fXT1 40% 60%

P1 4/SMCLK

fSMCLK = fLFXT1 = fLF

2 2 V/3 V

35% 65%

P1.4/SMCLK,

CL = 20 pF fSMCLK = fLFXT1/n

V/3

50%−

15 ns 50% 50%+

15 ns

tXdc Duty cycle of O/P

frequency fSMCLK = fDCOCLK 2.2 V/3 V 50%−

15 ns 50% 50%+

15 ns

frequency

P2 0/ACLK

fP20 = fLFXT1 = fXT1 40% 60%

P2.0/ACLK,

CL=20pF

fP20 = fLFXT1 = fLF 2.2 V/3 V 30% 70%

L =

fP20 = fLFXT1/n 50%

tTAdc TA0, TA1, TA2, CL = 20 pF, duty cycle = 50% 2.2 V/3 V 0±50 ns

NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 and P2 (continued)

Figure 2

VOL − Low-Level Output Voltage − V

0.0 0.5 1.0 1.5 2.0 2.5

VCC = 2.2 V

P1.0

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

TA = 25°C

TA = 85°C

I − Typical Low-Level Output Current − mA

Figure 3

VOL − Low-Level Output Voltage − V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VCC = 3 V

P1.0

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

TA = 25°C

TA = 85°C

I − Typical Low-Level Output Current − mA

Figure 4

VOH − High-Level Output Voltage − V

−14

−12

−10

−8

−6

−4

−2

0.0 0.5 1.0 1.5 2.0 2.5

VCC = 2.2 V

P1.0

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

TA = 25°C

TA = 85°C

I − Typical High-Level Output Current − mA

Figure 5

VOH − High-Level Output Voltage − V

−30

−25

−20

−15

−10

−5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VCC = 3 V

P1.0

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

TA = 25°C

TA = 85°C

I − Typical High-Level Output Current − mA

NOTE: One output loaded at a time.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

optional resistors, individually programmable with ROM code (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R(opt1) 2.5 5 10 kΩ

R(opt2) 3.8 7.7 15 kΩ

R(opt3) 7.6 15 31 kΩ

R(opt4) 11.5 23 46 kΩ

R(opt5) Resistors, individually pro

rammable with ROM code, all port pins,

V2 2 V/3 V

23 45 90 kΩ

R(opt6)

Resistors

individually

programmable

with

ROM

code

all

port

pins

values applicable for pulldown and pullup VCC = 2.2 V/3 V 46 90 180 kΩ

R(opt7) 70 140 280 kΩ

R(opt8) 115 230 460 kΩ

R(opt9) 160 320 640 kΩ

R(opt10) 205 420 830 kΩ

NOTE 1: Optional resistors Roptx for pulldown or pullup are not available in standard flash memory device MSP430F11x1A.

wake-up from low-power modes (LPMx)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t(LPM0) VCC = 2.2 V/3 V 100

t(LPM2) VCC = 2.2 V/3 V 100 ns

f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6

t(LPM3)

Delay time (see Note 1)

f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6μs

(LPM3)

Delay time (see Note 1) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6

f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6

t(LPM4) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6μs

(LPM4)

f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6

NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.

RAM

PARAMETER MIN TYP MAX UNIT

V(RAMh) CPU halted (see Note 1) 1.6 V

NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program

execution should happen during this supply voltage condition.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Comparator_A (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CAON=1 CARSEL=0 CAREF=0

VCC = 2.2 V 25 40

μA

I(DD) CAON=1, CARSEL=0, CAREF=0 VCC = 3 V 45 60 μA

CAON=1, CARSEL=0,

CAREF 1/2/3 no load at

VCC = 2.2 V 30 50

μA

I(Refladder/RefDiode) CAREF=1/2/3, no load at

P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 3 V 45 71 μA

V(IC)

Common-mode input

voltage CAON =1 VCC = 2.2 V/3 V 0 VCC−1 V

V(Ref025)

Voltage @ 0.25 VCC node

VCC

PCA0=1, CARSEL=1, CAREF=1,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

VCC = 2.2 V/3 V 0.23 0.24 0.25

V(Ref050)

Voltage @ 0.5VCC node

VCC

PCA0=1, CARSEL=1, CAREF=2,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

VCC = 2.2 V/3 V 0.47 0.48 0.5

(see Figure 6 and Figure 7)

PCA0=1, CARSEL=1, CAREF=3,

No load at P2 3/CA0/TA1 and

VCC = 2.2 V 390 480 540

V(RefVT) (see Figure 6 and Figure 7) No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2, TA = 85°CVCC = 3 V 400 490 550 mV

V(offset) Offset voltage See Note 2 VCC = 2.2 V/3 V −30 30 mV

Vhys Input hysteresis CAON=1 VCC = 2.2 V/3 V 0 0.7 1.4 mV

TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 160 210 300

25 C

Overdrive

Without filter: CAF=0 VCC = 3 V 90 150 240 ns

t(response LH) TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 1.4 1.9 3.4

μs

25 C

Overdrive

With filter: CAF=1 VCC = 3 V 0.9 1.5 2.6 μs

TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 130 210 300

25 C

Overdrive

Without filter: CAF=0 VCC = 3 V 80 150 240 ns

t(response HL) TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 1.4 1.9 3.4

μs

25 C

Overdrive

With filter: CAF=1 VCC = 3 V 0.9 1.5 2.6 μs

NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.

The two successive measurements are then summed together.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

TA − Free-Air Temperature − °C

400

450

500

550

600

650

−45 −25 −5 15 35 55 75 95

VCC = 3 V

Figure 6. V

(

RefVT

)

vs Temperature, VCC = 3 V

V(REFVT) − Reference Volts −mV

Typical

Figure 7. V

(

RefVT

)

vs Temperature, VCC = 2.2 V

TA − Free-Air Temperature − °C

400

450

500

550

600

650

−45 −25 −5 15 35 55 75 95

VCC = 2.2 V

V(REFVT) − Reference Volts −mV

Typical

CAON

V+ 0

CAF

Low Pass Filter

τ ≈ 2.0 μs

To Internal

Modules

Set CAIFG

Flag

CAOUT

V−

VCC

0 V

Figure 8. Block Diagram of Comparator_A Module

Overdrive VCAOUT

t(response)

V+

V−

400 mV

Figure 9. Overdrive Definition

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

PUC/POR

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t(POR_Delay) Internal time delay to release POR 150 250 μs

VCC threshold at which POR

TA = −40°C 1.4 1.8

VPOR

threshold

which

POR

release delay time begins TA = 25°C 1.1 1.5 V

VPOR

release

delay

time

begins

(see Note 1) TA = 85°CVCC = 2.2 V/3 V 0.8 1.2

V(min)

VCC threshold required to

generate a POR (see Note 2) VCC |dV/dt| ≥ 1V/ms 0.2 V

t(reset) RST/NMI low time for PUC/POR Reset is accepted internally 2μs

NOTES: 1. VCC rise time dV/dt ≥ 1V/ms.

2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less

than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms.

VCC

POR

VPOR

(min)

POR

No POR

Figure 10. Power-On Reset (POR) vs Supply Voltage

0.2

0.6

1.0

1.2

1.8

2.0

−40 −20 0 20 40 60 80

Temperature [°C]

V POR [V]

1.6

1.4

0.8

0.4

1.2

1.5

1.8

0.8

1.1

1.4

25°C

Max

Min

Figure 11. VPOR vs Temperature

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

DCO

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

R0 DCO 3 MOD 0 DCOR 0 T 25°C

2.2 V 0.08 0.12 0.15

MHz

f(DCO03) Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.08 0.13 0.16 MHz

R1 DCO 3 MOD 0 DCOR 0 T 25°C

2.2 V 0.14 0.19 0.23

MHz

f(DCO13) Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.14 0.18 0.22 MHz

f(CO )

R=2 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 0.22 0.30 0.36

MHz

f(DCO23) Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.22 0.28 0.34 MHz

R=3 DCO=3 MOD=0 DCOR=0 T =25°C

2.2 V 0.37 0.49 0.59

MHz

f(DCO33) Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.37 0.47 0.56 MHz

R=4 DCO=3 MOD=0 DCOR=0 T =25°C

2.2 V 0.61 0.77 0.93

MHz

f(DCO43) Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.61 0.75 0.9 MHz

R=5 DCO=3 MOD=0 DCOR=0 T =25°C

2.2 V 1 1.2 1.5

MHz

f(DCO53) Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 1 1.3 1.5 MHz

R=6 DCO=3 MOD=0 DCOR=0 T =25°C

2.2 V 1.6 1.9 2.2

MHz

f(DCO63) Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 1.69 2 2.29 MHz

R=7 DCO=3 MOD=0 DCOR=0 T =25°C

2.2 V 2.4 2.9 3.4

MHz

f(DCO73) Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 2.7 3.2 3.65 MHz

R=7 DCO=7 MOD=0 DCOR=0 T =25°C

2.2 V 4 4.5 4.9

MHz

f(DCO77) Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C3 V 4.4 4.9 5.4 MHz

R=4 DCO=7 MOD=0 DCOR=0 T =25°C

2 2 V/3 V

MHz

f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C2.2 V/3 V

fDCO40

x1.7

fDCO40

x2.1

fDCO40

x2.5 MHz

S(Rsel) SR = fRsel+1/fRsel 2.2 V/3 V 1.35 1.65 2

ratio

S(DCO) SDCO = fDCO+1/fDCO 2.2 V/3 V 1.07 1.12 1.16 ratio

Temperature drift R = 4 DCO = 3 MOD = 0 (see Note 1)

2.2 V −0.31 −0.36 −0.40

%/°C

DtTemperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) 3 V −0.33 −0.38 −0.43 %/°C

DVDrift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) 2.2 V/3 V 0 5 10 %/V

NOTE 1: These parameters are not production tested.

ÎÎÎÎÎ

2.2 V 3 V

VCC

Max

Min

Max

Min

f(DCOx7)

f(DCOx0)

Frequency Variance

012 34567

DCO Steps

fDCOCLK

Figure 12. DCO Characteristics

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

main DCO characteristics

DIndividual devices have a minimum and maximum operation frequency. The specified parameters for

f(DCOx0) to f(DCOx7) are valid for all devices.

DAll ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.

DDCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.

DModulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK

cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:

faverage +32 f(DCO) f(DCO)1)

MOD f(DCO))(32*MOD) f(DCO)1)

DCO when using ROSC (see Note 1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fCO DCO output frequency

R=4 DCO=3 MOD=0 DCOR=1 T =25

2.2 V 1.8±15% MHz

fDCO, DCO output frequency Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25°C3 V 1.95±15% MHz

Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 %/°C

Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 %/V

NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.

crystal oscillator, LFXT1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input capacitance

XTS=0, LF mode selected,

VCC = 2.2 V / 3 V 12

CXIN Input capacitance XTS=1, XT1 mode selected,

VCC = 2.2 V / 3 V (see Note 1) 2

Output capacitance

XTS=0, LF mode selected,

VCC = 2.2 V / 3 V 12

CXOUT Output capacitance XTS=1, XT1 mode selected,

VCC = 2.2 V / 3 V (see Note 1) 2

VIL

Input levels at XIN

V= 2 2 V/3 V (see Note 2)

VSS 0.2×VCC

VIH

Input levels at XIN VCC = 2.2 V/3 V (see Note 2) 0.8×VCC VCC

NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

flash memory

PARAMETER TEST

CONDITIONS VCC MIN TYP MAX UNIT

VCC(PGM/

ERASE) Program and erase supply voltage 2.7 3.6 V

fFTG Flash Timing Generator frequency 257 476 kHz

IPGM Supply current from VCC during program 2.7 V/ 3.6 V 3 5 mA

IERASE Supply current from VCC during erase 2.7 V/ 3.6 V 3 7 mA

tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 4 ms

tCMErase Cumulative mass erase time See Note 2 2.7 V/ 3.6 V 200 ms

Program/erase endurance 104105cycles

tRetention Data retention duration TJ = 25°C 100 years

tWord Word or byte program time 35

tBlock, 0Block program time for first byte or word 30

tBlock, 1-63 Block program time for each additional byte or word

See Note 3

tBlock, End Block program end-sequence wait time See Note 3 6tFTG

tMass Erase Mass erase time 5297

tSeg Erase Segment erase time 4819

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To

achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.

(A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).

JTAG interface

PARAMETER TEST

CONDITIONS VCC MIN TYP MAX UNIT

TCK input frequency

see Note 1

2.2 V 0 5 MHz

fTCK TCK input frequency see Note 1 3 V 0 10 MHz

RInternal Internal pulldown resistance on TEST see Note 2 2.2 V/ 3 V 25 60 90 kΩ

NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.

2. TEST pull-down resistor implemented in all versions.

JTAG fuse (see Note 1)

PARAMETER TEST

CONDITIONS VCC MIN TYP MAX UNIT

VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V

Voltage level on TEST for fuse blow (’C11x1) 3.5 3.9 V

VFB Voltage level on TEST for fuse blow (’F11x1A) 6 7 V

IFB Supply current into TEST during fuse blow 100 mA

tFB Time to blow fuse 1 ms

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation (F versions only) features is possible. The JTAG

block is switched to bypass mode.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.3, input/output with Schmitt trigger

(See Note 1)

(See Note 2)

(See Note 1)

GND

VCC

P1.0 − P1.3

Interrupt

Edge

Select

Set

P1IE.x

P1IFG.x

P1IRQ.x

Interrupt

Flag P1IES.x

P1SEL.x

Module X IN

P1IN.x

P1OUT.x

Module X OUT

Direction Control

From Module

P1DIR.x

P1SEL.x

Pad Logic

NOTE: x = Bit/identifier, 0 to 3 for port P1

PnSel.x PnDIR.x

Direction

control from

module

PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x

P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 VSS P1IN.0 TACLK†P1IE.0 P1IFG.0 P1IES.0

P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal†P1IN.1 CCI0A†P1IE.1 P1IFG.1 P1IES.1

P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 signal†P1IN.2 CCI1A†P1IE.2 P1IFG.2 P1IES.2

P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal†P1IN.3 CCI2A†P1IE.3 P1IFG.3 P1IES.3

†Signal from or to Timer_A

NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions

2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P1, P1.4 to P1.7, input/output with Schmitt trigger and in-system access features

See Note 1

See Note 2

See Note 1

GND

VCC

P1.4−P1.7

Interrupt

Edge

Select

Set

P1IE.x

P1IFG.x

P1IRQ.x

Interrupt

Flag P1IES.x

P1SEL.x

Module X IN

P1IN.x

P1OUT.x

Module X OUT

Direction Control

From Module

P1DIR.x

P1SEL.x

Pad Logic

Bus Keeper

TST

Fuse 60 kΩ

Fuse

Blow

Control

Control By JTAG

TDO

Controlled By JTAG

P1.x

TDI P1.x

TST

TMS

TST

TCK

TST

Controlled by JTAG

TST

P1.x

NOTE: The test pin should be protected from potential EMI

and ESD voltage spikes. This may require a smaller

external pulldown resistor in some applications.

x = Bit identifier, 4 to 7 for port P1

During programming activity and during blowing

of the fuse, the pin TDO/TDI is used to apply the test

input for JTAG circuitry.

P1.7/TDI/TDO

P1.6/TDI/TCLK

P1.5/TMS

P1.4/TCK

Typical

TEST

GND

PnSel.x PnDIR.x

Direction

control from

module

PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x

P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4

P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 signal†P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5

P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal†P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6

P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 Out2 signal†P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7

†Signal from or to Timer_A

NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions

2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P2, P2.0 to P2.2, input/output with Schmitt trigger

See Note 1

See Note 2

See Note 1

GND

VCC

P2.0 − P2.2

Interrupt

Edge

Select

Set

P2IE.x

P2IFG.x

P2IRQ.x

Interrupt

Flag P2IES.x

P2SEL.x

Module X IN

P2IN.x

P2OUT.x

Module X OUT

Direction Control

From Module

P2DIR.x

P2SEL.x

Pad Logic

NOTE: x = Bit Identifier, 0 to 2 for port P2

0: Input

1: Output

Bus Keeper

CAPD.X

PnSel.x PnDIR.x

Direction

control from

module

PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x

P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P1IES.0

P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 VSS P2IN.1 INCLK†P2IE.1 P2IFG.1 P1IES.1

P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT P2IN.2 CCI0B†P2IE.2 P2IFG.2 P1IES.2

†Signal from or to Timer_A

NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions

2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P2, P2.3 to P2.4, input/output with Schmitt trigger

See Note 1

See Note 2

See Note 1

GND

VCC

P2.3

Interrupt

Edge

Select

Set

P2IE.3

P2IFG.3

P2IRQ.3

Interrupt

Flag P2IES.3 P2SEL.3

Module X IN

P2IN.3

P2OUT.3

Module X

OUT

Direction Control

From Module

P2DIR.3

P2SEL.3

Pad Logic

0: Input

1: Output

Bus Keeper

CAPD.3

See Note 1

See Note 2

See Note 1

P2.4

Interrupt

Edge

Select

Set

P2IE.4

P2IFG.4

P2IRQ.4

Interrupt

Flag

P2IES.4 P2SEL.4

Module X IN

P2IN.4

P2OUT.4

Module X OUT

Direction Control

From Module

P2DIR.4

P2SEL.4

Pad Logic

0: Input

1: Output

Bus Keeper

CAPD.4

Comparator_A

Reference Block

CAREF

CAREF CAEXP2CA

CAF

CCI1B

0 V

VCC

GND

PnSel.x PnDIR.x Direction

control from module

PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x

P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal†P2IN.3 unused P2IE.3 P2IFG.3 P1IES.3

P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal†P2IN.4 unused P2IE.4 P2IFG.4 P1IES.4

†Signal from Timer_A

NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions

2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P2, P2.5, input/output with Schmitt trigger and ROSC function for the Basic Clock module

See Note 1

See Note 2

See Note 1

GND

VCC

P2.5

Interrupt

Edge

Select

Set

P2IE.5

P2IFG.5

P2IRQ.5

Interrupt

Flag P2IES.5

P2SEL.5

Module X IN

P2IN.5

P2OUT.5

Module X OUT

Direction Control

From Module

P2DIR.5

P2SEL.5 Pad Logic

NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad

Bus Keeper

VCC

Internal to

Basic Clock

Module

DCOR DC

Generator

0: Input

1: Output

CAPD.5

PnSel.x PnDIR.x

Direction

control from

module

PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x

P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5

NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions

2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P2, unbonded bits P2.6 and P2.7

Interrupt

Edge

Select

Set

P2IE.x

P2IFG.x

P2IRQ.x

Interrupt

Flag P2IES.x

P2SEL.x

Module X IN

P2IN.x

P2OUT.x

Module X OUT

Direction Control

From Module

P2DIR.x

P2SEL.x

Bus Keeper

0: Input

1: Output

Node Is Reset With PUC

PUC

NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins

P2Sel.x P2DIR.x

Direction

control from

module

P2OUT.x Module X OUT P2IN.x Module X IN P2IE.x P2IFG.x P2IES.x

P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 VSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6

P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7

NOTE 1: Unbonded bits 6 and 7 of port P2 can be used as software interrupt flags. The interrupt flags can only be influenced by software. They

work then as a software interrupt.

MSP430C11x1, MSP430F11x1A

MIXED SIGNAL MICROCONTROLLER

SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

JTAG fuse check mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of

the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care

must be taken to avoid accidentally activating the fuse check mode and increasing overall system power

consumption.

When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense

currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS

is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.

After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse

check mode has the potential to be activated.

The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see

Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Time TMS Goes Low After POR

TMS

ITF

ITEST

Figure 13. Fuse Check Mode Current, MSP430F11x1A and MSP430C11x1

NOTE:

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader

access key is used. Also, see the bootstrap loader section for more information.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430A003IPWR OBSOLETE TSSOP PW 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430C1101 ACTIVE TBD Call TI Call TI

MSP430F1101AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1101AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1101AIDW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101AIPW ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101AIRGER ACTIVE VQFN RGE 24 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1101AIRGET ACTIVE VQFN RGE 24 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1101IDW NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101IDWR NRND SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101IPW NRND TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1101IPWR NRND TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1111AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1111AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1111AIDW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430F1111AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1111AIPW ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1111AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1111AIRGER ACTIVE VQFN RGE 24 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1111AIRGET ACTIVE VQFN RGE 24 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1121AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1121AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1121AIDW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121AIPW ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121AIRGER ACTIVE VQFN RGE 24 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1121AIRGET ACTIVE VQFN RGE 24 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F1121CY NRND DIESALE Y 0 TBD Call TI Call TI

MSP430F1121IDW NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121IDWR NRND SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121IPW NRND TSSOP PW 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F1121IPWR NRND TSSOP PW 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2012

Addendum-Page 3

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

MSP430F1101AIDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

MSP430F1101AIDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

MSP430F1101AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

MSP430F1101IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

MSP430F1101IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

MSP430F1111AIDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

MSP430F1111AIDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

MSP430F1111AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

MSP430F1121AIDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

MSP430F1121AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430F1101AIDGVR TVSOP DGV 20 2000 367.0 367.0 35.0

MSP430F1101AIDWR SOIC DW 20 2000 367.0 367.0 45.0

MSP430F1101AIPWR TSSOP PW 20 2000 367.0 367.0 38.0

MSP430F1101IDWR SOIC DW 20 2000 367.0 367.0 45.0

MSP430F1101IPWR TSSOP PW 20 2000 367.0 367.0 38.0

MSP430F1111AIDGVR TVSOP DGV 20 2000 367.0 367.0 35.0

MSP430F1111AIDWR SOIC DW 20 2000 367.0 367.0 45.0

MSP430F1111AIPWR TSSOP PW 20 2000 367.0 367.0 38.0

MSP430F1121AIDGVR TVSOP DGV 20 2000 367.0 367.0 35.0

MSP430F1121AIPWR TSSOP PW 20 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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