LTC3865/LTC3865-1
1
3865fb
TYPICAL APPLICATION
DESCRIPTION
Dual, 2-Phase Synchronous
DC/DC Controller with
Pin Selectable Outputs
The LTC
®
3865/LTC3865-1 are high performance dual
synchronous step-down DC/DC switching regulator
controllers that drive all N-channel synchronous power
MOSFET stages. A constant frequency current mode
architecture allows a phase-lockable frequency of up to
770kHz. Power loss and noise are minimized by operating
the two controller output stages out of phase.
OPTI-LOOP
®
compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. Independent track/soft-start pins for
each controller ramp the output voltage during start-up.
Current foldback limits MOSFET heat dissipation during
short-circuit conditions. The MODE/PLLIN pin selects
among Burst Mode
®
operation, pulse-skipping mode,
and continuous inductor current mode. The output volt-
ages can be precisely programmed by pin strapping or
external resistors.
The LTC3865/LTC3865-1 are available in low profi le (5mm
× 5mm) 32-pin QFN and 38-Lead thermally enhanced
TSSOP packages.
FEATURES
APPLICATIONS
n Dual, 180° Phased Controllers
n 2-Pin VID Output Voltage Programming from 0.6V
to 5V
n High Effi ciency: Up to 95%
n RSENSE or DCR Current Sensing
n Phase-Lockable Fixed Frequency 250kHz to 770kHz
n Adjustable Current Limit
n Dual N-Channel MOSFET Synchronous Drive
n Wide VIN Range: 4.5V to 38V Operation
n Adjustable Soft-Start Current Ramping or Tracking
n Output OV Protection With Reverse Current Limit
n Power Good Output Voltage Monitor
n 32-Pin 5mm × 5mm QFN and 38-Lead TSSOP
Packages
n DC Power Distribution Systems
High Effi ciency 1.5V/15A, 1.2V/15A Step-Down Converter
0.1µF
0.47µH
1000pF
1000pF 1000pF
22µF
50V
10k
VOUT1
1.5V
15A
0.1µF
0.47µH
1000pF
100µF
15k
162k
VOUT2
1.2V
15A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
SENSE1–SENSE2–
VOSENSE1 VOSENSE2
ITH1 ITH2
VIN INTVCC
TK/SS1 TK/SS2
VIN
4.5V TO 24V
3865 TA01a
0.1µF
100pF 0.1µF
LTC3865
VID11
VID12
VID21
VID22
4.7µF
100µF
COUT2,3
100pF
100Ω
100Ω
100Ω
100Ω
2.2Ω
1µF
2mΩ 2mΩ
+
COUT5,6
+
+
LOAD CURRENT (A)
30
EFFICIENCY (%)
POWER LOSS (W)
90
100
20
10
80
50
70
60
40
0.01 1 10 100
3865 TA01b
0
0.1
10
1
0.01
0.1
VIN = 12V
VOUT = 1.5V
EFFICIENCY
POWER LOSS
Effi ciency and Power Loss
vs Load Current
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, µModule, Linear Technology and the Linear logo
are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All
other trademarks are the property of their respective owners. U.S. Patents, including 5481178,
5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.
LTC3865/LTC3865-1
2
3865fb
Input Supply Voltage (VIN) ......................... –0.3V to 40V
Topside Driver Voltages
BOOST1, BOOST2 .................................. –0.3V to 46V
Switch Voltage (SW1, SW2) ......................... –5V to 40V
INTVCC, RUN1, RUN2, PGOOD(s), EXTVCC,
(BOOST1-SW1), (BOOST2-SW2) ................. –0.3V to 6V
SENSE1+, SENSE2+, SENSE1–, SENSE2–
VOSENSE1, VOSENSE2 Voltages .................... –0.3V to 5.8V
MODE/PLLIN, ILIM, TK/SS1, TK/SS2, VID11,
VID12, VID21, VID22, FREQ Voltages ... –0.3V to INTVCC
(Note 1)
ABSOLUTE MAXIMUM RATINGS
LTC3865 LTC3865
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
33
SGND
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1VOSENSE1
TK/SS1
ITH1
VID11
VID12
ITH2
TK/SS2
VOSENSE2
BOOST1
BG1
VIN
INTVCC
EXTVCC
BG2
PGND
BOOST2
SENSE1–
SENSE1+
RUN1
FREQ
VID22
MODE/PLLIN
SW1
TG1
SENSE2–
SENSE2+
RUN2
VID21
ILIM
PGOOD
SW2
TG2
TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RUN1
SENSE1+
SENSE–
NC
VOSENSE1
TK/SS1
ITH1
SGND
VID11
VID12
ITH2
TK/SS2
VOSENSE2
NC
SENSE2–
SENSE2+
RUN2
VID21
ILIM
FREQ
VID22
MODE/PLLIN
SW1
TG1
BOOST1
PGND1
BG1
VIN
INTVCC
EXTVCC
BG2
PGND2
BOOST2
NC
TG2
SW2
PGOOD1
PGOOD2
39
SGND
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
ITH1, ITH2 Voltages .................................... –0.3V to 2.7V
INTVCC DC Output Current (Note 9) .......................80mA
Operating Junction Temperature Range (Notes 2, 3)
LTC3865/LTC3865-1 .......................... –40°C to 125°C
Storage Temperature Range ................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
FE Package ....................................................... 300°C
LTC3865/LTC3865-1
3
3865fb
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3865EUH#PBF LTC3865EUH#TRPBF 3865 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3865EUH-1#PBF LTC3865EUH-1#TRPBF 38651 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3865IUH#PBF LTC3865IUH#TRPBF 3865 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3865IUH-1#PBF LTC3865IUH-1#TRPBF 38651 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3865EFE#PBF LTC3865EFE#TRPBF LTC3865FE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3865IFE#PBF LTC3865IFE#TRPBF LTC3865FE 38-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
PIN CONFIGURATION
LTC3865-1
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
33
SGND
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1VOSENSE1
TK/SS1
ITH1
VID11
VID12
ITH2
TK/SS2
VOSENSE2
BOOST1
BG1
VIN
INTVCC
EXTVCC
BG2
PGND
BOOST2
SENSE1–
SENSE1+
RUN1
FREQ
VID22
MODE/PLLIN
SW1
TG1
SENSE2–
SENSE2+
RUN2
VID21
PGOOD2
PGOOD1
SW2
TG2
TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
LTC3865/LTC3865-1
4
3865fb
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VIN Input Voltage 4.5 38 V
VOSENSE1,2 Output Voltage Sensing (E-Grade) (Note 4) ITH1,2 Voltage = 1.2V
VID11 = VID21 = GND, VID12 = VID22 = GND
VID11 = VID21 = GND, VID12 = VID22 = Float
VID11 = VID21 = GND, VID12 = VID22 = INTVCC
VID11 = VID21 = Float, VID12 = VID22 = GND
VID11 = VID21 = Float, VID12 = VID22 = Float
VID11 = VID21 = Float, VID12 = VID22 = INTVCC
VID11 = VID21 = INTVCC, VID12 = VID22 = GND
VID11 = VID21 = INTVCC, VID12 = VID22 = Float
VID11 = VID21 = INTVCC, VID12 = VID22 = INTVCC
l
l
l
l
l
l
l
l
l
1.089
0.990
1.188
1.485
0.596
1.782
2.463
3.251
4.925
1.100
1.000
1.200
1.500
0.602
1.800
2.500
3.300
5.000
1.111
1.010
1.212
1.515
0.608
1.818
2.538
3.350
5.075
V
V
V
V
V
V
V
V
V
Output Voltage Sensing (I-Grade) (Note 4) ITH1,2 Voltage = 1.2V
VID11 = VID21 = GND, VID12 = VID22 = GND
VID11 = VID21 = GND, VID12 = VID22 = Float
VID11 = VID21 = GND, VID12 = VID22 = INTVCC
VID11 = VID21 = Float, VID12 = VID22 = GND
VID11 = VID21 = Float, VID12 = VID22 = Float
VID11 = VID21 = Float, VID12 = VID22 = INTVCC
VID11 = VID21 = INTVCC, VID12 = VID22 = GND
VID11 = VID21 = INTVCC, VID12 = VID22 = Float
VID11 = VID21 = INTVCC, VID12 = VID22 = INTVCC
l
l
l
l
l
l
l
l
l
1.084
0.985
1.182
1.478
0.593
1.773
2.450
3.234
4.900
1.100
1.000
1.200
1.500
0.602
1.800
2.500
3.300
5.000
1.117
1.015
1.218
1.523
0.611
1.827
2.550
3.366
5.100
V
V
V
V
V
V
V
V
V
IOSENSE1,2 Feedback Current (Note 4) VID11 = VID21 = VID12 = VID22 = Float –10 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 4.5V to 38V (Note 4) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔITH Voltage = 1.2V to 1.6V
l
l
0.01
–0.01
0.1
–0.1
%
%
gm1,2 Transconductance Amplifi er gmITH1,2 = 1.2V; Sink/Source 5µA; (Note 4) 2.2 mmho
IQInput DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V
VRUN1,2 = 0V
3
30 50
mA
µA
UVLO Undervoltage Lockout on INTVCC VINTVCC Ramping Down 3.3 V
UVLOHYS UVLO Hysteresis 0.55 V
VOVL Feedback Overvoltage Lockout Measured at VOSENSE1,2 with VID Pins Floating l0.64 0.66 0.68 V
ISENSE Sense Pins Total Current (Each Channel); VSENSE1,2 = 3.3V ±1 ±2 µA
DFMAX Maximum Duty Cycle In Dropout 94 95 %
ITK/SS1,2 Soft-Start Charge Current VTK/SS1,2 = 0V 0.9 1.3 1.7 µA
VRUN1,2 RUN Pin On Threshold VRUN1, VRUN2 Rising l1.1 1.22 1.35 V
VRUN1,2HYS RUN Pin On Hysteresis 80 mV
IRUN1,2HYS RUN Pin Current Hysteresis 4.5 µA
VSENSE(MAX) Maximum Current Sense Threshold
(E-Grade)
VITH1,2 = 3.3V, ILIM = 0V
VITH1,2 = 3.3V, ILIM = Float (Note 8)
VITH1,2 = 3.3V, ILIM = INTVCC
In Overvoltage Condition
l
l
l
l
24
44
68
–63
30
50
75
–53
36
56
82
–43
mV
mV
mV
mV
Maximum Current Sense Threshold
(I-Grade)
VITH1,2 = 3.3V, ILIM = 0V
VITH1,2 = 3.3V, ILIM = Float (Note 8)
VITH1,2 = 3.3V, ILIM = INTVCC
In Overvoltage Condition
l
l
l
l
22
42
66
–65
30
50
75
–53
38
58
84
–41
mV
mV
mV
mV
TG RUP TG Driver Pull-Up On-Resistance TG High 2.6
TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.5
BG RUP BG Driver Pull-Up On-Resistance BG High 3
LTC3865/LTC3865-1
5
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3865/LTC3865-1 are tested under pulsed load conditions
such that TJ ≈ TA. The LTC3865E/LTC3865E-1 are guaranteed to meet
performance specifi cations over the 0°C to 85°C operating junction
temperature range. Specifi cations over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3865I/LTC3865I-1
are guaranteed to meet performance specifi cations over the full –40°C
to 125°C operating junction temperature range. Note that the maximum
ambient temperature consistent with these specifi cations is determined by
specifi c operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3865UH: TJ = TA + (PD • 34°C/W)
LTC3865FE: TJ = TA + (PD • 25°C/W)
Note 4: The LTC3865/LTC3865-1 are tested in a feedback loop that servos
VITH1,2 to a specifi ed voltage and measures the resultant VOSENSE1,2.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specifi ed for an inductor peak-
to-peak ripple current 40% of IMAX (see Minimum On-Time Considerations
in the Applications Information section).
Note 8: VSENSE(MAX) defaults to 50mV for the LTC3865-1.
Note 9: Guaranteed by design.
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
BG RDOWN BG Driver Pull-Down On-Resistance BG Low 1.4
TG1,2 tr
TG1,2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
BG1,2 tr
BG1,2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver 30 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver 30 ns
tON(MIN) Minimum On-Time (Note 7) 90 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN < 38V 4.8 5.0 5.2 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 20mA 0.5 2 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l4.5 4.7 V
VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 50 100 mV
VLDOHYS EXTVCC Hysteresis 200 mV
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency RFREQ = 162k 450 500 550 kHz
fLOW Lowest Frequency RFREQ = 0 210 250 290 kHz
fHIGH Highest Frequency RFREQ ≥ 325k 650 770 880 kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ
IFREQ Frequency Setting Current VFREQ = 1.22V 6.5 7.5 8.5 µA
PGOOD OUTPUT
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±2 µA
VPG PGOOD Trip Level VOSENSE with Respect to Set Regulated Voltage
VID11 = VID12 = VID21 = VID22 = Float
VOSENSE Ramping Negative
VOSENSE Ramping Postitive
–7
7
–10
10
–12.5
12.5
%
%
tPG PGOOD Bad Blanking Time Measured from VID Transitition Edge 100 µs
LTC3865/LTC3865-1
6
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Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load Prebiased Output at 1V Coincident Tracking
VOUT
100mV/DIV
AC-
COUPLED
ILOAD
5A/DIV
500mA
TO 7A
IL
5A/DIV
40µs/DIVVIN = 12V
VOUT = 1.5V
FIGURE 16 CIRCUIT
3865 G01
VOUT
100mV/DIV
AC-
COUPLED
ILOAD
5A/DIV
500mA
TO 7A
IL
5A/DIV
40µs/DIV 3865 G02
VIN = 12V
VOUT = 1.5V
FIGURE 16 CIRCUIT
VOUT
100mV/DIV
AC-
COUPLED
ILOAD
5A/DIV
500mA
TO 7A
IL
5A/DIV
40µs/DIV 3865 G03
VIN = 12V
VOUT = 1.5V
FIGURE 16 CIRCUIT
RUN
2V/DIV
VTRACK/SS
1V/DIV
VOUT = 1.5V
500mV/DIV
40ms/DIV 3865 G05
FORCED
CONTINUOUS
MODE
5A/DIV
PULSE-
SKIPPING MODE
5A/DIV
Burst Mode
OPERATION
5A/DIV
2µs/DIVVIN = 12V
VOUT = 1.5V
ILOAD = 100mA
FIGURE 16 CIRCUIT
3865 G04
RUN1
2V/DIV
40ms/DIV 3865 G06
VOUT2 = 1.2V
1 LOAD
500mV/DIV
VOUT1 = 1.5V
1 LOAD
500mV/DIV
TYPICAL PERFORMANCE CHARACTERISTICS
Effi ciency vs Load Current Effi ciency vs Load Current
Effi ciency and Power Loss
vs Input Voltage
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10 100
3865 G23
0
0.1
VIN = 12V
VOUT = 1.5V
FIGURE 16 CIRCUIT
BURST
DCM CCM
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10 100
3865 G24
0
0.1
VIN = 12V
VOUT = 1.2V
FIGURE 16 CIRCUIT
BURST
DCM CCM
INPUT VOLTAGE (V)
0
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
3865 G25
40
30
20 10 20
80
90
100
3
2
1
0
4
5
30
EFFICIENCY
POWER LOSS
FIGURE 16 CIRCUIT
LTC3865/LTC3865-1
7
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TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
Maximum Current Sense
Threshold vs Common Mode
Voltage
Maximum Current Sense
Threshold vs Duty Cycle
TK/SS Pull-Up Current
vs Temperature
Tracking Up and Down with
External Ramp
(Forced Continuous Mode)
Quiescent Current vs Input
Voltage without EXTVCC INTVCC Line Regulation
Maximum Current Sense
Voltage vs Feedback Voltage
(Current Foldback)
VITH (V)
0
–40
VSENSE (mV)
–20
0
20
40
60
80
0.5 1 1.5 2
3865 G10
ILIM = INTVCC
ILIM = GND
ILIM = FLOAT
VSENSE COMMON MODE VOLTAGE (V)
0
CURRENT SENSE THRESHOLD (mV)
30
40
50
35
20
10
012 4
60
70
80
3865 G11
ILIM = INTVCC
ILIM = GND
ILIM = FLOAT
60
80
100
40
20
50
70
90
30
10
0
DUTY CYCLE (%)
0
CURRENT SENSE THRESHOLD (mV)
60 100
20 40 80
3865 G12
ILIM = INTVCC
ILIM = GND
ILIM = FLOAT
TK/SS1
TK/SS2
2V/DIV
VOUT1 = 1.5V
1 LOAD
500mV/DIV
VOUT2 = 1.2V
1 LOAD
500mV/DIV
20ms/DIV 3865 G07
INPUT VOLTAGE (V)
0
INTVCC VOLTAGE (V)
4.25
4.50
4.75
40
3865 G09
4.00
3.50
3.75
3.00 10 20 30
515 25 35
3.25
5.25
5.00
FEEDBACK VOLTAGE (V)
0
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
20
40
60
0.1 0.2 0.3 0.4
3865 G13
0.5
80
100
10
30
50
70
90
0.6
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
TEMPERATURE (°C)
–50
TK/SS CURRENT (µA)
1.75
25
3865 G14
1.00
0.50
–25 0 50
0.25
0
2.00
1.50
1.25
0.75
75 100 125
INPUT VOLTAGE (V)
510
0
QUIESCENT CURRENT (mA)
2
5
15 25 30
3865 G08
1
4
3
20 35 40
LTC3865/LTC3865-1
8
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TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
Oscillator Frequency
vs Input Voltage
Shutdown Current
vs Input Voltage
Shutdown Current vs Temperature
Quiescent Current vs Temperature
without EXTVCC
TEMPERATURE (°C)
–50 –25
0
INTVCC VOLTAGE (V)
2
5
050 75
3865 G18
1
4
3
25 100 125
FALLING
RISING
INPUT VOLTAGE (V)
4
450
FREQUENCY (kHz)
470
490
510
10 16 22 28
3865 G19
34
530
550
460
480
500
520
540
40
INPUT VOLTAGE (V)
05
0
INPUT CURRENT (µA)
20
50
10 20 25
3865 G20
10
40
30
15 30 35 40
TEMPERATURE (°C)
–50 –25
0
QUIESCENT CURRENT (mA)
2
5
050 75
3865 G22
1
4
3
25 100 125
VIN = 15V
TEMPERATURE (°C)
–50 –25
0
SHUTDOWN CURRENT (µA)
20
50
050 75
3865 G21
10
40
30
25 100 125
VIN = 15V
Regulated Feedback Voltage
vs Temperature
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50
100
OSCILLATOR FREQUENCY (kHz)
200
400
500
600
50
1000
3865 G17
300
0
–25 75 100
25 125
700
800
900 VFREQ = INTVCC
VFREQ = 1.2V
VFREQ = 0V
TEMPERATURE (°C)
–50
REGULATED FEEDBACK VOLTAGE (V)
0.604
0.606
0.608
25 75
3865 G16
0.602
0.600
–25 0 50 100 125
0.598
0.596
Shutdown (RUN) Threshold
vs Temperature
TEMPERATURE (°C)
–50 –25
1.0
RUN PIN VOLTAGE (V)
1.2
1.5
050 75
3865 G15
1.1
1.4
1.3
25 100 125
OFF
ON
LTC3865/LTC3865-1
9
3865fb
PIN FUNCTIONS
(QFN/TSSOP)
VOSENSE1, VOSENSE2 (Pins 1, 8/Pins 5, 13): When the
internal programmable resistive divider is used, these
pins must be connected to their corresponding outputs.
When an external resistive divider is used, these pins are
used for error amplifi er feedback inputs. They receive
the remotely sensed feedback voltages for each channel
directly from the outputs or from the external divider
across the outputs.
TK/SS1, TK/SS2 (Pins 2, 7/Pins 6, 12): Output Voltage
Tracking and Soft-Start Inputs. When one channel is
confi gured to be master of the two channels, a capacitor
to ground at this pin sets the ramp rate for the master
channel’s output voltage. When a channel is confi gured
to be the slave of the two channels, the output voltage
ramp of the master channel can be reproduced by a re-
sistor divider and applied to this pin of the slave channel.
Internal soft-start currents of 1.3µA charge the soft-start
capacitors.
ITH1, ITH2 (Pins 3, 6/Pins 7, 11): Current Control Thresholds
and Error Amplifi er Compensation Points. Each associated
channels’ current comparator tripping threshold increases
with its ITH control voltage.
VID11, VID12, VID21, VID22 (Pins 4, 5, 12, 28/ Pins 9,
10, 18, 37): VID Inputs for Output Voltage Programming.
Tie these pins to INTVCC, GND or leave them fl oating to
set the output voltages.
ILIM (Pin 13/Pin 19) (LTC3865 Only): Current Compara-
tor Sense Voltage Range Inputs. This pin can be tied to
SGND, FLOAT or INTVCC to set the maximum current
sense threshold for each comparator. Current compara-
tor sense voltage range of the LTC3865-1 is set to default
value of 50mV.
PGOOD (Pin 14 LTC3865/NA): Co-Bonded Power Good
Indicator Output for LTC3865 in QFN Package. Open-drain
logic output that is pulled to ground when either channel
output exceeds ±10% regulation window, after the internal
20µs power bad mask timer expires.
PGOOD1, PGOOD2 (Pins 14, 13 LTC3865-1/Pins 21, 20):
Separate Power Good Indicator Outputs for LTC3865-1 in
QFN package and LTC3865 in FE package. Open-drain logic
output that is pulled to ground when the corresponding
channel output exceeds ±10% regulation window, after
the internal 20µs power bad mask timer expires.
PGND (Pin 18/NA): Power Ground Pin. Connect this pin
closely to the sources of the bottom N-channel MOSFETs,
the (–) terminal of CVCC and the (–) terminal of CIN.
EXTVCC (Pin 20/Pin 28): External Power Input to an Inter-
nal Switch Connected to INTVCC. This switch closes and
supplies the IC power, bypassing the internal low dropout
regulator, whenever EXTVCC is higher than 4.7V. Do not
exceed 6V on this pin.
INTVCC (Pin 21/Pin 29): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7µF low ESR tan-
talum or ceramic capacitor.
VIN (Pin 22/Pin 30): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1µF to 1µF).
BG1, BG2 (Pins 23, 19/Pin 31, 27): Bottom Gate Driver
Outputs. These pins drive the gates of the bottom N-chan-
nel MOSFETs between PGND and INTVCC.
BOOST1, BOOST2 (Pins 24, 17/Pins 33, 25): Boosted
Floating Driver Supplies. The (+) terminal of the booststrap
capacitors connect to these pins. These pins swing from a
diode voltage drop below INTVCC up to VIN + INTVCC.
TG1, TG2 (Pins 25, 16/Pins 34, 23): Top Gate Driver
Outputs. These are the outputs of fl oating drivers with
a voltage swing equal to INTVCC superimposed on the
switch nodes voltages.
SW1, SW2 (Pins 26, 15/Pins 35, 22): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
ground to VIN.
LTC3865/LTC3865-1
10
3865fb
MODE/PLLIN (Pin 27/Pin 36): Force Continuous Mode,
Burst Mode or Pulse-Skip Mode Selection Pin and External
Synchronization Input to Phase Detector Pin. Connect this
pin to SGND to force both channels in continuous mode of
operation. Connect to INTVCC to enable pulse-skip mode of
operation. Leaving the pin fl oating will enable Burst Mode
operation. A clock on the pin will force the controller into
continuous mode of operation and synchronize the internal
oscillator with the clock on this pin.
FREQ (Pin 29/Pin 38): This pin sets the frequency of the
internal oscillator. A constant current of 7.5µA is fl owing
out of this pin and a resistor connected to this pin sets
its DC voltage, which in turn, sets the frequency of the
internal oscillator.
RUN1, RUN2 (Pins 30, 11/Pins 1, 17): Run Control
Inputs. A voltage above 1.22V on either pin turns on the IC.
However, forcing either of these pins below 1.22V causes
the IC to shut down the circuitry required for that particular
channel. There are 1µA pull-up currents for these pins.
Once the RUN pin rises above 1.22V, an additional 4.5µA
pull-up current is added to the pin.
PIN FUNCTIONS
(QFN/TSSOP)
SENSE1+, SENSE2+ (Pins 31, 10/Pins 2, 16): Current
Sense Comparator Inputs. The (+) inputs to the current
comparators are normally connected to DCR sensing
networks or current sensing resistors.
SENSE1–, SENSE2– (Pins 32, 9/Pin 3, 15): Current Sense
Comparator Inputs. The (–) inputs to the current compara-
tors are connected to the outputs.
SGND (Pin 33/Pin 8): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn connects to PGND
at one point. Pin 33 is the Exposed Pad and available for
QFN package.
SGND (Exposed Pad Pin 33/ Exposed Pad Pin 39): Signal
Ground. Must be soldered to PCB, providing a local ground
for the control components of the IC, and be tied to the
PGND pin under the IC.
PGND1, PGND2 (NA/Pins 32, 26): Power Ground Pin.
Connect this pin closely to the sources of the bottom
N-channel MOSFETs, the (–) terminal of CVCC and the (–)
terminal of CIN.
LTC3865/LTC3865-1
11
3865fb
FUNCTIONAL DIAGRAM
4.7V
–
+
–+
–
+
VIN
1µA
SLOPE COMPENSATION
UVLO
SLOPE RECOVERY
ACTIVE CLAMP
OSC S
RQ
3k
RUN
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BG
ON
FCNT
0.6V
OV
1.22V0.5V
ITH RC
INTVCC
INTVCC
ILIM
ICMP
CC1
SS
SGND
0.66V
VFB
RUN
PGND
PGOOD
INTVCC
EXTVCC
IREV
SW
TG CB
VIN
CIN
VIN SLEEP
BOOST
BURSTEN
–
+
–
+
UV
OV
CVCC
VOUT
COUT
M2
M1
L1
DB
MODE/PLLIN
SENSE+
SENSE–
–+
0.6V
REF
TK/SSRUN
0.5V
–+
FREQ/FREQ
7.5µA
PLL-SYNC
AND
LPF
MODE/SYNC
DETECT
+
5V
REG
1.3µA
CSS
+
VOSENSE
–+
–+
F
F
0.54V
VID1 VID2
3865 FBD
1
51k
ITHB
–+
EA
+
INPUT VID LOGIC
AND
RESISTIVE DIVIDERS
LTC3865/LTC3865-1
12
3865fb
OPERATION
Main Control Loop
The LTC3865/LTC3865-1 are constant-frequency, current
mode step-down controllers with two channels operating
180 degrees out-of-phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, ICMP, resets the RS latch. The peak inductor
current at which ICMP resets the RS latch is controlled
by the voltage on the ITH pin, which is the output of each
error amplifi er, EA (refer to the Functional Diagram). VFB
is the voltage feedback signal, which is compared to the
internal reference voltage by the EA. When the load current
increases, it causes a slight decrease in feedback voltage
relative to the 0.6V reference, which in turn causes the
ITH voltage to increase until the average inductor current
matches the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
reverse current comparator IREV, or the beginning of the
next cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5V linear regulator supplies INTVCC
power from VIN. If EXTVCC is taken above 4.7V, the 5V
regulator is turned off and an internal switch is turned
on connecting EXTVCC. Using the EXTVCC pin allows the
INTVCC power to be derived from a high effi ciency external
source such as one of the LTC3865/LTC3865-1 switching
regulator outputs.
Each top MOSFET driver is biased from the fl oating
bootstrap capacitor, CB, which normally recharges during
each off cycle through an external diode when the top
MOSFET turns off. If the input voltage VIN decreases to
a voltage close to VOUT, the loop may enter dropout and
attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one-twelfth of the clock period every third
cycle to allow CB to recharge. However, it is recommended
that a load be present during the drop-out transition to
ensure CB is recharged.
Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The two channels of the LTC3865/LTC3865-1 can be
independently shut down using the RUN1 and RUN2 pins.
Pulling either of these pins below 1.22V shuts down the
main control loop for that controller. Pulling both pins
low disables both controllers and most internal circuits,
including the INTVCC regulator. Releasing either RUN pin
allows an internal 1µA current to pull up the pin and enable
that controller. Alternatively, the RUN pin may be externally
pulled up or driven directly by logic. Be careful not to exceed
the absolute maximum rating of 6V on this pin.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the TK/SS1 and TK/SS2 pins.
When the voltage on the TK/SS pin is less than the 0.6V
internal reference, the LTC3865 regulates the VFB voltage
to the TK/SS pin voltage instead of the 0.6V reference.
This allows the TK/SS pin to be used to program a soft-
start by connecting an external capacitor from the TK/SS
pin to SGND. An internal 1.3µA pull-up current charges
this capacitor, creating a voltage ramp on the TK/SS pin.
As the TK/SS voltage rises linearly from 0V to 0.6V (and
beyond), the output voltage, VOUT
, rises smoothly from
zero to its fi nal value. Alternatively the TK/SS pin can
be used to cause the start-up of VOUT to “track” that of
another supply. Typically, this requires connecting to the
TK/SS pin an external resistor divider from the other sup-
ply to ground (see the Applications Information section).
When the corresponding RUN pin is pulled low to disable
a controller, or when INTVCC drops below its undervoltage
lockout threshold of 3.3V, the TK/SS pin is pulled low by
an internal MOSFET. When in undervoltage lockout, both
controllers are disabled and the external MOSFETs are
held off.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Continuous Conduction)
The LTC3865/LTC3865-1 can be enabled to enter high
effi ciency Burst Mode operation, constant-frequency pulse-
skipping mode, or forced continuous conduction mode. To
select forced continuous operation, tie the MODE/PLLIN
LTC3865/LTC3865-1
13
3865fb
pin to a DC voltage below 0.6V (e.g., SGND). To select
pulse-skipping mode of operation, tie the MODE/PLLIN
pin to INTVCC. To select Burst Mode operation, fl oat the
MODE/PLLIN pin. When a controller is enabled for Burst
Mode operation, the peak current in the inductor is set to
approximately one-third of the maximum sense voltage
even though the voltage on the ITH pin indicates a lower
value. If the average inductor current is higher than the
load current, the error amplifi er EA will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.5V, the
internal sleep signal goes high (enabling “sleep” mode)
and both external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
(IREV) turns off the bottom external MOSFET just before the
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the effi ciency at light
loads is lower than in Burst Mode operation. However,
continuous mode has the advantages of lower output
ripple and less interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTVCC, the
LTC3865 operates in PWM pulse-skipping mode at light
loads. At very light loads, the current comparator, ICMP
,
may remain tripped for several cycles and force the external
top MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
effi ciency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage. The switching
frequency of the LTC3865’s controllers can be selected
using the FREQ pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ pin can be
used to program the controller’s operating frequency from
250kHz to 770kHz.
There is a precision 7.5µA current fl ow out of FREQ pin
that user can program the controller’s switching frequency
with a single resistor to SGND. A curve is provided later in
the application section showing the relationship between
the voltage on the FREQ pin and switching frequency.
A phase-locked loop (PLL) is integrated on the LTC3865
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized.
The PLL loop fi lter network is integrated inside the
LTC3865/LTC3865-1. The phase-locked loop is capable
of locking any frequency within the range of 250kHz to
770kHz. The frequency setting resistor should always be
present to set the controller’s initial switching frequency
before locking to the external clock.
Power Good (PGOOD Pins)
On the LTC3865 (UH32 package), the PGOOD pin is bonded
to the open drains of two individual internal N-channel
MOSFETs. When either VOSENSE voltage is not within ±10%
of the programmed voltage, the PGOOD pin is pulled low.
The PGOOD pin is also pulled low when either RUN pin
is below 1.22V or when the LTC3865 is in the soft-start
or tracking phase. The PGOOD pin will fl ag power good
immediately when both VOSENSE are within the ±10%
of the programmed output voltage window. However,
there is an internal 20µs power bad mask when either
VOSENSE goes out the ±10% window. The internal power
OPERATION
LTC3865/LTC3865-1
14
3865fb
bad mask is 100µs when there are any VID transitions.
On the LTC3865-1 (UH32 package) or the LTC3865 (FE38
package), each channel has its own PGOOD pin. Therefore,
the PGOOD pins now only respond to their own channels.
The PGOOD pins are allowed to be pulled up by external
resistors to sources of up to 6V.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the reverse current limit for the overvoltage
condition is reached. The bottom MOSFET will be turned on
again at the next clock and be turned off when the reverse
current limit is reached again. This process repeats until
the overvoltage condition is cleared.
OPERATION
Output Voltage Programming
The output voltages of both channels of the LTC3865/
LTC3865-1 can be programmed to a preset value. There
are two VID pins for each channel and by connecting these
pins to INTVCC, GND, or by fl oating them, the output volt-
ages can be set to the values in Table 1.
Table 1. Programming of Output Voltage
VID11/VID21 VID12/VID22 VOUT1/VOUT2 (V)
INTVCC INTVCC 5.0
INTVCC Float 3.3
INTVCC GND 2.5
Float INTVCC 1.8
Float Float 0.6 or External Divider
Float GND 1.5
GND INTVCC 1.2
GND Float 1.0
GND GND 1.1
The Typical Application on the fi rst page is a basic LTC3865
application circuit. The LTC3865 can be confi gured to use
either DCR (inductor resistance) sensing or low value resis-
tor sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resis-
tors and is more power effi cient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
external component selection is driven by the load require-
ment, and begins with the selection of RSENSE (if RSENSE is
used) and inductor value. Next, the power MOSFETs are se-
lected. Finally, input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maxi-
mum current limit of the controller. When ILIM is either
grounded, fl oated or tied to INTVCC, the typical value for
the maximum current sense threshold will be 30mV, 50mV
or 75mV, respectively.
APPLICATIONS INFORMATION
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will
allow for the use of very low DCR inductors or sense
resistors, but at the expense of current limit accuracy.
The 50mV setting is a good balance between the two. For
single output dual phase applications, use the 50mV or
75mV setting for optimal current sharing.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5V. Both SENSE pins
are high impedance inputs with small base currents of
less than 1µA. When the SENSE pins ramp up from 0V to
1.4V, the small base currents fl ow out of the SENSE pins.
When the SENSE pins ramp down from 5V to 1.1V, the
small base currents fl ow into the SENSE pins. The high
impedance inputs to the current comparators allow ac-
curate DCR sensing. However, care must be taken not to
fl oat these pins during normal operation.
LTC3865/LTC3865-1
15
3865fb
APPLICATIONS INFORMATION
Filter components mutual to the sense lines should be
placed close to the LTC3865/LTC3865-1, and the sense
lines should run close together to a Kelvin connection
underneath the current sense element (shown in Figure 1).
Sensing current elsewhere can effectively add parasitic
inductance and capacitance to the current sense element,
degrading the information at the sense terminals and mak-
ing the programmed current limit unpredictable. If DCR
sensing is used (Figure 2b), sense resistor R1 should be
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes. The capacitor
C1 should be placed close to the IC pins.
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE
3865 F01
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
the LTC1628 / LTC3728 family) that the voltage drop across
the parasitic inductance of the sense resistor represented
a relatively small error. For today’s highest current density
solutions, however, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be as low
as 20mV. In addition, inductor ripple currents greater than
50% with operation up to 1MHz are becoming more com-
mon. Under these conditions the voltage drop across the
sense resistor’s parasitic inductance is no longer negligible.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. In previous generations of controllers, a small
RC fi lter placed near the IC was commonly used to reduce
the effects of capacitive and inductive noise coupled in
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The input
common mode range of the current comparator is 0V
to 5V. The current comparator threshold sets the peak of
the inductor current, yielding a maximum average output
current IMAX equal to the peak value less half the peak-to-
peak ripple current, ΔIL. To calculate the sense resistor
value, use the equation:
RV
II
SENSE
SENSE MAX
MAX L
=
+
()
()
Δ
2
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of ΔVSENSE = ΔIL • RSENSE
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 15mV ΔVSENSE voltage is recommended
as a conservative number to start with, either for RSENSE
or DCR sensing applications.
VIN VIN
INTVCC
BOOST
TG
SW
BG
PGND
FILTER COMPONENTS
PLACED NEAR SENSE PINS
SENSE+
SENSE–
SGND
LTC3865 VOUT
3865 F02a
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
RSESL
CF
RF
RF
VIN VIN
INTVCC
BOOST
TG
SW
BG
PGND
*PLACE C1 NEAR SENSE+,
SENSE– PINS
INDUCTOR
DCRL
SENSE+
SENSE–
SGND
LTC3865
VOUT
3865 F02b
R1
R2C1*
R1||R2 • C1 = L
DCR RSENSE(EQ) = DCR R2
R1 + R2
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
LTC3865/LTC3865-1
16
3865fb
APPLICATIONS INFORMATION
the sense traces on the PCB. A typical fi lter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
This same RC fi lter, with minor modifi cations, can be used
to extract the resistive component of the current sense
signal in the presence of parasitic inductance. For example,
Figure 3 illustrates the voltage waveform across a 2mΩ
sense resistor with a 2010 footprint for the 1.2V/15A
converter operating at 100% load. The waveform is the
superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
ESL V
I
tt
tt
ESL STEP
L
ON OFF
ON OFF
=Δ+
() •
If the RC time constant is chosen to be close to the parasitic
inductance divided by the sense resistor (L/R), the result-
ing waveform looks resistive again, as shown in Figure 4.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
the equation above to determine the ESL. However, do not
over fi lter. Keep the RC time constant less than or equal
to the inductor time constant to maintain a high enough
ripple voltage on VRSENSE.
The above generally applies to high density/high current
applications where I(MAX) >10A and low values of inductors
are used. For applications where I(MAX) < 10A, set RF to
10 and CF to 1000pF. This will provide a good starting
point.
The fi lter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin connected to the sense
resistor.
Inductor DCR Sensing
For applications requiring the highest possible effi ciency
at high load currents, the LTC3865/LTC3865-1 are capable
of sensing the voltage drop across the inductor DCR, as
shown in Figure 2b. The DCR of the inductor represents
the small amount of DC winding resistance of the copper,
which can be less than 1mΩ for today’s low value, high
current inductors. In a high current application requiring
such an inductor, conduction loss through a sense resis-
tor would cost several points of effi ciency compared to
DCR sensing.
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external fi lter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
500ns/DIV
VSENSE
20mV/DIV
3865 F03
VESL(STEP)
500ns/DIV
VSENSE
20mV/DIV
3865 F04
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor
Figure 4. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω
LTC3865/LTC3865-1
17
3865fb
APPLICATIONS INFORMATION
always the same and varies with temperature; consult the
manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Induc-
tor Value Calculation section, the target sense resistor
value is:
RV
II
SENSE EQUIV
SENSE MAX
MAX L
()
()
()
=
+Δ
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (24mV,
44mV or 68mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coeffi cient of resistance, which is approximately 0.4%/°C.
A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RR
DCR at T
D
SENSE EQUIV
MAX L MAX
=()
() ()
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1||R2 to around 2kΩ, reducing error
that might have been caused by the SENSE pins’ ±1µA
current.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
RR L
DCR at C C
12 20 1
|| ()•
=°
The sense resistor values are:
RRR
RRRR
R
D
D
D
112 21
1
==
−
|| ;•
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PR
VVV
R
LOSS
IN MAX OUT OUT
11
=−
()
() •
Ensure that R1 has a power rating higher than this value.
If high effi ciency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher effi ciency at heavy loads.
Peak effi ciency is about the same with either method.
To maintain a good signal to noise ratio for the current
sense signal, use a minimum ΔVSENSE of 10mV to 15mV.
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
Δ=
−
VVV
RC
V
Vf
SENSE IN OUT OUT
IN OSC
11••
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles >40%. However, the LTC3865/LTC3865-1
use a patented scheme that counteracts this compensating
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
IV
V
VV
fL
RIPPLE OUT
IN
IN OUT
OSC
=⎛
⎝
⎜⎞
⎠
⎟
–
•
LTC3865/LTC3865-1
18
3865fb
APPLICATIONS INFORMATION
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest effi ciency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specifi ed maximum,
the inductor should be chosen according to:
LVV
fI
V
V
IN OUT
OSC RIPPLE
OUT
IN
≥–
••
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fi xed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3865/LTC3865-1: one N-channel
MOSFET for the top (main) switch, and one N-channel
MOSFET for the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(VIN < 5V); then, sub-logic level threshold MOSFETs
(VGS(TH) < 3V) should be used. Pay close attention to the
BVDSS specifi cation for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
fl at divided by the specifi ed change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specifi ed VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle V
V
Synchronous Switc
OUT
IN
=
hh Duty Cycle VV
V
IN OUT
IN
=–
The MOSFET power dissipations at maximum output
current are given by:
PV
VIR
VI
MAIN OUT
IN MAX DS ON
IN MAX
=
()
+
()
+
()
2
2
1δ()
22
11
⎛
⎝
⎜⎞
⎠
⎟
()( )
+
RC
VV V
DR MILLER
INTVCC TH MIN
•
–() TTH MIN OSC
SYNC IN OUT
IN MAX
f
PVV
VI
()
•
–
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
=
())
+
()
21δRDS ON()
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
LTC3865/LTC3865-1
19
3865fb
APPLICATIONS INFORMATION
which are highest at high input voltages. For VIN < 20V
the high current effi ciency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead time
between the conduction of the two power MOSFETs. These
prevent the body diodes of the bottom MOSFETs from turn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
in effi ciency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
Soft-Start and Tracking
The LTC3865/LTC3865-1 have the ability to either soft-start
by themselves with a capacitor or track the output of another
channel or external supply. When one particular channel
is confi gured to soft-start by itself, a capacitor should be
connected to its TK/SS pin. This channel is in the shutdown
state if its RUN pin voltage is below 1.22V. Its TK/SS pin
is actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.22V, the channel pow-
ers up. A soft-start current of 1.3µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defi ned to be the voltage range from 0V to 0.6V on the
TK/SS pin. The total soft-start time can be calculated as:
tC
A
SOFTSTART SS
=06 13
.•.μ
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode
up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.54V. The output ripple
is minimized during the 40mV forced continuous mode
window ensuring a clean PGOOD signal.
When the channel is confi gured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the
ramp rate of the other supply’s voltage. Note that the small
soft-start capacitor charging current is always fl owing,
producing a small offset error. To minimize this error, select
the tracking resistive divider value to be small enough to
make this error negligible.
In order to track down another channel or supply after
the soft-start phase expires, the LTC3865/LTC3865-1 are
forced into continuous mode of operation as soon as VFB
is below the undervoltage threshold of 0.54V regardless of
the setting on the MODE/PLLIN pin. However, the LTC3865/
LTC3865-1 should always be set in forced continuous
mode tracking down when there is no load. After TK/SS
drops below 0.1V, the corresponding channel will operate
in discontinuous mode.
Output Voltage Tracking
The LTC3865/LTC3865-1 allow the user to program how its
output ramps up and down by means of the TK/SS pins.
Through these pins, the output can be set up to either co-
incidentally or ratiometrically track another supply’s output,
as shown in Figure 5. In the following discussions, VOUT1
refers to the LTC3865/LTC3865-1’s output 1 as a master
channel and VOUT2 refers to the LTC3865/LTC3865-1’s out-
put 2 as a slave channel. In practice, though, either phase
can be used as the master. To implement the coincident
tracking in Figure 5a, connect an additional resistive divider
to VOUT1 and connect its midpoint to the TK/SS pin of the
slave channel. The ratio of this divider should be the same
as that of the slave channel’s internal feedback divider
LTC3865/LTC3865-1
20
3865fb
APPLICATIONS INFORMATION
shown in Figure 6a. In this tracking mode, VOUT1 must
be set higher than VOUT2. To implement the ratiometric
tracking, the ratio of the VOUT2 divider should be exactly
the same as the master channel’s internal feedback divider.
By selecting different resistors, the LTC3865/LTC3865-1
can achieve different modes of tracking including the two
in Figure 5.
So which mode should be programmed? The coincident
mode offers better output regulation. This can be better
understood with the help of Figure 7. At the input stage
of the slave channel’s error amplifi er, two common an-
ode diodes are used to clamp the equivalent reference
voltage and an additional diode is used to match the shifted
common mode voltage. The top two current sources are
of the same magnitude. In coincident mode, the TK/SS
voltage is substantially higher than 0.6V at steady state and
effectively turns off D1. D2 and D3 will therefore conduct
the same current and offer tight matching between VFB2
and the internal precision 0.6V at steady state. In the
ratiometric mode, however, TK/SS equals 0.6V at steady
state. D1 will divert part of the bias current to make VFB2
slightly lower than 0.6V. Although this error is minimized
by the exponential I-V characteristics of the diode, it does
impose a fi nite amount of output voltage deviation.
TIME
(5a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME 3865 F05
(5b) Ratiometric Tracking
OUTPUT VOLTAGE
Figure 5. Two Different Modes of Output Voltage Tracking
nR3 R1
nR4 R2
R3
VOUT2
R4
(6a) Coincident Tracking Setup
TO
EA1
TO
TK/SS2
PIN
TO
EA2
VOUT1
38551 F06
(6b) Ratiometric Tracking Setup
nR1 R1
nR2 R2
R3
VOUT2
R4
TO
EA1
TO
TK/SS2
PIN
TO
EA2
VOUT1
Figure 6. Setup for Coincident and Ratiometric Tracking
–
+
D3
3865 F07
D2D1
TK/SS2
0.6V
VFB2
II
EA2
Figure 7. Equivalent Input Circuit of Error Amplifi er
LTC3865/LTC3865-1
21
3865fb
APPLICATIONS INFORMATION
When the master channel’s output experiences dynamic
excursion (under load transient, for example), the slave
channel output will be affected as well. For better output
regulation, use the coincident tracking mode instead of
ratiometric.
INTVCC Regulators and EXTVCC
The LTC3865 features a true PMOS LDO that supplies
power to INTVCC from the VIN supply. INTVCC powers the
gate drivers and much of the LTC3865/LTC3865-1’s internal
circuitry. The linear regulator regulates the voltage at the
INTVCC pin to 5V when VIN is greater than 5.5V. EXTVCC
connects to INTVCC through a P-channel MOSFET and can
supply the needed power when its voltage is higher than
4.7V. Each of these can supply a peak current of 80mA
and must be bypassed to ground with a minimum of 4.7µF
ceramic capacitor or low ESR electrolytic capacitor. No mat-
ter what type of bulk capacitor is used, an additional 0.1µF
ceramic capacitor placed directly adjacent to the INTVCC
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between channels.
High input voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum
junction temperature rating for the LTC3865/LTC3865-1
to be exceeded. The INTVCC current, which is dominated
by the gate charge current, may be supplied by either the
5V linear regulator or EXTVCC. When the voltage on the
EXTVCC pin is less than 4.7V, the linear regulator is enabled.
Power dissipation for the IC in this case is highest and is
equal to VIN • IINTVCC. The gate charge current is depen-
dent on operating frequency as discussed in the Effi ciency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, the LTC3865 INTVCC
current is limited to less than 42mA from a 38V supply in
the UH package and not using the EXTVCC supply:
T
J = 70°C + (42mA)(38V)(34°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
= SGND) at maximum VIN. When the voltage applied to
EXTVCC rises above 4.7V, the INTVCC linear regulator is
turned off and the EXTVCC is connected to the INTVCC.
The EXTVCC remains on as long as the voltage applied to
EXTVCC remains above 4.5V. Using the EXTVCC allows the
MOSFET driver and control power to be derived from one
of the LTC3865/LTC3865-1’s switching regulator outputs
during normal operation and from the INTVCC when the
output is out of regulation (e.g., start-up, short-circuit). If
more current is required through the EXTVCC than is speci-
fi ed, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. Do not apply more than 6V to
the EXTVCC pin and make sure that EXTVCC < VIN.
Signifi cant effi ciency and thermal gains can be realized by
powering INTVCC from the output, since the VIN current
resulting from the driver and control currents will be scaled
by a factor of (Duty Cycle)/(Switcher Effi ciency).
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
T
J = 70°C + (42mA)(5V)(34°C/W) = 77°C
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTVCC power from
the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5V regulator result-
ing in an effi ciency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
effi ciency.
3. EXTVCC connected to an external supply. If a 5V external
supply is available, it may be used to power EXTVCC
providing it is compatible with the MOSFET gate drive
requirements.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, effi ciency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V.
LTC3865/LTC3865-1
22
3865fb
APPLICATIONS INFORMATION
For applications where the main input power is below 5V,
tie the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 8 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET
which is typically 4.5V for logic-level devices.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the Functional Diagram is charged through
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST
= VIN + VINTVCC. The value of the boost capacitor, CB,
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the fi nal arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the effi ciency has
improved. If there is no change in input current, then there
is no change in effi ciency.
Undervoltage Lockout
The LTC3865/LTC3865-1 have two functions that help
protect the controller in case of undervoltage conditions.
A precision UVLO comparator constantly monitors the
INTVCC voltage to ensure that an adequate gate-drive
voltage is present. It locks out the switching action when
INTVCC is below 3.3V. To prevent oscillation when there is
a disturbance on the INTVCC, the UVLO comparator has
550mV of precision hysteresis.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pins have a
precision turn-on reference of 1.22V, one can use a resistor
divider to VIN to turn on the IC when VIN is high enough.
An extra 4.5µA of current fl ows out of the RUN pin once
the RUN pin voltage passes 1.22V. One can program the
hysteresis of the run comparator by adjusting the values
of the resistive divider. For accurate VIN undervoltage
detection, VIN needs to be higher than 4.5V.
CIN and COUT Selection
The selection of CIN is simplifi ed by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phase technique typically reduces the input capacitor’s RMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
INTVCC
LTC3865 RVIN
1Ω
CIN
3865 F08
CINTVCC
4.7µF
5V
+
VIN
Figure 8. Setup for a 5V Input
LTC3865/LTC3865-1
23
3865fb
APPLICATIONS INFORMATION
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
C quired I I
VVVV
IN RMS MAX
IN OUT IN OUT
Re –≈
()( )
⎡
⎣⎤
⎦⎦12/
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monly used for design because even signifi cant deviations
do not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3865, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefi t of the LTC3865/LTC3865-1 2-phase operation
can be calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the dual
controller design. Also, the input protection fuse resistance,
battery resistance, and PC board trace resistance losses
are also reduced due to the reduced peak currents in a
2-phase system. The overall benefi t of a multiphase design
will only be fully realized when the source impedance of the
power supply/battery is included in the effi ciency testing.
The sources of the top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the sources and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip VIN
pin and ground, placed close to the LTC3865/LTC3865-1,
is also suggested. A 2.2Ω to 10Ω resistor placed between
CIN (C1) and the VIN pin provides further isolation between
the two channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfi ed, the capacitance is adequate for fi ltering. The
output ripple (ΔVOUT) is approximated by:
Δ≈ +
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT RIPPLE OUT
1
8
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
The LTC3865/LTC3865-1 output voltages are each set
by the voltages at VID pins. Each of the VID pins can be
fl oated, or INTVCC or grounded, depending on what preset
voltages are needed at the output (Table 1).
If the desired output voltage is not one of the preset
values, select 0.6V and use 1% resistors to divide VOUT
,
as shown in Figure 9. The regulated output voltage is
determined by:
VV
R
R
OUT B
A
=+
⎛
⎝
⎜⎞
⎠
⎟
06 1.•
To improve the frequency response, a feed-forward ca-
pacitor, CFF
, may be used. Great care should be taken to
route the VOSENSE line away from noise sources, such as
the inductor or the SW line.
VOSENSE
VOUT
RB
RA
CFF
1/2 LTC3865
3865 F09
Figure 9. Setting Output Voltage
LTC3865/LTC3865-1
24
3865fb
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
The LTC3865/LTC3865-1 include current foldback to help
limit load current when the output is shorted to ground.
If the output falls below 50% of its nominal output level,
then the maximum sense voltage is progressively lowered
from its maximum programmed value to one-third of the
maximum value. Foldback current limiting is disabled
during the soft-start or tracking up. Under short-circuit
conditions with very low duty cycles, the LTC3865 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time tON(MIN) of the LTC3865/LTC3865-1 (≈ 90ns), the
input voltage and inductor value:
ΔIt V
L
LSC ONMIN IN
() ( )
•=
The resulting short-circuit current is:
IV
RI
SC
SENSE MAX
SENSE LSC
=13 1
2
/–
()
()
Δ
Phase-Locked Loop and Frequency Synchronization
The LTC3865/LTC3865-1 have a phase-locked loop (PLL)
comprised of an internal voltage-controlled oscillator (VCO)
and a phase detector. This allows the turn-on of the top
MOSFET of controller 1 to be locked to the rising edge of an
external clock signal applied to the MODE/PLLIN pin. The
turn-on of controller 2’s top MOSFET is thus 180 degrees
out-of-phase with the external clock. The phase detector
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal fi lter
network. There is a precision 7.5µA of current fl owing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the MODE/PLLIN pin. The internal switch
between FREQ pin and the integrated PLL fi lter network is
on, allowing the fi lter network to be at the same voltage
potential as of FREQ pin. The relationship between the volt-
age on the FREQ pin and the operating frequency is shown
in Figure 10 and specifi ed in the Electrical Characteristic
table. If an external clock is detected on the MODE/PLLIN
pin, the internal switch mentioned above will turn off and
isolate the infl uence of FREQ pin. Note that the LTC3865 can
only be synchronized to an external clock whose frequency
is within range of the LTC3865/LTC3865-1’s internal VCO.
This is guaranteed to be between 250kHz and 770kHz. A
simplifi ed block diagram is shown in Figure 11.
FREQ PIN VOLTAGE (V)
0
FREQUENCY (kHz)
0.5 1 1.5 2
3865 F10
2.5
0
100
300
400
500
900
800
700
200
600 DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC
VCO
2.4V 5V
7.5µA
RSET
3865 F11
FREQ
EXTERNAL
OSCILLATOR
MODE/
PLLIN
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
Figure 11. Phase-Locked Loop Block Diagram
LTC3865/LTC3865-1
25
3865fb
APPLICATIONS INFORMATION
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the fi lter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the fi lter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the fi lter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the fi lter capacitor holds the voltage.
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thres-hold
is 1V. The external clock should not be applied when the
IC is in shutdown.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3865/LTC3865-1 is capable of turning on the
top MOSFET. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that
tV
V
ON MIN OUT
IN
() ()
<f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3865/LTC3865-1 is
approximately 90ns, with reasonably good PCB layout,
minimum 30% inductor current ripple and at least 10mV
to 15mV ripple on the current sense signal. The mini-
mum on-time can be affected by PCB switching noise in
the voltage and current loop. As the peak sense voltage
decreases the minimum on-time gradually increases to
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a signifi cant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3865/LTC3865-1 circuits: 1) IC VIN current,
2) INTVCC regulator current, 3) I2R losses, 4) Topside
MOSFET transition losses.
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typi-
cally results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a cur-
rent out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
LTC3865/LTC3865-1
26
3865fb
APPLICATIONS INFORMATION
Supplying INTVCC power through EXTVCC from an
output-derived source will scale the VIN current re-
quired for the driver and control circuits by a factor
of (Duty Cycle)/(Effi ciency). For example, in a 20V
to 5V application, 10mA of INTVCC current results in
approximately 2.5mA of VIN current. This reduces the
mid-current loss from 10% or more (if the driver was
powered directly from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor.
In continuous mode, the average output current fl ows
through L and RSENSE, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistances of L and RSENSE to obtain
I2R losses. For example, if each RDS(ON) = 10mΩ, RL =
10mΩ, RSENSE = 5mΩ, then the total resistance is
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Effi ciency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at the
switching frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a max-
imum of 20mΩ to 50mΩ of ESR. The LTC3865 2-phase
architecture typically halves this input capacitance require-
ment over competing solutions. Other losses including
Schottky conduction losses during dead time and induc-
tor core losses generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC fi ltered closed loop response test point. The DC step,
rise time and settling at this test point truly refl ects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Typical Application circuit will provide an adequate
starting point for most applications.
LTC3865/LTC3865-1
27
3865fb
APPLICATIONS INFORMATION
The ITH series RC-CC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the fi ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 12. Figure 13 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1 cm of each other with a common drain con-
nection at CIN? Do not attempt to split the input de-
coupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) ter-
minals. The VOSENSE and ITH traces should be as short
as possible. The path formed by the top N-channel
MOSFET, Schottky diode and the CIN capacitor should
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
3. Do the LTC3865 VOSENSE pins connect to the (+) terminals
of COUT? The connections between the VOSENSE pins
and COUT should not be along the high current input
feeds from the input capacitor(s).
4. Are the SENSE+ and SENSE– leads routed together with
minimum PC trace spacing? The fi lter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor or inductor, whichever
is used for current sensing.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve
noise performance substantially.
LTC3865/LTC3865-1
28
3865fb
APPLICATIONS INFORMATION
CB2
CB1
CINTVCC
+
CIN
D1
CERAMIC
M1 M2
M3 M4 D2
+
CVIN
VIN
RIN
L1
L2
COUT1
VOUT1
GND
VOUT2
3865 F12
+
COUT2
+
RSENSE
RSENSE
RPU2
PGOOD
VPULL-UP
fIN
CERAMIC
ITH1
VOSENSE1
SENSE1+
SENSE1–
FREQ
SENSE2–
SENSE2+
VOSENSE2
ITH2
TK/SS2
TK/SS1
PGOOD
SW1
BOOST1
BG1
VIN
PGND
EXTVCC
INTVCC
BG2
BOOST2
SW2
TG2
SGND
ILIM
MODE/PLLIN
RUN1
RUN2
VID11
LTC3865
VID22
TG1
VID21
VID12
Figure 12. Recommended Printed Circuit Layout Diagram
LTC3865/LTC3865-1
29
3865fb
RL1
D1
L1
SW1 RSENSE1 VOUT1
COUT1
VIN
CIN
RIN
RL2
D2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L2
SW2
3865 F13
RSENSE2 VOUT2
COUT2
Figure 13. Branch Current Waveforms
APPLICATIONS INFORMATION
LTC3865/LTC3865-1
30
3865fb
APPLICATIONS INFORMATION
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feed-
back pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3865/LTC3865-1 and occupy
minimum PC trace area. If DCR sensing is used, place
the top resistor (Figure 2b, R1) close to the switching
node.
7. Use a modifi ed “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 10% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB
implementation. Variation in the duty cycle at a
subharmonic rate can suggest noise pickup at the current
or voltage sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is
not required. Only after each controller is checked for
its individual performance should both controllers be
turned on at the same time. A particularly diffi cult region
of operation is when one controller channel is nearing its
current comparator trip point when the other channel is
turning on its top MOSFET. This occurs around 50% duty
cycle on either channel due to the phasing of the internal
clocks and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN , Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
LTC3865/LTC3865-1
31
3865fb
APPLICATIONS INFORMATION
D3 D4
M1
0.1µF
L1
3.3µH
3.65k
1%
1800pF
100pF
0.1µF 0.1µF
22µF
50V
COUT1
100µF
s2
L1, L2: COILTRONICS HCP0703
M1, M2: VISHAY SILICONIX Si4816BDY
COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM
4.75k
1%
VOUT1
3.3V
5A
M2
0.1µF L2
2.2µH
1.58k
1%
2200pF
100pF
COUT2
100µF
s2
5.49k
1%
162k
1%
VOUT2
1.8V
5A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
VID21
SENSE1–SENSE2–
VOSENSE1 VOSENSE2
ITH1 ITH2
VIN PGOOD INTVCC
TK/SS1 TK/SS2
VIN
7V TO 20V
3865 F14
EXTVCC
0.1µF 0.1µF
LTC3865
MODE/PLLIN
ILIM
RUN2RUN1
VID22
VID12
VID11
5.49k
1%
1.37k
1%
4.7µF
1µF
2.2Ω
+
Figure 14. High Effi ciency Dual 500kHz 3.3V/1.8V Step-Down Converter
Design Example
As a design example for a 2-channel medium current
regulator, assume VIN = 12V (nominal), VIN = 20V
(maximum), VOUT1 = 3.3V, VOUT2 = 1.8V, IMAX1,2 = 5A, and
f = 500kHz (see Figure 14).
The regulated output voltages are set by connecting VID11
and VID22 to INTVCC and fl oating VID12 and VID21.
The frequency is set by biasing the FREQ pin to 1.2V (see
Figure 9).
The inductance values are based on a 35% maximum
ripple current assumption (1.75A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
LV
I
V
V
OUT
LMAX
OUT
IN MAX
=−
⎛
⎝
⎜⎞
⎠
⎟
f•() ()
Δ1
Channel 1 will require 3.2µH, and Channel 2 will require
1.9µH. The next highest standard values are 3.3µH
and 2.2µH. At the nominal input voltage (12V), the ripple
will be:
ΔIV
L
V
V
L NOM OUT OUT
IN NOM
() ()
•
=−
⎛
⎝
⎜⎞
⎠
⎟
f1
Channel 1 will have 1.45A (29%) ripple, and Channel 2 will
have 1.4A (28%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current,
or 5.725A for Channel 1 and 5.7A for Channel 2.
The minimum on-time occurs on Channel 1 at the maximum
VIN, and should not be less than 90ns:
tV
V
V
VkHz n
ON MIN OUT
IN MAX
() ()
.
()
== =
f
18
20 500 180ss
LTC3865/LTC3865-1
32
3865fb
APPLICATIONS INFORMATION
With ILIM fl oating, the equivalent RSENSE resistor value
can be calculated by using the minimum value for the
maximum current sense threshold (44mV).
RV
II
SENSE EQUIV
SENSE MIN
LOAD MAX
L NOM
()
()
()
(
=
+Δ))
..
2
44
515
2
77=
+
≅
mV
AAmΩ
The equivalent RSENSE is the same for Channel 2.
The Coiltronics (Cooper) HCP0703-2R2 (20m DCRMAX
at 20°C) and HCP0703-3R3 (30mΩ DCRMAX at 20°C) are
chosen. At 100°C, the estimated maximum DCR values are
26.4mΩ and 39.6mΩ. The divider ratios are:
RR
DCR at T
m
m
D
SENSE EQUIV
MAX L MAX
==
()
()
.
.
77
26 4
Ω
Ω==
≅
03
77
39 6 02
.;
.
..and m
m
Ω
Ω
For each channel, 0.1µF is selected for C1.
RR L
DCR at C C
H
mF
MAX
12 20 1
22
20 0 1
1
|| ()•
.
•.
=°=
=
μ
μΩ
.. ; .
•. .1 33
30 0 1 11kand H
mF
k
μ
μΩ =
For channel 1, the DCRSENSE fi lter/divider values are:
RRR
R
kk
RRR
R
k
D
D
D
11211
02 55
21
1
55
==≅
=−=
|| .
..;
•.•
002
102 137
.
..
−≅k
The power loss in R1 at the maximum input voltage is:
PRVVV
R
VV
LOSS
IN MAX OUT OUT
11
20 3 3 3
=−
=−
()•
(.)•
()
..
.
3
55 10
V
kmW=
The respective values for Channel 2 are R1 = 3.66k,
R2 = 1.57k; and PLOSS R1 = 8mW.
Burst Mode operation is chosen for high light load effi ciency
(Figure 15) by fl oating the MODE/PLLIN pin. Power loss
due to the DCR sensing network is slightly higher at light
loads than would have been the case with a suitable sense
resistor (8mΩ). At heavier loads, DCR sensing provides
higher effi ciency.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Siliconix Si4816BDY dual MOSFET
results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER ≅ 100pF.
At maximum input voltage with T(estimated) = 50°C:
PV
VCC
MAIN =
()
+°°
[]
33
20 5 1 0 005 50 25
00
2
.(. )( – )•
.223 20 5
22 100
1
523
1
2
2
Ω
()
+
()
⎛
⎝
⎜⎞
⎠
⎟Ω
()( )
+
VApF •
–. .. 3 500 186
⎡
⎣
⎢⎤
⎦
⎥
()
=kHz mW
LOAD CURRENT (mA)
0.01
70
EFFICIENCY (%)
POWER LOSS (mW)
80
90
0.1 1 10
60
50
40
100
0.1
1
0.01
10
3865 F16
DCR
8m
POWER LOSS
EFFICIENCY
Figure 15. Design Example Effi ciency vs Load
LTC3865/LTC3865-1
33
3865fb
APPLICATIONS INFORMATION
A short-circuit to ground will result in a folded back cur-
rent of:
ImV ns V
H
SC =
()
Ωμ
⎛
⎝
⎜⎞
⎠
⎟=
1350
0008
1
2
90 20
33
/
.–()
.11 8.A
with a typical value of RDS(ON) and δ = (0.005/°C)(20)
= 0.1. The resulting power dissipated in the bottom
MOSFET is:
PVV
VA
m
SYNC =
()( )
Ω
()
=
20 3 3
20 181 125 0 016
48
2
–. ...
WW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 2A at
temperature assuming only channel 1 or 2 is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE = RESR (ΔIL) = 0.02Ω(1.5A) = 30mVP-P
0.1µF
L2
0.47µH
Q1
RJK0305DPB
Q3
RJK0305DPB
Q4
RJK0330DPB D2
Q2
RJK0330DPB
1000pF
1000pF 1000pF
22µF
50V
10k
VOUT1
1.5V
15A
0.1µF L2
0.47µH
1000pF
COUT4
100µF
15k
162k
1%
VOUT2
1.2V
15A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
RUN2
SENSE1–SENSE2–
VOSENSE1 VOSENSE2
ITH1 ITH2
VIN PGOOD INTVCC
TK/SS1 TK/SS2
VIN
4.5V TO 24V
3865 F16
0.1µF
100pF 0.1µF
LTC3865
10µF
35V
10µF
35V
MODE/PLLIN
ILIM
RUN1
VID11
VID12
VID21
VID22
EXTVCC
4.7µF
COUT1
100µF
COUT2,3
100pF
100Ω
100Ω
100Ω
100Ω
2.2Ω
1µF
D4D3
D1, D2: VISHAY B340A
L1, L2: VISHAY IHLP4040DZERR47M11
COUT1, COUT4: TDK C322JX5R0J107MT
COUT2, COUT3, COUT5, COUT6: SANYO 4TPE 220µF
2mΩ 2mΩ
+
COUT5,6
+
+
D1
Figure 16. 1.5V/15A, 1.2V/15A Converter Using Sense Resistors
TYPICAL APPLICATIONS
LTC3865/LTC3865-1
34
3865fb
TYPICAL APPLICATIONS
Figure 17. High Current, Single Output, 1.2V/30A Converter Using Sense Resistors
D3 D4
0.1µF
RJK0305DPB
RJK0330DPB RJK0330DPB
L1
0.47µH
6800pF
100pF
0.1µF 0.1µF
162k
RUN1 RUN2
0
22µF
50V
COUT1
220µF
COUT1, COUT2: SANYO 4TPE 220µF
L1, L2: VISHAY IHLP4040DZERR47M11
100
100
1.21k
1%
2m
0.1µF L2
0.47µH
COUT2
220µF
1.2V
30A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
VID21
SENSE1–SENSE2–
VOSENSE1 VOSENSE2
ITH1 ITH2
VIN PGOOD INTVCC
TK/SS1 TK/SS2
VIN
7V TO 20V
3865 F17a
EXTVCC
0.1µF
LTC3865
MODE/PLLIN
ILIM
RUN2RUN1
VID22
VID12
VID11
2m
100
100
4.7µF
1µF
2.2Ω
++
+
RJK0305DPB
10µF
35V
10µF
35V
Effi ciency vs Load Current Load Step (Forced Continuous Mode)
LOAD CURRENT (A)
0
40
EFFICIENCY (%)
50
60
70
80
1 10 100
3865 F17b
30
20
10
0
90
100 VIN = 12V
Burst Mode
OPERATION
FORCED CONTINUOUS
MODE
PULSE-SKIPPING
MODE
40µs/DIVVIN = 12V
VOUT = 1.2V
VOUT
200mV/DIV
AC-COUPLED
IL
5A/DIV
ILOAD
0A TO 20A/DIV
3865 F17c
LTC3865/LTC3865-1
35
3865fb
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 p 0.10
3.45 p 0.10
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 p0.05
3.50 REF
(4 SIDES)
4.10 p0.05
5.50 p0.05
0.25 p 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45o CHAMFER
R = 0.05
TYP
3.45 p 0.05
3.45 p 0.05
LTC3865/LTC3865-1
36
3865fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev A)
Exposed Pad Variation AA
4.75
(.187) REF
FE38 (AA) TSSOP 0608 REV A
0.09 – 0.20
(.0035 – .0079)
0o – 8o
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3865/LTC3865-1
37
3865fb
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/10 Updated Temperature Range in Order Information Section
Updated Electrical Characteristics Table and Note 2
Updated Graph G08
Added Two Graphs to Typical Application
Updated Related Parts
2
4, 5
7
34
38
B 08/10 Added (Note 9) notation to Absolute Maximum Ratings section
Added (Note 8) notation to Electrical Characteristics section
Added Condition to IFREQ in Electrical Characteristics section
Added Note 9
Changed 1.2V to 1.22V throughout data sheet
2
4
5
5
10, 11, 12, 13,
19, 22
LTC3865/LTC3865-1
38
3865fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0810 REV B • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3850/LTC3850-1
LTC3850-2
Dual 2-Phase, High Effi ciency Synchronous Step-Down DC/DC
Controllers, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed 250kHz to 780kHz Frequency,
4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
LTC3855 Dual, Multiphase Synchronous Step-Down DC/DC Controller
with Diffamp and DCR Temperature Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, tON(MIN) = 90ns
LTC3860 Dual, Multiphase Synchronous Step-Down DC/DC Controller
with Diffamp and Three-State Output Drive
Operates with Power Blocks, DRMOS Devices or External
MOSFETs, 3V ≤ VIN ≤ 24V, tON(MIN) = 20ns
LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC
Controller, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed 250kHz to 750kHz Frequency,
4V ≤ VIN ≤ 24V, VOUT3 Up to 13.5V
LTC3854 Small Footprint Wide VIN Range Synchronous Step-Down
DC/DC Controller, RSENSE or DCR Current Sensing
Fixed 400kHz Operating Frequency 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12, MSOP-12
LTC3878/LTC3879 No RSENSE Constant On-Time Synchronous Step-Down
DC/DC Controller, No RSENSE Required
Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16, MSOP-16E, 3mm × 3mm QFN-16
LTC3775 High Frequency, Synchronous Voltage Mode Step-Down
DC/DC Controller
Fast Transient Response, tON(MIN) = 30ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 0.8VIN, MSOP-16E, 3mm × 3mm QFN-16
Figure 18. High VIN, 3.6V/10A, 2V/10A Converter With External Sense Resistors Synchronized at 400kHz
TYPICAL APPLICATION
D3
CMDSH-3
D4
CMDSH-3
0.1µF
HAT2266H
HAT2266H
L1
2.2µH
PLLIN
400kHz
0.004
HAT2266H
HAT2266H
1800pF
100pF
1nF 1nF
CIN1
22µF
50V
COUT1
220µF
s2
COUT1, COUT2: SANYO 4TPE 220µF
L1: TOKO FDA1055-2R2M
L2: TOKO FD1055-1R2M
49.9k
1%
100
100
17.8k
1%
10k
1%
VOUT1
3.6V
10A
0.1µF L2
1.2µH 0.004
2200pF
100pF
COUT2
220µF
s2
14.7k
1%
10k
1%
VOUT2
2V
10A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
VID21
SENSE1–SENSE2–
VOSENSE1 VOSENSE2
ITH1 ITH2
VIN PGOOD INTVCC
TK/SS1 TK/SS2
VIN
7V TO 36V
3865 F18
EXTVCC
0.1µF 0.1µF 121k
LTC3865
3.3µF
50V
3.3µF
50V
MODE/PLLIN
ILIM
RUN2RUN1
VID22
VID12
VID11
100
100
23.2k
1%
4.7µF
CIN2
1µF
2.2Ω
++
+
