208032-04
Jan 2018
Numonyx® Embedded Flash Memory (J3 65
nm) Single Bit per Cell (SBC)
32, 64, and 128 Mbit
Datasheet
Product Feature s
Architecture
Symmetrical 128-KB blocks
128 Mbit (128 blocks)
64 Mbit (64 blocks)
32 Mbit (32 blocks)
Blank Check to verify an erased block
Performance
Initial Access Speed: 75ns
25 ns 8-word Asynchronous page-mode
reads
256-Word write buffer for x16 mode, 256-
Byte write buffer for x8 mode;
1.41 µs per Byte Effective programming
time
System Voltage
—V
CC = 2.7 V to 3.6 V
—V
CCQ = 2.7 V to 3.6 V
Packaging
56-Lead TSOP
64-Ball Easy BGA package
Security
Enhanced security options for code
protection
Absolute protection with VPEN = Vss
Individual block locking
Block erase/program lockout during power
transitions
Password Access feature
One-Time Programmable Register:
64 OTP bits, programmed with unique
information by Numonyx
64 OTP bits, available for customer
programming
Software
Program and erase suspend support
—Numonyx
® Flash Data Integrator (FDI)
Common Flash Interface (CFI) Compatible
Scalable Command Set
Quality and Reliability
Operating temperature:
-40 °C to +85 °C
100K Minimum erase cycles per block
65 nm Flash Technology
JESD47E Compliant
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Datasheet
2
Legal Lines and Discla ime rs8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set
forth herein.
Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
Datasheet
3
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Contents
1.0 Introduction.............................................................................................................. 6
1.1 Nomenclature ..................................................................................................... 6
1.2 Acronyms........................................................................................................... 7
1.3 Conventions ....................................................................................................... 7
2.0 Functional Overview.................................................................................................. 9
2.1 Block Diagram .................................................................................................. 11
2.2 Memory Map..................................................................................................... 12
3.0 P ackage Inf ormation............................................................................................... 13
3.1 56-Lead TSOP Package for 32-, 64-, 128-Mbit ....................................................... 13
3.2 64-Ball Easy BGA Package for 32-, 64-, 128-Mbit .................................................. 14
4.0 Ballouts/Pinouts and Signal Descript io ns ................................................................ 16
4.1 Easy BGA Ballout for 32-, 64-, 128-Mbit ............................................................... 16
4.2 56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit .............................................. 17
4.3 Signal Descriptions ............................................................................................ 18
5.0 Maximum Ratings and Operating Cond itions............................................................ 19
5.1 Absolute Maximum Ratings................................................................................. 19
5.2 Operating Conditions ......................................................................................... 19
5.3 Power-Up/Down ................................................................................................ 19
5.3.1 Power-Up/Down Sequence....................................................................... 19
5.3.2 Power Supply Decoupling ........................................................................ 20
5.4 Reset............................................................................................................... 20
6.0 Electrical Characteristics ......................................................................................... 21
6.1 DC Current Specifications ................................................................................... 21
6.2 DC Voltage specifications.................................................................................... 22
6.3 Capacitance...................................................................................................... 22
7.0 AC Characteris ti c s ................................................................................................... 23
7.1 Read Specifications............................................................................................ 24
7.2 Program, Erase, Block-Lock Specifications ............................................................ 28
7.3 Reset Specifications........................................................................................... 28
7.4 AC Test Conditions ............................................................................................ 29
8.0 Bu s I nterfa c e........................................................................................................... 30
8.1 Bus Reads ........................................................................................................ 31
8.1.1 Asynchronous Page Mode Read ................................................................ 31
8.1.2 Output Disable....................................................................................... 32
8.2 Bus Writes........................................................................................................ 32
8.3 Standby ........................................................................................................... 33
8.3.1 Reset/Power-Down ................................................................................. 33
8.4 Device Commands............................................................................................. 33
9.0 Flash Operations ..................................................................................................... 34
9.1 Status Register ................................................................................................. 34
9.1.1 Clearing the Status Register .................................................................... 35
9.2 Read Operations ............................................................................................... 35
9.2.1 Read Array ............................................................................................ 35
9.2.2 Read Status Register .............................................................................. 36
9.2.3 Read Device Information ......................................................................... 36
9.2.4 CFI Query ............................................................................................. 36
9.3 Programming Operations.................................................................................... 36
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
4
9.3.1 Single-Word/Byte Programming................................................................36
9.3.2 Buffered Programming ............................................................................37
9.4 Block Erase Operations .......................................................................................38
9.5 Blank Check......................................................................................................39
9.6 Suspend and Resume.........................................................................................39
9.7 Status Signal ....................................................................................................41
9.8 Security and Protection.......................................................................................42
9.8.1 Normal Block Locking ..............................................................................42
9.8.2 Configurable Block Locking.......................................................................43
9.8.3 Password Access.....................................................................................43
9.8.4 128-bit OTP Protection Register ................................................................43
9.8.5 Reading the 128-bit OTP Protection Register...............................................43
9.8.6 Programming the 128-bit OTP Protection Register .......................................43
9.8.7 Locking the 128-bit OTP Protection Register ...............................................44
9.8.8 VPEN Protection......................................................................................45
10.0 ID Codes..................................................................................................................46
11.0 Device Command Codes ...........................................................................................47
12.0 Flow Charts..............................................................................................................48
13.0 Common Flash Interface ..........................................................................................57
13.1 Query Structure Output ......................................................................................57
13.2 Query Structure Overview...................................................................................58
13.3 Block Status Register .........................................................................................59
13.4 CFI Query Identification String ............................................................................59
13.5 System Interface Information..............................................................................60
13.6 Device Geometry Definition .................................................................................60
13.7 Primary-Vendor Specific Extended Query Table ......................................................61
A Additional Inform a tion.............................................................................................64
B Ordering Information...............................................................................................65
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Revision History
Date Revision Description
May 2009 01 Initial release
March 2010 02
Add Blank Check function and command.
Add Blank Check specification tBC/MB, update Clear Block Lock-Bits Max Time and Program
time in Table 13, “Configuration Performance” on page 28.
Update ICCR in Table 7, “DC Current Characteristics” on page 21.
Order information with device features digit.
Update part number information in Valid Combination table.
Add a note to clarify the SR output after E8 command in Figure 16, “Write to Buffer Flowchart” on
page 48.
State JESD47E Compliant at front page.
Update ECR.13 description in Table 18, “Enhanced Configuration Register” on page 32.
Jan 2011 03
Correct the typo of comment for offset 24h at CFI from 2048µs to 1024µs.
Correct the typo of tAVQV and tELQV to Max Specifications.
Emphasize the valid and legal command usage at Section 11.0, “Device Command Codes” on
page 47.
Put a link for part numbers after Table 46, “Valid Combinations” on page 65.
Add Buffer Program Time for 128 Words (256 Bytes) at Table 13, “Configuration Performance” on
page 28.
Add JEDEC standard lead width for TSOP56 package at Table 1, “56-Lead TSOP Dimension Table” on
page 13.
Jan 2018 04 Added Important Notes and Warnings section for further clarification aligning to industry
standards
Datasheet
5
Important Notes and Warnings
Important Notes and Warnings
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document, including without limitation specifications and product descriptions. This document
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are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written
agreement executed by Micron's duly authorized representative.
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
6
1.0 Introduction
This document contains information pertaining to the Numonyx® Embedded Flash
Memory (J3 65 nm) Single Bit per Cell (SBC) device features, operation, and
specifications.
Unless otherwise indicated throughout the rest of this document, the Numonyx®
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) device is referred to as
J3 65 nm SBC.
The J3 65 nm SBC device provides improved mainstream performance with enhanced
security features, taking advantage of the high quality and reliability of the NOR-based
65 nm technology. Offered in 128-Mbit, 64-Mbit, and 32-Mbit densities, the J3 65 nm
SBC device brings reliable, low-voltage capability (3 V read, program, and erase) with
high speed, low-power operation. The J3 65 nm SBC device takes advantage of proven
manufacturing experience and is ideal for code and data applications where high
density and low cost are required, such as in networking, telecommunications, digital
set top boxes, audio recording, and digital imaging. Numonyx Flash Memory
components also deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers
can take advantage of density upgrades and optimized write capabilities of future
Numonyx Flash Memory devices.
1.1 Nomenclature
J3 65 nm SBC Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
AMIN All Densities AMIN = A0 for x8
All Densities AMIN = A1 for x16
AMAX
32 Mbit AMAX = A21
64 Mbit AMAX = A22
128 Mbit AMAX = A23
Block A group of flash cells that share common erase circuitry and erase simultaneously.
Clear Indicates a logic zero (0)
Program Writes data to the flash array
Set Indicates a logic one (1)
VPEN Refers to a signal or package connection name
VPEN Refers to timing or voltage levels
Datasheet
7
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
1.2 Acronyms
1.3 Conventions
hHexadecimal Suffix
K(noun) 1,000
M (noun) 1,000,000
Nibble 4 bits
Byte 8 bits
Word 16 bits
Kb 1,024 bits
KB 1,024 bytes
KW 1,024 words
Mb 1,048,576 bits
MB 1,048,576 bytes
MW 1,048,576 words
Kbit 1,024 bits
Mbit 1,048,576 bits
SBC Single Bit per Cell
FDI Flash Data Integrator
CFI Common Flash Interface
SCS Scalable Command Set
CUI Command User Interface
OTP One Time Programmable
PLR Protection Lock Register
PR Protection Register
PRD Protection Register Data
RFU Reserved for Future Use
SR Status Register
SRD Status Register Data
WSM Write State Machine
ECR Enhanced Configuration Register
ECD Enhanced Configuration Register Data
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
8
Brackets Square brackets ([]) will be used to designate group membership or to
define a group of signals with similar function (i.e. A[21:1], SR[4,1]
and D[15:0]).
00FFh Denotes 16-bit hexadecimal numbers
00FF 00FFh Denotes 32-bit hexadecimal numbers
DQ[15:0] Data I/O signals
Datasheet
9
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
2.0 Functional Overview
The J3 65 nm SBC family contains high-density memory organized in any of the
following configurations:
16-MB or 8-MW (128-Mbit), organized as one-hundred-twenty-eight 128-KB erase
blocks.
8-MB or 4-MW (64-Mbit), organized as sixty-four 128-KB erase blocks.
4-MB or 2-MW (32-Mbit), organized as thirty-two 128-KB erase blocks.
These devices can be accessed as 8- or 16-bit words. See Figure 1, “Memory Block
Diagram for 32-, 64-, 128-Mbit” on page 11 for further details.
A 128-bit Protection Register has multiple uses, including unique flash device
identification.
The J3 65 nm SBC device includes new security features that were not available on the
(previous) 0.13µm versions of the J3 family. These new security features prevent
altering of code through different protection schemes that can be implemented, based
on user requirements.
The J3 65 nm SBC optimized architecture and interface dramatically increases read
performance by supporting page-mode reads. This read mode is ideal for non-clock
memory systems.
Its Common Flash Interface (CFI) permits software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and
forward- and backward-compatible software support for the specified flash device
families. Flash vendors can standardize their existing interfaces for long-term
compatibility.
The Scalable Command Set (SCS) allows a single, simple software driver in all host
systems to work with all SCS-compliant flash memory devices, independent of system-
level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally,
SCS provides the highest system/device data transfer rates and minimizes device and
system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence written to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s 128-KB blocks typically within one
second, independent of other blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software to suspend block erase to
read or program data from any other block. Similarly, program suspend allows system
software to suspend programming (byte/word program and write-to-buffer operations)
to read data or execute code from any other block that is not being suspended.
Each device incorporates a Write Buffer of 256-Byte (x8 mode) or 256-Word (x16
mode) to allow optimum programming performance. By using the Write Buffer data is
programmed more efficiently in buffer increments.
Memory Blocks are selectively and individually lockable in-system. Individual block
locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase
and program operations. Lock-bit configuration operations set and clear lock-bits (using
the Set Block Lock-Bit and Clear Block Lock-Bits commands).
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
10
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation completes.
The STS (status) output gives an additional indicator of WSM activity by providing both
a hardware signal of status (versus software polling) and status masking (interrupt
masking for background block erase, for example). Status indication using STS
minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design
(see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-Mb” on page 30) reduces
decoder logic typically required for multi-chip designs. External logic is not required
when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
byte.
BYTE#-high enables16-bit operation; address A1 becomes the lowest order
address and address A0 is not used (don’t care).
Figure 1, “Memory Block Diagram for 32-, 64-, 128-Mbit” on page 11 shows a device
block diagram.
When the device is disabled (see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-
Mb” on page 30), with CEx at VIH and RP# at VIH, the standby mode is enabled. When
RP# is at VIL, a further power-down mode is enabled which minimizes power
consumption and provides write protection during reset. A reset time (tPHQV) is
required from RP# going high until data outputs are valid. Likewise, the device has a
wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at
VIL, the WSM is reset and the Status Register is cleared.
Datasheet
11
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
2.1 Block Diagram
Figur e 1: Memory Block Di agram for 32-, 64-, 128-Mbit
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
12
2.2 Memory Map
Figure 2: J3 65 nm SBC Memory Map
Byte-Wide (x 8 ) Mode
128 KB Block
128 KB Block
0
1
-
-
128 KB Block
31
-
128 KB Block
63
-
128 KB Block
127
-
32- Mbit
64- Mbit
128- Mbit
A [23:0]:128 Mbi t
A [22:0]: 64Mbit
A [21:0]: 32Mbit
Word-Wide (x16) Mode
64 KW B lock
64 KW B lock
0
1
-
-
64 KW B lock
31
-
64 KW B lock
63
-
64 KW B lock
127
-
32- Mbit
64- Mbit
128- Mbit
A [23:1]:128 Mbit
A [22:1]: 64Mbit
A [21:1]: 32Mbit
F
0
F
0
F
00EF FFFh
h
FFFFF7h
0000E7h
FFFFF3h
0000E3h
FFFF30h
000020h
FFFF10h
000000h
F
0
F
0
F
00F7 FF7h
h
FFFFF3h
0000F3h
FFFFF1h
0000F1h
FFFF10h
000010h
FFFF00h
000000h
Datasheet
13
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
3.0 Package Information
3.1 56-Lead TSOP Package for 32-, 64-, 128-Mbit
Notes:
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Figure 3: 56-Lead TSOP Package Mechanical
A
0
L
Detail A
Y
D
C
Z
Pin 1
E
D1
b
Detail B
See Detail A
e
See Detail B
A1
Seating
Plane
A2
See Note 2
See Notes 1 and 3
Tabl e 1: 56-Lead TSOP Dimension Table
Parameter Symbol Millimeters Inches
Min Nom Max Min Nom Max
Package Height A 1.200 0.047
Standoff A10.050 0.002
Package Body Thickness A20.965 0.995 1.025 0.038 0.039 0.040
Lead Width1b 0.170 0.220 0.270 0.0067 0.0087 0.0106
Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008
Package Body Length D118.200 18.400 18.600 0.717 0.724 0.732
Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559
Lead Pitch e 0.500 0.0197
Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795
Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
14
3.2 6 4-Ball Easy BGA Package for 32-, 64-, 128-Mbit
Lead Count N 56 56
Lead Tip Angle θ
Seating Plane Coplanarity Y 0.100 0.004
Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014
1. For legacy lead width, 0.15mm (Typ), 0.10mm (Min), 0.20mm (Max).
Table 1: 56-Lead TSOP Dimension Table
Parameter Symbol Millimeters Inches
Min Nom Max Min Nom Max
Figure 4: 64-Ball Easy BGA Mechanical Specifications
2
Ball A1
Corner
8765432112345678
E
A
B
C
D
E
F
G
H
Seating
Plane
S1
S
e
b
Top View - Plastic Backside
Complete Ink Mark Not Shown Bottom View - Ball Side Up
Y
A
A1
D
A
B
C
D
E
F
G
H
Ball A1
Corner
A2
Table 2: Easy BGA Package Dimensions Table (Sheet 1 of 2)
Parameter Symbol Millimeters Inches
Min Nom Max Min Nom Max
Package Height A 1.200 0.0472
Ball Height A1 0.250 0.0098
Package Body Thickness A2 0.780 0.0307
Ball (Lead) Width b 0.310 0.410 0.510 0.012 0.016 0.020
Datasheet
15
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body Length E 12.900 13.000 13.100 0.5079 0.5118 0.5157
Pitch e 1.000 0.0394
Ball (Lead) Count N 64 64
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630
Corner to Ball A1 Distance Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220
Tabl e 2: Easy BGA Package Dimens ions Table (Sheet 2 of 2)
Parameter Symbol Millimeters Inches
Min Nom Max Min Nom Max
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
16
4.0 Ballouts/Pinouts and Signal De scriptions
J3 65 nm SBC is available in two package types. All densities of the J3 65 nm SBC
devices are supported on both 64-ball Easy BGA and 56-lead Thin Small Outline
Package (TSOP) packages. The figures below show the ballouts/Pinouts.
4.1 Easy BGA Ballout for 32-, 64-, 128-Mbit
Notes:
1. A0 is the least significant address bit.
2. A22 is valid for 64-Mbit density and above. On 32-Mbit, it is a no-connect (NC).
3. A23 is valid for 128-Mbit density. On 32- and 64-Mbit, it is a no-connect (NC).
4. A24 is a no connect (NC) on 128-, 64-, 32- Mbit, reserved for 256-Mbit.
Figure 5: Easy BGA Ballout (32/64/128 Mbit)
A1 A6 A8 VPEN A13 VCC A18 A22
A2 VSS A9 CE0 A14 RFU A19 CE1
A3 A7 A10 A12 A15 RFU A20 A21
A4 A5 A11 RP# RFU RFU A16 A17
DQ8 DQ1 DQ9 DQ3 DQ4 RFU DQ15 STS
BYTE# DQ0 DQ10 DQ11 DQ12 RFU RFU OE#
A23 A0 DQ2 VCCQ DQ5 DQ6 DQ14 WE#
CE2 RFU VCC VSS DQ13 VSS DQ7 A24
12345678
A
B
C
D
E
F
G
H
Easy BGA
Top View – Ba ll Si de Down
A22
CE1
A21
A17
STS
OE#
WE#
A24
8
A18
A19
A20
A16
DQ15
RFU
DQ14
DQ7
7
VCC
RFU
RFU
RFU
RFU
RFU
DQ6
VSS
6
A13
A14
A15
RFU
DQ4
DQ12
DQ5
DQ13
5
VPEN
CE0
A12
RP#
DQ3
DQ11
VCCQ
VSS
4
A8
A9
A10
A11
DQ9
DQ10
DQ2
VCC
3
A6
VSS
A7
A5
DQ1
DQ0
A0
RFU
2
A1
A2
A3
A4
DQ8
BYTE#
A23
CE2
1
A
B
C
D
E
F
G
H
Easy BGA
Bo tto m View – Ball Side Up
(1)
(3)
(4)
(2) (2)
(4)
(3)(1)
Datasheet
17
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
56-Lead TSOP Pac kage
14 mm x 20 m m
Top V i ew
A
22
CE1
A
21
A
19
A
18
A
17
A
16
VCC
A
15
A
14
A
13
A
12
CE0
V
PEN
RP#
A
11
A
10
A
9
A
8
VSS
A
7
A
6
A
5
A
4
A
3
A
2
A
20
A
1
A
24
WE#
OE#
DQ
15
DQ
7
DQ
14
DQ
6
VSS
DQ
13
DQ
5
DQ
12
DQ
4
VCCQ
VSS
DQ
11
DQ
3
DQ
10
DQ
2
VCC
DQ
9
DQ
1
DQ
8
DQ
0
A
0
BYTE
#
A
23
STS
CE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
(3) (5)
(4)
(2)
(1)
Numonyx
®
Em be dd ed Flash Memor y J 3
4.2 56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit
Notes:
1. No internal connection for pin 9; it may be driven or floated. For legacy designs, the pin can be tied to VCC.
2. A0 is the least significant address bit.
3. A22 is valid for 64-Mbit density and above. On 32-Mbit, it is a no-connect (NC).
4. A23 is valid for 128-Mbit density. On 32- and 64-Mbit, it is a no-connect (NC).
5. A24 is a no connect (NC) on 128-, 64-, 32- Mbit, reserved for 256-Mbit.
Figur e 6: 56-Lead TSOP Package Pinou t (32 /6 4/1 28 Mbit)
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
18
4.3 S ignal Descriptions
Table 3 lists the active signals used on J3 65 nm SBC and provides a description of
each.
Table 3: Signal De scriptio ns f or J3 65 nm SBC
Symbol Type Name and Function
A0 Input BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
A[MAX:1] Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
32-Mbit — A[21:1]
64-Mbit— A[22:1]
128-Mbit — A[23:1]
DQ[7:0] Input/
Output
LOW-B YTE DATA BUS : Inputs data during buffer writes and programming, and inputs commands
during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data
is internally latched during write operations.
DQ[15:8] Input/
Output
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15:8] float in x8 mode.
CE[2:0] Input
CHIP ENABLE: Activates the 32-, 64-, 128-Mbit devices’ control logic, input buffers, decoders, and
sense amplifiers. When the device is de-selected (see Table 17, “Chip Enable Truth Table
for 32-, 64-, 128-Mb” on page 30), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of
CE0, CE1, or CE2 that disables the device (see Table 17, “Chip Enable Truth Table for
32-, 64-, 128-Mb” on page 30).
RP# Input RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OE# Input OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
WE# Input WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STS Open Drain
Output
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the Status signal, see the
Configurations command and Section 9.7, “Status Signal” on page 41. STS is to be tied
to VCCQ with a pull-up resistor.
BYTE# Input
BYTE EN ABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
the device in x16 mode, and turns off the A0 input buffer, the address A1 becomes the lowest-order
address bit.
VPEN Input
ERASE / PROGRAM / BLO CK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With VPEN VPENLK, memory contents cannot be altered.
VCC Power
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC
VLko.
Caution: Device operation at invalid Vcc voltages should not be attempted.
VCCQ Power I/ O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC.
VSS Supply GROUND: Ground reference for device logic voltages. Connect to system ground.
NC No Connect: Lead is not internally connected; it may be driven or floated.
RFU Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
functionality and enhancement.
Datasheet
19
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
5.2 Operating Conditions
Warning: Operations beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
5.3 Power-Up/Down
This section provides an overview of system level considerations with regards to the
flash device. It includes a brief description of power-up/down sequence and decoupling
design considerations.
5.3.1 Power-Up/Down Sequence
To prevent conditions that could result in spurious program or erase operations, the
power-up/power-down sequence shown in Ta b l e 6 is recommended. For DC voltage
characteristics refer to Ta b l e 8 . Note that each power supply must reach its minimum
voltage range before applying/removing the next supply voltage.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without
notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.
Table 4: Absolute Maximum Rat ings
Parameter Min Max Unit Notes
Temperature under Bias Expanded (TA, Ambient) –40 +85 °C
Storage Temperature –65 +125 °C
VCC Voltage –2.0 +5.6 V 2
VCCQ Voltage –2.0 +5.6 V 2
Voltage on any input/output signal (except VCC, VCCQ) –2.0 VCCQ (max) + 2.0 V 1
ISH Output Short Circuit Current 100 mA 3
Notes:
1. Voltage is referenced to VSS. During infrequent non-periodic transitions, the voltage potential between VSS and input/
output pins may undershoot to –2.0 V for periods < 20 ns or overshoot to VCCQ (max) + 2.0 V for periods < 20 ns.
2. During infrequent non-periodic transitions, the voltage potential between VCC and the supplies may undershoot to –2.0
V for periods < 20 ns or VSUPPLY (max) + 2.0 V for periods < 20 ns.
3. Output shorted for less than one second. No more than one output pin/ball can be shorted at a time.
Table 5: Temperature and VCC Operat in g C on dition
Symbol Parameter Min Max Unit Test Condition
TAOperating Temperature -40.0 +85 °C Ambient Temperature
VCC VCC Supply Voltage 2.70 3.6 V
VCCQ VCCQ Supply Voltage 2.70 3.6 V
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
20
Note:
1. Power supplies connected or sequenced together.
Device inputs must not be driven until all supply voltages reach their minimum range.
RP# should be low during power transitions.
5.3.2 Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized,
charge pumps are switched on, and internal voltage nodes are ramped. All of this
internal activities produce transient signals. The magnitude of the transient signals
depends on the device and system loading. To minimize the effect of these transient
signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal.
Capacitors should be placed as close as possible to device connections.
Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be
placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor
should help overcome voltage slumps caused by PCB trace inductance.
5.4 Reset
By holding the flash device in reset during power-up and power-down transitions,
invalid bus conditions may be masked. The flash device enters reset mode when RP# is
driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-
impedance state. After return from reset, a certain amount of time is required before
the flash device is able to perform normal operations. After return from reset, the flash
device defaults to asynchronous page mode. If RP# is driven low during a program or
erase operation, the program or erase operation will be aborted and the memory
contents at the aborted block or address are no longer valid. See Figure 12, “AC
Waveform for Reset Operation” on page 28 for detailed information regarding reset
timings.
Table 6: Power-Up/Dow n Se qu en ce
Power Supply
Voltage Power-Up Sequence Power-Down Sequence
VCC(min) 1st 1st
1st(1) Sequencing not
required(1)
3rd 2nd
2nd(1) Sequencing not
required(1)
VCCQ(min) 2nd
2nd(1) 2nd
1st(1)
VPEN(min) 3rd 2nd 1st 1st
Datasheet
21
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
6.0 Electrical Characteristics
6.1 DC Current Specifications
Table 7: DC Current Charac teristics
VCCQ 2.7 - 3.6V
Test Conditions NotesVCC 2.7 - 3.6V
Symbol Parameter Typ Max Unit
ILI Input and VPEN Load Current ±1μAVCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or VSS
1
ILO Output Leakage Current ±10 μAVCC= VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or VSS
1
ICCS VCC Standby Current
50 120 μA
CMOS Inputs, VCC = VCC Max; Vccq =
VccqMax
Device is disabled (see Table 17, “Chip
Enable Truth Table for 32-, 64-,
128-Mb” on page 30),
RP# = VCCQ ± 0.2 V 1,2,3
0.71 2 mA
TTL Inputs, VCC = VCC Max,
Vccq = VccqMax
Device is disabled (see Table 17, “Chip
Enable Truth Table for 32-, 64-,
128-Mb” on page 30), RP# = VIH
ICCD VCC Power-Down Current 50 120 μARP# = V
SS ± 0.2 V, IOUT (STS) = 0 mA
ICCR 8-Word Page
15 20 mA
CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ
Max using standard 8 word page mode
reads.
Device is enabled (see Tab le 1 7, C h i p
Enable Truth Table for 32-, 64-,
128-Mb” on page 30)
f = 5 MHz, IOUT = 0 mA
1,3
30 54 mA
CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ
Max using standard 8 word page mode
reads.
Device is enabled (see Tab le 1 7, C h i p
Enable Truth Table for 32-, 64-,
128-Mb” on page 30)
f = 33 MHz, IOUT = 0 mA
ICCW VCC Program or Set Lock-Bit Current
35 60 mA CMOS Inputs, VPEN = VCC 1,4
40 70 mA TTL Inputs, VPEN = VCC
ICCE
ICCBC
VCC Block Erase or VCC Blank Check or
Clear Block Lock-Bits Current
35 70 mA CMOS Inputs, VPEN = VCC 1,4
40 80 mA TTL Inputs, VPEN = VCC
ICCWS
ICCES
VCC Program Suspend or Block Erase
Suspend Current —10mA
Device is enabled (see Tab le 1 7, C h i p
Enable Truth Table for 32-, 64-,
128-Mb” on page 30)
1,5
Notes:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
Contact Numonyx or your local sales office for information about typical specifications.
2. Includes STS.
3. CMOS inputs are either VCC ± 0.2 V or VSS ± 0.2 V. TTL inputs are either VIL or VIH.
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the
device’s current draw is ICCR and ICCWS.
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
22
6.2 DC Voltage specifications
6.3 Capacitance
Notes:
1. Sampled, not 100% tested.
2. TA = -40 °C to +85 °C, VCC= VCCQ= 0 to 3.6 V.
Table 8: DC Voltage Characteristics
VCCQ 2.7 - 3.6 V
Test Conditions NotesVCC 2.7 - 3.6 V
Symbol Parameter Min Max Unit
VIL Input Low Voltage –0.5 0.8 V 2, 5, 6
VIH Input High Voltage 2.0 VCCQ + 0.5 V 2, 5, 6
VOL Output Low Voltage
—0.4V
VCC = VCCMin
VCCQ = VCCQ Min
IOL = 2 mA
1, 2
—0.2V
VCC = VCCMin
VCCQ = VCCQ Min
IOL = 100 µA
VOH Output High Voltage
0.85 × VCCQ —V
VCC = VCCMIN
VCCQ = VCCQ Min
IOH = –2.5 mA
1, 2
VCCQ 0.2 V
VCC = VCCMIN
VCCQ = VCCQ Min
IOH = –100 µA
VPENLK
VPEN Lockout during Program,
Erase and Lock-Bit Operations —2.2V2, 3
VPENH
VPEN during Block Erase, Program,
or Lock-Bit Operations 2.7 3.6 V 3
VLKO VCC Lockout Voltage 2.0 V 4
Notes:
1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the
range between VPENLK (max) and VPENH (min), and above VPENH (max).
4. Block erases, programming, and lock-bit configurations are inhibited when VCC VLKO, and not guaranteed in the range
between VLKO and VCC (min), and above VCC (max).
5. Includes all operational modes of the device.
6. Input/Output signals can undershoot to -1.0V referenced to VSS and can overshoot to VCCQ + 1.0V for duration of 2ns or
less, the VCCQ valid range is referenced to VSS.
Table 9: Capacitance
Symbol Parameter1Type Max Unit Condition2
CIN Input Capacitance 67pF
VIN = 0.0 V
COUT Output Capacitance 45pF
VOUT = 0.0 V
Datasheet
23
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.0 AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention.
Note: Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that
refers to the aggregate initial-access delay as determined by tAVQV, tELQV
, and tGLQV
(whichever is satisfied last) of the flash device. tAPA is specified in the flash devices
data sheet, and is the address-to-data delay for subsequent page-mode reads.
Figure 7: Timing Signal Naming Convention
Tabl e 10: Timin g Signal Name Deco der
Signal Code State Code
Address A High H
Data - Read Q Low L
Data - Write D High-Z Z
Chip Enable (CE) E Low-Z X
Output Enable (OE#) G Valid V
Write Enable (WE#) W Invalid I
Status (STS) R
Reset (RP#) P
Byte Enable (BYTE#) F
Erase/Program/Block Lock
Enable (VPEN)V
E
t
L Q V
S
our ce Signal Target St at e
Source St at e Target Sign
al
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
24
7.1 Read Specifications
Notes:
1. CEX low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX (see note 1 and Tab le 1 7 , Chi p Ena b le Tru t h
Table for 32-, 64-, 128-Mb” on page 30) without impact on tELQV
.
4. See Figure 13, “AC Input/Output Reference Waveform” on page 29 and Figure 14, “Transient
Equivalent Testing Load Circuit” on page 29 for testing characteristics.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Table 11: Read Op er ations
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
# Sym Parameter Density Min Max Unit Notes
R1 tAVAV Read/Write Cycle Time
All
75 ns 1,2
R2 tAVQV Address to Output Delay 75 ns 1,2
R3 tELQV CEX to Output Delay 75 ns 1,2
R4 tGLQV OE# to Non-Array Output Delay 25 ns 1,2,4
R5 tPHQV RP# High to Output Delay
32 Mbit 150
ns
1,2
64 Mbit 180 1,2
128 Mbit 210 1,2
R6 tELQX CEX to Output in Low Z
All
0 ns 1,2,5
R7 tGLQX OE# to Output in Low Z 0 ns 1,2,5
R8 tEHQZ CEX High to Output in High Z 25 ns 1,2,5
R9 tGHQZ OE# High to Output in High Z 15 ns 1,2,5
R10 tOH
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First 0 ns 1,2,5
R11 tELFL/tELFH CEX Low to BYTE# High or Low 10 ns 1,2,5
R12 tFLQV/tFHQV BYTE# to Output Delay 1 µs 1,2
R13 tFLQZ BYTE# to Output in High Z 1 µs 1,2,5
R14 tEHEL CEx High to CEx Low 0 ns 1,2,5
R15 tAPA Page Address Access Time 25 ns 5, 6
R16 tGLQV OE# to Array Output Delay 25 ns 1,2,4
Datasheet
25
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Notes:
1. CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
query reads, or device identifier reads).
Notes:
1. CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2. In this diagram, BYTE# is asserted high.
Figure 8: Single-Word Asynchronous Read Waveform
Addres s [ A]
R2
R1
R3
R4
R7
R6
R5
CE x [E]
OE# [G]
WE# [W]
DQ[15:0] [Q]
BYT E# [F ]
RP# [P ]
R11 R12
R8
R9
R10
R13
Figure 9: 8-Wo rd Asynchronous Page Mode Read
A[M AX:4] [A]
000 111
1 2 87
R2
R1
R3
R4
R7
R6
R5
R10R15 R10 R9
R8
A[3:1] [A]
CE x [E ]
OE# [G]
WE# [W]
DQ[15:0] [Q]
RP# [P]
BYTE# [F]
001 110
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
26
Table 12: Write Operations
# Symbol Parameter Density
Valid for All
Speeds Unit Notes
Min Max
W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX) Going Low
32 Mbit 150
ns
1,2,3,464 Mbit 180
128 Mbit 210
W2 tELWL (tWLEL)CE
X (WE#) Low to WE# (CEX) Going Low
All
0 1,2,3,5
W3 tWP Write Pulse Width 60 1,2,3,5
W4 tDVWH (tDVEH) Data Setup to WE# (CEX) Going High 50 1,2,3,6
W5 tAVWH (tAVEH) Address Setup to WE# (CEX) Going High 55 1,2,3,6
W6 tWHEH (tEHWH)CE
X (WE#) Hold from WE# (CEX) High 0 1,2,3
W7 tWHDX (tEHDX) Data Hold from WE# (CEX) High 0 1,2,3
W8 tWHAX (tEHAX) Address Hold from WE# (CEX) High 0 1,2,3
W9 tWPH Write Pulse Width High 30 1,2,3,7
W11 tVPWH (tVPEH)V
PEN Setup to WE# (CEX) Going High 0 1,2,3,4
W12 tWHGL (tEHGL) Write Recovery before Read 35 1,2,3,8
W13 tWHRL (tEHRL)WE# (CE
X) High to STS Going Low 500 1,2,3,9
W15 tQVVL VPEN Hold from Valid SRD, STS Going High 0 1,2,3,4,
9,10
Notes:
1. CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for
32-, 64-, 128-Mb” on page 30).
2. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Char acte risti cs–Re ad-Only Oper ations.
3. A write operation can be initiated and terminated with either CEX or WE#.
4. Sampled, not 100% tested.
5. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
6. Refer to Table 18, “Enhanced Configuration Register” on page 32 for valid AIN and DIN for block erase,
program, or lock-bit configuration.
7. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going
low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
8. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
9. STS timings are based on STS configured in its RY/BY# default mode.
10. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1]
= 0).
Datasheet
27
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 10: Asynchronous Write Waveform
Address [ A]
D
W8
W3
CEx (WE#) [E (W)]
OE# [ G]
DA TA [D/Q]
VPEN [ V]
RP# [P]
W2
W5
W E# (CEx ) [W (E)]
STS [R] W1
W6
W9
W4 W7
W13
W11
Figure 11: Asynchronous Write to Read Waveform
Address [A]
D
W8
W3
CEx [E]
OE# [G]
DA TA [D/Q ]
VPEN [V]
RP # [P ]
W2
W5
WE# [W]
W1
W6
W12
W4 W7
W11
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
28
7.2 Program, Erase, Block-Lock Specifications
7.3 Reset Specifications
Note: STS is shown in its default mode (RY/BY#).
Table 1 3: Confi gu r a t ion P erformance
# Symbol Parameter Typ Max Unit Notes
W200 tPROG/W Program Time Single word 40 175 µs 1,2,3,4,6
W250 tPROG Buffer Program Time
Aligned 16 Words BP Time (32 Bytes) 128 654 µs 1,2,3,4,5,6
Aligned 128 Words BP Time (256 Bytes) 400 2000 µs 1,2,3,4,5,6
Aligned 256 Words BP Time 720 3600 µs 1,2,3,4,5,6
W501 tERS/AB Block Erase Time 1.0 4.0 sec 1,2,3,4,6
W650 tlks Set Lock-Bit Time 50 60 µs 1,2,3,4,6
W651 tlkc Clear Block Lock-Bits Time 0.5 1 sec 1,2,3,4,6
W600 tSUSP/P Program Suspend Latency Time to Read 15 20 µs 1,2,3,6
W601 tSUSP/E Erase Suspend Latency Time to Read 15 20 µs 1,2,3,6
W602 tERS/SUSP Erase to Suspend 500 µs 1,7
W652 tSTS STS Pulse Width Low Time 500 ns 1
W702 tBC/MB blank check Array Block 3.2 ms
Notes:
1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. These performance numbers are valid for all speed versions.
3. Sampled but not 100% tested.
4. Excludes system-level overhead.
5. These values are valid when the buffer is full, and the start address is aligned.
6. Max values are measured at worst case temperature, data pattern and VCC corner within 100K cycles. But for W650, W651,
W600 and W601, the Max value are expressed at +25 °C or -40 °C.
7. W602 is the typical time between an initial block erase or erase resume command and then a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Figure 12: AC Waveform for Reset Operation
P3
P1 P2P1
S
TS (R)
RP# (P)
Vcc
Datasheet
29
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.4 AC Test Conditions
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Note: CL Includes Jig Capacitance
Ta ble 14: Reset S peci fications
# Symbol Parameter Min Max Unit Notes
P1 tPLPH
RP# Pulse Low Time
(If RP# is tied to VCC, this
specification is not
applicable)
RP# is asserted during block erase,
program or lock-bit configuration
operation
25 µs 1
RP# is asserted during read 100 ns 1
P2 tPHRH
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration 100 ns 1,2
P3 tVCCPH Vcc Power Valid to RP# de-assertion (high) 60 µs
Notes:
1. These specifications are valid for all product versions (packages and speeds).
2. A reset time, tPHQV
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
Figure 13: AC In put/Output Re ference Wav e form
Figure 14: Transient Equivalent Testing Load Circuit
Table 15: Test Configuration
Test Configuration CL (pF)
VCCQ = VCCQMIN 30
OutputTest PointsInput VCCQ/2
VCCQ
0.0
VCCQ/2
Device
Under Test
C
L
O
ut
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
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30
8.0 Bus Interface
This section provides an overview of Bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of
all in-system read, write, and erase operations through the system bus. All bus cycles
to or from the flash memory conform to standard microprocessor bus cycles. Ta b l e 16
summarizes the necessary states of each control signal for different modes of
operations.
Notes:
1. See Ta b l e 1 7 for valid CEx configurations.
2. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
3. DQ refers to DQ[7:0] when BYTE# is low and DQ[15:0] if BYTE# is high.
4. Refer to DC characteristics. When VPEN VPENLK, memory contents can be read but not altered.
5. X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH.
6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration
algorithm. It is VOH (pulled up by an external pull up resistance10k) when the WSM is not busy, in block erase suspend
mode (with programming inactive), program suspend mode, or reset power-down mode.
7. See Section 11.0, “Device Command Codes” on page 47 for valid DIN (user commands) during a Write
operation.
8. Array writes are either program or erase operations.
Table 16: Bus Operations
Mode RP# CEx(1) OE#(2) WE#(2) VPEN DQ15:0(3) STS
(Default
Mode) Notes
Async., Status, Query and
Identifier Reads VIH Enabled VIL VIH XD
OUT High Z 4,6
Output Disable VIH Enabled VIH VIH X High Z High Z
Standby VIH DisabledXXXHigh ZHigh Z
Reset/Power-down VIL XXXXHigh ZHigh Z
Command Writes VIH Enabled VIH VIL XD
IN High Z 6,7
Array Writes VIH Enabled VIH VIL VPENH XV
IL 5,8
Table 17: Chip Enable Truth Table for 32-, 64-, 128-Mb
CE2 CE1 CE0 DEVICE
VIL VIL VIL Enabled
VIL VIL VIH Disabled
VIL VIH VIL Disabled
VIL VIH VIH Disabled
VIH VIL VIL Enabled
VIH VIL VIH Enabled
VIH VIH VIL Enabled
VIH VIH VIH Disabled
Note: For single-chip applications, CE2 and CE1 can be connected to VSS.
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
8.1 Bus Reads
Reading from flash memory outputs stored information to the processor or chipset, and
does not change any contents. Reading can be performed an unlimited number of
times. Besides array data, other types of data such as device information and device
status are available from the flash.
To perform a bus read operation, CEx (refer to Table 17 on page 30) and OE# must be
asserted. CEx is the device-select control; when active, it enables the flash memory
device. OE# is the data-output control; when active, the addressed flash memory data
is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See
Section 9.2, “Read Operations” on page 35.
8.1.1 Asynchr onous Page Mode Read
Unlike J3 130nm devices, J3 65 nm SBC device provides Eight-Word Asynchronous
Page mode only. Array data can be sensed up to eight words (16 Bytes) at a time. This
is the default mode on power-up or reset.
On J3 130nm devices, the Set Enhanced Configuration Register command is used to
enable Eight-Word Page mode upon power-up or reset, however this has no effect on J3
65 nm SBC device anymore.
After the initial access delay, the first word out of the page buffer corresponds to the
initial address. Address bits A[3:1] determine which word is output from the page
buffer for a x16 bus width, and A[3:0] determine which byte is output from the page
buffer for a x8 bus width. Subsequent reads from the device come from the page
buffer. These reads are output on DQ[15:0] for a x16 bus width and DQ[7:0] for a x8
bus width after a minimum delay by changing A[3:1] or A[3:0].
Data can be read from the page buffer multiple times, and in any order.If address bits
A[MAX:4] change at any time, or if CEx# is toggled, the device will sense and load new
data into the page buffer. Asynchronous Page mode is the default read mode on power-
up or reset.
To perform a Page mode read after any other operation, the Read Array command must
be issued to read from the flash array. Asynchronous Page mode reads are permitted in
all blocks and are used to access register information. During register access, only one
word is loaded into the page buffer.
8.1.1.1 Enh an ced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile storage register that when
addressed by the Set ECR command can select between Four-Word Page mode and
Eight-Word Page mode on J3 130nm devices, however this has no effect on J3 65 nm
SBC device.
The ECR is volatile; all bits will be reset to default values when RP# is deasserted or
power is removed from the device. To modify ECR settings, use the Set ECR command.
The Set ECR command is written along with the configuration register value, which is
placed on the lower 16 bits of the address bus A[16:1]. This is followed by a second
write that confirms the operation and again presents the ECR data on the address bus.
After executing this command, the device returns to Read Array mode.
The ECR is shown in Ta b l e 1 8 . 8-word page mode Command Bus-Cycle is captured in
Table 19 for backward compatibility reasons.
Note: If the 8-word Asynchronous Page mode is used on J3 65 nm SBC, a Clear Status
Register command must be executed after issuing the Set ECR command.
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8.1.2 Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled.
Output signals DQ[15:0] are placed in a high-impedance state.
8.2 Bus Writes
Writing or Programming to the device, is where the host writes information or data into
the flash device for non-volatile storage. When the flash device is programmed, ‘ones’
are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase
operation must be performed. Writing commands to the Command User Interface (CUI)
enables various modes of operation, including the following:
Reading of array data
Common Flash Interface (CFI) data
Identifier codes, inspection, and clearing of the Status Register
Block Erasure, Program, and Lock-bit Configuration (when VPEN = VPENH)
Erasing is performed on a block basis – all flash cells within a block are erased together.
Any information or data previously stored in the block will be lost. Erasing is typically
done prior to programming. The Block Erase command requires appropriate command
data and an address within the block to be erased. The Byte/Word Program command
requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear
Block Lock-Bits command requires the command and address within the device to be
cleared.
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or CEX (CEX low is defined as the combination of pins
CE0, CE1, and CE2 that enable the device. CEX high is defined as the combination of
pins CE0, CE1, and CE2 that disable the device. See Table 17 on page 30). Standard
microprocessor write timings are used.
Table 18: Enhanced Configuration Register
Reserved Page
Length Reserved
ECR
15
ECR
14
ECR
13
ECR
12
ECR
11
ECR
10
ECR
9
ECR
8
ECR
7
ECR
6
ECR
5
ECR
4
ECR
3
ECR
2
ECR
1
ECR
0
BITS DESCRIPTION NOTES
ECR[15:14] RFU All bits should be set to 0.
ECR.13 1” = 8-Word Page mode
“0” = 8-Word Page mode (Default)
Either “1” or “0” is for 8-word sense in page
mode.
ECR[12:0] RFU All bits should be set to 0.
Table 19: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command Bus
Cycles
Required
First Bus Cycle Second Bus Cycle
Oper Addr(1) Data Oper Addr(1) Data
Set Enhanced Configuration
Register (Set ECR) 2 Write ECD 0060h Write ECD 0004h
1. ECD = Enhanced Configuration Register Data
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
8.3 Standby
CE0, CE1, and CE2 can disable the device (see Table 17 on page 30) and place it in
standby mode. This manipulation of CEx substantially reduces device power
consumption. DQ[15:0] outputs are placed in a high-impedance state independent of
OE#. If deselected during block erase, program, or lock-bit configuration, the WSM
continues functioning, and consuming active power until the operation completes.
8.3.1 Reset/Power-Down
RP# at VIL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-
impedance state, and turns off numerous internal circuits. RP# must be held low for a
minimum of tPLPH. Time tPHQV is required after return from reset mode until initial
memory access outputs are valid. After this wake-up interval, normal operation is
restored. The CUI is reset to read array mode and Status Register is set to 0080h.
During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the
operation. In default mode, STS transitions low and remains low for a maximum time
of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered
are no longer valid; the data may be partially corrupted after a program or partially
altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to
logic-high (VIH) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When
the system comes out of reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed during Block Erase, Program,
or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,
proper initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx Flash memories allow proper initialization
following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
8.4 Device Commands
When VPEN VPENLK, only read operations from the Status Register, CFI, identifier
codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase,
program, and lock-bit configuration operations. Device operations are selected by
writing specific commands to the Command User Interface (CUI). The CUI does not
occupy an addressable memory location. It is the mechanism through which the flash
device is controlled.
A command sequence is issued in two consecutive write cycles - a Setup command
followed by a Confirm command. However, some commands are single-cycle
commands consisting of a setup command only. Generally, commands that alter the
contents of the flash device, such as Program or Erase, require at least two write cycles
to guard against inadvertent changes to the flash device. Flash commands fall into two
categories: Basic Commands and Extended Commands. Basic commands are
recognized by all Numonyx Flash devices, and are used to perform common flash
operations such as selecting the read mode, programming the array, or erasing blocks.
Extended commands are product-dependant; they are used to perform additional
features such as software block locking. Section 11.0, “Device Command Codes” on
page 47 describes all applicable commands on J3 65 nm SBC device.
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9.0 Flash Operations
This section describes the operational features of flash memory. Operations are
command-based, wherein command codes are first issued to the device, then the
device performs the desired operation. All command codes are issued to the device
using bus-write cycles (see Chapter 8.0, “Bus Interface). A complete list of available
command codes can be found in Section 11.0, “Device Command Codes” on page 47.
9.1 Status Register
The Status Register (SR) is an 8-bit, read-only register that indicates device status and
operation errors. To read the Status Register, issue the Read Status Register command.
Subsequent reads output Status Register information on DQ[7:0], and 00h on
DQ[15:8].
SR status bits are set and cleared by the device. SR e rror bits are set by the device, but
must be cleared using the Clear Status Register command. Upon power-up or exit from
reset, the Status Register defaults to 80h. Page-mode reads are not supported in this
read mode. Status Register contents are latched on the falling edge of OE# or CEX (CEX
low is defined as the combination of pins CE0, CE1, and CE2 that enable the device.
CEX high is defined as the combination of pins CE0, CE1, and CE2 that disable the
device). OE# must toggle to VIH or the device must be disabled before further reads to
update the Status Register latch. The Read Status Register command functions
independently of VPEN voltage.
Table 2 0 shows Status Register bit definitions.
Table 20: Status Register Bit Definitions
Statu s Regis ter (SR) Default Valu e = 80h
Ready
Status
Erase
Suspend
Status
Erase
Error Program
Error
Program/
Erase
Voltage
Error
Program
Suspend
Status
Block-Locked
Error Reserved
76 5 4 3 2 1 0
Bit Name Description
7Ready Status 0 = Device is busy. SR[6:0] are invalid (Not driven);
1 = Device is ready. SR[6:0] are valid.
6Erase Suspend Status 0 = Erase suspend not in effect.
1 = Erase suspend in effect.
5Erase Error Command
Sequence
Error
SR.5 SR.4
0 0 = Program or erase operation successful.
0 1 = Program error - operation aborted.
1 0 = Erase error - operation aborted.
1 1 = Command sequence error - command aborted.
4Program
Error
3 Program/Erase Voltage Error
0 = Within acceptable limits during program or erase operation.
1 = Not within acceptable limits during program or erase operation - Operation
aborted.
2 Program Suspend Status 0 = Program suspend not in effect.
1 = Program suspend in effect.
1Block-Locked Error 0 = Block NOT locked during program or erase - operation successful.
1 = Block locked during program or erase - operation aborted.
0 Reserved Reserved
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
9.1.1 Clearing the Status Register
The Status Register (SR) contain Status and error bits which are set by the device. SR
status bits are cleared by the device, however SR error bits are cleared by issuing the
Clear SR command (see Ta b l e 2 1 ). Resetting the device also clears the SR.
Issuing the Clear SR command places the device in Read SR mode.
Note: Care should be taken to avoid SR ambiguity. If a command sequence error occurs while
in an Erase Suspend condition, the SR will indicate a Command Sequence error by
setting SR.4 and SR.5. When the erase operation is resumed (and finishes), any errors
that may have occurred during the erase operation will be masked by the Command
Sequence error. To avoid this situation, clear the Status Register prior to resuming a
suspended erase operation. The Clear SR command functions independent of the
voltage level on VPEN.
9.2 Read Operations
Four types of data can be read from the device: array data, device information, CFI
data, and device status. Upon power-up or return from reset, the device defaults to
Read Array mode. To change the device’s read mode, the appropriate command must
be issued to the device. Tabl e 2 2 shows the command codes used to configure the
device for the desired read mode. The following sections describe each read mode.
9.2.1 Read Array
Upon power-up or return from reset, the device defaults to Read Array mode. Issuing
the Read Array command places the device in Read Array mode. Subsequent reads
output array data on DQ[15:0]. The device remains in Read Array mode until a
different read command is issued, or a program or erase operation is performed, in
which case, the read mode is automatically changed to Read Status.
To change the device to Read Array mode while it is programming or erasing, first issue
the Suspend command. After the operation has been suspended, issue the Read Array
command. When the program or erase operation is subsequently resumed, the device
will automatically revert back to Read Status mode.
Note: Issuing the Read Array command to the device while it is actively programming or
erasing causes subsequent reads from the device to output invalid data. Valid array
data is output only after the program or erase operation has finished.
Tabl e 21: Clear Status Register Command Bus-Cycles
Command Setup Write Cycle Confirm Write Cycle
Address Bus Data Bus Address Bus Data Bus
Clear Status Register Device Address 0050h
Tabl e 22: Read Mode Command Bus-Cycles
Command Setup Write Cy cle Confirm Write Cycle
Address Bu s Data Bus Address Bus Data Bus
Read Array Device Address 00FFh
Read Status Register Device Address 0070h
Read Device Information Device Address 0090h
CFI Query Device Address 0098h
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The Read Array command functions independent of the voltage level on VPEN.
9.2.2 Read Status Register
Issuing the Read Status Register command places the device in Read Status Register
mode. Subsequent reads output Status Register information on DQ[7:0], and 00h on
DQ[15:8]. The device remains in Read Status Register mode until a different read-
mode command is issued. Performing a program, erase, or block-lock operation also
changes the device’s read mode to Read Status Register mode.
The Status Register is updated on the falling edge of OE# or CEx, whichever occurs
last. Status Register contents are valid only when SR.7 = 1. When WSM is active, SR.7
indicates the WSM’s state and SR[6:0] are in high-Z state.
The Read Status Register command functions independent of the voltage level on
VPEN.
9.2.3 Read Device Information
Issuing the Read Device Information command places the device in Read Device
Information mode. Subsequent reads output device information on DQ[15:0].
The device remains in Read Device Information mode until a different read command is
issued. Also, performing a program, erase, or block-lock operation changes the device
to Read Status Register mode.
The Read Device Information command functions independent of the voltage level on
VPEN.
9.2.4 CFI Query
The CFI query table contains an assortment of flash product information such as block
size, density, allowable command sets, electrical specifications, and other product
information. The data contained in this table conforms to the CFI protocol.
Issuing the CFI Query command places the device in CFI Query mode. Subsequent
reads output CFI information on DQ[15:0]. The device remains in CFI Query mode until
a different read command is issued, or a program or erase operation is performed,
which changes the read mode to Read Status Register mode.
The CFI Query command functions independent of the voltage level on VPEN.
9.3 Programming Operations
All programming operations require the addressed block to be unlocked, and a valid
VPEN voltage applied throughout the programming operation. Otherwise, the
programming operation will abort, setting the appropriate Status Register error bit(s).
The following sections describe each programming method.
9.3.1 Single-Word/Byte Programming
Array programming is performed by first issuing the Single-Word/Byte Program
command. This is followed by writing the desired data at the desired array address. The
read mode of the device is automatically changed to Read Status Register mode, which
remains in effect until another read-mode command is issued.
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
During programming, STS and the Status Register indicate a busy status (SR.7 = 0).
Upon completion, STS and the Status Register indicate a ready status (SR.7 = 1). The
Status Register should be checked for any errors (SR.4), then cleared.
Note: Issuing the Read Array command to the device while it is actively programming causes
subsequent reads from the device to output invalid data. Valid array data is output only
after the program operation has finished.
Standby power levels are not be realized until the programming operation has finished.
Also, asserting RP# aborts the programming operation, and array contents at the
addressed location are indeterminate. The addressed block should be erased, and the
data re-programmed. If a Single-Word/Byte program is attempted when the
corresponding block lock-bit is set, SR.1 and SR.4 will be set.
9.3.2 Buffered Programming
Buffered programming operations simultaneously program multiple words/bytes into
the flash memory array, significantly reducing effective word-write/byte-write times.
User-data is first written to a write buffer, then programmed into the flash memory
array in buffer-size increments. For additional details, see the flow chart of the
buffered-programming operation.
Optimal performance and power consumption is realized by aligning the start address
on 256-Word boundaries (i.e., A[8:1] = 00000000b). Crossing a 256-Word boundary
during a buffered programming operation can cause programming time to double.
To perform a buffered programming operation, first issue the Buffered Program setup
command at the desired starting address. The read mode of the device/addressed
partition is automatically changed to Read Status Register mode.
Polling SR.7 determines write-buffer availability (0 = not available, 1 = available). If
the write buffer is not available, re-issue the setup command and check SR.7; repeat
until SR.7 = 1.
Note: The device defaults to output SR data after the Buffered Programming Setup command
(E8h) is issued. CE# and OE# must be toggled to update Status Register. Don’t issue
the Read SR command (70h), which would be interpreted by the internal state machine
as Buffer Word Count.
Next, issue the word count at the desired starting address. The word count represents
the total number of words to be written into the write buffer, minus one. This value can
range from 00h (one) to a maximum of FFh (256). Exceeding the allowable range
causes an abort.
Note: The maximum number of bytes in write buffer on CFI region (offset 2Ah, refer Tab le 4 1,
“Device Geometry Definition” on page 60) is set to 05h (32 bytes) for backward
compatible reasons. No software change is required on existing applications for both x8
and x16 mode. Applications can optimize the system performance using the maximum
of 256 buffer size. Please contact your sales representatives for questions.
Following the word count, the write buffer is filled with user-data. Subsequent bus-
write cycles provide addresses and data, up to the word count. All user-data addresses
must lie between <starting address> and <starting address + word count>, otherwise
the WSM continues to run as normal but, user may advertently change the content in
unexpected address locations.
Note: User-data is programmed into the flash array at the address issued when filling the
write buffer.
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After all user-data is written into the write buffer, issue the confirm command. If a
command other than the confirm command is issued to the device, a command
sequence error occurs and the operation aborts.
Note: After issuing the confirm command, write-buffer contents are programmed into the
flash memory array. The Status Register indicates a busy status (SR.7 = 0) during
array programming.Issuing the Read Array command to the device while it is actively
programming or erasing causes subsequent reads from the device to output invalid
data. Valid array data is output only after the program or erase operation has finished.
Upon completion of array programming, the Status Register indicates ready (SR.7 = 1).
A full Status Register check should be performed to check for any programming errors,
then cleared by using the Clear Status Register command.
Additional buffered programming operations can be initiated by issuing another setup
command, and repeating the buffered programming bus-cycle sequence. However, any
errors in the Status Register must first be cleared before another buffered
programming operation can be initiated.
9.4 Block Erase Operations
Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation
must be performed (See Section 9.3, “Programming Operations”). Erasing is performed
on a block basis - an entire block is erased each time an erase command sequence is
issued. Once a block is fully erased, all addressable locations within that block read as
logical ones (FFFFh for x16 mode, FFh for x8 mode). Only one block-erase operation
can occur at a time, and is not permitted during a program suspend.
To perform a block-erase operation, issue the Block Erase command sequence at the
desired block address. Ta b l e 2 3 shows the two-cycle Block Erase command sequence.
Note: A block-erase operation requires the addressed block to be unlocked, and a valid
voltage applied to VPEN throughout the block-erase operation. Otherwise, the
operation will abort, setting the appropriate Status Register error bit(s).
The Erase Confirm command latches the address of the block to be erased. The
addressed block is preconditioned (programmed to all zeros), erased, and then verified.
The read mode of the device is automatically changed to Read Status Register mode,
and remains in effect until another read-mode command is issued.
During a block-erase operation, STS and the Status Register indicates a busy status
(SR.7 = 0). Upon completion, STS and the Status Register indicates a ready status
(SR.7 = 1). The Status Register should be checked for any errors, then cleared. If any
errors did occur, subsequent erase commands to the device are ignored unless the
Status Register is cleared.
The only valid commands during a block erase operation are Read Array, Read Device
Information, CFI Query, and Erase Suspend. After the block-erase operation has
completed, any valid command can be issued.
Table 23: Block-Erase Command Bus-Cycles
Command Setup Write Cycle Confirm Write Cycle
Address Bus Data Bus Address Bus Data Bus
Block Erase Block Address 0020h Block Address 00D0h
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Note: Issuing the Read Array command to the device while it is actively erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only
after the block-erase operation has finished.
Standby power levels are not be realized until the block-erase operation has finished.
Also, asserting RP# aborts the block-erase operation, and array contents at the
addressed location are indeterminate. The addressed block should be erased before
programming within the block is attempted.
9.5 Blank Check
The Blank Check operation determines whether a specified array block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. Blank Check is especially useful in the case of
erase operation interrupted by a power loss event.
Blank Check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc.). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Block Blank Check command to the
block address. Next, the Blank Check Confirm command is issued along with the same
block address. When a successful command sequence is entered, the device
automatically enters the Read Status State. The WSM then reads the entire specified
block, and determines whether any bit in the block is programmed or over-erased.
The status register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status
Register indicates a ready status (SR.7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased, the Status Register bit SR.5 will be set (“1”). CE# or OE#
toggle (during polling) updates the Status Register.
The device remains in Status Register Mode until another command is written to the
device. After examining the Status Register, it should be cleared by the Clear Status
Register command before issuing a new command. Any command can follow once the
Blank Check command is complete.
9.6 Suspend and Resume
An erase or programming operation can be suspended to perform other operations, and
then subsequently resumed. Ta b l e 2 4 shows the Suspend and Resume command bus-
cycles.
Note: All erase and programming operations require the addressed block to remain unlocked
with a valid voltage applied to VPEN throughout the suspend operation. Otherwise, the
block-erase or programming operation will abort, setting the appropriate Status
Register error bit(s). Also, asserting RP# aborts suspended block-erase and
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
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programming operations, rendering array contents at the addressed location(s)
indeterminate.
To suspend an on-going erase or program operation, issue the Suspend command to
any device address. The program or erase operation suspends at pre-determined points
during the operation after a delay of tSUSP
. Suspend is achieved whenSTS (in RY/BY#
mode) goes high, SR[7,6] = 1 (erase-suspend) or SR[7,2] = 1 (program-suspend).
Note: Issuing the Suspend command does not change the read mode of the device. The
device will be in Read Status Register mode from when the erase or program command
was first issued, unless the read mode was changed prior to issuing the Suspend
command.
Not all commands are allowed when the device is suspended. Tabl e 25 shows which
device commands are allowed during Program Suspend or Erase Suspend.
During Suspend, array-read operations are not allowed in blocks being erased or
programmed.
A block-erase under program-suspend is not allowed. However, word-program under
erase-suspend is allowed, and can be suspended. This results in a simultaneous erase-
suspend/ program-suspend condition, indicated by SR[7,6,2] = 1.
Table 24: Suspend and Resume Command Bus-Cycles
Command Setup Write Cycle Confirm Write Cycle
Address Bu s Data Bus Ad dress Bus Data Bus
Suspend Device Address 00B0h
Resume Device Address 00D0h
Table 25: Valid Co mmands Dur in g S us pend
Device Command Program Suspend Erase Suspend
STS Configuration Allowed Allowed
Read Array Allowed Allowed
Read Status Register Allowed Allowed
Clear Status Register Allowed Allowed
Read Device Information Allowed Allowed
CFI Query Allowed Allowed
Word/Byte Program Not Allowed Allowed
Buffered Program Not Allowed Allowed
Block Erase Not Allowed Not Allowed
Program Suspend Not Allowed Allowed
Erase Suspend Not Allowed Not Allowed
Program/Erase Resume Allowed Allowed
Lock Block Not Allowed Not Allowed
Unlock Block Not Allowed Not Allowed
Program OTP Register Not Allowed Not Allowed
Blank Check Not Allowed Not Allowed
Datasheet
41
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
To resume a suspended program or erase operation, issue the Resume command to
any device address. The read mode of the device is automatically changed to Read
Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes
low, and the respective Status Register bits are cleared.
When the Resume command is issued during a simultaneous erase-suspend/ program-
suspend condition, the programming operation is resumed first. Upon completion of the
programming operation, the Status Register should be checked for any errors, and
cleared. The resume command must be issued again to complete the erase operation.
Upon completion of the erase operation, the Status Register should be checked for any
errors, and cleared.
9.7 Status Signal
The STATUS (STS) signal can be configured to different states using the STS
Configuration command (Ta b l e 2 6 ). Once the STS signal has been configured, it
remains in that configuration until another Configuration command is issued or RP# is
asserted low. Initially, the STS signal defaults to RY/BY# operation where RY/BY# low
indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready
for a new operation or suspended. Ta b l e 2 7 displays possible STS configurations.
To reconfigure the STATUS (STS) signal to other modes, the Configuration command is
given followed by the desired configuration code. The three alternate configurations are
all pulse mode for use as a system interrupt as described in the following paragraphs.
For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1
controls Program Complete interrupt pulse. Supplying the 00h configuration code with
the Configuration command resets the STS signal to the default RY/BY# level mode.
The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
Note: STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.
Tabl e 26: STS Configurati on Register Command Bus-Cycles
Command Setup Write Cycle Confirm Write Cycle
Address Bus Data Bus Address Bus Data Bus
STS Configuration Device Address 00B8h Device Address Register Data
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
42
9.8 Security and Protection
J3 65 nm SBC device offers both hardware and software security features. Block lock
operations, PRs and VPEN allow users to implement various levels of data protection.
9.8.1 Normal Block Locking
J3 65 nm SBC has the capability of Flexible Block Locking (locked blocks remain locked
upon reset or power cycle): All blocks within the device are in unlocked state when ship
from Numonyx. Blocks can be locked individually by issuing the Set Block Lock Bit
command sequence to any address within a block. Once locked, blocks remain locked
when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed. Ta b l e 2 8 summarizes the command bus-cycles.
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR.7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when VCC and VPEN
are valid. When VPEN VPENLK, block lock-bits cannot be changed.
Table 27: STS Configuration Register and Coding Definitions
D7 D6 D5 D4 D3 D2 D1 D0
Reserved3Pulse on
Program
Complete1
Pulse on
Erase
Complete1
D[1:0] = STS Configuration Codes2Notes
00 = default, level mode;
device ready indication
Controls HOLD to a memory controller to prevent accessing a flash memory
subsystem while any flash device's WSM is busy.
01 = pulse on Erase Complete
Generates a system interrupt pulse when any flash device in an array has
completed a block erase. Helpful for reformatting blocks after file system free
space reclamation or “cleanup.
10 = pulse on Program Complete Not supported on this device.
11 = pulse on Erase or Program Complete
Generates system interrupts to trigger servicing of flash arrays when either
erase or program operations are completed, when a common interrupt service
routine is desired.
Notes:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
2. An invalid configuration code will result in both SR.4 and SR.5 being set.
3. Reserved bits are invalid should be ignored.
Table 28: Block Locking Command Bus-Cycles
Command Setup Write Cycle Confirm Write Cycle
Address Bu s Data Bus Address Bu s Data Bus
Set Block Lock Bit Block Address 0060h Block Address 0001h
Clear Block Lock Bits Device Address 0060h Device Address 00D0h
Datasheet
43
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
When the set lock-bit operation is complete, SR.4 should be checked for any error.
When the clear lock-bit operation is complete, SR.5 should be checked for any error.
Errors bits must be cleared using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked).
9.8.2 Configurable Block Locking
J3 65 nm SBC devices feature user-configurable block locking. This feature can be
implemented to protect and/or secure the user’s system. The user can individually set
each block as Non-Volatile Temporary, Non-Volatile Semi-Permanent or Non-Volatile
Permanent. For additional information and collateral, please contact the sales
representative.
9.8.3 Password Access
Password Access is a security enhancement offered on the J3 65 nm SBC device. This
feature protects information stored in main-array memory blocks by preventing content
alteration or reads, until a valid 64-bit password is received. Password Access may be
combined with Non-Volatile Protection and/or Volatile Protection to create a multi-
tiered solution.
Please contact your Numonyx Sales for further details concerning Password Access.
9.8.4 128-bit OTP Protection Register
J3 65 nm SBC includes a 128-bit Protection Register (PR) that can be used to increase
the security of a system design. For example, the number contained in the PR can be
used to “match” the flash component with other system components such as the CPU
or ASIC, hence preventing device substitution.
The 128-bits of the PR are divided into two 64-bit segments:
One segment is programmed at the Numonyx factory with a unique unalterable 64-
bit number.
The other segment is left blank for customer designers to program as desired. Once
the customer segment is programmed, it can be locked to prevent further
programming.
9.8.5 Reading the 128-bit OTP Protection Register
The Protection Register is read in Identification Read mode. The device is switched to
this mode by issuing the Read Identifier command (0090h). Once in this mode, read
cycles from addresses shown in Table 31, “Word-Wide Protection Register Addressing”
or Table 32, “Byte-Wide Protection Register Addressing” retrieve the specified
information. To return to Read Array mode, write the Read Array command (00FFh).
9.8.6 Programming the 128-bit OTP Protection Register
PR bits are programmed using the two-cycle Program OTP Register command. The 64-
bit number is programmed 16 bits at a time for word-wide configuration and eight bits
at a time for byte-wide configuration. First write the Protection Program Setup
command, 00C0h. The next write to the device will latch in address and data and
program the specified location. The allowable addresses are shown in Table 31, “Word-
Wide Protection Register Addressing” on page 45 or Table 32, “Byte-Wide Protection
Register Addressing” on page 45. See Figure 24, “Protection Register Programming
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
44
Flowchart” on page 56. Any attempt to address Program OTP Register command
outside the defined PR address space will result in a Status Register error (SR.4 will be
set). Attempting to program a locked PR segment will result in a Status Register error
(SR.4 and SR.1 will be set).
9.8.7 Locking the 128-bit OTP Protection Register
The user-programmable segment of the PR is lockable by programming Bit 1 of the
Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. Bit 1 is set using the Protection
Program command to program “0xFFFD” to the PLR. After these bits have been
programmed, no further changes can be made to the values stored in the Protection
Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.
Note: A0 is not used in x16 mode when accessing the protection register map. See Ta b l e 3 1 for x16 addressing. In x8 mode
A0 is used, see Tabl e 32 for x8 addressing.
Table 29: Programmin g the 128-bit Protectio n Re gister Comman d Bus-Cycles
Command First Bus Cycle Second Bus Cyc le
Address Bu s Data Bus Address Bu s Data Bus
Program OTP Register Device Address 00C0h Register Offset Register Data
Table 30: Programming Protection Lock Reg is ter Comman d Bus -C ycles
Command First Bus Cycle Second Bus Cyc le
Address Bu s Data Bus Address Bu s Data Bus
Program OTP Register Device Address 00C0h 80h FFFDh
Figure 15: 128-bit Protection Register Memory Map
0x88
0x85
64- bit Segment
( User- Programmable)
0x84
0x81
0x80
P rot ec t i on Loc k R egi s t er
64- bit Segment
(Factory- Programmed)
15 14 13 12 11 10 9876543210
128-Bi t P rot ec tion Regis ter
0x82
0x83
0x86
0x87
Word Address 1 28-Mbi t: A[23: 1]
64-Mbit: A[22: 1]
32-Mbit: A[21: 1]
Datasheet
45
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
9.8.8 VPEN Protection
When it’s necessary to protect the entire array, global protection can be achieved using
a hardware mechanism using VPEN. Whenever a valid voltage is present on VPEN,
blocks within the main flash array can be erased or programmed. By grounding VPEN,
blocks within the main array cannot be altered – attempts to program or erase blocks
will fail resulting in the setting of the appropriate error bit in the Status Register. By
holding VPEN low, absolute write protection of all blocks in the array can be achieved.
Table 31: Word-Wide Pr otec t ion Regi ster Ad dr essing
Word Use A8A7A6A5A4A3A2A1
LOCK Both 10000000
0 Factory 10000001
1 Factory 10000010
2 Factory 10000011
3 Factory 10000100
4 User 10000101
5 User 10000110
6 User 10000111
7 User 10001000
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
Table 32: Byte-Wide Protection Register Addressing
ByteUseA8A7A6A5A4A3A2A1A0
LOCKBoth100000000
LOCKBoth100000001
0Factory100000010
1Factory100000011
2Factory100000100
3Factory100000101
4Factory100000110
5Factory100000111
6Factory100001000
7Factory100001001
8User100001010
9User100001011
AUser100001100
BUser100001101
CUser100001110
DUser100001111
EUser100010000
FUser100010001
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX:9] = 0.
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
46
10.0 ID Codes
Table 33: Read Identifier Codes
Code Address Data
Device Code
32-Mbit 00001h 0016h
64-Mbit 00001h 0017h
128-Mbit 00001h 0018h
Datasheet
47
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
11.0 Device Com mand Codes
For a complete definition on device operations refer to Section 8.4, “Device Commands”
on page 33. The list of all applicable commands are included here one more time for
the convenience.
Note: Some customer applications use illegal or invalid commands (like 0x00) accidentally or
intentionally with the device. An illegal or invalid command caused the device output to
change to Array Read mode on 130nm. On the 65nm device, the output will change to
Read Status Register mode.
After an illegal or invalid command, software may attempt to read the device. If the
illegal command was intentional, software will expect to read array data on 130nm
device, such as 0xFFFF in an unprogrammed location. On the 65nm device, software
may not get the expected array data and instead the status register is read.
Please refer to the legal and valid commands/spec defined in the Datasheet, such as
forread mode, issue 0xFF to Read Array mode, 0x90 to Read Signature, 0x98 to Read
CFI/OTP array mode.
Table 34: Command Bus Cycles and Command Codes
Command Setup Write Cycle Confirm Write Cycle
Address Bus Data Bu s Address Bus Data Bus
Registers
Program Enhanced Configuration Register Register Data 0060h Register Data 0004h
Program OTP Register Device Address 00C0h Register Offset Register Data
Clear Status Register Device Address 0050h
Program STS Configuration Register Device Address 00B8h Device Address Register Data
Read Modes
Read Array Device Address 00FFh
Read Status Register Device Address 0070h
Read Identifier Codes (Read Device Information) Device Address 0090h
CFI Query Device Address 0098h
Program and Erase
Word/Byte Program Device Address 0040h/
0010h Device Address Array Data
Buffered Program Block Address 00E8h Block Address 00D0h
Block Erase Block Address 0020h Block Address 00D0h
Program/Erase Suspend Device Address 00B0h
Program/Erase Resume Device Address 00D0h
Security
Set Block Lock Bit Block Address 0060h Block Address 0001h
Clear Block Lock Bits Device Address 0060h Device Address 00D0h
Blank Check
Blank Check Block Address 00BCh Block Address 00D0h
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
48
12.0 Flow Charts
Notes:
1. The device defaults to output SR data after the Buffered Programming Setup command (E8h) is issued. CE# and OE#
must be toggled to update Status Register. Don’t issue the Read SR command (70h), which would be interpreted by the
internal state machine as Buffer Word Count.
Figure 16: Write to Buffer Flowchart
Start
Setup
-Write 0xE8
- Bl ock Addres s
Check Buffer Status
- Perform Read Operation
- Read Ready Status on signal SR.7
(Note 1)
SR.7 = 1 ?
Word Count
- Address = block address
-Data = word c ount minus 1
(Val id range = 0x00 to 0xFF)
Load B uffer
- Fill write buffer up to word count
- Address = wi thin buffer range
- Data = User data
Confirm
-Write 0xD0
- Bl ock address
Read Status Register (SR)
SR.7 = 1 ?
Full Status Register Chec k(if
desired)
End
No
No
Yes
Yes
Datasheet
49
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figur e 17 : Status Register Flowchart
Start
SR 7 = '1'
SR 2 = '1'
SR 4 = '1'
SR 3 = '1'
SR 1 = '1'
Yes
Yes
Yes
No
No
No
No
SR 6 = '1' Yes
No
SR 5 = '1'
No
No
Error
C om m and Sequence
Yes
Yes
Yes
Error
Eras e Failure
Error
Program Failure
- Set b y W SM
- R eset b y u ser
- See C l ear Statu s
Register
Command
- Set/Reset
by W SM
SR 4 = '1' Yes
No
End
Command Cycle
- I s s ue St at us R egist er Comm and
- Addres s = any devic e addres s
- D at a = 0x70
Erase Suspen d
See Suspend/ R es um e F lowchart
Pr o g r am Su sp en d
See Suspend/ R es um e F lowchart
Error
V
PEN
< V
PENLK
Error
Block Locked
D ata C ycl e
- Read Stat us R egis t er SR [ 7: 0]
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
50
Figure 18: Byte/W ord Program Flowchart
Start
Write 40H,
Address
Write Data and
Address
Read Status
Register
SR.7 =
Full Status
Check if Desired
Byte/Word
Program Complete
Read Status
Register Data
(See Above)
Voltage Range Error
Device Protect Error
Programming Error
Byte/Word
Program
Successful
SR.3 =
SR.1 =
SR.4 =
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Write
Standby
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Stat us Register command.
Repeat for s ubsequent programming operations.
SR full status chec k can be done after each program operation, or
after a s equence of programming operations.
Writ e F F H after the last program operation to place device in read
array mode.
Bus
Operation
Standby
Standby
Toggling OE# (low to high to low) updates the status register. T his can
be done in place of issuing the Read Status Register command.
Repeat for s ubsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full stat us is checked.
If an error is detected, clear the status register before attempting retry
or other error recov ery.
0
1
1
0
1
0
1
0
Command
Setup Byte/
Word P rogram
Byte/Word
Program
Comments
Data = 40H
Addr = Location to Be Programmed
Data = Data to Be Programmed
Addr = Location to Be Programmed
Check SR. 7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check SR. 3
1 = Programming to Voltage Error
Detect
Check SR. 4
1 = Programming Error
Read
(Note 1) S tatus Regis ter Data
Standby
Check SR. 1
1 = Device Protect Detect
RP# = V
IH
, Block Lock-Bit Is Set
Only required for systems
implemeting lock-bit configuration.
Datasheet
51
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 19: Program Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
SR.7 =
SR.2 = Programming Completed
Write D0H
Programming Resumed
Wri te FFH
Read Array Data
1
1
0
0
Bus
Operation Command Comments
Write Program
Suspend Data = B0H
Addr = X
Read Status Register Data
Addr = X
Standby Check SR.7
1 - WSM Ready
0 = WSM Busy
Standby Check SR.6
1 = Programming Suspended
0 = Programming Completed
Read Read array locations other
than that being programmed.
Wri te FFH
Read Data Array
Done Reading
Yes
No
Write Read Array Data = FFH
Addr = X
Write Program
Resume Data = D0H
Addr = X
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
52
Figure 20: Block Erase Flowchart
Start
Read
Status Register
SR.7 =
Erase Flas h
Block(s) Complete
0
1
Fu ll S tatus
Check if Desired
Suspend Erase
Issue Single Block Erase
Command 20H, Block
Address
Suspend
Erase Loop
Write Confirm D0H
Bl oc k Address
Yes
No
Bus
Operation Command Comments
Write Erase Block Data = 20H
Addr = Block Address
Write (Note 1) Erase
Confirm Data = D0H
Addr = Block Address
Read
Status regis ter data
With the dev ice enabled,
OE# low updates S R
Addr = X
Standby Check SR.7
1 = WSM Ready
0 = WSM B usy
1. The Erase Conf irm byte must follow Er ase Setup.
This device does not suppor t erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Full status check can be done after all erase and write
sequenc es complete. Write FFH after the las t operation to
reset the device to read array mode.
Datasheet
53
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 21: Block Erase Su spend/Resume Flowchart
Start
Wr ite B0H
Read Status Reg i ster
SR.7 =
SR.6 = Block Erase Com p l eted
Read or Program?
Done?
Wr ite D0H
Block Erase Resu m ed
Write FFH
Read Array Data
Program
Program
Loop
Read Array
Data
Read
No
Yes
1
1
0
0
Bus
Operation Command Comments
Write Erase Suspen d Data = B0H
Addr = X
Read Status Register Data
Addr = X
Standby Check SR.7
1 - WSM Ready
0 = WSM Busy
Standby Check SR.6
1 = Block Erase Suspended
0 = Block Erase Com pleted
Write Erase Resume Data = D0H
Addr = X
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
54
Figure 22: Set Block Lock-Bit Flowchart
Start
Write 60H,
Block Address
Write 01H,
Block Address
Read Status Register
SR. 7 =
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
1
0
Command
Set Block Lock-Bit
Setup
Comments
Data = 60H
Addr =Block Address
Read Status Register
Data (See Above)
Voltage Range ErrorSR. 3 = 1
0
Command Sequence
Error
SR .4 ,5 = 1
0
Set Lock-Bit ErrorSR. 4 = 1
0
Set Lock-Bit
Successful
Bus
Operation
Standby
Command Comments
Check SR.3
1 = Programming Voltage Error
Detect
SR.5, SR.4 a nd SR. 3 are only c lear ed by the Cl ear Stat us Regis ter
command, in cases where multiple lock-bits are set before full status is
checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Standby Check SR.4, 5
Both 1 = Comm and Sequen ce
Error
Standby Check SR.4
1 = Set Lock-Bit Error
Write Set Block Lock-Bit
Confirm Data = 01H
Addr = Block Address
Standby
Repeat for subsequent lock-bit operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operati on to place devi ce in read
array mode.
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register Data
Datasheet
55
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 23: Clear Lock-Bit Flowchart
Start
Write 60H
Write D0H
Read Status Register
SR.7 =
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Write
Standby
Write FFH af te r the clear lock-bit s opera tion to place dev ice in read
array mode.
Bus
Operation
Standby
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.
If an error is detected, clear the stat us register before attempting retry
or other error recover y.
1
0
Command
Clear Block
Lock -B its Set up
Clear Bl ock or
Lock-Bits Confirm
Comments
Data = 60H
Addr = X
Data = D0H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check SR. 3
1 = Programm in g Vol tag e Error
Detect
Read Status Register
Data (See Above)
Voltage Range ErrorSR.3 = 1
0
Command Sequence
Error
SR.4,5 = 1
0
Clear Block Lock-Bi ts
Error
SR.5 = 1
0
Read Status Register Data
Standby Check SR.4, 5
Both 1 = Com m and Se quen ce
Error
Standby Check SR.5
1 = Clear Block Lock-Bi ts Error
Clear Block Lock-Bits
Successful
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
56
Figure 24: Protection Register Programming Flowchart
Start
Write C0H
(Protection Reg.
Program Setup)
Write Protect. Register
Address/Data
Read Status Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read Status Register
Data (See Above)
V
PEN
Range Error
Protection Register
Programming Er ror
Attempted Program to
Locked Register -
Aborted
Program Successful
SR.3, SR.4 =
SR.1, SR.4 =
SR.1, SR.4 =
FULL STAT US CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode
.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command
,
in cases of multiple protection register program operations before full status is
checked.
If an error is detected, clear the status register before attempting retry or othe
r
error recovery.
No
Yes
1, 1
0,1
1,1
Command
Protection Program
Setup
Protection Program
Comments
Data = C0H
Data = Data to Program
Addr = Location to Program
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
SR.1 SR.3 SR.4
0 1 1 V
PEN
Low
0 0 1 Prot. Reg.
Prog. Error
1 0 1 Register
Locked:
Aborted
Read Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby
Datasheet
57
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
13.0 Common Flash Interface
The CFI specification outlines device and host system software interrogation handshake
which allows specific vendor-specified software algorithms to be used for entire families
of devices. This allows device independent, JEDEC ID-independent, and forward- and
backward-compatible software support for the specified flash device families. It allows
flash vendors to standardize their existing interfaces for long-term compatibility.
This section defines the data structure or database” returned by the (CFI) Query
command. System software should parse this structure to gain critical information such
as block size, density, x8/x16, and electrical specifications. Once this information has
been obtained, the software will know which command sets to use to enable flash
writes, block erases, and otherwise control the flash component. The Query is part of
an overall specification for multiple command set and control interface descriptions
called CFI.
13.1 Query Structure Output
The Query “database” allows system software to gain information for controlling the
flash component. This section describes the device’s CFI-compliant interface that allows
the host system to access Query data.
Query data are always presented on the lowest-order data outputs (D[7:0]) only. The
numerical offset value is the address relative to the maximum bus width supported by
the device. On this family of devices, the Query table device starting address is a 10h,
which is a word address for x16 devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in
ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant
device outputs 00h data on upper bytes. Thus, the device outputs ASCII “Q” in the low
byte (D[7:0]) and 00h in the high byte (D[15:8]).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode.
Table 35: Summary of Query Structur e Ou tput as a Function of Device and Mode
Device
Type/
Mode
Query start location in
maximum device bus
width addresses
Query da ta with maximum device
bus width addressing Query data with byte addressing
Hex
Offset Hex Code ASCII
Value Hex
Offset Hex Code ASCII
Value
x16 device 10h 10: 0051 “Q” 20: 51 “Q”
x16 mode 11: 0052 “R” 21: 00 “Null”
12: 0059 “Y” 22: 52 “R”
x16 device 20: 51 “Q”
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
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58
13.2 Query Structure Overview
The Query command causes the flash component to display the Common Flash
Interface (CFI) Query structure or “database.” The structure sub-sections and address
locations are summarized below. See AP-646 Common Flash Interface (CFI) and
Command Sets (order number 292204) for a full description of CFI.
The following sections describe the Query structure sub-sections in detail.
x8 mode N/A(1) N/A(1) 21: 51 “Q”
22: 52 “R”
Note:
1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in
x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable"
for x8-configured devices.
Table 36: Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Byte Addressing
Offset Hex Code Value Offset Hex Code Value
A15–A0 D15–D0A7–A0 D7–D0
0010h 0051 “Q” 20h 51 “Q”
0011h 0052 “R 21h 51 “Q”
0012h 0059 “Y” 22h 52 “R
0013h P_IDLO PrVendor 23h 52 “R
0014h P_IDHI ID # 24h 59 “Y”
0015h PLO PrVendor 25h 59 “Y”
0016h PHI TblAdr 26h P_IDLO PrVendor
0017h A_IDLO AltVendor 27h P_IDLO PrVendor
0018h A_IDHI ID # 28h P_IDHI ID #
... ... ... ... ... ...
Table 35: Summary of Query Structure Output as a Function of Device and Mode
Device
Type/
Mode
Query start location in
maximum device bus
width addresses
Query data with maximum devi ce
bus width addressing Query data with byt e addressing
Hex
Offset Hex Code ASCII
Value Hex
Offset Hex Code ASCII
Value
Table 37: Query Structure
Offset Sub-Section Name Description Notes
00h Identification Code Manufacturer Code 1
01h Identification Code Device Code 1
(BA+2)h(2) Block Status Register Block-Specific Information 1,2
04-0Fh Reserved Reserved for Vendor-Specific Information 1
10h CFI Query Identification String Reserved for Vendor-Specific Information 1
1Bh System Interface Information Command Set ID and Vendor Data Offset 1
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
13.3 Block Status Re gister
The Block Status Register indicates whether an erase operation completed successfully
or whether a given block is locked or can be accessed for flash program/erase
operations.
13.4 CFI Query Identific ation String
The CFI Query Identification String provides verification that the component supports
the Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
27h Device Geometry Definition Flash Device Layout 1
P(3) Primary Numonyx-Specific Extended
Query Table
Vendor-Defined Additional Information Specific to
the Primary Vendor Algorithm 1,3
Notes:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is
128 KB).
3. Offset 15 defines “P” which points to the Primary Numonyx-Specific Extended Query Ta b l e .
Table 37: Qu e ry Structure
Offset Sub-Section Name Description Notes
Table 38: Block Status Register
Offset Length Description Address Value
(BA+2)h(1) 1
Block Lock Status Register BA+2: --00 or --01
BSR.0 Block Lock Status
0 = Unlocked
1 = Locked
BA+2: (bit 0): 0 or 1
BSR 1–15: Reserved for Future Use BA+2: (bit 1–15): 0
Note:
1. BA = The beginning location of a Block Address (i.e., 010000h is block 1’s (64-KW block) beginning location in word
mode).
Table 39: CFI Identification
Offset Length Description Add. Hex
Code Value
10h 3 Query-unique ASCII string “QRY”
10 --51 “Q”
11: --52 “R
12: --59 “Y”
13h 2 Primary vendor command set and control interface ID code. 13: --01
16-bit ID code for vendor-specified algorithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --31
16: --00
17h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
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13.5 Sys tem Interface Information
The following device information can optimize system interface software.
13.6 Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 40: System Inte rface Informa tion
Offset Length Description Add. Hex
Code Value
1Bh 1
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1B: --27 2.7 V
1Ch 1
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1C: --36 3.6 V
1Dh 1
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1D: --00 0.0 V
1Eh 1
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1E: --00 0.0 V
1Fh 1 n” such that typical single word program time-out = 2n µs 1F: --06 64 µs
20h 1 “n” such that typical max. buffer write time-out = 2n µs 20: --07 1 128 µs 1
21h 1 “n” such that typical block erase time-out = 2n ms 21: --0A 1 s
22h 1 “n” such that typical full chip erase time-out = 2n ms 22: --00 NA
23h 1 “n” such that maximum word program time-out = 2n times typical 23: --02 256 µs
24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --03 1024µs
25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --02 4 s
26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA
Notes:
1. The value is 32 Bytes buffer write typical time out
Table 41: Device Geometry Definition (Sheet 1 of 2)
Offset Length Description Code See Table Below
27h 1 “n” such that device size = 2n in number of bytes 27:
28h 2 Flash device interface: x8 async x16 async x8/x16 async 28: --02 x8/
x16
28:00,29:00 28:01,29:00 28:02,29:00 29: --00
2Ah 2 “n” such that maximum number of bytes in write buffer = 2n2A: --05 132 1
2B: --00
2Ch 1
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or more
contiguous same-size erase blocks
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
2C: --01 1
Notes:
1. The value is 32 Bytes buffer write typical time out
Datasheet
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
13.7 Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific
Extended Query table specifies this and other similar information.
2Dh 4
Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
Notes:
1. Compatible with J3 130nm device (32 bytes). J3 65 nm SBC device supports up to maximum 256 words (x16 mode)/
256 bytes (x8 mode) buffer write.
Table 42: Device Geometry: Address Codes
Address 32 Mbit 64 Mbit 128 M bit
27: --16 --17 --18
28: --02 --02 --02
29: --00 --00 --00
2A:--05--05--05
2B:--00--00--00
2C:--01--01--01
2D: --1F --3F --7F
2E: --00--00--00
2F: --00--00--00
30: --02 --02 --02
Tabl e 41: Device Geometry Definiti on (Sheet 2 of 2)
Offset Len gth Descript ion Code See Table Bel ow
Table 43: Primary Vendor-Specific E xtended Query (Sheet 1 of 2)
Offset(1)
P = 31h Length Description
(Optional Flash Features and Commands) Add. Hex
Code Value
(P+0)h 3 Primary extended query table 31: --50 “P”
(P+1)h Unique ASCII string “PRI” 32: --52 “R”
(P+2)h 33: --49 “I”
(P+3)h 1 Major version number, ASCII 34: --31 “1”
(P+4)h 1 Minor version number, ASCII 35: --31 “1”
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
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62
(P+5)h
(P+6)h
(P+7)h
(P+8)h
4Optional feature and command support (1=yes, 0=no)
Undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of optional features follows at
the end of the bit-30 field.
36: --CE
37: --00
38: --00
39: --00
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 1 Yes
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant Individual block locking supported bit 5 = 0 No
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Page-mode read supported bit 7 = 1 Yes
bit 8 Synchronous read supported bit 8 = 0 No
bit9 Simultaneous Operation Supported bit 9 = 0 No
bit 30 CFI Link(s) to follow (32, 64, 128 Mb) bit 30 = 0 No
bit 31 Another “Optional Feature” field to follow bit 31 = 0 No
(P+9)h 1
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0” 3A: --01
bit 0 Program supported after erase suspend bit 0 = 1 Yes
(P+A)h
(P+B)h 2
Block Status Register mask 3B: --01
bits 2–15 are Reserved; undefined bits are “0” 3C: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 0 No
(P+C)h 1
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
3D: --33 3.3 V
(P+D)h 1
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
3E: --00 0.0 V
Note:
1. Setting this bit, will lead to the extension of the CFI table.
Table 43: Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Offset(1)
P = 31h Length Description
(Optional Flash Features and Commands) Add. Hex
Code Value
Datasheet
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 44: P r otecti on Regi st er Inf or mation
Offset(1)
P = 31 h Length Description
(Optional Flash Features and Commands) Add. Hex
Code Value
(P+E)h 1 Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available 3F: --01 01
(P+F)h
(P+10)h
(P+11)h
(P+12)h
4
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user-programmable. Bits 0-15 point
to the protection register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
40:
41:
42:
43:
--80
--00
--03
--03
80h
00h
8bytes
8bytes
Note:
1. The variable P is a pointer which is defined at CFI offset 15h.
Table 45: Burst Read Information
Offset(1)
P = 31h Length Description
(Optional Flash Fe atures and Commands) Add. Hex
Code Value
(P+13)h 1
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of read-
page bytes. See offset 28h for device word width to determine page-
mode data output width. 00h indicates no read page buffer.
44: --04 16 byte
(P+14)h 1 Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability. 45: --00 0
(P+15)h 1
Synchronous Mode Read Capability Configuration 1
Bits 3-7 = Reserved
bits 0-2 = “n” such that 2n+1 HEX value represents the maximum
number of continuous synchronous burst reads when the device is
configured for its maximum word width. A value of 07h indicates that
the device is capable of continuous linear bursts until that will output
data until the internal burst counter reaches the end of the device’s
burstable address space. This field’s 3-bit value can be written directly
to the Read Configuration Register Bits 0-2 if the device is configured for
its maximum word width. See offset 1Fh for word width to determine
the burst data output width.
46: --00 n/a
(P+16h)h 1 Synchronous Mode Read Capability Configuration 2 47: --00 n/a
(P+45h)h 1 J3C mark for VIL fix for customers 76: --01 01
Note:
1. The variable P is a pointer which is defined at CFI offset 15h.
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
64
Appendix A Additional Information
Orde r Number Docume nt/Too l
316577 Numonyx® Embedded Flash Memory (J3 v D); 28F256J3D, 28F128J3D, 28F640J3D,
28F320J3D Specification Update
298136 Numonyx® Persistent Storage Manager (PSM) User’s Guide Software Manual
292204 AP-646 Common Flash Interface (CFI) and Command Sets
319942 Numonyx® Embedded Flash Memory (J3-65nm_256-Mbit_MLC Datasheet)
Note: Contact your local Numonyx or distribution sales office or visit the Numonyx home page http://www.numonyx.com for
technical documentation, tools, or the most current information on Numonyx® Embedded Flash Memory (J3 65 nm)
Single Bit per Cell (SBC) .
Datasheet
65
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Appendix B Ordering Information
Note: The last digit is randomly assigned to cover packing media and/or features or other
specific configuration.
Note: For further information on ordering products or for product part numbers, go to:http://
www.numonyx.com/en-US/MemoryProducts/Pages/PartNumberLookup.aspx.
Figur e 25: Decod er f or 32-, 64-, 128-Mbit
l
Table 46: Valid Combina tions
32-Mbit 64-Mbit 128-Mbit
JS28F320J3F75* JS28F640J3F75* JS28F128J3F75*
RC28F320J3F75* RC28F640J3F75* RC28F128J3F75*
PC28F320J3F75* PC28F640J3F75* PC28F128J3F75*
PC28F320J3F75*
Packa ge
JS = Pb-Free 56 -TSOP
RC = 64-Ball Easy B GA
PC = 64-Ball Pb -Free Easy BGA
P ro duct Line Designator
Numonyx® Flash Memory
Device De nsity
128 = 128-Mbit
640 = 64 -Mbit
320 = 32 -Mbit
Access Speed
75ns
Lithography
F = 65nm
Voltage (VCC/VPEN)
3 = 3 V /3 V
Product Family
J = Numonyx®
Flash Memory
Device Features *
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
66
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set
forth herein.
Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.