512Kx36 & 1Mx18 Flow-Through NtRAMTM
- 12 - Rev 1.0
July 2005
K7M161835B
K7M163635B
AC TIMING CHARACTERISTICS
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All addre ss inpu ts must mee t the sp eci fied setup and hold time s f or all risi ng clock(CLK) edges whe n AD V is sam pled low an d CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is de fined by WE low havin g been regi sterd into the de vice at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC.
The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. paramete r(wor st case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.
PARAMETER SYMBOL -65 UNIT
MIN MAX
Cycle Tim e tCYC 7.5 - ns
Clock Access Time tCD -6.5ns
Output Enable to Data Valid tOE -3.5 ns
Clock High to Output Low-Z tLZC 2.5 - ns
Output Hold from Clock High tOH 2.5 - ns
Output Enable Low to Output Low-Z tLZOE 0-ns
Output Enable High to Output High-Z tHZOE -3.5
ns
Clock High to Output High-Z tHZC -3.8ns
Clock High Pulse Width tCH 2.5 - ns
Clock Low Pulse Width tCL 2.5 - ns
Address Setup to Clock High tAS 1.5 -ns
CKE Setup to Clock High tCES 1.5 -ns
Data Setup to Clock High tDS 1.5 -ns
Write Setup to Clock High (WE, BWX)tWS 1.5 -ns
Address Advance Setup to Clock High tADVS 1.5 -ns
Chip Select Setup to Clock High tCSS 1.5 -ns
Address Hold from Clock High tAH 0.5 - ns
CKE Hold from Clock High tCEH 0.5 - ns
Data Hold from Clock High tDH 0.5 - ns
Write Hold from Clock High (WE, BWX)tWH 0.5 - ns
Address Advance Hold from Clock High tADVH 0.5 - ns
Chip Select Hold from Clock High tCSH 0.5 - ns
ZZ High to Power Down tPDS 2 - cycle
ZZ Low to Power Up tPUS 2 - cycle
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
353Ω / 1538Ω 5pF*
+3.3V for 3.3V I/O
319Ω / 1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50ΩVL=1.5V for 3.3V I/O
VDDQ/2 for 2 .5V I/O
/+2.5V for 2.5V I/O