SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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1
DOpen Drain Power-On Reset With 200 ms
Delay (TPS777xx)
DOpen Drain Power Good (TPS778xx)
D750-mA Low-Dropout Voltage Regulator
DAvailable in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed
Output and Adjustable Versions
DDropout Voltage to 260 mV (Typ) at 750 mA
(TPS77x33)
DUltralow 85 mA Typical Quiescent Current
DFast Transient Response
D2% Tolerance Over Specified Conditions for
Fixed-Output Versions
D8-Pin SOIC and 20-Pin TSSOP PowerPAD
(PWP) Package
DThermal Shutdown Protection
description
TPS777xx and TPS778xx are designed to have a
fast transient response and be stable with a 10 µF
low ESR capacitor. This combination provides
high performance at a reasonable cost.
TA − Free-Air Temperature − °C
−40 0 20 120
103
−60 40 60 80 100
− Dropout Voltage − mV
VDO
TPS77x33
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
102
101
100
10−1
10−2 −20 140
IO = 750 mA
IO = 10 mA
IO = 0
Co = 10 µF
t − Time − µs
TPS77x33
LOAD TRANSIENT RESPONSE
I − Output Current − mA
OVO− Change in∆
Output Voltage − mV
500
0
604020 80 100 140120 160 180 200
0
0
50
−50
1000
Co = 2x47 µF
ESR = 1/2x100 mΩ
VO = 3.3 V
VI = 4.3 V
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&"!"# " %)(&!&$"% )(# ( (#% "! (.$% %#'(% %$,$#, $##$/-
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Copyright 1999 − 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
1
2
3
4
8
7
6
5
GND
EN
IN
IN
RESET/PG
FB/NC
OUT
OUT
D PACKAGE
(TOP VIEW)
NC − No internal connection
GND/HSINK
GND/HSINK
GND
NC
EN
IN
IN
NC
GND/HSINK
GND/HSINK
GND/HSINK
GND/HSINK
NC
NC
RESET/PG
FB/NC
OUT
OUT
GND/HSINK
GND/HSINK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWP PACKAGE
(TOP VIEW)
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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2
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 260 mV at an output
current of 750 mA for the TPS77x33) and is directly proportional to the output current. Additionally, since the PMOS pass
element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 µA over
the full range of output current, 0 mA to 750 mA). These two key specifications yield a significant improvement in operating
life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable)
shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.
The RESET output of the TPS777xx initiates a reset in microcomputer and microprocessor systems in the event of an
undervoltage condition. An internal comparator in the TPS777xx monitors the output voltage of the regulator to detect an
undervoltage condition on the regulated output voltage.
Power good (PG) of the TPS778xx is an active high output, which can be used to implement a power-on reset or a
low-battery indicator.
The TPS777xx and TPS778xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable
version (programmable over the range of 1.5 V to 5.5 V for the TPS77701 option and 1.2 V to 5.5 V for the TPS77801 option).
Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS777xx and
TPS778xx families are available in 8-pin SOIC and 20-pin PWP packages.
AVAILABLE OPTIONS
TJ
OUTPUT
VOLTAGE
(V) PACKAGED DEVICES
TJ
TYP TSSOP
(PWP) SOIC
(D)
3.3 TPS77733PWP TPS77833PWP TPS77733D TPS77833D
2.5 TPS77725PWP TPS77825PWP TPS77725D TPS77825D
1.8 TPS77718PWP TPS77818PWP TPS77718D TPS77818D
−40
°
C to 125
°
C
1.5 TPS77715PWP TPS77815PWP TPS77715D TPS77815D
−40°C to 125°C
Adjustable
1.5 V to 5.5 V TPS77701PWP — TPS77701D —
Adjustable
1.2 V to 5.5 V — TPS77801PWP — TPS77801D
The TPS77x01 is programmable using an external resistor divider (see application information). The D and PWP
packages are available taped and reeled. Add an R suffix to the device type (e.g., TPS77701DR).
(1) See application information section for capacitor selection details.
RESET/
PG
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
0.1 µF
RESET/PG
VO
10 µF
+Co(1)
Figure 1. Typical Application Configuration for Fixed Output Options
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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3
functional block diagram—adjustable version
200 ms Delay
(for RESET Option)
_
+
Vref = 1.1834 V
OUT
FB/NC
EN
GND
PG or RESET
_
+
IN
External to the device
R1
R2
functional block diagram—fixed-voltage version
_
+
Vref = 1.1834 V
OUT
EN
GND
R1
R2
PG or RESET
_
+
IN
200 ms Delay
(for RESET Option)
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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4
Terminal Functions
SOIC Package (TPS777xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 2 I Enable input
FB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options)
GND 1 Regulator ground
IN 3, 4 IInput voltage
OUT 5, 6 ORegulated output voltage
RESET 8 O RESET output
TSSOP Package (TPS777xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 5 I Enable input
FB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options)
GND 3 Regulator ground
GND/HSINK 1, 2, 9, 10, 11,
12, 19, 20 Ground/heatsink
IN 6, 7 I Input
NC 4, 8, 17, 18 No connect
OUT 13, 14 ORegulated output voltage
RESET 16 O RESET output
SOIC Package (TPS778xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 2 I Enable input
FB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options)
GND 1 Regulator ground
IN 3, 4 IInput voltage
OUT 5, 6 ORegulated output voltage
PG 8 O PG output
TSSOP Package (TPS778xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 5 I Enable input
FB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options)
GND 3 Regulator ground
GND/HSINK 1, 2, 9, 10, 11,
12, 19, 20 Ground/heatsink
IN 6, 7 I Input
NC 4, 8, 17, 18 No connect
OUT 13, 14 ORegulated output voltage
PG 16 O PG output
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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5
TPS777xx RESET timing diagram
(1) Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconducto
r
symbology.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
V
I
Vres(1) Vres
t
t
t
VO
Threshold
Voltage
RESET
Output 200 ms
Delay 200 ms
Delay
Output
Undefined
Output
Undefined
VIT+(2)
VIT−(2) VIT−(2)
VIT+(2)
Less than 5% of the
output voltage
(2) V
IT
−Trip voltage is typically 5% lower than the output voltage (95%V
O
) V
IT−
to V
IT+
is the hysteresis voltage.
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)(1)
Input voltage range(2), VI −0.3 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN −0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum RESET voltage (TPS777xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum PG voltage (TPS778xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO (OUT, FB) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 − FREE-AIR TEMPERATURES
PACKAGE AIR FLOW
(CFM) TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D
0568 mW 5.68 mW/°C312 mW 227 mW
D
250 904 mW 9.04 mW/°C497 mW 361 mW
DISSIPATION RATING TABLE 2 − FREE-AIR TEMPERATURES
PACKAGE AIR FLOW
(CFM) TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
PWP§
02.9 W 23.5 mW/°C1.9 W 1.5 W
PWP§
300 4.3 W 34.6 mW/°C 2.8 W 2.2 W
PWP¶
03 W 23.8 mW/°C1.9 W 1.5 W
PWP¶
300 7.2 W 57.9 mW/°C4.6 W 3.8 W
(1) This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5 in × 5 in PCB, 1 oz.
copper, 2 in × 2 in coverage (4 in2).
(2) This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5 in × 2 in PCB, 1 oz.
copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more
information, refer to TI technical brief SLMA002.
recommended operating conditions MIN MAX UNIT
Input voltage, VI(1) 2.7 10 V
Output voltage range, VO
TPS77701 1.5 5.5
V
Output voltage range, VOTPS77801 1.2 5.5 V
Operating junction temperature, TJ−40 125 °C
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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7
electrical characteristics over recommended operating temperature range (TJ = −40°C to 125°C),
VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPS77701
1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C VO
TPS77701 1.5 V ≤ VO ≤ 5.5 V, 0.98VO1.02VO
TPS77801
1.2 V ≤ VO ≤ 5.5 V, TJ = 25°C VO
TPS77801 1.2 V ≤ VO ≤ 5.5 V, 0.98VO1.02VO
TPS77x15
TJ = 25°C, 2.7 V < VIN < 10 V 1.5
Output voltage (10 A to 750 mA load)
TPS77x15 TJ = −40°C to 125°C, 2.7 V < VIN < 10 V 1.470 1.530
V
Output voltage (10 µA to 750 mA load)
TPS77x18
TJ = 25°C, 2.8 V < VIN < 10 V 1.8 V
TPS77x18 TJ = −40°C to 125°C, 2.8 V < VIN < 10 V 1.764 1.836
TPS77x25
TJ = 25°C, 3.5 V < VIN < 10 V 2.5
TPS77x25 TJ = −40°C to 125°C, 3.5 V < VIN < 10 V 2.450 2.550
TPS77x33
TJ = 25°C, 4.3 V < VIN < 10 V 3.3
TPS77x33 TJ = −40°C to 125°C, 4.3 V < VIN < 10 V 3.234 3.366
Quiescent current (GND current)
10 µA < IO < 750 mA, TJ = 25°C 85
A
Quiescent current (GND current) IO = 750 mA 125 µA
Output voltage line regulation (∆VO/VO)VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.01 %/V
Load regulation 3 mV
Output noise voltage (TPS77x18) BW = 200 Hz to 100 kHz, Co = 10 µF,
TJ = 25°C, IC = 750 µA54 µVrms
Output current limit VO = 0 V 1.2 1.7 2 A
Thermal shutdown junction temperature 150 °C
Standby current
EN = VI, TJ = 25°C,
2.7 V < VI < 10 V 1µA
Standby current EN = VI, 2.7 V < VI < 10 V 10 µA
FB input current TPS77x01 FB = 1.5 V 2 nA
High level enable input voltage 1.7 V
Low level enable input voltage 0.9 V
Power supply ripple rejection f = 1 KHz, Co = 10 µF,
TJ = 25°C60 dB
Minimum input voltage for valid RESET IO(RESET) = 300 µA 1.1 V
Trip threshold voltage VO decreasing 92 98 %VO
Reset
(TPS777xx)
Hysteresis voltage Measured at VO0.5 %VO
Reset
(TPS777xx
)
Output low voltage VI = 2.7 V, IO(RESET) = 1 mA 0.15 0.4 V
Leakage current V(RESET) = 5 V 1µA
RESET time-out delay 200 ms
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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8
electrical characteristics over recommended operating temperature range (TJ = −40°C to 125°C),
VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input voltage for valid PG IO(PG) = 300 µA 1.1 V
PG
Trip threshold voltage VO decreasing 92 98 %VO
PG
(TPS778xx)
Hysteresis voltage Measured at VO0.5 %VO
(TPS778xx)
Output low voltage VI = 2.7 V, IO(PG) = 1 mA 0.15 0.4 V
Leakage current V(PG) = 5 V 1µA
Input current (EN)
EN = 0 V −1 0 1
A
Input current (EN)EN = VI−1 1 µA
TPS77733
IO = 750 mA, TJ = 25°C 260
Dropout voltage (1)
TPS77733 IO = 750 mA, 427
mV
Dropout voltage (1)
TPS77833
IO = 750 mA, TJ = 25°C 260 mV
TPS77833 IO = 750 mA, 427
(1) IN voltage equals VO(typ) − 100 mV; TPS77x01 output voltage set to 3.3 V nominal with external resistor divider. TPS77x15, TPS77x18, and
TPS77x25 dropout voltage limited by input voltage range limitations (i.e., TPS77x33 input voltage needs to drop to 3.2 V for purpose of this
test).
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VO
Output voltage
vs Output current 2, 3, 4
VOOutput voltage vs Free-air temperature 5, 6, 7
Ground current vs Free-air temperature 8
Power supply ripple rejection vs Frequency 9
Output spectral noise density vs Frequency 10
ZoOutput impedance vs Frequency 11
VDO
Dropout voltage
vs Input voltage 12
VDO Dropout voltage vs Free-air temperature 13
Input voltage (min) vs Output voltage 14
Line transient response 15, 17
Load transient response 16, 18
VOOutput voltage vs Time 19
Equivalent series resistance (ESR) vs Output current 21 − 24
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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9
TYPICAL CHARACTERISTICS
Figure 2
IO − Output Current − A
TPS77x33
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.2830
3.2815
3.2800 0.125 0.375
3.2825
3.2820
3.2810
0.25
3.2835
0
− Output Voltage − V
VO
3.2805
0.5 0.675 0.75
VI = 4.3 V
TA = 25°C
Figure 3
IO − Output Current − A
1.4975
1.4960
1.4950
1.4970
1.4965
1.4955
1.4985
− Output Voltage − V
VO
TPS77x15
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.4980
0.125 0.3750.250 0.5 0.675 0.75
VI = 2.7 V
TA = 25°C
Figure 4
0.125 0.3750.250 0.5 0.675 0.75
IO − Output Current − A
TPS77x25
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
2.4955
2.4940
2.4920
2.4950
2.4945
2.4935
2.4960
− Output Voltage − V
VO
2.4930
2.4925
VI = 3.5 V
TA = 25°C
Figure 5
TA − Free-Air Temperature − °C
TPS77x33
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
− Output Voltage − V
VO
3.31
3.28
3.25 −40 0
3.30
3.29
3.27
−20 100 140
3.32
−60 120
3.26
20 40 60 80
VI = 4.3 V
IO = 750 mA IO = 1 mA
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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10
TYPICAL CHARACTERISTICS
Figure 6
TA − Free-Air Temperature − °C
TPS77x15
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
− Output Voltage − V
VO
1.515
1.500
1.485 −40 0
1.510
1.505
1.495
−20 100−60 120
1.490
20 40 60 80
VI = 2.7 V
IO = 750 mA
IO = 1 mA
140
Figure 7
TA − Free-Air Temperature − °C
TPS77x25
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
− Output Voltage − V
VO
−40 0−20 100−60 12020 40 60 80
2.515
2.500
2.480
2.510
2.505
2.495
2.490
2.485
VI = 3.5 V
IO = 750 mA
IO = 1 mA
Figure 8
TA − Free-Air Temperature − °C
TPS77xxx
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
Ground Current − Aµ
−40 0−20 100−60 12020 40 60 80 140
IO = 500 mA
100
95
90
85
80
75
IO = 1 mA
IO = 750 mA
Figure 9
100k10k
PSRR − Power Supply Ripple Rejection − dB
f − Frequency − Hz
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY
70
60
50
40
30
20
10
0
−10
TPS77x33
90
80
1k10010 1M
VI = 4.3 V
Co = 10 µF
TA = 25°C
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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11
TYPICAL CHARACTERISTICS
Figure 10
TPS77x33
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
f − Frequency − Hz
102103104105
10−5
10−6
10−8
10−7
IO = 7 mA
IO = 750 mA
VI = 4.3 V
Co = 10 µF
TA = 25°C
V HzOutput Spectral Noise Density − µ
Figure 11
f − Frequency − kHz
− Output Impedance −ZoΩ
101102105106
0
10−1
10−2 104
103
IO = 1 mA
IO = 750 mA
VI = 4.3 V
Co = 10 µF
TA = 25°C
TPS77x33
OUTPUT IMPEDANCE
vs
FREQUENCY
Figure 12
VI − Input Voltage − V
600
300
034
500
400
200
3.52.5
− Dropout Voltage − mV
100
4.5 5
VDO
TA = 125°C
TA = −40°C
TA = 25°C
IO = 750 mA
TPS77x01
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
Figure 13
TA − Free-Air Temperature − °C
−40 0 20 120
103
−60 40 60 80 100
− Dropout Voltage − mV
VDO
TPS77x33
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
102
101
100
10−1
10−2 −20 140
IO = 750 mA
IO = 10 mA
IO = 0
Co = 10 µF
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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12
TYPICAL CHARACTERISTICS
Figure 14
3
2.7
21.5 1.75 2 2.25 2.5 2.75
− Input Voltage (Min) − V
INPUT VOLTAGE (MIN)
vs
OUTPUT VOLTAGE
4
3 3.25 3.5
VI
VO − Output Voltage − V
IO = 0.75 A
TA = −40°C
TA = 125°C
TA = 25°C
Figure 15
VO− Change in
10
0
3.7
2.7
TPS77x15
LINE TRANSIENT RESPONSE
VI
t − Time − µs
0604020 80 100 140120 160 180 200
− Input Voltage − V
∆
Output Voltage − mV
Co = 10 µF
TA = 25°C
−10
Figure 16
t − Time − µs
TPS77x15
LOAD TRANSIENT RESPONSE
I − Output Current − mA
OVO− Change in∆
Output Voltage − mV
500
0
604020 80 100 140120 160 180 200
0
0
50
−50
1000
Co = 2x47 µF
ESR = 1/2x100 mΩ
VO = 1.5 V
VI = 2.7 V
Figure 17
TPS77x33
LINE TRANSIENT RESPONSE
t − Time − µs
VO− Change in VI− Input Voltage − V
∆
Output Voltage − mV
5.3
604020 80 100 140120 160 180 200
Co = 10 µF
TA = 25°C
0
4.3
10
0
−10
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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13
TYPICAL CHARACTERISTICS
Figure 18
t − Time − µs
TPS77x33
LOAD TRANSIENT RESPONSE
I − Output Current − mA
OVO− Change in∆
Output Voltage − mV
500
0
604020 80 100 140120 160 180 200
0
0
50
−50
1000
Co = 2x47 µF
ESR = 1/2x100 mΩ
VO = 3.3 V
VI = 4.3 V
Figure 19
t − Time − ms
TPS77x33
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
3
2
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 10
VO− Output Voltage − V
0
1
4
Enable Pulse − V
0
Co = 10 µF
IO = 750 mA
TA = 25°C
IN
EN
OUT
+
GND Co
ESR
R
VITo Load
RL
Figure 20. Test Circuit for Typical Regions of Stability (Figures 21 through 24) (Fixed Output Options)
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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14
TYPICAL CHARACTERISTICS
Figure 21
0 125 250 375 500 625
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1)
vs
OUTPUT CURRENT
10
IO − Output Current − mA
1
750
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TA = 25°C
Region of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0.01
Region of Instability
Figure 22
0 125 250 375 500 625 750
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1)
vs
OUTPUT CURRENT
IO − Output Current − mA
ESR − Equivalent Series Resistance − Ω
10
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TJ = 125°CRegion of Stability
Region of Instability
1
0.1
0.01
Region of Instability
Figure 23
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1)
vs
OUTPUT CURRENT
IO − Output Current − mA
0 125 250 375 500 625 750
Region of Instability
Region of Stability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TA = 25°C
ESR − Equivalent Series Resistance − Ω
Region of Instability
10
1
0.1
0.01
Figure 24
ESR − Equivalent Series Resistance − Ω
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1)
vs
OUTPUT CURRENT
IO − Output Current − mA
0 125 250 375 500 625 750
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TJ = 125°CRegion of Stability
Region of Instability
10
1
0.1
0.01
Region of Instability
(1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to Co.
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
www.ti.com
15
APPLICATION INFORMATION
The TPS777xx and TPS778xx families include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an
adjustable regulator, the TPS77x01 (adjustable from 1.5 V to 5.5 V for TPS77701 option and 1.2 V to 5.5 V for TPS77801
option).
device operation
The TPS777xx and TPS778xx feature very low quiescent current, which remains virtually constant even with varying loads.
Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current
through the regulator (IB = IC/β). The TPS777xx and TPS778xx use a PMOS transistor to pass current; because the gate
of the PMOS is voltage driven, operating current is low and invariable over the full load range.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The
resulting drop in β forces an increase in IB to maintain the load. During power up, this translates to large start-up currents.
Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when
the voltage decays below the minimum required for regulation. The TPS777xx and TPS778xx quiescent currents remain
low even when the regulator drops out, eliminating both problems.
The TPS777xx and TPS778xx families also feature a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdown feature is not
used, EN should be tied to ground.
minimum load requirements
The TPS777xx and TPS778xx families are stable even at zero load; no minimum load is required for operation.
FB—pin connection (adjustable version only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output voltage is
sensed through a resistor divider network to close the loop as it is shown in Figure 26. Normally, this connection should
be as short as possible; however, the connection can be made near a critical circuit to improve performance at that point.
Internally, FB connects to a high-impedance wide-bandwidth amplifier and noise pickup feeds through to the regulator
output. Routing the FB connection to minimize/avoid noise pickup is essential.
external capacitor requirements
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improves load transient
response and noise rejection if the TPS777xx or TPS778xx are located more than a few inches from the power supply. A
higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise
times are anticipated.
Like all low dropout regulators, the TPS777xx and TPS778xx require an output capacitor connected between OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR (equivalent
series resistance) must be between 50 mΩ and 1.5 Ω. Capacitor values 10 µF or larger are acceptable, provided the ESR
is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable,
provided they meet the requirements described previously.
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
www.ti.com
16
APPLICATION INFORMATION
external capacitor requirements (continued)
RESET/
PG
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
C1
0.1 µF
RESET/PG
VO
10 µF
+Co
250 kΩ
Figure 25. Typical Application Circuit (Fixed Versions)
programming the TPS77x01 adjustable LDO regulator
The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as shown in
Figure 26. The output voltage is calculated using:
VO+Vref ǒ1)R1
R2Ǔ(
1)
Where:
V
ref
= 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 10-µA divider current. Lower value resistors can be used but of fer
no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the
output voltage error. The recommended design procedure is to choose R2 = 110 kΩ to set the divider current at
approximately 10 µA and then calculate R1 using:
R1 +ǒVO
Vref *1Ǔ R2 (2)
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
4.75 V
UNIT
121
196
226
332
110
110
110
110
kΩ
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIRESET/
PG
OUT
FB / NC
R1
R2
GND
EN
IN
≤0.9 V
≥1.7 V
TPS77x01
Reset or PG Output
0.1 µF250 kΩ
Co
Figure 26. TPS77x01 Adjustable LDO Regulator Programming
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
www.ti.com
17
APPLICATION INFORMATION
reset indicator
The TPS777xx features a RESET output that can be used to monitor the status of the regulator. The internal comparator
monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the RESET
output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left
floating. RESET can be used to drive power-on reset circuitry or as a low-battery indicator. RESET does not assert itself
when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low relative
to its nominal regulated value (refer to timing diagram for start-up sequence).
power-good indicator
The TPS778xx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal
comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value,
the PG output transistor turns on, taking the signal low . The open-drain output requires a pullup resistor. If not used, it can
be left floating. PG can be used to drive power-on reset circuitry or used as a low-battery indicator.
regulator protection
The TPS777xx and TPS778xx PMOS-pass transistors have a built-in back diode that conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input
and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate.
The TPS777xx and TPS778xx also feature internal current limiting and thermal protection. During normal operation, the
TPS777xx and TPS778xx limit output current to approximately 1.7 A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation
resumes.
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
www.ti.com
18
APPLICATION INFORMATION
POWER DISSIPATION AND JUNCTION TEMPERATURE
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be
restricted to 1 2 5 °C under normal operating conditions. This restriction limits the power dissipation the regulator can handle
in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable
dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
PD(max) +TJmax *TA
RqJA
Where:
TJmax is the maximum allowable junction temperature.
TA is the ambient temperature.
RθJA is the thermal resistance junction-to-ambient for the package, and is calculated as
1
derating factor from the dissipation rating tables.
The regulator dissipation is calculated using:
PD+ǒVI*VOǓ IO
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal
protection circuit.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77701D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77701DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77701DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77701DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77701PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77701PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77701PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77701PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77715D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77715DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77715DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77715DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77715PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77715PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77718D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77718DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77718DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77718DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77718PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77718PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77718PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77718PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77725D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77725DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77725PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77725PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77725PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77725PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77733D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77733DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77733DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77733DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77733PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77733PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77733PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77733PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77801D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77801DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77801DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77801DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77801PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77801PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77801PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77801PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77815D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77815DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77815DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77815DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77815PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77815PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77815PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77815PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77818D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77818DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77818PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77818PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77818PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77818PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77825D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77825DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77825DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77825DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77825PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77825PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77825PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77825PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77833D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77833DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77833DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77833DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77833PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 5
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77833PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77833PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS77833PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS77701DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77701PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77715DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77718DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77718PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77725PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77733DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77733PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77801DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77801PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77815DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77815PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77818PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77825DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77825PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS77833DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS77833PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS77701DR SOIC D 8 2500 367.0 367.0 35.0
TPS77701PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77715DR SOIC D 8 2500 367.0 367.0 35.0
TPS77718DR SOIC D 8 2500 367.0 367.0 35.0
TPS77718PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77725PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77733DR SOIC D 8 2500 367.0 367.0 35.0
TPS77733PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77801DR SOIC D 8 2500 367.0 367.0 35.0
TPS77801PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77815DR SOIC D 8 2500 367.0 367.0 35.0
TPS77815PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77818PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77825DR SOIC D 8 2500 367.0 367.0 35.0
TPS77825PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS77833DR SOIC D 8 2500 367.0 367.0 35.0
TPS77833PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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