User's Manual TM V850E/PH2 32-Bit Single-Chip Microcontroller Hardware PD70F3187 PD70F3447 Document No. U16580EE3V1UD00 Date Published January 2007 (c) NEC Electronics Corporation 2007 Printed in Germany NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office. 2 User's Manual U16580EE3V1UD00 * The information in this document is current as of October, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 User's Manual U16580EE3V1UD00 3 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu District, Beijing 100083, P.R.China Tel: 010-8235-1155 http://www.cn.necel.com/ Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel: 0 511 33 40 2-0 Munich Office Werner-Eckert-Strasse 9 81829 Munchen Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Francaise 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 NEC Electronics Shanghai Ltd. Room 2511-2512, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C: Tel: 021-5888-5400 http://www.cn.necel.com/ NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-8175-9600 http://www.tw.necel.com/ NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ NEC Electronics Korea Ltd. 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 http://www.kr.necel.com/ Tyskland Filial Taby Centrum Entrance S (7th floor) 18322 Taby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The Netherlands Tel: 040 265 40 10 G06 4 User's Manual U16580EE3V1UD00 Preface Readers This manual is intended for users who want to understand the functions of the V850E/PH2 (PHOENIX-F). Purpose This manual presents the hardware manual of V850E/PH2. Organization This system specification describes the following sections: Legend * Pin function * CPU function * Internal peripheral function * Flash memory Symbols and notation are used as follows: Weight in data notation : Left is high-order column, right is low order column Active low notation : xxx (pin or signal name is over-scored) or /xxx (slash before signal name) Memory map address: : High order at high stage and low order at low stage Note : Explanation of (Note) in the text Caution : Item deserving extra attention Remark : Supplementary explanation to the text Numeric notation : Binary... XXXX or XXXB Decimal... XXXX Hexadecimal... XXXXH or 0x XXXX Prefixes representing powers of 2 (address space, memory capacity) K (kilo): 210 = 1024 M (mega): 220 = 10242 = 1,048,576 G (giga): 230 = 10243 = 1,073,741,824 User's Manual U16580EE3V1UD00 5 Preface 6 User's Manual U16580EE3V1UD00 Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.1 Internal block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.2 On-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Chapter 2 2.1 2.2 2.3 2.4 2.5 Chapter 3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Pin I/O Circuits and Recommended Connection of Unused Pins . . . . . . . . . . . . . . . 76 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 CPU Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.1 3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.2.3 Floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.3.1 Operating modes outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.3.2 Operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.4.2 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.4.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.4.5 Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.4.6 Peripheral I/O registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.4.7 Programmable peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.4.8 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.4.9 System wait control register (VSWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1) . . . . . . . . . . . . . . . 142 3.4.11 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Chapter 4 Bus Control Function (PD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.1 4.2 4.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.3.1 Chip select control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.4 Bus Cycle Type Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.4.1 Bus cycle type configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.5 Bus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.5.1 Number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.5.2 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.5.3 Endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.5.4 Bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.6 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 4.6.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 User's Manual U16580EE3V1UD00 7 4.7 4.8 4.9 Idle State Insertion Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Bus Priority Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Boundary Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Chapter 5 5.1 Memory Access Control Function (PD70F3187 only) . . . . . . . . . . . . . . . 181 SRAM, External ROM, External I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.1.2 SRAM connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.1.3 SRAM, external ROM, external I/O access . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Chapter 6 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.1 6.2 6.3 6.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.4.1 DMA transfer of A/D converter result registers (ADC0, ADC1) . . . . . . . . . . . . 200 6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1) . . . . . . . . . . . . . . . . . . . . . 204 6.4.3 DMA transfer of serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.4.4 Forcible termination of DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6.5 DMA Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Chapter 7 7.1 7.2 7.3 7.4 7.5 7.6 Chapter 8 8.1 8.2 8.3 8 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Power Save Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 8.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 8.3.2 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Chapter 9 9.1 9.2 9.3 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 219 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Non-maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 7.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 7.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 7.2.3 Non-maskable interrupt status flag (NP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 7.2.4 Edge Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 7.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.3.4 Interrupt control register (PICn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6) . . . . . . . . . . . . . . . . . . . . . . . . 240 7.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7.3.8 Interrupt trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.4.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 7.4.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.5.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Periods in Which CPU Does Not Acknowledge Interrupts. . . . . . . . . . . . . . . . . . . . 254 16-Bit Timer/Event Counter P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 User's Manual U16580EE3V1UD00 9.4 9.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.5.1 Anytime rewrite and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000B) . . . . . . . . . . . . . . . . . . . . . 279 9.5.3 External event count mode (TPnMD2 to TPnMD0 = 001B) . . . . . . . . . . . . . . . 282 9.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B) . . . . . . . . . 286 9.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011B) . . . . . . . . . . . . . . . . . . . 289 9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 9.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101B) . . . . . . . . . . . . . . . . . . . . . 297 9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B) . . . . . . . . . . . 304 9.5.9 Counter synchronous operation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 10.1 10.2 10.3 10.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 10.4.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 10.4.2 Compare register rewrite operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 10.4.3 List of outputs in each mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 10.5 Match Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 10.5.1 Compare match interrupt related cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 10.6 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 10.6.1 Up count flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 10.6.2 Normal phase/inverted phase simultaneous active detection flag . . . . . . . . . . 369 10.6.3 Reload hold flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 10.7 Interrupt Thinning Out Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 10.7.1 Operation of interrupt thinning out function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 10.7.2 Operation examples when peak interrupts and valley interrupts occur alternately 374 10.7.3 Interrupt thinning out function during counter saw tooth wave operation . . . . . 375 10.8 A/D Conversion Trigger Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 10.8.1 A/D conversion trigger operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 10.9 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 10.9.1 Error interrupt and error signal output functions . . . . . . . . . . . . . . . . . . . . . . . . 380 10.10 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 10.10.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 10.10.2 10.10.3 10.10.4 10.10.5 10.10.6 10.10.7 10.10.8 10.10.9 10.10.10 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 External trigger pulse output mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . 394 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Pulse width measurement mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . . . 415 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 High-accuracy T-PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 PWM mode with dead time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Chapter 11 16-bit Timer/Event Counter T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 11.1 11.2 11.3 11.4 11.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.5.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.5.2 Method for writing to compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 11.6 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 User's Manual U16580EE3V1UD00 9 11.6.1 11.6.2 11.6.3 11.6.4 11.6.5 11.6.6 11.6.7 11.6.8 11.6.9 11.6.10 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 External trigger pulse output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 Pulse width measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 Encoder count function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 Offset trigger generation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (PD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.1 12.2 12.3 12.4 12.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 12.5.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 12.5.2 Operation in general-purpose timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 12.5.3 Operation in UDC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 12.6 Supplementary Description of Internal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 566 12.6.1 Clearing of count value in UDC mode B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 12.6.2 Clearing of count value upon occurrence of compare match . . . . . . . . . . . . . . 567 12.6.3 Transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 12.6.4 Interrupt signal output upon compare match . . . . . . . . . . . . . . . . . . . . . . . . . . 568 12.6.5 TM1UBD flag (bit 0 of STATUS register) operation . . . . . . . . . . . . . . . . . . . . . 568 Chapter 13 Auxiliary Frequency Output Function (AFO) . . . . . . . . . . . . . . . . . . . . . . . 569 13.1 13.2 13.3 13.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 13.4.1 Auxiliary frequency output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 13.4.2 Auxiliary frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 13.4.3 Interval timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Chapter 14 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 14.1 14.2 14.3 14.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 14.4.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 14.4.2 Operation mode and trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 14.5 Operation in A/D Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 14.5.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 14.5.2 Scan mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 14.6 Operation in Timer Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 14.6.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 14.6.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 14.7 Operation in External Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 14.7.1 Select mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 14.7.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 14.8 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 Chapter 15 Asynchronous Serial Interface C (UARTC) . . . . . . . . . . . . . . . . . . . . . . . . 609 15.1 15.2 10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 User's Manual U16580EE3V1UD00 15.3 15.4 15.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 15.5.1 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 15.5.2 SBF transmission/reception format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 15.5.3 SBF transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 15.5.4 SBF receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 15.5.5 UART transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 15.5.6 Continuous transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 15.5.7 UART receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 15.5.8 Receive error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 15.5.9 Parity types and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 15.5.10 Receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 15.6 Dedicated Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 15.6.1 Baud rate generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 15.6.2 Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 15.6.3 Baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 15.6.4 Baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 15.6.5 Allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 15.6.6 Baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 Chapter 16 Clocked Serial Interface B (CSIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 16.1 16.2 16.3 16.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 16.4.1 Single transfer mode (master mode, transmission/reception mode) . . . . . . . . 655 16.4.2 Single transfer mode (master mode, transmission mode) . . . . . . . . . . . . . . . . 656 16.4.3 Single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 657 16.4.4 Continuous mode (master mode, transmission/reception mode) . . . . . . . . . . . 658 16.4.5 Continuous mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . 659 16.4.6 Continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 660 16.4.7 Continuous reception mode (error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 16.4.8 Continuous mode (slave mode, transmission/reception mode) . . . . . . . . . . . . 662 16.4.9 Continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . 663 16.4.10 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 16.5 Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 16.6 Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 16.7 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 16.7.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 16.7.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 16.7.3 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 16.8 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 Chapter 17 Clocked Serial Interface 3 (CSI3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 17.1 17.2 17.3 17.4 17.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 Dedicated Baud Rate Generator 3n (BRG3n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 17.5.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 17.5.2 Function of CSI data buffer register (CSIBUFn) . . . . . . . . . . . . . . . . . . . . . . . . 696 17.5.3 Data transfer direction specification function . . . . . . . . . . . . . . . . . . . . . . . . . . 697 17.5.4 Transfer data length changing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 17.5.5 Function to select serial clock and data phase . . . . . . . . . . . . . . . . . . . . . . . . . 700 17.5.6 Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 17.5.7 Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 17.5.8 Transfer clock selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 User's Manual U16580EE3V1UD00 11 17.5.9 Single mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 17.5.10 Consecutive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 17.5.11 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 17.5.12 Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 17.5.13 Transmission/reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 17.5.14 Delay control of transmission/reception completion interrupt (INTC3n) . . . . . . 708 17.5.15 Transfer wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 17.5.16 Output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 17.5.17 CSIBUFn overflow interrupt signal (INTC3nOVF) . . . . . . . . . . . . . . . . . . . . . . 713 17.6 Operating Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 17.6.1 Single mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . 714 17.6.2 Single mode (master mode, reception mode). . . . . . . . . . . . . . . . . . . . . . . . . . 716 17.6.3 Single mode (master mode, transmission/reception mode) . . . . . . . . . . . . . . . 718 17.6.4 Single mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . . 720 17.6.5 Single mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 17.6.6 Single mode (slave mode, transmission/reception mode) . . . . . . . . . . . . . . . . 724 17.6.7 Consecutive mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . 726 17.6.8 Consecutive mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 728 17.6.9 Consecutive mode (master mode, transmission/reception mode) . . . . . . . . . . 730 17.6.10 Consecutive mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . 732 17.6.11 Consecutive mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . 734 17.6.12 Consecutive mode (in slave mode and transmission/reception mode) . . . . . . 736 17.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 Chapter 18 AFCAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.1.1 Overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 18.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 18.2 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 18.2.1 Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 18.2.2 Frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 18.2.3 Data frame and remote frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 18.2.4 Error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 18.2.5 Overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 18.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 18.3.1 Determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 18.3.2 Bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 18.3.3 Multi masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 18.3.4 Multi cast. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 18.3.5 CAN sleep mode/CAN stop mode function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 18.3.6 Error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 18.3.7 Baud rate control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 18.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 18.5 Internal Registers of CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 18.5.1 CAN module register and message buffer addresses . . . . . . . . . . . . . . . . . . . 764 18.5.2 CAN Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 18.5.3 CAN registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 18.5.4 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 18.6 Bit Set/Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 18.7 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 18.8 CAN Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 18.8.1 Initialization of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 18.8.2 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 18.8.3 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 18.8.4 Transition from Initialization Mode to Operation Mode . . . . . . . . . . . . . . . . . . . 808 18.8.5 Resetting error counter CnERC of CAN module . . . . . . . . . . . . . . . . . . . . . . . 809 18.9 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 18.9.1 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 12 User's Manual U16580EE3V1UD00 18.9.2 Receive Data Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 18.9.3 Receive history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 18.9.4 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 18.9.5 Multi buffer receive block function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 18.9.6 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 18.10 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 18.10.1 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 18.10.2 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 18.10.3 Automatic block transmission (ABT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 18.10.4 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 18.10.5 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 18.11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 18.11.1 CAN sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 18.11.2 CAN stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 18.11.3 Example of using power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 18.12 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 18.13 Diagnosis Functions and Special Operational Modes . . . . . . . . . . . . . . . . . . . . . . . 828 18.13.1 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 18.13.2 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 18.13.3 Self-test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 18.13.4 Receive/Transmit Operation in Each Operation Mode . . . . . . . . . . . . . . . . . . . 830 18.14 Time Stamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 18.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 18.15 Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 18.15.1 Baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 18.15.2 Representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . 836 18.16 Operation of CAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 Chapter 19 Random Number Generator (PD70F3187 only) . . . . . . . . . . . . . . . . . . . . 865 19.1 19.2 19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 19.3.1 Access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 Chapter 20 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 20.1 20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 20.2.1 Function of each port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 20.2.2 Port types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 20.2.3 Peripheral registers of I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 20.2.4 Peripheral registers of valid edge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 20.3 Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 20.3.1 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 20.3.2 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 20.3.3 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 20.3.4 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 20.3.5 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 20.3.6 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 20.3.7 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 20.3.8 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 20.3.9 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 20.3.10 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 20.3.11 Port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 20.3.12 Port AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 20.3.13 Port AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 20.3.14 Port DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 20.3.15 Port DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 20.3.16 Port CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 User's Manual U16580EE3V1UD00 13 20.3.17 Port CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 20.3.18 Port CM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 20.3.19 Port CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 20.4 Noise Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 Chapter 21 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 21.1 21.2 21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 Chapter 22 Internal RAM Parity Check Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 22.1 22.2 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 Chapter 23 On-Chip Debug Function (OCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 23.1 Function Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 23.1.1 On-chip debug unit type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 23.1.2 Debug function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 23.2 Connection with N-Wire Type Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 23.2.1 KEL connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 23.3 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 Chapter 24 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 24.1 24.2 24.3 24.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 Functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 Rewriting by Dedicated Flash Programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 24.4.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 24.4.2 Communication mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 24.4.3 Flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 24.4.4 Selection of communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 24.4.5 Communication commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 24.4.6 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 24.5 Rewriting by Self Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 24.5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 24.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 Chapter 25 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 25.1 25.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 25.2.1 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 25.2.2 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 25.2.3 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 25.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 25.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 25.4.1 External asynchronous memory access read timing . . . . . . . . . . . . . . . . . . . 1012 25.4.2 External asynchronous memory access write timing . . . . . . . . . . . . . . . . . . . 1014 25.4.3 Reset Timing (Power Up/Down Sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 25.4.4 Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 25.5 Peripheral Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 25.5.1 Timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 25.5.2 Serial interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 25.5.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 25.6 Flash Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 Chapter 26 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 14 User's Manual U16580EE3V1UD00 Chapter 27 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 Appendix A Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 Appendix B Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 User's Manual U16580EE3V1UD00 15 16 User's Manual U16580EE3V1UD00 List of Figures Figure 1-1: Figure 1-2: Figure 1-3: Figure 1-4: Figure 2-1: Figure 2-2: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: Figure 3-11: Figure 3-12: Figure 3-13: Figure 3-14: Figure 3-15: Figure 3-16: Figure 3-17: Figure 3-18: Figure 3-19: Figure 3-20: Figure 3-21: Figure 3-22: Figure 3-23: Figure 3-24: Figure 3-25: Figure 3-26: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 5-1: Figure 5-2: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 6-7: Figure 6-8: Figure 6-9: Figure 6-10: Figure 6-11: Pin Configuration 208-pin Plastic LQFP ...................................................................... 37 Pin Configuration 256-pin Plastic BGA (21 x 21) ........................................................ 38 Internal Block Diagram of mPD70F3187 ..................................................................... 44 Internal Block Diagram of mPD70F3447 ..................................................................... 45 Pin I/O Circuits ............................................................................................................ 80 Noise Removal Time Control Register (1/2) .............................................................. 82 CPU Register Set ........................................................................................................ 86 Program Counter (PC) ............................................................................................... 87 Interrupt Status Saving Registers (EIPC, EIPSW) ..................................................... 89 NMI Status Saving Registers (FEPC, FEPSW) .......................................................... 90 Interrupt Source Register (ECR) ............................................................................... 90 Program Status Word (PSW) .................................................................................... 91 CALLT Execution Status Saving Registers (CTPC, CTPSW) .................................... 92 Exception/Debug Trap Status Saving Registers (DBPC, DBPSW) ............................ 93 CALLT Base Pointer (CTBP) ...................................................................................... 93 Floating Point Arithmetic Control Register (ECT) ....................................................... 94 Floating Point Arithmetic Status Register (EFG) ........................................................ 95 CPU Address Space ................................................................................................... 98 Address Space Image ................................................................................................. 99 Program Space ......................................................................................................... 100 Data Space................................................................................................................ 100 Memory Map of PD70F3187 ................................................................................... 101 Memory Map of PD70F3447 ................................................................................... 102 Internal ROM / Internal Flash Memory Area of PD70F3187 ................................... 103 Internal ROM / Internal Flash Memory Area of PD70F3447 .................................. 104 Internal RAM Area of PD70F3187........................................................................... 105 Internal RAM Area of PD70F3447........................................................................... 105 On-Chip Peripheral I/O Area ..................................................................................... 106 Programmable Peripheral I/O Area (Outline) ............................................................ 121 Programmable Peripheral Area Control Register BPC ............................................. 122 Processor Command Register (PRCMD).................................................................. 140 System Status Register Format PHS ...................................................................... 141 Memory Block Function ............................................................................................. 146 Chip Area Select Control Registers 0, 1 (1/2) ......................................................... 147 Bus Cycle Configuration Registers 0, 1 (BCT0, BCT1) ........................................... 150 Bus Size Configuration Register (BSC) .................................................................... 152 Big Endian Addresses within Word ........................................................................... 153 Little Endian Addresses within Word ......................................................................... 153 Endian Configuration Register (BEC) ....................................................................... 154 Data Wait Control Registers 0, 1 (DWC0, DWC1) Format ..................................... 174 Address Wait Control Register (AWC) ..................................................................... 175 Bus Cycle Control Register (BCC) ........................................................................... 177 Bus Clock Dividing Control Register (DVC) .............................................................. 178 Examples of Connection to SRAM (1/2).................................................................... 182 SRAM, External ROM, External I/O Access Timing (1/8).......................................... 184 DMA Transfer Memory Start Address Registers 0 to 7 (MAR0 to MAR7) ................ 194 DMA Transfer SFR Start Address Registers 2, 3 (SAR2, SAR3) ............................. 195 DMA Transfer Count Registers 0 to 7 (DTCR0 to DTCR7) ...................................... 196 DMA Mode Control Register (DMAMC) .................................................................... 197 DMA Status Register (DMAS) .................................................................................. 197 DMA Data Size Control Register (DMDSC) ............................................................. 198 DMA Trigger Factor Registers 4 to 7 (DTFR4 to DTFR7) ........................................ 199 Initialization of DMA Transfer for A/D Conversion Result.......................................... 201 Operation of DMA Channel 0/1 ................................................................................. 202 DMA Channel 0 and 1 Trigger Signal Timing ............................................................ 203 Initialization of DMA Transfer for TMRn Compare Registers .................................... 205 User's Manual U16580EE3V1UD00 17 Figure 6-12: Figure 6-13: Figure 6-14: Figure 6-15: Figure 6-16: Figure 6-17: Figure 6-18: Figure 6-19: Figure 6-20: Figure 6-21: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Figure 7-10: Figure 7-11: Figure 7-12: Figure 7-13: Figure 7-14: Figure 7-15: Figure 7-16: Figure 7-17: Figure 7-18: Figure 7-19: Figure 7-20: Figure 7-21: Figure 7-22: Figure 7-23: Figure 7-24: Figure 8-1: Figure 8-2: Figure 9-1: Figure 9-2: Figure 9-3: Figure 9-4: Figure 9-5: Figure 9-6: Figure 9-7: Figure 9-8: Figure 9-9: Figure 9-10: Figure 9-11: Figure 9-12: Figure 9-13: Figure 9-14: Figure 9-15: Figure 9-16: Figure 9-17: Figure 9-18: Figure 9-19: Figure 9-20: Figure 9-21: 18 Operation of DMA Channel 2/3 ................................................................................. 206 DMA Channel 2 and 3 Trigger Signal Timing ............................................................ 207 Initialization of DMA Transfer for Serial Data Reception ........................................... 209 Operation of DMA Channel 4/5 ................................................................................. 210 DMA Channel 4 and 5 Trigger Signal Timing ............................................................ 211 Initialization of DMA Transfer for Serial Data Transmission ...................................... 213 DMA Channel 6 and 7 Trigger Signal Timing ............................................................ 214 Operation of DMA Channel 6/7 ................................................................................. 215 CPU and DMA Controller Processing of DMA Transfer Termination (Example)....... 216 Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts 218 Processing Configuration of Non-Maskable Interrupt................................................ 225 Acknowledging Non-Maskable Interrupt Request ..................................................... 226 RETI Instruction Processing ...................................................................................... 227 Non-maskable Interrupt Status Flag (NP) ................................................................ 228 NMI Edge Detection Specification: Interrupt Mode Register 0 (INTM0) .................. 228 Maskable Interrupt Processing .................................................................................. 230 RETI Instruction Processing ...................................................................................... 231 Example of Processing in which Another Interrupt Request Is Issued while an Interrupt is being Processed (1/2) ............................................................... 233 Example of Processing Interrupt Requests Simultaneously Generated.................... 235 Interrupt Control Register (PICn) .............................................................................. 236 Interrupt Mask Registers 0 to 2 (IMR0 to IMR2) ....................................................... 240 Interrupt Mask Registers 3 to 6 (IMR3 to IMR6) ....................................................... 241 Interrupt Service Priority Register (ISPR) ................................................................. 242 Maskable interrupt status flag (ID) ............................................................................ 243 Interrupt Mode Register 0 (INTM0) .......................................................................... 245 Interrupt Mode Register 1 (INTM1) .......................................................................... 246 Interrupt Mode Register 2 (INTM2) .......................................................................... 247 Interrupt Mode Register 3 (INTM3) .......................................................................... 248 Software Exception Processing................................................................................. 249 RETI Instruction Processing ...................................................................................... 250 Exception Status Flag (EP) ...................................................................................... 251 Illegal Opcode............................................................................................................ 252 Exception Trap Processing........................................................................................ 253 Restore Processing from Exception Trap.................................................................. 253 Clock Generator ........................................................................................................ 255 Power Save Mode State Transition Diagram ............................................................ 256 Block Diagram of Timer P.......................................................................................... 260 TMPn Capture/Compare Register 0 (TPnCCR0) ..................................................... 261 TMPn Capture/Compare Register 1 (TPnCCR1) ..................................................... 262 TMPn Counter Register (TPnCNT) .......................................................................... 263 TMPn Control Register 0 (TPnCTL0) ...................................................................... 264 TMPn Control Register 1 (TPnCTL1) (1/2)............................................................... 265 TMPn I/O Control Register 0 (TPnIOC0) .................................................................. 267 TMPn I/O Control Register 1 (TPnIOC1) .................................................................. 268 TMPn I/O Control Register 2 (TPnIOC2) .................................................................. 269 TMPn Option Register 0 (TPnOPT0) ........................................................................ 270 TMPn Input Control Register 0 (TPIC0) .................................................................. 271 TMP Input Control Register 1 (TPIC1) .................................................................... 272 TMP Input Control Register 1 (TPIC1) .................................................................... 273 Basic Operation Flow for Anytime Write.................................................................... 275 Timing Diagram for Anytime Write............................................................................. 276 Basic Operation Flow for Reload (Batch Rewrite) ..................................................... 277 Timing Chart for Reload ............................................................................................ 278 Flowchart of Basic Operation in Interval Timer Mode................................................ 279 Basic Operation Timing in Interval Timer Mode (1/2) ................................................ 280 Flowchart of Basic Operation in External Event Count Mode.................................... 283 Basic Operation Timing in External Event Count Mode (1/2) .................................... 284 User's Manual U16580EE3V1UD00 Figure 9-22: Figure 9-23: Figure 9-24: Figure 9-25: Figure 9-26: Figure 9-27: Figure 9-28: Figure 9-29: Figure 9-30: Figure 9-31: Figure 9-32: Figure 9-33: Figure 9-34: Figure 9-35: Figure 9-36: Figure 9-37: Figure 9-38: Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: Figure 10-5: Figure 10-6: Figure 10-7: Figure 10-8: Figure 10-9: Figure 10-10: Figure 10-11: Figure 10-12: Figure 10-13: Figure 10-14: Figure 10-15: Figure 10-16: Figure 10-17: Figure 10-18: Figure 10-19: Figure 10-20: Figure 10-21: Figure 10-22: Figure 10-23: Figure 10-24: Figure 10-25: Figure 10-26: Figure 10-27: Figure 10-28: Figure 10-29: Figure 10-30: Figure 10-31: Figure 10-32: Figure 10-33: Figure 10-34: Figure 10-35: Figure 10-36: Figure 10-37: Figure 10-38: Figure 10-39: Figure 10-40: Flowchart of Basic Operation in External Trigger Pulse Output Mode ...................... 287 Basic Operation Timing in External Trigger Pulse Output Mode ............................... 288 Flowchart of Basic Operation in One-Shot Pulse Mode ............................................ 290 Timing of Basic Operation in One-Shot Pulse Mode ................................................. 291 Flowchart of Basic Operation in PWM Mode (1/2) .................................................... 293 Basic Operation Timing in PWM Mode (1/2) ............................................................. 295 Flowchart of Basic Operation in Free-Running Mode................................................ 299 Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0) ...... 300 Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 1) ...... 301 Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 0) ...... 302 Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1) ...... 303 Flowchart of Pulse Period Measurement .................................................................. 305 Basic Operation Timing of Pulse Period Measurement............................................. 306 Flowchart of Alternating Pulse Width and Pulse Space Measurement ..................... 307 Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement 308 Flowchart of Simultaneous Pulse Width and Pulse Space Measurement................. 309 Basic Operation Timing of Simultaneous Pulse Width and Pulse Space Measurement ................................................................................ 310 Timer Rn Block Diagram ........................................................................................... 315 TMRn Capture/Compare Register 0 (TRnCCR0) ..................................................... 316 TMRn Capture/Compare Register 1 (TRnCCR1) ..................................................... 317 TMRn Capture/Compare Register 2 (TRnCCR2) ..................................................... 318 TMRn Capture/Compare Register 3 (TRnCCR3) ..................................................... 319 TMRn Compare Register 4 (TRnCCR4) ................................................................... 320 TMRn Compare Register 5 (TRnCCR5) ................................................................... 321 TMRn Counter Read Register (TRnCNT) ................................................................ 322 TMRn Sub-Counter Read Register (TRnSBC) ......................................................... 322 TMRn Dead Time Setting Register 0 (TRnDTC0) .................................................... 323 TMRn Dead Time Setting Register 1 (TRnDTC1) .................................................... 323 TMRn Control Register 0 (TRnCTL0) (1/2) .............................................................. 324 TMRn Control Register 1 (TRnCTL1) (1/2) ............................................................... 326 TMRn I/O Control Register 0 (TRnIOC0) ................................................................. 328 TMR1 I/O Control Register 1 (TR1IOC1) ................................................................. 329 TMR1 I/O Control Register 2 (TR1IOC2) ................................................................. 330 TMRn I/O Control Register 3 (TRnIOC3) ................................................................. 331 TMRn I/O Control Register 4 (TRnIOC4) ................................................................. 332 TMRn Option Register 0 (TRnOPT0) (1/2)................................................................ 333 TMRn Option Register 1 (TRnOPT1) (1/2)................................................................ 335 TMRn Option Register 2 (TRnOPT2) (1/2)................................................................ 337 TMRn Option Register 3 (TRnOPT3) (1/2)................................................................ 339 TMRn Option Register 6 (TRnOPT6) ....................................................................... 341 TMRn Option Register 7 (TRnOPT7) ....................................................................... 342 Anytime Rewrite Timing ............................................................................................ 347 Basic Operation Flow during Batch Rewrite .............................................................. 352 Batch Rewrite Timing (1/2) ........................................................................................ 353 TORn7 Pin Output Timing 1 ...................................................................................... 360 Interrupt Signal Output Example (1/2) ....................................................................... 364 Up Count Flags Timings (1/2) ................................................................................... 368 Normal Phase/Inverted Phase Simultaneous Active Detection Flag Timing ............. 369 Reload Hold Flag Timings ......................................................................................... 370 Interrupt Thinning Out Operations (1/2) .................................................................... 372 Examples when Peak Interrupts and Valley Interrupts Occur Alternately (1/2)......... 374 A/D Conversion Trigger Output Controller................................................................. 376 A/D Conversion Trigger Timings (1/2) ....................................................................... 378 Error Interrupt (INTTRnER) and Error Signal (TRnER) Output Controller................. 380 Error Interrupt and Error Signal Output Controller in PWM mode ............................. 381 Error Interrupt and Error Signal Output Controller in triangular wave PWM mode.... 382 Error Interrupt and Error Signal Output Controller User's Manual U16580EE3V1UD00 19 Figure 10-41: Figure 10-42: Figure 10-43: Figure 10-44: Figure 10-45: Figure 10-46: Figure 10-47: Figure 10-48: Figure 10-49: Figure 10-50: Figure 10-51: Figure 10-52: Figure 10-53: Figure 10-54: Figure 10-55: Figure 10-56: Figure 10-57: Figure 10-58: Figure 10-59: Figure 10-60: Figure 10-61: Figure 10-62: Figure 10-63: Figure 10-64: Figure 10-65: Figure 10-66: Figure 10-67: Figure 10-68: Figure 10-69: Figure 10-70: Figure 10-71: Figure 10-72: Figure 10-73: Figure 10-74: Figure 10-75: Figure 10-76: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 11-9: Figure 11-10: Figure 11-11: Figure 11-12: Figure 11-13: Figure 11-14: Figure 11-15: Figure 11-16: Figure 11-17: Figure 11-18: Figure 11-19: 20 in High-Accuracy T-PWM Mode / PWM Mode with Dead Time ................................ 383 Basic Operation Flow in Interval Timer Mode............................................................ 384 Basic Timing in Interval Timer Mode (1/2)................................................................. 386 Basic Operation Timing in External Event Count Mode (1/4) .................................... 390 Basic Operation Flow in External Trigger Pulse Output Mode .................................. 396 Basic Operation Timing in External Trigger Pulse Output Mode ............................... 397 Basic Operation Flow in One-Shot Pulse Mode ........................................................ 400 Basic Operation Timing in One-Shot Pulse Mode ..................................................... 401 Basic Operation Mode in PWM Mode (1/2) ............................................................... 404 Basic Operation Timing in PWM Mode (1/2) ............................................................. 406 Basic Operation Flow in Free-Running Mode............................................................ 408 Basic Operation Timing in Free-Running Mode (Compare Function) ....................... 411 Basic Operation Timing in Free-Running Mode (Capture Function) ......................... 412 Basic Operation Timing in Free-Running Mode (Compare/Capture Function).......... 413 Basic Operation Timing in Pulse Width Measurement Mode .................................... 415 Basic Operation Timing in Triangular Wave PWM Mode .......................................... 419 High-Accuracy T-PWM Mode Block Diagram............................................................ 420 Counter Operation in High-Accuracy T-PWM Mode.................................................. 424 Sub-Counter Operation in High-Accuracy T-PWM Mode .......................................... 424 Timer Output Example When TRnCE = 1 Is Set (Initial) (High-Accuracy T-PWM Mode).................................................................................. 425 Timer Output Example During Operation (High-Accuracy T-PWM Mode) ................ 426 TORn1 Pin Output Example When Performing Additional Pulse Control.................. 427 TORn1 Pin Output Example When Additional Pulse Control Is Not Performed ........ 428 Timings of Timer Output in High-accuracy T-PWM mode (1/3)................................. 429 Timer Output Change after Compare Register Updating Timings (1/3) .................... 433 Compare Register Value After Trough Reload Timing (1/3)...................................... 436 Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (1/3) ......... 439 Compare Register Value After Trough Reload (1/3) ................................................. 442 Output Waveform Example When Dead Time Is Set ................................................ 445 Dead Time Control in High-Accuracy T-PWM Mode ................................................. 446 Operation Example Setting Is Out of Range ............................................................. 447 Error Interrupt Operation Example ............................................................................ 448 Block Diagram in PWM Mode With Dead Time......................................................... 449 Output Waveform Example in PWM Mode with Dead Time...................................... 451 Timer Output Example When TRnCE = 1 Is Set (Initial) (PWM mode with Dead Time) ................................................................................... 454 Output Waveform Example in PWM Mode with Dead Time...................................... 455 Error Interrupt (INTTRnER) in PWM Mode with Dead Time...................................... 456 Block Diagram of Timer T.......................................................................................... 460 TMTn Capture/Compare Register 0 (TTnCCR0) ...................................................... 461 TMTn Capture/Compare Register 1 (TTnCCR1) ...................................................... 462 TMTn Counter Write Buffer Register (TTnTCW) ...................................................... 464 TMTn Counter Read Buffer Register (TTnCNT) ....................................................... 464 TMTn Control Register 0 (TTnCTL0) (1/2) ................................................................ 465 TMTn Control Register 1 (TTnCTL1) (1/2) ................................................................ 467 TMTn Control Register 2 (TTnCTL2) (1/2) ................................................................ 469 TMTn I/O Control Register 0 (TTnIOC0) .................................................................. 471 TMTn I/O Control Register 1 (TTnIOC1) .................................................................. 472 TMTn I/O Control Register 2 (TTnIOC2) .................................................................. 473 TMTn I/O Control Register 3 (TTnIOC3) (1/2)........................................................... 474 TMTn Option Register 0 (TTnOPT0) ........................................................................ 476 TMTn Option Register 1 (TTnOPT1) (1/2)................................................................. 477 TMTn Option Register 2 (TTnOPT2) ......................................................................... 479 Basic Operation Flow for Anytime Rewrite ................................................................ 483 Basic Anytime Rewrite Operation Timing .................................................................. 484 Basic Operation Flow for Reload (Batch Rewrite) ..................................................... 485 Basic Reload Operation Timing................................................................................. 486 User's Manual U16580EE3V1UD00 Figure 11-20: Figure 11-21: Figure 11-22: Figure 11-23: Figure 11-24: Figure 11-25: Figure 11-26: Figure 11-27: Figure 11-28: Figure 11-29: Figure 11-30: Figure 11-31: Figure 11-32: Figure 11-33: Figure 11-34: Figure 11-35: Figure 11-36: Figure 11-37: Figure 11-38: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: Figure 12-12: Figure 12-13: Figure 12-14: Figure 12-15: Figure 12-16: Figure 12-17: Figure 12-18: Figure 12-19: Figure 12-20: Figure 12-21: Figure 12-22: Figure 12-23: Figure 12-24: Figure 12-25: Figure 12-26: Figure 12-27: Figure 12-28: Figure 13-1: Figure 13-2: Figure 13-3: Figure 14-1: Figure 14-2: Basic Operation Flow in Interval Timer Mode............................................................ 487 Basic Timing in Interval Timer Mode (1/2)................................................................. 488 Basic Operation Timing in External Event Count Mode (1/4) .................................... 491 Basic Operation Flow in External Trigger Pulse Output Mode .................................. 496 Basic Operation Timing in External Trigger Pulse Output Mode ............................... 497 Basic Operation Flow in One-Shot Pulse Mode ........................................................ 499 Basic Operation Timing in One-Shot Pulse Mode ..................................................... 500 Basic Operation Mode in PWM Mode (1/2) ............................................................... 501 Basic Operation Timing in PWM Mode (1/2) ............................................................. 503 Basic Operation Flow in Free-Running Mode............................................................ 505 Basic Operation Timing in Free-Running Mode (Compare Function) ....................... 507 Basic Operation Timing in Free-Running Mode (Capture Function) ......................... 508 Basic Operation Timing in Free-Running Mode (Compare/Capture Function).......... 509 Basic Operation Timing in Pulse Width Measurement Mode .................................... 511 Basic Operation Timing in Triangular Wave PWM Mode .......................................... 513 Encoder Count Function Up/Down Count Selection Specification Timings (1/6) ...... 516 Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (1/4) ............................................................................................................. 523 Counter Hold through Bit TTnECC Timings (1/5) ...................................................... 527 Basic Timing in Offset Trigger Generation Mode ...................................................... 533 Block Diagram of Timer ENC10 (TMENC10) ............................................................ 538 Timer ENC10 (TMENC10) ........................................................................................ 539 Compare Register 100 (CM100) .............................................................................. 541 Compare Register 101 (CM101) .............................................................................. 542 Capture/Compare Register 100 (CC100) ................................................................. 543 Capture/Compare Register 101 (CC101) ................................................................. 544 Timer Unit Mode Register 10 (TUM10) ................................................................... 545 Timer Control Register 10 (TMC10) (1/2) ................................................................. 546 Capture/Compare Control Register 10(CCR10) ....................................................... 548 Signal Edge Selection Register 10 (SESA10) (1/2) ................................................ 549 Prescaler Mode Register 10 (PRM10) ..................................................................... 551 Status Register 10 (STATUS10) ............................................................................. 553 TMENC10 Block Diagram (During PWM Output Operation) ..................................... 556 PWM Signal Output Example (When ALVT10 Bit = 0 Is Set).................................... 557 Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin) ..................... 559 Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin): In Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing....................................... 559 Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1, TCUD1 Pins) ..... 560 Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin) ..................... 561 Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin): In Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing....................................... 561 Mode 4 ...................................................................................................................... 562 Example of TMENC10 Operation When Interval Operation and Transfer Operation are Combined ........................................................................................... 563 Example of TM1Operation in UDC Mode .................................................................. 564 Clear Operation upon Match with CM100 During TMENC10 Up Count Operation ... 566 Clear Operation upon Match with CM101 during TMENC10 Down Count Operation .............................................................................................. 566 Count Value Clear Operation upon Compare Match................................................. 567 Internal Operation During Transfer Operation ........................................................... 567 Interrupt Output upon Compare Match (CM101 with Operation Mode set to General-Purpose Timer Mode and Count Clock Set to fXX/8) ......................... 568 TM1UBDn Flag Operation ......................................................................................... 568 Block Diagram of Auxiliary Frequency Output Function ............................................ 569 Prescaler Mode Register 2 (PRSM2) ...................................................................... 570 Prescaler Compare Register 2 (PRSCM2) .............................................................. 571 Block Diagram of A/D Converter (ADCn) .................................................................. 575 A/D Converter n Mode Register 0 (ADMn0) ............................................................ 576 User's Manual U16580EE3V1UD00 21 Figure 14-3: Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 14-20: Figure 15-1: Figure 15-2: Figure 15-3: Figure 15-4: Figure 15-5: Figure 15-6: Figure 15-7: Figure 15-8: Figure 15-9: Figure 15-10: Figure 15-11: Figure 15-12: Figure 15-13: Figure 15-14: Figure 15-15: Figure 15-16: Figure 15-17: Figure 15-18: Figure 15-19: Figure 15-20: Figure 15-21: Figure 15-22: Figure 15-23: Figure 16-1: Figure 16-2: Figure 16-3: Figure 16-4: Figure 16-5: Figure 16-6: Figure 16-7: Figure 16-8: Figure 16-9: Figure 16-10: Figure 16-11: Figure 16-12: Figure 16-13: Figure 16-14: Figure 16-15: 22 A/D Converter n Mode Register 1 (ADMn1) (1/2) ..................................................... 577 A/D Converter n Mode Register 2 (ADMn2) ............................................................ 579 A/D Converter n Trigger Source Select Register (ADTRSELn) ............................... 580 A/D Conversion Result Registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) ..................................................... 581 Relationship Between Analog Input Voltage and A/D Conversion Results ............... 583 A/D Conversion Result Registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) ..................................................... 584 Select Mode Operation Timing: 1-Buffer Mode (ANIn1)............................................ 588 Select Mode Operation Timing: 4-Buffer Mode (ANIn2)............................................ 589 Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3)................................ 590 Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer)......................... 591 Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers)....................... 593 Example of Scan Mode Operation (A/D Trigger Scan).............................................. 595 Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (ANIn1) ........ 597 Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANIn3) ...... 599 Example of Scan Mode Operation (Timer Trigger Scan) (ANIn0 to ANIn4) .............. 601 Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (ANIn1) .... 603 Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (ANIn2) .. 605 Example of Scan Mode Operation (External Trigger Scan) (ANIn0 to ANIn3) .......... 607 Block Diagram of Asynchronous Serial Interface n ................................................... 611 UARTCn Control Register 0 (UCnCTL0) (1/2) ........................................................ 612 UARTCn Control Register 1 (UCnCTL1) ................................................................. 614 UARTCn Control Register 2 (UCnCTL2) ................................................................. 615 UARTCn Option Control Register 0 (UCnOPT0) (1/2) ............................................. 616 UARTCn Option Control Register 1 (UCnOPT1) ..................................................... 618 UARTCn Status Register (UCnSTR) (1/2) .............................................................. 620 UARTCn Status Register 1 (UCnSTR1) .................................................................. 622 UARTCn Receive Data Register (UCnRX, UCnRXL) .............................................. 623 UARTCn Transmit Data Register (UCnTX, UCnTXL) .............................................. 624 UARTC Transmit/Receive Data Format (1/2)............................................................ 626 LIN Transmission Manipulation Outline..................................................................... 628 LIN Reception Manipulation Outline .......................................................................... 629 SBF Transmission Timing ......................................................................................... 630 SBF Reception Timing............................................................................................... 631 UART Transmission .................................................................................................. 632 Continuous Transmission Processing Flow............................................................... 633 Continuous Transfer Operation Timing ..................................................................... 634 UART Reception Timing............................................................................................ 635 Noise Filter Circuit ..................................................................................................... 638 Configuration of Baud Rate Generator ...................................................................... 639 Allowable Baud Rate Range During Reception......................................................... 642 Transfer Rate During Continuous Transfer ............................................................... 644 Block Diagram of CSIBn............................................................................................ 646 CSIBn Receive Data Register (CBnRX, CBnRXL) ................................................... 647 CSIBn Transmit Data Register (CBnTX, CBnTXL) ................................................... 648 CSIBn Control Register 0 (CBnCTL0) (1/2) ............................................................. 649 CSIBn Control Register 1 (CBnCTL1) ..................................................................... 651 CSIBn Control Register 2 (CBnCTL2) ...................................................................... 652 Effect of Transfer Data Length Setting ...................................................................... 653 CSIBn Status Register (CBnSTR) ........................................................................... 654 Single Transfer Mode (Master Mode, Transmission/Reception Mode) ..................... 655 Single Transfer Mode (Master Mode, Transmission Mode) ...................................... 656 Single Transfer Mode (Master Mode, Reception Mode)............................................ 657 Continuous Mode (Master Mode, Transmission/Reception Mode) ........................... 658 Continuous Mode (Master Mode, Transmission Mode)............................................. 659 Continuous Mode (Master Mode, Reception Mode).................................................. 660 Continuous Reception Mode (Error).......................................................................... 661 User's Manual U16580EE3V1UD00 Figure 16-16: Figure 16-17: Figure 16-18: Figure 16-19: Figure 16-20: Figure 16-21: Figure 16-22: Figure 16-23: Figure 16-24: Figure 16-25: Figure 16-26: Figure 16-27: Figure 16-28: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Figure 17-10: Figure 17-11: Figure 17-12: Figure 17-13: Figure 17-14: Figure 17-15: Figure 17-16: Figure 17-17: Figure 17-18: Figure 17-19: Figure 17-20: Figure 17-21: Figure 17-22: Figure 17-23: Figure 17-24: Figure 17-25: Figure 17-26: Figure 17-27: Figure 17-28: Figure 17-29: Figure 17-30: Figure 17-31: Figure 17-32: Figure 17-33: Figure 18-1: Figure 18-2: Figure 18-3: Figure 18-4: Figure 18-5: Figure 18-6: Figure 18-7: Figure 18-8: Figure 18-9: Figure 18-10: Figure 18-11: Figure 18-12: Continuous Mode (Slave Mode, Transmission/Reception Mode) ............................. 662 Continuous Mode (Slave Mode, Reception Mode).................................................... 663 CSIBn Clock Timing (1/2) .......................................................................................... 664 Operation Flow of Single Transmission..................................................................... 667 Operation Flow of Single Reception (Master)............................................................ 668 Operation Flow of Single Reception (Slave) ............................................................. 669 Operation Flow of Continuous Transmission............................................................. 670 Operation Flow of Continuous Reception (Master) ................................................... 671 Operation Flow of Continuous Reception (Slave) ..................................................... 672 Block Diagram of Baud Rate Generators 0 and 1 (BRG0, BRG1) ............................ 673 Block Diagram of CSIBn Baud Rate Generators....................................................... 673 Prescaler Mode Registers 0 and 1 (PRSM0, PRSM1) ............................................ 674 Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1) ................................. 675 Block Diagram of Clocked Serial Interface 3n (CSI3n).............................................. 679 Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2) .................................... 680 Clocked Serial Interface Clock Select Register 3n (CSIC3n) (1/3) .......................... 682 Receive Data Buffer Register 3n (SIRB3n, SIRB3nL, SIRB3nH) ............................ 685 Chip Select CSI Buffer Register 3n (SFCS3n, SFCS3nL) ........................................ 686 Transmit Data CSI Buffer Register 3n (SFDB3n, SFDB3nL, SFDB3nH) ................ 687 CSIBUF Status Register 3n (SFA3n)(1/3) ............................................................... 688 Transfer Data Length Select Register 3n (CSIL3n) ................................................. 691 Transfer Data Number Specification Register 3n (SFN3n) ..................................... 692 Transfer Clock of CSI3n ............................................................................................ 693 Function of CSI Data Buffer Register n (CSIBUFn)................................................... 696 Data Transfer Direction Specification (MSB first) ...................................................... 697 Data Transfer Direction Specification (LSB first) ....................................................... 698 Transfer Data Length Changing Function ................................................................. 699 Clock Timing.............................................................................................................. 700 Master Mode ............................................................................................................. 701 Slave Mode ............................................................................................................... 702 Single Mode .............................................................................................................. 704 Consecutive Mode..................................................................................................... 706 Delay Control of Transmission/Reception Completion Interrupt (INTC3n):............... 708 Transfer Wait Function (1/3)...................................................................................... 709 Single Mode (Master Mode, Transmission Mode)..................................................... 714 Single Mode (Master Mode, Reception Mode) .......................................................... 716 Single Mode (Master Mode, Transmission/Reception Mode).................................... 718 Single Mode (Slave Mode, Transmission Mode)....................................................... 720 Single Mode (Slave Mode, Reception Mode) ............................................................ 722 Single Mode (Slave Mode, Transmission/Reception Mode)...................................... 724 Consecutive Mode (Master Mode, Transmission Mode) ........................................... 726 Consecutive Mode (Master Mode, Reception Mode) ................................................ 728 Consecutive Mode (Master Mode, Transmission/Reception Mode).......................... 730 Consecutive Mode (Slave Mode, Transmission Mode) ............................................. 732 Consecutive Mode (Slave Mode, Reception Mode) .................................................. 734 Consecutive Mode (Slave Mode, Transmission/Reception Mode)............................ 736 Block Diagram of CAN Module.................................................................................. 741 Composition of Layers............................................................................................... 742 Data Frame ............................................................................................................... 743 Remote Frame .......................................................................................................... 744 Start of frame (SOF) .................................................................................................. 744 Arbitration field (in standard format mode) ................................................................ 745 Arbitration field (in extended format mode) ............................................................... 745 Control field ............................................................................................................... 746 Data field ................................................................................................................... 747 CRC field ................................................................................................................... 747 ACK field ................................................................................................................... 748 End of frame (EOF) ................................................................................................... 748 User's Manual U16580EE3V1UD00 23 Figure 18-13: Figure 18-14: Figure 18-15: Figure 18-16: Figure 18-17: Figure 18-18: Figure 18-19: Figure 18-20: Figure 18-21: Figure 18-22: Figure 18-23: Figure 18-24: Figure 18-25: Figure 18-26: Figure 18-27: Figure 18-28: Figure 18-29: Figure 18-30: Figure 18-31: Figure 18-32: Figure 18-33: Figure 18-34: Figure 18-35: Figure 18-36: Figure 18-37: Figure 18-38: Figure 18-39: Figure 18-40: Figure 18-41: Figure 18-42: Figure 18-43: Figure 18-44: Figure 18-45: Figure 18-46: Figure 18-47: Figure 18-48: Figure 18-49: Figure 18-50: Figure 18-51: Figure 18-52: Figure 18-53: Figure 18-54: Figure 18-55: Figure 18-56: Figure 18-57: Figure 18-58: Figure 18-59: Figure 18-60: Figure 19-1: Figure 20-1: Figure 20-2: Figure 20-3: Figure 20-4: Figure 20-5: Figure 20-6: Figure 20-7: Figure 20-8: 24 Interframe space (error active node) ......................................................................... 749 Interframe space (error passive node) ...................................................................... 749 Error frame ................................................................................................................ 750 Overload frame.......................................................................................................... 751 Recovery from bus-off state through normal recovery sequence.............................. 758 Segment setting......................................................................................................... 759 Configuration of data bit time defined by CAN specification...................................... 760 Adjusting synchronization of data bit ......................................................................... 761 Re-synchronization.................................................................................................... 762 Connection to CAN bus ............................................................................................. 763 Example of bit setting/clearing operations................................................................. 771 CAN module clock ..................................................................................................... 791 Data bit time .............................................................................................................. 792 Setting transmission request (TRQ) to transmit message buffer after redefinition.... 808 Transition to operation modes ................................................................................... 809 DN and MUC Bit Setting Period (for Standard ID Format) ........................................ 811 Receive history list..................................................................................................... 812 Message processing example ................................................................................... 816 Transmit history list.................................................................................................... 819 CAN module terminal connection in receive-only mode............................................ 828 CAN module terminal connection in self-test mode................................................... 830 Timing diagram of capture signal TSOUT ................................................................. 831 Initialization................................................................................................................ 840 Re-initialization .......................................................................................................... 841 Message buffer initialization ...................................................................................... 842 Message buffer redefinition ....................................................................................... 843 Message Buffer Redefinition during Transmission .................................................... 844 Message transmit processing.................................................................................... 845 ABT Message transmit processing............................................................................ 846 Transmission via interrupt (using CnLOPT register) ................................................. 847 Transmission via interrupt (using CnTGPT register) ................................................. 848 Transmission via software polling.............................................................................. 849 Transmission abort processing (Except Normal Operation Mode with ABT) ............ 850 Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) .......................................................................... 851 Transmission abort processing (normal operation mode with ABT).......................... 852 Transmission request abort processing (normal operation mode with ABT)............. 853 Reception via interrupt (using CnLIPT register) ........................................................ 854 Reception via interrupt (using CnRGPT register) ...................................................... 855 Reception via software polling................................................................................... 856 Setting CAN sleep mode/stop mode ......................................................................... 857 Clear CAN sleep/stop mode ...................................................................................... 858 Bus-Off recovery (Except Normal Operation Mode with ABT) .................................. 859 Bus-Off recovery (Normal Operation Mode with ABT) .............................................. 860 Normal shutdown process ......................................................................................... 861 Forced shutdown process ......................................................................................... 861 Error handling ............................................................................................................ 862 Setting CPU stand-by (from CAN sleep mode) ......................................................... 863 Setting CPU stand-by (from CAN stop mode) ........................................................... 864 Random Number Register (RNG) ............................................................................. 865 Port Configuration...................................................................................................... 868 Port Type 1 ................................................................................................................ 870 Port Type 1S.............................................................................................................. 871 Port Type 1E.............................................................................................................. 872 Port Type 2 ................................................................................................................ 873 Port Type 2A.............................................................................................................. 874 Port Type 2C ............................................................................................................. 875 Port Type 3 ................................................................................................................ 876 User's Manual U16580EE3V1UD00 Figure 20-9: Figure 20-10: Figure 20-11: Figure 20-12: Figure 20-13: Figure 20-14: Figure 20-15: Figure 20-16: Figure 20-17: Figure 20-18: Figure 20-19: Figure 20-20: Figure 20-21: Figure 20-22: Figure 20-23: Figure 20-24: Figure 20-25: Figure 20-26: Figure 20-27: Figure 20-28: Figure 20-29: Figure 20-30: Figure 20-31: Figure 20-32: Figure 20-33: Figure 20-34: Figure 20-35: Figure 20-36: Figure 20-37: Figure 20-38: Figure 20-39: Figure 20-40: Figure 20-41: Figure 20-42: Figure 20-43: Figure 20-44: Figure 20-45: Figure 20-46: Figure 20-47: Figure 20-48: Figure 20-49: Figure 20-50: Figure 20-51: Figure 20-52: Figure 20-53: Figure 20-54: Figure 20-55: Figure 20-56: Figure 20-57: Figure 20-58: Figure 20-59: Figure 20-60: Figure 20-61: Figure 20-62: Figure 20-63: Figure 20-64: Figure 20-65: Figure 20-66: Port Type 4 ................................................................................................................ 877 Port Type 4C ............................................................................................................. 878 Port Type 5 ................................................................................................................ 879 Port Type 6 ................................................................................................................ 880 Port Type 7 ................................................................................................................ 881 Port Type 8 ................................................................................................................ 882 Port Type 9 ................................................................................................................ 883 Port Type 10 .............................................................................................................. 884 Port Type 11 .............................................................................................................. 885 Port Type 12 .............................................................................................................. 886 Port Type 13 .............................................................................................................. 888 Port Type 14 .............................................................................................................. 890 Port Type 15 .............................................................................................................. 891 Port Type 15A ........................................................................................................... 892 Port Register 0 (P0) ................................................................................................. 897 Port Register 1 (P1) ................................................................................................. 899 Port Mode Register 1 (PM1) .................................................................................... 899 Port Mode Control Register 1 (PMC1) (1/2) ............................................................. 900 Port Register 2 (P2) ................................................................................................. 903 Port Mode Register 2 (PM2) .................................................................................... 903 Port Mode Control Register 2 (PMC2) (1/2) ............................................................. 904 Port Register 3 (P3) ................................................................................................. 907 Port Mode Register 3 (PM3) .................................................................................... 907 Port Mode Control Register 3 (PMC3) (1/2) ............................................................. 908 Port Register 4 (P4) ................................................................................................. 911 Port Mode Register 4 (PM4) .................................................................................... 911 Port Mode Control Register 4 (PMC4) ...................................................................... 912 Port Register 5 (P5) ................................................................................................. 914 Port Mode Register 5 (PM5) .................................................................................... 914 Port Mode Control Register 5 (PMC5)) .................................................................... 915 Port Emergency Shut Off Control Register 5 (PESC5) ............................................ 916 Port Emergency Shut Off Status Register 5 (ESOST5)) .......................................... 917 Port Register 6 (P6) ................................................................................................. 919 Port Mode Register 6 (PM6) .................................................................................... 919 Port Mode Control Register 6 (PMC6) (1/2) ............................................................. 920 Port Emergency Shut Off Control Register 6 (PESC6) ............................................ 922 Port Emergency Shut Off Status Register 6 (ESOST6)) .......................................... 923 Port Register 7 (P7) ................................................................................................. 925 Port Mode Register 7 (PM7) .................................................................................... 925 Port Mode Control Register 7 (PMC7) (1/2) ............................................................. 926 Port Register 8 (P8) ................................................................................................. 929 Port Mode Register 8 (PM8) .................................................................................... 929 Port Mode Control Register 8 (PMC8) (1/2) ............................................................. 930 Port Register 9 (P9) ................................................................................................. 933 Port Mode Register 9 (PM9) .................................................................................... 933 Port Mode Control Register 9 (PMC9) (1/2) ............................................................. 934 Port Register 10 (P10) ............................................................................................. 937 Port Mode Register 10 (PM10) ................................................................................ 937 Port Mode Control Register 10 (PMC10) .................................................................. 938 Port Register AL(PAL) ........................................................................................... 940 Port Mode Register AL(PMAL) .............................................................................. 941 Port Mode Control Register AL (PMCAL) .............................................................. 942 Port Register AH (PAH) ........................................................................................... 943 Port Mode Register AH (PMAH) ............................................................................... 944 Port Mode Control Register AH (PMCAH) ............................................................... 944 Port Register DL(PDL) .......................................................................................... 946 Port Mode Register DL(PMDL) ............................................................................. 947 Port Mode Control Register DL (PMCDL) ............................................................. 948 User's Manual U16580EE3V1UD00 25 Figure 20-67: Figure 20-68: Figure 20-69: Figure 20-70: Figure 20-71: Figure 20-72: Figure 20-73: Figure 20-74: Figure 20-75: Figure 20-76: Figure 20-77: Figure 20-78: Figure 20-79: Figure 20-80: Figure 20-81: Figure 20-82: Figure 21-1: Figure 22-1: Figure 22-2: Figure 23-1: Figure 23-2: Figure 23-3: Figure 24-1: Figure 24-2: Figure 24-3: Figure 24-4: Figure 24-5: Figure 24-6: Figure 24-7: Figure 24-8: Figure 24-9: Figure 24-10: Figure 24-11: Figure 24-12: Figure 24-13: Figure 24-14: Figure 24-15: Figure 24-16: Figure 25-1: Figure 25-2: Figure 25-3: Figure 25-4: Figure 25-5: Figure 25-6: Figure 25-7: Figure 25-8: Figure 25-9: Figure 25-10: Figure 25-11: Figure 25-12: Figure 25-13: Figure 25-14: Figure 25-15: Figure 25-16: Figure 25-17: Figure 25-18: Figure 25-19: Figure 25-20: 26 Port Register DH(PDH) ......................................................................................... 950 Port Mode Register DH(PMDH) ............................................................................ 951 Port Mode Control Register DH (PMCDH) ............................................................ 952 Port Register CS (PCS) ........................................................................................... 953 Port Mode Register CS (PMCS) ............................................................................... 954 Port Mode Control Register CS (PMCCS) ............................................................... 954 Port Register CT (PCT) ........................................................................................... 955 Port Mode Register CT (PMCT) ............................................................................... 956 Port Mode Control Register CT (PMCCT) ............................................................... 957 Port Register CM (PCM) .......................................................................................... 958 Port Mode Register CM (PMCM) .............................................................................. 959 Port Mode Control Register CM (PMCCM) .............................................................. 960 Port Register CD (PCD) .......................................................................................... 961 Port Mode Register CD (PMCD) .............................................................................. 963 Port Mode Control Register CD (PMCCD) .............................................................. 964 Noise Elimination Control Register (NRC) (1/2) ....................................................... 967 Reset Timing ............................................................................................................. 972 Internal RAM Parity Error Status Register (RAMERR) ............................................ 974 Internal RAM Parity Error Address Register (RAMPADD) ...................................... 975 Connecting N-Wire Type Emulator (IE-V850E1-CD-NW (N-Wire Card)) .................. 979 Pin Configuration of Emulator Connector (on Target System Side) .......................... 980 Example of Recommended Emulator Connection of V850E/PH2............................. 982 Flash Memory Mapping of PD70F3187................................................................... 986 Flash Memory Mapping of PD70F3447................................................................... 987 Environment Required for Writing Programs to Flash Memory ................................. 991 Communication with Dedicated Flash Programmer (UARTC0) ................................ 992 Communication with Dedicated Flash Programmer (CSIB0) .................................... 992 Communication with Dedicated Flash Programmer (CSIB0 + HS) ........................... 993 Procedure for Manipulating Flash Memory................................................................ 995 Selection of Communication Mode............................................................................ 996 Communication Commands ...................................................................................... 997 FLMD0 Pin Connection Example .............................................................................. 998 FLMD1 Pin Connection Example .............................................................................. 999 Conflict of Signals (Serial Interface Input Pin) ......................................................... 1000 Malfunction of Other Device .................................................................................... 1001 Conflict of Signals (RESET Pin) .............................................................................. 1002 Concept of Self Programming ................................................................................. 1003 Rewriting Entire Memory Area (Boot Swap)............................................................ 1005 Oscillator Recommendations................................................................................... 1009 AC Test Input/Output Waveform ............................................................................. 1011 AC Test Load Condition .......................................................................................... 1011 External Asynchronous Memory Access Read Timing............................................ 1013 External Asynchronous Memory Access Write Timing............................................ 1015 Reset Timing ........................................................................................................... 1016 Interrupt Timing ....................................................................................................... 1017 Timer P Characteristics ........................................................................................... 1018 Timer R Characteristics ........................................................................................... 1019 Timer T Characteristics ........................................................................................... 1020 CSIB Timing in Master Mode (CKP, DAP bits = 00B or 11B).................................. 1022 CSIB Timing in Master Mode (CKP, DAP bits = 01B or 10B).................................. 1022 CSIB Timing in Slave Mode (CKP, DAP bits = 00B or 11B).................................... 1023 CSIB Timing in Slave Mode (CKP, DAP bits = 01B or 10B).................................... 1023 CSI3 Timing in Master Mode (CKP, DAP bits = 00B or 11B) .................................. 1025 CSI3 Timing in Master Mode (CKP, DAP bits = 01B or 10B) .................................. 1025 CSI3 Timing in Slave Mode (CKP, DAP bits = 00B or 11B) .................................... 1026 CSI3 Timing in Slave Mode (CKP, DAP bits = 01B or 10B) .................................... 1026 CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 0, CSMD = 0) .. 1027 CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 0) .. 1027 User's Manual U16580EE3V1UD00 Figure 25-21: Figure 25-22: Figure 25-23: Figure 25-24: Figure 25-25: Figure 25-26: Figure 26-1: Figure 26-2: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 1) .. 1028 CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 0, CSMD = 0) .. 1028 CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 0) .. 1029 CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 1) .. 1029 Equivalent Circuit of Analog Inputs ......................................................................... 1030 Serial Write Operation Characteristics .................................................................... 1032 208-Pin Plastic QFP (Fine Pitch) (28 x 28).............................................................. 1033 256-Pin Plastic BGA (Fine Pitch) (21 x 21) ............................................................. 1034 User's Manual U16580EE3V1UD00 27 28 User's Manual U16580EE3V1UD00 List of Tables Table 1-1: Table 2-1: Table 2-2: Table 2-3: Table 2-4: Table 2-5: Table 3-1: Table 3-2: Table 3-3: Table 3-4: Table 3-5: Table 3-6: Table 4-1: Table 4-2: Table 6-1: Table 6-2: Table 6-3: Table 6-4: Table 7-1: Table 7-2: Table 8-1: Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 10-6: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 11-5: Table 11-6: Table 11-7: Table 12-1: Table 12-2: Table 12-3: Table 12-4: Table 13-1: Table 14-1: Table 14-2: Table 14-3: Table 14-4: Table 14-5: Table 14-6: Differences in Pin Assignment of 256-pin Plastic BGA .................................................. 39 Port Pins ......................................................................................................................... 49 Non-Port Pins ................................................................................................................. 54 Pin Status in Reset and Standby Mode.......................................................................... 60 I/O Circuit Types............................................................................................................. 76 Noise Suppression Timing.............................................................................................. 81 Program Registers.......................................................................................................... 87 System Register Numbers.............................................................................................. 88 Saturated Operation Results ......................................................................................... 92 Floating Point Arithmetic Unit Registers ......................................................................... 94 Peripheral I/O Registers ............................................................................................... 107 Programmable Peripheral I/O Registers....................................................................... 123 Number of Bus Access Clocks ..................................................................................... 151 Bus Priority Order ......................................................................................................... 179 Timer TMR Address Mapping for DMA Transfer .......................................................... 204 DMA Configuration of Serial Data Reception ............................................................... 208 DMA Configuration of Serial Data Transmission .......................................................... 212 Relations Between DMA Trigger Factors and DMA Completion Interrupts.................. 217 Interrupt/Exception Source List .................................................................................... 219 Addresses and Bits of Interrupt Control Registers ....................................................... 237 Operation Status in HALT Mode................................................................................... 257 Operation After Releasing HALT Mode by Interrupt Request Signal ........................... 258 Configuration of TMP0 to TMP8 ................................................................................... 260 Timer R Configuration .................................................................................................. 314 TMRn Count Clock and Count Delay ........................................................................... 325 List of Timer Outputs in Each Mode (1/2)..................................................................... 358 List of Interrupts in Each Mode (1/2) ............................................................................ 361 List of A/D Conversion Triggers, Peak Interrupts and Valley Interrupts in Each Mode 363 Positive Phase Operation Condition List ...................................................................... 432 Negative Phase Operation Condition List..................................................................... 432 Compare Register Value After Trough Reload (TRnDTC0 < TRnDTC1) ..................... 433 Compare Register Value After Trough Reload............................................................. 436 Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) ..................... 438 Compare Register Value After Trough Reload............................................................. 442 Timer T Configuration................................................................................................... 458 List of Timer T Registers .............................................................................................. 459 Capture/Compare Functions in Each Mode ................................................................. 461 Capture/Compare Functions in Each Mode ................................................................. 463 TMTn Count Clock and Count Delay............................................................................ 466 Counter Clear Operation .............................................................................................. 481 Capture/Compare Rewrite Methods in Each Mode ...................................................... 486 Timer ENC10 Configuration List................................................................................... 537 Timer ENC10 (TMENC10) Clear Conditions ................................................................ 540 Capture Trigger Signal to 16-Bit Capture Register....................................................... 556 List of Count Operations in UDC Mode ........................................................................ 558 AFO Configuration ....................................................................................................... 569 Assignment of A/D Conversion Result Registers to Analog Input Pins ........................ 582 Relationship Between Operation Mode and Trigger Mode........................................... 586 Correspondence Between Analog Input Pins and ADCRnm Register (A/D Trigger Select: 1 Buffer) ....................................................................................... 591 Correspondence Between Analog Input Pins and ADCRnm Register (A/D Trigger Select: 4 Buffers) ..................................................................................... 592 Correspondence Between Analog Input Pins and ADCRnm Register (A/D Trigger Scan)........................................................................................................ 594 Correspondence Between Analog Input Pins and ADCRnm Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer)).......................................................... 597 User's Manual U16580EE3V1UD00 29 Table 14-7: Table 14-8: Table 14-9: Table 14-10: Table 14-11: Table 15-1: Table 15-2: Table 15-3: Table 15-4: Table 15-5: Table 16-1: Table 17-1: Table 17-2: Table 17-3: Table 17-4: Table 17-5: Table 18-1: Table 18-2: Table 18-3: Table 18-4: Table 18-5: Table 18-6: Table 18-7: Table 18-8: Table 18-9: Table 18-10: Table 18-11: Table 18-12: Table 18-13: Table 18-14: Table 18-15: Table 18-16: Table 18-17: Table 18-18: Table 18-19: Table 18-20: Table 18-21: Table 18-22: Table 18-23: Table 18-1: Table 18-2: Table 18-3: Table 18-4: Table 18-5: Table 20-1: Table 20-2: Table 20-3: Table 20-4: Table 20-5: Table 20-6: Table 20-7: 30 Correspondence Between Analog Input Pins and ADCRnm Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers)) ........................................................ 598 Correspondence Between Analog Input Pins and ADCRnm Register (Scan Mode (Timer Trigger Scan))............................................................................... 600 Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Select: 1 Buffer) ................................................................................ 602 Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Select: 4 Buffers)) ............................................................................. 604 Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Scan) ................................................................................................ 606 Relation between UARTCn Register Settings and Data Format ................................. 619 Default Priorities of UARTCn Interrupts....................................................................... 625 Reception Error Causes .............................................................................................. 636 Baud Rate Generator Setting Data............................................................................... 641 Maximum/Minimum Allowable Baud Rate Error ........................................................... 643 CSIBn Configuration..................................................................................................... 645 Operation Modes .......................................................................................................... 695 Conditions Under Which Data Can Be Transferred in Slave Mode.............................. 702 Default Output Level of SCK3n Pin ............................................................................. 712 Default Output Level of SO3n Pin ................................................................................ 712 Default Output Level of SCS3n0 to SCS3n3 Pins ........................................................ 713 Overview of Functions .................................................................................................. 740 Frame types.................................................................................................................. 743 RTR frame settings....................................................................................................... 745 Frame format setting (IDE bit) and number of identifier (ID) bits.................................. 746 Data length setting........................................................................................................ 746 Operation in error status............................................................................................... 750 Definition of error frame fields ...................................................................................... 750 Definition of overload frame fields ................................................................................ 751 Determining bus priority................................................................................................ 752 Bit stuffing..................................................................................................................... 752 Error types .................................................................................................................... 753 Output timing of error frame ......................................................................................... 754 Types of error states..................................................................................................... 755 Error counter................................................................................................................. 756 Segment setting............................................................................................................ 759 Configuration of data bit time defined by CAN specification......................................... 760 CAN module base addresses....................................................................................... 764 List of CAN Controller registers .................................................................................... 765 CAN0 global and module registers............................................................................... 766 CAN0 message buffer registers ................................................................................... 767 CAN global register bit configuration ............................................................................ 767 CAN module register bit configuration.......................................................................... 768 Message buffer register bit configuration ..................................................................... 770 List of CAN module interrupt sources........................................................................... 827 Outline of the Receive/Transmit in Each Operation Mode ........................................... 830 Settable bit rate combinations ...................................................................................... 833 Representative examples of baud rate settings (fCANMOD = 8 MHz).................................................................................................... 836 Representative examples of baud rate settings (fCANMOD = 16 MHz).................................................................................................. 838 Port Type and Function Overview ................................................................................ 869 Peripheral Registers of I/O Ports................................................................................. 893 Peripheral Registers of Valid Edge Control ................................................................. 896 Alternate Function Pins and Port Types of Port 0 ........................................................ 897 Alternate Function Pins and Port Types of Port 1 ........................................................ 898 Alternate Function Pins and Port Types of Port 2 ........................................................ 902 Alternate Function Pins and Port Types of Port 3 ........................................................ 906 User's Manual U16580EE3V1UD00 Table 20-8: Table 20-9: Table 20-10: Table 20-11: Table 20-12: Table 20-13: Table 20-14: Table 20-15: Table 20-16: Table 20-17: Table 20-18: Table 20-19: Table 20-20: Table 20-21: Table 20-22: Table 20-23: Table 23-1: Table 24-1: Table 24-2: Table 24-3: Table 24-4: Table 24-5: Table 24-6: Table 24-7: Table 25-1: Table 25-2: Table 25-3: Table 25-4: Table 25-5: Table 25-6: Table 25-7: Table 25-8: Table 25-9: Table 25-10: Table 25-11: Table 25-12: Table 25-13: Table 25-14: Table 25-15: Table 25-16: Table 25-17: Table 25-18: Table 25-19: Table 25-20: Table 25-21: Table 27-1: Alternate Function Pins and Port Types of Port 4 ........................................................ 910 Alternate Function Pins and Port Types of Port 5 ........................................................ 913 Alternate Function Pins and Port Types of Port 6 ........................................................ 918 Alternate Function Pins and Port Types of Port 7 ........................................................ 924 Alternate Function Pins and Port Types of Port 8 ........................................................ 928 Alternate Function Pins and Port Types of Port 9 ........................................................ 932 Alternate Function Pins and Port Types of Port 10 ...................................................... 936 Alternate Function Pins and Port Types of Port AL ...................................................... 939 Alternate Function Pins and Port Types of Port AH ..................................................... 943 Alternate Function Pins and Port Types of Port DL...................................................... 945 Alternate Function Pins and Port Types of Port DH ..................................................... 949 Alternate Function Pins and Port Types of Port CS ..................................................... 953 Alternate Function Pins and Port Types of Port CT...................................................... 955 Alternate Function Pins and Port Types of Port CM..................................................... 958 Alternate Function Pins and Port Types of Port CD ..................................................... 961 Noise Elimination.......................................................................................................... 965 Pin Functions of Connector for IE-V850E1-CD-NW (on Target System Side) ............. 981 Rewrite Method ............................................................................................................ 988 Basic Functions ............................................................................................................ 989 Protection Functions..................................................................................................... 990 Signal Connections of Dedicated Flash Programmer (PG-FP4) .................................. 994 Communication Commands ......................................................................................... 997 Relationship Between FLMD0 and FLMD1 Pins and Operation Mode when Reset is Released............................................................................................... 999 Pins Used by Serial Interfaces ................................................................................... 1000 Absolute Maximum Ratings........................................................................................ 1007 Capacitance ............................................................................................................... 1008 Operating Conditions ................................................................................................. 1008 Oscillator Characteristics ........................................................................................... 1009 DC Characteristics...................................................................................................... 1010 External Asynchronous Memory Access Read Timing .............................................. 1012 External Asynchronous Memory Access Write Timing .............................................. 1014 Reset Timing ............................................................................................................. 1016 Interrupt Timing ......................................................................................................... 1017 Timer P Characteristics ............................................................................................. 1018 Timer R Characteristics ............................................................................................. 1019 Timer T Characteristics ............................................................................................. 1020 CSIB Characteristics (Master Mode) .......................................................................... 1021 CSIB Characteristics (Slave Mode) ............................................................................ 1021 CSI3 Characteristics (Master Mode) .......................................................................... 1024 CSI3 Characteristics (Slave Mode) ............................................................................ 1024 A/D Converter Characteristics ................................................................................... 1030 Analog Input Characteristics....................................................................................... 1030 Flash Memory Basic Characteristics .......................................................................... 1031 Flash Memory Programming Characteristics ............................................................. 1031 Serial Write Operation Characteristics ....................................................................... 1032 Soldering Conditions .................................................................................................. 1035 User's Manual U16580EE3V1UD00 31 32 User's Manual U16580EE3V1UD00 Chapter 1 Introduction The V850E/PH2 (PHOENIX-FNote) is a product of the NEC Electronics single-chip microcontrollers "V850 seriesTM". This chapter gives a short outline of the V850E/PH2 microcontroller. 1.1 Outline The V850E/PH2 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation. It uses the V850E1 CPU (NU85EFC) of the V850 Series including single-precision floating point unit, and has on-chip ROM, RAM, bus interface, DMA controller, a realtime pulse unit including 3-phase PWM timer for inverter control, various serial interfaces including AFCAN, and peripheral facilities such as A/D converters, as well as an on-chip debug interface. (1) V850E1 CPU The V850E1 CPU (NU85EFC) supports a RISC instruction set that enhances the performance of the V850 CPU, which is the CPU core integrated in the V850 Series, and has added instructions supporting high-level languages, such as C-language switch statement processing, table look-up branching, stack frame creation/deletion, and data conversion. This enhances the performance of both data processing and control. It is possible to use the software resources of the V850 CPU integrated system since the instruction codes of the V850E1 are upwardly compatible at the object code level with those of the V850 CPU. In addition, the V850E1 CPU (NU85EFC) incorporates a single-precision floating point unit, which supports high speed floating point arithmetic operations. (2) External memory interface function The V850E/PH2 microcontroller features n on-chip external memory interface including separately configured address (22 bits) and data (32 bits) buses. SRAM and ROM can be connected. (3) On-chip flash memory The V850E/PH2 microcontroller has a quickly accessible flash memory on-chip, that can shorten system development time since it is possible to rewrite a program with the V850E/PH2 microcontroller mounted in an application system. Moreover, it can greatly improve maintain ability after system ships. (4) A full range of development environment products A development environment system that includes an optimized C compiler, debugger, in-circuit emulator, simulator, system performance analyser, and other elements is also available. Note: PHOENIX-F is the European name of the V850E/PH2 microcontroller. User's Manual U16580EE3V1UD00 33 Chapter 1 Introduction 1.2 Device Features * Number of instructions: 96 * Instruction execution time: 15.625 ns (@ = 64 MHz) * General-purpose registers: 32 bits x 32 * Instruction set: V850E1 CPU (NU85EFC) (compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed) Single-precision floating point arithmetic operation Signed multiplication (16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits): 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions Load/store instructions with long/short format Signed load instructions * Memory space: 64 MB linear address space (common program/data) Chip select output function: 4 spaces Memory block division function: 2, 4, or 8 MB/block Programmable wait function Idle state insertion function * External bus interfaceNote1: 32-bit data bus (address/data separated) 22-bit address bus 4 programmable chip select areas 32-/16-/8-bit bus sizing function External wait function * Internal memory: Flash ROM: RAM: PD70F3187 512 KB 32 KB PD70F3447 384 KB 24 KB * Interrupts/exceptions: External interrupts: up to 14 (including NMI) Internal interrupts: up to 85 sources Exceptions: 1 source 8 programmable interrupt priority levels * Memory access controllerNote1: SRAM controller * DMA controller: 8 channels Transfer mode: Single transfer Transfer units: 8 bits or 16 bits (depending on peripheral) Maximum transfer count: 256 (28) Transfer target: internal RAM I/O Transfer request: On-chip peripheral I/O DMA transfer termination interrupt * I/O lines: Input ports: I/O ports: 34 User's Manual U16580EE3V1UD00 5 137 Chapter 1 Introduction * Timer: 16-bit timer for 3-phase PWM inverter control: 2 channels 16-bit up/down counter for 4-quadrant encoding: 1 channelNote 1 16-bit general purpose timers: 9 channels 16-bit general purpose timers with encoding capability: 2 channels * Serial interfaces: Asynchronous serial interface (UARTC): 2 channels Clocked serial interface (CSIB): up to 2 channelsNote 2 Queued clocked serial interface (CSI3): up to 2 channelsNote 2 FCAN interface (AFCAN): up to 2 channelsNote 2 * A/D converters: 10-bit resolution 2 x 10 channels * Random number generator: Automatic seed generation Fips/Maurer test passing * Clock generator: 16 MHz clock oscillator 4 fold PLL synthesizer for internal system clock * Power save modes: HALT mode * Auxiliary frequency output: Programmable by user software * Supply voltage: 1.5 V (internal power supply, clock generator) 3.3 V (external I/O pins, A/D converter) * Package 208-pin plastic LQFP (fine pitch) (28 x 28) 256-pin plastic BGA (21 x 21) * CMOS technology Notes: 1. Not available on PD70F3447 2. Only 1 channel on PD70F3447 User's Manual U16580EE3V1UD00 35 Chapter 1 Introduction 1.3 Applications The V850E/PH2 microcontroller is ideally suited for automotive applications, like electrical power steering and electric car control. It is also an excellent choice for other applications where a combination of general-purpose inverter control functions and CAN network support is required. 1.4 Ordering Information Part Number Package PD70F3187GD-64-LML 208-pin plastic LQFP (fine pitch) (28 x 28) PD70F3187GD(A1)-64-LML 208-pin plastic LQFP (fine pitch) (28 x 28) PD70F3187GD(A2)-64-LML 208-pin plastic LQFP (fine pitch) (28 x 28) PD70F3187F1(A2)-64-JN4 256-pin plastic BGA (21 x 21) PD70F3447F1(A2)-64-JN4 256-pin plastic BGA (21 x 21) 36 User's Manual U16580EE3V1UD00 Chapter 1 Introduction 1.5 Pin Configuration (Top View) 208-pin plastic LQFP (fine pitch) (28 x 28) PD70F3187GD-64-LML PD70F3187GD(A1)-64-LML PD70F3187GD(A2)-64-LML Pin Configuration 208-pin Plastic LQFP 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PAH4/A20 PAH3/A19 PAH2/A18 PAH1/A17 PAH0/A16 PAL15/A15 PAL14/A14 PAL13/A13 PAL12/A12 PCS3/CS3 PCS1/CS1 VSS34 VDD34 PAL11/A11 PAL10/A10 PAL9/A9 PAL8/A8 PAL7/A7 PAL6/A6 PAL5/A5 PAL4/A4 MODE0/FLMD0 VSS13 VDD13 PAL3/A3 PAL2/A2 PAL1/A1 PAL0/A0 PCS0/CS0 P42/SCKB0 P41/SOB0 P40/SIB0 P96/SCS313/SSB1 P95/SCS312/INTP11 P94/SCS311/INTP10 P93/SCS310/INTP9 VSS33 VDD33 P86/SCS303/SSB0 P85/SCS302/INTP8 P84/SCS301/INTP7 P83/SCS300/INTP6 P90/SI31 P91/SO31 P92/SCK31 P80/SI30 P81/SO30 P82/SCK30 P43/SIB1 P44/SOB1 P45/SCKB1 P33/TXDC1 Figure 1-1: 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 P32/RXDC1/INTP5 P31/TXDC0 P30/RXDC0/INTP4 P37/FCTXD1 P36/FCRXD1 P35/FCTXD0 P34/FCRXD0 VSS32 VDD32 P67/TOR17/TRTEVT1 P66/TOR16 P65/TOR15 P64/TOR14/TIR13 P63/TOR13/TIR12 VSS12 VDD12 DDO DDI DMS DRST DCK RESET CVDD X1 X2 CVSS P62/TOR12/TIR11 P61/TOR11/TIR10 P60/TOR10/TTRGR1 P57/TOR07 P56/TOR06 P55/TOR05 P54/TOR04 VSS31 VDD31 P53/TOR03 P52/TOR02 P51/TOR01 P50/TOR00 VSS11 VDD11 P102/TIUD0/TO0 P101/TCUD0/TICC01 P100/TCLR0/TICC00/TOP81 P75/TECRT1/AFO P74/TIT11/TEVTT0/TOT11/TENCT11 P73/TIT10/TTRGT0/TOT10/TENCT10 P72/TECRT0/INTP12 P71/TIT01/TTRGT1/TOT01/TENCT01 P70/TIT00/TEVTT1/TOT00/TENCT00 P27/TIP71/TEVTP6/TOP71 P26/TIP70/TTRGP6/TOP70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PAH5/A21 PCS4/CS4 PDL0/D0 PDL1/D1 PDL2/D2 PDL3/D3 VDD35 VSS35 PDL4/D4 PDL5/D5 PDL6/D6 PDL7/D7 VSS14 VDD14 PDL8/D8 PDL9/D9 PDL10/D10 PDL11/D11 PDL12/D12 PDL13/D13 PDL14/D14 PDL15/D15 VDD36 VSS36 PDH0/D16 PDH1/D17 PDH2/D18 PDH3/D19 PDH4/D20 PDH5/D21 PDH6/D22 PDH7/D23 PDH8/D24 PDH9/D25 PDH10/D26 PDH11/D27 PDH12/D28 VDD15 VSS15 PDH13/D29 PDH14/D30 PDH15/D31 VDD37 VSS37 PCM1 PCT5/WR PCM6 PCM7 PCT4/RD PCD2/BEN0 PCD3/BEN1 PCD4/BEN2 PCD5/BEN3 PCM0/WAIT MODE2 MODE1/FLMD1 AVSS0 ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 ANI08 ANI09 AVREF0 AVDD AVREF1 ANI19 ANI18 ANI17 ANI16 ANI15 ANI14 ANI13 ANI12 ANI11 ANI10 AVSS1 P00/NMI P01/INTP0/ESO0 P02/INTP1/ESO1 P03/INTP2/ADTRG0 P04/INTP3/ADTRG1 VDD10 VSS10 P10/TIP00/TEVTP1/TOP00 P11/TIP01/TTRGP1/TOP01 P12/TIP10/TTRGP0/TOP10 VDD30 VSS30 P13/TIP11/TEVTP0/TOP11 P14/TIP20/TEVTP3/TOP20 P15/TIP21/TTRGP3/TOP21 P16/TIP30/TTRGP2/TOP30 P17/TIP31/TEVTP2/TOP31 P20/TIP40/TEVTP5/TOP40 P21/TIP41/TTRGP5/TOP41 P22/TIP50/TTRGP4/TOP50 P23/TIP51/TEVTP4/TOP51 P24/TIP60/TEVTP7/TOP60 P25/TIP61/TTRGP7/TOP61 * User's Manual U16580EE3V1UD00 37 Chapter 1 * Introduction 256-pin plastic BGA (21 x 21) PD70F3187F1(A2)-JN4 PD70F3447F1(A2)-JN4 Figure 1-2: Pin Configuration 256-pin Plastic BGA (21 x 21) Top View Bottom View 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJKLMNPRTUVWY YWVUTRPNMLKJHGFEDCBA Index mark 38 Index mark User's Manual U16580EE3V1UD00 Chapter 1 Introduction Table 1-1: Pin No Differences in Pin Assignment of 256-pin Plastic BGA (1/4) Pin Function (Name) PD70F3187 Pin No Pin Function (Name) PD70F3447 PD70F3187 PD70F3447 A1 NC NC B1 NC NC A2 NC NC B2 NC NC A3 PCT4/RD PCT4 B3 PCD5/BEN3 PCD5 A4 PCT5/WR PCT5 B4 PCD2/BEN0 PCD2 A5 PDH15/D31 PDH15 B5 PCM6 PCM6 A6 PDH13/D29 PDH13 B6 PCM1 PCM1 A7 PDH11/D27 PDH11 B7 PDH14/D30 PDH14 A8 PDH9/D25 PDH9 B8 PDH12/D28 PDH12 A9 PDH8/D24 PDH8 B9 PDH10/D26 PDH10 A10 PDH6/D22 PDH6 B10 PDH7/D23 PDH7 A11 PDH3/D19 PDH3 B11 PDH5/D21 PDH5 A12 PDH0/D16 PDH0 B12 PDH1/D17 PDH1 A13 PDL15/D15 PDL15 B13 PDL13/D13 PDL13 A14 PDL14/D14 PDL14 B14 PDL12/D12 PDL12 A15 PDL9/D9 PDL9 B15 PDL8/D8 PDL8 A16 PDL5/D5 PDL5 B16 PDL4/D4 PDL4 A17 PDL1/D1 PDL1 B17 PDL3/D3 PDL3 A18 PDL0/D0 PDL0 B18 PCS4/CS4 PCS4 A19 NC NC B19 NC NC A20 NC NC B20 NC NC C1 AVSS0 AVSS0 D1 AVSS0 AVSS0 C2 MODE1 MODE1 D2 AVSS0 AVSS0 C3 MODE2 MODE2 D3 AVSS0 AVSS0 C4 PCD4/BEN2 PCD4 D4 PCM0/WAIT PCM0 C5 PCM7 PCM7 D5 PCD3/BEN1 PCD3 C6 VSS37 VSS37 D6 VDD37 VDD37 C7 VSS37 VSS37 D7 VDD37 VDD37 C8 VSS15 VSS15 D8 VDD15 VDD15 C9 VSS15 VSS15 D9 VDD15 VDD15 C10 PDH4/D20 PDH4 D10 PDH2/D18 PDH2 C11 VSS36 VSS36 D11 VDD36 VDD36 C12 VSS36 VSS36 D12 VDD36 VDD36 C13 PDL11/D11 PDL11 D13 PDL10/D10 PDL10 C14 VSS14 VSS14 D14 VDD14 VDD14 C15 PDL7/D7 PDL7 D15 PDL6/D6 PDL6 C16 VSS35 VSS35 D16 VDD35 VDD35 C17 VSS35 VSS35 D17 VDD35 VDD35 C18 PDL2/D2 PDL2 D18 PAH4/A20 PAH4 User's Manual U16580EE3V1UD00 39 Chapter 1 Table 1-1: Pin No Differences in Pin Assignment of 256-pin Plastic BGA (2/4) Pin Function (Name) PD70F3187 40 Introduction Pin No PD70F3447 Pin Function (Name) PD70F3187 PD70F3447 C19 PAH5/A21 PAH5 D19 PAH3/A19 PAH3 C20 NC NC D20 PAL14/A14 PAL14 E1 ANI00 ANI00 F1 ANI03 ANI03 E2 ANI02 ANI02 F2 ANI06 ANI06 E3 ANI01 ANI01 F3 ANI05 ANI05 E4 AVSS0 AVSS0 F4 ANI04 ANI04 E17 PAH0/A16 PAH0 F17 PAL12/A12 PAL12 E18 PAH2/A18 PAH2 F18 PAL15/A15 PAL15 E19 PAH1/A17 PAH1 F19 PAL13/A13 PAL13 E20 PCS3/CS3 PCS3 F20 PAL11/A11 PAL11 G1 ANI07 ANI07 H1 ANI18 ANI18 G2 ANI09 ANI09 H2 ANI19 ANI19 G3 ANI08 ANI08 H3 AVDD AVDD G4 AVREF0 AVREF0 H4 AVREF1 AVREF1 G17 VDD34 VDD34 H17 VDD34 VDD34 G18 VSS34 VSS34 H18 VSS34 VSS34 G19 PCS1/CS1 PCS1 H19 PAL10/A10 PAL10 G20 PAL9/A9 PAL9 H20 PAL6/A6 PAL6 J1 ANI17 ANI17 K1 ANI13 ANI13 J2 ANI14 ANI14 K2 ANI10 ANI10 J3 ANI15 ANI15 K3 ANI11 ANI11 J4 ANI16 ANI16 K4 ANI12 ANI12 J17 PAL5/A5 PAL5 K17 VDD13 VDD13 J18 PAL8/A8 PAL8 K18 VSS13 VSS13 J19 PAL7/A7 PAL7 K19 PAL4/A4 PAL4 J20 MODE0 MODE0 K20 PAL2/A2 PAL2 L1 AVSS1 AVSS1 M1 P01/INTP0/ESO0 P01/INTP0/ESO0 L2 AVSS1 AVSS1 M2 P00/NMI P00/NMI L3 AVSS1 AVSS1 M3 VSS10 VSS10 L4 AVSS1 AVSS1 M4 VDD10 VDD10 L17 VDD13 VDD13 M17 P95/SCS312/INTP1 P95/INTP11 1 L18 VSS13 VSS13 M18 PAL0 PAL0 L19 PAL3/A3 PAL3 M19 PCS0 PCS0 L20 PAL1/A1 PAL1 M20 P42/SCKB0 P42/SCKB0 N1 P02/INTP1/ESO1 P02/INTP1/ESO1 P1 P04/INTP3/ ADTRG1 P04/INTP3/ ADTRG1 N2 P03/INTP2/ ADTRG0 P03/INTP2/ ADTRG0 P2 P10/TIP00/ TEVTP1/TOP00 P10/TIP00/ TEVTP1/TOP00 N3 VSS10 VSS10 P3 VSS30 VSS30 User's Manual U16580EE3V1UD00 Chapter 1 Introduction Table 1-1: Pin No Differences in Pin Assignment of 256-pin Plastic BGA (3/4) Pin Function (Name) PD70F3187 Pin No PD70F3447 Pin Function (Name) PD70F3187 PD70F3447 N4 VDD10 VDD10 P4 VDD30 VDD30 N17 VDD33 VDD33 P17 VDD33 VDD33 N18 VSS33 VSS33 P18 VSS33 VSS33 N19 P41/SOB0 P41/SOB0 P19 P96/SCS313/SSB1 P96 N20 P40/SIB0 P40/SIB0 P20 P94/SCS311/ INTP10 R1 P11/TIP01/ TTRGP1/TOP01 P11/TIP01/ TTRGP1/TOP01 T1 P13/TIP11/TEVTP0/ P13/TIP11/TEVTP0/ TOP11 TOP11 R2 P12/TIP10/ TTRGP0/TOP10 P12/TIP10/ TTRGP0/TOP10 T2 P14/TIP20/TEVTP3/ P14/TIP20/TEVTP3/ TOP20 TOP20 R3 VSS30 VSS30 T3 P16/TIP30/TTRGP2/ P16/TIP30/TTRGP2/ TOP30 TOP30 R4 VDD30 VDD30 T4 P21/TIP41/TTRGP5/ P21/TIP41/TTRGP5/ TOP41 TOP41 R17 P83/SCS300/INTP6 P83/SCS300/INTP6 T17 P80/SI30 R18 P86/SCS303/SSB0 P86/SCS303/SSB0 T18 P84/SCS301/INTP7 P84/SCS301/INTP7 R19 P93/SCS310/INTP9 P93/INTP9 T19 P90/SI31 P90 R20 P85/SCS302/INTP8 P85/SCS302/INTP8 T20 P91/SO31 P91 U1 P15/TIP21/ TTRGP3/TOP21 P15/TIP21/ TTRGP3/TOP21 V1 P20/TIP40/ TEVTP5/TOP40 P20/TIP40/ TEVTP5/TOP40 U2 P17/TIP31/ TEVTP2/TOP31 P17/TIP31/ TEVTP2/TOP31 V2 P23/TIP51/ TEVTP4/TOP51 P23/TIP51/ TEVTP4/TOP51 U3 P22/TIP50/ TTRGP4/TOP50 P22/TIP50/ TTRGP4/TOP50 V3 P24/TIP60/ TEVTP7/TOP60 P24/TIP60/ TEVTP7/TOP60 U4 P25/TIP61/ TTRGP7/TOP61 P25/TIP61/ TTRGP7/TOP61 V4 P70/TIT00/TEVTT1/ P70/TIT00/TEVTT1/ TOT00/TENCT00 TOT00/TENCT00 U5 P71/TIT01/TTRGT1/ P71/TIT01/TTRGT1/ TOT01/TENCT01 TOT01/TENCT01 V5 P74/TIT11/TEVTT0/ P74/TIT11/TEVTT0/ TOT11/TENCT11 TOT11/TENCT11 U6 P75 P75 V6 P102/TIUD1/TO1 P102 U7 VDD11 VDD11 V7 VSS11 VSS11 U8 VDD31 VDD31 V8 VSS31 VSS31 U9 P62/TOR12/TIR11 P62/TOR12/TIR11 V9 P61/TOR11/TIR10 P61/TOR11/TIR10 U10 VSS31 VSS31 V10 VSS31 VSS31 U11 DCK DCK V11 RESET RESET U12 VDD12 VDD12 V12 VSS12 VSS12 U13 VDD12 VDD12 V13 VSS12 VSS12 U14 VDD32 VDD32 V14 VSS32 VSS32 U15 VDD32 VDD32 V15 VSS32 VSS32 U16 P32/RXDC1/INTP5 P32/INTP5 V16 P67/TOR17/ TEVTR1 P67/TOR17/ TEVTR1 U17 P81/SO30 P81/SO30 V17 P31/TXDC0 P31/TXDC0 U18 P82/SCK30 P82/SCK30 V18 P30/RXDC0/INTP4 P30/RXDC0/INTP4 U19 P44/SOB1 P44 V19 P43/SIB1 User's Manual U16580EE3V1UD00 P94/INTP10 P80/SI30 P43 41 Chapter 1 Table 1-1: Pin No Differences in Pin Assignment of 256-pin Plastic BGA (4/4) Pin Function (Name) PD70F3187 42 Introduction Pin No Pin Function (Name) PD70F3447 PD70F3187 PD70F3447 U20 P92/SCK31 P92 V20 P45/SCKB1 P45 W1 NC NC Y1 NC NC W2 P26 P26 Y2 NC NC W3 P27/TIP71/ TEVTP6/TOP71 P27/TIP71/ TEVTP6/TOP71 Y3 P72/TECRT0/ INTP12 P72/INTP12 W4 P73/TIT10/TTRGT0/ P73/TIT10/TTRGT0/ TOT10/TENCT10 TOT10/TENCT10 Y4 P100/TCLR1/ TICC10/TOP81 P100/TOP81 W5 P101/TCUD1/ TICC11 P101 Y5 P50/TOR00 P50/TOR00 W6 P51/TOR01 P51/TOR01 Y6 P52/TOR02 P52/TOR02 W7 P53/TOR03 P53/TOR03 Y7 P54/TOR04 P54/TOR04 W8 P55/TOR05 P55/TOR05 Y8 P56/TOR06 P56/TOR06 W9 P57/TOR07 P57/TOR07 Y9 P60/TOR10/TTRGR P60/TOR10/TTRGR 1 1 W10 VSS31 VSS31 Y10 VSS31 VSS31 W11 X2 X2 Y11 CVSS CVSS W12 X1 X1 Y12 CVDD CVDD W13 DMS DMS Y13 DRST DRST W14 DDO DDO Y14 DDI DDI W15 P65/TOR15 P65/TOR15 Y15 P63/TOR13/TIR12 P63/TOR13/TIR12 W16 P66/TOR16 P66/TOR16 Y16 P64/TOR14/TIR13 P64/TOR14/TIR13 W17 P34/FCRXD0 P34/FCRXD0 Y17 P35/FCTXD0 P35/FCTXD0 W18 P36/FCRXD1 P36 Y18 P37/FCTXD1 P37 W19 P33/TXDC1 P33 Y19 NC NC W20 NC NC Y20 NC NC User's Manual U16580EE3V1UD00 Chapter 1 Introduction Pin Identification A0 to A21: Address bus ADTRG0, ADTRG1: A/D trigger input AFO: Auxiliary frequency output ANI00 to ANI09, ANI10 to ANI19: Analog input Analog power supply AVDD: Analog reference voltage AVREF0, AVREF1: Analog ground AVSS0, AVSS1: BEN0 to BEN3: Byte enable CS0, CS1, CS3, CS4: Chip select Power supply for oscillator CVDD: Oscillator ground CVSS: D0 to D31: Data bus DCK: Debug clock input DDI: Debug data input DDO: Debug data output DMS: Debug mode select Debug reset DRST: ESO0, ESO1: Emergency shut-off FCRXD0, FCRXD1: FCAN receive data input FCTXD0, FCTXD1: FCAN transmit data output INTP0 to INTP12: External interrupt request MODE0 to MODE2: Mode NMI: Non-maskable interrupt request NC: Not connected P00 to P04: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30 to P37: Port 3 P40 to P45: Port 4 P50 to P57: Port 5 P60 to P67: Port 6 P70 to P75: Port 7 P80 to P86: Port 8 P90 to P96: Port 9 P100 to P102: Port 10 PAL0 to PAL15: Port AL PAH0 to PAH5: Port AH PCD2 to PCD5: Port CD PCM0, PCM1, PCM6, PCM7: Port CM PCS0, PCS1, PCS3, PCS4: Port CS PCT4, PCT5: Port CT PDL0 to PDL15: Port DH PDH0 to PDH15: Port DL Read strobe RD: Reset RESET: RXDC0, RXDC1: Receive data input SCK30, SCK31, Serial clock SCKB0, SCKB1: SCS300 to SCS303, SCS310 to SCS313: Serial chip select SI30, SI31, SIB0, SIB1: Serial data input SO30, SO31, SOB0, SOB1: Serial data output SSB0, SSB1: Serial slave select input TCLR1: Timer clear TCUD1: Timer control pulse input TECRT0, TECRT1: Timer external clear TENCT00, TENCT01, TENCT10, TENCT11: Timer encoder input TEVTP0 to TEVTP7, TEVTR1, TEVTT0, TEVTT1: Timer event input TICC10, TICC11 TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31, TIP40, TIP41, TIP50, TIP51, TIP60, TIP61, TIP70, TIP71, TIR10 to TIR13, TIT00, TIT01, TIT10, TIT11: Timer input TIUD1: Timer count pulse input TO1, TOP00, TOP01, TOP10, TOP11, TOP20, TOP21, TOP30, TOP31, TOP40, TOP41, TOP50, TOP51, TOP60, TOP61, TOP70, TOP71, TOP81, TOR00 to TOR07, TOR10 to TOR17, TOT00, TOT01, TOT10, TOT11: Timer output TTRGP0 to TTRGP7, TTRGR1, TTRGT0, TTRGT1: Timer trigger input TXDC0, TXDC1: Transmit data output Power supply for CPU VDD10 to VDD15: VDD30 to VDD37: I/O buffers power supply CPU Ground VSS10 to VSS15: VSS30 to VSS37: I/O buffers ground Wait WAIT: Write strobe WR: X1, X2: Crystal User's Manual U16580EE3V1UD00 43 Chapter 1 Introduction 1.6 Function Blocks 1.6.1 Internal block diagrams Figure 1-3: Internal Block Diagram of PD70F3187 NMI INTP0 to INTP12 ESO0, ESO1 TTRGR1 TIR10 to TIR13 TIP00 to TIP70 TIP01 to TIP71 TEVTP0 to TEVTP8 TTRGP0 to TTRGP8 TIT00, TIT01 TIT10, TIT11 TENCT00, TENCT01, TECRT0 TENCT10, TENCT11, TECRT1 TEVTT0, TEVTT1 TTRGT0, TTRGT1 TICC10 TICC11 TCLR1 TCUD1,TIUD1 TOR00 to TOR07 TOR10 to TOR17 TOP00 to TOP70 TOP01 to TOP81 TOT00, TOT01 TOT10, TOT11 TO1 INTC ROM CPU PC RPU 32-bit Barrel Shifter 512 KB MEMC Instruction Queue SRAM RD WR ROM WAIT Floating Point Unit BE0 to BE3 System Registers Multiplier 32 x 32 64 RAM TMR: 2ch BCU CS0, CS1 CS3, CS4 D0 to D31 General Registers TMP: 9ch TMT: 2ch A0 to A21 ALU 32-bit x 32 32 KB TMENC10:1ch DCU DCK, DMS DDI, DDO DRST DMAC ANI00 to ANI09 TXDC0 RXDC0 UARTC0 TXDC1 RXDC1 UARTC1 A/D Converter 0 Ports ADTRG0 AVDD AVSS0 AVREF0 44 CSI30 SO31 SI31 SCK31 CSC310 to CSC313 CSI31 FCRXD0 FCTXD0 FCAN0 RNG FCRXD1 FCTXD1 FCAN1 BRG2 User's Manual U16580EE3V1UD00 PDL0 to PDL15 PDH0 to PDH15 PAH0 to PAH5 AFO PAL0 to PAL15 PCT4, PCT5 PCD2 to PCD5 P90 to P96 P100 to P102 PCS0, PCS1, PCS3, PCS4 SO30 SI30 SCK30 CSC300 to CSC303 PCM0, PCM1, PCM6, PCM7 BRG1 P80 to P86 P60 to P67 P70 to P75 P40 to P45 P50 to P57 P30 to P37 CSIB1 BRG0 P20 to P27 SOB1 SIB1 SCKB1 SSB1 P10 to P17 CSIB0 P00 to P04 ANI10 to ANI19 SOB0 SIB0 SCKB0 SSB0 A/D Converter 1 ADTRG1 AVDD AVSS1 AVREF1 RESET MODEn Clock Generator & System Control X1 X2 VDD1 VSS1 VDD3 VSS3 CVDD CVSS Chapter 1 Introduction Internal Block Diagram of PD70F3447 Figure 1-4: NMI INTP0 to INTP12 ESO0, ESO1 TTRGR1 TIR10 to TIR13 TIP00 to TIP70 TIP01 to TIP71 TEVTP0 to TEVTP8 TTRGP0 to TTRGP8 TIT00, TIT01 TIT10, TIT11 TECRT0 TECRT1 TEVTT0, TEVTT1 TTRGT0, TTRGT1 INTC ROM CPU BCU Instruction Queue PC RPU 32-bit Barrel Shifter 384 KB Floating Point Unit System Registers Multiplier 32 x 32 64 RAM TMR: 2ch General Registers TMP: 9ch TMT: 2ch TOR00 to TOR07 TOR10 to TOR17 TOP00 to TOP70 TOP01 to TOP81 TOT00, TOT01 TOT10, TOT11 ALU 32-bit x 32 24 KB DCU DCK, DMS DDI, DDO DRST DMAC ANI00 to ANI09 TXDC0 RXDC0 UARTC0 TXDC1 RXDC1 UARTC1 A/D Converter 0 Ports ADTRG0 AVDD AVSS0 AVREF0 FCAN0 AFO User's Manual U16580EE3V1UD00 PDL0 to PDL15 PDH0 to PDH15 PAH0 to PAH5 PAL0 to PAL15 PCT4, PCT5 PCD2 to PCD5 P90 to P96 PCS0, PCS1, PCS3, PCS4 FCRXD0 FCTXD0 BRG2 PCM0, PCM1, PCM6, PCM7 CSI30 P100 to P102 BRG1 SO30 SI30 SCK30 CSC300 to CSC303 P80 to P86 P60 to P67 P70 to P75 P40 to P45 P50 to P57 P30 to P37 P20 to P27 BRG0 P10 to P17 CSIB0 P00 to P04 ANI10 to ANI19 SOB0 SIB0 SCKB0 SSB0 A/D Converter 1 ADTRG1 AVDD AVSS1 AVREF1 RESET MODEn Clock Generator & System Control X1 X2 VDD1 VSS1 VDD3 VSS3 CVDD CVSS 45 Chapter 1 Introduction 1.6.2 On-chip units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions. (2) Bus control unit (BCU) The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue in the CPU. The BCU controls a memory controller (MEMC) and DMA controller (DMAC) and performs external memory access and DMA transfer. (a) Memory controller (MEMC)Note2 The MEMC controls SRAM, ROM, and various I/O for external memory expansion. * SRAM, external ROM, external I/O interface Supports access to SRAM, external ROM, and external I/O. (b) DMA controller (DMAC) The DMAC performs data transfers b/w internal on-chip RAM and peripheral I/O. For this purpose eight DMA channels are provided for particular transfer functions of serial I/O interfaces, real-time pulse unit (TMR), and A/D converter. (3) ROM There is on-chip flash memory of 512 KB provided in the PD70F3187, and 384 KB in the PD70F3447. On an instruction fetch, the ROM can be accessed by the CPU in one clock. When single-chip mode 0 or flash memory programming mode is set, ROM is mapped starting from address 00000000H. When single-chip mode 1Note2 is set, it is mapped starting from address 00100000H. ROM cannot be accessed if ROM-less modeNote2 is set. (4) RAM There is on-chip RAM of 32 KB provided in the PD70F3187, and 24 KB in the PD70F3447. Onchip RAM is mapped starting from address 03FF0000H for both, PD70F3187 and PD70F3447. It can be accessed by the CPU in one clock on an instruction fetch or data access. (5) Interrupt controller (INTC) The INTC services hardware interrupt requests from on-chip peripheral I/O and external sources (NMI, INTP0 to INTP12). Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple-interrupt servicing control can be performed for interrupt sources 46 User's Manual U16580EE3V1UD00 Chapter 1 Introduction (6) Clock generator (CG) The CG provides a frequency that is 4 times the input clock (fX) (using the on-chip PLL) as the internal system clock (fCPU). As the input clock, connect an external crystal or resonator to pins X1 and X2 or input an external clock from the X1 pin. (7) Real-time pulse unit (RPU) The RPU incorporates a 2-channel 16-bit timer (TMR) for 3/6-phase sine wave PWM inverter control, an 1-channel 16-bit up/down counter (TMENC10), PD70F3187 only and a 2-channel 16-bit up/down counter (TMT) that can be used for 2-phase encoder input or as a general-purpose timer, a 9-channel 16-bit general-purpose timer unit (TMP). The RPU can measure pulse interval or frequency and can output programmable pulses. (8) Serial interface (SIO) The serial interfaces consist of 2 channels asynchronous serial interface C (UARTC), up to 2 channels clocked serial interface B (CSIB), up to 2 channels clocked serial interface 3 (CSI3), and up to 2 channels FCAN interface (AFCAN). The UARTC performs data transfer using pins TXDCn and RXDCn (n = 0, 1). The CSIB performs data transfer using pins SOBn, SIBn, SCKBn, SSIn, and SSOnNote1. The CSI3 performs data transfer using pins SO3n, SI3n, SCK3n, SCS3n0 to SCS3Note1. The AFCAN performs data transfer using pins FCTXDn and FCRXDnNote1. (9) Baud rate generator (BRG) The baud rate generator comprises 3 channels of 8-bit counters and comparators that can be used for clock supply of serial interfaces (CSIB), auxiliary frequency output (AFO) or interval timer. (10) A/D converter (ADC) The two units of high-speed, high-resolution 10-bit A/D converter include 10 analog input pins for each unit. Conversion is performed using the successive approximation method. (11) Random number generator (RNG) For encryption purpose a random number generator is provided. (12) Debug control unit (DCU) On-chip debugging can be performed via a debug control unit (n-wire interface). Notes: 1. n = 0, 1 for PD70F3187 n = 0 for PD70F3447 2. Not available on PD70F3447 User's Manual U16580EE3V1UD00 47 Chapter 1 Introduction (13) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Control Function PD70F3187 48 PD70F3447 Port 0 5-bit input NMI input, external interrupt input, A/D converter external trigger input, emergency shut-off input Port 1 8-bit I/O Real-time pulse unit I/O Port 2 8-bit I/O Real-time pulse unit I/O Port 3 8-bit I/O Serial interface I/O, external interrupt input Port 4 6-bit I/O Serial interface I/O Port 5 8-bit I/O Real-time pulse unit I/O Port 6 8-bit I/O Real-time pulse unit I/O Port 7 6-bit I/O Real-time pulse unit I/O, external interrupt input Port 8 7-bit I/O Serial interface I/O, external interrupt input Port 9 7-bit I/O Serial interface I/O, external interrupt input Port 10 3-bit I/O Real-time pulse unit I/O Port AL 16-bit I/O External address bus None Port AH 6-bit I/O External address bus None Port DL 16-bit I/O External data bus None Port DH 16-bit I/O External data bus None Port CD 4-bit I/O External bus interface control signal output None Port CM 4-bit I/O Wait insertion signal input None Port CS 4-bit I/O External bus interface control signal output None Port CT 2-bit I/O External bus interface control signal output None External interrupt input User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of the V850E/PH2 microcontroller pins are listed below. These pins can be divided into port pins and non-port pins according to their functions. (1) Port pins Table 2-1: Pin Name I/O Port Pins (1/5) Function Alternate Function PD70F3187 P00 I P01 Port 0 5-bit input-only port NMI INTP0, ESO0 P02 INTP1, ESO1 P03 INTP2, ADTRG0 P04 INTP3, ADTRG1 P10 I/O P11 P12 Port 1 8-bit I/O port Input or output direction can be specified in 1-bit units PD70F3447 TIP00, TEVTP1, TOP00 TIP01, TTRGP1, TOP01 TIP10, TTRGP0, TOP10 P13 TIP11, TEVTP0, TOP11 P14 TIP20, TEVTP3, TOP20 P15 TIP21, TTRGP3, TOP21 P16 TIP30, TTRGP2, TOP30 P17 TIP31, TEVTP2, TOP31 P20 I/O P21 P22 Port 2 8-bit I/O port Input or output direction can be specified in 1-bit units TIP40, TEVTP5, TOP40 TIP41, TTRGP5, TOP41 TIP50, TTRGP4, TOP50 P23 TIP51, TEVTP4, TOP51 P24 TIP60, TEVTP7, TOP60 P25 TIP61, TTRGP7, TOP61 P26 TIP70, TTRGP6, TOP70 P27 TIP71, TEVTP6, TOP71 P30 P31 P32 I/O Port 3 8-bit I/O port Input or output direction can be specified in 1-bit units RXDC0, INTP4 TXDC0 RXDC1, INTP5 P33 TXDC1 P34 FCRXD0 P35 FCTXD0 P36 FCRXD1 - P37 FCTXD1 - User's Manual U16580EE3V1UD00 49 Chapter 2 Pin Functions Table 2-1: Pin Name I/O Port Pins (2/5) Function Alternate Function PD70F3187 P40 I/O P41 P42 Port 4 6-bit I/O port Input or output direction can be specified in 1-bit units PD70F3447 SIB0 SOB0 SCKB0 P43 SIB1 - P44 SOB1 - P45 SCKB1 - P50 I/O P51 P52 Port 5 8-bit I/O port Input or output direction can be specified in 1-bit units TOR00 TOR01 TOR02 P53 TOR03 P54 TOR04 P55 TOR05 P56 TOR06 P57 TOR07 P60 I/O P61 P62 Port 6 8-bit I/O port Input or output direction can be specified in 1-bit units TOR10, TTRGR1 TOR11, TIR10 TOR12, TIR11 P63 TOR13, TIR12 P64 TOR14, TIR13 P65 TOR15 P66 TOR16 P67 TOR17, TEVTR1 P70 I/O P71 P72 Port 7 6-bit I/O port Input or output direction can be specified in 1-bit units TIT00, TEVTT1, TOT00, TENCT00 TIT01, TTRGT1, TOT01, TENCT01 TECRT0, INTP12 P73 TIT10, TTRGT0, TOT10, TENCT10 P74 TIT11, TEVTT0, TOT11, TENCT11 P75 TECRT1, AFO P80 P81 P82 I/O Port 8 7-bit I/O port Input or output direction can be specified in 1-bit units SI30 SO30 SCK30 P83 SCS300, INTP6 P84 SCS301, INTP7 P85 SCS302, INTP8 P86 SCS303, SSB0 50 User's Manual U16580EE3V1UD00 Pin Name I/O Chapter 2 Pin Functions Table 2-1: Port Pins (3/5) Function Alternate Function PD70F3187 P90 I/O SI31 - SO31 - SCK31 - P93 SCS310, INTP9 INTP9 P94 SCS311, INTP10 INTP10 P95 SCS312, INTP11 INTP11 P96 SCS313, SSB1 - TCLR1, TICC10, TOP81 TOP81 TCUD1, TICC11 - TIUD1, TO1 - A0 - P91 P92 P100 I/O P101 Port 9 7-bit I/O port Input or output direction can be specified in 1-bit units PD70F3447 Port 10 3-bit I/O port Input or output direction can be specified in 1-bit units P102 PAL0 I/O PAL1 PAL2 Port AL 16-bit I/O port Input or output direction can be specified in 1-bit units A1 A2 PAL3 A3 PAL4 A4 PAL5 A5 PAL6 A6 PAL7 A7 PAL8 A8 PAL9 A9 PAL10 A10 PAL11 A11 PAL12 A12 PAL13 A13 PAL14 A14 PAL15 A15 PAH0 PAH1 PAH2 I/O Port AH 6-bit I/O port Input or output direction can be specified in 1-bit units A16 - A17 A18 PAH3 A19 PAH4 A20 PAH5 A21 User's Manual U16580EE3V1UD00 51 Chapter 2 Pin Functions Table 2-1: Pin Name I/O Port Pins (4/5) Function Alternate Function PD70F3187 PDL0 I/O PDL1 PDL2 Port DL 16-bit I/O port Input or output direction can be specified in 1-bit units D0 D2 D3 PDL4 D4 PDL5 D5 PDL6 D6 PDL7 D7 PDL8 D8 PDL9 D9 PDL10 D10 PDL11 D11 PDL12 D12 PDL13 D13 PDL14 D14 PDL15 D15 I/O PDH1 PDH2 Port DH 16-bit I/O port Input or output direction can be specified in 1-bit units D16 D18 D19 PDH4 D20 PDH5 D21 PDH6 D22 PDH7 D23 PDH8 D24 PDH9 D25 PDH10 D26 PDH11 D27 PDH12 D28 PDH13 D29 PDH14 D30 PDH15 D31 PCD3 PCD4 PCD5 52 I/O Port CD 4-bit I/O port Input or output direction can be specified in 1-bit units - D17 PDH3 PCD2 - D1 PDL3 PDH0 PD70F3447 BEN0 BEN1 BEN2 BEN3 User's Manual U16580EE3V1UD00 - Pin Name I/O Chapter 2 Pin Functions Table 2-1: Port Pins (5/5) Function Alternate Function PD70F3187 PCM0 I/O PCM1 PCM6 Port CM 4-bit I/O port Input or output direction can be specified in 1-bit units PCM7 PCS0 I/O PCS3 Port CS 4-bit I/O port Input or output direction can be specified in 1-bit units PCS4 PCT5 - - - - PCS1 PCT4 WAIT PD70F3447 CS0 - CS1 CS3 CS4 I/O Port CT 2-bit I/O port Input or output direction can be specified in 1-bit units RD - WR - User's Manual U16580EE3V1UD00 53 Chapter 2 Pin Functions (2) Non-port pins Table 2-2: Pin Name I/O Non-Port Pins (1/6) Function Alternate Function PD70F3187 A0 to A15Note O 22-bit external address bus PAL0 to PAL15 PAH0 to PAH5 A16 to A21Note ADTRG0 I A/D conversion start trigger (ADC0) P03, INTP2 ADTRG1 I A/D conversion start trigger (ADC1) P04, INTP3 AFO O Auxiliary frequency output P75, TECRT1 ANI00 to ANI09 I Analog input channels (ADC0) - ANI10 to ANI19 I Analog input channels (ADC1) - AVDD - Positive power supply (3.3 V) (ADC0, ADC1) - AVREF0 I Reference voltage input (ADC0) - AVREF1 I Reference voltage input (ADC1) - AVSS0 - Power supply ground (ADC0) - AVSS1 - Power supply ground (ADC1) - BEN0Note O External byte enable output PCD2 BEN1Note PCD3 BEN2Note PCD4 BEN3Note PCD5 CS0Note O Chip select signal output PCS0 CS1Note PCS1 CS3Note PCS3 CS4Note PCS4 CVDD - Oscillator power supply (1.5 V) - CVSS - Oscillator power supply ground - 32-bit external data bus PDL0 to PDL15 D0 to D15Note I/O PDH0 to PDH15 D16 to D31Note DCK I N-wire interface clock - DDI I N-wire data input and reset mode selection - DDO O N-wire data output - DMS I N-wire mode select - DRST I N-wire interface reset - ESO0 I Emergency shut off input (TMR0) INTP0, P01 ESO1 I Emergency shut off input (TMR1) INTP1, P02 FCRXD0 I Receive input (AFCAN0) P34 FCRXD1Note I Receive input (AFCAN1) P36 FCTXD0 O Transmit output (AFCAN0) P35 FCTXD1Note O Transmit output (AFCAN1) P37 54 User's Manual U16580EE3V1UD00 PD70F3447 Chapter 2 Table 2-2: Pin Name I/O Pin Functions Non-Port Pins (2/6) Function Alternate Function PD70F3187 FLMD0 I Flash programming mode selection FLMD1 INTP0 PD70F3447 MODE0 MODE1 I External maskable interrupt request input P01, ESO0 INTP1 P02, ESO1 INTP2 P03, ADTRG0 INTP3 P04, ADTRG1 INTP4 P30, RXDC0 INTP5 P32, RXDC1 INTP6 P83, SCS300 INTP7 P84, SCS301 INTP8 P85, SCS302 INTP9 P93, SCS310 P93 INTP10 P94, SCS311 P94 INTP11 P95, SCS312 P95 INTP12 P72, TECRT0 MODE0 I Device operating mode selection FLMD0 MODE1 FLMD1 MODE2 - NMI I Non-maskable interrupt request input P00 RDNote O Read strobe signal output PCT4 RESET I System reset input - RXDC0 I Receive input (UARTC0) P30, INTP4 RXDC1 I Receive input (UARTC1) P32, INTP5 SCK30 I/O Serial shift clock I/O (CSI30) P82 SCK31Note I/O Serial shift clock I/O (CSI31) P92 SCKB0 I/O Serial shift clock I/O (CSIB0) P42 SCKB1Note I/O Serial shift clock I/O (CSIB1) P45 SCS300 O Serial peripheral chip select (CSI30) P83, INTP7 SCS301 P84, INTP8 SCS302 P85, INTP9 SCS303 P86, SSB0 SCS310Note O Serial peripheral chip select (CSI31) P32 P93, INTP10 SCS311Note P94, INTP10 SCS312Note P95, INTP11 SCS313Note P96, SSB1 SI30 I Serial data input (CSI30) P80 SI31Note I Serial data input (CSI31) P90 SIB0 I Serial data input (CSIB0) P40 User's Manual U16580EE3V1UD00 P96 55 Chapter 2 Pin Functions Table 2-2: Pin Name I/O Non-Port Pins (3/6) Function Alternate Function PD70F3187 PD70F3447 SIB1Note I Serial data input (CSIB1) P43 SO30 O Serial data output (CSI30) P81 SO31 O Serial data output (CSI31) P91 SOB0 O Serial data output (CSIB0) P41 SOB1 O Serial data output (CSIB1) P44 SSB0 I Serial slave select input (CSIB0) P86, SCS303 SSB1Note I Serial slave select input (CSIB1) P96, SCS313 P96 TCLR1Note I Timer clear input (TMENC10) P100, TICC10, TOP81 P100, TOP81 TCUD1Note I Count up/down direction control input (TMENC10) P101, TICC11 P101 TECRT0 I Timer clear input (TMT0) P72, INTP12 TECRT1 I Timer clear input (TMT1) P75, AFO TENCT00 I Timer encoder input (TMT0) P70, TIT00, TEVTT1, TOT00 TENCT01 I TENCT10 I TENCT11 I TEVTP0 I Timer event input (TMP0) P13, TIP11, TOP11 TEVTP1 I Timer event input (TMP1) P10, TIP00, TOP00 TEVTP2 I Timer event input (TMP2) P17, TIP31, TOP31 TEVTP3 I Timer event input (TMP3) P14, TIP20, TOP20 TEVTP4 I Timer event input (TMP4) P23, TIP51, TOP51 TEVTP5 I Timer event input (TMP5) P20, TIP40, TOP40 TEVTP6 I Timer event input (TMP6) P27, TIP71, TOP71 TEVTP7 I Timer event input (TMP7) P24, TIP60, TOP60 TEVTR1 I Timer event input (TMR1) P67, TOR17 TEVTT0 I Timer event input (TMT0) P74,TIT11, TOT11, TENCT11 TEVTT1 I Timer event input (TMT1) P70, TIT00, TOT00, TENCT00 TICC10Note I TMENC10 capture trigger input P100, TCLR1, TOP81 P100, TOP81 P101, TCUD1 P101 P71, TIT01, TTRGT1, TOT01 Timer encoder input (TMT1) P74, TIT11, TEVTT0, TOT11 TICC11Note TIP00 I Capture trigger input (TMP0) TIP01 TIP10 I Capture trigger input (TMP1) TIP31 56 P12, TTRGP0, TOP10 P13, TEVTP0, TOP11 I Capture trigger input (TMP2) TIP21 TIP30 P10, TEVTP1, TOP00 P11, TTRGP1, TOP01 TIP11 TIP20 P73, TIT10, TTRGT0, TOT10 P14, TEVTP3, TOP20 P15, TTRGP3, TOP21 I Capture trigger input (TMP3) P16, TTRGP2, TOP30 P17, TEVTP2, TOP31 User's Manual U16580EE3V1UD00 Chapter 2 Table 2-2: Pin Name I/O Pin Functions Non-Port Pins (4/6) Function Alternate Function PD70F3187 TIP40 I Capture trigger input (TMP4) TIP41 TIP50 I Capture trigger input (TMP5) I Capture trigger input (TMP6) P24, TEVTP7, TOP60 P25, TTRGP7, TOP61 I Capture trigger input (TMP7) TIP71 TIR10 P22, TTRGP4, TOP50 P23, TEVTP4, TOP51 TIP61 TIP70 P20, TEVTP5, TOP40 P21, TTRGP5, TOP41 TIP51 TIP60 P26, TTRGP6, TOP70 P27, TEVTP6, TOP71 I Capture trigger input (TMR1) P61, TOR11 TIR11 P62, TOR12 TIR12 P63, TOR13 TIR13 P64, TOR14 TIT00 I Capture trigger input (TMT0) TIT01 TIT10 PD70F3447 P70, TEVTT1, TOT00, TENCT00 P71, TTRGT1, TOT01, TENCT01 I Capture trigger input (TMT0) TIT11 P73, TTRGT0, TOT10, TENCT10 P74,TEVTT0, TOT11, TENCT11 TIUD1Note I External count clock input (TMENC10) P102, TO1 P102 TO1Note O Pulse signal output (TMENC10) P102, TIUD1 P102 TOP00 O Pulse signal output (TMP0) P10, TIP00, TEVTP1 TOP01 TOP10 P11, TIP01, TTRGP1 O Pulse signal output (TMP1) TOP11 TOP20 P13, TIP11, TEVTP0 O Pulse signal output (TMP2) TOP21 TOP30 O Pulse signal output (TMP3) O Pulse signal output (TMP4) O Pulse signal output (TMP5) O Pulse signal output (TMP6) P24, TIP60, TEVTP7 P25, TIP61, TTRGP7 O Pulse signal output (TMP7) TOP71 TOP81 P22, TIP50, TTRGP4 P23, TIP51, TEVTP4 TOP61 TOP70 P20, TIP40, TEVTP5 P21, TIP41, TTRGP5 TOP51 TOP60 P16, TIP30, TTRGP2 P17, TIP31, TEVTP2 TOP41 TOP50 P14, TIP20, TEVTP3 P15, TIP21, TTRGP3 TOP31 TOP40 P12, TIP10, TTRGP0 P26, TIP70, TTRGP6 P27, TIP71, TEVTP6 O Pulse signal output (TMP8) P100, TCLR1, TICC10 User's Manual U16580EE3V1UD00 P100 57 Chapter 2 Pin Functions Table 2-2: Pin Name I/O Non-Port Pins (5/6) Function Alternate Function PD70F3187 TOR00 O Pulse signal output (TMR0) P50 TOR01 P51 TOR02 P52 TOR03 P53 TOR04 P54 TOR05 P55 TOR06 P56 TOR07 P57 TOR10 O Pulse signal output (TMR1) P60, TTRGR1 TOR11 P61, TIR10 TOR12 P62, TIR11 TOR13 P63, TIR12 TOR14 P64, TIR13 TOR15 P65 TOR16 P66 TOR17 P67, TEVTR1 TOT00 O Pulse signal output (TMT0) TOT01 TOT10 P70, TIT00, TEVTT1, TENCT00 P71, TIT01, TTRGT1, TENCT01 O Pulse signal output (TMT1) TOT11 TTRGP0 PD70F3447 P73, TIT10, TTRGT0, TENCT10 P74,TIT11, TEVTT0, TENCT11 I Timer trigger input (TMP0) P12, TIP10, TOP10 TTRGP1 Timer trigger input (TMP1) P11, TIP01, TOP01 TTRGP2 Timer trigger input (TMP2) P16, TIP30, TOP30 TTRGP3 Timer trigger input (TMP3) P15, TIP21, TOP21 TTRGP4 Timer trigger input (TMP4) P22, TIP50, TOP50 TTRGP5 Timer trigger input (TMP5) P21, TIP41, TOP41 TTRGP6 Timer trigger input (TMP6) P26, TIP70, TOP70 TTRGP7 Timer trigger input (TMP7) P25, TIP61, TOP61 TTRGR1 I Timer trigger input (TMR1) P60, TOR10 TTRGT0 I Timer trigger input (TMT0) P73, TIT10, TOT10, TENCT10 TTRGT1 I Timer trigger input (TMT1) P71, TIT01, TOT01, TENCT01 TXDC0 O Transmit output (UARTC0) P31 TXDC1 O Transmit output (UARTC1) P33 VDD10 to VDD15 - Positive power supply for internal CPU (1.5 V) - VDD30 to VDD37 - Positive power supply for peripheral interface (3.3 V) - VSS10 to VSS15 - Power supply ground for internal CPU - VSS30 to VSS37 - Power supply ground for peripheral interface - 58 User's Manual U16580EE3V1UD00 Chapter 2 Table 2-2: Pin Name I/O Pin Functions Non-Port Pins (6/6) Function Alternate Function PD70F3187 WAITNote I External wait control signal input PCM0 WRNote O Write strobe signal output PCT5 X1 I Crystal connection - X2 - PD70F3447 - Note: Not available on PD70F3447 User's Manual U16580EE3V1UD00 59 Chapter 2 Pin Functions 2.2 Pin Status Table 2-3: Pin Status in Reset and Standby Mode Operating Status During reset Pin After reset release Single-chip Mode 0 Single-chip Mode 1Note ROM-less ModeNote A0 to A15 (PAL0 to PAL15) Hi-Z Hi-Z Operating Operating A16 to A21 (PAH0 to PAH5) Hi-Z Hi-Z Operating Operating D0 to D15 (PDL0 to PDL15) Hi-Z Hi-Z Operating Operating D16 to D31 (PDH0 to PDH15) Hi-Z Hi-Z Operating Operating BEN0 to BEN3 (PCD2 to PCD5) Hi-Z Hi-Z Operating Operating CS0 (PCS0) Hi-Z Hi-Z Operating Operating CS1 (PCS1) Hi-Z Hi-Z Operating Operating CS3 (PCS3) Hi-Z Hi-Z Operating Operating CS4 (PCS4) Hi-Z Hi-Z Operating Operating RD (PCT4) Hi-Z Hi-Z Operating Operating WR (PCT5) Hi-Z Hi-Z Operating Operating WAIT (PCM0) Hi-Z Hi-Z Operating Operating PCM1, PCM6, PCM7 Hi-Z Hi-Z Hi-Z Operating DCK Operating Operating Operating Operating DDI Operating Operating Operating Operating DDO Operating Operating Operating Operating DMS Operating Operating Operating Operating DRST Operating Operating Operating Operating INTP0 to INTP3 (P01 to P04) - Input Input Operating INTP4 (P30) - Input Input Operating INTP5 (P32) - Input Input Operating INTP6 to INTP8 (P83 to P85) - Input Input Operating INTP9 to INTP11 (P93 to P95) - Input Input Operating NMI (P00) - Input Input Operating Hi-Z Hi-Z Hi-Z Operating Peripheral output pin other than above x x x Operating Port input pin other than above Hi-Z Hi-Z Hi-Z - x x x Hold Peripheral input pin other than above Port output pin other than above Remark: Hi-Z: High Impedance -: Input data is not sampled x: No function selected at reset Note: Not available on PD70F3447 60 HALT Mode User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions 2.3 Description of Pin Functions (1) P00 to P04 (Port 0) ... Input Port 0 is an 8-bit input-only port in which all pins are fixed for input. Besides functioning as a port, in control mode, P00 to P04 operate as NMI input, external interrupt request signal, real-time pulse unit (RPU) emergency shut off signal input, and A/D converter (ADC) external trigger input. Normally, if function pins also serve as ports, one mode or the other is selected using a port mode control register. However, there is no such register for P00 to P04. Therefore, the input port cannot be switched with the NMI input pin, external interrupt request input pin, RPU emergency shut off signal input pin, and A/D converter (ADC) external trigger input pin. Read the status of each pin by reading the port. (a) Port mode P00 to P04 are input-only. (b) Control mode P00 to P04 also serve as NMI, INTP0 to INTP3, ESO0, ESO1, ADTRG0, and ADTRG1 pins, but the control function cannot be disabled. (i) NMI (Non-maskable interrupt request) ... Input This is non-maskable interrupt request input. (ii) INTP0 to INTP3 (Interrupt request from peripherals) ... Input These are external interrupt request input pins. (iii) ESO0, ESO1 (Emergency shut off) ... Input These pins input timer TMR0 and timer TMR1 emergency shut off signals. (iv) ADTRG0, ADTRG1 (A/D trigger input) ... Input These are A/D converter external trigger input pins. User's Manual U16580EE3V1UD00 61 Chapter 2 Pin Functions (2) P10 to P17 (Port 1) ... Input/Output Port 1 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P10 to P17 operate as RPU input or output. The operation mode can be specified by the port 1 mode control register (PMC1) to port or control mode for each port pin individually. (a) Port mode P10 to P17 can be set to input or output in 1-bit units using the port 1 mode register (PM1). (b) Control mode P10 to P17 can be set to port or control mode in 1-bit units using the PMC1 register. (i) TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31 (Timer capture input) ... Input These are timer TMP0 to TMP3 capture trigger input pins. (ii) TEVTP0, TEVTP1, TEVTP2, TEVTP3 (Timer event input) ... Input These are timer TMP0 to TMP3 external event counter input pins. (iii) TTRGP0, TTRGP1, TTRGP2, TTRGP3 (Timer trigger) ... Input These are timer TMP0 to TMP3 external trigger input pins. (iv) TOP00, TOP01, TOP10, TOP11, TOP20, TOP21, TOP30, TOP31 (Timer output) ... Output These pins output timer TMP0 to TMP3 pulse signals. (3) P20 to P27 (Port 2) ... Input/Output Port 2 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P20 to P27 operate as RPU input or output. The operation mode can be specified by the port 2 mode control register (PMC2) to port or control mode for each port pin individually. (a) Port mode P20 to P27 can be set to input or output in 1-bit units using the port 2 mode register (PM2). (b) Control mode P20 to P27 can be set to port or control mode in 1-bit units using the PMC2 register. (i) TIP40, TIP41, TIP50, TIP51, TIP60, TIP61, TIP70, TIP71 (Timer capture input) ... Input These are timer TMP4 to TMP7 capture trigger input pins. (ii) TEVTP4, TEVTP5, TEVTP6, TEVTP7 (Timer event input) ... Input These are timer TMP4 to TMP7 external event counter input pins. (iii) TTRGP4, TTRGP5, TTRGP6, TTRGP7 (Timer trigger) ... Input These are timer TMP4 to TMP7 external trigger input pins. (iv) TOP40, TOP41, TOP50, TOP51, TOP60, TOP61, TOP70, TOIP71 (Timer output) ... Output These pins output timer TMP4 to TMP7 pulse signals. 62 User's Manual U16580EE3V1UD00 Chapter 2 (4) Pin Functions P30 to P37 (Port 3) ... Input/Output Port 3 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P30 to P37 operate as serial interface (UARTC0, UARTC1, AFCAN0, AFCAN1Note). Additionally external interrupt request signal inputs are available in port input mode. The operation mode can be specified by the port 3 mode control register (PMC3) to port or control mode for each port pin individually. (a) Port mode P30 to P37 can be set to input or output in 1-bit units using the port 3 mode register (PM3). (i) INTP4, INTP5 (Interrupt request from peripherals) ... Input These are external interrupt request input pins, which are simultaneously enabled in port input mode. (b) Control mode P30 to P37 can be set to port or control mode in 1-bit units using the PMC3 register. (i) TXDC0, TXDC1 (Transmit data) ... Output These pins output serial transmit data of UARTC0 and UARTC1. (ii) RXDC0, RXDC1 (Receive data) ... Input These pins input serial receive data of UARTC0 and UARTC1. (iii) FCTXD0, FCTXD1Note (Transmit data for controller area network) ... Output These pins output AFCAN0 and AFCAN1Note serial transmit data. (iv) FCRXD 0, FCRXD1Note (Receive data for controller area network) ... Input These pins input AFCAN0 and AFCAN1Note serial receive data. Note: Not available on PD70F3447 User's Manual U16580EE3V1UD00 63 Chapter 2 Pin Functions (5) P40 to P45 (Port 10) ... Input/Output Port 4 is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P40 to P45 operate as serial interface (CSIB0, CSIB1Note). The operation mode can be specified by the port 4 mode control register (PMC4) to port or control mode for each port pin individually. (a) Port mode P40 to P45 can be set to input or output in 1-bit units using the port 4 mode register (PM4). (b) Control mode P40 to P45 can be set to port or control mode in 1-bit units using the PMC4 register. (i) SOB0, SOB1Note (Serial output) ... Output These pins output CSIB0 and CSIB1Note serial transmit data. (ii) SIB0, SIB1Note (Serial input) ... Input These pins input CSIB0 and CSIB1Note serial receive data. (iii) SCKB0, SCKB1 Note(Serial clock) ... I/O These are the CSIB0 and CSIB1Note serial clock I/O pins. Note: Not available on PD70F3447 64 User's Manual U16580EE3V1UD00 Chapter 2 (6) Pin Functions P50 to P57 (Port 5) ... Input/Output Port 5 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P50 to P57 operate as RPU input or output. The operation mode can be specified by the port 5 mode control register (PMC5) to port or control mode for each port pin individually. (a) Port mode P50 to P57 can be set to input or output in 1-bit units using the port 5 mode register (PM5). (b) Control mode P50 to P57 can be set to port or control mode in 1-bit units using the PMC5 register. (i) TOR00, TOR01, TOR02, TOR03, TOR04 (Timer output) ... Output These pins output timer TMR0 pulse signals. (7) P60 to P67 (Port 6) ... Input/Output Port 6 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P60 to P67 operate as RPU input or output. The operation mode can be specified by the port 6 mode control register (PMC6) to port or control mode for each port pin individually. (a) Port mode P60 to P67 can be set to input or output in 1-bit units using the port 6 mode register (PM6). (b) Control mode P60 to P67 can be set to port or control mode in 1-bit units using the PMC6 register. (i) TIR10, TIR11, TIR12, TIR13 (Timer capture input) ... Input These are timer TMR1 capture trigger input pins. (ii) TEVTR1 (Timer event input) ... Input This is a timer TMR1 external event counter input pin. (iii) TTRGR1 (Timer trigger) ... Input This is a timer TMR1 external trigger input pin. (iv) TOR10, TOR11, TOR12, TOR13, TOR14 (Timer output) ... Output These pins output timer TMR1 pulse signals. User's Manual U16580EE3V1UD00 65 Chapter 2 Pin Functions (8) P70 to P75 (Port 7) ... Input/Output Port 7 is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P70 to P75 operate as RPU input or output, and auxiliary frequency output. Additionally an external interrupt request signal input is available in port input mode. The operation mode can be specified by the port 7 mode control register (PMC7) to port or control mode for each port pin individually. (a) Port mode P70 to P75 can be set to input or output in 1-bit units using the port 7 mode register (PM7). (i) INTP12 (Interrupt request from peripherals) ... Input This is an external interrupt request input pin, which is simultaneously enabled in port input mode. (b) Control mode P70 to P75 can be set to port or control mode in 1-bit units using the PMC7 register. (i) TIT00, TIT01, TIT10, TIT11 (Timer capture input) ... Input These are timer TMT0 and TMT1 capture trigger input pins. (ii) TEVTT0, TEVTT1 (Timer event input) ... Input These are timer TMT0 and TMT1 external event counter input pins. (iii) TTRGT0, TTRGT1 (Timer trigger) ... Input These are timer TMT0 and TMT1 external trigger input pins. (iv) TECRT0, TECRT1 (Timer clear) ... Input These are timer TMT0 and TMT1 external clear input pins. (v) TENCT00, TENCT01, TENCT10, TENCT11 (Timer encoder input ... Input These are timer TMT0 and TMT1 encoder input pins. (vi) TOT00, TOT01, TOT10, TOT11 (Timer output) ... Output These pins output timer TMT0 and TMT1 pulse signals. (vii)AFO (Auxiliary frequency) ... Output This is an auxiliary frequency output signal pin of baudrate generator BGR2. 66 User's Manual U16580EE3V1UD00 Chapter 2 (9) Pin Functions P80 to P86 (Port 8) ... Input/Output Port 8 is a 7-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P80 to P86 operate as serial interface (CSI30, CSIB0). Additionally external interrupt request signal inputs are available in port input mode. The operation mode can be specified by the port 8 mode control register (PMC8) to port or control mode for each port pin individually. (a) Port mode P80 to P86 can be set to input or output in 1-bit units using the port 8 mode register (PM8). (i) INTP6, INTP7, INTP8 (Interrupt request from peripherals) ... Input These are external interrupt request input pins, which are simultaneously enabled in port input mode. (b) Control mode P80 to P86 can be set to port or control mode in 1-bit units using the PMC8 register. (i) SO30 (Serial output) ... Output This pin outputs CSI30 serial transmit data. (ii) SI30 (Serial input) ... Input This pin inputs CSI30 serial receive data. (iii) SCK30 (Serial clock) ... I/O This is the CSI30 serial clock I/O pin. (iv) SCS300 to SCS303 (Serial chip select) ... Output These pins output CSI30 serial chip select signals. (v) SSB0 (Serial slave select signal) ... Input This pin inputs CSIB0 slave select signal. User's Manual U16580EE3V1UD00 67 Chapter 2 Pin Functions (10) P90 to P96 (Port 9) ... Input/Output Port 9 is a 7-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P90 to P96 operate as serial interface (CSI31Note, CSIB1Note). Additionally external interrupt request signal inputs are available in port input mode. The operation mode can be specified by the port 9 mode control register (PMC9) to port or control mode for each port pin individually. (a) Port mode P90 to P96 can be set to input or output in 1-bit units using the port 9 mode register (PM9). (i) INTP9, INTP10, INTP11 (Interrupt request from peripherals) ... Input These are external interrupt request input pins, which are simultaneously enabled in port input mode. (b) Control mode P90 to P96 can be set to port or control mode in 1-bit units using the PMC9 register. (i) SO31 (Serial output) ... OutputNote This pin outputs CSI31 serial transmit data. (ii) SI31 (Serial input) ... InputNote This pin inputs CSI31 serial receive data. (iii) SCK31 (Serial clock) ... I/ONote This is the CSI31 serial clock I/O pin. (iv) SCS310 to SCS313 (Serial chip select) ... OutputNote These pins output CSI31 serial chip select signals. (v) SSB1 (Serial slave select input) ... InputNote This pin inputs CSIB1 slave select signal. Note: not available on PD70F3447 68 User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions (11) P100 to P102 (Port 10) ... Input/Output Port 10 is a 3-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P100 to P102 operate as RPU input or output The operation mode can be specified by the port 10 mode control register (PMC10) to port or control mode for each port pin individually. (a) Port mode P100 to P102 can be set to input or output in 1-bit units using the port 10 mode register (PM10). (b) Control mode P100 to P102 can be set to port or control mode in 1-bit units using the PMC4 register. (i) TIUD1 (Timer count pulse input) ... InputNote This is an external count clock input pin to the up/down counter (TMENC10). (ii) TCUD1 (Timer control pulse input) ... InputNote This is an input count operation switching signal to the up/down counter (TMENC10). (iii) TCLR1 (Timer clear) ... InputNote This is a clear signal input pin to the up/down counter (TMENC10). (iv) TICC10, TICC11 (Timer capture input) ... InputNote These are timer TMENC10 external capture trigger input pins. (v) TO1 (Timer output) ... OutputNote This pin outputs timer TMENC10 pulse signals. (vi) TOP80 (Timer output) ... Output This pin outputs timer TMP8 pulse signals. (12) PAL0 to PAL15 (Port AL) ... I/O Port AL is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the address bus (A0 to A15) when memory is expanded externally. The operation mode can be specified by the port AL mode control register (PMCAL) to port or control mode for each port pin individually. (a) Port mode PAL0 to PAL15 can be set to input or output in 1-bit units using the port AL mode register (PMAL). (b) Control mode PAL0 to PAL15 can be set to port or control mode in 1-bit units using the PMCAL register. (i) A0 to A15 (Address bus) ... 3-state outputNote These are the address output pins of the lower 16 bits of the 22-bit address bus when the external memory is accessed. Note: not available on PD70F3447 User's Manual U16580EE3V1UD00 69 Chapter 2 Pin Functions (13) PAH0 to PAH5 (Port AH) ... I/O Port AH is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the address bus (A16 to A21) when memory is expanded externally. The operation mode can be specified by the port AH mode control register (PMCAH) to port or control mode for each port pin individually. (a) Port mode PAH0 to PAH5 can be set to input or output in 1-bit units using the port AH mode register (PMAH). (b) Control mode PAH0 to PAH6 can be set to port or control mode in 1-bit units using the PMCAH register. (i) A16 to A21 (Address bus) ... 3-state outputNote These are the address output pins of the higher 6 bits of the 22-bit address bus when the external memory is accessed. (14) PDL0 to PDL15 (Port DL) ... I/O Port DL is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the data bus (D0 to D15) when memory is expanded externally. The operation mode can be specified by the port DL mode control register (PMCDL) to port or control mode for each port pin individually. (a) Port mode PDL0 to PDL15 can be set to input or output in 1-bit units using the port DL mode register (PMDL). (b) Control mode PDL0 to PDL15 can be set to port or control mode in 1-bit units using the PMCDL register. (i) D0 to D15 (Address bus) ... 3-state I/ONote These are the data I/O pins of the lower 16 bits of the 32-bit data bus when the external memory is accessed. Note: not available on PD70F3447 70 User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions (15) PDH0 to PDH15 (Port DH) ... I/O Port DH is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the data busNote (D16 to D31) when memory is expanded externally. The operation mode can be specified by the port DH mode control register (PMCDH) to port or control mode for each port pin individually. (a) Port mode PDH0 to PDH15 can be set to input or output in 1-bit units using the port DH mode register (PMDH). (b) Control mode PDH0 to PDH15 can be set to port or control mode in 1-bit units using the PMCDH register. (i) D16 to D31 (Address bus) ... 3-state I/ONote These are the data I/O pins of the higher 16 bits of the 32-bit data bus when the external memory is accessed. (16) PCD2 to PCD5 (Port CD) ... I/O Port CD is a 4-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as control signal outputsNote when memory is expanded externally. The operation mode can be specified by the port CD mode control register (PMCCD) to port or control mode for each port pin individually. (a) Port mode PCD2 to PCD5 can be set to input or output in 1-bit units using the port CD mode register (PMCD). (b) Control mode PCD2 to PCD5 can be set to port or control mode in 1-bit units using the PMCCD register. (i) BEN0 to BEN3 (Byte enable) ... 3-state outputNote These are the byte enable control signal pins, which indicate the validity of the corresponding byte on the 32-bit data bus. Note: not available on PD70F3447 User's Manual U16580EE3V1UD00 71 Chapter 2 Pin Functions (17) PCM0, PCM1, PCM6, PCM7 (Port CM) ... I/O Port CM is a 4-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as control signal inputNote when memory is expanded externally. The operation mode can be specified by the port CM mode control register (PMCCM) to port or control mode for each port pin individually. (a) Port mode PCM0, PCM1, PCM6, and PCM7 can be set to input or output in 1-bit units using the port CM mode register (PMCM). (b) Control mode PCM0 can be set to port or control mode in 1-bit units using the PMCCM register. (i) WAIT (Wait) ... InputNote This is the control signal input pin at which an external data wait is inserted into the bus cycle. The WAIT signal can be input asynchronously, and is sampled at the falling edge of the BCLK signal. When the setup or hold time is terminated within the sampling timing, wait insertion may not be executed. (18) PCS0, PCS1, PCS3, PCS4 (Port CS) ... I/O Port CS is a 4-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as control signal outputsNote when memory is expanded externally. The operation mode can be specified by the port CS mode control register (PMCCS) to port or control mode for each port pin individually. (a) Port mode PCS0, PCS1, PCS3, and PCS4 can be set to input or output in 1-bit units using the port CS mode register (PMCS). (b) Control mode PCS0, PCS1, PCS3, and PCS4 can be set to port or control mode in 1-bit units using the PMCCS register. (i) CS0, CS1, CS3, CS4 (Chip select) ... 3-state outputNote These are the chip select signal output pins for the external memory or peripheral I/O extension areas. The CSn signal is assigned to the memory block n (n = 0, 1, 3, 4). It becomes active while the bus cycle that accesses the corresponding memory block is activated. In the idle state (TI), it becomes inactive. Note: not available on PD70F3447 72 User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions (19) PCT4, PCT5 (Port CT) ... I/O Port CT is a 2-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as control signal outputsNote when memory is expanded externally. The operation mode can be specified by the port CT mode control register (PMCCT) to port or control mode for each port pin individually. (a) Port mode PCT4 and PCT5 can be set to input or output in 1-bit units using the port CT mode register (PMCT). (b) Control mode PCT4 and PCT5 can be set to port or control mode in 1-bit units using the PMCCT register. (i) RD (Read strobe) ... 3-state outputNote This is a strobe signal output pin that shows whether the bus cycle currently being executed is a read cycle for the external memory or peripheral I/O extension area. In the idle state (TI), it becomes inactive. (ii) WR (Write strobe) ... 3-state outputNote This is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the external memory or peripheral I/O extension area. Note: not available on PD70F3447 User's Manual U16580EE3V1UD00 73 Chapter 2 Pin Functions (20) DCK (Debug clock) ... Input This pin inputs a debug clock. At the rising edge of the DCK signal, the DMS and DDI signals are sampled, and data is output from the DDO pin at the falling edge of the DCK signal. Keep this pin high when the debug function is not used. (21) DDI (Debug data input) ... Input This pin inputs debug data, which is sampled at the rising edge of the DCK signal when the debug serial interface is in the shift state. Data is input with the LSB first. Keep this pin high when the debug function is not used. (22) DDO (Debug data output) ... Output This pin outputs debug data at the falling edge of the DCK signal when the debug serial interface is in the shift state. Data is output with the LSB first. (23) DMS (Debug mode select) ... Input This input pin selects a debug mode. Depending on the level of the DMS signal, the state machine of the debug serial interface changes. This pin is sampled at the rising edge of the DCK signal. Keep this pin high when the debug function is not used. (24) DRST (Debug reset) ... Input This pin inputs a debug reset signal that is a negative-logic signal to initialize the DCU asynchronously. When this signal goes low, the DCU is reset/invalidated. Keep this pin low when the debug function is not used. (25) MODE0 to MODE2 (Mode) ... Input These are input pins used to specify the operating mode. (26) FLMD0, FLMD1 (flash programming mode) These are input pins used to specify the flash programming mode. (27) RESET (Reset) ... Input RESET is a signal that is input asynchronously and that has a constant low level width regardless of the operating clock's status. When this signal is input, a system reset is executed as the first priority ahead of all other operations. In addition to being used for ordinary initialization/start operations, this pin can also be used to release a standby mode (HALT). (28) X1, X2 (Crystal) These pins are used to connect the resonator that generates the system clock. (29) ANI00 to ANI09, ANI10 to ANI19 (Analog input) ... Input These are analog input pins of the corresponding A/D converter (ADC0, ADC1). (30) AVREF0, AVREF1 (Analog reference voltage) ... Input These are reference voltage supply pins for the corresponding A/D converter (ADC0, ADC1). (31) AVDD (Analog power supply) This is the positive power supply pin for the A/D converters. 74 User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions (32) AVSS (Analog ground) This is the analog ground pin for the A/D converters. (33) CVDD (Power supply for clock generator) This is the positive power supply pin for the clock generator. (34) CVSS (Ground for clock oscillator) This is the ground pin for the clock generator. (35) VDD10 to VDD15 (Power supply) These are the positive power supply pins for the internal CPU. (36) VDD30 to VDD37 (Power supply) These are the positive power supply pins for the peripheral interface. (37) VSS10 to VSS15 (Ground) These are the ground pins for the internal CPU. (38) VSS30 to VSS37 (Ground) These are the ground pins for the peripheral interface. User's Manual U16580EE3V1UD00 75 Chapter 2 Pin Functions 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4: Terminal PD70F3187 I/O Circuit Types (1/4) I/O circuit type Recommended termination PD70F3447 P00/NMI 2 Connect independently to VSS3 via a resistor P01/INTP0/ESO0 P02/INTP1/ESO1 P03INTP2/ADTRG0 P04INTP3/ADTRG1 P10/TIP00/TEVTP1/TOP00 P11/TIP01/TTRGP1/TOP01 5-K Input: Connect independently to VDD3 or VSS3 via a resistor Output: leave open P12/TIP10/TTRGP0/TOP10 P13/TIP11/TEVTP0/TOP11 P14/TIP20/TEVTP3/TOP20 P15/TIP21/TTRGP3/TOP21 P16/TIP30/TTRGP2/TOP30 P17/TIP31/TEVTP2/TOP31 P20/TIP40/TEVTP5/TOP40 P21/TIP41/TTRGP5/TOP41 P22/TIP50/TTRGP4/TOP50 P23/TIP51/TEVTP4/TOP51 P24/TIP60/TEVTP7/TOP60 P25/TIP61/TTRGP7/TOP61 P26/TIP70/TTRGP6/TOP70 P27/TIP71/TEVTP6/TOP71 P30/RXDC0/INTP4 P31/TXDC0 P32/RXDC1/INTP5 P33/TXDC1 P34/FCRXD0 P35/FCTXD0 P36/FCRXD1 P36 P37/FCTXD1 P37 P40/SIB0 P41/SOB0 P42/SCKB0 P43/SIB1 P43 P44/SOB1 P44 P45/SCKB1 P45 P50/TOR00 to P57/TOR07 76 User's Manual U16580EE3V1UD00 Chapter 2 Table 2-4: Terminal PD70F3187 Pin Functions I/O Circuit Types (2/4) I/O circuit type Recommended termination 5-K Input: Connect independently to VDD3 or VSS3 via a resistor Output: leave open PD70F3447 P60/TOR10/TTRGR1 P61/TOR11/TIR10 P62/TOR12/TIR11 P63/TOR13/TIR12 P64/TOR14/TIR13 P65/TOR15 P66/TOR16 P67/TOR17/TEVTR1 P70/TIT00/TEVTT1/TOT00/TENCT00 P71/TIT01/TTRGT1/TOT01/TENCT01 P72/TECRT0/INTP12 P73/TIT10/TTRGT0/TOT10/TENCT10 P74/TIT11/TEVTT0/TOT11/TENCT11 P75/TECRT1/AFO P80/SI30 P81/SO30 P82/SCK30 P83/SCS300/INTP6 P84/SCS301/INTP7 P85/SCS302/INTP8 P86/SCS303/SSB0 P90/SI31 P90 P91/SO31 P91 P92/SCK31 P92 P93/SCS310/ INTP9 P93/INTP9 P94/SCS311/ INTP10 P94/INTP10 P95/SCS312 /INTP11 P95/INTP11 P96/SCS313/ SSB1 P96 P100/TCLR1/ TICC10/TOP80 P100/TOP80 P101/TCUD1/ TICC11 P101 P102/TIUD1/TO1 P102 User's Manual U16580EE3V1UD00 77 Chapter 2 Pin Functions Table 2-4: Terminal I/O Circuit Types (3/4) I/O circuit type Recommended termination 5 Input: Connect independently to VDD3 or VSS3 via a resistor Output: leave open 5 Input: Connect independently to VDD3 or VSS3 via a resistor Output: leave open RESET 2 Pin must be used in the intended way X1 - X2 - MODE0/FLMD0 2 MODE1/FLMD1 2 MODE2 2 DCK 1 PD70F3187 PD70F3447 PAH0/A16 to PAH5/A21 PAH0 to PAH5 PAL0/A0 to PAL15/A15 PAL0 to PAL15 PDH0/D16 to PDH15/D31 PDH0 to PDH15 PDL0/D0 to PDL15/D15 PDL0 to PDL15 PCS0/CS0 PCS0 PCS1/CS1 PCS1 PCS3/CS3 PCS3 PCS4/CS4 PCS4 PCD2/BEN0 to PCD5/BEN3 PCD2 to PCD5 PCT4/RD PCT4 PCT5/WR PCT5 PCM0/WAIT PCM0 PCM1 PCM1 PCM6 PCM6 PCM7 PCM7 Connect independently to VDD3 via a resistor DRST 2-I Leave open (on-chip pull-down resistor DMS 1 Connect independently to VDD3 via a resistor DDO 3 Leave open (always level output during reset) ANI00 to ANI09 7 Connect independently to AVDD or AVSS via a resistor - Connect independently to AVSS via a resistor DDI ANI10 to ANI19 AVREF0 AVREF1 78 User's Manual U16580EE3V1UD00 Chapter 2 Table 2-4: Terminal PD70F3187 AVDD Pin Functions I/O Circuit Types (4/4) I/O circuit type Recommended termination PD70F3447 - Pin must be used in the intended way AVSS0 AVSS1 VDD10 to VDD15 VSS10 to VSS15 VDD30 to VDD37 VSS30 to VSS37 CVDD CVSS User's Manual U16580EE3V1UD00 79 Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type 5 Type 1 VDD IN VDD data P-ch IN/OUT P-ch N-ch output disable N-ch input enable Type 5-K Type 2 VDD data P-ch IN/OUT IN N-ch output disable Schmitt trigger input with hysteresis characteristics input enable Type 7 Type 2-I P-ch IN comparator IN N-ch VREF (threshold voltage) Schmitt trigger input with hysteresis characteristics Type 3 VDD P-ch OUT N-ch 80 User's Manual U16580EE3V1UD00 Chapter 2 Pin Functions 2.5 Noise Suppression The V850E/PH2 has a digital or analog delay circuits for noise suppression on all edge sensitive inputs. The digital delay circuit suppresses input pulses shorter than the internally generated edge detection signal to assure the hold time for these signals. The noise suppression is only effective on alternate pin functions, and it is not effective when the port input function is selected. Table 2-5: Noise Suppression Timing Pin Function Noise removal time NMI 4 to 5 clocks INTP0, INTP1, ESO0, ESO1 Clock Source fXX/16 or fXX/64 (set by NCR0 bit of NRC register) Analog delay (60ns to 200ns) INTP2 to INTP11, ADTRG0, ADTRG1 4 to 5 clocks fXX/16 or fXX/64 (set by NCR1 bit of NRC register) INTP12, TICC00Note, TICC01Note, TCLR0Note, TCUD0Note, TIUD0Note, TIT00, TIT01, TIT10, TIT11, TECRT0, TECRT1, TEVTT0, TEVTT1, TTRGT0, TTRGT1, TENCT00, TENCT01, TENCT10, TENCT11 4 to 5 clocks fXX/16 or fXX/64 (set by NCR2 bit of NRC register) TIP00, TIP01, TIP10, TIP11, TEVTP0, TEVTP1, TTRGP0, TTRGP1 4 to 5 clocks fXX/16 or fXX/64 (set by NCR3 bit of NRC register) TIP20, TIP21, TIP30, TIP31, TEVTP2, TEVTP3, TTRGP2, TTRGP3 4 to 5 clocks fXX/16 or fXX/64 (set by NCR4 bit of NRC register) TIP40, TIP41, TIP50, TIP51, TEVTP4, TEVTP5, TTRGP4, TTRGP5 4 to 5 clocks fXX/16 or fXX/64 (set by NCR5 bit of NRC register) TIP60, TIP61, TIP70, TIP71, TEVTP6, TEVTP7, TTRGP6, TTRGP7 4 to 5 clocks fXX/16 or fXX/64 (set by NCR6 bit of NRC register) TIR10 to TIR13, TEVTR1, TTRGR1 4 to 5 clocks fXX/16 or fXX/64 (set by NCR7 bit of NRC register) Note: Not available on PD70F3447 User's Manual U16580EE3V1UD00 81 Chapter 2 Pin Functions (1) Noise removal time control register (NRC) The NRC register specifies the noise removal clock setting for different edge sensitive inputs. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 2-2: After reset: NRC 00H Noise Removal Time Control Register (1/2) R/W Address: FFFFF7A0H 7 6 5 4 3 2 1 0 NCR7 NCR6 NCR5 NCR4 NCR3 NCR2 NCR1 NCR0 NCR7 Noise removal clock setting for input pins TIR10 to TIR13, TEVTR1, TTRGR1 0 fXX/16 1 fXX/64 NCR6 Noise removal clock setting for input pins TIP60, TIP61, TIP70, TIP71, TEVTP6, TEVTP7, TTRGP6, TTRGP7 0 fXX/16 1 fXX/64 NCR5 Noise removal clock setting for input pins TIP40, TIP41, TIP50, TIP51, TEVTP4, TEVTP5, TTRGP4, TTRGP5 0 fXX/16 1 fXX/64 NCR4 Noise removal clock setting for input pins TIP20, TIP21, TIP30, TIP31, TEVTP2, TEVTP3, TTRGP2, TTRGP3 0 fXX/16 1 fXX/64 NCR3 Noise removal clock setting for input pins TIP00, TIP01, TIP10, TIP11, TEVTP0, TEVTP1, TTRGP0, TTRGP1 0 fXX/16 1 fXX/64 NCR2 Noise removal clock setting for input pins INTP12, TICC00, TICC01, TCLR0, TCUD0, TIUD0, TIT00, TIT01, TIT10, TIT11, TECRT0, TECRT1, TEVTT0, TEVTT1, TTRGT0, TTRGT1, TENCT00, TENCT01, TENCT10, TENCT11Note 0 fXX/16 1 fXX/64 Note: Input pins TIC00, TIC01, TCRL0, TCUD0, and TIUD0 are not available on PD70F3447 82 User's Manual U16580EE3V1UD00 Chapter 2 Figure 2-2: NCR1 Noise Removal Time Control Register (2/2) Noise removal clock setting for input pins INTP2 to INTP11, ADTRG0, ADTRG1 0 fXX/16 1 fXX/64 NCR0 Pin Functions Noise removal clock setting for NMI input pin 0 fXX/16 1 fXX/64 User's Manual U16580EE3V1UD00 83 Chapter 2 Pin Functions [MEMO] 84 User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions The CPU of the V850E/PH2 microcontroller is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 Features * Number of instructions: 96 * Minimum instruction execution time: 15.6 ns (@ 64 MHz operation) * Memory space Program space: Data space: * General-purpose registers: 32 bits x 32 * Internal 32-bit architecture * 5-stage pipeline control * Multiply/divide instructions (32 bits x 32 bits 64 bits in 1 to 2 clocks) * Saturated operation instructions * Floating point arithmetic unit (single precision, 32 bits, IEEE754-85 standard) * 32-bit shift instruction: * Load/store instruction with long/short format * Four types of bit manipulation instructions - SET1 - CLR1 - NOT1 - TST1 64 MB linear 4 GB linear 1 clock User's Manual U16580EE3V1UD00 85 Chapter 3 CPU Functions 3.2 CPU Register Set The CPU registers of the V850E/PH2 can be classified into three categories: a general-purpose program register set, a dedicated system register set and a dedicated floating point arithmetic register set. All the registers have 32-bit width. In addition, the V850E/PH2 contains special system control registers that should be initialized before CPU operation, and a specific register controlling its clock. For detailed description of V850E1 core, refer to V850E1 Core Architecture Manual and the addendum for floating point arithmetic. Figure 3-1: (1) Program register set 31 r0 CPU Register Set (2) System register set 0 31 0 (Zero register) EIPC (Status saving register during interrupt) (Assembler-reserved register) EIPSW (Status saving register during interrupt) r3 (Stack pointer (SP)) FEPC (Status saving register during NMI) r4 (Global pointer (GP)) FEPSW (Status saving register during NMI) r5 (Text pointer (TP)) r1 r2 r6 ECR (Interrrupt source register) PSW (Program status word) CTPC (Status saving register during CALLT execution) r7 r8 r9 r10 r11 CTPSW (Status saving register during CALLT execution) r12 r13 DBPC r14 (Status saving register during exception/debug trap) DBPSW (Status saving register during exception/debug trap) r15 r16 CTBP r17 (CALLT base pointer) r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 (3) Floating point arithmetic register set r29 r30 (Element pointer (EP)) r31 (Link pointer (LP)) 31 PC 86 31 EFG 0 (Flag register) 0 (Program counter) ECT (Control register) User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 or offset 0 addressing. r30 is used as a base pointer when performing memory access with the SLD and SST short instructions. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after use. There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a variable register. Table 3-1: Name Program Registers Usage Operation r0 Zero register Always holds 0 r1 Assembler-reserved register Working register for generating 32-bit immediate r2 Address/data variable register (when r2 is not used by the real-time OS to be used) r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text area (area for placing program code) r6 to r29 Address/data variable register r30 Element pointer Base pointer when memory is accessed r31 Link pointer Used by compiler when calling function (2) Program counter (PC) This register holds the address of the instruction under execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to bit 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed. Figure 3-2: 31 PC Program Counter (PC) 26 25 Fixed to 0 1 0 Instruction address under execution User's Manual U16580EE3V1UD00 0 After reset 00000000H 87 Chapter 3 CPU Functions 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2: System Register Numbers System Register No. Name 0 EIPC 1 EIPSW 2 FEPC 3 FEPSW 4 Operand Specification Enabled for instruction Function LDSR STSR Yes Yes PSW value at Interrupt handler entry Note 1 Yes Yes PC value at NMI handler entry Yes Yes PSW value at NMI handler entry Yes Yes ECR Exception Cause Register No Yes 5 PSW Program status word Yes Yes 6 to 15 - Reserved numbers for future function expansion (The operation is not guaranteed if accessed.) No No 16 CTPC PC value at CALLT subroutine entry Note 2 Yes Yes 17 CTPSW PSW value at CALLT subroutine entry Note 2 Yes Yes 18 DBPC PC value at exception/debug trap entry Yes Yes 19 DBPSW PSW value at exception/debug trap entry Yes Yes 20 CTBP CALLT base pointer Yes Yes 21 to 31 - Reserved numbers for future function expansion (The operation is not guaranteed if accessed.) No No PC value at Interrupt handler entry Note 1 Notes: 1. Since only one set of registers is available, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. 2. Since only one set of registers is available, the contents of these registers must be saved by the program when CALLT instructions nesting is used. Caution: 88 Even if bit 0 of EIPC, FEPC, or CTPC is set to (1) by the LDSR instruction, bit 0 is ignored during return with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). If setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0). User's Manual U16580EE3V1UD00 Chapter 3 (1) CPU Functions Interrupt status saving registers (EIPC, EIPSW) There are two context saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the content of the program counter (PC) is saved to EIPC and the content of the program status word (PSW) is saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for the DIVH instruction (see Chapter 7 "Interrupt/Exception Processing Function" on page 219). Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion. Figure 3-3: 31 EIPC EIPSW 26 25 0 0 0 0 0 0 31 Interrupt Status Saving Registers (EIPC, EIPSW) 0 (PC contents) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents) After reset 0xxxxxxxH (x: Undefined) After reset 000000xxH (x: Undefined) The values of EIPC and EIPSW are restored to PC and PSW during execution of a RETI instruction. User's Manual U16580EE3V1UD00 89 Chapter 3 (2) CPU Functions NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the content of the program counter (PC) is saved to FEPC and the content of the program status word (PSW) is saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for the DIVH instruction. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion. Figure 3-4: 31 FEPC NMI Status Saving Registers (FEPC, FEPSW) 26 25 0 0 0 0 0 0 0 (PC contents) 31 8 7 FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents) After reset 0xxxxxxxH (x: Undefined) After reset 000000xxH (x: Undefined) The values of FEPC and FEPSW are restored to PC and PSW during execution of a RETI instruction. (3) Exception cause register (ECR) Upon occurrence of an interrupt or an exception, the Exception Cause Register (ECR) holds the source of the interrupt or the exception. The value held by ECR is an exception code, coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction. Figure 3-5: 31 Interrupt Source Register (ECR) 16 15 ECR 0 FECC EICC Bit position Bit name 31 to 16 FECC Non-maskable interrupt (NMI) exception code 15 to 0 EICC Exception, maskable interrupt exception code After reset 00000000H Description The list of exception codes is tabulated in Table 7-1, "Interrupt/Exception Source List," on page 219. 90 User's Manual U16580EE3V1UD00 Chapter 3 (4) CPU Functions Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of the LDSR instruction execution. However, if the ID flag is set to 1, interrupt request acknowledgement during LDSR instruction execution is prohibited. Bits 31 to 8 are reserved (fixed to 0) for future function expansion. Figure 3-6: 31 Program Status Word (PSW) 26 25 PSW 8 7 6 5 RFU 4 3 2 1 0 NP EP ID SAT CY OV S Z After reset 00000020H Bit position Bit name Description 31 to 8 RFU 7 NP Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when a NMI request is acknowledged, and disables multiple interrupts. 0: NMI servicing not in progress 1: NMI servicing in progress 6 EP Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set. 0: Exception processing not in progress 1: Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is enabled. 0: Interrupt enabled 1: Interrupt disabled 4 SATNote 3 CY 2 OVNote 1 SNote 0 Z Reserved field. Fixed to 0. Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed. 0: Not saturated 1: Saturated Indicates whether carry or borrow occurred as the result of an operation. 0: No carry or borrow occurred 1: Carry or borrow occurred Indicates whether overflow occurred during an operation. 0: No overflow occurred 1: Overflow occurred. Indicates whether the result of an operation is negative. 0: Operation result is positive or 0. 1: Operation result is negative. Indicates whether operation result is 0. 0: Operation result is not 0. 1: Operation result is 0. Note: During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation. This is explained on the following table. User's Manual U16580EE3V1UD00 91 Chapter 3 Table 3-3: CPU Functions Saturated Operation Results Operation result status Flag status Saturated operation result SAT OV S Maximum positive value exceeded 1 1 0 7FFFFFFFH Maximum negative value exceeded 1 1 1 80000000H Holds value before operation 0 0 Actual operation result Positive (maximum value not exceeded) Negative (maximum value not exceeded) (5) 1 CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. Bits 31 to 26 CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion. Figure 3-7: 31 CTPC CALLT Execution Status Saving Registers (CTPC, CTPSW) 26 25 0 0 0 0 0 0 0 (PC contents) 31 8 7 CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents) After reset 0xxxxxxxH (x: Undefined) After reset 000000xxH (x: Undefined) The values of CTPC and CTPSW are restored to PC and PSW during execution of the CTRET instruction. 92 User's Manual U16580EE3V1UD00 Chapter 3 (6) CPU Functions Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion. Figure 3-8: 31 DBPC Exception/Debug Trap Status Saving Registers (DBPC, DBPSW) 26 25 0 0 0 0 0 0 0 (PC contents) 31 8 7 DBPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents) After reset 0xxxxxxxH (x: Undefined) After reset 000000xxH (x: Undefined) The values of DBPC and DBPSW are restored to PC and PSW during execution of the DBRET instruction. (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify CALLT table start address and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion. Figure 3-9: 31 CTBP CALLT Base Pointer (CTBP) 26 25 0 0 0 0 0 0 1 0 (Base address) User's Manual U16580EE3V1UD00 0 After reset 0xxxxxxxH (x: Undefined) 93 Chapter 3 CPU Functions 3.2.3 Floating point arithmetic unit register set The floating point arithmetic unit is provided with one flag register and one control register. Table 3-4: Name Floating Point Arithmetic Unit Registers Usage Operation ECT Control register Sets the operation of the EFG register EFG Flag register Holds the status of the FPU (1) Floating point arithmetic control register (ECT) This register is used for controlling the setting conditions of the TR flag: TR is a logical OR between all the invalid operations the FPU can detect and each bit of ECT is a mask bit for each condition. Figure 3-10: Floating Point Arithmetic Control Register (ECT) 31 ECT RFU 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IT ZT VT UT PT 0 0 0 0 0 0 0 0 Bit position Bit name 31 to 13 RFU 12 IT Enables invalid operation detection in the TR value calculation 0: IV is set when an invalid operation is detected 1: IV and TR are set when an invalid operation is detected 11 ZT Enables zero divide operation detection in the TR value calculation 0: ZD is set when a zero divide operation is detected 1: ZD and TR are set when a zero divide operation is detected 10 VT Enables overflow detection in the TR value calculation 0: VF is set when an overflow is detected 1: VF and TR are set when an overflow is detected 9 UT Enables underflow detection in the TR value calculation 0: UD is set when an underflow is detected 1: UD and TR are set when an underflow is detected 8 PT Enables accuracy fail detection in the TR value calculation 0: PR is set when an accuracy fail is detected 1: PR and TR are set when an accuracy fail is detected 7 to 0 0 94 Description Reserved field. Fixed to 0. Reserved field. Fixed to 0. User's Manual U16580EE3V1UD00 After reset 00000000H Chapter 3 (2) CPU Functions Floating point arithmetic status register (EFG) Figure 3-11: Floating Point Arithmetic Status Register (EFG) 31 14 13 12 11 10 9 8 7 6 5 EFG RFU 4 3 2 1 0 RO IV ZD VF UD PR 0 0 0 TR 0 OV S Z After reset 00000000H Bit position Bit name Description 31 to 14 RFU Reserved field. Fixed to 0. 13 RO Running Operation: indicates whether the floating point arithmetic unit is running 0: operation in progress 1: FPU idle 12 IV InValid operation: Indicates that an invalid operation has been requested. 0: normal operation 1: invalid operation detected 11 ZD Zero Divide: Indicates whether a division by 0 has been detected. 0: normal operation 1: division by 0 detected 10 VF oVerFlow: indicates that the result of executing a floating point operation has overflowed. 0: no overflow generated 1: overflow generated 9 UD Undervalue: indicates that the result of executing a floating point operation has underflowed. 0: no underflow generated 1: underflow generated 8 PR PRecision error: indicates that an accuracy failure occurred. 0: no accuracy failure occurred 1: accuracy failure occurred 7 to 5 0 4 TR 3 0 2 OV 1 S Indicates whether floating point operation result is negative. 0: Operation result is not negative. 1: Operation result is negative. 0 Z Indicates whether floating point operation result is 0. 0: Operation result is not 0. 1: Operation result is 0. Reserved field. Fixed to 0. This flag summarizes the state of the FPU: 0: normal state 1: abnormal condition detected: one of the bits 13 to 8 is set. The setting conditions of this flag depends on the ECT register value. Reserved field. Fixed to 0. Indicates whether an overflow occurred during floating point to integer conversion 0: no overflow generated 1: overflow generated User's Manual U16580EE3V1UD00 95 Chapter 3 CPU Functions 3.3 Operating Modes The V850E/PH2 has the following operating modes. 3.3.1 Operating modes outline (1) Normal operating mode (a) Single-chip mode 0 Access to the internal ROM is enabled. In single-chip mode 0, after the system reset is released, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts. By setting the PMCDH, PMCDL, PMCCS, PMCCT, and PMCCM registers to control mode by instruction, an external device can be connected to the external memory area. (b) Single-chip mode 1 (PD70F3187 only) In single-chip mode 1Note, after the system reset is released, each pin related to the bus interface enters the control mode, program execution branches to the external device's (memory) reset entry address, and instruction processing starts. The internal ROM area is mapped from address 100000H. (c) ROM-less mode (PD70F3187 only) After the system reset is released, each pin related to the bus interface enters the control mode, program execution branches to the external device's (memory) reset entry address, and instruction processing starts. Fetching of instructions and data access for internal ROM becomes impossible. In ROM-less mode the data bus width is 32 bits. (2) Flash memory programming mode In this mode the internal flash memory can be written or erased with an external flash writer, using the CSIB0 or UARTC0 as serial interface. Note: Single-chip mode 1 is not available on PD70F3447. 96 User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE2. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation. MODE2 MODE1 MODE0 L L L Single chip mode 0 Internal ROM area is allocated from address 00000000H. L L H Flash memory programming mode CSIB0/IUARTC0 selected by MODE0 pin toggling. L H L ROM-less modeNote 2 External 32-bit data bus L H H Single chip mode 1Note 1 Internal ROM area is allocated from address 00100000H. External 32-bit data bus other value than above Remark: Mode Remark Setting prohibited L: Low-level input H: High-level input Notes: 1. Single-chip mode 1 is not available on PD70F3447. 2. ROM-less mode is not available on PD70F3447. User's Manual U16580EE3V1UD00 97 Chapter 3 CPU Functions 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/PH2 uses a 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When addressing instructions, a linear address space (program space) of up to 64 MB is supported. However, both the program and data spaces include areas whose use is prohibited. For details, refer to Figure 3-13, "Address Space Image," on page 99. Figure 3-12 shows the CPU address space. Figure 3-12: CPU Address Space CPU address space FFFFFFFFH Data area (4 GB linear) 04000000H 03FFFFFFH Program area (64 MB linear) 00000000H 98 User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.4.2 Images When addressing an instruction address, up to 64 MB of linear address space (program space) and Internal RAM area are supported. For operand addressing (data access), up to 4 GB of linear address space (data area) is supported. On this 4 GB address space, however, 256 MB physical address spaces can be seen as an image. Therefore, whatever the values of bits 31 to 29 of an address may be, a physical address space of the same 256 MB is accessed. Figure 3-13: Address Space Image CPU address space FFFFFFFFH Image F0000000H EFFFFFFFH Image Physical address space E0000000H DFFFFFFFH Peripheral I/O FFFFFFFH Internal RAM Image External memory 20000000H 1FFFFFFFH Internal ROM 0000000H Image 10000000H 0FFFFFFFH Image 00000000H User's Manual U16580EE3V1UD00 99 Chapter 3 CPU Functions 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. Therefore, the lower-limit address of the program space, 00000000H, and the upper-limit address, 03FFFFFFH, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. Caution: No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is a peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. Figure 3-14: 03FFFFFEH Program Space Program space 03FFFFFFH (+) direction (-) direction 00000000H 00000001H Program space (2) Data space The result of an operand address calculation that exceeds 32 bits is truncated to 32 bits. Therefore, the lower-limit address of the data space, address 00000000H, and the upper-limit address, FFFFFFFFH, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. Figure 3-15: FFFFFFFEH Data Space Data space FFFFFFFFH (+) direction 00000000H 00000001H Data space 100 User's Manual U16580EE3V1UD00 (-) direction Chapter 3 CPU Functions 3.4.4 Memory map Areas are reserved in V850E/PH2 as shown in Figure 3-16. Each mode is specified by the MODE0 to MODE2 pins. Figure 3-16: xFFFFFFFH xFFFF000H xFFFEFFFH xFFF8000H xFFF7FFFH Memory Map of PD70F3187 Single-chip mode 0 Single-chip mode 1 ROMless mode On-chip peripheral I/O area On-chip peripheral I/O area On-chip peripheral I/O area 4 KB Internal RAM area Internal RAM area Internal RAM area 32 KB Access prohibitedNote 1 Access prohibitedNote 1 Access prohibitedNote 1 On-chip peripheral I/O area mirrorNote 2 On-chip peripheral I/O area mirrorNote 2 On-chip peripheral I/O area mirrorNote 2 Access prohibitedNote 3 Access prohibitedNote 3 Access prohibitedNote 3 Internal RAM area mirror Internal RAM area mirror Internal RAM area mirror External memory area External memory area Access prohibitedNote 2 xFFF0000H xFFEFFFFH x4000000H x3FFFFFFH x3FFF000H x3FFEFFFH x3FF8000H x3FF7FFFH x3FF0000H x3FEFFFFH Program area (64 MB) Access prohibitedNote 1 x0200000H x01FFFFFH Internal ROM area 1 MB External memory area 1 MB x0100000H x00FFFFFH Internal ROM area x0000000H Notes: 1. By setting the PMCAL, PMCAH, PMCDL, PMCDH, PMCCS, PMCCT, and PMCCD port mode control registers to control mode, this area can be used as external memory area. 2. Accessing addresses 3FFF000H to 3FFFFFFH is prohibited. Specify addresses FFFF000H to FFFFFFFH to access the on-chip peripheral I/O. 3. The operation is not guaranteed if an access-prohibited area is accessed. User's Manual U16580EE3V1UD00 101 Chapter 3 Figure 3-17: CPU Functions Memory Map of PD70F3447 Single-chip mode 0 xFFFFFFFH xFFFF000H xFFFEFFFH xFFF6000H xFFF5FFFH On-chip peripheral I/O area 4 KB Access prohibitedNote 1 Internal RAM area 24 KB xFFF0000H xFFEFFFFH Access prohibited x4000000H x3FFFFFFH x3FFF000H x3FFEFFFH x3FF6000H x3FF5FFFH x3FF0000H x3FEFFFFH On-chip peripheral I/O area mirrorNote 1 Access prohibitedNote 2 Internal RAM area mirror Program area (64 MB) Access prohibited x0100000H x00FFFFFH Internal ROM area 1 MB x0000000H Notes: 1. Accessing addresses 3FFF000H to 3FFFFFFH is prohibited. Specify addresses FFFF000H to FFFFFFFH to access the on-chip peripheral I/O. 2. The operation is not guaranteed if an access-prohibited area is accessed. 102 User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.4.5 Areas (1) Internal ROM area (a) Memory map 1MB of the internal area is reserved for the physical internal ROM (flash memory). In case of uPD70F3187 internal flash memory of 512 KB are physically provided in the following addresses as internal ROM (flash memory). * In single-chip mode 0: Addresses 000000H to 07FFFFH (addresses 080000H to 0FFFFFH are undefined) * In single-chip mode 1: Addresses 0100000H to 017FFFFH (addresses 0180000H to 01FFFFFH are undefined) Figure 3-18: Internal ROM / Internal Flash Memory Area of PD70F3187 Single-chip mode 0 Single-chip mode 1 1FFFFFH 0FFFFFH Undefined Undefined 180000H 17FFFFH 080000H 07FFFFH Internal flash memory area 000000H Internal flash memory area 100000H In case of PD70F3447 internal flash memory of 384 KB are physically provided in the following addresses as internal ROM (flash memory). * In single-chip mode 0: Addresses 000000H to 05FFFFH (addresses 060000H to 0FFFFFH are undefined) Remark: Single-chip mode 1 is not supported by PD70F3447. User's Manual U16580EE3V1UD00 103 Chapter 3 Figure 3-19: CPU Functions Internal ROM / Internal Flash Memory Area of PD70F3447 Single-chip mode 0 0FFFFFH Undefined 060000H 05FFFFH Internal flash memory area 000000H (b) Interrupt/exception table The V850E/PH2 increases the interrupt response speed by assigning handler addresses corresponding to each interrupt/exception. This group of handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address and the program written in that memory is executed. For detailed list of the interrupt/exception sources and the corresponding handler addresses, please refer to Table 7-1, "Interrupt/Exception Source List," on page 219. 104 User's Manual U16580EE3V1UD00 Chapter 3 (2) CPU Functions Internal RAM area An area of 60 KB from FFF0000H to FFFEFFFH is reserved for the internal RAM area. In case of PD70F3187 internal RAM of 32 KB are physically provided at addresses FFF0000H to FFF7FFFH as internal RAM. The 32 KB area of 3FF0000H to 3FF7FFFH can be seen as an image of FFF0000H to FFF7FFFH. Figure 3-20: Internal RAM Area of PD70F3187 FFF7FFFH Internal RAM area (32 KB) FFF0000H In case of PD70F3447 internal RAM of 24 KB are physically provided at addresses FFF0000H to FFF5FFFH as internal RAM. The 32 KB area of 3FF0000H to 3FF5FFFH can be seen as an image of FFF0000H to FFF5FFFH. Figure 3-21: Internal RAM Area of PD70F3447 FFF5FFFH Internal RAM area (24 KB) FFF0000H User's Manual U16580EE3V1UD00 105 Chapter 3 (3) CPU Functions On-chip peripheral I/O area (SFR area) A 4 KB area from FFFF000H to FFFFFFFH is provided as the on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFHNote. Note: Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. Figure 3-22: On-Chip Peripheral I/O Area FFFFFFFH On-chip peripheral I/O area (4 KB) FFFF000H Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification and state monitoring are mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this area. Cautions: 1. For registers in which byte access is possible, if half-word access is executed, the higher 8 bits become undefined during a read operation, and the lower 8 bits of data are written to the register during a write operation. Do not access an 8-bit register in half-word units. 2. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. 106 User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.4.6 Peripheral I/O registers list . Table 3-5: Address Symbol Peripheral I/O Registers (1/14) Function Register Name Bit Units for Manipulation 1 FFFFF000H PAL 8 Port register AL Reset 16 R/W 0000H FFFFF000H PALL Port register ALL R/W R/W 00H FFFFF001H PALH Port register ALH R/W R/W 00H R/W R/W 00H FFFFF002H PAH Port register AH FFFFF004H PDL Port register DL R/W 0000H FFFFF004H PDLL Port register DLL R/W R/W 00H FFFFF005H PDLH Port register DLH R/W R/W 00H FFFFF006H PDH Port register DH R/W 0000H FFFFF006H PDHL Port register DHL R/W R/W 00H FFFFF007H PDHH Port register DHH R/W R/W 00H FFFFF008H PCS Port register CS R/W R/W 00H FFFFF00AH PCT Port register CT R/W R/W 00H FFFFF00CH PCM Port register CM R/W R/W 00H FFFFF00EH PCD Port register CD R/W R/W 00H FFFFF020H PMAL Port mode register AL R/W FFFFH FFFFF020H PMALL Port mode register ALL R/W R/W FFH FFFFF021H PMALH Port mode register ALH R/W R/W FFH R/W R/W FFH FFFFF022H PMAH Port mode register AH FFFFF024H PMDL Port mode register DL R/W FFFFH FFFFF024H PMDLL Port mode register DLL R/W R/W FFH FFFFF025H PMDLH Port mode register DLH R/W R/W FFH FFFFF026H PMDH Remarks Port mode register DH R/W FFFFH FFFFF026H PMDHL Port mode register DHL R/W R/W FFH FFFFF027H PMDHH Port mode register DHH R/W R/W FFH FFFFF028H PMCS Port mode register CS R/W R/W FFH FFFFF02AH PMCT Port mode register CT R/W R/W FFH FFFFF02CH PMCM Port mode register CM R/W R/W FFH FFFFF02EH PMCD Port mode register CD R/W R/W FFH FFFFF040H PMCAL Port mode control register AL R/W 0000H FFFFF040H PMCALL Port mode control register ALL R/W R/W 00H Note 1 FFFFF041H PMCALH Port mode control register ALH R/W R/W 00H Note 1 R/W R/W 00H Note 1 FFFFF042H PMCAH Port mode control register AH FFFFF044H PMCDL Port mode control register DL R/W 0000H Note 1 FFFFF044H PMCDLL Port mode control register DLL R/W R/W 00H Note 1 FFFFF045H PMCDLH Port mode control register DLH R/W R/W 00H Note 1 FFFFF046H PMCDH FFFFF046H PMCDHL Port mode control register DH Port mode control register DHL R/W 0000H R/W R/W User's Manual U16580EE3V1UD00 00H Note 1 Note 1 107 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (2/14) Function Register Name Bit Units for Manipulation 1 FFFFF047H PMCDHH 8 Reset Remarks 16 Port mode control register DHH R/W R/W 00H Note 1 FFFFF048H PMCCS Port mode control register CS R/W R/W 00H Note 1 FFFFF04AH PMCCT Port mode control register CT R/W R/W 00H Note 1 FFFFF04CH PMCCM Port mode control register CM R/W R/W 00H Note 1 FFFFF04EH PMCCD Port mode control register CD R/W R/W 00H Note 1 FFFFF060H CSC0 Chip area select control register 0 R/W 2C11H Note 2 FFFFF062H CSC1 Chip area select control register 1 R/W 2C11H Note 2 FFFFF064H BPC Peripheral area select control register R/W 0FFFH FFFFF066H BSC Bus size configuration register R/W AAAAH Note 2 FFFFF068H BEC Endian configuration register R/W 0000H Note 2 FFFFF06EH VSWC System wait control register FFFFF100H IMR0 Interrupt mask register 0 R/W R/W 77H R/W FFFFH FFFFF100H IMR0L Interrupt mask register 0L R/W R/W FFH FFFFF101H IMR0H Interrupt mask register 0H R/W R/W FFH FFFFF102H IMR1 Interrupt mask register 1 R/W FFFFH FFFFF102H IMR1L Interrupt mask register 1L R/W R/W FFH FFFFF103H IMR1H Interrupt mask register 1H R/W R/W FFH FFFFF104H IMR2 Interrupt mask register 2 R/W FFFFH FFFFF104H IMR2L Interrupt mask register 2L R/W R/W FFH FFFFF105H IMR2H Interrupt mask register 2H R/W R/W FFH FFFFF106H IMR3 Interrupt mask register 3 R/W FFFFH FFFFF106H IMR3L Interrupt mask register 3L R/W R/W FFH FFFFF107H IMR3H Interrupt mask register 3H R/W R/W FFH FFFFF108H IMR4 Interrupt mask register 4 R/W FFFFH FFFFF108H IMR4L Interrupt mask register 4L R/W R/W FFH FFFFF109H IMR4H Interrupt mask register 4H R/W R/W FFH FFFFF10AH IMR5 Interrupt mask register 5 R/W FFFFH FFFFF10AH IMR5L Interrupt mask register 5L R/W R/W FFH FFFFF10BH IMR5H Interrupt mask register 5H R/W R/W FFH FFFFF10CH IMR6 Interrupt mask register 6 R/W FFFFH FFFFF10CH IMR6L Interrupt mask register 6L R/W R/W FFH FFFFF10DH IMR6H Interrupt mask register 6H R/W R/W FFH FFFFF10EH IMR7 Interrupt mask register 7 R/W FFFFH FFFFF10EH IMR7L Interrupt mask register 7L R/W R/W FFH FFFFF10FH IMR7H Interrupt mask register 7H R/W R/W FFH FFFFF110H PIC0 Interrupt control register 0 R/W R/W 47H FFFFF112H PIC1 Interrupt control register 1 R/W R/W 47H FFFFF114H PIC2 Interrupt control register 2 R/W R/W 47H FFFFF116H PIC3 Interrupt control register 3 R/W R/W 47H FFFFF118H PIC4 Interrupt control register 4 R/W R/W 47H 108 User's Manual U16580EE3V1UD00 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (3/14) Function Register Name Bit Units for Manipulation 1 8 Reset 16 FFFFF11AH PIC5 Interrupt control register 5 R/W R/W 47H FFFFF11CH PIC6 Interrupt control register 6 R/W R/W 47H FFFFF11EH PIC7 Interrupt control register 7 R/W R/W 47H FFFFF120H PIC8 Interrupt control register 8 R/W R/W 47H FFFFF122H PIC9 Interrupt control register 9 R/W R/W 47H FFFFF124H PIC10 Interrupt control register 10 R/W R/W 47H FFFFF126H PIC11 Interrupt control register 11 R/W R/W 47H FFFFF128H PIC12 Interrupt control register 12 R/W R/W 47H FFFFF12AH PIC13 Interrupt control register 13 R/W R/W 47H FFFFF12CH PIC14 Interrupt control register 14 R/W R/W 47H FFFFF12EH PIC15 Interrupt control register 15 R/W R/W 47H FFFFF130H PIC16 Interrupt control register 16 R/W R/W 47H FFFFF132H PIC17 Interrupt control register 17 R/W R/W 47H FFFFF134H PIC18 Interrupt control register 18 R/W R/W 47H FFFFF136H PIC19 Interrupt control register 19 R/W R/W 47H FFFFF138H PIC20 Interrupt control register 20 R/W R/W 47H FFFFF13AH PIC21 Interrupt control register 21 R/W R/W 47H FFFFF13CH PIC22 Interrupt control register 22 R/W R/W 47H FFFFF13EH PIC23 Interrupt control register 23 R/W R/W 47H FFFFF140H PIC24 Interrupt control register 24 R/W R/W 47H FFFFF142H PIC25 Interrupt control register 25 R/W R/W 47H FFFFF144H PIC26 Interrupt control register 26 R/W R/W 47H FFFFF146H PIC27 Interrupt control register 27 R/W R/W 47H FFFFF148H PIC28 Interrupt control register 28 R/W R/W 47H FFFFF14AH PIC29 Interrupt control register 29 R/W R/W 47H FFFFF14CH PIC30 Interrupt control register 30 R/W R/W 47H FFFFF14EH PIC31 Interrupt control register 31 R/W R/W 47H FFFFF150H PIC32 Interrupt control register 32 R/W R/W 47H FFFFF152H PIC33 Interrupt control register 33 R/W R/W 47H FFFFF154H PIC34 Interrupt control register 34 R/W R/W 47H FFFFF156H PIC35 Interrupt control register 35 R/W R/W 47H FFFFF158H PIC36 Interrupt control register 36 R/W R/W 47H FFFFF15AH PIC37 Interrupt control register 37 R/W R/W 47H FFFFF15CH PIC38 Interrupt control register 38 R/W R/W 47H FFFFF15EH PIC39 Interrupt control register 39 R/W R/W 47H FFFFF160H PIC40 Interrupt control register 40 R/W R/W 47H FFFFF162H PIC41 Interrupt control register 41 R/W R/W 47H FFFFF164H PIC42 Interrupt control register 42 R/W R/W 47H FFFFF166H PIC43 Interrupt control register 43 R/W R/W 47H FFFFF168H PIC44 Interrupt control register 44 R/W R/W 47H User's Manual U16580EE3V1UD00 Remarks 109 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (4/14) Function Register Name Bit Units for Manipulation 1 8 Reset Remarks 16 FFFFF16AH PIC45 Interrupt control register 45 R/W R/W 47H FFFFF16CH PIC46 Interrupt control register 46 R/W R/W 47H FFFFF16EH PIC47 Interrupt control register 47 R/W R/W 47H FFFFF170H PIC48 Interrupt control register 48 R/W R/W 47H FFFFF172H PIC49 Interrupt control register 49 R/W R/W 47H FFFFF174H PIC50 Interrupt control register 50 R/W R/W 47H FFFFF176H PIC51 Interrupt control register 51 R/W R/W 47H FFFFF178H PIC52 Interrupt control register 52 R/W R/W 47H FFFFF17AH PIC53 Interrupt control register 53 R/W R/W 47H FFFFF17CH PIC54 Interrupt control register 54 R/W R/W 47H FFFFF17EH PIC55 Interrupt control register 55 R/W R/W 47H FFFFF180H PIC56 Interrupt control register 56 R/W R/W 47H FFFFF182H PIC57 Interrupt control register 57 R/W R/W 47H FFFFF184H PIC58 Interrupt control register 58 R/W R/W 47H FFFFF186H PIC59 Interrupt control register 59 R/W R/W 47H FFFFF188H PIC60 Interrupt control register 60 R/W R/W 47H FFFFF18AH PIC61 Interrupt control register 61 R/W R/W 47H FFFFF18CH PIC62 Interrupt control register 62 R/W R/W 47H FFFFF18EH PIC63 Interrupt control register 63 R/W R/W 47H FFFFF190H PIC64 Interrupt control register 64 R/W R/W 47H FFFFF192H PIC65 Interrupt control register 65 R/W R/W 47H FFFFF194H PIC66 Interrupt control register 66 R/W R/W 47H FFFFF196H PIC67 Interrupt control register 67 R/W R/W 47H FFFFF198H PIC68 Interrupt control register 68 R/W R/W 47H FFFFF19AH PIC69 Interrupt control register 69 R/W R/W 47H FFFFF19CH PIC70 Interrupt control register 70 R/W R/W 47H FFFFF19EH PIC71 Interrupt control register 71 R/W R/W 47H FFFFF1A0H PIC72 Interrupt control register 72 R/W R/W 47H FFFFF1A2H PIC73 Interrupt control register 73 R/W R/W 47H FFFFF1A4H PIC74 Interrupt control register 74 R/W R/W 47H FFFFF1A6H PIC75 Interrupt control register 75 R/W R/W 47H Note 2 FFFFF1A8H PIC76 Interrupt control register 76 R/W R/W 47H Note 2 FFFFF1AAH PIC77 Interrupt control register 77 R/W R/W 47H Note 2 FFFFF1ACH PIC78 Interrupt control register 78 R/W R/W 47H Note 2 FFFFF1AEH PIC79 Interrupt control register 79 R/W R/W 47H FFFFF1B0H PIC80 Interrupt control register 80 R/W R/W 47H FFFFF1B2H PIC81 Interrupt control register 81 R/W R/W 47H FFFFF1B4H PIC82 Interrupt control register 82 R/W R/W 47H Note 2 FFFFF1B6H PIC83 Interrupt control register 83 R/W R/W 47H Note 2 FFFFF1B8H PIC84 Interrupt control register 84 R/W R/W 47H Note 2 110 User's Manual U16580EE3V1UD00 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (5/14) Function Register Name Bit Units for Manipulation 1 8 Reset Remarks 16 FFFFF1BAH PIC85 Interrupt control register 85 R/W R/W 47H FFFFF1BCH PIC86 Interrupt control register 86 R/W R/W 47H FFFFF1BEH PIC87 Interrupt control register 87 R/W R/W 47H Note 2 FFFFF1C0H PIC88 Interrupt control register 88 R/W R/W 47H Note 2 FFFFF1C2H PIC89 Interrupt control register 89 R/W R/W 47H FFFFF1C4H PIC90 Interrupt control register 90 R/W R/W 47H FFFFF1C6H PIC91 Interrupt control register 91 R/W R/W 47H FFFFF1C8H PIC92 Interrupt control register 92 R/W R/W 47H FFFFF1CAH PIC93 Interrupt control register 93 R/W R/W 47H FFFFF1CCH PIC94 Interrupt control register 94 R/W R/W 47H FFFFF1CEH PIC95 Interrupt control register 95 R/W R/W 47H FFFFF1D0H PIC96 Interrupt control register 96 R/W R/W 47H FFFFF1D2H PIC97 Interrupt control register 97 R/W R/W 47H Note 2 FFFFF1D4H PIC98 Interrupt control register 98 R/W R/W 47H Note 2 FFFFF1D6H PIC99 Interrupt control register 99 R/W R/W 47H Note 2 FFFFF1D8H PIC100 Interrupt control register 100 R/W R/W 47H Note 2 FFFFF1DAH PIC101 Interrupt control register 101 R/W R/W 47H Note 2 FFFFF1DCH PIC102 Interrupt control register 102 R/W R/W 47H Note 2 FFFFF1DEH PIC103 Interrupt control register 103 R/W R/W 47H FFFFF1E0H PIC104 Interrupt control register 104 R/W R/W 47H FFFFF1E2H PIC105 Interrupt control register 105 R/W R/W 47H FFFFF1FAH ISPR Interrupt service priority register R R 00H W undefined FFFFF1FCH PRCMD Command register FFFFF200H ADM00 A/D converter 0 mode register 0 R/W R/W 00H FFFFF201H ADM01 A/D converter 0 mode register 1 R/W R/W 00H FFFFF202H ADM02 A/D converter 0 mode register 2 R/W R/W 00H FFFFF210H ADCR00 A/D conversion result register 00 FFFFF211H ADCR00H FFFFF212H ADCR01 FFFFF213H ADCR01H FFFFF214H ADCR02 FFFFF215H ADCR02H FFFFF216H ADCR03 FFFFF217H ADCR03H FFFFF218H ADCR04 FFFFF219H ADCR04H FFFFF21AH ADCR05 FFFFF21BH ADCR05H FFFFF21CH ADCR06 FFFFF21DH ADCR06H A/D conversion result register 00H R R A/D conversion result register 01 A/D conversion result register 01H A/D conversion result register 02H R R A/D conversion result register 04H R A/D conversion result register 05H R A/D conversion result register 06H R User's Manual U16580EE3V1UD00 undefined undefined R R undefined undefined R A/D conversion result register 06 undefined undefined R A/D conversion result register 05 undefined undefined R A/D conversion result register 04 undefined undefined R A/D conversion result register 03 A/D conversion result register 03H undefined R A/D conversion result register 02 undefined undefined undefined 111 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (6/14) Function Register Name Bit Units for Manipulation 1 FFFFF21EH ADCR07 FFFFF21FH ADCR07H FFFFF220H ADCR08 FFFFF221H ADCR08H FFFFF222H ADCR09 FFFFF223H ADCR09H 8 A/D conversion result register 07 16 R A/D conversion result register 07H R A/D conversion result register 08 R A/D conversion result register 09 undefined undefined R A/D conversion result register 09H undefined undefined R A/D conversion result register 08H Reset R undefined undefined FFFFF22EH ADDMA0 A/D conversion result register 0 for DMA FFFFF240H ADM10 A/D converter 1 mode register 0 R/W R/W 00H FFFFF241H ADM11 A/D converter 1 mode register 1 R/W R/W 00H FFFFF242H ADM12 A/D converter 1 mode register 2 R/W R/W 00H FFFFF250H ADCR10 A/D conversion result register 10 FFFFF251H ADCR10H FFFFF252H ADCR11 FFFFF253H ADCR11H FFFFF254H ADCR112 FFFFF255H ADCR12H FFFFF256H ADCR13 FFFFF257H ADCR13H FFFFF258H ADCR14 FFFFF259H ADCR14H FFFFF25AH ADCR15 FFFFF25BH ADCR15H FFFFF25CH ADCR16 FFFFF25DH ADCR16H FFFFF25EH ADCR17 FFFFF25FH ADCR17H FFFFF260H ADCR18 FFFFF261H ADCR18H FFFFF262H ADCR19 FFFFF263H ADCR19H R R A/D conversion result register 10H R A/D conversion result register 11 R A/D conversion result register 12 R A/D conversion result register 13 R A/D conversion result register 14 R A/D conversion result register 15 R A/D conversion result register 16 R A/D conversion result register 17 R A/D conversion result register 18 R A/D conversion result register 19 undefined undefined R A/D conversion result register 19H undefined undefined R A/D conversion result register 18H undefined undefined R A/D conversion result register 17H undefined undefined R A/D conversion result register 16H undefined undefined R A/D conversion result register 15H undefined undefined R A/D conversion result register 14H undefined undefined R A/D conversion result register 13H undefined undefined R A/D conversion result register 12H undefined undefined R A/D conversion result register 11H undefined R undefined undefined FFFFF26EH ADDMA1 A/D conversion result register 1 for DMA FFFFF270H ADTRSEL0 A/D trigger select register 0 R/W R/W 00H FFFFF272H ADTRSEL1 A/D trigger select register 1 R/W R/W 00H FFFFF300H MAR0 Memory transfer start address register 0 R/W undefined FFFFF302H MAR1 Memory transfer start address register 1 R/W undefined FFFFF304H MAR2 Memory transfer start address register 2 R/W undefined FFFFF306H MAR3 Memory transfer start address register 3 R/W undefined FFFFF308H MAR4 Memory transfer start address register 4 R/W undefined FFFFF30AH MAR5 Memory transfer start address register 5 R/W undefined FFFFF30CH MAR6 Memory transfer start address register 6 R/W undefined 112 R User's Manual U16580EE3V1UD00 undefined Remarks Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (7/14) Function Register Name Bit Units for Manipulation 1 8 Reset Remarks 16 FFFFF30EH MAR7 Memory transfer start address register 7 R/W undefined FFFFF314H SAR2 SFR transfer start address register 2 R/W R/W undefined FFFFF316H SAR3 SFR transfer start address register 3 R/W R/W undefined FFFFF320H DTCR0 DMA transfer count register 0 R/W R/W undefined FFFFF322H DTCR1 DMA transfer count register 1 R/W R/W undefined FFFFF324H DTCR2 DMA transfer count register 2 R/W R/W undefined FFFFF326H DTCR3 DMA transfer count register 3 R/W R/W undefined FFFFF328H DTCR4 DMA transfer count register 4 R/W R/W undefined FFFFF32AH DTCR5 DMA transfer count register 5 R/W R/W undefined FFFFF32CH DTCR6 DMA transfer count register 6 R/W R/W undefined FFFFF32EH DTCR7 DMA transfer count register 7 R/W R/W undefined FFFFF330H DMAMC DMA mode control register R/W R/W 00H FFFFF332H DMAS DMA status register R/W R/W 00H FFFFF334H DMADSC DMA data size control register R/W R/W 00H FFFFF348H DTFR4 DMA trigger factor register 4 R/W R/W 00H FFFFF34AH DTFR5 DMA trigger factor register 5 R/W R/W 00H FFFFF34CH DTFR6 DMA trigger factor register 6 R/W R/W 00H FFFFF34EH DTFR7 DMA trigger factor register 7 R/W R/W 00H FFFFF400H P0 Port register 0 FFFFF402H P1 Port register 1 R/W R/W undefined FFFFF404H P2 Port register 2 R/W R/W undefined FFFFF406H P3 Port register 3 R/W R/W undefined FFFFF408H P4 Port register 4 R/W R/W undefined FFFFF40AH P5 Port register 5 R/W R/W undefined FFFFF40CH P6 Port register 6 R/W R/W undefined FFFFF40EH P7 Port register 7 R/W R/W undefined FFFFF410H P8 Port register 8 R/W R/W undefined FFFFF412H P9 Port register 9 R/W R/W undefined FFFFF414H P10 Port register 10 R/W R/W undefined FFFFF422H PM1 Port mode register 1 R/W R/W FFH FFFFF424H PM2 Port mode register 2 R/W R/W FFH FFFFF426H PM3 Port mode register 3 R/W R/W FFH FFFFF428H PM4 Port mode register 4 R/W R/W FFH FFFFF42AH PM5 Port mode register 5 R/W R/W FFH FFFFF42CH PM6 Port mode register 6 R/W R/W FFH FFFFF42EH PM7 Port mode register 7 R/W R/W FFH FFFFF430H PM8 Port mode register 8 R/W R/W FFH FFFFF432H PM9 Port mode register 9 R/W R/W FFH FFFFF434H PM10 Port mode register 10 R/W R/W FFH FFFFF442H PMC1 Port mode control register 1 R/W R/W 00H R User's Manual U16580EE3V1UD00 R undefined 113 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (8/14) Function Register Name Bit Units for Manipulation 1 8 Reset Remarks 16 FFFFF444H PMC2 Port mode control register 2 R/W R/W 00H FFFFF446H PMC3 Port mode control register 3 R/W R/W 00H FFFFF448H PMC4 Port mode control register 4 R/W R/W 00H FFFFF44AH PMC5 Port mode control register 5 R/W R/W 00H FFFFF44CH PMC6 Port mode control register 6 R/W R/W 00H FFFFF44EH PMC7 Port mode control register 7 R/W R/W 00H FFFFF450H PMC8 Port mode control register 8 R/W R/W 00H FFFFF452H PMC9 Port mode control register 9 R/W R/W 00H FFFFF454H PMC10 Port mode control register 10 R/W R/W 00H FFFFF480H BCT0 Bus cycle type configuration register 0 R/W CCCCH Note 2 FFFFF482H BCT1 Bus cycle type configuration register 1 R/W CCCCH Note 2 FFFFF484H DWC0 Data wait control register 0 R/W 7777H Note 2 FFFFF486H DWC1 Data wait control register 1 R/W 7777H Note 2 FFFFF488H AWC Address wait control register R/W 0000H Note 2 FFFFF48AH BCC Bus and cycle control register R/W AAAAH Note 2 FFFFF48EH DVC Bus clock dividing control register FFFFF4C0H RAMERR iRAM parity error flag register FFFFF4C2H RAMPADD iRAM parity error address register FFFFF580H TR0CTL0 TMR0 control register 0 R/W R/W 00H FFFFF581H TR0CTL1 TMR0 control register 1 R/W R/W 00H FFFFF582H TR0IOC0 TMR0 I/O control register 0 R/W R/W 00H FFFFF585H TR0IOC3 TMR0 I/O control register 3 R/W R/W 00H FFFFF586H TR0IOC4 TMR0 I/O control register 4 R/W R/W 00H FFFFF587H TR0OPT0 TMR0 option register 0 R/W R/W 00H FFFFF588H TR0OPT2 TMR0 option register 2 R/W R/W 00H FFFFF589H TR0OPT3 TMR0 option register 3 R/W R/W 00H FFFFF58CH TR0OPT6 TMR0 option register 6 R/W R/W 00H FFFFF58DH TR0OPT7 TMR0 option register 7 R/W R/W 00H FFFFF58EH TR0OPT1 TMR0 option register 1 R/W R/W 00H FFFFF590H TR0CCR5 TMR0 capture/compare register 5 R/W 0000H FFFFF592H TR0CCR4 TMR0 capture/compare register 4 R/W 0000H FFFFF598H TR0CCR0 TMR0 capture/compare register 0 R/W 0000H FFFFF59AH TR0CCR3 TMR0 capture/compare register 3 R/W 0000H FFFFF59CH TR0CCR2 TMR0 capture/compare register 2 R/W 0000H FFFFF59EH TR0CCR1 TMR0 capture/compare register 1 R/W 0000H FFFFF5A0H TR0DTC0 TMR0 dead time set register 0 R/W 0000H FFFFF5A2H TR0DTC1 TMR0 dead time set register 1 R/W 0000H FFFFF5A4H TR0CNT TMR0 timer counter read register R/W 0000H FFFFF5A6H TR0SBC TMR0 timer sub-counter read register R/W 0000H FFFFF5C0H TR1CTL0 TMR1 control register 0 114 R/W 01H R/W R/W 00H R/W 8000H R/W R/W User's Manual U16580EE3V1UD00 00H Note 2 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (9/14) Function Register Name Bit Units for Manipulation 1 8 Reset 16 FFFFF5C1H TR1CTL1 TMR1 control register 1 R/W R/W 00H FFFFF5C2H TR1IOC0 TMR1 I/O control register 0 R/W R/W 00H FFFFF5C3H TR1IOC1 TMR1 I/O control register 1 R/W R/W 00H FFFFF5C4H TR1IOC2 TMR1 I/O control register 2 R/W R/W 00H FFFFF5C5H TR1IOC3 TMR1 I/O control register 3 R/W R/W 00H FFFFF5C6H TR1IOC4 TMR1 I/O control register 4 R/W R/W 00H FFFFF5C7H TR1OPT0 TMR1 option register 0 R/W R/W 00H FFFFF5C8H TR1OPT2 TMR1 option register 2 R/W R/W 00H FFFFF5C9H TR1OPT3 TMR1 option register 3 R/W R/W 00H FFFFF5CCH TR1OPT6 TMR1 option register 6 R/W R/W 00H FFFFF5CDH TR1OPT7 TMR1 option register 7 R/W R/W 00H FFFFF5CEH TR1OPT1 TMR1 option register 1 R/W R/W 00H FFFFF5D0H TR1CCR5 TMR1 capture/compare register 5 R/W 0000H FFFFF5D2H TR1CCR4 TMR1 capture/compare register 4 R/W 0000H FFFFF5D8H TR1CCR0 TMR1 capture/compare register 0 R/W 0000H FFFFF5DAH TR1CCR3 TMR1 capture/compare register 3 R/W 0000H FFFFF5DCH TR1CCR2 TMR1 capture/compare register 2 R/W 0000H FFFFF5DEH TR1CCR1 TMR1 capture/compare register 1 R/W 0000H FFFFF5E0H TR1DTC0 TMR1 dead time set register 0 R/W 0000H FFFFF5E2H TR1DTC1 TMR1 dead time set register 1 R/W 0000H FFFFF5E4H TR1CNT TMR1 timer counter read register R 0000H FFFFF5E6H TR1SBC TMR1 timer sub-counter read register R 0000H FFFFF600H TP0CTL0 TMP0 timer control register 0 R/W R/W 00H FFFFF601H TP0CTL1 TMP0 timer control register 1 R/W R/W 00H FFFFF602H TP0IOC0 TMP0 I/O control register 0 R/W R/W 00H FFFFF603H TP0IOC1 TMP0 I/O control register 1 R/W R/W 00H FFFFF604H TP0IOC2 TMP0 I/O control register 2 R/W R/W 00H FFFFF605H TP0OPT0 TMP0 option register R/W R/W 00H FFFFF606H TP0CCR0 TMP0 capture/compare register 0 R/W 0000H FFFFF608H TP0CCR1 TMP0 capture/compare register 1 R/W 0000H FFFFF60AH TP0CNT TMP0 count register FFFFF610H TP1CTL0 TMP1 timer control register 0 R/W R/W 00H FFFFF611H TP1CTL1 TMP1 timer control register 1 R/W R/W 00H FFFFF612H TP1IOC0 TMP1 I/O control register 0 R/W R/W 00H FFFFF613H TP1IOC1 TMP1 I/O control register 1 R/W R/W 00H FFFFF614H TP1IOC2 TMP1 I/O control register 2 R/W R/W 00H FFFFF615H TP1OPT0 TMP1 option register R/W R/W 00H FFFFF616H TP1CCR0 TMP1 capture/compare register 0 R/W 0000H FFFFF618H TP1CCR1 TMP1 capture/compare register 1 R/W 0000H FFFFF61AH TP1CNT TMP1 count register R User's Manual U16580EE3V1UD00 Remarks R 0000H 0000H 115 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (10/14) Function Register Name Bit Units for Manipulation 1 8 Reset 16 FFFFF620H TP2CTL0 TMP2 timer control register 0 R/W R/W 00H FFFFF621H TP2CTL1 TMP2 timer control register 1 R/W R/W 00H FFFFF622H TP2IOC0 TMP2 I/O control register 0 R/W R/W 00H FFFFF623H TP2IOC1 TMP2 I/O control register 1 R/W R/W 00H FFFFF624H TP2IOC2 TMP2 I/O control register 2 R/W R/W 00H FFFFF625H TP2OPT0 TMP2 option register R/W R/W 00H FFFFF626H TP2CCR0 TMP2 capture/compare register 0 R/W 0000H FFFFF628H TP2CCR1 TMP2 capture/compare register 1 R/W 0000H FFFFF62AH TP2CNT TMP2 count register FFFFF630H TP3CTL0 TMP3 timer control register 0 R/W R/W 00H FFFFF631H TP3CTL1 TMP3 timer control register 1 R/W R/W 00H FFFFF632H TP3IOC0 TMP3 I/O control register 0 R/W R/W 00H FFFFF633H TP3IOC1 TMP3 I/O control register 1 R/W R/W 00H FFFFF634H TP3IOC2 TMP3 I/O control register 2 R/W R/W 00H FFFFF635H TP3OPT0 TMP3 option register R/W R/W 00H FFFFF636H TP3CCR0 TMP3 capture/compare register 0 R/W 0000H FFFFF638H TP3CCR1 TMP3 capture/compare register 1 R/W 0000H FFFFF63AH TP3CNT TMP3 count register FFFFF640H TP4CTL0 TMP4 timer control register 0 R/W R/W 00H FFFFF641H TP4CTL1 TMP4 timer control register 1 R/W R/W 00H FFFFF642H TP4IOC0 TMP4 I/O control register 0 R/W R/W 00H FFFFF643H TP4IOC1 TMP4 I/O control register 1 R/W R/W 00H FFFFF644H TP4IOC2 TMP4 I/O control register 2 R/W R/W 00H FFFFF645H TP4OPT0 TMP4 option register R/W R/W 00H FFFFF646H TP4CCR0 TMP4 capture/compare register 0 R/W 0000H FFFFF648H TP4CCR1 TMP4 capture/compare register 1 R/W 0000H FFFFF64AH TP4CNT TMP4 count register FFFFF650H TP5CTL0 TMP5 timer control register 0 R/W R/W 00H FFFFF651H TP5CTL1 TMP5 timer control register 1 R/W R/W 00H FFFFF652H TP5IOC0 TMP5 I/O control register 0 R/W R/W 00H FFFFF653H TP5IOC1 TMP5 I/O control register 1 R/W R/W 00H FFFFF654H TP5IOC2 TMP5 I/O control register 2 R/W R/W 00H FFFFF655H TP5OPT0 TMP5 option register R/W R/W 00H FFFFF656H TP5CCR0 TMP5 capture/compare register 0 R/W 0000H FFFFF658H TP5CCR1 TMP5 capture/compare register 1 R/W 0000H FFFFF65AH TP5CNT TMP5 count register FFFFF660H TP6CTL0 TMP6 timer control register 0 R/W R/W 00H FFFFF661H TP6CTL1 TMP6 timer control register 1 R/W R/W 00H FFFFF662H TP6IOC0 TMP6 I/O control register 0 R/W R/W 00H FFFFF663H TP6IOC1 TMP6 I/O control register 1 R/W R/W 00H 116 R R R R User's Manual U16580EE3V1UD00 0000H 0000H 0000H 0000H Remarks Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (11/14) Function Register Name Bit Units for Manipulation 1 8 Reset 16 FFFFF664H TP6IOC2 TMP6 I/O control register 2 R/W R/W 00H FFFFF665H TP6OPT0 TMP6 option register R/W R/W 00H FFFFF666H TP6CCR0 TMP6 capture/compare register 0 R/W 0000H FFFFF668H TP6CCR1 TMP6 capture/compare register 1 R/W 0000H FFFFF66AH TP6CNT TMP6 count register FFFFF670H TP7CTL0 TMP7 timer control register 0 R/W R/W 00H FFFFF671H TP7CTL1 TMP7 timer control register 1 R/W R/W 00H FFFFF672H TP7IOC0 TMP7 I/O control register 0 R/W R/W 00H FFFFF673H TP7IOC1 TMP7 I/O control register 1 R/W R/W 00H FFFFF674H TP7IOC2 TMP7 I/O control register 2 R/W R/W 00H FFFFF675H TP7OPT0 TMP7 option register R/W R/W 00H FFFFF676H TP7CCR0 TMP7 capture/compare register 0 R/W 0000H FFFFF678H TP7CCR1 TMP7 capture/compare register 1 R/W 0000H FFFFF67AH TP7CNT TMP7 count register FFFFF680H TP8CTL0 TMP8 timer control register 0 R/W R/W 00H FFFFF681H TP8CTL1 TMP8 timer control register 1 R/W R/W 00H FFFFF682H TP8IOC0 TMP8 I/O control register 0 R/W R/W 00H FFFFF683H TP8IOC1 TMP8 I/O control register 1 R/W R/W 00H FFFFF684H TP8IOC2 TMP8 I/O control register 2 R/W R/W 00H FFFFF685H TP8OPT0 TMP8 option register R/W R/W 00H FFFFF686H TP8CCR0 TMP8 capture/compare register 0 R/W 0000H FFFFF688H TP8CCR1 TMP8 capture/compare register 1 R/W 0000H FFFFF68AH TP8CNT TMP8 count register FFFFF690H TT0CTL0 TMT0 timer control register 0 R/W R/W 00H FFFFF691H TT0CTL1 TMT0 timer control register 1 R/W R/W 00H FFFFF692H TT0CTL2 TMT0 timer control register 2 R/W R/W 00H FFFFF693H TT0IOC0 TMT0 I/O control register 0 R/W R/W 00H FFFFF694H TT0IOC1 TMT0 I/O control register 1 R/W R/W 00H FFFFF695H TT0IOC2 TMT0 I/O control register 2 R/W R/W 00H FFFFF696H TT0IOC3 TMT0 I/O control register 3 R/W R/W 00H FFFFF697H TT0OPT0 TMT0 option register 0 R/W R/W 00H FFFFF698H TT0OPT1 TMT0 option register 1 R/W R/W 00H FFFFF699H TT0OPT2 TMT0 option register 2 R/W R/W 00H FFFFF69AH TT0CCR0 TMT0 capture/compare register 0 R/W 0000H FFFFF69CH TT0CCR1 TMT0 capture/compare register 1 R/W 0000H FFFFF69EH TT0CNT TMT0 counter read register FFFFF6A0H TT1CTL0 TMT1 timer control register 0 R/W R/W 00H FFFFF6A1H TT1CTL1 TMT1 timer control register 1 R/W R/W 00H FFFFF6A2H TT1CTL2 TMT1 timer control register 2 R/W R/W 00H FFFFF6A3H TT1IOC0 TMT1 I/O control register 0 R/W R/W 00H R R R R User's Manual U16580EE3V1UD00 Remarks 0000H 0000H 0000H 0000H 117 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (12/14) Function Register Name Bit Units for Manipulation 1 8 Reset Remarks 16 FFFFF6A4H TT1IOC1 TMT1 I/O control register 1 R/W R/W 00H FFFFF6A5H TT1IOC2 TMT1 I/O control register 2 R/W R/W 00H FFFFF6A6H TT1IOC3 TMT1 I/O control register 3 R/W R/W 00H FFFFF6A7H TT1OPT0 TMT1 option register 0 R/W R/W 00H FFFFF6A8H TT1OPT1 TMT1 option register 1 R/W R/W 00H FFFFF6A9H TT1OPT2 TMT1 option register 2 R/W R/W 00H FFFFF6AAH TT1CCR0 TMT1 capture/compare register 0 R/W 0000H FFFFF6ACH TT1CCR1 TMT1 capture/compare register 1 R/W 0000H FFFFF6AEH TT1CNT TMT1 counter read register FFFFF6B0H TMENC10 Timer ENC10 count register R/W 0000H Note 2 FFFFF6B2H CM100 Compare register 100 R/W 0000H Note 2 FFFFF6B4H CM101 Compare register 101 R/W 0000H Note 2 FFFFF6B6H CC100 Capture/Compare register 100 R/W 0000H Note 2 FFFFF6B8H CC101 Capture/Compare register 101 R/W 0000H Note 2 R 0000H FFFFF6BAH CCR10 Capture/Compare control register 10 R/W R/W 00H Note 2 FFFFF6BBH TUM10 Timer unit mode register 10 R/W R/W 00H Note 2 FFFFF6BCH TMC10 Timer control register 10 R/W R/W 00H Note 2 FFFFF6BDH SESA10 Signal edge selection register 10 R/W R/W 00H Note 2 FFFFF6BEH PRM10 Prescaler mode register 10 R/W R/W 07H Note 2 FFFFF6BFH STATUS10 Status register 10 00H Note 2 FFFFF6F0H TPIC0 TMP input source control register 0 R/W R/W 00H FFFFF6F2H TPIC1 TMP input source control register 1 R/W R/W 00H FFFFF6F4H TPIC2 TMP input source control register 2 R/W R/W 00H FFFFF700H RNG Random number register FFFFF7A0H NRC Noise removal time control register R/W R/W 00H FFFFF802H PHS Peripheral status register R/W R/W 00H FFFFF880H INTM0 Interrupt mode register 0 R/W R/W 00H FFFFF882H INTM1 Interrupt mode register 1 R/W R/W 00H FFFFF884H INTM2 Interrupt mode register 2 R/W R/W 00H FFFFF886H INTM3 Interrupt mode register 3 R/W R/W 00H FFFFF888H PESC5 Port emergency shut off control register 5 R/W R/W 00H FFFFF88AH ESOST5 Port emergency shut off status register 5 R/W R/W 00H FFFFF88CH PESC6 Port emergency shut off control register 6 R/W R/W 00H FFFFF88EH ESOST6 Port emergency shut off status register 6 00H FFFFF990H TT0TCW Timer T0 counter write buffer register R/W 0000H FFFFF9A0H TT1TCW Timer T1 counter write buffer register R/W 0000H FFFFFA00H UC0CTL0 UARTC0 control register 0 R/W R/W 10H FFFFFA01H UC0CTL1 UARTC0 control register 1 R/W 00H FFFFFA02H UC0CTL2 UARTC0 control register 2 R/W 00H FFFFFA03H UC0OPT0 UARTC0 option control register 0 R/W R/W 14H 118 R R R R/W R/W User's Manual U16580EE3V1UD00 undefined Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (13/14) Function Register Name Bit Units for Manipulation 1 FFFFFA04H UC0STR UARTC0 status register FFFFFA06H UC0RX UARTC0 receive data register FFFFFA06H UC0RXL FFFFFA08H UC0TX FFFFFA08H UC0TXL 8 00H R R UARTC0 transmit data register 01FFH FFH R/W 01FFH UARTC0 transmit data register L R/W FFH R/W R/W 00H FFFFFA0AH UC0OPT1 UARTC0 option control register 1 FFFFFA0BH UC0STR1 UARTC0 status register 1 FFFFFA20H UC1CTL0 UARTC1 control register 0 R/W R/W 10H FFFFFA21H UC1CTL1 UARTC1 control register 1 R/W 00H FFFFFA22H UC1CTL2 UARTC1 control register 2 R/W 00H FFFFFA23H UC1OPT0 UARTC1 option control register 0 R/W R/W 14H FFFFFA24H UC1STR UARTC1 status register R/W R/W 00H FFFFFA26H UC1RX UARTC1 receive data register FFFFFA26H UC1RXL FFFFFA28H UC1TX FFFFFA28H UC1TXL Remarks 16 R/W R/W UARTC0 receive data register L Reset R R 00H R UARTC1 receive data register L R UARTC1 transmit data register 01FFH FFH R/W 01FFH UARTC1 transmit data register L R/W FFH R/W R/W 00H FFFFFA2AH UC1OPT1 UARTC1 option control register 1 FFFFFA2BH UC1STR1 UARTC1 status register 1 FFFFFD00H CB0CTL0 CSIB0 control register 0 R/W R/W 01H FFFFFD01H CB0CTL1 CSIB0 control register 1 R/W R/W 00H FFFFFD02H CB0CTL2 CSIB0 control register 2 R/W 00H FFFFFD03H CB0STR CSIB0 state register R/W R/W 00H FFFFFD04H CB0RX0 CSIB0 receive data register FFFFFD04H CB0RX0L CSIB0 receive data register L R 00H FFFFFD06H CB0TX0L CSIB0 transmit data register L R/W 00H FFFFFD06H CB0TX0 CSIB0 transmit data register FFFFFD20H CB1CTL0 CSIB1 control register 0 R/W R/W 01H Note 2 FFFFFD21H CB1CTL1 CSIB1 control register 1 R/W R/W 00H Note 2 FFFFFD22H CB1CTL2 CSIB1 control register 2 R/W 00H Note 2 FFFFFD23H CB1STR CSIB1 state register R/W R/W 00H Note 2 FFFFFD24H CB1RX0 CSIB1 receive data register 0000H Note 2 FFFFFD24H CB1RX0L CSIB1 receive data register L R 00H Note 2 FFFFFD26H CB1TX0L CSIB1 transmit data register L R/W 00H Note 2 FFFFFD26H CB1TX0 CSIB1 transmit data register FFFFFD40H CSIM30 CSI30 operation mode register R/W R/W 00H FFFFFD41H CSIC30 CSI30 clock selection register R/W R/W 07H FFFFFD42H SIRB30 CSI30 receive data buffer register FFFFFD42H SIRB30L CSI30 receive data buffer register L R 00H FFFFFD43H SIRB30H CSI30 receive data buffer register H R 00H FFFFFD44H SFCS30L CSI30 chip selection CSI buffer register L R/W R/W R R 00H R 0000H R/W 0000H R R/W 0000H User's Manual U16580EE3V1UD00 R Note 2 0000H FFH 119 Chapter 3 Table 3-5: Address Symbol CPU Functions Peripheral I/O Registers (14/14) Function Register Name Bit Units for Manipulation 1 FFFFFD44H SFCS30 CSI30 chip selection CSI buffer register FFFFFD45H SFCS30H CSI30 chip selection CSI buffer register H FFFFFD46H SFDB30L CSI30 transmit data CSI buffer register L FFFFFD46H SFDB30 CSI30 transmit data CSI buffer register FFFFFD47H SFDB30H CSI30 transmit data CSI buffer register H FFFFFD48H SFA30 FFFFFD49H 8 Reset Remarks 16 R/W FFFFH R R FFH R/W 00H R/W 0000H R/W 00H CSI30 SIBUF state register R/W R/W 20H CSIL30 CSI30 transfer data length select register R/W R/W 00H FFFFFD4CH SFN30 CSI30 transfer data number specification register R/W R/W 00H FFFFFD60H CSIM31 CSI31 operation mode register R/W R/W 00H Note 2 FFFFFD61H CSIC31 CSI31 clock selection register R/W R/W 07H Note 2 FFFFFD62H SIRB31 CSI31 receive data buffer register 0000H Note 2 FFFFFD62H SIRB31L CSI31 receive data buffer register L R 00H Note 2 FFFFFD63H SIRB31H CSI31 receive data buffer register H R 00H Note 2 FFFFFD64H SFCS31L CSI31 chip selection CSI buffer register L R/W R/W FFH Note 2 FFFFFD64H SFCS31 CSI31 chip selection CSI buffer register FFFFFD65H SFCS31H CSI31 chip selection CSI buffer register H FFFFFD66H SFDB31L CSI31 transmit data CSI buffer register L FFFFFD66H SFDB31 CSI31 transmit data CSI buffer register FFFFFD67H SFDB31H CSI31 transmit data CSI buffer register H FFFFFD68H SFA31 FFFFFD69H R R/W FFFFH R Note 2 R FFH Note 2 R/W 00H Note 2 R/W 0000H Note 2 R/W 00H Note 2 CSI31 SIBUF state register R/W R/W 20H Note 2 CSIL31 CSI31 transfer data length select register R/W R/W 00H Note 2 FFFFFD6CH SFN31 CSI31 transfer data number specification register R/W R/W 00H Note 2 FFFFFDC0H PRSM0 Prescaler mode register 0 R/W R/W 00H FFFFFDC1H PRSCM0 Prescaler compare register 0 R/W R/W 00H FFFFFDD0H PRSM1 Prescaler mode register 1 R/W R/W 00H FFFFFDD1H PRSCM1 Prescaler compare register 1 R/W R/W 00H FFFFFDE0H PRSM2 Prescaler mode register 2 R/W R/W 00H FFFFFDE1H PRSCM2 Prescaler compare register 2 R/W R/W 00H FFFFFE00H DMAWC0 DMA wait control register 0 R/W R/W 37H FFFFFE02H DMAWC1 DMA wait control register 1 R/W R/W 07H Notes: 1. Only writing of the reset value is permitted for this register on PD70F3447. 2. Register not available on PD70F3447. 120 User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.4.7 Programmable peripheral I/O area In the V850E/PH2, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x0000H and x08FFH is used exclusively for the CAN controllers (CAN0, CAN1Note). The internal bus of the V850E/PH2 becomes active when the on-chip peripheral I/O register area (FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n= xx11B). However, the on-chip peripheral I/O area is allocated to the last 4 KB of the programmable peripheral I/O register area. Note that when data is written to this area, the written contents are reflected on the on-chip peripheral I/O area. Therefore, access to this area is prohibited. To access the on-chip peripheral I/O area, be sure to specify addresses FFFF000H to FFFFFFFH. Figure 3-23: 3FFFFFFH 3FFF000H 3FFEFFFH xxxxNFFFH xxxxM000H Programmable Peripheral I/O Area (Outline) Peripheral I/O register Programmable peripheral I/O register Internal local bus On-chip peripheral x3FFFH x3000H I/O area x2FFFH Programmable peripheral x08FFH I/O area x0000H Dedicated area for CAN controllers 0000000H Remark: M = xx00B, N = M + 11B, P= M + 10B Cautions: 1. It is recommended to locate the programmable peripheral area in the first 32 Mbyte of the physical memory. 2. The programmable peripheral area is not allowed to overlap the ROM or RAM areas: BPC must be initialized with a value in the range 0040H to 0FFBH. Note: CAN1 not available for PD70F3447. User's Manual U16580EE3V1UD00 121 Chapter 3 (1) CPU Functions Peripheral area selection control register (BPC) The peripheral area selection control register (BPC) is used to select a programmable peripheral I/O register area where the registers of the CAN controller are allocated. This register can be read/written in 16-bit units. Figure 3-24: After reset: BPC Programmable Peripheral Area Control Register BPC 0000H 15 14 PA15 0 R/W 13 12 11 Address: 10 9 PA13 PA12 PA11 PA10 PA9 FFFFF064H 8 7 6 5 4 3 2 1 0 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 (n = 0, 1) PA15 Remark: 122 Usage of Programmable Peripheral I/O Area 0 Disables usage of programmable peripheral I/O area 1 Enables usage of programmable peripheral I/O area PA13 to PA0 Base address of Programmable Peripheral I/O Area 0000H to 3FFFH Specifies the base address of the programmable peripheral I/O area (PA13 to PA0 corresponds to A27 to A14, respectively). The recommended value of the BPC register to enable the programmable peripheral I/O area is 87FFH. This setting assigns the programmable peripheral I/O area to addresses from 1FFC000H to 1FFFFFFH. User's Manual U16580EE3V1UD00 Chapter 3 (2) CPU Functions Registers in the programmable peripheral I/O area In the following Table 3-6 the addresses shown are offsets in the programmable peripheral I/O area, which have to be added to base address set by the BPC register. Table 3-6: Programmable Peripheral I/O Registers (1/16) Address Offset Symbol 0000000H C0GMCTRL CAN0 global macro control register R/W 0000000H C0GMCTRLL CAN0 global macro control register L R/W x x 00H 0000001H C0GMCTRLH CAN0 global macro control register H R/W x x 00H 0000002H C0GMCS CAN0 global macro clock selection register R/W x x 00H 0000006H C0GMABT CAN0 global macro automatic block transmission register R/W 0000006H C0GMABTL CAN0 global macro automatic block transmission register L R/W x x 00H 0000007H C0GMABTH CAN0 global macro automatic block transmission register H R/W x x 00H 0000008H C0GMABTD CAN0 global macro automatic block transmission delay register R/W x x 00H 0000040H C0MASK1L CAN0 module mask 1 register L R/W x Undefined 0000042H C0MASK1H CAN0 module mask 1 register H R/W x Undefined 0000044H C0MASK2L CAN0 module mask 2 register L R/W x Undefined 0000046H C0MASK2H CAN0 module mask 2 register H R/W x Undefined 0000048H C0MASK3L CAN0 module mask 3 register L R/W x Undefined 000004AH C0MASK3H CAN0 module mask 3 register H R/W x Undefined 000004CH C0MASK4L CAN0 module mask 4 register L R/W x Undefined 000004EH C0MASK4H CAN0 module mask 4 register H R/W x Undefined 0000050H C0CTRL CAN0 module control register R/W x 0000H 0000052H C0LEC CAN0 module last error code register R/W x x 00H 0000053H C0INFO CAN0 module information register R x x 00H 0000054H C0ERC CAN0 module error counter R/W x 0000H 0000056H C0IE CAN0 module interrupt enable register R/W x 0000H 0000056H C0IEL CAN0 module interrupt enable register L R/W x x 00H 0000057H C0IEH CAN0 module interrupt enable register H R/W x x 00H C0INTS CAN0 module interrupt status register R/W C0INTSL CAN0 module interrupt status register L R/W x x 00H 000005AH C0BRP CAN0 module bit-rate prescaler register R/W x x FFH 000005CH C0BTR CAN0 bit-rate register R/W 000005EH C0LIPT CAN0 module last in-pointer register R/W 0000060H C0RGPT CAN0 module receive history list get pointer register R/W C0RGPTL CAN0 module receive history list get pointer register L R/W C0LOPT CAN0 module last out-pointer register 0000058H 0000058H 0000060H 0000062H Function Register Name R/W Bit Units for Manipulation 1 User's Manual U16580EE3V1UD00 R 8 16 x x x x x 0000H 0000H 0000H 370FH Undefined x x After Reset Undefined x 01H x Undefined 123 Chapter 3 Table 3-6: Address Offset 0000064H Symbol CPU Functions Programmable Peripheral I/O Registers (2/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C0TGPT CAN0 module transmit history list get pointer register R/W C0TGPTL CAN0 module transmit history list get pointer register L R/W C0TS CAN0 module time stamp register R/W 0000066H C0TSL CAN0 module time stamp register L R/W x x 00H 0000067H C0TSH CAN0 module time stamp register H R/W x x 00H C0MDATA0100 CAN0 message data byte 0 and 1 register 00 R/W 0000100H C0MDATA000 CAN0 message data byte 0 register 00 R/W x x Undefined 0000101H C0MDATA100 CAN0 message data byte 1 register 00 R/W x x Undefined C0MDATA2300 CAN0 message data byte 2 and 3 register 00 R/W 0000102H C0MDATA200 CAN0 message data byte 2 register 00 R/W x x Undefined 0000103H C0MDATA300 CAN0 message data byte 3 register 00 R/W x x Undefined C0MDATA4500 CAN0 message data byte 4 and 5 register 00 R/W 0000104H C0MDATA400 CAN0 message data byte 2 register 00 R/W x x Undefined 0000105H C0MDATA500 CAN0 message data byte 3 register 00 R/W x x Undefined C0MDATA6700 CAN0 message data byte 6 and 7 register 00 R/W 0000106H C0MDATA600 CAN0 message data byte 6 register 00 R/W x x Undefined 0000107H C0MDATA700 CAN0 message data byte 7 register 00 R/W x x Undefined 0000108H C0MDLC00 CAN0 message data length code register 00 R/W x x Undefined 0000109H C0MCONF00 CAN0 message configuration register 00 R/W x x Undefined 000010AH C0MIDL00 CAN0 message identifier L register 00 R/W x Undefined 000010CH C0MIDH00 CAN0 message identifier H register 00 R/W x Undefined 000010EH C0MCTRL00 CAN0 message control register 00 R/W x Undefined 0000120H C0MDATA0101 CAN0 message data byte 0 and 1 register 01 R/W x Undefined 0000120H C0MDATA001 CAN0 message data byte 0 register 01 R/W x x Undefined 0000121H C0MDATA101 CAN0 message data byte 1 register 01 R/W x x Undefined C0MDATA2301 CAN0 message data byte 2 and 3 register 01 R/W 0000122H C0MDATA201 CAN0 message data byte 2 register 01 R/W x x Undefined 0000123H C0MDATA301 CAN0 message data byte 3 register 01 R/W x x Undefined C0MDATA4501 CAN0 message data byte 4 and 5 register 01 R/W 0000124H C0MDATA401 CAN0 message data byte 2 register 01 R/W x x Undefined 0000125H C0MDATA501 CAN0 message data byte 3 register 01 R/W x x Undefined C0MDATA6701 CAN0 message data byte 6 and 7 register 01 R/W 0000126H C0MDATA601 CAN0 message data byte 6 register 01 R/W x x Undefined 0000127H C0MDATA701 CAN0 message data byte 7 register 01 R/W x x Undefined 0000128H C0MDLC01 CAN0 message data length code register 01 R/W x x Undefined 0000129H C0MCONF01 CAN0 message configuration register 01 R/W x x Undefined 000012AH C0MIDL01 CAN0 message identifier L register 01 R/W x Undefined 000012CH C0MIDH01 CAN0 message identifier H register 01 R/W x Undefined 000012EH C0MCTRL01 CAN0 message control register 01 R/W x Undefined 0000064H 0000066H 0000100H 0000102H 0000104H 0000106H 0000122H 0000124H 0000126H 124 User's Manual U16580EE3V1UD00 x x Undefined 01H x x x x x x x x 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Chapter 3 Table 3-6: Address Offset 0000140H Symbol CPU Functions Programmable Peripheral I/O Registers (3/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C0MDATA0102 CAN0 message data byte 0 and 1 register 02 R/W 0000140H C0MDATA002 CAN0 message data byte 0 register 02 R/W x x Undefined 0000141H C0MDATA102 CAN0 message data byte 1 register 02 R/W x x Undefined C0MDATA2302 CAN0 message data byte 2 and 3 register 02 R/W 0000142H C0MDATA202 CAN0 message data byte 2 register 02 R/W x x Undefined 0000143H C0MDATA302 CAN0 message data byte 3 register 02 R/W x x Undefined C0MDATA4502 CAN0 message data byte 4 and 5 register 02 R/W 0000144H C0MDATA402 CAN0 message data byte 2 register 02 R/W x x Undefined 0000145H C0MDATA502 CAN0 message data byte 3 register 02 R/W x x Undefined C0MDATA6702 CAN0 message data byte 6 and 7 register 02 R/W 0000146H C0MDATA602 CAN0 message data byte 6 register 02 R/W x x Undefined 0000147H C0MDATA702 CAN0 message data byte 7 register 02 R/W x x Undefined 0000148H C0MDLC02 CAN0 message data length code register 02 R/W x x Undefined 0000149H C0MCONF02 CAN0 message configuration register 02 R/W x x Undefined 000014AH C0MIDL02 CAN0 message identifier L register 02 R/W x Undefined 000014CH C0MIDH02 CAN0 message identifier H register 02 R/W x Undefined 000014EH C0MCTRL02 CAN0 message control register 02 R/W x Undefined 0000160H C0MDATA0103 CAN0 message data byte 0 and 1 register 03 R/W x Undefined 0000160H C0MDATA003 CAN0 message data byte 0 register 03 R/W x x Undefined 0000161H C0MDATA103 CAN0 message data byte 1 register 03 R/W x x Undefined C0MDATA2303 CAN0 message data byte 2 and 3 register 03 R/W 0000162H C0MDATA203 CAN0 message data byte 2 register 03 R/W x x Undefined 0000163H C0MDATA303 CAN0 message data byte 3 register 03 R/W x x Undefined C0MDATA4503 CAN0 message data byte 4 and 5 register 03 R/W 0000164H C0MDATA403 CAN0 message data byte 2 register 03 R/W x x Undefined 0000165H C0MDATA503 CAN0 message data byte 3 register 03 R/W x x Undefined C0MDATA6703 CAN0 message data byte 6 and 7 register 03 R/W 0000166H C0MDATA603 CAN0 message data byte 6 register 03 R/W x x Undefined 0000167H C0MDATA703 CAN0 message data byte 7 register 03 R/W x x Undefined 0000168H C0MDLC03 CAN0 message data length code register 03 R/W x x Undefined 0000169H C0MCONF03 CAN0 message configuration register 03 R/W x x Undefined 000016AH C0MIDL03 CAN0 message identifier L register 03 R/W x Undefined 000016CH C0MIDH03 CAN0 message identifier H register 03 R/W x Undefined 000016EH C0MCTRL03 CAN0 message control register 03 R/W x Undefined 0000180H C0MDATA0104 CAN0 message data byte 0 and 1 register 04 R/W x Undefined 0000180H C0MDATA004 CAN0 message data byte 0 register 04 R/W x x Undefined 0000181H C0MDATA104 CAN0 message data byte 1 register 04 R/W x x Undefined C0MDATA2304 CAN0 message data byte 2 and 3 register 04 R/W 0000182H C0MDATA204 CAN0 message data byte 2 register 04 R/W x x Undefined 0000183H C0MDATA304 CAN0 message data byte 3 register 04 R/W x x Undefined 0000142H 0000144H 0000146H 0000162H 0000164H 0000166H 0000182H User's Manual U16580EE3V1UD00 x x x x x x x Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 125 Chapter 3 Table 3-6: Address Offset 0000184H Symbol CPU Functions Programmable Peripheral I/O Registers (4/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C0MDATA4504 CAN0 message data byte 4 and 5 register 04 R/W 0000184H C0MDATA404 CAN0 message data byte 2 register 04 R/W x x Undefined 0000185H C0MDATA504 CAN0 message data byte 3 register 04 R/W x x Undefined C0MDATA6704 CAN0 message data byte 6 and 7 register 04 R/W 0000186H C0MDATA604 CAN0 message data byte 6 register 04 R/W x x Undefined 0000187H C0MDATA704 CAN0 message data byte 7 register 04 R/W x x Undefined 0000188H C0MDLC04 CAN0 message data length code register 04 R/W x x Undefined 0000189H C0MCONF04 CAN0 message configuration register 04 R/W x x Undefined 000018AH C0MIDL04 CAN0 message identifier L register 04 R/W x Undefined 000018CH C0MIDH04 CAN0 message identifier H register 04 R/W x Undefined 000018EH C0MCTRL04 CAN0 message control register 04 R/W x Undefined 00001A0H C0MDATA0105 CAN0 message data byte 0 and 1 register 05 R/W x Undefined 00001A0H C0MDATA005 CAN0 message data byte 0 register 05 R/W x x Undefined 00001A1H C0MDATA105 CAN0 message data byte 1 register 05 R/W x x Undefined CAN0 message data byte 2 and 3 register 05 R/W 00001A2H C0MDATA205 CAN0 message data byte 2 register 05 R/W x x Undefined 00001A3H C0MDATA305 CAN0 message data byte 3 register 05 R/W x x Undefined CAN0 message data byte 4 and 5 register 05 R/W 00001A4H C0MDATA405 CAN0 message data byte 2 register 05 R/W x x Undefined 00001A5H C0MDATA505 CAN0 message data byte 3 register 05 R/W x x Undefined CAN0 message data byte 6 and 7 register 05 R/W 00001A6H C0MDATA605 CAN0 message data byte 6 register 05 R/W x x Undefined 00001A7H C0MDATA705 CAN0 message data byte 7 register 05 R/W x x Undefined 0000186H 00001A2H 00001A4H 00001A6H C0MDATA2305 C0MDATA4505 C0MDATA6705 x x x x Undefined Undefined Undefined Undefined Undefined 00001A8H C0MDLC05 CAN0 message data length code register 05 R/W x x Undefined 00001A9H C0MCONF05 CAN0 message configuration register 05 R/W x x Undefined 00001AAH C0MIDL05 CAN0 message identifier L register 05 R/W x Undefined 00001ACH C0MIDH05 CAN0 message identifier H register 05 R/W x Undefined 00001AEH C0MCTRL05 CAN0 message control register 05 R/W x Undefined 00001C0H C0MDATA0106 CAN0 message data byte 0 and 1 register 06 R/W x Undefined 00001C0H C0MDATA006 CAN0 message data byte 0 register 06 R/W x x Undefined 00001C1H C0MDATA106 CAN0 message data byte 1 register 06 R/W x x Undefined CAN0 message data byte 2 and 3 register 06 R/W 00001C2H C0MDATA206 CAN0 message data byte 2 register 06 R/W x x Undefined 00001C3H C0MDATA306 CAN0 message data byte 3 register 06 R/W x x Undefined CAN0 message data byte 4 and 5 register 06 R/W 00001C4H C0MDATA406 CAN0 message data byte 2 register 06 R/W x x Undefined 00001C5H C0MDATA506 CAN0 message data byte 3 register 06 R/W x x Undefined CAN0 message data byte 6 and 7 register 06 R/W 00001C6H C0MDATA606 CAN0 message data byte 6 register 06 R/W x x Undefined 00001C7H C0MDATA706 CAN0 message data byte 7 register 06 R/W x x Undefined 00001C2H 00001C4H 00001C6H 126 C0MDATA2306 C0MDATA4506 C0MDATA6706 User's Manual U16580EE3V1UD00 x x x Undefined Undefined Undefined Chapter 3 Table 3-6: CPU Functions Programmable Peripheral I/O Registers (5/16) Address Offset Symbol Function Register Name 00001C8H C0MDLC06 CAN0 message data length code register 06 00001C9H C0MCONF06 00001CAH R/W Bit Units for Manipulation 1 8 R/W x x Undefined CAN0 message configuration register 06 R/W x x Undefined C0MIDL06 CAN0 message identifier L register 06 R/W x Undefined 00001CCH C0MIDH06 CAN0 message identifier H register 06 R/W x Undefined 00001CEH C0MCTRL06 CAN0 message control register 06 R/W x Undefined 00001E0H C0MDATA0107 CAN0 message data byte 0 and 1 register 07 R/W x Undefined 00001E0H C0MDATA007 CAN0 message data byte 0 register 07 R/W x x Undefined 00001E1H C0MDATA107 CAN0 message data byte 1 register 07 R/W x x Undefined CAN0 message data byte 2 and 3 register 07 R/W 00001E2H C0MDATA207 CAN0 message data byte 2 register 07 R/W x x Undefined 00001E3H C0MDATA307 CAN0 message data byte 3 register 07 R/W x x Undefined CAN0 message data byte 4 and 5 register 07 R/W 00001E4H C0MDATA407 CAN0 message data byte 2 register 07 R/W x x Undefined 00001E5H C0MDATA507 CAN0 message data byte 3 register 07 R/W x x Undefined CAN0 message data byte 6 and 7 register 07 R/W 00001E6H C0MDATA607 CAN0 message data byte 6 register 07 R/W x x Undefined 00001E7H C0MDATA707 CAN0 message data byte 7 register 07 R/W x x Undefined 00001E2H 00001E4H 00001E6H C0MDATA2307 C0MDATA4507 C0MDATA6707 16 After Reset x x x Undefined Undefined Undefined 00001E8H C0MDLC07 CAN0 message data length code register 07 R/W x x Undefined 00001E9H C0MCONF07 CAN0 message configuration register 07 R/W x x Undefined 00001EAH C0MIDL07 CAN0 message identifier L register 07 R/W x Undefined 00001ECH C0MIDH07 CAN0 message identifier H register 07 R/W x Undefined 00001EEH C0MCTRL07 CAN0 message control register 07 R/W x Undefined 0000200H C0MDATA0108 CAN0 message data byte 0 and 1 register 08 R/W x Undefined 0000200H C0MDATA008 CAN0 message data byte 0 register 08 R/W x x Undefined 0000201H C0MDATA108 CAN0 message data byte 1 register 08 R/W x x Undefined C0MDATA2308 CAN0 message data byte 2 and 3 register 08 R/W 0000202H C0MDATA208 CAN0 message data byte 2 register 08 R/W x x Undefined 0000203H C0MDATA308 CAN0 message data byte 3 register 08 R/W x x Undefined C0MDATA4508 CAN0 message data byte 4 and 5 register 08 R/W 0000204H C0MDATA408 CAN0 message data byte 2 register 08 R/W x x Undefined 0000205H C0MDATA508 CAN0 message data byte 3 register 08 R/W x x Undefined C0MDATA6708 CAN0 message data byte 6 and 7 register 08 R/W 0000206H C0MDATA608 CAN0 message data byte 6 register 08 R/W x x Undefined 0000207H C0MDATA708 CAN0 message data byte 7 register 08 R/W x x Undefined 0000208H C0MDLC08 CAN0 message data length code register 08 R/W x x Undefined 0000209H C0MCONF08 CAN0 message configuration register 08 R/W x x Undefined 000020AH C0MIDL08 CAN0 message identifier L register 08 R/W x Undefined 000020CH C0MIDH08 CAN0 message identifier H register 08 R/W x Undefined 000020EH C0MCTRL08 CAN0 message control register 08 R/W x Undefined 0000202H 0000204H 0000206H User's Manual U16580EE3V1UD00 x x x Undefined Undefined Undefined 127 Chapter 3 Table 3-6: Address Offset 0000220H Symbol CPU Functions Programmable Peripheral I/O Registers (6/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C0MDATA0109 CAN0 message data byte 0 and 1 register 09 R/W 0000220H C0MDATA009 CAN0 message data byte 0 register 09 R/W x x Undefined 0000221H C0MDATA109 CAN0 message data byte 1 register 09 R/W x x Undefined C0MDATA2309 CAN0 message data byte 2 and 3 register 09 R/W 0000222H C0MDATA209 CAN0 message data byte 2 register 09 R/W x x Undefined 0000223H C0MDATA309 CAN0 message data byte 3 register 09 R/W x x Undefined C0MDATA4509 CAN0 message data byte 4 and 5 register 09 R/W 0000224H C0MDATA409 CAN0 message data byte 2 register 09 R/W x x Undefined 0000225H C0MDATA509 CAN0 message data byte 3 register 09 R/W x x Undefined C0MDATA6709 CAN0 message data byte 6 and 7 register 09 R/W 0000226H C0MDATA609 CAN0 message data byte 6 register 09 R/W x x Undefined 0000227H C0MDATA709 CAN0 message data byte 7 register 09 R/W x x Undefined 0000228H C0MDLC09 CAN0 message data length code register 09 R/W x x Undefined 0000229H C0MCONF09 CAN0 message configuration register 09 R/W x x Undefined 000022AH C0MIDL09 CAN0 message identifier L register 09 R/W x Undefined 000022CH C0MIDH09 CAN0 message identifier H register 09 R/W x Undefined 000022EH C0MCTRL09 CAN0 message control register 09 R/W x Undefined 0000240H C0MDATA0110 CAN0 message data byte 0 and 1 register 10 R/W x Undefined 0000240H C0MDATA010 CAN0 message data byte 0 register 10 R/W x x Undefined 0000241H C0MDATA110 CAN0 message data byte 1 register 10 R/W x x Undefined C0MDATA2310 CAN0 message data byte 2 and 3 register 10 R/W 0000242H C0MDATA210 CAN0 message data byte 2 register 10 R/W x x Undefined 0000243H C0MDATA310 CAN0 message data byte 3 register 10 R/W x x Undefined C0MDATA4510 CAN0 message data byte 4 and 5 register 10 R/W 0000244H C0MDATA410 CAN0 message data byte 2 register 10 R/W x x Undefined 0000245H C0MDATA510 CAN0 message data byte 3 register 10 R/W x x Undefined C0MDATA6710 CAN0 message data byte 6 and 7 register 10 R/W 0000246H C0MDATA610 CAN0 message data byte 6 register 10 R/W x x Undefined 0000247H C0MDATA710 CAN0 message data byte 7 register 10 R/W x x Undefined 0000248H C0MDLC10 CAN0 message data length code register 10 R/W x x Undefined 0000249H C0MCONF10 CAN0 message configuration register 10 R/W x x Undefined 000024AH C0MIDL10 CAN0 message identifier L register 10 R/W x Undefined 000024CH C0MIDH10 CAN0 message identifier H register 10 R/W x Undefined 000024EH C0MCTRL10 CAN0 message control register 10 R/W x Undefined 0000260H C0MDATA0111 CAN0 message data byte 0 and 1 register 11 R/W x Undefined 0000260H C0MDATA011 CAN0 message data byte 0 register 11 R/W x x Undefined 0000261H C0MDATA111 CAN0 message data byte 1 register 11 R/W x x Undefined C0MDATA2311 CAN0 message data byte 2 and 3 register 11 R/W 0000262H C0MDATA211 CAN0 message data byte 2 register 11 R/W x x Undefined 0000263H C0MDATA311 CAN0 message data byte 3 register 11 R/W x x Undefined 0000222H 0000224H 0000226H 0000242H 0000244H 0000246H 0000262H 128 User's Manual U16580EE3V1UD00 x x x x x x x Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Chapter 3 Table 3-6: Address Offset 0000264H Symbol CPU Functions Programmable Peripheral I/O Registers (7/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C0MDATA4511 CAN0 message data byte 4 and 5 register 11 R/W 0000264H C0MDATA411 CAN0 message data byte 2 register 11 R/W x x Undefined 0000265H C0MDATA511 CAN0 message data byte 3 register 11 R/W x x Undefined C0MDATA6711 CAN0 message data byte 6 and 7 register 11 R/W 0000266H C0MDATA611 CAN0 message data byte 6 register 11 R/W x x Undefined 0000267H C0MDATA711 CAN0 message data byte 7 register 11 R/W x x Undefined 0000268H C0MDLC11 CAN0 message data length code register 11 R/W x x Undefined 0000269H C0MCONF11 CAN0 message configuration register 11 R/W x x Undefined 000026AH C0MIDL11 CAN0 message identifier L register 11 R/W x Undefined 000026CH C0MIDH11 CAN0 message identifier H register 11 R/W x Undefined 000026EH C0MCTRL11 CAN0 message control register 11 R/W x Undefined 0000280H C0MDATA0112 CAN0 message data byte 0 and 1 register 12 R/W x Undefined 0000280H C0MDATA012 CAN0 message data byte 0 register 12 R/W x x Undefined 0000281H C0MDATA112 CAN0 message data byte 1 register 12 R/W x x Undefined C0MDATA2312 CAN0 message data byte 2 and 3 register 12 R/W 0000282H C0MDATA212 CAN0 message data byte 2 register 12 R/W x x Undefined 0000283H C0MDATA312 CAN0 message data byte 3 register 12 R/W x x Undefined C0MDATA4512 CAN0 message data byte 4 and 5 register 12 R/W 0000284H C0MDATA412 CAN0 message data byte 2 register 12 R/W x x Undefined 0000285H C0MDATA512 CAN0 message data byte 3 register 12 R/W x x Undefined C0MDATA6712 CAN0 message data byte 6 and 7 register 12 R/W 0000286H C0MDATA612 CAN0 message data byte 6 register 12 R/W x x Undefined 0000287H C0MDATA712 CAN0 message data byte 7 register 12 R/W x x Undefined 0000288H C0MDLC12 CAN0 message data length code register 12 R/W x x Undefined 0000289H C0MCONF12 CAN0 message configuration register 12 R/W x x Undefined 000028AH C0MIDL12 CAN0 message identifier L register 12 R/W x Undefined 000028CH C0MIDH12 CAN0 message identifier H register 12 R/W x Undefined 000028EH C0MCTRL12 CAN0 message control register 12 R/W x Undefined 00002A0H C0MDATA0113 CAN0 message data byte 0 and 1 register 13 R/W x Undefined 00002A0H C0MDATA013 CAN0 message data byte 0 register 13 R/W x x Undefined 00002A1H C0MDATA113 CAN0 message data byte 1 register 13 R/W x x Undefined CAN0 message data byte 2 and 3 register 13 R/W 00002A2H C0MDATA213 CAN0 message data byte 2 register 13 R/W x x Undefined 00002A3H C0MDATA313 CAN0 message data byte 3 register 13 R/W x x Undefined CAN0 message data byte 4 and 5 register 13 R/W 00002A4H C0MDATA413 CAN0 message data byte 2 register 13 R/W x x Undefined 00002A5H C0MDATA513 CAN0 message data byte 3 register 13 R/W x x Undefined CAN0 message data byte 6 and 7 register 13 R/W 00002A6H C0MDATA613 CAN0 message data byte 6 register 13 R/W x x Undefined 00002A7H C0MDATA713 CAN0 message data byte 7 register 13 R/W x x Undefined 0000266H 0000282H 0000284H 0000286H 00002A2H 00002A4H 00002A6H C0MDATA2313 C0MDATA4513 C0MDATA6713 User's Manual U16580EE3V1UD00 x x x x x x x Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 129 Chapter 3 Table 3-6: CPU Functions Programmable Peripheral I/O Registers (8/16) Address Offset Symbol Function Register Name 00002A8H C0MDLC13 CAN0 message data length code register 13 00002A9H C0MCONF13 00002AAH R/W Bit Units for Manipulation 1 8 R/W x x Undefined CAN0 message configuration register 13 R/W x x Undefined C0MIDL13 CAN0 message identifier L register 13 R/W x Undefined 00002ACH C0MIDH13 CAN0 message identifier H register 13 R/W x Undefined 00002AEH C0MCTRL13 CAN0 message control register 13 R/W x Undefined 00002C0H C0MDATA0114 CAN0 message data byte 0 and 1 register 14 R/W x Undefined 00002C0H C0MDATA014 CAN0 message data byte 0 register 14 R/W x x Undefined 00002C1H C0MDATA114 CAN0 message data byte 1 register 14 R/W x x Undefined CAN0 message data byte 2 and 3 register 14 R/W 00002C2H C0MDATA214 CAN0 message data byte 2 register 14 R/W x x Undefined 00002C3H C0MDATA314 CAN0 message data byte 3 register 14 R/W x x Undefined CAN0 message data byte 4 and 5 register 14 R/W 00002C4H C0MDATA414 CAN0 message data byte 2 register 14 R/W x x Undefined 00002C5H C0MDATA514 CAN0 message data byte 3 register 14 R/W x x Undefined CAN0 message data byte 6 and 7 register 14 R/W 00002C6H C0MDATA614 CAN0 message data byte 6 register 14 R/W x x Undefined 00002C7H C0MDATA714 CAN0 message data byte 7 register 14 R/W x x Undefined 00002C2H 00002C4H 00002C6H C0MDATA2314 C0MDATA4514 C0MDATA6714 16 After Reset x x x Undefined Undefined Undefined 00002C8H C0MDLC14 CAN0 message data length code register 14 R/W x x Undefined 00002C9H C0MCONF14 CAN0 message configuration register 14 R/W x x Undefined 00002CAH C0MIDL14 CAN0 message identifier L register 14 R/W x Undefined 00002CCH C0MIDH14 CAN0 message identifier H register 14 R/W x Undefined 00002CEH C0MCTRL14 CAN0 message control register 14 R/W x Undefined 00002E0H C0MDATA0115 CAN0 message data byte 0 and 1 register 15 R/W x Undefined 00002E0H C0MDATA015 CAN0 message data byte 0 register 15 R/W x x Undefined 00002E1H C0MDATA115 CAN0 message data byte 1 register 15 R/W x x Undefined CAN0 message data byte 2 and 3 register 15 R/W 00002E2H C0MDATA215 CAN0 message data byte 2 register 15 R/W x x Undefined 00002E3H C0MDATA315 CAN0 message data byte 3 register 15 R/W x x Undefined CAN0 message data byte 4 and 5 register 15 R/W 00002E4H C0MDATA415 CAN0 message data byte 2 register 15 R/W x x Undefined 00002E5H C0MDATA515 CAN0 message data byte 3 register 15 R/W x x Undefined CAN0 message data byte 6 and 7 register 15 R/W 00002E6H C0MDATA615 CAN0 message data byte 6 register 15 R/W x x Undefined 00002E7H C0MDATA715 CAN0 message data byte 7 register 15 R/W x x Undefined 00002E2H 00002E4H 00002E6H C0MDATA2315 C0MDATA4515 C0MDATA6715 x x x Undefined Undefined Undefined 00002E8H C0MDLC15 CAN0 message data length code register 15 R/W x x Undefined 00002E9H C0MCONF15 CAN0 message configuration register 15 R/W x x Undefined 00002EAH C0MIDL15 CAN0 message identifier L register 15 R/W x Undefined 00002ECH C0MIDH15 CAN0 message identifier H register 15 R/W x Undefined 00002EEH C0MCTRL15 CAN0 message control register 15 R/W x Undefined 130 User's Manual U16580EE3V1UD00 Chapter 3 Table 3-6: CPU Functions Programmable Peripheral I/O Registers (9/16) Address Offset Symbol 0000600H C1GMCTRL CAN1 global macro control register R/W 0000600H C1GMCTRLL CAN1 global macro control register L R/W x x 00H 0000601H C1GMCTRLH CAN1 global macro control register H R/W x x 00H 0000602H C1GMCS CAN1 global macro clock selection register R/W x x 00H 0000606H C1GMABT CAN1 global macro automatic block transmission register R/W 0000606H C1GMABTL CAN1 global macro automatic block transmission register L R/W x x 00H 0000607H C1GMABTH CAN1 global macro automatic block transmission register H R/W x x 00H 0000608H C1GMABTD CAN1 global macro automatic block transmission delay register R/W x x 00H 0000640H C1MASK1L CAN1 module mask 1 register L R/W x Undefined 0000642H C1MASK1H CAN1 module mask 1 register H R/W x Undefined 0000644H C1MASK2L CAN1 module mask 2 register L R/W x Undefined 0000646H C1MASK2H CAN1 module mask 2 register H R/W x Undefined 0000648H C1MASK3L CAN1 module mask 3 register L R/W x Undefined 000064AH C1MASK3H CAN1 module mask 3 register H R/W x Undefined 000064CH C1MASK4L CAN1 module mask 4 register L R/W x Undefined 000064EH C1MASK4H CAN1 module mask 4 register H R/W x Undefined 0000650H C1CTRL CAN1 module control register R/W x 0000H 0000652H C1LEC CAN1 module last error code register R/W x x 00H 0000653H C1INFO CAN1 module information register R x x 00H 0000654H C1ERC CAN1 module error counter R/W x 0000H 0000656H C1IE CAN1 module interrupt enable register R/W x 0000H 0000656H C1IEL CAN1 module interrupt enable register L R/W x x 00H 0000657H C1IEH CAN1 module interrupt enable register H R/W x x 00H C1INTS CAN1 module interrupt status register R/W C1INTSL CAN1 module interrupt status register L R/W x x 00H 000065AH C1BRP CAN1 module bit-rate prescaler register R/W x x FFH 000065CH C1BTR CAN1 bit-rate register R/W 000065EH C1LIPT CAN1 module last in-pointer register R/W 0000660H C1RGPT CAN1 module receive history list get pointer register R/W C1RGPTL CAN1 module receive history list get pointer register L R/W 0000662H C1LOPT CAN1 module last out-pointer register 0000664H C1TGPT CAN1 module transmit history list get pointer register R/W C1TGPTL CAN1 module transmit history list get pointer register L R/W 0000658H 0000658H 0000660H 0000664H Function Register Name R/W Bit Units for Manipulation 1 User's Manual U16580EE3V1UD00 8 16 x x x x x R 0000H 0000H 370FH Undefined x 01H x Undefined x x 0000H Undefined x x After Reset x Undefined 01H 131 Chapter 3 Table 3-6: Address Offset 0000666H Symbol CPU Functions Programmable Peripheral I/O Registers (10/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C1TS CAN1 module time stamp register R/W 0000666H C1TSL CAN1 module time stamp register L R/W x x 00H 0000667H C1TSH CAN1 module time stamp register H R/W x x 00H C1MDATA0100 CAN1 message data byte 0 and 1 register 00 R/W 0000700H C1MDATA000 CAN1 message data byte 0 register 00 R/W x x Undefined 0000701H C1MDATA100 CAN1 message data byte 1 register 00 R/W x x Undefined C1MDATA2300 CAN1 message data byte 2 and 3 register 00 R/W 0000702H C1MDATA200 CAN1 message data byte 2 register 00 R/W x x Undefined 0000703H C1MDATA300 CAN1 message data byte 3 register 00 R/W x x Undefined C1MDATA4500 CAN1 message data byte 4 and 5 register 00 R/W 0000704H C1MDATA400 CAN1 message data byte 2 register 00 R/W x x Undefined 0000705H C1MDATA500 CAN1 message data byte 3 register 00 R/W x x Undefined C1MDATA6700 CAN1 message data byte 6 and 7 register 00 R/W 0000706H C1MDATA600 CAN1 message data byte 6 register 00 R/W x x Undefined 0000707H C1MDATA700 CAN1 message data byte 7 register 00 R/W x x Undefined 0000708H C1MDLC00 CAN1 message data length code register 00 R/W x x Undefined 0000709H C1MCONF00 CAN1 message configuration register 00 R/W x x Undefined 000070AH C1MIDL00 CAN1 message identifier L register 00 R/W x Undefined 000070CH C1MIDH00 CAN1 message identifier H register 00 R/W x Undefined 000070EH C1MCTRL00 CAN1 message control register 00 R/W x Undefined 0000720H C1MDATA0101 CAN1 message data byte 0 and 1 register 01 R/W x Undefined 0000720H C1MDATA001 CAN1 message data byte 0 register 01 R/W x x Undefined 0000721H C1MDATA101 CAN1 message data byte 1 register 01 R/W x x Undefined C1MDATA2301 CAN1 message data byte 2 and 3 register 01 R/W 0000722H C1MDATA201 CAN1 message data byte 2 register 01 R/W x x Undefined 0000723H C1MDATA301 CAN1 message data byte 3 register 01 R/W x x Undefined C1MDATA4501 CAN1 message data byte 4 and 5 register 01 R/W 0000724H C1MDATA401 CAN1 message data byte 2 register 01 R/W x x Undefined 0000725H C1MDATA501 CAN1 message data byte 3 register 01 R/W x x Undefined C1MDATA6701 CAN1 message data byte 6 and 7 register 01 R/W 0000726H C1MDATA601 CAN1 message data byte 6 register 01 R/W x x Undefined 0000727H C1MDATA701 CAN1 message data byte 7 register 01 R/W x x Undefined 0000728H C1MDLC01 CAN1 message data length code register 01 R/W x x Undefined 0000729H C1MCONF01 CAN1 message configuration register 01 R/W x x Undefined 000072AH C1MIDL01 CAN1 message identifier L register 01 R/W x Undefined 000072CH C1MIDH01 CAN1 message identifier H register 01 R/W x Undefined 000072EH C1MCTRL01 CAN1 message control register 01 R/W x Undefined 0000740H C1MDATA0102 CAN1 message data byte 0 and 1 register 02 R/W x Undefined 0000740H C1MDATA002 CAN1 message data byte 0 register 02 R/W x x Undefined 0000741H C1MDATA102 CAN1 message data byte 1 register 02 R/W x x Undefined 0000700H 0000702H 0000704H 0000706H 0000722H 0000724H 0000726H 132 User's Manual U16580EE3V1UD00 x x x x x x x 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Chapter 3 Table 3-6: Address Offset 0000742H Symbol CPU Functions Programmable Peripheral I/O Registers (11/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C1MDATA2302 CAN1 message data byte 2 and 3 register 02 R/W 0000742H C1MDATA202 CAN1 message data byte 2 register 02 R/W x x Undefined 0000743H C1MDATA302 CAN1 message data byte 3 register 02 R/W x x Undefined C1MDATA4502 CAN1 message data byte 4 and 5 register 02 R/W 0000744H C1MDATA402 CAN1 message data byte 2 register 02 R/W x x Undefined 0000745H C1MDATA502 CAN1 message data byte 3 register 02 R/W x x Undefined C1MDATA6702 CAN1 message data byte 6 and 7 register 02 R/W 0000746H C1MDATA602 CAN1 message data byte 6 register 02 R/W x x Undefined 0000747H C1MDATA702 CAN1 message data byte 7 register 02 R/W x x Undefined 0000748H C1MDLC02 CAN1 message data length code register 02 R/W x x Undefined 0000749H C1MCONF02 CAN1 message configuration register 02 R/W x x Undefined 000074AH C1MIDL02 CAN1 message identifier L register 02 R/W x Undefined 000074CH C1MIDH02 CAN1 message identifier H register 02 R/W x Undefined 000074EH C1MCTRL02 CAN1 message control register 02 R/W x Undefined 0000760H C1MDATA0103 CAN1 message data byte 0 and 1 register 03 R/W x Undefined 0000760H C1MDATA003 CAN1 message data byte 0 register 03 R/W x x Undefined 0000761H C1MDATA103 CAN1 message data byte 1 register 03 R/W x x Undefined C1MDATA2303 CAN1 message data byte 2 and 3 register 03 R/W 0000762H C1MDATA203 CAN1 message data byte 2 register 03 R/W x x Undefined 0000763H C1MDATA303 CAN1 message data byte 3 register 03 R/W x x Undefined C1MDATA4503 CAN1 message data byte 4 and 5 register 03 R/W 0000764H C1MDATA403 CAN1 message data byte 2 register 03 R/W x x Undefined 0000765H C1MDATA503 CAN1 message data byte 3 register 03 R/W x x Undefined C1MDATA6703 CAN1 message data byte 6 and 7 register 03 R/W 0000766H C1MDATA603 CAN1 message data byte 6 register 03 R/W x x Undefined 0000767H C1MDATA703 CAN1 message data byte 7 register 03 R/W x x Undefined 0000768H C1MDLC03 CAN1 message data length code register 03 R/W x x Undefined 0000769H C1MCONF03 CAN1 message configuration register 03 R/W x x Undefined 000076AH C1MIDL03 CAN1 message identifier L register 03 R/W x Undefined 000076CH C1MIDH03 CAN1 message identifier H register 03 R/W x Undefined 000076EH C1MCTRL03 CAN1 message control register 03 R/W x Undefined 0000780H C1MDATA0104 CAN1 message data byte 0 and 1 register 04 R/W x Undefined 0000780H C1MDATA004 CAN1 message data byte 0 register 04 R/W x x Undefined 0000781H C1MDATA104 CAN1 message data byte 1 register 04 R/W x x Undefined C1MDATA2304 CAN1 message data byte 2 and 3 register 04 R/W 0000782H C1MDATA204 CAN1 message data byte 2 register 04 R/W x x Undefined 0000783H C1MDATA304 CAN1 message data byte 3 register 04 R/W x x Undefined C1MDATA4504 CAN1 message data byte 4 and 5 register 04 R/W 0000784H C1MDATA404 CAN1 message data byte 2 register 04 R/W x x Undefined 0000785H C1MDATA504 CAN1 message data byte 3 register 04 R/W x x Undefined 0000744H 0000746H 0000762H 0000764H 0000766H 0000782H 0000784H User's Manual U16580EE3V1UD00 x x x x x x x Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 133 Chapter 3 Table 3-6: Address Offset 0000786H Symbol CPU Functions Programmable Peripheral I/O Registers (12/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C1MDATA6704 CAN1 message data byte 6 and 7 register 04 R/W 0000786H C1MDATA604 CAN1 message data byte 6 register 04 R/W x x Undefined 0000787H C1MDATA704 CAN1 message data byte 7 register 04 R/W x x Undefined 0000788H C1MDLC04 CAN1 message data length code register 04 R/W x x Undefined 0000789H C1MCONF04 CAN1 message configuration register 04 R/W x x Undefined 000078AH C1MIDL04 CAN1 message identifier L register 04 R/W x Undefined 000078CH C1MIDH04 CAN1 message identifier H register 04 R/W x Undefined 000078EH C1MCTRL04 CAN1 message control register 04 R/W x Undefined 00007A0H C1MDATA0105 CAN1 message data byte 0 and 1 register 05 R/W x Undefined 00007A0H C1MDATA005 CAN1 message data byte 0 register 05 R/W x x Undefined 00007A1H C1MDATA105 CAN1 message data byte 1 register 05 R/W x x Undefined CAN1 message data byte 2 and 3 register 05 R/W 00007A2H C1MDATA205 CAN1 message data byte 2 register 05 R/W x x Undefined 00007A3H C1MDATA305 CAN1 message data byte 3 register 05 R/W x x Undefined CAN1 message data byte 4 and 5 register 05 R/W 00007A4H C1MDATA405 CAN1 message data byte 2 register 05 R/W x x Undefined 00007A5H C1MDATA505 CAN1 message data byte 3 register 05 R/W x x Undefined CAN1 message data byte 6 and 7 register 05 R/W 00007A6H C1MDATA605 CAN1 message data byte 6 register 05 R/W x x Undefined 00007A7H C1MDATA705 CAN1 message data byte 7 register 05 R/W x x Undefined 00007A2H 00007A4H 00007A6H C1MDATA2305 C1MDATA4505 C1MDATA6705 x x x Undefined Undefined Undefined Undefined 00007A8H C1MDLC05 CAN1 message data length code register 05 R/W x x Undefined 00007A9H C1MCONF05 CAN1 message configuration register 05 R/W x x Undefined 00007AAH C1MIDL05 CAN1 message identifier L register 05 R/W x Undefined 00007ACH C1MIDH05 CAN1 message identifier H register 05 R/W x Undefined 00007AEH C1MCTRL05 CAN1 message control register 05 R/W x Undefined 00007C0H C1MDATA0106 CAN1 message data byte 0 and 1 register 06 R/W x Undefined 00007C0H C1MDATA006 CAN1 message data byte 0 register 06 R/W x x Undefined 00007C1H C1MDATA106 CAN1 message data byte 1 register 06 R/W x x Undefined CAN1 message data byte 2 and 3 register 06 R/W 00007C2H C1MDATA206 CAN1 message data byte 2 register 06 R/W x x Undefined 00007C3H C1MDATA306 CAN1 message data byte 3 register 06 R/W x x Undefined CAN1 message data byte 4 and 5 register 06 R/W 00007C4H C1MDATA406 CAN1 message data byte 2 register 06 R/W x x Undefined 00007C5H C1MDATA506 CAN1 message data byte 3 register 06 R/W x x Undefined CAN1 message data byte 6 and 7 register 06 R/W 00007C6H C1MDATA606 CAN1 message data byte 6 register 06 R/W x x Undefined 00007C7H C1MDATA706 CAN1 message data byte 7 register 06 R/W x x Undefined 00007C2H 00007C4H 00007C6H C1MDATA2306 C1MDATA4506 C1MDATA6706 x x x Undefined Undefined Undefined 00007C8H C1MDLC06 CAN1 message data length code register 06 R/W x x Undefined 00007C9H C1MCONF06 CAN1 message configuration register 06 R/W x x Undefined 00007CAH C1MIDL06 CAN1 message identifier L register 06 R/W 134 User's Manual U16580EE3V1UD00 x Undefined Chapter 3 Table 3-6: Address Offset Symbol CPU Functions Programmable Peripheral I/O Registers (13/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 After Reset 00007CCH C1MIDH06 CAN1 message identifier H register 06 R/W x Undefined 00007CEH C1MCTRL06 CAN1 message control register 06 R/W x Undefined 00007E0H C1MDATA0107 CAN1 message data byte 0 and 1 register 07 R/W x Undefined 00007E0H C1MDATA007 CAN1 message data byte 0 register 07 R/W x x Undefined 00007E1H C1MDATA107 CAN1 message data byte 1 register 07 R/W x x Undefined CAN1 message data byte 2 and 3 register 07 R/W 00007E2H C1MDATA207 CAN1 message data byte 2 register 07 R/W x x Undefined 00007E3H C1MDATA307 CAN1 message data byte 3 register 07 R/W x x Undefined CAN1 message data byte 4 and 5 register 07 R/W 00007E4H C1MDATA407 CAN1 message data byte 2 register 07 R/W x x Undefined 00007E5H C1MDATA507 CAN1 message data byte 3 register 07 R/W x x Undefined CAN1 message data byte 6 and 7 register 07 R/W 00007E6H C1MDATA607 CAN1 message data byte 6 register 07 R/W x x Undefined 00007E7H C1MDATA707 CAN1 message data byte 7 register 07 R/W x x Undefined 00007E2H 00007E4H 00007E6H C1MDATA2307 C1MDATA4507 C1MDATA6707 x x x Undefined Undefined Undefined 00007E8H C1MDLC07 CAN1 message data length code register 07 R/W x x Undefined 00007E9H C1MCONF07 CAN1 message configuration register 07 R/W x x Undefined 00007EAH C1MIDL07 CAN1 message identifier L register 07 R/W x Undefined 00007ECH C1MIDH07 CAN1 message identifier H register 07 R/W x Undefined 00007EEH C1MCTRL07 CAN1 message control register 07 R/W x Undefined 0000800H C1MDATA0108 CAN1 message data byte 0 and 1 register 08 R/W x Undefined 0000800H C1MDATA008 CAN1 message data byte 0 register 08 R/W x x Undefined 0000801H C1MDATA108 CAN1 message data byte 1 register 08 R/W x x Undefined C1MDATA2308 CAN1 message data byte 2 and 3 register 08 R/W 0000802H C1MDATA208 CAN1 message data byte 2 register 08 R/W x x Undefined 0000803H C1MDATA308 CAN1 message data byte 3 register 08 R/W x x Undefined C1MDATA4508 CAN1 message data byte 4 and 5 register 08 R/W 0000804H C1MDATA408 CAN1 message data byte 2 register 08 R/W x x Undefined 0000805H C1MDATA508 CAN1 message data byte 3 register 08 R/W x x Undefined C1MDATA6708 CAN1 message data byte 6 and 7 register 08 R/W 0000806H C1MDATA608 CAN1 message data byte 6 register 08 R/W x x Undefined 0000807H C1MDATA708 CAN1 message data byte 7 register 08 R/W x x Undefined 0000808H C1MDLC08 CAN1 message data length code register 08 R/W x x Undefined 0000809H C1MCONF08 CAN1 message configuration register 08 R/W x x Undefined 000080AH C1MIDL08 CAN1 message identifier L register 08 R/W x Undefined 000080CH C1MIDH08 CAN1 message identifier H register 08 R/W x Undefined 000080EH C1MCTRL08 CAN1 message control register 08 R/W x Undefined 0000820H C1MDATA0109 CAN1 message data byte 0 and 1 register 09 R/W x Undefined 0000820H C1MDATA009 CAN1 message data byte 0 register 09 R/W x x Undefined 0000821H C1MDATA109 CAN1 message data byte 1 register 09 R/W x x Undefined 0000802H 0000804H 0000806H User's Manual U16580EE3V1UD00 x x x Undefined Undefined Undefined 135 Chapter 3 Table 3-6: Address Offset 0000822H Symbol CPU Functions Programmable Peripheral I/O Registers (14/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C1MDATA2309 CAN1 message data byte 2 and 3 register 09 R/W 0000822H C1MDATA209 CAN1 message data byte 2 register 09 R/W x x Undefined 0000823H C1MDATA309 CAN1 message data byte 3 register 09 R/W x x Undefined C1MDATA4509 CAN1 message data byte 4 and 5 register 09 R/W 0000824H C1MDATA409 CAN1 message data byte 2 register 09 R/W x x Undefined 0000825H C1MDATA509 CAN1 message data byte 3 register 09 R/W x x Undefined C1MDATA6709 CAN1 message data byte 6 and 7 register 09 R/W 0000826H C1MDATA609 CAN1 message data byte 6 register 09 R/W x x Undefined 0000827H C1MDATA709 CAN1 message data byte 7 register 09 R/W x x Undefined 0000828H C1MDLC09 CAN1 message data length code register 09 R/W x x Undefined 0000829H C1MCONF09 CAN1 message configuration register 09 R/W x x Undefined 000082AH C1MIDL09 CAN1 message identifier L register 09 R/W x Undefined 000082CH C1MIDH09 CAN1 message identifier H register 09 R/W x Undefined 000082EH C1MCTRL09 CAN1 message control register 09 R/W x Undefined 0000840H C1MDATA0110 CAN1 message data byte 0 and 1 register 10 R/W x Undefined 0000840H C1MDATA010 CAN1 message data byte 0 register 10 R/W x x Undefined 0000841H C1MDATA110 CAN1 message data byte 1 register 10 R/W x x Undefined C1MDATA2310 CAN1 message data byte 2 and 3 register 10 R/W 0000842H C1MDATA210 CAN1 message data byte 2 register 10 R/W x x Undefined 0000843H C1MDATA310 CAN1 message data byte 3 register 10 R/W x x Undefined C1MDATA4510 CAN1 message data byte 4 and 5 register 10 R/W 0000844H C1MDATA410 CAN1 message data byte 2 register 10 R/W x x Undefined 0000845H C1MDATA510 CAN1 message data byte 3 register 10 R/W x x Undefined C1MDATA6710 CAN1 message data byte 6 and 7 register 10 R/W 0000846H C1MDATA610 CAN1 message data byte 6 register 10 R/W x x Undefined 0000847H C1MDATA710 CAN1 message data byte 7 register 10 R/W x x Undefined 0000848H C1MDLC10 CAN1 message data length code register 10 R/W x x Undefined 0000849H C1MCONF10 CAN1 message configuration register 10 R/W x x Undefined 000084AH C1MIDL10 CAN1 message identifier L register 10 R/W x Undefined 000084CH C1MIDH10 CAN1 message identifier H register 10 R/W x Undefined 000084EH C1MCTRL10 CAN1 message control register 10 R/W x Undefined 0000860H C1MDATA0111 CAN1 message data byte 0 and 1 register 11 R/W x Undefined 0000860H C1MDATA011 CAN1 message data byte 0 register 11 R/W x x Undefined 0000861H C1MDATA111 CAN1 message data byte 1 register 11 R/W x x Undefined C1MDATA2311 CAN1 message data byte 2 and 3 register 11 R/W 0000862H C1MDATA211 CAN1 message data byte 2 register 11 R/W x x Undefined 0000863H C1MDATA311 CAN1 message data byte 3 register 11 R/W x x Undefined C1MDATA4511 CAN1 message data byte 4 and 5 register 11 R/W 0000864H C1MDATA411 CAN1 message data byte 2 register 11 R/W x x Undefined 0000865H C1MDATA511 CAN1 message data byte 3 register 11 R/W x x Undefined 0000824H 0000826H 0000842H 0000844H 0000846H 0000862H 0000864H 136 User's Manual U16580EE3V1UD00 x x x x x x x Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Chapter 3 Table 3-6: Address Offset 0000866H Symbol CPU Functions Programmable Peripheral I/O Registers (15/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 x After Reset C1MDATA6711 CAN1 message data byte 6 and 7 register 11 R/W 0000866H C1MDATA611 CAN1 message data byte 6 register 11 R/W x x Undefined 0000867H C1MDATA711 CAN1 message data byte 7 register 11 R/W x x Undefined 0000868H C1MDLC11 CAN1 message data length code register 11 R/W x x Undefined 0000869H C1MCONF11 CAN1 message configuration register 11 R/W x x Undefined 000086AH C1MIDL11 CAN1 message identifier L register 11 R/W x Undefined 000086CH C1MIDH11 CAN1 message identifier H register 11 R/W x Undefined 000086EH C1MCTRL11 CAN1 message control register 11 R/W x Undefined 0000880H C1MDATA0112 CAN1 message data byte 0 and 1 register 12 R/W x Undefined 0000880H C1MDATA012 CAN1 message data byte 0 register 12 R/W x x Undefined 0000881H C1MDATA112 CAN1 message data byte 1 register 12 R/W x x Undefined C1MDATA2312 CAN1 message data byte 2 and 3 register 12 R/W 0000882H C1MDATA212 CAN1 message data byte 2 register 12 R/W x x Undefined 0000883H C1MDATA312 CAN1 message data byte 3 register 12 R/W x x Undefined C1MDATA4512 CAN1 message data byte 4 and 5 register 12 R/W 0000884H C1MDATA412 CAN1 message data byte 2 register 12 R/W x x Undefined 0000885H C1MDATA512 CAN1 message data byte 3 register 12 R/W x x Undefined C1MDATA6712 CAN1 message data byte 6 and 7 register 12 R/W 0000886H C1MDATA612 CAN1 message data byte 6 register 12 R/W x x Undefined 0000887H C1MDATA712 CAN1 message data byte 7 register 12 R/W x x Undefined 0000888H C1MDLC12 CAN1 message data length code register 12 R/W x x Undefined 0000889H C1MCONF12 CAN1 message configuration register 12 R/W x x Undefined 000088AH C1MIDL12 CAN1 message identifier L register 12 R/W x Undefined 000088CH C1MIDH12 CAN1 message identifier H register 12 R/W x Undefined 000088EH C1MCTRL12 CAN1 message control register 12 R/W x Undefined 00008A0H C1MDATA0113 CAN1 message data byte 0 and 1 register 13 R/W x Undefined 00008A0H C1MDATA013 CAN1 message data byte 0 register 13 R/W x x Undefined 00008A1H C1MDATA113 CAN1 message data byte 1 register 13 R/W x x Undefined CAN1 message data byte 2 and 3 register 13 R/W 00008A2H C1MDATA213 CAN1 message data byte 2 register 13 R/W x x Undefined 00008A3H C1MDATA313 CAN1 message data byte 3 register 13 R/W x x Undefined CAN1 message data byte 4 and 5 register 13 R/W 00008A4H C1MDATA413 CAN1 message data byte 2 register 13 R/W x x Undefined 00008A5H C1MDATA513 CAN1 message data byte 3 register 13 R/W x x Undefined CAN1 message data byte 6 and 7 register 13 R/W 00008A6H C1MDATA613 CAN1 message data byte 6 register 13 R/W x x Undefined 00008A7H C1MDATA713 CAN1 message data byte 7 register 13 R/W x x Undefined 0000882H 0000884H 0000886H 00008A2H 00008A4H 00008A6H C1MDATA2313 C1MDATA4513 C1MDATA6713 x x x x x x Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00008A8H C1MDLC13 CAN1 message data length code register 13 R/W x x Undefined 00008A9H C1MCONF13 CAN1 message configuration register 13 R/W x x Undefined 00008AAH C1MIDL13 CAN1 message identifier L register 13 R/W User's Manual U16580EE3V1UD00 x Undefined 137 Chapter 3 Table 3-6: Address Offset Symbol CPU Functions Programmable Peripheral I/O Registers (16/16) Function Register Name R/W Bit Units for Manipulation 1 8 16 After Reset 00008ACH C1MIDH13 CAN1 message identifier H register 13 R/W x Undefined 00008AEH C1MCTRL13 CAN1 message control register 13 R/W x Undefined 00008C0H C1MDATA0114 CAN1 message data byte 0 and 1 register 14 R/W x Undefined 00008C0H C1MDATA014 CAN1 message data byte 0 register 14 R/W x x Undefined 00008C1H C1MDATA114 CAN1 message data byte 1 register 14 R/W x x Undefined CAN1 message data byte 2 and 3 register 14 R/W 00008C2H C1MDATA214 CAN1 message data byte 2 register 14 R/W x x Undefined 00008C3H C1MDATA314 CAN1 message data byte 3 register 14 R/W x x Undefined CAN1 message data byte 4 and 5 register 14 R/W 00008C4H C1MDATA414 CAN1 message data byte 2 register 14 R/W x x Undefined 00008C5H C1MDATA514 CAN1 message data byte 3 register 14 R/W x x Undefined CAN1 message data byte 6 and 7 register 14 R/W 00008C6H C1MDATA614 CAN1 message data byte 6 register 14 R/W x x Undefined 00008C7H C1MDATA714 CAN1 message data byte 7 register 14 R/W x x Undefined 00008C2H 00008C4H 00008C6H C1MDATA2314 C1MDATA4514 C1MDATA6714 x x x Undefined Undefined Undefined 00008C8H C1MDLC14 CAN1 message data length code register 14 R/W x x Undefined 00008C9H C1MCONF14 CAN1 message configuration register 14 R/W x x Undefined 00008CAH C1MIDL14 CAN1 message identifier L register 14 R/W x Undefined 00008CCH C1MIDH14 CAN1 message identifier H register 14 R/W x Undefined 00008CEH C1MCTRL14 CAN1 message control register 14 R/W x Undefined 00008E0H C1MDATA0115 CAN1 message data byte 0 and 1 register 15 R/W x Undefined 00008E0H C1MDATA015 CAN1 message data byte 0 register 15 R/W x x Undefined 00008E1H C1MDATA115 CAN1 message data byte 1 register 15 R/W x x Undefined CAN1 message data byte 2 and 3 register 15 R/W 00008E2H C1MDATA215 CAN1 message data byte 2 register 15 R/W x x Undefined 00008E3H C1MDATA315 CAN1 message data byte 3 register 15 R/W x x Undefined CAN1 message data byte 4 and 5 register 15 R/W 00008E4H C1MDATA415 CAN1 message data byte 2 register 15 R/W x x Undefined 00008E5H C1MDATA515 CAN1 message data byte 3 register 15 R/W x x Undefined CAN1 message data byte 6 and 7 register 15 R/W 00008E6H C1MDATA615 CAN1 message data byte 6 register 15 R/W x x Undefined 00008E7H C1MDATA715 CAN1 message data byte 7 register 15 R/W x x Undefined 00008E2H 00008E4H 00008E6H C1MDATA2315 C1MDATA4515 C1MDATA6715 x x x Undefined Undefined Undefined 00008E8H C1MDLC15 CAN1 message data length code register 15 R/W x x Undefined 00008E9H C1MCONF15 CAN1 message configuration register 15 R/W x x Undefined 00008EAH C1MIDL15 CAN1 message identifier L register 15 R/W x Undefined 00008ECH C1MIDH15 CAN1 message identifier H register 15 R/W x Undefined 00008EEH C1MCTRL15 CAN1 message control register 15 R/W x Undefined Remark: 138 C1xxxx registers are not available for the PD70F3347. User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.4.8 Specific registers Specific registers are registers that prevent invalid data from being written if an inadvertent program behaviour occurs. The V850E/PH2 has the following specific registers: * Port registers 5 and 6 (P5, P6) * Port mode registers 5 and 6 (PM5, PM6) * Port mode control registers 5 and 6 (PMC5, PMC6) * Port emergency shut off control registers 5 and 6 (PESC5, PESC6) * Port emergency shut off status registers 5 and 6 (ESOST5, ESOST6) Moreover, there is also a command register (PRCMD), which is a protection register against write operations to the specific registers. Write access to the specific registers is performed with a special sequence and illegal store operations are notified to the system status register (PHS). This section of the manual describes the access method to these specific registers, rather than the values that can be written to these registers. For details on these register values, please refer to sections 20.3.6 "Port 5" on page 913 and 20.3.7 "Port 6" on page 918. (1) Setting data to specific registers Setting data to a specific registers is done in the following sequence. <1> <2> <3> Prepare the data to be set to the special register in a general-purpose register. Write the data prepared in <1> to the command register (PRCMD). Write the data to the specific register (using the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) Example <1> MOV 0x02, r10 <2> ST.B r10, PRCMD[r0] <3> ST.B r10, P5 (next instruction) ; Prepare data in r10 ; Write PRCMD register ; Set P5 register Cautions: 1. Interrupts are not acknowledged when executing the store instruction to the PRCMD register. If another instruction is placed between steps <2> and <3>, the correct sequence may not be realized if an interrupt is acknowledged for that instruction, resulting in the writing to the protected register to be not done, and an error to be stored in the PRERR bit of the PHS register. 2. If there is a possibility of an active DMA register before <2> and <3>, the specific register may not be written. In this case, ensure that no DMA register is active during the sequence <2> to <3>, or repeat the sequencer <2> to <3> as long as the PRERR bit of the PHS register is set to <1>. User's Manual U16580EE3V1UD00 139 Chapter 3 (2) CPU Functions Processor command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop. Only the first write operation to a specific register following the execution of a write operation to the PRCMD register, is valid. As a result, register values can be overwritten only using a preset sequence, preventing invalid write operations. PRCMD register must be written with store instruction execution by CPU only (not with DMA transfer). If an illegal store operation to a command or specific register takes place, it is reported by the PRERR flag of the system status register (PHS). This register can be written in 8-bit units only. Undefined data is read from this register. Figure 3-25: After reset: PRCMD 140 Undefined Processor Command Register (PRCMD) W Address: FFFFF1FCH 7 6 5 4 3 2 1 0 REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 User's Manual U16580EE3V1UD00 Chapter 3 (3) CPU Functions System status register (PHS) The PHS register is an 8-bit register to which the PRERR flag showing the generation of protection errors is assigned. If a write operation to a specific register has not been executed in the correct sequence including the access to the command register (PRCMD), the write operation to the intended register is not executed, a protection error is generated and the PRERR flag is set to 1. The value of this register becomes "00H" by RESET input. This register can be read/written in 8-bit and 1-bit units. Figure 3-26: After reset: PHS 00H System Status Register Format PHS R/W Address: FFFFF802H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PRERR PRERR Detection of Protection Error 0 Protection error did not occur 1 Protection error occurred The PRERR flag operates under the following conditions. (a) Setting condition (PRERR flag = 1) * When a write operation is not performed on the PRCMD register and an operation to write a specific register is performed (when <4> in the example 3.4.8 (1) Setting data to specific registers is executed without <3>). * If a write operation (including a bit manipulation instruction) is performed on an on-chip peripheral I/O register other than a specific register after a write operation to the PRCMD register (when <4> in the example 3.4.8 (1) Setting data to specific registers is not performed for a specific register). Remark: Even if an on-chip peripheral I/O register is read (including a bit manipulation instruction) between writing the PRCMD register and writing a specific register (such as an access to the internal RAM), the PRERR flag is not set, and data can be written to the special register. (b) Clearing condition (PREER flag = 0) * When 0 is written to the PRERR flag of the PHS register. * When system reset is executed. Cautions: 1. If 0 is written to the PRERR bit of the PHS register (that is not a specific register) immediately following write to the PRCMD register, the PRERR bit becomes 0 (write priority). 2. If data is written to the PRCMD register (that is not a specific registers) immediately following write to the PRCMD register, the PRERR bit becomes 1. User's Manual U16580EE3V1UD00 141 Chapter 3 CPU Functions 3.4.9 System wait control register (VSWC) The system wait control register (VSWC) is a register that controls the bus access wait for the on-chip peripheral I/O registers. Access to on-chip peripheral I/O registers is made in 3 clocks (without wait), however, in the V850E/PH2 waits may be required depending on the operation frequency. Set the values described in the table below to the VSWC register in accordance with the operation frequency used. This register can be read or written in 1-bit or 8-bit units. Register Name Operating frequency VSWC 64 MHz Set Value Address After reset 13H FFFFF06EH 77H 3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1) The DMA wait control registers 0 and 1 (DMAWC0, DMAWC1) are a registers that control the bus access wait and signal timing for DMA transfers. Set the values described in the table below to the DMAWC0 and DMAWC1 registers in accordance with the operation frequency used. This register can be read or written in 1-bit or 8-bit units. Register Name Operating frequency DMAWC0 DMAWC1 142 64 MHz Set Value Address After reset 13H FFFFFE00H 37H 04H FFFFFE02H 07H User's Manual U16580EE3V1UD00 Chapter 3 CPU Functions 3.4.11 Cautions * Initialize the following registers immediately after reset signal release in the following sequence: - System wait control register (VSWC) (refer to 3.4.9 System wait control register (VSWC)) - DMA wait control registers 0 and 1 (DMAWC0,DMAWC1) (refer to 3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1)) User's Manual U16580EE3V1UD00 143 Chapter 3 CPU Functions [MEMO] 144 User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) The PD70F3187 is provided with an external bus interface function by which external memories, such as ROM and RAM, and external I/O can be connected. The PD70F3447 is not equipped external bus interface function. 4.1 Features * 32-bit/16-bit/8-bit data bus sizing function * 8 chip areas select function * 4 chip area select signals externally available (CS0, CS1, CS3 and CS4) * Wait function - Programmable wait function, capable of inserting up to 7 wait states for each memory block - External wait function via WAIT pin * Idle state insertion function * External device connection can be enabled via bus control/port alternate function pins * Programmable Endian format (Little Endian/Big Endian) 4.2 Bus Control Pins The following pins are used for connecting to external devices. Bus Control Pin (Function when in Control Mode) Function when in Port Mode Register for Port/ Control Mode SwitchingNote Data bus (D0 to D15) PDL0 to PDL15 (Port DL) PMCDL Data bus (D16 to D31) PDH0 to PDH15 (Port DH) PMCDH Address bus (A0 to A15) PAL0 to PAL15 (Port AL) PMCAL Address bus (A16 to A21) PAH0 to PAH5 (Port AH) PMCAH Chip select (CS0, CS1, CS3 and CS4) PCS0, PCS1, PCS3 and PCS4 (Port CS) PMCCS Read/write control (RD,WR) PCT4, PCT5 (Port CT) PMCCT Byte enable control (BE0 to BE3) PCD2 to PCD5 (Port CD) PMCCD External wait control (WAIT) PCM0 (Port CM) PMCCM Note: Even if the port mode control registers for the PD70F3447 exist, it is prohibited to write other values to these registers than the reset values. User's Manual U16580EE3V1UD00 145 Chapter 4 Bus Control Function (PD70F3187 only) 4.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB units. Figure 4-1: 3FFFFFFH CS7, CS5, CS6, CS4 3E00000H 3DFFFFFH 3C00000H 3BFFFFFH 3A00000H 39FFFFFH 3800000H 37FFFFFH Block 15 (2 Mbytes) Block 14 (2 Mbytes) Block 13 (2 Mbytes) Block 12 (2 Mbytes) Memory Block Function 3FFFFFFH Internal peripheral I/O area (4 Kbytes) 3FFF000H 3FF7FFFH Internal RAM area (32 Kbytes) 3FF0000H Block 11 (4 Mbytes) CS6, CS4 3400000H 33FFFFFH Block 10 (4 Mbytes) 3000000H 2FFFFFFH Block 9 (8 Mbytes) CS4 2800000H 27FFFFFH Block 8 (8 Mbytes) 2000000H 1FFFFFFH External memory area Block 7 (8 Mbytes) CS3 1800000H 17FFFFFH Block 6 (8 Mbytes) 1000000H 0FFFFFFH CS1, CS3 Block 5 (4 Mbytes) 0C00000H 0BFFFFFH Block 4 (4 Mbytes) CS0, CS2, CS1, CS3 146 0800000H 07FFFFFH 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 3 (2 Mbytes) Block 2 (2 Mbytes) Block 1 (2 Mbytes) Block 0 (2 Mbytes) User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) 4.3.1 Chip select control function The 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals. The memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function. The priority order is described below. (1) Chip area selection control registers 0, 1 (CSC0, CSC1) These registers can be read/written in 16-bit units. Valid by setting each bit (to 1). If different chip area select signals are set to the same block, the priority order is controlled as follows. CSC0: Peripheral I/O area > CS0 > CS2 > CS1 > CS3 Note CSC1: Peripheral I/O area > CS7 > CS5 > CS6 > CS4 Note Note: Not all the chip area select signals are externally available on output pins. Even so, enabling chip area select signals other than CS0, CS1, CS3 or CS4, the setting for the corresponding memory blocks will be effective too, regardless of an external chip select output pin. Figure 4-2: After reset: 15 CSC0 2C11H 14 13 Chip Area Select Control Registers 0, 1 (1/2) R/W 12 11 10 9 8 FFFFF060H 7 6 5 4 3 2 1 0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 CS3 After reset: 15 CSC1 Address: CS2 2C11H 14 13 R/W 12 11 CS1 Address: 10 9 8 CS0 FFFFF062H 7 6 5 4 3 2 1 0 CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60 CS73 CS72 CS71 CS70 CS4 CS5 CS6 User's Manual U16580EE3V1UD00 CS7 147 Chapter 4 Figure 4-2: CSnm Chip Area Select Control Registers 0, 1 (2/2) Chip Select Operation CS00 CS0 active during block 0 access CS01 CS0 active during block 1 access. CS02 CS0 active during block 2 access. CS03 CS0 active during block 3 access. CS10 CS1 active during block 0 or 1 access. CS11 CS1 active during block 2 or 3 access. CS12 CS1 active during block 4 access. CS13 CS1 active during block 5 access. CS20 CS2 active during block 0 access. CS21 CS2 active during block 1 access. CS22 CS2 active during block 2 access. CS23 CS2 active during block 3 access. CS30 CS3 active during block 0, 1, 2, or 3 access. CS31 CS3 active during block 4 or 5 access. CS32 CS3 active during block 6 access. CS33 CS3 active during block 7 access. CS40 CS4 active during block 12, 13, 14, or 15 access. CS41 CS4 active during block 10 or 11 access. CS42 CS4 active during block 9 access. CS43 CS4 active during block 8 access. CS50 CS5 active during block 15 access. CS51 CS5 active during block 14 access. CS52 CS5 active during block 13 access. CS53 CS5 active during block 12 access. CS60 CS6 active during block 14 or 15 access. CS61 CS6 active during block 12 or 13 access. CS62 CS6 active during block 11 access. CS63 CS6 active during block 10 access. CS70 CS7 active during block 15 access. CS71 CS7 active during block 14 access. CS72 CS7 active during block 13 access. CS73 CS7 active during block 12 access. Remark: 148 Bus Control Function (PD70F3187 only) Dedicated chip select operation is enabled when corresponding CSnm bit is set (1), and disabled when CSnm is cleared (0) (n = 0 to 7, m = 0 to 3) User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) 4.4 Bus Cycle Type Control Function In the V850E/PH2, the following external devices can be connected directly to each memory block. * SRAM, external ROM, external I/O Connected external devices are specified by the bus cycle type configuration registers 0, 1 (BCT0, BCT1). User's Manual U16580EE3V1UD00 149 Chapter 4 Bus Control Function (PD70F3187 only) 4.4.1 Bus cycle type configuration (1) Bus cycle configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units Cautions: 1. Write to the BCT0 and BCT1 registers after reset, and then do not change the set value. Also, do not access an external memory area other than that for this initialization routine until initial setting of the BCT0 and BCT1 registers is finished. However, it is possible to access external memory areas whose initialization has been finished. 2. The bits marked as 0 and 1 are reserved. The values of these bits must not be changed. Otherwise the operation of the external bus interface cannot be ensured. Figure 4-3: After reset: BCT0 Bus Cycle Configuration Registers 0, 1 (BCT0, BCT1) CCCCH R/W Address: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ME3 1 0 0 ME2 1 0 0 ME1 1 0 0 ME0 1 0 0 CS2 CS3 After reset: BCT1 CCCCH R/W CS1 Address: CS0 FFFFF482H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ME7 1 0 0 ME6 1 0 0 ME5 1 0 0 ME4 1 0 0 CS6 CS7 MEn 150 FFFFF480H 15 CS5 Memory Controller Operation Enable for CSn Area 0 Operation disable 1 Operation enable User's Manual U16580EE3V1UD00 CS4 Chapter 4 Bus Control Function (PD70F3187 only) 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 4-1: Resources (Bus width) Bus Cycle Configuration Instruction fetch Normal access Branch Operand data access Number of Bus Access Clocks Internal RAM (32 bits) Peripheral I/O (16 bits) External memory (16 bits) 1Note 1 - 2Note 2 1 - 2Note 2 1 3Note 2 2Note 2 Notes: 1. The instruction fetch becomes 2 clocks, in case of contention with data access. 2. This is the minimum value. User's Manual U16580EE3V1UD00 151 Chapter 4 Bus Control Function (PD70F3187 only) 4.5.2 Bus sizing function The bus sizing function controls data bus width for each CS area. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units. Caution: Write to the BSC register after reset, and then do not change the set value. Also, do not access an external memory area other than that for this initialization routine until initial setting of the BSC register is finished. However, it is possible to access external memory areas whose initialization has been finished. Figure 4-4: After reset: AAAAH 15 BSC 152 14 Bus Size Configuration Register (BSC) R/W 13 12 11 Address: 10 9 FFFFF066H 8 7 6 5 4 3 2 1 0 BS71 BS70 BS61 BS60 BS51 BS50 BS41 BS40 BS31 BS30 BS21 BS20 BS11 BS10 BS01 BS00 CS7 CS6 CS5 CS4 BEn1 BEn0 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 Setting prohibited CS3 CS2 Data Bus Width of CSn Area User's Manual U16580EE3V1UD00 CS1 CS0 Chapter 4 Bus Control Function (PD70F3187 only) 4.5.3 Endian control function The Endian control function can be used to set processing of word data in memory either by the Big Endian method or the Little Endian method for each CS area selected with the chip select signal (CS0 to CS7). Switching of the Endian method is specified with the Endian configuration register (BEC). Figure 4-5: 31 Big Endian Addresses within Word 24 23 16 17 8 7 0 0008H 0009H 000AH 000BH 0004H 0005H 0006H 0007H 0000H 0001H 0002H 0003H Figure 4-6: 31 Little Endian Addresses within Word 24 23 16 17 8 7 0 000BH 000AH 0009H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H User's Manual U16580EE3V1UD00 153 Chapter 4 (1) Bus Control Function (PD70F3187 only) Endian configuration register (BEC) This register can be read/written in 16-bit units. Cautions: 1. Bits 15, 13, 11, 9, 7, 5, 3, and 1 of the BEC register must be cleared (0). If these bits are set to 1, the operation is not guaranteed. 2. Set the CSn area specified as the programmable peripheral I/O area to Little Endian format (n = 0 to 7). 3. In the following areas, the data processing method is fixed to Little Endian method. Any setting of Big Endian method for these areas according to the BEC register is invalid. - On-chip peripheral I/O area - Internal RAM area - Fetch area of external memory Figure 4-7: After reset: BEC 0000H Endian Configuration Register (BEC) R/W Address: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BE70 0 BE60 0 BE50 0 BE40 0 BE30 0 BE20 0 BE10 0 BE00 CS7 CS6 CS5 BEn0 154 FFFFF068H 15 CS4 CS3 CS2 Endian Control 0 Little Endian method 1 Big Endian method User's Manual U16580EE3V1UD00 CS1 CS0 Chapter 4 Bus Control Function (PD70F3187 only) 4.5.4 Bus width The V850E/PH2 accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower order side. (1) Byte access (8 bits) (a) When the data bus width is 32 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address <3> Access to address (4n+2) Address <4> Access to address (4n+3) Address Address 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 7 8 7 7 8 7 7 8 7 7 8 7 0 0 0 0 0 0 0 0 Byte data External data bus Byte data External data bus Byte data External data bus Byte data External data bus 4n + 3 4n + 2 16 15 4n + 1 4n (b) When the data bus width is 16 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) <3> Access to address (4n+2) Address Address <4> Access to address (4n+3) Address Address 15 15 7 8 7 7 8 7 0 0 0 0 0 External data bus Byte data External data bus Byte data External data bus 15 15 7 8 7 7 8 7 0 0 0 Byte data External data bus Byte data 4n + 3 4n + 1 4n 4n + 2 User's Manual U16580EE3V1UD00 155 Chapter 4 Bus Control Function (PD70F3187 only) (c) When the data bus width is 8 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address Address 7 7 0 0 External data bus Byte data 7 7 0 Byte data <3> Access to address (4n+2) Address 7 7 0 0 External data bus Byte data Address 7 7 0 0 0 External data bus Byte data External data bus 4n + 1 4n <4> Access to address (4n+3) 4n + 2 4n + 3 (d) When the data bus width is 32 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address <3> Access to address (4n+2) Address <4> Access to address (4n+3) Address Address 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 8 7 8 7 31 4n 4n + 1 4n + 2 7 7 7 7 8 7 4n + 3 0 0 0 0 0 0 0 0 Byte data External data bus Byte data External data bus Byte data External data bus Byte data External data bus 156 User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) (e) When the data bus width is 16 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address <3> Access to address (4n+2) Address Address 15 <4> Access to address (4n+3) Address 15 15 7 8 7 7 8 7 15 4n 4n + 2 7 8 7 7 8 7 0 0 0 0 0 0 0 0 Byte data External data bus Byte data External data bus Byte data External data bus Byte data External data bus 4n + 1 4n + 3 (f) When the data bus width is 8 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address 7 7 0 Byte data <3> Access to address (4n+2) Address 7 7 0 0 External data bus Byte data Address Address 7 7 0 0 0 External data bus Byte data External data bus 7 7 0 0 External data bus Byte data 4n <4> Access to address (4n+3) 4n + 1 4n + 2 User's Manual U16580EE3V1UD00 4n + 3 157 Chapter 4 (2) Bus Control Function (PD70F3187 only) Halfword access (16 bits) (a) When the data bus width is 32 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address Address 31 31 24 23 24 23 15 16 15 15 16 15 8 7 8 7 8 7 8 7 4n + 2 4n + 1 4n + 1 4n 0 0 0 0 Halfword data External data bus Halfword data External data bus <3> Access to address (4n+2) <4> Access to address (4n+3) 1st access Address 2nd access Address 31 Address 31 4n + 3 31 4n + 3 24 23 24 23 24 23 4n + 2 15 16 15 8 7 8 7 0 0 Halfword data External data bus 15 16 15 15 16 15 8 7 8 7 8 7 8 7 0 0 0 0 Halfword data External data bus Halfword data External data bus 4n + 4 158 User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) (b) When the data bus width is 16 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access Address 15 15 8 7 8 7 0 Halfword data 2nd access Address Address 15 15 8 7 8 7 8 7 0 0 0 0 Halfword data External data bus Halfword data External data bus 15 15 8 7 0 External data bus 4n + 1 4n + 1 4n + 2 4n <3> Access to address (4n+2) <4> Access to address (4n+3) 1st access Address 15 15 15 15 15 8 7 8 7 4n + 3 8 7 8 7 Address Address 15 4n + 3 8 7 2nd access 8 7 4n + 4 4n + 2 0 0 0 0 0 0 Halfword data External data bus Halfword data External data bus Halfword data External data bus User's Manual U16580EE3V1UD00 159 Chapter 4 Bus Control Function (PD70F3187 only) (c) When the data bus width is 8 bits (Little Endian) <1> Access to address (4n) 1st access <2> Access to address (4n+1) 2nd access 1st access 15 15 Address Address 7 0 0 External data bus Halfword data 7 0 Halfword data 0 External data bus Halfword data External data bus External data bus Halfword data 4n + 2 4n + 1 <4> Access to address (4n+3) 1st access 2nd access 15 15 Address 8 7 7 0 0 External data bus Halfword data 8 7 Address 0 0 0 Halfword data External data bus Halfword data Address 8 7 7 0 0 0 External data bus Halfword data External data bus 7 4n + 3 4n + 2 160 0 0 15 Address 0 0 2nd access 7 7 4n + 1 1st access Address 8 7 7 <3> Access to address (4n+2) 8 7 Address 8 7 4n 15 15 15 8 7 8 7 2nd access 4n + 4 4n + 3 User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) (d) When the data bus width is 32 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address Address 31 31 4n 24 23 24 23 4n + 1 4n + 1 15 16 15 15 16 15 8 7 8 7 8 7 8 7 4n + 2 0 0 0 0 Halfword data External data bus Halfword data External data bus <3> Access to address (4n+2) <4> Access to address (4n+3) 1st access 2nd access Address Address Address 31 31 31 24 23 24 23 24 23 4n + 4 15 16 15 8 7 8 7 15 16 15 15 16 15 8 7 8 7 8 7 8 7 4n + 2 4n + 3 4n + 3 0 Halfword data 0 0 0 0 0 External data bus Halfword data External data bus Halfword data External data bus User's Manual U16580EE3V1UD00 161 Chapter 4 Bus Control Function (PD70F3187 only) (e) When the data bus width is 16 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access Address 15 15 8 7 8 7 2nd access Address Address 15 15 15 15 8 7 8 7 8 7 8 7 0 0 0 External data bus Halfword data External data bus 4n + 2 4n 4n + 1 4n + 1 0 0 0 Halfword data External data bus Halfword data <3> Access to address (4n+2) <4> Access to address (4n+3) 1st access Address Address 15 15 2nd access Address 15 15 15 15 8 7 8 7 8 7 8 7 4n + 4 4n + 2 8 7 8 7 4n + 3 4n + 3 162 0 0 0 0 0 0 Halfword data External data bus Halfword data External data bus Halfword data External data bus User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) (f) When the data bus width is 8 bits (Big Endian) <1> Access to address (4n) 1st access <2> Access to address (4n+1) 2nd access 15 1st access 15 Address 8 7 7 0 Halfword data Address 7 0 0 External data bus Halfword data 0 0 0 External data bus Halfword data External data bus 0 External data bus Halfword data 4n + 1 4n + 2 4n + 1 <4> Access to address (4n+3) 1st access 2nd access 15 15 Address 7 0 2nd access 7 Address 8 7 7 <3> Access to address (4n+2) 8 7 Address 8 7 4n 15 15 15 8 7 1st access 2nd access Address 8 7 7 8 7 15 Address 7 4n + 3 4n + 2 8 7 Address 7 4n + 4 4n + 3 0 0 0 0 0 0 0 0 Halfword data External data bus Halfword data External data bus Halfword data External data bus Halfword data External data bus User's Manual U16580EE3V1UD00 163 Chapter 4 (3) Bus Control Function (PD70F3187 only) Word access (32 bits) (a) When the bus width is 32 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access Address Address 31 31 24 23 24 23 16 15 16 15 8 7 8 7 0 0 2nd access 31 31 4n + 3 Address 31 31 24 23 24 23 16 15 16 15 8 7 8 7 4n + 3 24 23 24 23 4n + 2 4n + 2 16 15 16 15 8 7 8 7 4n + 1 4n + 1 4n + 4 4n Word data 0 External data bus <3> Access to address (4n+2) 1st access 0 Word data 2nd access 1st access 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 8 7 8 7 8 7 0 0 0 0 0 External data bus Word data External data bus Word data External data bus 31 24 23 24 23 24 23 16 15 16 15 16 15 8 7 8 7 8 7 8 7 0 0 0 Word data External data bus Word data 16 15 Address 31 31 24 23 2nd access 31 31 24 23 External data bus Address Address 31 31 0 Word data <4> Access to address (4n+3) Address 31 0 External data bus 4n + 3 4n + 3 4n + 6 4n + 2 4n + 5 4n + 5 4n + 4 4n + 4 164 User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) (b) When the bus width is 16 bits (Little Endian) <1> Access to address (4n) 1st access 2nd access 31 31 24 23 24 23 Address 16 15 15 Address 16 15 15 4n + 3 4n + 1 8 7 8 7 8 7 8 7 4n 4n + 2 0 0 0 0 Word data External data bus Word data External data bus <2> Access to address (4n+1) 1st access 2nd access 3rd access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 8 7 Address 16 15 15 8 7 8 7 Address 16 15 15 8 7 8 7 4n + 3 4n + 1 4n + 4 4n + 2 0 0 0 0 Word data External data bus Word data External data bus User's Manual U16580EE3V1UD00 0 Word data 0 External data bus 165 Chapter 4 Bus Control Function (PD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access 31 31 24 23 24 23 Address 16 15 15 Address 16 15 15 4n + 5 4n + 3 8 7 8 7 8 7 8 7 4n + 2 0 Word data 4n + 4 0 0 0 External data bus Word data External data bus <4> Access to address (4n+3) 1st access 2nd access 3rd access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 8 7 Address 16 15 15 8 7 8 7 Address 16 15 15 8 7 8 7 4n + 5 4n + 3 4n + 6 4n + 4 0 Word data 166 0 External data bus 0 Word data 0 External data bus User's Manual U16580EE3V1UD00 0 Word data 0 External data bus Chapter 4 Bus Control Function (PD70F3187 only) (c) When the data bus width is 8 bits (Little Endian) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 Address 8 7 7 4n 0 0 Word data 7 4n + 1 0 External data bus Address 8 7 0 Word data 7 4n + 2 0 External data bus Address 8 7 0 Word data 4n + 3 0 External data bus 0 Word data External data bus <2> Access to address (4n+1) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 Address 8 7 7 4n + 1 0 Word data 0 External data bus 8 7 Address 7 4n + 2 0 0 Word data External data bus 8 7 Address 7 4n + 3 0 Word data 0 External data bus User's Manual U16580EE3V1UD00 4n + 4 0 Word data 0 External data bus 167 Chapter 4 Bus Control Function (PD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 Address 8 7 7 4n + 2 0 Word data Address 8 7 7 4n + 3 0 0 0 External data bus Word data External data bus Address 8 7 7 4n + 4 0 0 Word data 4n + 5 0 External data bus 0 Word data External data bus <4> Access to address (4n+3) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 Address 8 7 7 4n + 3 0 Word data 168 0 External data bus 8 7 Address 7 4n + 4 0 0 Word data External data bus 8 7 Address 7 4n + 5 0 Word data 0 External data bus User's Manual U16580EE3V1UD00 4n + 6 0 Word data 0 External data bus Chapter 4 Bus Control Function (PD70F3187 only) (d) When the data bus width is 32 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access Address Address 31 31 31 31 2nd access Address 31 31 4n + 4 4n 24 23 24 23 24 23 24 23 16 15 16 15 16 15 8 7 8 7 8 7 0 0 0 <3> Access to address (4n+2) 31 24 23 24 23 8 7 8 7 External data bus 0 0 Word data External data bus <4> Access to address (4n+3) 2nd access Address 31 0 Word data External data bus 1st access 16 15 4n + 3 4n + 3 Word data 16 15 4n + 2 4n + 2 8 7 24 23 4n + 1 4n + 1 16 15 24 23 1st access Address Address 31 31 24 23 24 23 2nd access 31 31 24 23 24 23 Address 31 31 24 23 24 23 4n + 4 4n + 4 4n + 5 16 15 16 15 8 7 8 7 4n + 5 16 15 16 15 16 15 16 15 16 15 16 15 8 7 8 7 8 7 8 7 8 7 8 7 0 0 4n + 6 4n + 2 4n + 3 4n + 3 0 Word data 0 External data bus 0 0 Word data External data bus 0 Word data 0 External data bus User's Manual U16580EE3V1UD00 Word data External data bus 169 Chapter 4 Bus Control Function (PD70F3187 only) (e) When the data bus width is 16 bits (Big Endian) <1> Access to address (4n) 1st access 2nd access 31 31 24 23 24 23 Address 16 15 15 Address 16 15 15 8 7 8 7 4n 8 7 8 7 4n + 2 4n + 3 4n + 1 0 0 Word data External data bus 0 0 Word data External data bus <2> Access to address (4n+1) 1st access 2nd access 3rd access 31 31 31 24 23 24 23 24 23 Address Address 16 15 15 16 15 15 8 7 8 7 8 7 8 7 0 0 Address 16 15 15 8 7 8 7 0 0 4n + 2 4n + 1 0 Word data 170 0 External data bus 4n + 4 4n + 3 Word data External data bus User's Manual U16580EE3V1UD00 Word data External data bus Chapter 4 Bus Control Function (PD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access 31 31 24 23 24 23 Address 16 15 15 Address 16 15 15 8 7 8 7 4n + 2 8 7 8 7 4n + 4 4n + 5 4n + 3 0 0 Word data 0 External data bus 0 Word data External data bus <4> Access to address (4n+3) 1st access 2nd access 3rd access 31 31 31 24 23 24 23 24 23 Address Address 16 15 15 16 15 15 8 7 8 7 8 7 8 7 0 0 0 External data bus Word data External data bus Address 16 15 15 8 7 8 7 0 0 4n + 4 4n + 3 0 Word data 4n + 6 4n + 5 User's Manual U16580EE3V1UD00 Word data External data bus 171 Chapter 4 Bus Control Function (PD70F3187 only) (f) When the data bus width is 8 bits (Big Endian) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 Address 8 7 7 4n 0 0 Word data 7 0 0 Word data External data bus Address 8 7 7 4n + 3 4n + 2 4n + 1 0 External data bus Address 8 7 0 0 Word data External data bus 0 Word data External data bus <2> Access to address (4n+1) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 Address 8 7 7 4n + 1 0 Word data 172 0 External data bus 8 7 Address 7 4n + 2 0 0 Word data External data bus 8 7 Address 7 4n + 4 4n + 3 0 Word data 0 External data bus User's Manual U16580EE3V1UD00 0 Word data 0 External data bus Chapter 4 Bus Control Function (PD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 Address 8 7 7 4n + 2 0 0 Word data 7 4n + 3 0 External data bus Address 8 7 0 Word data 7 4n + 5 4n + 4 0 External data bus Address 8 7 0 0 Word data External data bus 0 Word data External data bus <4> Access to address (4n+3) 1st access 2nd access 3rd access 4th access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 Address 8 7 7 4n + 3 0 Word data 0 External data bus 8 7 Address 7 0 0 External data bus Address 7 4n + 6 4n + 5 4n + 4 Word data 8 7 0 Word data 0 External data bus User's Manual U16580EE3V1UD00 0 Word data 0 External data bus 173 Chapter 4 Bus Control Function (PD70F3187 only) 4.6 Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each CS area. The number of wait states can be specified by data wait control registers 0 and 1 (DWC0, DWC1) in programming. Just after system reset, all blocks have 7 data wait states inserted. These registers can be read/written in 16-bit units. Cautions: 1. The internal ROM area (flash memory) and the internal RAM area are not subject to programmable waits and ordinarily no wait access is carried out. The internal peripheral I/O area is also not subject to programmable wait states, with wait control performed only by each peripheral function. 2. Write to the DWC0 and DWC1 registers after reset, and then do not change the set values. Also, do not access an external memory area other than that for this initialization routine until initial setting of the DWC0 and DWC1 registers is finished. However, it is possible to access external memory areas whose initialization has been finished. Figure 4-8: After reset: 7777H 15 DWC0 0 Data Wait Control Registers 0, 1 (DWC0, DWC1) Format 14 R/W 13 12 Address: 11 DW32 DW31 DW30 10 0 DWC1 0 14 R/W 174 0 6 13 12 11 DW72 DW71 DW70 0 10 9 4 3 0 2 1 0 DW02 DW01 DW00 CS0 FFFFF486H 8 7 DW62 DW61 DW60 CS6 5 DW12 DW11 DW10 CS1 Address: CS7 Remark: 7 CS2 7777H 15 8 DW22 DW21 DW20 CS3 After reset: 9 FFFFF484H 0 6 5 4 DW52 DW51 DW50 CS5 3 0 2 1 DW42 DW41 DW40 CS4 Number of Inserted Data Wait States During CSn Area Access DWCn2 DWCn1 DWCn0 0 0 0 No wait states inserted 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 n = 0 to 7 User's Manual U16580EE3V1UD00 0 Chapter 4 (2) Bus Control Function (PD70F3187 only) Address wait control register (AWC) The V850E/PH2 allows insertion of address setup wait and address hold wait states before and after the T1 cycle. The address setup wait and address hold wait states can be set with the AWC register for each CS area. This register can be read/written in 16-bit units. Cautions: 1. The internal ROM area (flash memory) and the internal RAM area are not subject to programmable waits and ordinarily no wait access is carried out. The internal peripheral I/O area is also not subject to programmable wait states, with wait control performed only by each peripheral function. 2. Write to the AWC registers after reset, and then do not change the set values. Also, do not access an external memory area other than that for this initialization routine until initial setting of the AWC registers is finished. However, it is possible to access external memory areas whose initialization has been finished. Figure 4-9: After reset: 0000H 15 AWC 14 R/W 13 12 11 Address: 10 9 8 FFFFF488H 7 6 5 4 3 2 1 0 AHW7 ASW7 AHW6 ASW6 AHW5 ASW5 AHW4 ASW4 AHW3 ASW3 AHW2 ASW2 AHW1 ASW1 AHW0 ASW0 CS7 CS6 CS5 AHWn CS4 CS3 CS2 CS1 CS0 Address Hold Wait Insertion During CSn Area Access 0 No Insertion 1 Address hold wait state inserted after T1 bus cycle ASW1 Remark: Address Wait Control Register (AWC) Address Setup Wait Insertion During CSn Area Access 0 No Insertion 1 Address setup wait state inserted before T1 bus cycle n = 0 to 7 User's Manual U16580EE3V1UD00 175 Chapter 4 Bus Control Function (PD70F3187 only) 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle after the T2 state to meet the data output float delay time (tdf) on memory read access for each CS space. The bus cycle following the T2 state starts after the idle state is inserted. An idle state is inserted after read/write cycles for SRAM, external I/O, or external ROM. In the following cases, an idle state is inserted in the timing. * after read/write cycles for SRAM, external I/O, or external ROM The idle state insertion setting can be specified by program using the bus cycle control register (BCC) and the bus clock dividing control register (DVC). Immediately after the system reset, idle state insertion is automatically programmed for all memory blocks on read access. 176 User's Manual U16580EE3V1UD00 Chapter 4 (1) Bus Control Function (PD70F3187 only) Bus cycle control register (BCC) This register can be read/written in 16-bit units. Reset input changes the value of this register to initial setting AAAAH. Cautions: 1. Idle states cannot be inserted in internal ROM, internal RAM, on-chip peripheral I/O, or programmable peripheral I/O areas. 2. Write to the BCC register after reset, and then do not change the set value. Also, do not access an external memory area other than that for this initialization routine until initial setting of the BCC register is finished. However, it is possible to access external memory areas whose initialization has been finished. 3. Do not change the settings of bits that are 0 after reset. Otherwise the operation of the external bus interface cannot be ensured. Figure 4-10: After reset: BCC AAAAH R/W Address: FFFFF48AH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BC71 0 BC61 0 BC51 0 BC41 0 BC31 0 BC21 0 BC11 0 BC01 0 BCn1 Idle State Insertion During CSn Area Access 0 No insertion 1 Idle state inserted Remark: Remark: Bus Cycle Control Register (BCC) When bit BCn1 bit is set to "1", an idle state will be inserted after any read access. If an idle state after write access is necessary, the BCWI bit of the DVC register has to be set additionally. n = 0 to 7 User's Manual U16580EE3V1UD00 177 Chapter 4 (2) Bus Control Function (PD70F3187 only) Bus clock dividing control register (DVC) This register can be read/written in 8-bit units. Reset input changes the value of this register to initial setting 01H. Cautions: 1. Idle states cannot be inserted in internal ROM, internal RAM, on-chip peripheral I/O, or programmable peripheral I/O areas. 2. Write to the DVC register after reset, and then do not change the set value. Also, do not access an external memory area other than that for this initialization routine until initial setting of the DVC register is finished. However, it is possible to access external memory areas whose initialization has been finished. 3. Do not change the settings of bits 0 to 6. Otherwise the operation of the external bus interface cannot be ensured. Figure 4-11: After reset: DVC 01H Bus Clock Dividing Control Register (DVC) R/W Address: FFFFF48EH 7 6 5 4 3 2 1 0 BCWI 0 0 0 0 0 0 1 BCWI Idle State Insertion after Write Cycle 0 Idle state not inserted after write access 1 Idle state inserted after write accessNote Note: BCWI bit setting is only valid when BCn1 bit of the BCC register, corresponding to the CSn area for which the write access will be performed, is set to "1". (n = 0 to 7) 178 User's Manual U16580EE3V1UD00 Chapter 4 Bus Control Function (PD70F3187 only) 4.8 Bus Priority Order There are two external bus cycles: operand data access and instruction fetch. As for the priority order, the highest priority has the instruction fetch than operand data access. An instruction fetch may be inserted between read access and write access during read modify write access. Also, an instruction fetch may be inserted between bus access and bus access during CPU bus clock. Table 4-2: Priority Order Low High Bus Priority Order External Bus Cycle Bus Master Operand data access CPU Instruction fetch CPU User's Manual U16580EE3V1UD00 179 Chapter 4 Bus Control Function (PD70F3187 only) 4.9 Boundary Operation Conditions 4.9.1 Program space Branching to the on-chip peripheral I/O area is prohibited. If the above is performed, undefined data is fetched, and fetching from the external memory is not performed. 4.9.2 Data space The V850E/PH2 is provided with an address misalign function. Through this function, regardless of the data format (word, halfword or byte), data can be allocated to all addresses. However, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) External bus width: 16 bits (a) In the case of halfword-length data access When the address's LSB is 1, a byte-length bus cycle will be generated 2 times. (b) In the case of word-length data access * When the address's LSB is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle. * When the address's lower 2 bits are 10B, a halfword-length bus cycle will be generated 2 times. (2) External bus width: 32 bits (a) In the case of halfword-length data access When the address's lower 2 bits are 11B, a byte-length bus cycle will be generated 2 times. (b) In the case of word-length data access When the address's lower 2 bits are 10B, a halfword-length bus cycle will be generated 2 times. 180 User's Manual U16580EE3V1UD00 Chapter 5 Memory Access Control Function (PD70F3187 only) 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features * SRAM is accessed in a minimum of 2 states. * Up to 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers. * Data wait can be controlled via WAIT pin input. * An idle state can be inserted after a read/write cycle by setting the BCC and DVC registers. * An address setup wait state and an address hold state can be inserted by setting the ASC register. Remark: The memory access control function is not available on PD70F3447. User's Manual U16580EE3V1UD00 181 Chapter 5 Memory Access Control Function (PD70F3187 only) 5.1.2 SRAM connection Examples of connection to SRAM are shown below. Figure 5-1: Examples of Connection to SRAM (1/2) (a) When Data Bus Width is 32 Bits and Data Size of SRAM is 8 Bits V850E/PH2 A2 to A20 D24 to D31 CSn RD WR BEN3 1 D16 to D23 BEN2 1 D8 to D15 BEN1 1 D0 to D7 BEN0 1 SRAM A0 to A18 I/O1 to I/O8 (PD444008L CS 512 Kwords x 8 bits) OE WE SRAM A0 to A18 I/O1 to I/O8 (PD444008L CS 512 Kwords x 8 bits) OE WE SRAM A0 to A18 I/O1 to I/O8 (PD444008L CS 512 Kwords x 8 bits) OE WE SRAM A0 to A18 I/O1 to I/O8 (PD444008L CS 512 Kwords x 8 bits) OE WE (b) When Data Bus Width is 8 Bits and Data Size of SRAM is 8 Bits V850E/PH2 A0 to A18 D0 to D7 SRAM A0 to A18 I/O1 to I/O8 (PD444008L CS 512 Kwords x 8 bits) OE WE CSn RD WR Remark: 182 n = 0, 1, 3, 4 User's Manual U16580EE3V1UD00 Chapter 5 Memory Access Control Function (PD70F3187 only) Figure 5-1: Examples of Connection to SRAM (2/2) (c) When Data Bus Width is 32 Bits and Data Size of SRAM is 16 Bits V850E/PH2 A2 to A19 D16 to D31 SRAM A0 to A17 I/O1 to I/O16 (PD444016L 256 Kwords x 16 bits) CSn RD BEN3 BEN2 WR CS OE UB LB WE SRAM A0 to A17 I/O1 to I/O16 D0 to D15 (PD444016L 256 Kwords x 16 bits) CS OE UB LB WE BEN1 BEN0 (d) When Data Bus Width is 16 Bits and Data Size of SRAM is 16 Bits V850E/PH2 A1 to A18 D0 to D15 SRAM A0 to A17 I/O1 to I/O16 (PD444016L 256 Kwords x 16 bits) CS OE UB LB WE CSn RD BEN1 BEN0 WR Remark: n = 0, 1, 3, 4 User's Manual U16580EE3V1UD00 183 Chapter 5 Memory Access Control Function (PD70F3187 only) 5.1.3 SRAM, external ROM, external I/O access Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/8) (a) Read T1 T2 T1 TW T2 Bus clock A0 to A21 (output) Address Address CSn (output) Note 1 Note 1 Note 2 Note 2 RD (output) WR (output) H BEN0 to BEN3 (output) D0 to D31 (input) Data Data WAIT (input) without data wait insertion with data wait insertion Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. 184 User's Manual U16580EE3V1UD00 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (2/8) (b) Read (Idle State Inserted) T1 T2 TI Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0 to BEN3 (output) H Note 2 D0 to D31 (input) Data WAIT (input) Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. User's Manual U16580EE3V1UD00 185 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (3/8) (c) Read (Data Wait, Idle State Inserted) T1 TW T2 TI Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0 to BEN3 (output) H Note 2 D0 to D31 (input) Data WAIT (input) Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. 186 User's Manual U16580EE3V1UD00 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (4/8) (d) Read (Address Setup Wait and Address Hold Wait State Inserted) T1S T1 T1H T2 Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) H BEN0 to BEN3 (output) Note 2 D0 to D31 (input) Data WAIT (input) Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. User's Manual U16580EE3V1UD00 187 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (5/8) (e) Write T1 T2 T1 TW T2 Bus clock A0 to A21 (output) Address Address CSn (output) Note 1 Note 1 Note 2 Note 2 RD (output) H WR (output) BEN0 to BEN3 (output) D0 to D31 (input) Data Data WAIT (input) without data wait insertion with data wait insertion Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. 188 User's Manual U16580EE3V1UD00 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (6/8) (f) Write (Idle State Inserted) T1 T2 TI Bus clock A0 to A21 (output) Address CSn (output) RD (output) Note 1 H WR (output) BEN1 to BEN3 (output) D0 to D31 (input) Note 2 Data WAIT (input) Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. User's Manual U16580EE3V1UD00 189 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (7/8) (g) Write (Data Wait, Idle State Inserted) T1 TW T2 TI Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) H WR (output) BEN0 to BEN3 (output) D0 to D31 (input) Note 2 Data WAIT (input) Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. 190 User's Manual U16580EE3V1UD00 Chapter 5 Figure 5-2: Memory Access Control Function (PD70F3187 only) SRAM, External ROM, External I/O Access Timing (8/8) (h) Read (Address Setup Wait and Address Hold Wait State Inserted) T1S T1 T1H T2 Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) H WR (output) BEN0 to BEN3 (output) Note 2 D0 to D31 (input) Data WAIT (input) Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1 registers. 2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the BSC register Remarks: 1. n = 0, 1, 3, 4 2. Bus clock = fXX/2 3. The circle indicates the sampling timing. 4. The dashed line indicates the high impedance state. User's Manual U16580EE3V1UD00 191 Chapter 5 Memory Access Control Function (PD70F3187 only) [MEMO] 192 User's Manual U16580EE3V1UD00 Chapter 6 DMA Functions (DMA Controller) 6.1 Features The V850E/PH2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between internal RAM (iRAM) and peripheral I/O registers, based on DMA requests issued by the on-chip peripheral I/O (A/D converters, inverter timers, and serial interfaces), with the following features. * 2 channels for DMA transfer from A/D converter (ADC0, ADC1) - Transfer object: I/O iRAM - Transfer size: 16 bits - Dedicated transfer channels for ADC0 and ADC1 * 2 channels for DMA transfer to PWM timer (TMR0, TMR1) - Transfer object: iRAM I/O - Transfer size: 16 bits - Dedicated transfer channels for TMR0 and TMR1 * 2 channels for DMA transfer from serial interfaces on reception completion - Transfer object: I/O iRAM - Transfer size: 8 or 16 bits - DMA request for each channel selectable Clocked serial interfaces: CSIB0, CSIB1, CSI30, CSI31 Asynchronous serial interface: UARTC0, UARTC1 * 2 channels for DMA transfer to serial interfaces on transmission repetition - Transfer object: iRAM I/O - Transfer size: 8 or 16 bits - DMA request for each channel selectable Clocked serial interfaces: CSIB0, CSIB1, CS30, CSI31 Asynchronous serial interface: UARTC0, UARTC1 * Up to 256 transfer counts for each channel. User's Manual U16580EE3V1UD00 193 Chapter 6 DMA Functions (DMA Controller) 6.2 Control Registers (1) DMA transfer memory start address registers 0 to 7 (MAR0 to MAR7) The MARn register specifies the subordinated 16 bits of the DMA transfer start address within the internal RAM area for the DMA channel n (n = 0 to 7). This register can be read or written in 16-bit units. After reset the register content is undefined. Figure 6-1: DMA Transfer Memory Start Address Registers 0 to 7 (MAR0 to MAR7) After reset: undefined 15 14 13 R/W 12 11 Address: 10 9 8 MAR0 MAR2 MAR4 MAR6 7 FFFFF300H, FFFFF304H, FFFFF308H, FFFFF30CH, 6 5 4 MAR1 MAR3 MAR5 MAR7 3 FFFFF302H FFFFF306H FFFFF30AH FFFFF30EH 2 1 0 MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn MARn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MARn (n = 0 to 7) Cautions: 1. Since the internal RAM area is mapped between 3FF0000H and 3FF7FFFH the value written to the MARn register has to be in the range from 0000H to 7FFFH. 2. The value set to the MARn register is increased by each DMA transfer of channels. It does not keep the initial value after the DMA transfer ends. 194 User's Manual U16580EE3V1UD00 Chapter 6 (2) DMA Functions (DMA Controller) DMA transfer SFR start address registers 2, 3 (SAR2, SAR3) The SARn register specifies the start address of the TMR register for which the DMA transfer is started on DMA channel n (n = 2, 3). This register can be read or written in 8-bit units. After reset the register content is undefined. Figure 6-2: After reset: SARn DMA Transfer SFR Start Address Registers 2, 3 (SAR2, SAR3) undefined R/W Address: SAR2 FFFFF314H, SAR3 FFFFF316H 7 6 5 4 3 2 1 0 0 0 0 0 0 SARn2 SARn1 SARn0 (n = 2, 3) DMA Transfer Start Address of TMR Reload Register SARn2 SARn1 SARn0 n=2 n=3 Register Address Register Address 0 0 0 TR0CCR5 FFFFF590H TR1CCR5 FFFFF5D0H 0 0 1 TR0CCR4 FFFFF592H TR1CCR4 FFFFF5D2H 0 1 0 -Note 1 FFFFF594H -Note 1 FFFFF5D4H 0 1 1 -Note 2 FFFFF596H -Note 2 FFFFF5D6H 1 0 0 TR0CCR0 FFFFF598H TR1CCR0 FFFFF5D8H 1 0 1 TR0CCR3 FFFFF59AH TR1CCR3 FFFFF5DAH 1 1 0 TR0CCR2 FFFFF59CH TR1CCR2 FFFFF5DCH 1 1 1 TR0CCR1 FFFFF59EH TR1CCR1 FFFFF5DEH Notes: 1. Although the register address is meaningless, a transfer to this address is always performed when SARn2 to SARn0 bits are equal to 010B or less. 2. Although the register address is meaningless, a transfer to this address is always performed when SARn2 to SARn0 bits are equal to 011B or less. Caution: During DMA transfer (DEn = 1) the contents of the SARn register may change. After each DMA transfer the contents is incremented by 1 until the final value (07H) is reached. When the SARn register contents becomes 07H, the initial set value is reloaded. User's Manual U16580EE3V1UD00 195 Chapter 6 (3) DMA Functions (DMA Controller) DMA transfer count registers 0 to 7 (DTCR0 to DTCR7) The DTCRn register is an 8-bit register that set the transfer count for DMA channel n and stores the remaining transfer count during DMA transfer (n = 0 to 7). This register can be read or written in 8-bit units. After reset the register content is undefined. Figure 6-3: After reset: DTCRn DMA Transfer Count Registers 0 to 7 (DTCR0 to DTCR7) undefined R/W Address: DTCR0 DTCR2 DTCR4 DTCR6 FFFFF320H, FFFFF324H, FFFFF328H, FFFFF32CH, DTCR1 DTCR3 DTCR5 DTCR7 FFFFF322H FFFFF326H FFFFF32AH FFFFF32EH 7 6 5 4 3 2 1 0 DTCRn7 DTCRn6 DTCRn5 DTCRn4 DTCRn3 DTCRn2 DTCRn1 DTCRn0 DTCRn DTCRn DTCRn DTCRn DTCRn DTCRn DTCRn DTCRn 7 6 5 4 3 2 1 0 Remaining DMA Transfer Counts 0 0 0 0 0 0 0 0 256 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 3 * * * * * * 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 Cautions: 1. The value set to the DTCRn register is decreased by each DMA transfer of channel n. It does not keep the initial value after the DMA transfer ends. Therefore, after DMA transfer end the DTCRn register values becomes 00H. 2. A DMA request becomes only effective after the DTCRn register was written. Even if 00H (means a transfer count of 256) is the initial value, the DTRCn register must be rewritten in order to enable a new DMA transfer. Remark: 196 n = 0 to 7 User's Manual U16580EE3V1UD00 Chapter 6 (4) DMA Functions (DMA Controller) DMA mode control register (DMAMC) The DMAMC register is an 8-bit register that controls the operation of the DMA channels. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 6-4: After reset: DMAMC 00H DMA Mode Control Register (DMAMC) R/W Address: 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DEn Caution: (5) DMAMC FFFFF330H Control Bit of DMA Channel n 0 DMA transfer operation of channel n disabled 1 DMA transfer operation of channel n enabled Writing of the DE1 and DE0 bits is prohibited if the corresponding A/D converter is operating. DMA status register (DMAS) The DMAS register is an 8-bit register that displays the transfer status of the DMA channels. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 6-5: After reset: DMAS 00H DMA Status Register (DMAS) R/W Address: DMAMC FFFFF332H 7 6 5 4 3 2 1 0 DMAS7 DMAS6 DMAS5 DMAS4 DMAS3 DMAS2 DMAS1 DMAS0 DMASn Status Bit of DMA Channel n 0 DMA transfer of channel n is idle or in progress 1 DMA transfer of channel n is completed * The DMASn bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. * Since the DMASn bit is not cleared by the DMAC, it has to be cleared by software before DMA transfer is started. Remark: n = 0 to 7 User's Manual U16580EE3V1UD00 197 Chapter 6 (6) DMA Functions (DMA Controller) DMA data size control register (DMDSC) The DMADSC register is an 8-bit register that controls the transfer data size of DMA channels 4 to 7. The data size of DMA channels 0 to 3 is fixed, and therefore not selectable. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 6-6: After reset: 00H 7 DMADSC R/W 6 198 Address: 5 4 DMADSC7 DMADSC6 DMADSC5 DMADSC4 DMADSCn Remark: DMA Data Size Control Register (DMDSC) DMAMC FFFFF334H 3 2 1 0 0 0 0 0 Transfer Data Size of DMA Channel n 0 8 bits 1 16 bits n = 4 to 7 User's Manual U16580EE3V1UD00 Chapter 6 (7) DMA Functions (DMA Controller) DMA trigger factor registers 4 to 7 (DTFR4 to DTFR7) The DTFRn register is an 8-bit register that controls the DMA transfer start trigger of DMA channel n via interrupt requests from on-chip peripheral I/O (n = 4 to 7). The interrupt request set by this register serves as DMA transfer start factor. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Cautions: 1. Do not set the same transfer start factor by different DTFRn registers. 2. Do not rewrite the DTFRn register until a started DMA transfer ends (corresponding DTCRn register value is 00H). 3. Write the DTFRn register before setting the corresponding DTCRn register. According to the present transfer start factor in the DTFRn register a DMA might be started when the DTCRn register is written previously. Figure 6-7: After reset: DTFRn DMA Trigger Factor Registers 4 to 7 (DTFR4 to DTFR7) 00H R/W Address: DTFR4 FFFFF348H, DTFR5 FFFFF34AH DTFR6 FFFFF34CH, DTFR7 FFFFF34EH 7 6 5 4 3 2 1 0 0 0 0 0 0 IFCn2 IFCn1 IFCn0 IFCn2 IFCn1 IFCn0 0 0 0 DMA request from on-chip peripheral I/O disabled 0 0 1 INTUC0R INTUC0T 0 1 0 INTUC1R INTUC1T 0 1 1 INTCB0R INTCB0T 1 0 0 INTCB1RNote INTCB1TNote 1 0 1 INTC30 INTC30 1 1 0 INTC31Note INTC31Note 1 1 1 Setting prohibited DMA Transfer Start Factor when n = 4, 5 when n = 6, 7 Note: Not available on PD70F3447. Remark: n = 4 to 7 User's Manual U16580EE3V1UD00 199 Chapter 6 DMA Functions (DMA Controller) 6.3 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 >... > DMA channel 7 6.4 DMA Operation 6.4.1 DMA transfer of A/D converter result registers (ADC0, ADC1) The DMAC has two dedicated channels to support DMA transfer for both A/D converters independently, DMA channel 0 for A/D converter 0 and DMA channel 1 for A/D converter 1. As DMA trigger factor, which requests and starts the DMA transfer, the end of conversion interrupt signal of the corresponding A/D converter is pre-defined (INTADn) (n = 0, 1). For each DMA trigger the data will be transferred from the A/D conversion result register for DMA (ADDMAn) into the internal RAM specified as destination. While the source transfer address is fixed to the ADDMAn register of the corresponding A/D converter (ADCn), the destination start address can be set up to any even address in the internal RAM. When the DMA transfer count of a DMA channel terminates, the DMA transfer is stopped and a termination interrupt is generated. The maximum DMA transfer count is 256. Since the DMA transfer is performed for each finished A/D conversion, it is possible to transfer more than conversion results of one A/D converter scan sequence. However, the user has to take care that the number of transfer counts complies with the product of A/D converter scan area size and the number of A/D converter start triggers. 200 User's Manual U16580EE3V1UD00 Chapter 6 Figure 6-8: DMA Functions (DMA Controller) Initialization of DMA Transfer for A/D Conversion Result Initialization of DMA transfer for A/D conversion result of ADCn (DMA channel 0 or 1) no ADCEn bit = 1? yes ADCSn bit = 1? no yes Disable operation of A/D converter n: ADCEn bit = 0 Set up A/D conversion scan range in the ADMn2 register Set up the MARx register with destination start address within iRAM in Specify the DMA transfer count in the DTCRx register (1 to 256) Clear status bit of DMA channel x: DMASx bit = 0 Enable DMA transfer channel x: DEx bit = 1 Enable operation of A/D converter n: ADCEn bit = 1 End of initialization Remark: n = 0, 1 x=n (number of ADC channel) (number of DMA channel) User's Manual U16580EE3V1UD00 201 Chapter 6 DMA Functions (DMA Controller) Figure 6-9: Operation of DMA Channel 0/1 Operation of DMA channel 0/1 no DEx bit newly written ? DMA transfer will be enabled by write access to the corresponding DEn bit. yes no DEx bit = 1 ? yes ADDMARQn occured ? no yes Transfer content from ADDMAn register to iRAM : (MARx) ADDMAn Increment source pointer: MARx MARx + 2 Decrement DMA transfer count register: DTCRx DTCRx - 1 no DTCRx = 0? yes Set DMA transfer status bit: DMASx = 1 Generate interrupt signal (INTDMAx Note ) Note: DMA transfer completion interrupt has the same interrupt vector address as the corresponding A/D conversion completion interrupt (INTADn), and replaces that interrupt. Remark: 202 n = 0, 1 x=n (number of ADC channel) (number of DMA transfer channel) User's Manual U16580EE3V1UD00 Chapter 6 Figure 6-10: DMA Functions (DMA Controller) DMA Channel 0 and 1 Trigger Signal Timing Re-setup DTCRx, DMAMC register (write DEx bit = 1) Setup MARx, DTCRx, DMAMC register ADDMARQn DMA transfer MARx 1000H 1002H 1004H 1006H 1008H 100AH 100CH 100EH 1010H DTCRx 0003H 0002H 0001H 0000H 0000H 0003H 0002H 0001H 0000H INTADn Remarks: 1. The DMA request by ADDMARQ is disregarded after INTDMA is generated, and the DMA transfer is not restarted automatically. Write "1" in the corresponding DEx bit of the DMAMC register again to enable the next transfer of DMA channel x. The DEx bit is not cleared by hardware. 2. n = 0, 1 x=n (number of the A/D converter channel) (number of the DMA channel) User's Manual U16580EE3V1UD00 203 Chapter 6 DMA Functions (DMA Controller) 6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1) The DMAC has two dedicated channels to support DMA transfer for both PWM timers TMRn independently, DMA channel 2 for TMR0 and DMA channel 3 for TMR1. As DMA trigger factor, which requests and starts the DMA transfer, two corresponding timer interrupt signals are pre-defined (INTTRnOD or INTTRnCD). These are the same signals as for reloading the internal buffer compare registers by the contents of the capture/compare registers TRnCCRm (n = 0, 1)(m = 0 to 5). For each DMA trigger data will be transferred from internal RAM to the capture/compare registers of corresponding timer TMRn. The destination start address of the TMRn register (TRnCC0, TRnCC2 to TRnCC5) can be set up by the SARx register, as well as the source start address in the internal RAM by the MARx register. The destination end address is always fixed to TRnCC1 register, which also enables the buffer reload in the timer TMRn period (ref. to Table 6-1). The DMA transfer count is defined by the destination start and end address. However, an additionally DMA trigger count is available, which can be specified in the DTCRx register from 1 to 256. After decrementing the DTCRx register the DMAC will be prepared for a new DMA transfer from internal RAM to the timer TMRn registers until the DMA trigger count terminates (DTCRx register = 0). Table 6-1: Timer TMR Address Mapping for DMA Transfer DMA Transfer Destination Address TMRn registers Address Offset TRnCCR5 00H TRnCCR4 02H TRnCCR0 08H TRnCCR3 0AH TRnCCR2 0CH TRnCCR1 0EH Remark: 204 Selectable as start address Always end address n = 0, 1 m = 0 to 5 x=n+2 User's Manual U16580EE3V1UD00 DMA Transfer Source Address Any even address in internal RAM area Chapter 6 Figure 6-11: DMA Functions (DMA Controller) Initialization of DMA Transfer for TMRn Compare Registers Initialization of DMA transfer for TMRn compare registers (DMA channel 2 or 3) Set up SARx register with TMRn start address offset (TRnCCR0,TRnCCR2 to TRnCCR5) Set up the MARx register with source start address in iRAM Specify the DMA transfer count in the DTCRx register (1 to 256) Clear status bit of DMA channel x: DMASx bit = 0 Enable DMA transfer channel x: DEx bit = 1 End of initialization Remark: n = 0, 1 (number of TMR channel) x = n + 2 (number of DMA channel) User's Manual U16580EE3V1UD00 205 Chapter 6 DMA Functions (DMA Controller) Figure 6-12: Operation of DMA Channel 2/3 Operation of DMA channel 2/3 no DMA transfer will be enabled by write access to the corresponding DEn bit. DEx bit newly written ? yes no DEx bit = 1 ? yes no INTTRnOD occurred ? yes no INTTRnCD occurred ? yes Initialize destination pointer to 1st TMR compare register: m 2 SARx + Address of TRnCCR5 Transfer content from iRAM to TMRn compare register: (m) (MARx) Increment destination pointer: mm + 2 Increment source pointer: MARx MARx + 2 m > Address of TRnCCR0 ? no yes Decrement DMA transfer count register: DTCRx DTCRx - 1 no DTCRx = 0? yes Set DMA transfer status bit: DMASx = 1 Generate interrupt signal (INTDMAx) Remark: 206 n = 0, 1 (number of TMR channel) x = n + 2 (number of DMA transfer channel) User's Manual U16580EE3V1UD00 Chapter 6 Figure 6-13: DMA Functions (DMA Controller) DMA Channel 2 and 3 Trigger Signal Timing Setup MARx, DTCRx, SARx register INTTRnOD or INTTRnCD DMA transfer MARx 1000H 1002H SARx 04H 05H DTCRx 02H 1004H 06H 1006H 1008H 100AH 100EH 1010H 07H 04H 05 H 07H 04H 01H 0H INTDMAx Remarks: 1. The DMA request by INTTRnOD or INTTRnCD is disregarded after INTDMAx is generated, and the DMA transfer is not restarted automatically. Write "1" in the corresponding DEx bit of the DMAMC register again to enable the next transfer of DMA channel x. The DEx bit is not cleared by hardware. 2. n = 0, 1 x = n+2 (number of the TMR channel) (number of the DMA channel) User's Manual U16580EE3V1UD00 207 Chapter 6 DMA Functions (DMA Controller) 6.4.3 DMA transfer of serial interfaces (1) Serial data reception with DMA transfer The DMAC has two dedicated channels (4 and 5) to support the serial data reception. Each of both channels can be assigned to a serial interface (CSI30, CSI31Note, CSIB0, CSIB1Note, UARTC0, UARTC1). As DMA trigger factor, which requests and starts the DMA transfer, the corresponding interrupt signal at the end of reception is pre-defined (ref. to Table 6-2). For each DMA trigger the data will be transferred from the corresponding serial reception register to internal RAM. Depending on the serial interface the transfer data size can be set to 8 or 16 bits (refer to Table 6-2). In case of 8 bits transfer data size, the destination address is incremented by 1 for each occurrence of DMA trigger. When selecting 16 bits transfer data size the destination address must be even, and is incremented by 2 for each DMA trigger. When the DMA transfer count of a DMA channel terminates, the DMA transfer is stopped and a DMA completion interrupt is generated. The maximum DMA transfer count is 256. Table 6-2: Serial Interface DMA Trigger Factor CSI30 INTC30 CSI31Note CSIB0 CSIB1 Note UARTC0 UARTC1 INTC31 INTCB0T INTCB1T INTUC0T INTUC1T DMA Configuration of Serial Data Reception Transfer Data Size Source 8 bits SIRB0L Any iRAM address 16 bits SIRB0 Any even iRAM address 8 bits SIRB1L Any iRAM address 16 bits SIRB1 Any even iRAM address 8 bits CB0RXL Any iRAM address 16 bits CB0RX Any even iRAM address 8 bits CB1RXL Any iRAM address 16 bits CB1RX Any even iRAM address 8 bits UC0RX Any iRAM address 16 bits Setting prohibited 8 bits UC1RX 16 bits Setting prohibited Note: Not available on PD70F3447. 208 Destination User's Manual U16580EE3V1UD00 Any iRAM address Chapter 6 DMA Functions (DMA Controller) The procedure of the DMA transfer in case of serial data reception is shown in Figure 6-14. Figure 6-14: Initialization of DMA Transfer for Serial Data Reception Initialization of DMA transfer for serial data reception (DMA channel 4 or 5) Set up MARx register with the destination start address in iRAM Specify the DMA trigger factor in the DTFRx register depending on the used serial interface (CSI3n, CSIBn, UARTCn) Select the DMA transfer data size (8 or 16 bits) by the DMADSCx bit in the DMADSC register Specify the DMA transfer count in the DTCRx register (1 to 256) Clear status bit of DMA channel x: DMASx bit = 0 Enable DMA transfer channel x: DEx bit = 1 End of initialization Remark: n = 0, 1 x = 4, 5 (number of serial interface channel) (number of DMA channel) User's Manual U16580EE3V1UD00 209 Chapter 6 DMA Functions (DMA Controller) Figure 6-15: Operation of DMA Channel 4/5 Operation of DMA channel 4/5 no DEx bit newly written ? DMA transfer will be enabled by write access to the corresponding DEn bit. yes no DEx bit = 1 ? yes DMA trigger factor occurred ? no DMA trigger factor is the interrupt source specified by DTFRx register. yes yes (16 bit) DMADSCx bit = 1 ? no (8 bit) Transfer content from serial receive buffer (depending on DTFRx register) to iRAM : (MARx) SIRBn or CBnRX Transfer content from serial receive buffer (depending on DTFRx register) to iRAM : (MARx) SIRBnL, CBnRXL or UXnRX Increment source pointer: MARx MARx + 2 Increment source pointer: MARx MARx + 1 Decrement DMA transfer count register: DTCRx DTCRx - 1 no DTCRx = 0? yes Set DMA transfer status bit: DMASx = 1 Generate interrupt signal (INTDMAx Note ) Note: DMA transfer completion interrupt has the same interrupt vector address as the corresponding reception completion interrupt specified by DTFRX register, and replaces that interrupt. Remark: 210 n = 0, 1 x = 4, 5 (number of serial interface channel) (number of DMA transfer channel) User's Manual U16580EE3V1UD00 Chapter 6 Figure 6-16: DMA Functions (DMA Controller) DMA Channel 4 and 5 Trigger Signal Timing DTCRm, DMAMCm MARm, DTCRm, DTRFm, DMAMCm Trigger signal (by DTFRm register) DMA transfer MARm 1000H 1002H 1004H 1006H 1008H 100AH 100CH 100EH 1010H DTCRm 0003H 0002H 0001H 0000H 0000H 0003H 0002H 0001H 0000H INTUCnR or INTCBnR or INTCSI3n Remark: m = 4, 5 n = 0, 1 User's Manual U16580EE3V1UD00 211 Chapter 6 (2) DMA Functions (DMA Controller) Serial data transmission with DMA transfer The DMAC has two dedicated channels (6 and 7) to support the serial data transmission. Each of both channels can be assigned to a serial interface (CSI30, CSI31Note 1, CSIB0, CSIB1Note 1, UARTC0, UARTC1). As DMA trigger factor, which requests and starts the DMA transfer, the corresponding transmission enable interrupt signal is pre-defined (refer to Table 6-3). For each DMA trigger the data will be transferred from internal RAM to the corresponding serial transmit register. Depending on the serial interface the transfer data size can be set to 8 or 16 bits (refer to Table 6-3). In case of 8 bits transfer data size, the source address is incremented by 1 for each occurrence of DMA trigger. When selecting 16 bits transfer data size the source address must be even, and is incremented by 2 for each DMA trigger. When the DMA transfer count of a DMA channel terminates, the DMA transfer is stopped and a DMA completion interrupt is generated. The maximum DMA transfer count is 256. Table 6-3: Serial Interface DMA Trigger Factor CSI30Note 2 INTC30 CSI31Notes 1, 2 CSIB0 CSIB1Note 1 UARTC0 UARTC1 INTC31 INTCB0T INTCB1T INTUC0T INTUC1T DMA Configuration of Serial Data Transmission Transfer Data Size Source Destination 8 bits Any iRAM address SFDB0L 16 bits Any even iRAM address SFDB0 8 bits Any iRAM address SFDB1L 16 bits Any even iRAM address SFDB1 8 bits Any iRAM address CB0TXL 16 bits Any even iRAM address CB0TX 8 bits Any iRAM address CB1TXL 16 bits Any even iRAM address CB1TX 8 bits Any iRAM address UC0TX 16 bits Setting prohibited 8 bits Any iRAM address 16 bits Setting prohibited UC1TX Notes: 1. Not available on PD70F3447. 2. The serial peripheral chip select lines SCS0 to SCS3 will not be supported by DMA transfer. 212 User's Manual U16580EE3V1UD00 Chapter 6 DMA Functions (DMA Controller) The procedure of the DMA transfer in case of serial data transmission is shown in Figure 6-17. Figure 6-17: Initialization of DMA Transfer for Serial Data Transmission Initialization of DMA transfer for serial data transmission (DMA channel 6 or 7) Set up MARx register with the source start address in iRAM Specify the DMA trigger factor in the DTFRx register depending on the used serial interface (CSI3n, CSIBn, UARTCn) Select the DMA transfer data size (8 or 16 bits) by the DMADSCx bit in the DMADSC register Specify the DMA transfer count in the DTCRx register (1 to 256) Clear status bit of DMA channel x: DMASx bit = 0 Enable DMA transfer channel x: DEx bit = 1 End of initialization Remark: n = 0, 1 x = 6, 7 (number of serial interface channel) (number of DMA channel) User's Manual U16580EE3V1UD00 213 Chapter 6 Figure 6-18: DMA Functions (DMA Controller) DMA Channel 6 and 7 Trigger Signal Timing DTCRm, DMAMCm MARm, DTCRm, DTRFm, DMAMCm Trigger signal (by DTFRm register) DMA transfer MARm 1000H 1002H 1004H 1006H 1008H 100AH 100CH 100EH 1010H DTCRm 0003H 0002H 0001H 0000H 0000H 0003H 0002H 0001H 0000H INTUCnT or INTCBnT or INTCSI3n Remark: 214 m = 6, 7 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 6 DMA Functions (DMA Controller) Figure 6-19: Operation of DMA Channel 6/7 Operation of DMA channel 6/7 no DEx bit newly written ? DMA transfer will be enabled by write access to the corresponding DEn bit. yes no DEx bit = 1 ? yes DMA trigger factor occurred ? no DMA trigger factor is the interrupt source specified by DTFRx register. yes yes (16 bit) DMADSCx bit = 1 ? no (8 bit) Transfer content from iRAM to serial transmit buffer (spec. by DTFRx register): SFDBn or CBnTX (MARx) Transfer content from iRAM to serial transmit buffer (spec. by DTFRx register): SFDBnL, CBnTXL or UCnTX (MARx) Increment source pointer: MARx MARx + 2 Increment source pointer: MARx MARx + 1 Decrement DMA transfer count register: DTCRx DTCRx - 1 no DTCRx = 0? yes Set DMA transfer status bit: DMASx = 1 Generate interrupt signal (INTDMAx Note ) Note: DMA transfer completion interrupt has the same interrupt vector address as the corresponding transmission start interrupt specified by DTFRX register, and replaces that interrupt. Remark: n = 0, 1 x = 6, 7 (number of serial interface channel) (number of DMA transfer channel) User's Manual U16580EE3V1UD00 215 Chapter 6 DMA Functions (DMA Controller) 6.4.4 Forcible termination of DMA transfer A once started DMA transfer can be forcible terminated when the corresponding DEn bit in the DMAMC register is cleared (0). However, if the DEn bit is cleared while DMA transferring, an once started data transfer is stopped first after it has been finished (see Figure 6-20). Figure 6-20: CPU and DMA Controller Processing of DMA Transfer Termination (Example) CPU processing SAR2 = 0AH DTCR2 = 8 DMAS2 = 0 DE2 = 1 (DMA transfer channel 2 enabled) DMAC processing DMA trigger occurred (INTTR0CD) DMA transfer to TR0CCR3 DMA transfer to TR0CCR2 DMA transfer to TR0CCR1 DTCR2 =7 DMA trigger occurred (INTTR0CD) DE2 = 0 (DMA transfer channel 2 forcibly disabled) DMA transfer to TR0CCR3 DMA transfer to TR0CCR2 DMA transfer to TR0CCR1 DTCR2 = 6 No further DMA trigger (INTTR0CD) will be accepted 216 User's Manual U16580EE3V1UD00 Chapter 6 DMA Functions (DMA Controller) 6.5 DMA Interrupt Function The peripheral I/O interrupts of the A/D converters and the serial interfaces, which serve as DMA trigger factors, are shared with the DMA transfer completion interrupt of the corresponding channel n (INTDMAn) (n = 0, 1, 4 to 7). When a DMA channel is enabled the specified peripheral I/O interrupt is no longer applied to the interrupt controller. Instead of it the corresponding DMA transfer completion interrupt is applied to the appropriate interrupt handler address. In opposite to the other interrupts serving as DMA trigger factors, the TMR0 interrupts INTTR0OD and INTTR0CD, and the TMR1 interrupts INTTR1OD and INTTR1CD respectively, are not shared with DMA transfer completion interrupt of channel 2 (INTDMA2) and channel 3 (INTDMA3) respectively. These DMA completion interrupts have dedicated entries in the interrupt source list (refer to Table 7-1: "Interrupt/Exception Source List" on page 219). Table 6-4 shows the relations between DMA trigger factors and DMA completion interrupts. Table 6-4: DMA channel Relations Between DMA Trigger Factors and DMA Completion Interrupts DMA trigger factor DMA completion interrupt Name Handler Address 0 INTAD0 INTDMA0 INTAD0 00000670H Note 2 1 INTAD1 INTDMA1 INTAD1 00000680H Note 2 2 INTTR0CD or INTR0OD INTDMA2 INTDMA2 000006F0H 3 INTTR1CD or INTR1OD INTDMA3 INTDMA3 00000700H INTC30 INTDMA4, INTDMA5 INTC30 000005E0H Note 2 INTC31Note 1 00000600H Note 2 INTCB0R INTCB0R 00000580H Note 2 INTCB1RNote 1 INTCB1RNote 1 000005B0H Note 2 INTUC0R INTUC0R 00000620H Note 2 INTUC1R INTUC1R 00000650H Note 2 INTC30 000005E0H Note 2 INTC31Note 1 00000600H Note 2 INTCB0T 00000570H Note 2 000005A0H Note 2 4, 5 INTC31Note 1 6, 7 INTC30 INTC31Note 1 INTDMA6, INTDMA7 INTCB0T INTCB1T Notes: 1. Entry Remark Note 1 INTCIB1T Note 1 INTUC0T INTUC0T 00000630H Note 2 INTUC1T INTUC1T 00000660H Note 2 Not available on PD70F3447. 2. An interrupt request is not generated for a signal, which serves as DMA trigger factor. Instead of this the defined DMA completion interrupt request is executed on the same interrupt entry address of the DMA trigger factor. User's Manual U16580EE3V1UD00 217 Chapter 6 Figure 6-21: INTUC0R' INTUC1R' INTCB0R' Note INTCB1R' INTCSI30' Note INTCSI31' DMA Functions (DMA Controller) Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts INTUC0R' INTDMA4 INTUC0R DMA channel 4 INTUC1R' INTUC1R INTCB0R' INTDMA5 INTCB0R DMA channel 5 INTCB1R' Note INTCB1R Note INTCSI30' INTCSI30 INTCSI31' Note INTCSI31 Note INTUC0T' INTUC1T' INTCB0T' Note INTCB1T' INTCSI30' INTCSI31' Note INTUC0T' INTDMA6 INTUC0T DMA channel 6 INTUC1T' INTUC1T INTCB0T' INTCB0T INTDMA7 DMA channel 7 INTCB1T' Note INTCB1T Note INTCSI30' INTCSI31' Note Note: Not available on PD70F3447. Remark: 218 Interrupt signals with quote mark (') are signals, which are directly connected from the corresponding serial interface. Interrupt signals without quote mark are provided to the interrupt controller. User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function The V850E/PH2 microcontroller is provided with a dedicated interrupt controller (INTC) for interrupt servicing, which realizes a high-performance interrupt function that can service interrupt requests from a total of up to 107 sources. An interrupt is an event that occurs asynchronously (independently of program execution), and an exception is an event that occurs synchronously (dependently on program execution). Generally, an exception takes precedence over an interrupt. The V850E/PH2 microcontroller can process interrupt requests from the internal peripheral hardware and external sources. Moreover, exception processing can be started (exception trap) by the TRAP instruction (software exception) or by generation of an exception event (fetching of an illegal op code). 7.1 Features * Interrupts * Non-maskable interrupt: 1 source * Maskable interrupt: - 106 sources (PD70F3187) - 91 sources (PD70F3447) * 8 levels programmable priorities * Mask specification for the interrupt request according to priority * Mask can be specified to each maskable interrupt request. * Valid edge for detection of external interrupt request signal can be specified. * Exceptions * Software exceptions: 32 sources * Exception trap: 1 source (illegal op code exception) Interrupt/exception sources are listed in Table 7-1. Table 7-1: Type Classification Interrupt/Exception Source Name Reset Interrupt/Exception Source List (1/5) Interrupt RESET Control Register Generating Source Gener. Unit Default Exception Priority Code Handler Restored Address PC - RESET input Pin - 0000H 00000000H undefined NonInterrupt NMI maskable - NMI input Pin - 0010H 00000010H nextPC Software Exception TRAP0nNote exception Exception TRAP1nNote - TRAP instruction - - 004nHNote 00000040H nextPC - TRAP instruction - - 005nHNote 00000050H nextPC Exception Exception ILGOP/ trap DBTRAP - Illegal opcode/ DBTRAP instruction - - 0060H 00000060H nextPC Maskable Interrupt INTP0 PIC0 INTP0 valid edge input Pin 0 0080H 00000080H nextPC Interrupt INTP1 PIC1 INTP1 valid edge input Pin 1 0090H 00000090H nextPC Interrupt INTP2 PIC2 INTP2 valid edge input Pin 2 00A0H 000000A0H nextPC Interrupt INTP3 PIC3 INTP3 valid edge input Pin 3 00B0H 000000B0H nextPC Interrupt INTP4 PIC4 INTP4 valid edge input Pin 4 00C0H 000000C0H nextPC Note: n = 0 to FH User's Manual U16580EE3V1UD00 219 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Type Classification Interrupt/Exception Source Name Maskable Interrupt INTP5 Control Register PIC5 Generating Source Gener. Unit INTP5 valid edge input Pin Default Exception Priority Code 5 Handler Restored Address PC 00D0H 000000D0H nextPC Interrupt INTP6 PIC6 INTP6 valid edge input Pin 6 00E0H 000000E0H nextPC Interrupt INTP7 PIC7 INTP7 valid edge input Pin 7 00F0H 000000F0H nextPC Interrupt INTP8 PIC8 INTP8 valid edge input Pin 8 0100H 00000100H nextPC Interrupt INTP9 PIC9 INTP9 valid edge input Pin 9 0110H 00000110H nextPC Interrupt INTP10 PIC10 INTP10 valid edge input Pin 10 0120H 00000120H nextPC Interrupt INTP11 PIC11 INTP11 valid edge input Pin 11 0130H 00000130H nextPC Interrupt INTP12 PIC12 INTP12 valid edge input Pin 12 0140H 00000140H nextPC Interrupt INTTR0OV PIC13 TR0CNT overflow TMR0 13 0150H 00000150H nextPC Interrupt INTTR0CC0 PIC14 TR0CCR0 match TMR0 14 0160H 00000160H nextPC Interrupt INTTR0CC1 PIC15 TR0CCR1 match TMR0 15 0170H 00000170H nextPC Interrupt INTTR0CC2 PIC16 TR0CCR2 match TMR0 16 0180H 00000180H nextPC Interrupt INTTR0CC3 PIC17 TR0CCR3 match TMR0 17 0190H 00000190H nextPC Interrupt INTTR0CC4 PIC18 TR0CCR4 match TMR0 18 01A0H 000001A0H nextPC Interrupt INTTR0CC5 PIC19 TR0CCR5 match TMR0 19 01B0H 000001B0H nextPC Interrupt INTTR0CD TR0CNT top reversal TMR0 20 01C0H 000001C0H nextPC Interrupt INTTR0OD PIC21 TR0CNT bottom reversal TMR0 21 01D0H 000001D0H nextPC Interrupt INTTR0ER PIC22 TMR0 error detection TMR0 22 01E0H 000001E0H nextPC Interrupt INTTR1OV PIC23 TR1CNT overflow TMR1 23 01F0H 000001F0H nextPC Interrupt INTTR1CC0 PIC24 TIR10 capture input/ TR1CCR0 match TMR1 24 0200H 00000200H nextPC Interrupt INTTR1CC1 PIC25 TIR11 capture input/ TR1CCR1 match TMR1 25 0210H 00000210H nextPC Interrupt INTTR1CC2 PIC26 TIR12 capture input/ TR1CCR2 match TMR1 26 0220H 00000220H nextPC Interrupt INTTR1CC3 PIC27 TIR13 capture input/ TR1CCR3 match TMR1 27 0230H 00000230H nextPC Interrupt INTTR1CC4 PIC28 TR1CCR4 match TMR1 28 0240H 00000240H nextPC Interrupt INTTR1CC5 PIC29 TR1CCR5 match TMR1 29 0250H 00000250H nextPC Interrupt INTTR1CD TR1CNT top reversal TMR1 30 0260H 00000260H nextPC TR1CNT bottom reversal TMR1 31 0270H 00000270H nextPC PIC20 PIC30 Interrupt INTTR1OD PIC31 220 Interrupt/Exception Source List (2/5) Interrupt INTTR1ER PIC32 TMR1 error detection TMR1 32 0280H 00000280H nextPC Interrupt INTT0OV PIC33 TMT0 overflow TMT0 33 0290H 00000290H nextPC Interrupt INTT0CC0 PIC34 TIT00 capture input/ TT0CCR0 match TMT0 34 02A0H 000002A0H nextPC Interrupt INTT0CC1 PIC35 TIT01 capture input/ TT0CCR1 match TMT0 35 02B0H 000002B0H nextPC Interrupt INTT0EC PIC36 TMT0 encoder clear TMT0 36 02C0H 000002C0H nextPC Interrupt INTT1OV PIC37 TMT1 overflow TMT1 37 02D0H 000002D0H nextPC Interrupt INTT1CC0 PIC38 TIT10 capture input/ TT1CCR0 match TMT1 38 02E0H 000002E0H nextPC Interrupt INTT1CC1 PIC39 TIT11 capture input/ TT1CCR1 match TMT1 39 02F0H 000002F0H nextPC User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Type Classification Interrupt/Exception Source List (3/5) Interrupt/Exception Source Name Maskable Interrupt INTT1EC Control Register PIC40 Generating Source Gener. Unit Default Exception Priority Code Handler Restored Address PC TMT1 encoder clear TMT1 40 0300H 00000300H nextPC Interrupt INTP0OV PIC41 TMP0 overflow TMP0 41 0310H 00000310H nextPC Interrupt INTP0CC0 PIC42 TIP00 capture input/ TP0CCR0 match TMP0 42 0320H 00000320H nextPC Interrupt INTP0CC1 PIC43 TIP01 capture input/ TP0CCR1 match TMP0 43 0330H 00000330H nextPC Interrupt INTP1OV PIC44 TMP1 overflow TMP1 44 0340H 00000340H nextPC Interrupt INTP1CC0 PIC45 TIP10 pin/ TP1CCR0 match TMP1 45 0350H 00000350H nextPC Interrupt INTP1CC1 PIC46 TIP11 capture input/ TP1CCR1 match TMP1 46 0360H 00000360H nextPC Interrupt INTP2OV PIC47 TMP2 overflow TMP2 47 0370H 00000370H nextPC Interrupt INTP2CC0 PIC48 TIP20 capture input/ TP2CCR0 match TMP2 48 0380H 00000380H nextPC Interrupt INTP2CC1 PIC49 TIP21capture input/ TP2CCR1 match TMP2 49 0390H 00000390H nextPC Interrupt INTP3OV PIC50 TMP3 overflow TMP3 50 03A0H 000003A0H nextPC Interrupt INTP3CC0 PIC51 TIP30 capture input/ TP3CCR0 match TMP3 51 03B0H 000003B0H nextPC Interrupt INTP3CC1 PIC52 TIP31 capture input/ TP3CCR1 match TMP3 52 03C0H 000003C0H nextPC Interrupt INTP4OV PIC53 TMP4 overflow TMP4 53 03D0H 000003D0H nextPC Interrupt INTP4CC0 PIC54 TIP40 capture input/ TP4CCR0 match TMP4 54 03E0H 000003E0H nextPC Interrupt INTP4CC1 PIC55 TIP41 capture input/ TP4CCR1 match TMP4 55 03F0H 000003F0H nextPC Interrupt INTP5OV PIC56 TMP5overflow TMP5 56 0400H 00000400H nextPC Interrupt INTP5CC0 PIC57 TIP50 capture input/ TP5CCR0 match TMP5 57 0410H 00000410H nextPC Interrupt INTP5CC1 PIC58 TIP51 capture input/ TP5CCR1 match TMP5 58 0420H 00000420H nextPC Interrupt INTP6OV PIC59 TMP6 overflow TMP6 59 0430H 00000430H nextPC Interrupt INTP6CC0 PIC60 TIP60 capture input/ TP6CCR0 match TMP6 60 0440H 00000440H nextPC Interrupt INTP6CC1 PIC61 TIP61 capture input/ TP6CCR1 match TMP6 61 0450H 00000450H nextPC Interrupt INTP7OV PIC62 TMP7 overflow TMP7 62 0460H 00000460H nextPC Interrupt INTP7CC0 PIC63 TIP70 capture input/ TP7CCR0 match TMP7 63 0470H 00000470H nextPC Interrupt INTP7CC1 PIC64 TIP71 capture input/ TP7CCR1 match TMP7 64 0480H 00000480H nextPC Interrupt INTP8OV PIC65 TMP8 overflow TMP8 65 0490H 00000490H nextPC Interrupt INTP8CC0 PIC66 TP8CCR0 match TMP8 66 04A0H 000004A0H nextPC Interrupt INTP8CC1 PIC67 TP8CCR1 match TMP8 67 04B0H 000004B0H nextPC Interrupt INTBRG0 PIC68 BRG0 match BRG0 68 04C0H 000004C0H nextPC Interrupt INTBRG1 PIC69 BRG1 match BRG1 69 04D0H 000004D0H nextPC Interrupt INTBRG2 PIC70 BRG2 match BRG2 70 04E0H 000004E0H nextPC User's Manual U16580EE3V1UD00 221 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Type Classification Interrupt/Exception Source List (4/5) Interrupt/Exception Source Name Control Register Maskable Interrupt INTC0ERR PIC71 Generating Source FCAN0 error Default Exception Priority Code Handler Restored Address PC FCAN0 71 04F0H 000004F0H nextPC Interrupt INTC0WUP PIC72 FCAN0 wake up FCAN0 72 0500H 00000500H nextPC Interrupt INTC0REC PIC73 FCAN0 bus reception FCAN0 73 0510H 00000510H nextPC Interrupt INTC0TRX PIC74 FCAN0 bus transmission FCAN0 74 0520H 00000520H nextPC Interrupt INTC1ERR PIC75 FCAN1 error FCAN1 75 0530H 00000530H nextPC 76 0540H 00000540H nextPC 77 0550H 00000550H nextPC 78 0560H 00000560H nextPC Note Interrupt INTC1WUP PIC76 Note FCAN1 wake up Note Interrupt INTC1REC PIC77 Interrupt INTC1TRX PIC78 Note FCAN1 Note FCAN1 bus reception Note FCAN1 Note FCAN1 bus transmission FCAN1 Note Interrupt INTCB0T PIC79 CSIB0 transmission enable/ DMA transfer completion CSIB0/ DMAC 79 0570H 00000570H nextPC Interrupt INTCB0R PIC80 CSIB0 reception completion/ DMA transfer completion CSIB0/ DMAC 80 0580H 00000580H nextPC Interrupt INTCB0RE PIC81 CSIB0 receive error CSIB0 81 0590H 00000590H nextPC Interrupt INTCB1T PIC82 CSIB1 transmission enable/ DMA transfer completion CSIB1 82 05A0H 000005A0H nextPC CSIB1 reception completion/ DMA transfer completion CSIB1 83 05B0H 000005B0H nextPC 84 05C0H 000005C0H nextPC Note Interrupt INTCB1R PIC83 Note Interrupt INTCB1RE PIC84 CSIB1 receive error Note Note / DMAC Note / DMAC CSIB1 Note Interrupt INTC30OVF PIC85 CSI30 overrun CSI30 85 05D0H 000005D0H nextPC Interrupt INTC30 CSI30 transmission enable/ DMA transfer completion CSI30/ DMAC 86 05E0H 000005E0H nextPC CSI31 87 05F0H 000005F0H nextPC 88 0600H 00000600H nextPC PIC86 Interrupt INTC31OVF PIC87 CSI31 overrun Note Note CSI31 transmission enable/ DMA transfer completion CSI31 Interrupt INTUC0RE PIC89 UARTC0 receive error UARTC0 89 0610H 00000610H nextPC Interrupt INTUC0R PIC90 UARTC0 reception completion/ DMA transfer completion UARTC0 / DMAC 90 0620H 00000620H nextPC Interrupt INTUC0T PIC91 UARTC0 transmission enable/ DMA transfer completion UARTC0 / DMAC 91 0630H 00000630H nextPC Interrupt INTUC1RE PIC92 UARTC1receive error UARTC1 92 0640H 00000640H nextPC Interrupt INTUC1R PIC93 UARTC1 reception completion/ DMA transfer completion UARTC1 / DMAC 93 0650H 00000650H nextPC Interrupt INTUC1T PIC94 UARTC1 transmission enable/ DMA transfer completion UARTC1 / DMAC 94 0660H 00000660H nextPC Interrupt INTC31 PIC88 Note 222 Gener. Unit Note / DMAC User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Type Classification Interrupt/Exception Source List (5/5) Interrupt/Exception Source Name Maskable Interrupt INTAD1 Interrupt INTCC10 Control Register Interrupt INTCM10 Interrupt INTCM11 Interrupt INTOVF Interrupt INTUDF Gener. Unit PIC96 ADC1 conversion completion/ DMA transfer completion PIC97 CC10 capture input/ compare match Note Note CC11capture input/ compare match Note PIC99 CM10 compare match TMENC1 Note Interrupt INTCC11 Generating Source PIC98 Default Exception Priority Code Handler Restored Address PC ADC1/ DMAC 96 0680H 00000680H nextPC TMENC1 97 0690H 00000690H nextPC 98 06A0H 000006A0H nextPC 99 TMENC1 06B0H 000006B0H nextPC Note Note PIC100 CM10 compare match TMENC1 100 06C0H 000006C0H nextPC Note Note PIC101 TMENC1 overflow TMENC1 101 06D0H Note Note PIC102 TMENC1 underflow TMENC1 102 06E0H Note Note 000006D0H nextPC 000006E0H nextPC Interrupt INTDMA2 PIC103 DMA channel 2 transfer DMAC completion 103 06F0H 000006F0H nextPC Interrupt INTDMA3 PIC104 DMA channel 3 transfer DMAC completion 104 0700H 00000700H nextPC Interrupt INTPERR PIC105 Internal RAM parity error iRAM 105 0710H 00000710H nextPC Note: Not available on PD70F3447. Remarks: 1. Default Priority: The priority order that takes precedence when two or more maskable interrupt requests at the same software priority level are present at the same time. The highest priority is 0. Restored PC: The value of PC saved when an interrupt/exception (other than RESET) occurs is the value of the current PC, which holds the address of the next instruction to be executed when returning from interrupt handling routine. However, if the interrupt request occurs during execution of a divide instruction (DIV, DIVH, DIVU or DIVHU), the value of the PC saved is the address of the divide instruction itself (rather than the address of the instruction following the divide instruction), because the division is cancelled in this case, and restarted completely after interrupt servicing. nextPC: The PC value that proceeds the processing following interrupt/ exception processing. 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). User's Manual U16580EE3V1UD00 223 Chapter 7 Interrupt/Exception Processing Function 7.2 Non-maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. A NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin. When the valid edge specified by ESN0, ESN1 bits of the interrupt mode register 0 (INTM0) is detected at the NMI pin, the interrupt occurs. While the service program of the non-maskable interrupt is being executed (PSW.NP = 1), the acknowledgment of another non-maskable interrupt request is held pending. The pending NMI is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the RETI instruction). Note that if two or more NMI requests are input during the execution of the service program for a NMI, the number of NMIs that will be acknowledged after PSW.NP is cleared to 0 is only one. Remark: 224 PSW.NP: The NP bit of the PSW register. User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) (2) (3) (4) (5) Saves the restored PC to FEPC. Saves the current PSW to FEPSW. Writes exception code 0010H to the higher half-word (FECC) of ECR. Sets the NP and ID bits of the PSW and clears the EP bit. Sets the handler address (00000010H) corresponding to the non-maskable interrupt to the PC, and transfers control. The processing configuration of a non-maskable interrupt is shown in Figure 7-1. Figure 7-1: Processing Configuration of Non-Maskable Interrupt NMI input INTC acknowledgement Non-maskable interrupt request CPU processing PSW.NP 1 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC Restored PC PSW Exception code 1 0 1 NMI-Handler address Interrupt service Interrupt request pending User's Manual U16580EE3V1UD00 225 Chapter 7 Figure 7-2: Interrupt/Exception Processing Function Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while a NMI service program is being executed Main routine (PSW.NP = 1) NMI request NMI request NMI request held pending because PSW.NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while a NMI service program is being executed Main routine NMI request Held pending because NMI service program is being processed NMI request Held pending because NMI service program is being processed NMI request Only one NMI request is acknowledged even though two NMI requests are generated 226 User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.2.2 Restore Execution is restored from the non-maskable interrupt (NMI) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1. <2> Transfers control back to the address of the restored PC and PSW. Figure 7-3 illustrates how the RETI instruction is processed. Figure 7-3: RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution: When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non-maskable interrupt processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction. Remark: The solid line indicates the CPU processing flow. User's Manual U16580EE3V1UD00 227 Chapter 7 Interrupt/Exception Processing Function 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when a NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. Figure 7-4: Non-maskable Interrupt Status Flag (NP) 31 PSW 8 7 6 5 4 3 2 1 0 After reset 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z NP NMI Servicing Status 0 No NMI interrupt servicing 1 NMI interrupt currently servicing 7.2.4 Edge Detection Function The behaviour of the non-maskable interrupt (NMI) can be specified by the interrupt mode register 0 (INTM0). The valid edge of the external NMI pin input can be specified by the ESN0 and ESN1 bits. The INTM0 register can be read/written in 8-bit or 1-bit units. Figure 7-5: After reset: INTM0 228 NMI Edge Detection Specification: Interrupt Mode Register 0 (INTM0) 00H R/W Address: FFFFF880H 7 6 5 4 3 2 1 0 ES21 ES20 ES11 ES10 ES01 ES00 ESN1 ESN0 ESN1 ESN0 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges Valid Edge Specification of NMI pin input User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The PD70F3187 has 106 maskable interrupt sources and the PD70F3447 has 91 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). When an interrupt request has been acknowledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt processing routine, the interrupt enabled (EI) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. However, if multiple interrupts are executed, the following processing is necessary. (1) (2) Save EIPC and EIPSW in memory or a general-purpose register before executing the EI instruction. Execute the DI instruction before executing the RETI instruction, then reset EIPC and EIPSW with the values saved in (1). 7.3.1 Operation If a maskable interrupt occurs by INT input, the CPU performs the following processing, and transfers control to a handler routine: (1) (2) (3) (4) (5) Saves the restored PC to EIPC. Saves the current PSW to EIPSW. Writes an exception code to the lower half-word of ECR (EICC). Sets the ID bit of the PSW and clears the EP bit. Sets the handler address corresponding to each interrupt to the PC, and transfers control. The processing configuration of a maskable interrupt is shown in Figure 7-6. User's Manual U16580EE3V1UD00 229 Chapter 7 Interrupt/Exception Processing Function Figure 7-6: Maskable Interrupt Processing INT input INTC accepted xxIF = 1 No Yes xxMK = 0 Yes Priority higher than that of interrupt currently being processed? No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request Interrupt request held pending CPU processing PSW.NP 1 0 PSW.ID 1 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID Corresponding bit of ISPRNote PC restored PC PSW exception code 0 1 1 Interrupt request held pending handler address Interrupt processing Note: For the ISPR register, see 7.3.6 "In-service priority register (ISPR)" on page 242. An INT input masked by the interrupt controllers and an INT input that occurs while another interrupt is being processed (when PSW.NP = 1 or PSW.ID = 1) are held pending internally by the interrupt controller. In such case, if the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by the RETI and LDSR instructions, input of the pending INT starts the new maskable interrupt processing. 230 User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) (2) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0. Transfers control to the address of the restored PC and PSW. Figure 7-7 illustrates the processing of the RETI instruction. Figure 7-7: RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Restores original processing Note: For the ISPR register, see 7.3.6 "In-service priority register (ISPR)" on page 242. Caution: When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during maskable interrupt processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction. Remark: The solid lines show the CPU processing flow. User's Manual U16580EE3V1UD00 231 Chapter 7 Interrupt/Exception Processing Function 7.3.3 Priorities of maskable interrupts The V850E/PH2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (PRn) of the interrupt control register (PICn). When two or more interrupts having the same priority level specified by the PRn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. For more information, refer to Table 7-1, "Interrupt/Exception Source List," on page 219. The programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request is acknowledged, the ID flag of PSW is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode. Remark: 232 n = 0 to 105 (number of interrupt) User's Manual U16580EE3V1UD00 Chapter 7 Figure 7-8: Interrupt/Exception Processing Function Example of Processing in which Another Interrupt Request Is Issued while an Interrupt is being Processed (1/2) Main routine Processing of a EI Interrupt request a (level 3) Processing of b EI Interrupt request b (level 2) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Processing of c Interrupt request c (level 3) Interrupt request d (level 2) Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Processing of d Processing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Processing of f Processing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Processing of h Caution: The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks: 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt requests. User's Manual U16580EE3V1UD00 233 Chapter 7 Figure 7-8: Interrupt/Exception Processing Function Example of Processing in which Another Interrupt Request Is Issued while an Interrupt is being Processed (2/2) Main routine Processing of i EI Interrupt request i (level 2) Processing of k EI Interrupt request j (level 3) Interrupt request k (level 1) Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Processing of j Processing of l Interrupt request l (level 2) Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request m (level 3) Interrupt request n (level 1) Processing of n Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Processing of m Interrupt request o (level 3) Processing of o Processing of p Processing of q EI Processing of r EI Interrupt EI Interrupt request p (level 2) request q (level 1) Interrupt request r (level 0) If levels 3 to 0 are acknowledged Processing of s Interrupt request s (level 1) Interrupt request t (level 2) Interrupt request u (level 2) Note 1 Note 2 Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Processing of u Processing of t Notes: 1. Lower default priority 2. Higher default priority Caution: 234 The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. User's Manual U16580EE3V1UD00 Chapter 7 Figure 7-9: Interrupt/Exception Processing Function Example of Processing Interrupt Requests Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Default priority a>b>c Processing of interrupt request b Processing of interrupt request c . . Interrupt request b and c are acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first according to the default priority. Processing of interrupt request a Caution: The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. User's Manual U16580EE3V1UD00 235 Chapter 7 Interrupt/Exception Processing Function 7.3.4 Interrupt control register (PICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Figure 7-10: After reset: PICn 47H Interrupt Control Register (PICn) R/W Address: Refer to Table 7-2 7 6 5 4 3 2 1 0 IFn MKn 0 0 0 PRn2 PRn1 PRn0 IFn Interrupt Request Flag nNote 0 Interrupt request is not issued 1 Interrupt request issued MKn Interrupt Mask Flag n 0 Interrupt servicing enabled 1 Interrupt servicing disabled (IFn flag hold pending) PRn2 PRn1 PRn0 Interrupt Priority Specification n 0 0 0 Specifies level 0 (highest) 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Specifies level 4 1 0 1 Specifies level 5 1 1 0 Specifies level 6 1 1 1 Specifies level 7 (lowest) Note: Automatically reset by hardware when interrupt request is acknowledged. Remark: 236 n = 0 to 105 (see Table 7-2: Addresses and Bits of Interrupt Control Registers) User's Manual U16580EE3V1UD00 Chapter 7 Table 7-2: Address Interrupt/Exception Processing Function Addresses and Bits of Interrupt Control Registers (1/3) Register Bit 7 6 5 4 3 2 1 0 Associated Interrupt FFFFF110H PIC0 IF0 MK0 0 0 0 PR02 PR01 PR00 INTP0 FFFFF112H PIC1 IF1 MK1 0 0 0 PR12 PR11 PR10 INTP1 FFFFF114H PIC2 IF2 MK2 0 0 0 PR22 PR21 PR20 INTP2 FFFFF116H PIC3 IF3 MK3 0 0 0 PR32 PR31 PR30 INTP3 FFFFF118H PIC4 IF4 MK4 0 0 0 PR42 PR41 PR40 INTP4 FFFFF11AH PIC5 IF5 MK5 0 0 0 PR52 PR51 PR50 INTP5 FFFFF11CH PIC6 IF6 MK6 0 0 0 PR62 PR61 PR60 INTP6 FFFFF11EH PIC7 IF7 MK7 0 0 0 PR72 PR71 PR70 INTP7 FFFFF120H PIC8 IF8 MK8 0 0 0 PR82 PR81 PR80 INTP8 FFFFF122H PIC9 IF9 MK9 0 0 0 PR92 PR91 PR90 INTP9 FFFFF124H PIC10 IF10 MK10 0 0 0 PR102 PR101 PR100 INTP10 FFFFF126H PIC11 IF11 MK11 0 0 0 PR112 PR111 PR110 INTP11 FFFFF128H PIC12 IF12 MK12 0 0 0 PR122 PR121 PR120 INTP12 FFFFF12AH PIC13 IF13 MK13 0 0 0 PR132 PR131 PR130 INTTR0OV FFFFF12CH PIC14 IF14 MK14 0 0 0 PR142 PR141 PR140 INTTR0CC0 FFFFF12EH PIC15 IF15 MK15 0 0 0 PR152 PR151 PR150 INTTR0CC1 FFFFF130H PIC16 IF16 MK16 0 0 0 PR162 PR161 PR160 INTTR0CC2 FFFFF132H PIC17 IF17 MK17 0 0 0 PR172 PR171 PR170 INTTR0CC3 FFFFF134H PIC18 IF18 MK18 0 0 0 PR182 PR181 PR180 INTTR0CC4 FFFFF136H PIC19 IF19 MK19 0 0 0 PR192 PR191 PR190 INTTR0CC5 FFFFF138H PIC20 IF20 MK20 0 0 0 PR202 PR201 PR200 INTTR0CD FFFFF13AH PIC21 IF21 MK21 0 0 0 PR212 PR211 PR210 INTTR0OD FFFFF13CH PIC22 IF22 MK22 0 0 0 PR222 PR221 PR220 INTTR0ER FFFFF13EH PIC23 IF23 MK23 0 0 0 PR232 PR231 PR230 INTTR1OV FFFFF140H PIC24 IF24 MK24 0 0 0 PR242 PR241 PR240 INTTR1CC0 FFFFF142H PIC25 IF25 MK25 0 0 0 PR252 PR251 PR250 INTTR1CC1 FFFFF144H PIC26 IF26 MK26 0 0 0 PR262 PR261 PR260 INTTR1CC2 FFFFF146H PIC27 IF27 MK27 0 0 0 PR272 PR271 PR270 INTTR1CC3 FFFFF148H PIC28 IF28 MK28 0 0 0 PR282 PR281 PR280 INTTR1CC4 FFFFF14AH PIC29 IF29 MK29 0 0 0 PR292 PR291 PR290 INTTR1CC5 FFFFF14CH PIC30 IF30 MK30 0 0 0 PR302 PR301 PR300 INTTR1CD FFFFF14EH PIC31 IF31 MK31 0 0 0 PR312 PR311 PR310 INTTR1OD FFFFF150H PIC32 IF32 MK32 0 0 0 PR322 PR321 PR320 INTTR1ER FFFFF152H PIC33 IF33 MK33 0 0 0 PR332 PR331 PR330 INTT0OV FFFFF154H PIC34 IF34 MK34 0 0 0 PR342 PR341 PR340 INTT0CC0 FFFFF156H PIC35 IF35 MK35 0 0 0 PR352 PR351 PR350 INTT0CC1 FFFFF158H PIC36 IF36 MK36 0 0 0 PR362 PR361 PR360 INTT0EC FFFFF15AH PIC37 IF37 MK37 0 0 0 PR372 PR371 PR370 INTT1OV FFFFF15CH PIC38 IF38 MK38 0 0 0 PR382 PR381 PR380 INTT1CC0 FFFFF15EH PIC39 IF39 MK39 0 0 0 PR392 PR391 PR390 INTT1CC1 User's Manual U16580EE3V1UD00 237 Chapter 7 Table 7-2: Address Interrupt/Exception Processing Function Addresses and Bits of Interrupt Control Registers (2/3) Register Bit 7 6 5 4 3 2 1 0 Associated Interrupt FFFFF160H PIC40 IF40 MK40 0 0 0 PR402 PR401 PR400 INTT1EC FFFFF162H PIC41 IF41 MK41 0 0 0 PR412 PR411 PR410 INTP0OV FFFFF164H PIC42 IF42 MK42 0 0 0 PR422 PR421 PR420 INTP0CC0 FFFFF166H PIC43 IF43 MK43 0 0 0 PR432 PR431 PR430 INTP0CC1 FFFFF168H PIC44 IF44 MK44 0 0 0 PR442 PR441 PR440 INTP1OV FFFFF16AH PIC45 IF45 MK45 0 0 0 PR452 PR451 PR450 INTP1CC0 FFFFF16CH PIC46 IF46 MK46 0 0 0 PR462 PR461 PR460 INTP1CC1 FFFFF16EH PIC47 IF47 MK47 0 0 0 PR472 PR471 PR470 INTP2OV FFFFF170H PIC48 IF48 MK48 0 0 0 PR482 PR481 PR480 INTP2CC0 FFFFF172H PIC49 IF49 MK49 0 0 0 PR492 PR491 PR490 INTP2CC1 FFFFF174H PIC50 IF50 MK50 0 0 0 PR502 PR501 PR500 INTP3OV FFFFF176H PIC51 IF51 MK51 0 0 0 PR512 PR511 PR510 INTP3CC0 FFFFF178H PIC52 IF52 MK52 0 0 0 PR522 PR521 PR520 INTP3CC1 FFFFF17AH PIC53 IF53 MK53 0 0 0 PR532 PR531 PR530 INTP4OV FFFFF17CH PIC54 IF54 MK54 0 0 0 PR542 PR541 PR540 INTP4CC0 FFFFF17EH PIC55 IF55 MK55 0 0 0 PR552 PR551 PR550 INTP4CC1 FFFFF180H PIC56 IF56 MK56 0 0 0 PR562 PR561 PR560 INTP5OV FFFFF182H PIC57 IF57 MK57 0 0 0 PR572 PR571 PR570 INTP5CC0 FFFFF184H PIC58 IF58 MK58 0 0 0 PR582 PR581 PR580 INTP5CC1 FFFFF186H PIC59 IF59 MK59 0 0 0 PR592 PR591 PR590 INTP6OV FFFFF188H PIC60 IF60 MK60 0 0 0 PR602 PR601 PR600 INTP6CC0 FFFFF18AH PIC61 IF61 MK61 0 0 0 PR612 PR611 PR610 INTP6CC1 FFFFF18CH PIC62 IF62 MK62 0 0 0 PR622 PR621 PR620 INTP7OV FFFFF18EH PIC63 IF63 MK63 0 0 0 PR632 PR631 PR630 INTP7CC0 FFFFF190H PIC64 IF64 MK64 0 0 0 PR642 PR641 PR640 INTP7CC1 FFFFF192H PIC65 IF65 MK65 0 0 0 PR652 PR651 PR650 INTP8OV FFFFF194H PIC66 IF66 MK66 0 0 0 PR662 PR661 PR660 INTP8CC0 FFFFF196H PIC67 IF67 MK67 0 0 0 PR672 PR671 PR670 INTP8CC1 FFFFF198H PIC68 IF68 MK68 0 0 0 PR682 PR681 PR680 INTBRG0 FFFFF19AH PIC69 IF69 MK69 0 0 0 PR692 PR691 PR690 INTBRG1 FFFFF19CH PIC70 IF70 MK70 0 0 0 PR702 PR701 PR700 INTBRG2 FFFFF19EH PIC71 IF71 MK71 0 0 0 PR712 PR711 PR710 INTC0ERR FFFFF1A0H PIC72 IF72 MK72 0 0 0 PR722 PR721 PR720 INTC0WUP FFFFF1A2H PIC73 IF73 MK73 0 0 0 PR732 PR731 PR730 INTC0REC FFFFF1A4H PIC74 IF74 MK74 0 0 0 PR742 PR741 PR740 INTC0TRX FFFFF1A6H PIC75 IF75 MK75 0 0 0 PR752 PR751 PR750 INTC1ERR Note FFFFF1A8H PIC76 Note IF76 MK76 0 0 0 PR762 PR761 Note FFFFF1AAH PIC77 Note IF77 MK77 0 0 0 PR772 Note 238 PR760 INTC1WUP PR771 PR770 INTC1REC Note User's Manual U16580EE3V1UD00 Chapter 7 Table 7-2: Address FFFFF1ACH Interrupt/Exception Processing Function Addresses and Bits of Interrupt Control Registers (3/3) Register PIC78 Bit 7 6 5 4 3 2 1 IF78 MK78 0 0 0 PR782 PR781 Note 0 Associated Interrupt PR780 INTC1TRX Note FFFFF1AEH PIC79 IF79 MK79 0 0 0 PR792 PR791 PR790 INTCB0T FFFFF1B0H PIC80 IF80 MK80 0 0 0 PR802 PR801 PR800 INTCB0R FFFFF1B2H PIC81 IF81 MK81 0 0 0 PR812 PR811 PR810 INTCB0RE FFFFF1B4H PIC82 IF82 MK82 0 0 0 PR822 PR821 PR820 INTCB1T Note Note FFFFF1B6H PIC83 IF83 Note MK83 0 0 0 PR832 PR831 Note FFFFF1B8H PIC84 PR830 INTCB1R Note IF84 MK84 0 0 0 PR842 PR841 Note PR840 INTCB1RE Note FFFFF1BAH PIC85 IF85 MK85 0 0 0 PR852 PR851 PR850 INTC30OVF FFFFF1BCH PIC86 IF86 MK86 0 0 0 PR862 PR861 PR860 INTC30 PIC87 IF87 MK87 0 0 0 PR872 PR871 PR870 INTC31OVF FFFFF1BEH Note FFFFF1C0H PIC88 Note IF88 MK88 0 0 0 PR882 PR881 Note PR880 INTC31 Note FFFFF1C2H PIC89 IF89 MK89 0 0 0 PR892 PR891 PR890 INTUC0RE FFFFF1C4H PIC90 IF90 MK90 0 0 0 PR902 PR901 PR900 INTUC0R FFFFF1C6H PIC91 IF91 MK91 0 0 0 PR912 PR911 PR910 INTUC0T FFFFF1C8H PIC92 IF92 MK92 0 0 0 PR922 PR921 PR920 INTUC1RE FFFFF1CAH PIC93 IF93 MK93 0 0 0 PR932 PR931 PR930 INTUC1R FFFFF1CCH PIC94 IF94 MK94 0 0 0 PR942 PR941 PR940 INTUC1T FFFFF1CEH PIC95 IF95 MK95 0 0 0 PR952 PR951 PR950 INTAD0 FFFFF1D0H PIC96 IF96 MK96 0 0 0 PR962 PR961 PR960 INTAD1 FFFFF1D2H PIC97 IF97 MK97 0 0 0 PR972 PR971 PR970 INTCC10 IF98 MK98 0 0 0 PR982 PR981 PR980 INTCC11 Note FFFFF1D4H PIC98 Note Note FFFFF1D6H PIC99 Note IF99 MK99 0 0 0 PR992 Note FFFFF1D8H PIC100 PIC101 IF100 MK100 0 0 0 PR1002 PR1001 PR1000 INTCM11 Note IF101 MK101 0 0 0 PR1012 PR1011 PR1010 INTOVF Note FFFFF1DCH PIC102 PR990 INTCM10 Note Note FFFFF1DAH PR991 Note IF102 MK102 0 0 0 PR1022 PR1021 PR1020 INTUDF Note Note FFFFF1DEH PIC103 IF103 MK103 0 0 0 PR1032 PR1031 PR1030 INTDMA2 FFFFF1E0H PIC104 IF104 MK104 0 0 0 PR1042 PR1041 PR1040 INTDMA3 FFFFF1E2H PIC105 IF105 MK105 0 0 0 PR1052 PR1051 PR1050 INTPERR Note: Not available on PD70F3447. User's Manual U16580EE3V1UD00 239 Chapter 7 Interrupt/Exception Processing Function 7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6) The IMR0 to IMR6 registers set the interrupt mask state for the maskable interrupts. The IMK0 to IMK104 bits are equivalent to the MKn bit in the corresponding PICn register. The IMRm register (m = 0 to 6) can be read or written in 16-bit units. If the higher 8 bits of the IMRm register are used as the IMRmH register and the lower 8 bits as the IMRmL register, these registers can be read or written in 8-bit or 1-bit units. Reset input sets these registers to FFFFH. Bits 15 to 9 of the IMR6 register (bits 7 to 1 of the IMR6H register) are fixed to 1. If these bits are not 1, the operation cannot be guaranteed. Caution: The device file defines the MKn bit as a reserved word. If a bit is manipulated using the name of MKn, the contents of the PICn register, instead of the IMRm register, are rewritten (as a result, the contents of the IMRm register are also rewritten). Figure 7-11: After reset: IMR0 Address: 13 12 11 10 9 8 MK15 MK14 MK13 MK12 MK11 MK10 MK9 MK8 7 6 5 4 3 2 1 0 MK7 MK6 MK5 MK4 MK3 MK2 MK1 MK0 FFFFH R/W Address: 240 IMR1 FFFFF102H IMR1L FFFFF102H, IMR1H FFFFF103H 15 14 13 12 11 10 9 8 MK31 MK30 MK29 MK28 MK27 MK26 MK25 MK24 7 6 5 4 3 2 1 0 MK23 MK22 MK21 MK20 MK19 MK18 MK17 MK16 FFFFH R/W Address: IMR2 FFFFF104H IMR2L FFFFF104H, IMR2H FFFFF105H 15 14 13 12 11 10 9 8 MK47 MK46 MK45 MK44 MK43 MK42 MK41 MK40 7 6 5 4 3 2 1 0 MK39 MK38 MK37 MK36 MK35 MK34 MK33 MK32 IMKn Remark: IMR0 FFFFF100H IMR0L FFFFF100H, IMR0H FFFFF101H 14 After reset: IMR2 R/W 15 After reset: IMR1 FFFFH Interrupt Mask Registers 0 to 2 (IMR0 to IMR2) Interrupt Mask Flag 0 Enable interrupt servicing 1 Disable interrupt servicing (pending) n = 0 to 105 (see Table 7-1) User's Manual U16580EE3V1UD00 Chapter 7 Figure 7-12: After reset: IMR3 R/W Address: IMR3 FFFFF106H IMR3L FFFFF106H, IMR3H FFFFF107H 14 13 12 11 10 9 8 MK63 MK62 MK61 MK60 MK59 MK58 MK57 MK56 MK55 MK54 MK53 MK52 MK51 MK50 MK49 MK48 FFFFH R/W Address: IMR4 FFFFF108H IMR4L FFFFF108H, IMR4H FFFFF109H 15 14 13 12 11 10 9 8 MK79 MK78 MK77 MK76 MK75 MK74 MK73 MK72 Note Note Note Note MK70 MK69 MK68 MK67 MK66 MK65 MK64 MK71 After reset: IMR5 Interrupt Mask Registers 3 to 6 (IMR3 to IMR6) 15 After reset: IMR4 FFFFH Interrupt/Exception Processing Function FFFFH R/W Address: IMR5 FFFFF10AH IMR5L FFFFF10AH, IMR5H FFFFF10BH 15 14 13 12 11 10 9 8 MK95 MK94 MK93 MK92 MK91 MK90 MK89 MK88 Note MK87 MK86 MK85 MK84 MK83 MK82 Note Note Note Note After reset: IMR6 FFFFH R/W Address: MK81 MK80 IMR6 FFFFF10CH IMR6L FFFFF10CH, IMR6H FFFFF10DH 15 14 13 12 11 10 9 8 1 1 1 1 1 1 MK105 MK104 MK103 MK102 MK101 MK100 MK99 MK98 MK97 MK96 Note Note Note Note Note Note Note: The reset value (1) of these mask bits should be kept for PD70F3447 at any time. IMKn Remark: Interrupt Mask Flag 0 Enable interrupt servicing 1 Disable interrupt servicing (pending)Note n = 0 to 105 (see Table 7-1) Note: Not available on PD70F3447. User's Manual U16580EE3V1UD00 241 Chapter 7 Interrupt/Exception Processing Function 7.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. Reset input clears this register to 00H. This register is read-only, in 8-bit or 1-bit units. Caution: In the interrupt enabled (EI) state, if an interrupt is acknowledged during the reading of the ISPR register, the value of the ISPR register may be read after the bit is set (1) by this interrupt acknowledgment. To read the value of the ISPR register properly before interrupt acknowledgment, read it in the interrupt disabled (DI) state. Figure 7-13: After reset: ISPR 00H R 242 Address: FFFFF1FAH 7 6 5 4 3 2 1 0 ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 ISPRn Remark: Interrupt Service Priority Register (ISPR) Priority of Interrupt Currently Being Acknowledged 0 Interrupt request with priority n is not acknowledged 1 Interrupt request with priority n is being acknowledged n = 0 to 7 (priority level) User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and controls the maskable interrupt's operating state, and stores control information regarding enabling or disabling of interrupt requests. Figure 7-14: Maskable interrupt status flag (ID) 31 PSW 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z ID After reset 00000020H Maskable Interrupt Servicing SpecificationNote 0 Maskable interrupt request acknowledgment enabled 1 Maskable interrupt request acknowledgment disabled (pending) Note: Interrupt disable flag (ID) function * This flag is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. * Non-maskable interrupt and exceptions are acknowledged regardless of this flag. When a maskable interrupt is acknowledged, the ID flag is automatically set to 1 by hardware. * The interrupt request generated during the acknowledgement disabled period (ID = 1) can be acknowledged when the IFn bit of the interrupt control register PICn is set to 1, and the ID flag is reset to 0. User's Manual U16580EE3V1UD00 243 Chapter 7 Interrupt/Exception Processing Function 7.3.8 Interrupt trigger mode selection The valid edge of the maskable external interrupt input pin (INTPn) can be selected by program (n = 0 to 12). The edge that can be selected as the valid edge is one of the following. * Rising edge * Falling edge * Both, the rising and falling edges The edge-detected INTPn signal becomes an interrupt source. The valid edge is specified by interrupt mode registers 0 to 3 (INTM0 to INTM3) 244 User's Manual U16580EE3V1UD00 Chapter 7 (1) Interrupt/Exception Processing Function Interrupt mode register 0 (INTM0) The behaviour of the external interrupt input pins INTP0 to INTP2 can be specified by the interrupt mode register 0 (INTM0). The INTM0 register can be read/written in 8-bit or 1-bit units. Figure 7-15: After reset: INTM0 Caution: 00H Interrupt Mode Register 0 (INTM0) R/W Address: FFFFF880H 7 6 5 4 3 2 1 0 ES21 ES20 ES11 ES10 ES01 ES00 ESN1 ESN0 ES21 ES20 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES11 ES10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ESN1 ESN0 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges Valid Edge Specification of INTP2 pin input Valid Edge Specification of INTP1 pin input Valid Edge Specification of INTP0 pin input Valid Edge Specification of NMI pin input Changing the state of interrupt mode configuration registers ESn0/ESn1 may trigger an unintended interrupt event for the respective interrupt channels. Be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits ESn0/ESn1 of the interrupt channel (n = 0 to 2). User's Manual U16580EE3V1UD00 245 Chapter 7 (2) Interrupt/Exception Processing Function Interrupt mode register 1 (INTM1) The behaviour of the external interrupt input pins INTP3 to INTP6 can be specified by the interrupt mode register 1 (INTM1). The INTM1 register can be read/written in 8-bit or 1-bit units. Figure 7-16: After reset: INTM1 Caution: 246 00H Interrupt Mode Register 1 (INTM1) R/W Address: FFFFF882H 7 6 5 4 3 2 1 0 ES61 ES60 ES51 ES50 ES41 ES40 ES31 ES30 ES61 ES60 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES51 ES50 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES41 ES40 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES31 ES30 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges Valid Edge Specification of INTP6 pin input Valid Edge Specification of INTP5 pin input Valid Edge Specification of INTP4 pin input Valid Edge Specification of INTP4 pin input Changing the state of interrupt mode configuration registers ESn0/ESn1 may trigger an unintended interrupt event for the respective interrupt channels. Be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits ESn0/ESn1 of the interrupt channel (n = 3 to 6). User's Manual U16580EE3V1UD00 Chapter 7 (3) Interrupt/Exception Processing Function Interrupt mode register 2 (INTM2) The behaviour of the external interrupt input pins INTP7 to INTP10 can be specified by the interrupt mode register 2 (INTM2). The INTM2 register can be read/written in 8-bit or 1-bit units. Figure 7-17: After reset: INTM1 Caution: 00H Interrupt Mode Register 2 (INTM2) R/W Address: FFFFF884H 7 6 5 4 3 2 1 0 ES101 ES100 ES91 ES90 ES81 ES80 ES71 ES70 ES101 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES91 ES90 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES81 ES80 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES71 ES70 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges Valid Edge Specification of INTP10 pin input Valid Edge Specification of INTP9 pin input Valid Edge Specification of INTP8 pin input Valid Edge Specification of INTP7 pin input Changing the state of interrupt mode configuration registers ESn0/ESn1 may trigger an unintended interrupt event for the respective interrupt channels. Be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits ESn0/ESn1 of the interrupt channel (n = 7 to 10). User's Manual U16580EE3V1UD00 247 Chapter 7 (4) Interrupt/Exception Processing Function Interrupt mode register 3 (INTM3) The behaviour of the external interrupt input pins INTP11 and INTP12 can be specified by the interrupt mode register 3 (INTM3). The INTM3 register can be read/written in 8-bit or 1-bit units. Figure 7-18: After reset: INTM1 Caution: 248 00H Interrupt Mode Register 3 (INTM3) R/W Address: FFFFF886H 7 6 5 4 3 2 1 0 0 0 0 0 ES121 ES120 ES111 ES110 ES121 ES120 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges ES111 ES110 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges Valid Edge Specification of INTP12 pin input Valid Edge Specification of INTP11 pin input Changing the state of interrupt mode configuration registers ESn0/ESn1 may trigger an unintended interrupt event for the respective interrupt channels. Be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits ESn0/ESn1 of the interrupt channel (n = 11, 12). User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and is always accepted. For details of the instruction function, refer to the V850 Family User's Manual Architecture. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: <1> <2> <3> <4> <5> Saves the current PC to EIPC. Saves the current PSW to EIPSW. Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). Sets the EP and ID bits of PSW. Loads the handler address (00000040H or 00000050H) of the software exception routine in the PC, and transfers control. The processing of a software exception is shown below. Figure 7-19: Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC restored PC PSW exception code 1 1 handler address Exception processing Note: TRAP instruction format: TRAP vector (the vector is a value from 0 to 1FH.) The handler address is determined by the TRAP instruction's operand (vector). If the vector is 0 to 0FH, it becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H. User's Manual U16580EE3V1UD00 249 Chapter 7 Interrupt/Exception Processing Function 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 7-20: RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution: When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the software exception process, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 using the LDSR instruction immediately before the RETI instruction. Remark: The solid line shows the CPU processing flow. 250 User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function 7.4.3 Exception status flag (EP) The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. This flag is set when an exception occurs. Figure 7-21: Exception Status Flag (EP) 31 PSW 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z EP After reset 00000020H Exception Processing Status 0 Exception processing not in progress 1 Exception processing in progress User's Manual U16580EE3V1UD00 251 Chapter 7 Interrupt/Exception Processing Function 7.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850E/PH2, an illegal opcode trap (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 1000B to 1111B, and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal instruction is executed. Figure 7-22: 15 11 10 xxxxx 5 4 1 1 1 1 1 1 Illegal Opcode 0 31 27 26 xxxxxxxxxx 23 22 1 0 0 0 to 1 1 1 1 xxxxxx 16 0 Caution: Caution Since it is possible that this instruction may be assigned to an illegal opcode in the future, it is recommended that it not be used. Remark: x: don't care (1) Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> <2> <3> <4> Saves the restored PC to DBPC. Saves the current PSW to DBPSW. Sets the PSW.NP, PSW.EP, and PSW.ID bits. Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control. Figure 7-23 illustrates the processing of the exception trap. 252 User's Manual U16580EE3V1UD00 Chapter 7 Interrupt/Exception Processing Function Figure 7-23: Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC restored PC PSW 1 1 1 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW. Figure 7-24 illustrates the restore processing from an exception trap. Figure 7-24: Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC User's Manual U16580EE3V1UD00 253 Chapter 7 Interrupt/Exception Processing Function 7.6 Periods in Which CPU Does Not Acknowledge Interrupts The CPU acknowledges an interrupt while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows. * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (for PSW) * The store instruction for the command register (PRCMD) * The store, or bit manipulation instructions excluding the tst1 instruction for the following interruptrelated registers: - Interrupt control register (PICn) - Interrupt mask registers 0 to 3 (IMR0 to IMR3) Remark: 254 n = 0 to 105 (see Table 7-2, "Addresses and Bits of Interrupt Control Registers," on page 237) User's Manual U16580EE3V1UD00 Chapter 8 Clock Generator The clock generator (CG) generates and controls the internal system clock (fXX) that is supplied to each internal unit, such as the CPU. 8.1 Features * Multiplier function using a phase locked loop (PLL) synthesizer (fXX = 4 x fX) - Crystal frequency: fX = 16 MHz - Internal system clock: fXX = 64 MHz * Power saving mode: HALT mode 8.2 Configuration Figure 8-1: Clock Generator fXX X1 X2 Remark: fX: fXX: CPU Clock Generator (CG) fX On-chip peripheral I/O External resonator or external clock frequency Internal system clock An external resonator or crystal is connected to X1 and X2 pins, whose frequency is multiplied by the PLL synthesizer. By this an internal system clock (fXX) is generated that is 4 times the frequency (fX) of the external resonator or crystal. The clock controller enables PLL automatically and starts clock supply to the system after oscillation stabilization time has passed. Internal System Clock Frequency (fXX) External Resonator or Crystal Frequency (fX) 64.000 MHz 16.0000 MHz User's Manual U16580EE3V1UD00 255 Chapter 8 Clock Generator 8.3 Power Save Control 8.3.1 Overview The power save function of V850E/PH2 supports the HALT mode only. In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU's operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues. The power consumption of the overall system can be reduced by intermittent operation that is achieved due to a combination of HALT mode and normal operation mode. The system is switched to HALT mode by a specific instruction (the HALT instruction). Figure 8-2 shows the operation of the clock generator in normal operation mode and HALT mode. Figure 8-2: Power Save Mode State Transition Diagram Set HALT mode HALT mode Normal operation mode Note 1 Interrupt request Note 2 RESET pin input Wait for stabilization of oscillation and PLL Notes: 1. Non-maskable interrupt request signal (NMI) or unmasked maskable interrupt request signal. 2. The oscillation stabilization time is necessary after release of reset because the PLL is initialized by a reset. The stabilization time is determined by default. 256 User's Manual U16580EE3V1UD00 Chapter 8 Clock Generator 8.3.2 HALT mode (1) Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. When HALT mode is set, clock supply is stopped to the CPU only. The clock generator and PLL continue operating. Clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 18-3 shows the operation status in the HALT mode. The average power consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Cautions: 1. Insert five or more NOP instructions after the HALT instruction. 2. If the HALT instruction is executed while an interrupt request is being held pending, the HALT mode is set but is released immediately by the pending interrupt request. Table 8-1: Operation Status in HALT Mode Function Operation Status Clock generator Operating Internal system clock (fXX) Supplied CPU Stopped DMA Operating Interrupt controller Operating Ports Maintained On-chip peripheral I/O (excluding ports) Operating Internal data All internal data such as CPU registers, states, data, and the contents of internal RAM are retained in the state they were before HALT mode was set. A0 to A21 Operating D0 to D31 RD WR BEN0 to BEN3 CS0, CS1, CS3, CS4 WAIT User's Manual U16580EE3V1UD00 257 Chapter 8 (2) Clock Generator Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI), an unmasked maskable interrupt request signal, or RESET pin input. After the HALT mode has been released, the normal operation mode is restored. (a) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal (INTWDT) or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. * If an interrupt request signal with a priority lower than or same as the interrupt currently being serviced is generated, the HALT mode is released, but the newly generated interrupt request signal is not acknowledged. The interrupt request signal itself is retained. * If an interrupt request signal with a priority higher than that of the interrupt currently being serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt request signal is acknowledged. Table 8-2: Operation After Releasing HALT Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address Unmasked maskable interrupt request signal Execution branches to the handler address or the next instruction is executed The next instruction is executed (b) Releasing HALT mode by RESET pin input or WDTRES signal generation The same operation as the normal reset operation is performed. 258 User's Manual U16580EE3V1UD00 Chapter 9 16-Bit Timer/Event Counter P 9.1 Features Timer P (TMP) is a 16-bit timer/event counter that can be used in various ways. TMP can perform the following operations. * PWM output * Interval timer * External event counter (operation not possible when clock is stopped) * One-shot pulse output * Pulse width measurement 9.2 Function Outline * Capture trigger input signal x 2 * External trigger input signal x 1 * Clock select x 8 * External event count input x 1 * Readable counter x 1 * Capture/compare reload register x 2 * Capture/compare match interrupt x 2 * Timer output (TOPn0, TOPn1) x 2 User's Manual U16580EE3V1UD00 259 Chapter 9 16-Bit Timer/Event Counter P 9.3 Configuration TMP includes the following hardware. Table 9-1: Configuration of TMP0 to TMP8 Item Configuration Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter register (TPnCNT) CCR0 buffer register, CCR1 buffer register Timer input 2 x 8 (TIPm0, TIPm1, TTRGPm, TEVTPm)Note Timer output 2 x 8 (TOPm0, TOPm1)Note 1 x 1 (TOP81) Control registers TMPn control registers 0, 1 (TPnCTL0, TPnCTL1) TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2) TMPn option registers 0, 1 (TPnOPT0, TPnOPT1) Note: TIPm0 and TIPm1 captures inputs are shared with external trigger inputs TTRGPm, and external event inputs TEVTPm, and the corresponding TOPm0 and TOPm1 outputs. Remark: n = 0 to 8 m = n for n= 0 to 7 Figure 9-1: Block Diagram of Timer P Internal bus Note 1 TTRGPn Note 1 TIPn0 Note 1 TIPn1 Selector INTTPnOV 16-bit timer counter Output controller Selector Clear Edge detector Note 1 TEVTPn TPnCNT Edge detector fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/256 fXX/1024 CCR0 buffer register CCR1 buffer register TOPn0 Note 1 TOPn1 INTTPnCC0 INTTPnCC1 TPnCCR0 TPnCCR1 Note 2 INTCM10 Note 2 INTT0CC0 Internal bus Note 2 INTCM11 Note 2 INTT0CC1 Notes: 1. External pin is not available for TMP8. 2. Internal signal inputs (INTTT0CC0 and INTTT0CC1 of TMT0, or INTCM10 and INTCM11 of TMENC1) available on TMP8 only. (ref. to 9.4 (9) TMP input control register 2 (TPIC2)). 260 User's Manual U16580EE3V1UD00 Chapter 9 (1) 16-Bit Timer/Event Counter P TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TPnCCS0 bit of the TPnOPT0 register, but only in the free-running mode. In the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) In modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. In the initial setting, the TPnCCR0 register is a compare register. This register can be read or written in 16-bit units. Reset input clears this register to 0000H. Figure 9-2: After reset: 15 TMPn Capture/Compare Register 0 (TPnCCR0) 0000H 14 13 R/W 12 11 Address: 10 9 8 TP0CCR0 TP2CCR0 TP4CCR0 TP6CCR0 TP8CCR0 7 6 FFFFF606H, TP1CCR0 FFFFF626H, TP3CCR0 FFFFF646H, TP5CCR0 FFFFF666H, TP7CCR0 FFFFF686H 5 4 3 2 FFFFF616H, FFFFF636H, FFFFF656H, FFFFF676H, 1 0 TPnCCR0 (n = 0 to 8) (a) Use as compare register TPnCCR0 can be rewritten when TPnCE = 1 The timing at which the TPnCCR0 rewrite values become valid when TPnCE = 1 is as follows. TMP Operation Mode Method of Writing TPnCCR0 Register PWM mode, external trigger pulse output mode Reload Free-running mode, external event count mode, one-shot pulse output mode, interval timer mode Anytime write Pulse width measurement mode Cannot be used because dedicated capture register (b) Use as capture register * TMP0 to TMP7 The counter value is saved to TPnCCR0 upon capture trigger (TIPn0) input edge detection. * TMP8 Since TMP8 has no external input pin, the capture function can only be used internally for capturing the interrupt signal (INTTT0CC0 of TMT0, or INTCM10 of TMENC1) specified by the TPIC22 bit of TPIC2 register (ref. to 9.4 (9) TMP input control register 2 (TPIC2)). User's Manual U16580EE3V1UD00 261 Chapter 9 (2) 16-Bit Timer/Event Counter P TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TPnCCS1 bit of the TPnOPT0 register, but only in the free-running mode. In the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) In modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. In the initial setting, the TPnCCR1 register is a reload register. This register can be read or written in 16-bit units. Reset input clears this register to 0000H. Figure 9-3: After reset: 15 TMPn Capture/Compare Register 1 (TPnCCR1) 0000H 14 13 R/W 12 11 Address: 10 9 8 TP0CCR1 TP2CCR1 TP4CCR1 TP6CCR1 TP8CCR1 7 6 FFFFF608H, TP1CCR1 FFFFF628H, TP3CCR1 FFFFF648H, TP5CCR1 FFFFF668H, TP7CCR1 FFFFF688H 5 4 3 2 FFFFF618H, FFFFF638H, FFFFF658H, FFFFF678H, 1 0 TPnCCR1 (n = 0 to 8) (a) Use as compare register TPnCCR1 can be rewritten when TPnCE = 1 The timing at which the TPnCCR1 rewrite values become valid when TPnCE = 1 is as follows. TMP Operation Mode Method of Writing TPnCCR0 Register PWM mode, external trigger pulse output mode Reload Free-running mode, external event count mode, one-shot pulse output mode, interval timer mode Anytime write Pulse width measurement mode Cannot be used because dedicated capture register (b) Use as capture register * TMP0 to TMP7 The counter value is saved to TPnCCR1 upon capture trigger (TIPn1) input edge detection. * TMP8 Since TMP8 has no external input pin, the capture function can only be used internally for capturing the interrupt signal (INTTT0CC1 of TMT0, or INTCM11 of TMENC1) specified by the TPIC22 bit of TPIC2 register (ref. to 9.4 (9) TMP input control register 2 (TPIC2)). 262 User's Manual U16580EE3V1UD00 Chapter 9 (3) 16-Bit Timer/Event Counter P TMPn counter register (TPnCNT) The TPnCNT register is a read buffer register that can read 16-bit counter values. This register is read-only, in 16-bit units. Reset input clears this register to 0000H, as the TPnCE bit is cleared to 0. Figure 9-4: After reset: 15 0000H 14 TMPn Counter Register (TPnCNT) R 13 12 11 Address: 10 9 8 TP0CNT TP2CNT TP4CNT TP6CNT TP8CNT 7 6 FFFFF60AH, TP1CNT FFFFF62AH, TP3CNT FFFFF64AH, TP5CNT FFFFF66AH, TP7CNT FFFFF68AH 5 4 3 2 FFFFF61AH, FFFFF63AH, FFFFF65AH, FFFFF67AH, 1 0 TPnCNT (n = 0 to 8) Remark: The value of the TPnCNT register is cleared to 0000H when the TPnCE bit = 0. If the TPnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. User's Manual U16580EE3V1UD00 263 Chapter 9 16-Bit Timer/Event Counter P 9.4 Control Registers (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of timer P. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. The same value can always be written to the TPnCTL0 register by software. Figure 9-5: After reset: TPnCTL0 00H TMPn Control Register 0 (TPnCTL0) R/W Address: TP0CTL0 TP2CTL0 TP4CTL0 TP6CTL0 TP8CTL0 7 6 5 4 3 TPnCE 0 0 0 0 FFFFF600H, TP1CTL0 FFFFF620H, TP3CTL0 FFFFF640H, TP5CTL0 FFFFF660H, TP7CTL0 FFFFF680H 2 FFFFF610H, FFFFF630H, FFFFF650H, FFFFF670H, 1 0 TPnCKS2 TPnCKS1 TPnCKS0 (n = 0 to 8) TPnCE Timer Pn Operation Control 0 Internal operating clock operation disabled (TMPn reset asynchronously) 1 Internal operating clock operation enabled * Internal operating clock control and TMPn asynchronous reset are performed with the TPnCE bit. When the TPnCE bit is cleared to 0, the internal operating clock of TMPn stops (fixed to low level) and TMPn is reset asynchronously. * When the TPnCE bit is set to 1, the internal operating clock is enabled and count-up operation starts within 2 input clocks after the TPnCE bit was set to 1 TPnCKS2 TPnCKS1 TPnCKS0 Internal Count Clock Selection 0 0 0 fXX/2 0 0 1 fXX/4 0 1 0 fXX/8 0 1 1 fXX/16 1 0 0 fXX/32 1 0 1 fXX/64 1 1 0 fXX/256 1 1 1 fXX/1024 Caution: Set the TPnCKS2 to TPnCKS0 bits when TPnCE = 0. When the value of the TPnCE bit is changed from 0 to 1, the TPnCKS2 to TPnCKS0 bits can be set simultaneously. Remark: n = 0 to 8 264 User's Manual U16580EE3V1UD00 Chapter 9 (2) 16-Bit Timer/Event Counter P TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of timer P. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-6: After reset: TPnCTL1 00H TMPn Control Register 1 (TPnCTL1) (1/2) R/W Address: TP0CTL1 TP2CTL1 TP4CTL1 TP6CTL1 TP8CTL1 FFFFF601H, TP1CTL1 FFFFF621H, TP3CTL1 FFFFF641H, TP5CTL1 FFFFF661H, TP7CTL1 FFFFF681H FFFFF611H, FFFFF631H, FFFFF651H, FFFFF671H, 7 6 5 4 3 2 1 0 TPnSYE TPnEST TPnEEE 0 0 TPnMD2 TPnMD1 TPnMD0 (n = 0 to 8) TPnSYE Synchronous Mode Selection 0 Timer Pn operates in single operation mode 1 Timer Pn operates in synchronous operation modeNote * This bit supports synchronous operation of two or more timer P. * Two groups of timers exist, which can be synchronized: TMP0 to TMP3 with TMP0 as master, and TMP4 to TMP7 with TMP4 as master. Note: Synchronous operation mode is not available for TMP8 (n = 8). TPnEST Software Trigger Control 0 No operation 1 In one-shot pulse mode: One-shot pulse software trigger In external trigger pulse output mode: Pulse output software trigger * The TPnEST bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output modeNote 1, if it is set to 1 when TPnCE = 1. Therefore, be sure to set TPnEST to 1 after setting TPnCE to 1. * TTRGPn pin is used as the external trigger input of TMPn.Note 2 * The read value of the TPnEST bit is always 0. Notes: 1. The TRnEST bit is invalid even if it is controlled in any other mode. 2. External trigger input pin is not available for TMP8 (n = 8) Cautions: 1. Always clear the TPnSYE bit for the master timers TMP0 and TMP4. 2. Always clear the TPnSYE bit for TMP8. Do not operate TMP8 in synchronous mode. Remark: n = 0 to 8 User's Manual U16580EE3V1UD00 265 Chapter 9 Figure 9-6: 16-Bit Timer/Event Counter P TMPn Control Register 1 (TPnCTL1) (2/2) TPnEEE Count Clock Selection 0 Use the internal clock (selected by bits TPnCKS2 to TPnCKS0) 1 Use external clock input (TEVTPn input edge)Note * When TPnEEE = 1 (external clock input TEVTPn), the valid edge is specified by bits TPnEES1 and TPnEES0. Note: External clock input pin is not available for TMP8 (n = 8). TPnMD2 TPnMD1 TPnMD0 Timer Mode Selection 0 0 0 Interval timer mode Note 1, 2 0 0 1 External event count mode Note 1, 2, 3 0 1 0 External trigger pulse output mode Note 2, 3 0 1 1 One-shot pulse mode Note 2 1 0 0 PWM mode Note 2 1 0 1 Free-running mode 1 1 0 Pulse width measurement mode Note 1, 2 1 1 1 Setting prohibited Notes: 1. Setting prohibited for TMP0 and TMP4, when synchronous operation function is enabled (TPnSYE = 1). 2. Setting prohibited for TMP1 to TMP3, and TMP5 to TMP7, when synchronous operation function is enabled (TPnSYE = 1). 3. Setting prohibited for TMP8. Cautions: 1. Rewrite the TPnEEE and TPnMD2 to TPnMD0 bits only when TPnCE = 0. (The same value can be written when TPnCE = 1.) The operation is not guaranteed if rewriting is performed when TPnCE = 1. If rewriting was mistakenly performed, set TPnCE = 0 and then set the bits again. 2. Set TP8EEE bit of the TR0CTL1 register always to 0, because TMP8 does not incorporate an external clock input. In case of TP8EEE = 1 operation of TMP8 is not guaranteed. Remark: 266 n = 0 to 8 User's Manual U16580EE3V1UD00 Chapter 9 (3) 16-Bit Timer/Event Counter P TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-7: After reset: TPnIOC0 00H TMPn I/O Control Register 0 (TPnIOC0) R/W Address: TP0IOC0 TP2IOC0 TP4IOC0 TP6IOC0 TP8IOC0 FFFFF602H, TP1IOC0 FFFFF622H, TP3IOC0 FFFFF642H, TP5IOC0 FFFFF662H, TP7IOC0 FFFFF682H FFFFF612H, FFFFF632H, FFFFF652H, FFFFF672H, 7 6 5 4 3 2 1 0 0 0 0 0 TPnOL1 TPnOE1 TPnOL0 TPnOE0 (n = 0 to 8) TPnOL1 Timer Output Level Setting (TOPn1 pin) 0 Normal output (Low level, when output is inactive.) 1 Inverted output (High level, when output is inactive.) TPnOE1 Timer Output Control (TOPn1 pin) 0 Timer output prohibited (TOPn1 pin output is fixed to inactive level.) 1 Timer output enabled (A pulse can be output from the TOPn1 pin.) TPnOL0 Timer Output Level Setting (TOPn0 pin)Note 0 Normal output (Low level, when output is inactive.) 1 Inverted output (High level, when output is inactive.) TPnOE0 Timer Output Control (TOPn0 pin)Note 0 Timer output prohibited (TOPn0 pin output is fixed to inactive level.) 1 Timer output enabled (A pulse can be output from the TOPn0 pin.) Note: TOPn0 output pin is not available for TMP8. Caution: Rewrite the TPnOL1, TPnOE1, TPnOl0, and TPnOE0 bits only when TPnCE = 0. (The same value can be written when TPnCE = 1.) If rewriting was mistakenly performed, set TPnCE = 0 and then set the bits again. Remark: n = 0 to 8 User's Manual U16580EE3V1UD00 267 Chapter 9 (4) 16-Bit Timer/Event Counter P TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIPn0, TIPn1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-8: After reset: TPnIOC1 00H TMPn I/O Control Register 1 (TPnIOC1) R/W Address: TP0IOC1 TP2IOC1 TP4IOC1 TP6IOC1 TP8IOC1 FFFFF603H, TP1IOC1 FFFFF623H, TP3IOC1 FFFFF643H, TP5IOC1 FFFFF663H, TP7IOC1 FFFFF683H FFFFF613H, FFFFF633H, FFFFF653H, FFFFF673H, 7 6 5 4 3 2 1 0 0 0 0 0 TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIS3 TPnIS2 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection TPnIS1 TPnIS0 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection (n = 0 to 8) Capture Input (TIPn1) Valid Edge SettingNote Capture Input (TIPn0) Valid Edge SettingNote Note: TIPn0 and TIPn1 input pins are not available for TMP8. These inputs are only connected internally to capture the interrupt signals INTTT0CC0 and INTT0CC1 of TMT0, or INTCM10 and INTCM11 of TMENC1, specified by the TPIC22 bit of TPIC2 register (ref. to 9.4 (9) TMP input control register 2 (TPIC2)). Cautions: 1. Rewrite the TPnIS3 to TPnIS0 bits only when TPnCE = 0. (The same value can be written when TPnCE = 1.) If rewriting was mistakenly performed, set TPnCE = 0 and then set the bits again. 2. The TPnIS3 to TPnIS0 bits are valid only in the free-running mode and the pulse width measurement mode. In all other modes, a capture operation is not possible. Remark: 268 n = 0 to 8 User's Manual U16580EE3V1UD00 Chapter 9 (5) 16-Bit Timer/Event Counter P TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TEVTPn) and external trigger input signal (TTRGPn). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-9: After reset: TPnIOC2 00H TMPn I/O Control Register 2 (TPnIOC2) R/W Address: 7 6 5 4 0 0 0 0 TP0IOC2 TP2IOC2 TP4IOC2 TP6IOC2 TP8IOC2 FFFFF604H, TP1IOC2 FFFFF624H, TP3IOC2 FFFFF644H, TP5IOC2 FFFFF664H, TP7IOC2 FFFFF684H 3 2 FFFFF614H, FFFFF634H, FFFFF654H, FFFFF674H, 1 0 TPnEES1 TPnEES0 TPnETS1 TPnETS0 (n = 0 to 7) TP1EES1 TP1EES0 External Event Counter Input (TEVTPn) Valid Edge Setting 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection TP1ETS1 TP1ETS0 External Trigger Input (TTRGPn) Valid Edge Setting 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Cautions: 1. Rewrite the TPnEES1, TPnEES0, TPnEST1, and TPnEST0 bits only when TPnCE = 0. (The same value can be written when TPnCE = 1.) If rewriting was mistakenly performed, set TPnCE = 0 and then set the bits again. 2. The TPnEES1 and TPnEES0 bits are valid only when TPnEEE = 1 or when the external event count mode (TPnMD2 to TPnMD0 = 001B of the TPnCTL1 register) has been set. Remark: n = 0 to 7 User's Manual U16580EE3V1UD00 269 Chapter 9 (6) 16-Bit Timer/Event Counter P TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-10: After reset: TPnOPT0 00H TMPn Option Register 0 (TPnOPT0) R/W 7 6 0 0 Address: 5 4 TPnCCS1 TPnCCS0 TP0OPT0 TP2OPT0 TP4OPT0 TP6OPT0 TP8OPT0 FFFFF605H, TP1OPT0 FFFFF625H, TP3OPT0 FFFFF645H, TP5OPT0 FFFFF665H, TP7OPT0 FFFFF685H FFFFF615H, FFFFF635H, FFFFF655H, FFFFF675H, 3 2 1 0 0 0 0 TPnOVF (n = 0 to 8) TPnCCS1 TPnCCR1 register capture/compare selection 0 Compare register selection 1 Capture register selection The TPnCCS1 bit settings are valid only in the free-running mode. TPnCCS0 TPnCCR0 register capture/compare selection 0 Compare register selection 1 Capture register selection The TPnCCS0 bit settings are valid only in the free-running mode. TPnOVF Timer P overflow detection flag 0 No overflow occurrence after timer restart or flag reset 1 Overflow occurrence * The TPnOVF flag is set when the 16-bit counter value overflows from FFFFH to 0000H in the free-running mode or the pulse measurement mode. * An interrupt request signal (INTTPnOV) is generated at the same time that the TPnOVF flag is set (1). The INTTPnOV signal is not generated in modes other than the free-running mode or the pulse measurement mode. * The TPnOVF flag is not cleared even when the TPnOVF flag and the TPnOPT0 register are read. * The TPnOVF flag can be both read and written, but only reset (0) is accepted. Writing 1 has no influence on the operation of timer P. Caution: Rewrite the TPnCCS1 and TPnCCS0 bits only when TPnCE = 0. (The same value can be written when TPnCE = 1.) If rewriting was mistakenly performed, set TPnCE = 0 and then set the bits again. Remark: n = 0 to 8 270 User's Manual U16580EE3V1UD00 Chapter 9 (7) 16-Bit Timer/Event Counter P TMP input control register 0 (TPIC0) The TPIC0 register is an 8-bit register that controls the external input pin source of the capture register 1 of TMP0 to TMP3. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 9-11: After reset: TPIC0 00H TMPn Input Control Register 0 (TPIC0) R/W Address: FFFFF6F0H 7 6 5 4 3 2 1 0 0 0 0 0 TPIC03 TPIC02 TPIC01 TPIC00 TPIC03 TP3CCR1 Register Capture Source Input Selection 0 Capture source input is pin P17/TIP31 1 Capture source input is pin P16/TIP30 TPIC02 TP2CCR1 Register Capture Source Input Selection 0 Capture source input is pin P15/TIP21 1 Capture source input is pin P14/TIP20 TPIC01 TP1CCR1 Register Capture Source Input Selection 0 Capture source input is pin P13/TIP11 1 Capture source input is pin P12/TIP10 TPIC00 TP0CCR1 Register Capture Source Input Selection 0 Capture source input is pin P11/TIP01 1 Capture source input is pin P10/TIP00 User's Manual U16580EE3V1UD00 271 Chapter 9 (8) 16-Bit Timer/Event Counter P TMP input control register 1 (TPIC1) The TPIC1 register is an 8-bit register that controls the external input pin source of the capture register 1 of TMP4 to TMP7, as well as the internal time trigger source from the AFCAN controllers of both capture registers 0 and 1 of TMP7. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 9-12: After reset: TPIC1 00H TMP Input Control Register 1 (TPIC1) R/W Address: FFFFF6F2H 7 6 5 4 3 2 1 0 0 0 TIP15 TIP14 TPIC13 TPIC12 TPIC11 TPIC10 TIPC14 TIPC13 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 TPIC15 Note TPIC12 Capture Source Input Selection of TP7CCR0 Pin P26/TIP70 AFCAN0 time trigger Pin P27/TIP71 Pin P26/TIP70 Pin P26/TIP70 AFCAN1 time triggerNote AFCAN0 time trigger TP6CCR1 Register Capture Source Input Selection Capture source input is pin P25/TIP61 1 Capture source input is pin P24/TIP60 TP5CCR1 Register Capture Source Input Selection 0 Capture source input is pin P23/TIP51 1 Capture source input is pin P22/TIP50 TPIC10 Pin P27/TIP71 Pin P26/TIP70 0 TPIC11 TP7CCR1 TP4CCR1 Register Capture Source Input Selection 0 Capture source input is pin P21/TIP41 1 Capture source input is pin P20/TIP40 Note: Setting TPIC15 to 1 is prohibited for PD70F3447, since the AFCAN1 controller is not available. 272 User's Manual U16580EE3V1UD00 Chapter 9 (9) 16-Bit Timer/Event Counter P TMP input control register 2 (TPIC2) The TPIC2 register is an 8-bit register that controls the external input pin source of the capture register 1 of TMT0 and TMT1, as well as the internal source of both capture registers 0 and 1 of TMP8. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 9-13: After reset: TPIC2 00H TMP Input Control Register 1 (TPIC1) R/W Address: FFFFF6F4H 7 6 5 4 3 2 1 0 0 0 0 0 0 TPIC22 TPIC21 TPIC20 Capture Source Input Selection of TIPC22 Note TP8CCR0 TP8CCR1 0 INTTT0CC0 signal of TMT0 INTTT1CC1 signal of TMT0 1 TPIC21 INTCM10 signal of TMENC1Note TT1CCR1 Register Capture Source Input Selection 0 Capture source input is pin P74/TIT11 1 Capture source input is pin P73/TIT10 TPIC20 INTCM11 signal of TMENC1Note TT0CCR1 Register Capture Source Input Selection 0 Capture source input is pin P71/TIT01 1 Capture source input is pin P70/TIT00 Note: Setting TIPC22 to 1 is prohibited for PD70F3447, since TMENC1 is not available. User's Manual U16580EE3V1UD00 273 Chapter 9 16-Bit Timer/Event Counter P 9.5 Operation Timer P can perform the following operations. Operation TPnEST (Software Trigger Bit) TTRGPn0 (External Trigger Input) Capture/Compare Mode Compare Register Rewriting Method Interval timer mode Invalid Invalid Compare only Anytime rewrite External event count mode Note 1 Invalid Invalid Compare only Anytime rewrite External trigger pulse output mode Note 2 Valid Valid Compare only Reload One-shot pulse output mode Note 2 Valid Valid Compare only Anytime rewrite PWM mode Invalid Invalid Compare only Reload Free-running mode Invalid Invalid Capture/compare selectable Anytime rewrite Pulse width measurement mode Note 2 Invalid Invalid Capture only Not applicable Notes: 1. To use the external event count function, specify that the edge of the capture input TIPn1 or TIPn0 respectively, shared with event input TEVTPn is not detected (by clearing the TPSn3, TPSn2 bits or TPnIS1, TPnIS0 bits of the TPnIOC1 register respectively to "00B") (n = 0 to 7). 2. When using the external trigger pulse output mode, one-shot pulse mode, and pulse width measurement mode, select a count clock (by clearing the TPnEEE bit of the TPnCTL1 register to 0). Remark: n = 0 to 7 9.5.1 Anytime rewrite and reload TPnCCR0 and TPnCCR1 register rewrite is possible for timer P during timer operation (TPnCE = 1), but the write method (anytime rewrite, reload) differs depending on the mode. (1) Anytime rewrite When the TPnCCRm register is written during timer operation, the write data is transferred at that time to the CCRm buffer register and used as the 16-bit counter comparison value. Remark: 274 n = 0 to 8 m = 0, 1 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-14: 16-Bit Timer/Event Counter P Basic Operation Flow for Anytime Write START Initial settings Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register TPnCCR0 rewrite Transfer to CCR0 buffer register TPnCCR1 rewrite Transfer to CCR1 buffer register * Match between CCR0 buffer register and 16-bit counter * 16-bit counter clear & start INTTPnCC0 output Remarks: 1. The above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 8 User's Manual U16580EE3V1UD00 275 Chapter 9 Figure 9-15: 16-Bit Timer/Event Counter P Timing Diagram for Anytime Write TPnCE = 1 D01 D01 D02 16-bit counter 0000H CCR1 buffer register D02 D01 D11 TPnCCR1 0000H D12 D12 D01 TPnCCR0 CCR0 buffer register D11 D11 D02 D12 D11 D12 INTTPnCC0 INTTPnCC1 Remarks: 1. D01, D02: Setting values of TPnCCR0 register (0000H to FFFFH) D11, D12: Setting values of TPnCCR1 register (0000H to FFFFH) 2. The above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 8 276 User's Manual U16580EE3V1UD00 Chapter 9 (2) 16-Bit Timer/Event Counter P Reload method (Batch Rewrite) When the TPnCCR0 and TPnCCR1 registers are written during timer operation via the CCRm buffer register, the write data is used as the 16-bit counter comparison value. The TPnCCR0 register and the TPnCCR1 register can be rewritten when TPnCE = 1. In order for the setting value when the TPnCCR0 register and the TPnCCR1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the CCRm buffer register), it is necessary to rewrite TPnCCR0 and then write to the TPnCCR1 register before the 16-bit counter value and the TPnCCR0 register value match. Thereafter, the values of the TPnCCR0 and the TPnCCR1 register are reloaded upon TPnCCR0 register match. Whether to enable or disable the next reload timing is controlled by writing to the TPnCCR1 register. Thus even when wishing only to rewrite the value of the TPnCCR0 register, also write the same value to the TPnCCR1 register. Figure 9-16: Basic Operation Flow for Reload (Batch Rewrite) START Initial settings Timer operation enable (TPnCE = 1) Transfer of TPnCCRm values to CCRm buffer register TPnCCR0 rewrite TPnCCR1 rewrite * Match between TPnCCR0 and 16-bit counter * 16-bit counter clear & start * Reload of TPnCCRm values to CCRm buffer register Caution: Reload enable INTTPnCC0 output Writing to the TPnCCR1 register includes enabling of reload. Thus, rewrite the TPnCCR1 register after rewriting the TPnCCR0 register. Remarks: 1. The above flowchart illustrates an example of the operation in the PWM mode. 2. n = 0 to 8 m = 0, 1 User's Manual U16580EE3V1UD00 277 Chapter 9 16-Bit Timer/Event Counter P Figure 9-17: Timing Chart for Reload TPnCE = 1 D01 D02 D11 D12 16-bit counter TPnCCR0 D01 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register D12 D11 D03 Note D02 Note D03 Same value write D12 D12 D11 D12 D12 D02 D01 D03 D02 D12 D12 INTTPnCC0 INTTPnCC1 Note: Reload is not performed because the TPnCCR1 register was not rewritten. Remarks: 1. D01, D02, D03: Setting value of TPnCCR0 register (0000H to FFFFH) D11, D12: Setting value of TPnCCR1 register (0000H to FFFFH) 2. The above timing chart illustrates the operation in the PWM mode as an example. 3. n = 0 to 8 278 User's Manual U16580EE3V1UD00 Chapter 9 16-Bit Timer/Event Counter P 9.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000B) In the interval timer mode, an interrupt request signal (INTTPnCC0) is output upon a match between the setting value of the TPnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. The TPnCCR0 register can be rewritten when TPnCE = 1, and when a value is set to the TPnCCR0 register with a write instruction from the CPU, it is transferred to the CCR0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. In the interval timer mode, the 16-bit counter is cleared only upon a match between the value of the 16bit counter and the value of the CCR0 buffer register. 16-bit counter clearing using the TPnCCR1 register is not performed. However, the setting value of the TPnCCR1 register is transferred to the CCR1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (INTTPnCC1) is output if these values match. Moreover, TOPnm pin output is also possible by setting the TPnOEm bit to 1. When the TPnCCR1 register is not used, it is recommended to set FFFFH as the setting value for the TPnCCR1 register. Remark: n = 0 to 8 m = 0, 1 Figure 9-18: Flowchart of Basic Operation in Interval Timer Mode START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * Interval timer mode setting (TPnCTL0: TPnMD2 to TPnMD0 = 000) * Compare register setting (TPnCCR0, TPnCCR1) Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register Match between 16-bit counter and CCR1 buffer registerNote INTTPnCC1 output Match between 16-bit counter and CCR0 buffer register, 16-bit counter clear & start INTTPnCC0 output Note: The 16-bit counter is not cleared upon a match between the 16-bit counter and TPnCCR1. Remark: n = 0 to 8 User's Manual U16580EE3V1UD00 279 Chapter 9 Figure 9-19: 16-Bit Timer/Event Counter P Basic Operation Timing in Interval Timer Mode (1/2) (a) D1 > D2 > D3; rewrite of TPnCCR0 register only; TOPn0, TOPn1 are not output (TPnOE0/TPnOE1 = 0, TPnOL0 = 0, TPnOL = 1) TPnCE = 1 FFFFH D1 D1 D2 D3 16-bit counterNote TPnCCR0 CCR0 buffer register D1 0000H D2 D1 D2 D3 TPnCCR1 CCR1 buffer register D3 D3 D3 0000H INTTPnCC0 INTTPnCC1 TOPn0 TOPn1 L H tD1 tD1 tD2 Note: The 16-bit counter is not cleared when its value matches the value of TPnCCR1. Remarks: 1. D1, D2: Setting values of TPnCCR0 register (0000H to FFFFH) D3: Setting value of TPnCCR1 register (0000H to FFFFH) 2. Interval time (tDn) = (Dn + 1) x (count clock cycle) 3. n = 0 to 8 280 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-19: 16-Bit Timer/Event Counter P Basic Operation Timing in Interval Timer Mode (2/2) (b) D1 = D2; no TPnCCR0, TPnCCR1 rewrite; TOPn0 and TOPn1 are output (TPnOE0/TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1) TPnCE = 1 FFFFH D 1 = D2 D1 = D2 D1 = D2 16-bit counter TPnCCR0 CCR0 buffer register D1 D1 0000H TPnCCR1 CCR1 buffer register D2 D2 0000H INTTPnCC0 INTTPnCC1 TOPn0 TOPn1 tD1 = tD2 tD1 = tD2 tD1 = tD2 Remarks: 1. D1: Setting value of TPnCCR0 register (0000H to FFFFH) D2: Setting value of TPnCCR1 register (0000H to FFFFH) 2. Interval time (tDn) = (Dn + 1) x (count clock cycle) 3. n = 0 to 8 User's Manual U16580EE3V1UD00 281 Chapter 9 16-Bit Timer/Event Counter P 9.5.3 External event count mode (TPnMD2 to TPnMD0 = 001B) In the external event count mode, external event count input (TEVTPn pin input) is used as a count-up signal. When the external event count mode is set, count-up is performed using external event count input (TEVTPn pin input), regardless of the setting of the TPnEEE bit of the TPnCTL0 register. In the external event count mode, a match interrupt request (INTTPnCC0) is output upon a match between the setting value of the TPnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. When a value is set to the TPnCCR0 register with a write instruction from the CPU, it is transferred to the CCR0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. In the external event count mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the CCR0 buffer register. 16-bit counter clearing using the TPnCCR1 register is not performed. However, the setting value of the TPnCCR1 register is transferred to the CCR1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (INTTPnCC1) is output if these values match. Moreover, TOPn1 pin output is also possible by setting the TPnOE1 bit to 1. The TPnCCR0 register can be rewritten when TPnCE = 1. When the TPnCCR1 register is not used, it is recommended to set TPnCCR1 to FFFFH. Cautions: 1. In external event count mode, when the content of the TRnCCR0 register is set to m, the number of TEVTPn pin input edge detection times is m+1. 2. In external event count mode, do not set TPnCCR0 register to 0000H. 3. When the TPnCCR1 register value is set to 0000H in external event count mode the corresponding interrupt (INTTPnCC1) does not occur immediately after start, but after the first overflow of the timer (FFFFH to 0000H). 4. TOPn0 pin output cannot be used in external event count mode. Alternatively use the interval timer mode (refer to section 9.5.2 on page 279) and set TPnEEE = 1 in conjunction with TOPn0 pin output. Remark: 282 n = 0 to 7 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-20: 16-Bit Timer/Event Counter P Flowchart of Basic Operation in External Event Count Mode START Initial settings External event count mode setting (TPnCTL0. TPnMD2 to TPnMD0 = 001)Note 1 * Valid edge setting (TPnIOC2. TPnEES1, TPnEES0) * Compare register setting (TPnCCR0, TPnCCR1) * Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register Match between 16-bit counter and CCR1 buffer registerNote 2 INTTPnCC1 output Match between 16-bit counter and CCR0 buffer register, 16-bit counter clear & start INTTPnCC0 output Notes: 1. Selection of the TPnEEE bit has no influence. 2. The 16-bit counter is not cleared upon a match between the 16-bit counter and the CCR1 buffer register. Remark: n = 0 to 7 User's Manual U16580EE3V1UD00 283 Chapter 9 Figure 9-21: 16-Bit Timer/Event Counter P Basic Operation Timing in External Event Count Mode (1/2) (a) D1 > D2 > D3; rewrite of TPnCCR0 only; no TOPn1 output TPnCE = 1 FFFFH D1 D1 D2 16-bit counter D3 D3 D1 TPnCCR0 CCR0 buffer register 0000H D2 D1 D2 D3 TPnCCR1 CCR1 buffer register D3 0000H D3 INTTPnCC0 INTTPnCC1 Remarks: 1. D1, D2: Setting values of TPnCCR0 register (0000H to FFFFH) D3: Setting value of TPnCCR1 register (0000H to FFFFH) 2. Event count = (Dn + 1) 3. n = 0 to 7 284 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-21: 16-Bit Timer/Event Counter P Basic Operation Timing in External Event Count Mode (1/2) (b) D1 = D2; no TPnCCR0, TPnCCR1 rewrite; TOPn1 output TPnCE = 1 FFFFH D1 = D2 D1 = D2 D1 = D2 16-bit counter TPnCCR0 D1 CCR0 buffer 0000H register D1 TPnCCR1 D2 CCR1 buffer 0000H register D2 INTTPnCC0 INTTPnCC1 TOPn1 Remarks: 1. D1: Setting value of TPnCCR0 register (0000H to FFFFH) D2: Setting value of TPnCCR1 register (0000H to FFFFH) 2. Event count = (Dn + 1) 3. n = 0 to 7 User's Manual U16580EE3V1UD00 285 Chapter 9 16-Bit Timer/Event Counter P 9.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B) In the external trigger pulse output mode, setting TPnCE = 1 causes external trigger input (TTRGPn pin input) wait with the 16-bit counter stopped at FFFFH. The count-up operation starts upon detection of the external trigger input (TTRGPn pin input) edge. Regarding TOPn1 output control, the reload register (TPnCCR1) is used as the duty setting register and the compare register (TPnCCR0) is used as the cycle setting register. The TPnCCR0 register and the TPnCCR1 register can be rewritten when TPnCE = 1. In order for the setting value when the TPnCCR0 register and the TPnCCR1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the CCRm buffer register), it is necessary to rewrite TPnCCR0 and then write to the TPnCCR1 register before the 16-bit counter value and the TPnCCR0 register value match. Thereafter, the values of the TPnCCR0 and the TPnCCR1 register are reloaded upon a TPnCCR0 register match. Whether to enable or disable the next reload timing is controlled by writing to the TPnCCR1 register. Thus even when wishing only to rewrite the value of the TPnCCR0 register, also write the same value to the TPnCCR1 register. Reload is disabled even when only the TPnCCR0 register is rewritten. To stop timer P, set TPnCE = 0. If the external trigger (TTRGPn pin input) edge is detected several times in the external trigger pulse mode, the 16-bit counter is cleared at the edge detection timing and count-up starts. To realize the same function (software trigger pulse mode) as external trigger pulse mode using a software trigger instead of external trigger input (TTRGPn pin input), set the TPnEST bit of the TPnCTL1 register to 1 so that the software trigger is output. The external trigger pulse waveform is output from TOPn1. The TOPn0 pin performs toggle output upon a match between the TPnCCR0 register and the 16-bit counter. Since the TPnCCR0 register and the TPnCCR1 register have their function fixed to that of a compare register in the external trigger pulse mode, they cannot be used for capture operation in this mode. Caution: In the external trigger pulse output mode, the external event clock input (TEVTPn) is prohibited (TPnCTL1.TPnEEE = 0). Remarks: 1. For the reload operation when TPnCCR0 and TPnCCR1 are rewritten during timer operation, refer to 9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B). 2. n = 0 to 7 m = 0, 1 286 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-22: 16-Bit Timer/Event Counter P Flowchart of Basic Operation in External Trigger Pulse Output Mode START Initial settings * Clock selection (TPnCTL1. TPnEEE = 0) (TPnCTL0. TPnCKS2 to TPnCKS0) * External trigger pulse output mode setting (TPnCTL1. TPnMD2 to TPnMD0 = 010) * Compare register setting (TPnCCR0, TPnCCR1) External trigger (TIPn0 pin) input 16-bit counter clear & start Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register External trigger (TIPn0 pin) input 16-bit counter start Match between 16-bit counter and TPnCCR1Note INTTPnCC1 output Match between 16-bit counter and TPnCCR0, 16-bit counter clear & start INTTPnCC0 output Note: The 16-bit counter is not cleared upon a match between the 16-bit counter and the CCR1 buffer register. Remark: n = 0 to 7 User's Manual U16580EE3V1UD00 287 Chapter 9 Figure 9-23: 16-Bit Timer/Event Counter P Basic Operation Timing in External Trigger Pulse Output Mode TPnCE = 1 FFFFH D01 D02 D11 16-bit counter D11 D02 D12 D12 External trigger (TIPn0 pin) TPnCCR0 CCR0 buffer register D01 0000H D01 TPnCCR1 CCR1 buffer register D02 D11 0000H D02 D12 D11 D12 TOPn0 TOPn1 Remarks: 1. D01, D02: Setting value of TPnCCR0 register (0000H to FFFFH) D11, D12: Setting value of TPnCCR1 register (0000H to FFFFH) 2. TOPn1 output duty = (Setting value of TPnCCR1 register) / (Setting value of TP0CCR0 register) TOPn1 output cycle = (Setting value of TPnCCR0 register) x (Count clock cycle) 3. n = 0 to 7 288 User's Manual U16580EE3V1UD00 Chapter 9 16-Bit Timer/Event Counter P 9.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011B) In the one-shot pulse mode, setting TPnCE = 1 causes waiting on TPnEST bit setting (1) or TTRGPn pin edge detection triggerNote 1 with the 16-bit counter held at FFFFH. The 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the CCR1 buffer register transferred from the TPnCR1 register, TOPn1 becomes high level; Upon a match between the value of the 16-bit counter and the value of the CCR0 register transferred from the TPnCCR0 register, TOPn1 becomes low level and the 16-bit counter is cleared to 0000H and stops. Any trigger input past the first one during 16-bit counter operation is ignored. Be sure to input the second and subsequent triggers when the 16-bit counter has stopped at 0000H. In the one-shot pulse mode, the TPnCCR0 and TPnCCR1 registers can be rewritten when TPnCE = 1. The setting values rewritten to the TPnCCR0 and TPnCCR1 registers become valid following execution of a write instruction from the CPU, at which time they are transferred to the CCR0 buffer register and the CCR0 buffer register through anytime write, and become the values for comparison with the 16-bit counter value. The one-shot pulse waveform is output from the TOPn1 pin. The TOPn0 pin performs toggle output upon a match between the 16-bit counter and the TPnCCR0 registerNote 2. Since the TPnCCR0 and TPnCCR1 registers have their function fixed to that of a compare register in the one-shot pulse mode, they cannot be used for capture operation in this mode. Notes: 1. External trigger input pin (TTRGPn) is not available for TMP8 (n = 8). 2. Output pin (TOPn0) is not available for TMP8 (n = 8). Caution: In the one-shot pulse mode, the external event clock input (TEVTPn) is prohibited (TPnCTL1.TPnEEE = 0). Remark: n = 0 to 8 User's Manual U16580EE3V1UD00 289 Chapter 9 Figure 9-24: 16-Bit Timer/Event Counter P Flowchart of Basic Operation in One-Shot Pulse Mode START Initial settings * Clock selection (TPnCTL1: TPnEEE = 0) (TPnCTL0: TPnCKS2 to TPnCKS0) * One-shot pulse mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 011B) * Compare register setting (TPnCCR0, TPnCCR1) Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register Trigger wait status, 16-bit counter in standby at FFFFH External trigger (TEVTPn pin) input Note 1, or TPnEST = 1 16-bit counter start Trigger wait status, 16-bit counter in standby at 0000H Match between 16-bit counter and CCR1 buffer registerNote 2 Match between 16-bit counter and CCR0 buffer register, 16-bit counter clear INTTPnCC1 output INTTPnCC0 output Notes: 1. External trigger input (TTRGPn) is not available for TMP8 (n = 8). 2. The 16-bit counter is not cleared upon a match between the 16-bit counter and the CCR1 buffer register. Caution: The 16-bit counter is not cleared and trigger input is ignored even if trigger input is performed during the count-up operation of the 16-bit counter. Remark: n = 0 to 8 290 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-25: 16-Bit Timer/Event Counter P Timing of Basic Operation in One-Shot Pulse Mode TPnCE = 1 TPnEST = 1 FFFFH 16-bit counter D0 D0 Note 1 D1 D1 D0 D1 External trigger (TTRGPn)Note 2 TPnCCR0 CCR0 buffer register D0 0000H TPnCCR1 CCR1 buffer register D0 D1 0000H D1 INTTPnCC0 INTTPnCC1 TOPn1 TOPn0 Note 3 Notes: 1. The 16-bit counter starts counting up when either TPnEST = 1 is set or TEVTPn is input. 2. External trigger input pin (TTRGPn) is not available for TMP8 (n = 8). 3. Output pin (TOPn0) is not available for TMP8 (n = 8). Remarks: 1. D0: Setting value of TPnCCR0 register (0000H to FFFFH) D1: Setting value of TPnCCR1 register (0000H to FFFFH) 2. Delay time of one-shot pulse output (TOPn1) when external pin edge detection trigger is used: (TPnCCR1 value + 1) (Selected count clock) + 2/(fXX) + (TTRGPn input filter delay) 3. n = 0 to 8 User's Manual U16580EE3V1UD00 291 Chapter 9 16-Bit Timer/Event Counter P 9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B) In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used as the duty setting register and TMPn capture/compare register 0 (TPnCCR0) is used as the cycle setting register. Variable duty PWM is output by setting these two registers and operating the timer. The TPnCCR0 register and the TPnCCR1 register can be rewritten when TPnCE = 1. In order for the setting value when the TPnCCR0 register and the TPnCCR1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to CCR0 buffer register or CCR1 buffer register), it is necessary to rewrite TPnCCR0 and then write to the TPnCCR1 register before the 16-bit counter value and the TPnCCR0 register value match. Thereafter, the values of the TPnCCR0 register and the TPnCCR1 register are reloaded upon a TPnCCR0 register match. Whether to enable or disable the next reload timing is controlled by writing to the TPnCCR1 register. Thus even when wishing only to rewrite the value of the TPnCCR0 register, also write the same value to the TPnCCR1 register. Reload is disabled even when only the TPnCCR0 register is rewritten. To stop timer P, set TPnCE = 0. PWM waveform output is performed from the TOPn1 pin. The TOPn0 pinNote performs toggle output upon a match between the 16-bit counter and the TPnCCR0 register. Since the TPnCCR0 and TPnCCR1 registers have their function fixed that of a compare register in the PWM mode, they cannot be used for capture operation in this mode. Note: TOPn0 output pin is not available for TMP8 (n = 8). Remark: 292 n = 0 to 8 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-26: 16-Bit Timer/Event Counter P Flowchart of Basic Operation in PWM Mode (1/2) (a) Values of TPnCCR0, TPnCCR1 registers not rewritten during timer operation START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * PWM mode settings (TPnCTL1: TPnMD2 to TPnMD0 = 100B) * Compare register setting (TPnCCR0, TPnCCR1) Timer operation enable (TPnCE = 1) Transfer of TPnCCRm register values to CCRm buffer register Match between 16-bit counter and CCR1 buffer register, TOPn1 low-level output Match between 16-bit counter and CCR0 buffer register, 16-bit counter clear & start TOPn1 high-level output Remark: INTTPnCC1 output INTTPnCC0 output n = 0 to 8 m = 0, 1 User's Manual U16580EE3V1UD00 293 Chapter 9 Figure 9-26: 16-Bit Timer/Event Counter P Flowchart of Basic Operation in PWM Mode (2/2) (b) Values of TPnCCR0, TPnCCR1 registers rewritten during timer operation START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * PWM mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 100B) * Compare register setting (TPnCCR0, TPnCCR1) Timer operation enable (TPnCE = 1) Transfer of TPnCCRm register values to CCRm buffer register Match between 16-bit counter and TPnCCR1, TOPn1 low-level output INTTPnCC1 output Match between 16-bit counter and TPnCCR0, 16-bit counter clear & start, TOPn1 high-level output TPnCCR0 rewrite INTTPnCC0 output <1> Match between 16-bit counter and CCR1 <2> buffer register, TOPn1 low-level output TPnCCR1 rewrite INTTPnCC1 output Note <3> * Match between CCR0 buffer register and 16-bit counter * 16-bit counter clear & start * Values of TPnCCRm reloaded to CCRm buffer register Reload enable INTTPnCC0 output Note: The timing of <2> in the above flowchart may differ depending on the rewrite timing of steps <1> and <3> and the value of TPnCCR1, but make sure that step <3> comes after step <1>. Remark: 294 n = 0 to 8 m = 0, 1 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-27: 16-Bit Timer/Event Counter P Basic Operation Timing in PWM Mode (1/2) (a) TPnCCR1 value rewritten TPnCE = 1 FFFFH D00 D00 D00 D00 D11 16-bit counter D10 D10 D12 D00 TPnCCR0 CCR0 buffer register 0000H TPnCCR1 D00 D10 CCR1 buffer register 0000H D11 D10 D12 D11 D13 D12 D13 TOPn1 Note TOPn0 Note: TOPn0 output pin is not available for TMP8 (n = 8). Remarks: 1. D00: D10, D11, D12, D13: Setting value of TPnCCR0 register (0000H to FFFFH) Setting values of TPnCCR1 register (0000H to FFFFH) 2. TOPn1 output duty factor = / TOPn1 output cycle = x TOPn0 output toggle width = x (Setting value of TPnCCR1 register) (Setting value of TP0CCR0 register + 1) (Setting value of TPnCCR0 register + 1) (Count clock cycle) (Setting value of TPnCCR0 register + 1) (Count clock cycle) 3. n = 0 to 8 User's Manual U16580EE3V1UD00 295 Chapter 9 Figure 9-27: 16-Bit Timer/Event Counter P Basic Operation Timing in PWM Mode (2/2) (b) TPnCCR0, TPnCCR1 values rewritten TPnCE = 1 FFFFH D00 D01 D01 D02 16-bit counter D11 D11 D12 D10 D00 TPnCCR0 CCR0 buffer register 0000H D01 D02 D03 Note D01 D00 D02 D03 Same value write TPnCCR1 CCR1 buffer register D10 0000H D11 D10 D12 Note D11 D12 D12 TOPn1 Note 2 TOPn0 Notes: 1. Reload is not performed because the TPnCCR1 register was not rewritten. 2. TOPn0 output pin is not available for TMP8 (n = 8). Remarks: 1. D00, D01, D02, D03: Setting values of TPnCCR0 register (0000H to FFFFH) D10, D11, D12, D13: Setting values of TPnCCR1 register (0000H to FFFFH) 2. TOPn1 output duty factor = (Setting value of TPnCCR1 register) / (Setting value of TP0CCR0 register + 1) TOPn1 output cycle = (Setting value of TPnCCR0 register + 1) x (Count clock cycle) TOPn0 output toggle width = (Setting value of TPnCCR0 register + 1) x (Count clock cycle) 3. n = 0 to 8 296 User's Manual U16580EE3V1UD00 D12 Chapter 9 16-Bit Timer/Event Counter P 9.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101B) In the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the TPnCCS1 and TPnCCS0 bits. The settings of the TPnCCS1 and TPnCCS0 bits of the TPnOPT0 register are valid only in the free-running mode. TPnCCS1 Operation 0 Use TPnCCR1 register as compare register 1 Use TPnCCR1 register as capture register TPnCCS0 Operation 0 Use TPnCCR0 register as compare register 1 Use TPnCCR0 register as capture register (a) Using TPnCCR1 register as compare register An interrupt is output upon a match between the 16-bit counter and the CCR1 buffer register in the free-running mode (interval function). Rewrite during compare timer operation is enabled and performed with anytime write. (Once the compare value has been written, synchronization with the internal clock is done and this value is used as the 16-bit counter comparison value.) When timer output (TOPn1) has been enabled, TOPn1 performs toggle output upon a match between the 16-bit counter and the CCR1 buffer register. User's Manual U16580EE3V1UD00 297 Chapter 9 16-Bit Timer/Event Counter P (b) Using TPnCCR1 register as capture register The value of the 16-bit counter is saved to the TPnCCR1 register upon TIPn1 pinNote 1 edge detection. (c) Using TPnCCR0 register as compare register An interrupt is output upon a match between the 16-bit counter and the CCR0 buffer register in the free-running mode (interval function). Rewrite during compare timer operation is enabled and performed with anytime rewrite. When timer output (TOPn0) has been enabled, TOPn0Note 2 performs toggle output upon a match between the 16-bit counter and the CCR0 buffer register. (d) Using TPnCCR0 register as capture register The value of the 16-bit counter is saved to the TPnCCR0 register upon TIPn0 pinNote 1 edge detection. Notes: 1. Since TMP8 has no external input pin, the capture function can only be used internally for capturing the interrupt signal INTTT0CC0 of TMT0, or INTCM10 of TMENC1, into the TP8CCR0 register, or the interrupt signal INTTT0CC1 of TMT0, or INTCM11 of TMENC1 into the TP8CCR1 register respectively, which is specified by the TPIC22 bit of TPIC2 register (refer to 9.4 (9) TMP input control register 2 (TPIC2)). 2. TOPn0 output pin is not available for TMP8 (n = 8). Cautions: 1. In free-running mode the external event clock input (TEVTPn) is prohibited (TPnCTL1.TPnEEE = 0). 2. When an internal count clock fXX/16 (TPnCTL0.TPnCKS2-0) is selected in freerunning mode, and TPnCCR0 and/or TPnCCR1 are used as capture registers, the a value of FFFFH will be captured if a valid signal edge is input before the first count up. 298 User's Manual U16580EE3V1UD00 Chapter 9 Figure 9-28: 16-Bit Timer/Event Counter P Flowchart of Basic Operation in Free-Running Mode START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * Free-running mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 101B) TPnCCS1, TPnCCS0 setting TPnCCS1 = 0 TPnCCS1 = 1 TPnCCS1 = 0 TPnCCS1 = 1 TPnCCS0 = 0 TPnCCS0 = 0 TPnCCS0 = 1 TPnCCS0 = 1 Timer operation enable (TPnCE = 1) Transfer of TPnCCR0 and TPnCCR1 values to CCR0 buffer register CCR0 and CCR1 buffer registers respectively TIPn0 edge detection setting TIPn1 edge detection setting TIPn1, TIPn0 edge detection (TPnIS1, TPnIS0) (TPnIS3, TPnIS2) setting (TPnIS3 to TPnIS0) Timer operation enable (TPnCE = 1) Transfer of TPnCCR1 value to CCR1 buffer register Timer operation enable (TPnCE = 1) Transfer of TPnCCR0 (TPnCE = 1) value to CCR0 buffer register Match between CCR1 buffer register and 16-bit counter Timer operation enable TIPn1 edge detection, capture of 16-bit counter value to TPnCCR1 Match between CCR1 buffer register and 16-bit counter TIPn1 edge detection, capture of 16-bit counter value to TPnCCR1 Match between CCR0 buffer TIPn0 edge detection, capture of 16-bit counter value to TPnCCR0 register and 16-bit counter TIPn0 edge detection, Match between CCR0 buffer capture of 16-bit counter register and 16-bit counter 16-bit counter overflow value to TPnCCR0 16-bit counter overflow 16-bit counter overflow Remark: 16-bit counter overflow n = 0 to 8 User's Manual U16580EE3V1UD00 299 Chapter 9 (1) 16-Bit Timer/Event Counter P TPnCCS1 = 0, TPnCCS0 = 0 settings (interval function description) When TPnCE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running count-up operation continues until TPnCE = 0 is set. In this mode, when a value is written to the TPnCCR0 and TPnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1 buffer register (anytime write). In this mode, no one-shot pulse is output even when an one-shot pulse trigger is input. Moreover, when TPnOEm = 1 is set, TOPnm performs toggle output upon a match between the 16-bit counter and the CCRm buffer register. Figure 9-29: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0) TPnCE = 1 FFFFH D01 D11 D11 D00 D00 16-bit counter D10 TPnCCR0 CCR0 buffer register D00 0000H D01 D00 D01 TOPn0 Note INTTPnCC0 match interupt D10 TPnCCR1 CCR1 buffer register 0000H D11 D10 D11 INTTPnCC1 match interupt TOPn1 Note: TOPn0 output pin is not available for TMP8 (n = 8). Remarks: 1. D00, D01: Setting values of TPnCCR0 register (0000H to FFFFH) D10, D11: Setting values of TPnCCR1 register (0000H to FFFFH) 2. TOPnm output rises to the high level when counting is started. 3. n = 0 to 8 m = 0, 1 300 User's Manual U16580EE3V1UD00 Chapter 9 (2) 16-Bit Timer/Event Counter P TPnCCS1 = 1, TPnCCS0 = 1 settings (capture function description) When TPnCE = 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. During this time, values are captured by capture trigger operation and are written to the TPnCCR0 and TPnCCR1 registers. Regarding capture in the vicinity of overflow (FFFFH), judgment is made using the overflow flag (TPnOVF). However, if overflow occurs twice (2 or more free-running cycles), the capture trigger interval cannot be judged with the TPnOVF flag. In this case, the system should be revised. Figure 9-30: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 1) TPnCE = 1 FFFFH D10 D02 D00 D12 D01 16-bit counter D11 D03 TIPn0 TPnCCR0 0000H D00 D01 D02 D03 TIPn1 0000H TPnCCR1 D10 D11 D12 Remarks: 1. D00, D01: Values captured to TPnCCR0 register (0000H to FFFFH) D10, D11: Values captured to TPnCCR1 register (0000H to FFFFH) 2. TIPn0: Set to rising edge detection (TPnIS1, TPnIS0 = 01B) TIPn1: Set to falling edge detection (TPnIS3, TPnIS2 = 10B) 3. n = 0 to 7 User's Manual U16580EE3V1UD00 301 Chapter 9 (3) 16-Bit Timer/Event Counter P TPnCCS1 = 1, TPnCCS0 = 0 settings When TPnCE = 1 is set, the counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR0 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the CCR0 buffer register from the TPnCCR0 register as an interval function. Even if TPnOE1 = 1 is set to realize the capture function, the TPnCCR1 register cannot control TOPn1. Figure 9-31: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 0) TPnCE = 1 FFFFH D01 D11 D14D15 D10 D00 D00 D13 16-bit counter D12 D00 TPnCCR0 CCR0 buffer register D01 D00 0000H D01 INTTPnCC0 match interrupt TIPn1 TPnCCR1 0000H D10 D11 D12 D13 D15 D14 Remarks: 1. D00, D01: Setting values of TPnCCR0 register (0000H to FFFFH) D10, D11, D12, D13, D14, D15: Values captured to TPnCCR1 register (0000H to FFFFH) 2. TIPn1: Set to detection of both rising and falling edges (TPnIS3, TPnIS2 = 11B) 3. n = 0 to 7 302 User's Manual U16580EE3V1UD00 Chapter 9 (4) 16-Bit Timer/Event Counter P TPnCCS1 = 0, TPnCCS0 = 1 settings When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR1 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value of the TPnCCR1 register as an interval function. When TPnOE1 = 1 is set, TOPn1 performs toggle output upon mach between the value of the 16-bit counter and the setting value of the TPnCCR1 register. Figure 9-32: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1) TPnCE = 1 FFFFH D02 D00 D03 D10 D12 D01 16-bit counter D11 D11 TIPn0 TPnCCR0 0000H D00 D01 D02 D03 INTTPnCC0 capture interrupt TPnCCR1 CCR1 buffer register D10 0000H D11 D10 D11 D12 D12 INTTPnCC1 Remarks: 1. D00, D01, D02, D03: Values captured to TPnCCR0 register (0000H to FFFFH) D10, D11, D12: Setting value of TPnCCR1 register (0000H to FFFFH) 2. TIPn0: Set to falling edge detection (TPnIS1, TPnIS0 = 10B) 3. n = 0 to 7 (5) Overflow flag When the counter overflows from FFFFH to 0000H in the free-running mode, the overflow flag (TPnOVF) is set to 1 and an overflow interrupt (INTTPnOV) is output. Be sure to confirm that the overflow flag (TPnOVF) is set to "1" when the overflow interrupt (INTTPnOV) has occurred. The overflow flag is cleared by writing 0 from the CPU. User's Manual U16580EE3V1UD00 303 Chapter 9 16-Bit Timer/Event Counter P 9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B) In the pulse width measurement mode, free-running count is performed. The value of the 16-bit counter is saved to capture register 0 (TPnCCR0), or capture register 1 (TPnCCR1) respectively, and the 16-bit counter is cleared upon edge detection of the TIPn0 pin, or TIPn1 respectively. The external input pulse width can be measured as a result. However, when measuring a large pulse width that exceeds 16-bit counter overflow, perform judgment with the overflow flag. Since measurement of pulses for which overflow occurs twice or more is not possible, adjust the operating frequency of the 16-bit counter. Depending on the selected capture input sources and specified edge detection three different measurement methods can be applied. <1> Pulse period measurement <2> Alternating pulse width and pulse space measurement: This requires a fast interrupt handling, in order to measure pulse width and pulse space correctly. <3> Simultaneous pulse width and pulse space measurement: Both capture inputs are required to measure pulse width and pulse space simultaneously. The measurements methods are explained in the following sub-chapters. Cautions: 1. In the pulse width measurement mode, the external event clock input (TEVTPn) is prohibited (TPnCTL1.TPnEEE = 0). 2. When an internal count clock fXX/16 (TPnCTL0.TPnCKS2-0) is selected in pulse width measurement mode, and a valid signal edge is input before the first count up, the a value of FFFFH will be captured in the corresponding TPnCCR0 or TPnCCR1 register. 3. Pulse width measurement cannot be performed by timer P8 (TMP8). Remark: 304 n = 0 to 7 User's Manual U16580EE3V1UD00 Chapter 9 (1) 16-Bit Timer/Event Counter P Pulse period measurement The pulse period of a signal can be measured in the pulse width measurement mode, when the edge detection of one of the inputs TIPn0 and TIPn1 is set either to "rising edge" or "falling edge". The detection of the other input should be set to "no edge detection". By detection of the specified edge the resulting value is captured in the corresponding capture register (TPnCCR0 or TPnCCR1), and the timer is cleared and restarts counting. Figure 9-33: Flowchart of Pulse Period Measurement START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * Pulse width measurement mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 110B) * Capture register setting (TPnCCR0, TPnCCR1) TIPn1/TIPn0 edge detection settingNote (TPnIS3 to TPnIS0) Timer operation enable (TPnCE = 1) Specified edge input to TIPnm (rising or falling edge), capture of value to TPnCCRm, 16-bit counter clear & start Note: External pulse input is possible for both TIPn0 and TIPn1, but only one should be selected for the pulse period measurement. Specify either "rising edge" or "falling edge" for edge detection. Specify the edge of the external input pulse that is not used as "no edge detection". Remark: n = 0 to 7 m = 0, 1 User's Manual U16580EE3V1UD00 305 Chapter 9 Figure 9-34: 16-Bit Timer/Event Counter P Basic Operation Timing of Pulse Period Measurement TPnCE = 1 FFFFH D01 FFFFH D02 16-bit counter D00 TIPn0 TPnCCR0 0000H D00 D01 D02 INTTPnCCR0 cleared by writing 0 from CPU TPnOVF INTTPnOV Remarks: 1. D00, D01, D02: Values captured to TPnCCR0 register (0000H to FFFFH) 2. TIPn0: Set to detection of rising edge (TPnIS1, TPnIS0 = 01B) 3. TIPn1: Set to no edge detection (TPnIS3, TPnIS2 = 00B) 4. n = 0 to 7 306 User's Manual U16580EE3V1UD00 Chapter 9 (2) 16-Bit Timer/Event Counter P Alternating pulse width and pulse space measurement The pulse period of a signal can be measured in the pulse width measurement mode alternating in one capture register, when the edge detection of one of the inputs TIPn0 and TIPn1 is set to "both rising and falling edges". The detection of the other input should be set to "no edge detection". By detection of a falling or rising edge the resulting value is captured in the corresponding capture register (TPnCCR0 or TPnCCR1), and the timer is cleared and restarts counting. Figure 9-35: Flowchart of Alternating Pulse Width and Pulse Space Measurement START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * Pulse width measurement mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 110B) * Capture register setting (TPnCCR0, TPnCCR1) TIPn1/TIPn0 edge detection settingNote (TPnIS3 to TPnIS0) Timer operation enable (TPnCE = 1) Rising edge input to TIPnm, capture of value to TPnCCRm, 16-bit counter clear & start Falling edge input to TIPnm, capture of value to TPnCCRm, 16-bit counter clear & start Note: External pulse input is possible for both TIPn0 and TIPn1, but only one should be selected for the alternating pulse width and pulse space measurement. Specify "both rising and the falling edges" for edge detection. Specify the edge of the external input pulse that is not used as "no edge detection". Remark: n = 0 to 7 m = 0, 1 User's Manual U16580EE3V1UD00 307 Chapter 9 Figure 9-36: 16-Bit Timer/Event Counter P Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement TPnCE = 1 FFFFH FFFFH D01 16-bit counter D02 D00 D03 D04 TIPn0 TPnCCR0 0000H D00 D01 D02 D03 D04 INTTPnCCR0 cleared by writing 0 from CPU TPnOVF INTTPnOV Remarks: 1. D00, D01, D02, D03, D04: Values captured to TPnCCR0 register (0000H to FFFFH) 2. TIPn0: Set to detection of both rising and falling edges (TPnIS1, TPnIS0 = 11B) 3. TIPn1: Set to no edge detection (TPnIS3, TPnIS2 = 00B) 4. n = 0 to 7 308 User's Manual U16580EE3V1UD00 Chapter 9 (3) 16-Bit Timer/Event Counter P Simultaneous pulse width and pulse space measurement Pulse width and pulse space can be measure simultaneously in the pulse width measurement mode, when the signal is input to both inputs TIPn0 and TIPn1, where both inputs detect opposite edges. Alternatively the signal can be input to TIPn0 only, when the capture source input selection for capture register 1 is used (ref. to 9.4 (7) TMP input control register 0 (TPIC0) and 9.4 (8) TMP input control register 1 (TPIC1)). By detection of the specified edge the resulting values of pulse width or pulse space are captured in the corresponding capture registers (TPnCCR0, TPnCCR1), and the timer is cleared and restarts counting. Figure 9-37: Flowchart of Simultaneous Pulse Width and Pulse Space Measurement START Initial settings * Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) * Pulse width measurement mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 110B) * Capture register setting (TPnCCR0, TPnCCR1) TIPn1/TIPn0 edge detection settingNote (TPnIS3 to TPnIS0) Timer operation enable (TPnCE = 1) Rising edge input to TIPnx, capture of value to TPnCCRx, 16-bit counter clear & start Falling edge input to TIPny, capture of value to TPnCCRy, 16-bit counter clear & start Note: External pulse input must be input to both TIPn0 and TIPn1, or to TIPn0 only, if the internal connection between both inputs is selected. Specify "rising edge" for edge detection of first input, and "falling edge" for the second input, or vice versa. Remark: n = 0 to 7 x = 0, 1 y = 0 when x = 1; y = 1 when x = 0 User's Manual U16580EE3V1UD00 309 Chapter 9 Figure 9-38: 16-Bit Timer/Event Counter P Basic Operation Timing of Simultaneous Pulse Width and Pulse Space Measurement TPnCE = 1 FFFFH FFFFH D10 16-bit counter D01 D00 D11 D02 TIPn0, TIPn1 Note TPnCCR0 0000H TPnCCR1 0000H D00 D01 D10 D02 D11 INTTPnCCR0 INTTPnCCR1 cleared by writing 0 from CPU TPnOVF INTTPnOV Note: The signal to measure has to be assigned to both inputs, TIPn0 and TIPn1. This can be done either by external pin connection, or internally when selecting TIPn1 input on TIPn0 pin. In case of internal connection the signal has to be input on TIPn0 pin. Remarks: 1. D00, D01, D02: 2. D10, D11: Values captured to TPnCCR0 register (0000H to FFFFH) Values captured to TPnCCR1 register (0000H to FFFFH) 3. TIPn0: Set detection to rising edge (TPnIS1, TPnIS0 = 01B) 4. TIPn1: Set detection to falling edge (TPnIS3, TPnIS2 = 10B) 5. n = 0 to 7 310 User's Manual U16580EE3V1UD00 Chapter 9 16-Bit Timer/Event Counter P 9.5.9 Counter synchronous operation function Timer P supports a function to start several timers P simultaneously. For this purpose two timer groups are defined, TMP0 to TMP3, as well as TMP4 to TMP7. For each timer group the counting of one to three slave counters (TMP1 to TMP3, or TMP5 to TMP7) can be synchronized with the corresponding master counter (TMP0 or TMP4). The synchronous operation function is enabled for each incorporated timer by the TPnSYE bit in the TPnCTL1 register (ref. to 9.4 (2) TMPn control register 1 (TPnCTL1)). When enabling the synchronous operation function, observe the following procedure: <1> Clear the synchronous mode selection bit TPmSYE of the master counter TMPm to 0. <2> Disable the count operation of the master counter TMPm (TPmCE = 0). <3> Enable the synchronous operation for each of the incorporated slave counters TMPs (TPsSYE = 1). <4> Enable the operation of the master counter TMPm (TPmCE = 1). Master and incorporated slave counters of that group start and clock synchronously. When the master counter is cleared, the slave counters are cleared synchronously too. Cautions: 1. In synchronous operation mode, the master counter can be used only in PWM mode (TPmMD2 to TPmMD0 = 100B), external trigger pulse output mode (TPmMD2 to TPmMD0 = 010B), one-shot pulse output mode (TPmMD2 to TPmMD0 = 011B), and free-running mode (TPmMD2 to TPmMD0 = 101B). 2. In synchronous operation mode, the slave counters can be used in free-running mode only (TPsMD2 to TPsMD0 = 101B). Remark: n = 0 to 7, m = 0, 4 s = 1 to 3, 5 to 7 User's Manual U16580EE3V1UD00 311 Chapter 9 16-Bit Timer/Event Counter P [MEMO] 312 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.1 Features Timer R is a 16-bit timer/counter that provides various motor control functions. * Count clock resolution: 31.25 ns min. (when using 32 MHz count clock) * General-purpose timer and operation mode supporting various motor control methods * Compare registers with reload buffers * 10-bit dead time counter - Dead time value independently settable through normal phase inverted phase normal phase * A/D conversion trigger signal generation - Generation of A/D conversion trigger with 2 compare registers, TRnCCR4 and TRnCCR5 - Dedicated output pin (TORn7) set with the TRnADTRG0 signal and reset with the TRnADTRG1 signal * Interrupt thinning out function - Thinning out rates of 1/1 to 1/32 * Forced output stop function: ESO - High-impedance output of pins TORn0 to TORn7 possible during ESOn input * Compare value setting - Reload (batch rewrite)/anytime rewrite mode selectable Note * Reload mode - Reload enabled by writing to TRnCCR1 register last, multiple registers simultaneity maintained - Peak/valley/peak and valley reload, transfer possible at reload timing Note - Provision of reload request flag TRnRSF - DMA transferable register address placement * High-accuracy T-PWM mode - 0 to 100% duty PWM output possible, including dead time reduction - Increased output resolution without software load, because presence/absence of added pulse to PWM output on up-count side can be controlled with LSB of compare register * 8 selectable count clocks: /2, /4, /8, /16, /32, /64, /256, /1024 * Active level of output pins TORn0 to TORn7 settable for each pin * Fail-safe function (error interrupt output possible) - Simultaneous active output detection function in normal phase/inverted phase Note: High-accuracy T-PWM mode User's Manual U16580EE3V1UD00 313 Chapter 10 16-bit Inverter Timer/Counter R 10.2 Configuration Timer R is configured of the following hardware. Table 10-1: Item Timer R Configuration Configuration Counters 16-bit counter x 1 16-bit sub-counter x 1 10-bit dead time counter x 3 Registers Timer Rn counter read register (TRnCNT) Timer Rn sub-counter read register (TRnSBC) Timer Rn dead time setting registers 0, 1 (TRnDTC0, TRnDTC1) Timer Rn capture/compare registers 0 to 3 (TRnCCR0-TRnCCR3) Timer Rn compare registers 4, 5 (TRnCCR4, TRnCCR5) TRnCCR0 to TRnCCR5 buffer registers TRnDTC0, TRnDTC1 buffer registers Timer input pins 3 (TIR10 to TIR13, TTRGR1, TEVTR1, ESOn)Note Timer output pins 8 (TORn0 to TORn7)Note Timer input signal - Timer output signal TRnADTRG0, TRnADTRG1 Control registers Timer Rn control registers 0, 1 (TRnCTL0, TRnCTL1) Timer Rn I/O control registers 0 to 4 (TRnIOC0 to TRnIOC4) Timer Rn option registers 0 to 3, 6, 7 (TRnOPT0 to TRnOPT3, TRnOPT6, TRnOPT7) Interrupt requests Compare match interrupts (INTTRnCC0 to INTTRnCC5) Peak interrupt (INTTRnCD) Valley interrupt (INTTRnOD) Overflow interrupt (INTTRnOV) Error interrupt (INTTRnER) Note: Alternate-function pins Remark: 314 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-1: Timer Rn Block Diagram Internal bus TRnSBC TRnCNT TRnSUF Counter control load TRnCUF 16-bit TMRn sub-counter TORn0 TORn1 CCR0 buffer TRnSUF TORn2 CCR1 buffer TRnDTC1 TORn4 Output control & dead time control CCR3 buffer fxx /2 fxx /4 fxx /8 fxx/16 fxx /32 fxx/64 fxx /256 fxx /1024 TORn3 TRnDTC0 CCR2 buffer CCR0TRnDTC1 TORn5 TORn6 TORn7 INTTRnER Counter control 16-bit TMRn counter TEVTR1 Note TIR10 TIR11 TIR12 TIR13 TRnCUF Note Note Note Note Edge detector TTRGR1 CCR4 buffer CCR5 buffer TRnCCR0 TRnADTRG0 TRnADTRG1 ADTRG control TRnCCR1 TRnCCR2 Note TRnCCR3 TRnCCR4 TRnCCR5 INTTRnO V INTTRnCC0 INTTRnCC1 INTTRnCC2 INTTRnCC3 INTTRnCC4 INTTRnCC5 INTTRnOD INTTRnCD Internal bus Note: Timer inputs are only available in TMR1 (n = 1). The TIR10 to TIR13 capture inputs are shared with TOR11 to TOR14. External trigger input TTRGR1 is shared with TIR10 output, and external event input TEVTR1 is shared with TIR17 output. Remarks: 1. n = 0, 1 2. fXX: Internal system clock User's Manual U16580EE3V1UD00 315 Chapter 10 (1) 16-bit Inverter Timer/Counter R TMRn capture/compare register 0 (TRnCCR0) The TRnCCR0 register is a 16-bit register provided with a capture function and a compare function. In the case of the free-running mode only, bit TRnCCS0 of the TRnOPT0 register is used to select use of the register as a capture register or as a compare register. In the pulse width measurement mode, this register can be used as a capture-only register. (The register cannot be used as a compare register.) In modes other than the free-running mode and the pulse width measurement mode, the register is used as a compare-only register. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, writing to bit 0 of the TRnCCR0 register is ignored. Moreover, bit 0 is read as 0. 2. n = 0, 1 Figure 10-2: After reset: 15 TMRn Capture/Compare Register 0 (TRnCCR0) 0000H 14 13 R/W 12 11 Address: 10 9 8 TR0CCR0 FFFFF598H, TR1CCR0 FFFFF5D8H 7 6 5 4 3 2 1 0 TRnCCR0 (a) Use as compare register When TRnCE = 1, the TRnCCR0 register write access method is as follows. Timer Rn Operation Mode TRnCCR0 Register Write Access Mode PWM mode, external trigger pulse output mode, triangular wave PWM mode, PWM mode with dead time Reload Free-running mode, external event count mode, one-shot pulse mode, interval timer mode Anytime rewrite High-accuracy T-PWM mode Reload/anytime rewrite switchable Remarks: 1. For details about the compare register rewrite operation, refer to 10.4.2 Compare register rewrite operation. 2. n = 0, 1 Caution: To set the carrier frequency in the high-accuracy T-PWM mode, set the TRnCCR0 register as follows. Number of count clocks of carrier frequency + TRnDTC0 register value + TRnDTC1 register value. For details about the carrier wave and dead time settings, refer to 10.10.9 10.10.9. (b) Use as capture register The counter value is saved to the TR1CCR0 register upon detection of the edge of the capture trigger (TIR10) input. Remark: 316 The capture function is provided only for TMR1. User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) TMRn capture/compare register 1 (TRnCCR1) The TRnCCR1 register is a 16-bit register that functions both as a capture register and a compare register. When a compare register is rewritten in the reload mode, the reload request flag (TRnRSF) becomes 1 when write access is performed to the TRnCCR1 register, and all the registers are rewritten at the same time at the next reload timing. In the free-running mode only, the TRnCCS1 bit of the TRnOPT0 register is used to select whether to use the TRnCCR1 register as a capture register or as a compare register. In the pulse width measurement mode, the TRnCCR1 register can be used as a dedicated capture register. (The register cannot be used as a compare register.) In modes other than the free-running mode and the pulse width measurement mode, all TRnCCR1 registers function as dedicated compare registers. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, when bit 0 is set to 1, the additional pulse control function is engaged. (For details about the additional pulse control function, refer to 10.10.9 10.10.9.) 2. n = 0, 1 Figure 10-3: After reset: 15 TMRn Capture/Compare Register 1 (TRnCCR1) 0000H 14 13 R/W 12 11 Address: 10 9 8 TR0CCR1 FFFFF59EH, TR1CCR1 FFFFF5DEH 7 6 5 4 3 2 1 0 TRnCCR1 (a) Use as compare register When TRnCE = 1, the TRnCCR1 register write access method is as follows. Timer Rn Operation Mode TRnCCR1 Register Write Access Mode PWM mode, external trigger pulse output mode, triangular wave PWM mode, PWM mode with dead time Reload Free-running mode, external event count mode, one-shot pulse mode, interval timer mode Anytime rewrite High-accuracy T-PWM mode Reload/anytime rewrite switchable Remarks: 1. For details about the compare register rewrite operation, refer to 10.4.2 Compare register rewrite operation. 2. n = 0, 1 (b) Use as capture register The counter value is saved to the TR1CCR1 register upon detection of the edge of the capture trigger (TIR11) input. Remark: The capture function is provided only for TMR1. User's Manual U16580EE3V1UD00 317 Chapter 10 (3) 16-bit Inverter Timer/Counter R TMRn capture/compare register 2 (TRnCCR2) The TRnCCR2 register is a 16-bit register that functions both as a capture register and compare register. In the free-running mode only, bit TRnCCS2 of the TRnOPT0 register is used to select whether to use the TRnCCR2 register as a capture register or a compare register. In the pulse width measurement mode, the TRnCCR2 register can be used as a dedicated capture register. (The register cannot be used as a compare register.) In modes other than the free-running mode and the pulse width measurement mode, all TRnCCR2 registers function as dedicated compare registers. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, when bit 0 is set to "1", the additional pulse control function is engaged. (For details about the additional pulse control function, refer to 10.10.9 10.10.9.) 2. n = 0, 1 Figure 10-4: After reset: 15 TMRn Capture/Compare Register 2 (TRnCCR2) 0000H 14 13 R/W 12 11 Address: 10 9 8 TR0CCR2 FFFFF59CH, TR1CCR2 FFFFF5DCH 7 6 5 4 3 2 1 0 TRnCCR2 (a) Use as compare register When TRnCE = 1, the TRnCCR2 register write access method is as follows. Timer Rn Operation Mode TRnCCR2 Register Write Access Mode PWM mode, external trigger pulse output mode, triangular wave PWM mode, PWM mode with dead time Reload Free-running mode, external event count mode, one-shot pulse mode, interval timer mode Anytime rewrite High-accuracy T-PWM mode Reload /anytime rewrite switchable Remarks: 1. For details about the compare register rewrite operation, refer to 10.4.2 Compare register rewrite operation. 2. n = 0, 1 (b) Use as capture register The counter value is saved to the TRnCCR2 register upon detection of the edge of the capture trigger (TIR12) input. Remark: 318 The capture function is provided only for TMR1. User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (4) TMRn capture/compare register 3 (TRnCCR3) the TRnCCR3 register is a 16-bit register that functions both as a capture register and a compare register. In the free-running mode only, bit TRnCCS3 of the TRnOPT0 register is used to select whether to use the TRnCCR3 register as a capture register or a compare register. In the pulse width measurement mode, the TRnCCR3 register can be used as a dedicated capture register. (The register cannot be used as a compare register.) In modes other than the free-running mode and the pulse width measurement mode, all TRnCCR3 registers function as dedicated compare registers. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, when bit 0 is set to "1", the additional pulse control function is engaged. (For details about the additional pulse control function, refer to 10.10.9 10.10.9.) 2. n = 0, 1 Figure 10-5: After reset: 15 TMRn Capture/Compare Register 3 (TRnCCR3) 0000H 14 13 R/W 12 11 Address: 10 9 8 TR0CCR3 FFFFF59AH, TR1CCR3 FFFFF5DAH 7 6 5 4 3 2 1 0 TRnCCR3 (a) Use as compare register When TRnCE = 1, the TRnCCR3 register write access method is as follows. Timer Rn Operation Mode TRnCCR3 Register Write Access Mode PWM mode, external trigger pulse output mode, triangular wave PWM mode, PWM mode with dead time Reload Free-running mode, external event count mode, one-shot pulse mode, interval timer mode Anytime rewrite High-accuracy T-PWM mode Reload/anytime rewrite switchable Remarks: 1. For details about the compare register rewrite operation, refer to 10.4.2 Compare register rewrite operation. 2. n = 0, 1 (b) Use as capture register The counter value is saved to the TR1CCR3 register upon detection of the edge of the capture trigger (TIR13) input. Remark: The capture function is provided only for TMR1. User's Manual U16580EE3V1UD00 319 Chapter 10 (5) 16-bit Inverter Timer/Counter R TMRn compare register 4 (TRnCCR4) The TRnCCR4 register is a 16-bit register that functions as a compare function. In the high-accuracy T-PWM mode and the PWM mode with dead time, the interrupt for matches between the counter and the TRnCCR4 register can be selected as the timing for A/D conversion trigger input. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, bit 0 of the TRnCCR4 register is ignored. 2. n = 0, 1 Figure 10-6: After reset: 15 0000H 14 13 TMRn Compare Register 4 (TRnCCR4) R/W 12 11 Address: 10 9 8 TR0CCR4 FFFFF592H, TR1CCR4 FFFFF5D2H 7 6 5 4 3 2 1 0 TRnCCR4 When TRnCE = 1, the TRnCCR4 register write access method is as follows. Timer Rn Operation Mode TRnCCR4 Register Write Access Mode PWM mode, external trigger pulse output mode, triangular wave PWM mode, PWM mode with dead time Reload Free-running mode, external event count mode, one-shot pulse mode, interval timer mode Anytime rewrite High-accuracy T-PWM mode Reload/anytime rewrite switchable Remarks: 1. For details about the compare register rewrite operation, refer to 10.4.2 Compare register rewrite operation. 2. n = 0, 1 320 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (6) TMRn compare register 5 (TRnCCR5) The TRnCCR5 register is a 16-bit compare register. In the high-accuracy T-PWM mode and the PWM mode with dead time, the interrupt for matches between the counter and the TRnCCR5 register can be selected as the timing for A/D conversion trigger input. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, bit 0 of the TRnCCR5 register is ignored 2. n = 0, 1 Figure 10-7: After reset: 15 0000H 14 13 TMRn Compare Register 5 (TRnCCR5) R/W 12 11 Address: 10 9 8 TR0CCR5 FFFFF590H, TR1CCR5 FFFFF5D0H 7 6 5 4 3 2 1 0 TRnCCR5 When TRnCE = 1, the TRnCCR5 register write access method is as follows. Timer Rn Operation Mode TRnCCR5 Register Write Access Mode PWM mode, external trigger pulse output mode, triangular wave PWM mode, PWM mode with dead time Reload Free-running mode, external event count mode, one-shot pulse mode, interval timer mode Anytime rewrite High-accuracy T-PWM mode Reload/anytime rewrite switchable Remarks: 1. For details about the compare register rewrite operation, refer to 10.4.2 Compare register rewrite operation. 2. n = 0, 1 User's Manual U16580EE3V1UD00 321 Chapter 10 (7) 16-bit Inverter Timer/Counter R TMRn counter read register (TRnCNT) The TRnCNT register is a timer read register that can read the values of the 16-bit counter. This register can only be read in 16-bit units. RESET input or setting TRnCE = 0 clears this register to 0000H. During the interval from when CE = 1 until count up, the value of the TRnCNT register is FFFFH. Figure 10-8: After reset: 15 0000H 14 TMRn Counter Read Register (TRnCNT) R 13 12 11 Address: 10 9 8 TR0CNT FFFFF5A4H, TR1CNT FFFFF5E4H 7 6 5 4 3 2 1 TRnCNT 0 Note Note: In the high-accuracy T-PWM mode, bit 0 is read as "0". Remark: (8) n = 0, 1 TMRn sub-counter read register (TRnSBC) The TRnSBC register can read the value of the 16-bit counter. This register can only be read in 16-bit units. RESET input or setting TRnCE = 0 clears this register to 0000H. Remarks: 1. In the high-accuracy T-PWM mode, this register can be used only in the PWM mode with dead time. 2. n = 0, 1 Figure 10-9: After reset: 15 0000H 14 TMRn Sub-Counter Read Register (TRnSBC) R 13 12 11 Address: 10 9 8 TR0SBC FFFFF5A6H, TR1SBC FFFFF5E6H 7 6 5 TRnSBC 3 2 1 0 Note Note: In the high-accuracy T-PWM mode, bit 0 is read as 0. 322 4 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (9) TMRn dead time setting register 0 (TRnDTC0) The TRnDTC0 register is a 10-bit register that specifies the dead time value. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. The dead time counter operates in the high-accuracy T-PWM mode and the PWM mode with dead time. In all other modes, be sure to set the TRnDTC0 register to 0000H. Cautions: 1. When TRnCE = 1, do not rewrite TRnDTC0 with a different value. 2. When the TRnDTC0 register is set to 0000H, dead time is not inserted. 3. Bits 0 and 10 to 15 are fixed to 0. Remark: n = 0, 1 Figure 10-10: After reset: TRnDTC0 0000H TMRn Dead Time Setting Register 0 (TRnDTC0) R/W Address: 15 14 13 12 11 10 0 0 0 0 0 0 9 8 TR0DTC0 FFFFF5A0H, TR1DTC0 FFFFF5E0H 7 6 5 4 3 2 1 0 0 (10) TMRn dead time setting register 1 (TRnDTC1) The TRnDTC1 register is a 10-bit register that specifies the dead time value. This register can be read and written in 16-bit units. Reset input clears this register to 0000H. The dead time counter operates in the high-accuracy T-PWM mode and the PWM mode with dead time. In all other modes, be sure to set the TRnDTC1 register to 0000H. Cautions: 1. When TRnCE = 1, do not rewrite TRnDTC1 with a different value. 2. When the TRnDTC1 register is set to 0000H, dead time is not inserted. 3. Bits 0 and 10 to 15 are fixed to 0. Remark: n = 0, 1 Figure 10-11: After reset: TRnDTC1 0000H TMRn Dead Time Setting Register 1 (TRnDTC1) R/W Address: 15 14 13 12 11 10 0 0 0 0 0 0 9 8 TR0DTC1 FFFFF5A2H, TR1DTC1 FFFFF5E2H 7 6 5 User's Manual U16580EE3V1UD00 4 3 2 1 0 0 323 Chapter 10 16-bit Inverter Timer/Counter R 10.3 Control Registers (1) TMRn control register 0 (TRnCTL0) The TRnCTL0 register is an 8-bit register that controls the operation of timer Rn. This register can be read and written in 8-bit or 1-bit units. RESET input changes the value of this register to initial setting 00H. Caution: When TRnCE = 1, do not rewrite bits other than bit TRnCE of the TRnCTL0 register. Figure 10-12: After reset: TRnCTL0 00H TMRn Control Register 0 (TRnCTL0) (1/2) R/W Address: TR0CTL0 FFFFF580H, TR1CTL0 FFFFF5C0H 7 6 5 4 3 TRnCE 0 0 0 0 2 1 0 TRnCKS2 TRnCKS1 TRnCKS0 (n = 0, 1) TRnCE Timer Rn Operation Control 0 Internal operating clock operation disabled (Reset timer Rn asynchronously) 1 Internal operating clock operation enabled When bit TRnCE is set to "0", the internal operation clock of timer Rn stops (fixed to low level), and timer Rn is set asynchronously. When bit TRnCE is set to "1", the internal operation of timer Rn is enabled from when bit TRnCE was set to "1" and count-up is performed. The time until count-up is as listed in Table 10-2, "TMRn Count Clock and Count Delay," on page 325. Remark: Remark: 324 By setting TRnCE = 0 following functions of timer Rn are reset. * Internal registers and internal latch circuits other than registers that can be written to/from the CPU * TRnOVF flag and flags in TRnOPT6 register * Counter, sub-counter, dead time counter, counter read register, sub-counter read register * TRnCCR0 to TRnCCR5 buffer registers, TRnDTC0 buffer register, and TRnDTC1 buffer register * Timer output (inactive level output) n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-12: TMRn Control Register 0 (TRnCTL0) (2/2) TRnCKS2 TRnCKS1 TRnCKS0 Internal Count Clock Selection of Timer Rn 0 0 0 fXX/2 0 0 1 fXX/4 0 1 0 fXX/8 0 1 1 fXX/16 1 0 0 fXX/32 1 0 1 fXX/64 1 1 0 fXX/256 1 1 1 fXX/1024 Caution: Set bits TRnCKS2 to TRnCKS0 when TRnCE = 0. When bit TRnCE is set from 0 to 1, bits TRnCKS2 to TRnCKS0 can be simultaneously set. Remark: Remark: fXX: System clock n = 0, 1 Table 10-2: TTnCKS1 TMRn Count Clock and Count Delay Count Clocks TTnCKS2 TTnCKS0 fXX/2 0 0 0 fXX/4 0 0 1 fXX/8 0 1 0 fXX/16 0 1 1 fXX/32 1 0 0 fXX/64 1 0 1 fXX/256 1 1 0 fXX/1024 1 1 1 Count Delay Minimum Maximum 3 base clocks 4 base clocks 4 base clocks 5 base clocks + 1 count clock Remarks: 1. fXX: System clock 2. fTMRn: Base clock of timer Rn (fTMRn = fXX/2) 3. n = 0, 1 User's Manual U16580EE3V1UD00 325 Chapter 10 (2) 16-bit Inverter Timer/Counter R TMRn control register 1 (TRnCTL1) The TRnCTL1 register is an 8-bit register that controls the operation of timer Rn. This register can be read and written in 8-bit or 1-bit units. RESET input changes the value of this register to initial setting 00H. Cautions: 1. In the one-shot pulse mode and external trigger pulse output mode, write access using "1", the same value as that of bit TRnEST, functions as one trigger. 2. Set bits TRnEEE and TRnMD2 to TRnMD0 when TRnCE = 0. (The same value as when TRnCE = 1 can be written). Do not perform rewrite when TRnCE = 1. Figure 10-13: After reset: TRnCTL1 00H TMRn Control Register 1 (TRnCTL1) (1/2) R/W Address: TR0CTL1 FFFFF581H, TR1CTL1 FFFFF5C1H 7 6 5 4 3 2 1 0 0 TRnEST TRnEEE 0 TRnMD3 TRnMD2 TRnMD1 TRnMD0 (n = 0, 1) TRnEST Software Trigger Control 0 No operation 1 Enables software trigger control * In one-shot pulse mode: One-shot pulse software trigger * In external trigger pulse output mode: Pulse output software trigger * The TRnEST bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output mode, if it is set to 1 when TRnCE = 1. Always write TRnEST = 1 when TRnCE = 1. * The read value of the TRnEST bit is always 0. TRnEEE Count Clock Specification 0 Use the internal clock (selected with bits TRnCKS2 to TRnCKS0 of the TRnCTL0 register) 1 Use external clock input (TEVTR1 pin input edge)Note * When TR1EEE = 1 (external clock input TEVTR1), the valid edge is specified by bits TR1EES1 and TR1EES0 of the TRnIOC2 register. Note: External clock input pin is not available for TMR0 (n = 0). Remark: 326 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-13: TMRn Control Register 1 (TRnCTL1) (2/2) TRnMD3 TRnMD2 TRnMD1 TRnMD0 0 0 0 0 Interval timer mode 0 0 0 1 External event count mode Note 1 0 0 1 0 External trigger pulse output mode Note 2 0 0 1 1 One-shot pulse mode 0 1 0 0 PWM mode 0 1 0 1 Free-running mode 0 1 1 0 Pulse width measurement mode Note 1 0 1 1 1 Triangular wave PWM mode 1 0 0 0 High accuracy T-PWM mode 1 0 0 1 PWM mode with dead time Other than above Timer Mode Selection Setting prohibited Notes: 1. Setting prohibited for TMR0. 2. For TMR0 an output pulse can be triggered only by software trigger (TR0EST = 1). Remark: n = 0, 1 User's Manual U16580EE3V1UD00 327 Chapter 10 (3) 16-bit Inverter Timer/Counter R TMRn I/O control register 0 (TRnIOC0) The TRnIOC0 register is an 8-bit register that controls the timer output (pins TORn0 to TORn3). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: If the dead time cannot be secured or if spikes (noise) may occur on the output pin, set the TRnIOC0 register when TRnCE = 0. When TRnCE = 1, the TRnIOC0 register can be write accessed using the same value. Figure 10-14: After reset: TRnIOC0 00H TMRn I/O Control Register 0 (TRnIOC0) R/W Address: TR0IOC0 FFFFF582H, TR1IOC0 FFFFF5C2H 7 6 5 4 3 2 1 0 TRnOL3 TRnOE3 TRnOL2 TRnOE2 TRnOL1 TRnOE1 TRnOL0 TRnOE0 (n = 0, 1) TRnOLm Timer Output Level Setting of TORnm Pin 0 Active level = High level 1 Active level = Low level TRnOEm Remark: 328 Timer Output Control (TORnm pin) 0 Disable timer output (inactive level is output) 1 Enable timer output n = 0, 1 m = 0 to 3 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (4) TMR1 I/O control register 1 (TR1IOC1) The TR1IOC1 register is an 8-bit register that controls the valid edge of external signal inputs (pins TIR10 to TIR13). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Cautions: 1. Set the TR1IOC1 register when TR1CE = 0. When TR1CE = 1, write access to the TR1IOC1 register can be performed using the same value. 2. The TR1IOC1 register is valid only in the free-running mode and the pulse width measurement mode. In all other modes, capture operation is not performed. Figure 10-15: After reset: TR1IOC1 00H TMR1 I/O Control Register 1 (TR1IOC1) R/W Address: FFFFF5C3H 7 6 5 4 3 2 1 0 TR1IS7 TR1IS6 TR1IS5 TR1IS4 TR1IS3 TR1IS2 TR1IS1 TR1IS0 TR1IS7 TR1IS6 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection TR1IS5 TR1IS4 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection TR1IS3 TR1IS2 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection TR1IS1 TR1IS0 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Capture Input (TIR13) Valid Edge Setting Capture Input (TIR12) Valid Edge Setting Capture Input (TIR11) Valid Edge Setting Capture Input (TIR10) Valid Edge Setting User's Manual U16580EE3V1UD00 329 Chapter 10 (5) 16-bit Inverter Timer/Counter R TMR1 I/O control register 2 (TR1IOC2) The TR1IOC2 register is an 8-bit register that controls the valid edge of external event count input (pin TEVTR1) and external trigger input (pin TTRGR1). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: Set the TR1IOC2 register when TR1CE = 0. When TR1CE = 1, write access to the TR1IOC2 register can be performed using the same value. Figure 10-16: After reset: TR1IOC2 00H R/W Address: 7 6 5 4 0 0 0 0 TR1EES1 TR1EES0 FFFFF5C4H 3 2 0 External Event Counter Input (TEVTR1) Valid Edge Setting 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Bits TR1EES1 and TR1EES0 are valid only when TR1CTL1 register bit TR1EEE = 1, or when the external event count mode (TR1CTL1 register bits TR1MD3 to TR1MD0 = 0001B) is set. TR1ETS1 TR1ETS0 External Trigger Input (TTRGR1) Valid Edge Setting 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Remark: 1 TR1EES1 TR1EES0 TR1ETS1 TR1ETS0 0 Remark: 330 TMR1 I/O Control Register 2 (TR1IOC2) Bits TR1ETS1 and TR1ETS0 are valid only when the external trigger pulse output mode or one-shot pulse mode (TR1CTL1 register bits TR1MD3 to TR1MD0 = 0010B or 0011B) is set. User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (6) TMRn I/O control register 3 (TRnIOC3) The TRnIOC3 register is an 8-bit register that controls timer output (pins TORn4 to TORn7). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: If the dead time cannot be secured or if spikes (noise) may occur on the output pin, set the TRnIOC3 register when TRnCE = 0. When TRnCE = 1, the TRnIOC0 register can be write accessed using the same value. Figure 10-17: After reset: TRnIOC3 00H TMRn I/O Control Register 3 (TRnIOC3) R/W Address: TR0IOC3 FFFFF585H, TR1IOC3 FFFFF5C5H 7 6 5 4 3 2 1 0 TRnOL7 TRnOE7 TRnOL6 TRnOE6 TRnOL5 TRnOE5 TRnOL4 TRnOE4 (n = 0, 1) TRnOLm Timer Output Level Setting of TORnm Pin 0 Active level = High level 1 Active level = Low level TRnOEm Remark: Timer Output Control (TORnm pin) 0 Disable timer output (inactive level is output) 1 Enable timer output n = 0, 1 m = 4 to 7 User's Manual U16580EE3V1UD00 331 Chapter 10 (7) 16-bit Inverter Timer/Counter R TMRn I/O control register 4 (TRnIOC4) The TRnIOC4 register is an 8-bit register that controls timer output error detection. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: Set the TRnIOC4 register when TRnCE = 0. When TRnCE = 1, write access to the TRnIOC4 register can be performed using the same value. Figure 10-18: After reset: 00H 7 TRnIOC4 0 TMRn I/O Control Register 4 (TRnIOC4) R/W 6 Address: 5 4 TRnTBA2 TRnTBA1 TRnTBA0 TR0IOC4 FFFFF586H, TR1IOC4 FFFFF5C6H 3 2 1 0 0 0 0 TRnEOC (n = 0, 1) TRnTBA2 0 No detection of simultaneous active state of pins TORn5 and TORn6 1 Detection of simultaneous active state of pins TORn5 and TORn6 Remark: If simultaneous active state is detected when TRnTBA2 = 1, the TRnTBF flag is set (1), and an error interrupt (INTTRnER) is output. TRnTBA1 Timer Outputs (TORn3/TORn4) True Bar Active Detection Control 0 No detection of simultaneous active state of pins TORn3 and TORn4 1 Detection of simultaneous active state of pins TORn3 and TORn4 Remark: If simultaneous active state is detected when TRnTBA1 = 1, the TRnTBF flag is set (1), and an error interrupt (INTTRnER) is output. TRnTBA0 Timer Outputs (TORn1/TORn2) True Bar Active Detection Control 0 No detection of simultaneous active state of pins TORn1 and TORn2 1 Detection of simultaneous active state of pins TORn1 and TORn2 Remark: If simultaneous active state is detected when TRnTBA0 = 1, the TRnTBF flag is set (1), and an error interrupt (INTTRnER) is output. TRnEOC Error Interrupt Output Control 0 Disable output of error interrupt (INTTRnER) 1 Enable output of error interrupt (INTTRnER) Remark: Remark: 332 Timer Outputs (TORn5/TORn6) True Bar Active Detection Control For details about error interrupt control, refer to 10.9 n = 0, 1 User's Manual U16580EE3V1UD00 Error Interrupts. Chapter 10 16-bit Inverter Timer/Counter R (8) TMRn option register 0 (TRnOPT0) The TRnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: When TR1CE = 1, do not rewrite bits TR1CCS3 to TR1CCS0. Figure 10-19: After reset: TR0OPT0 00H Address: FFFFF587H 6 5 4 3 2 1 0 0 0 0 0 0 TR0CMS TR0CUF TR0OVF 00H 7 R/W 6 Address: 5 4 TR1CCS3 TR1CCS2 TR1CCS1 TR1CCS0 TR1CCS3 FFFFF5C7H 3 2 1 0 0 TR1CMS TR1CUF TR1OVF TR1CCR3 register capture/compare selection 0 Select compare register 1 Select capture register Remark: Bit TR1CCS3 is only valid in the free-running mode. In all other modes, this bit is invalid. TR1CCS2 TR1CCR2 register capture/compare selection 0 Select compare register 1 Select capture register Remark: Bit TR1CCS2 is only valid in the free-running mode. In all other modes, this bit is invalid. TR1CCS1 TR1CCR1 register capture/compare selection 0 Select compare register 1 Select capture register Remark: Bit TR1CCS1 is only valid in the free-running mode. In all other modes, this bit is invalid. TR1CCS0 TRnCCR0 register capture/compare selection 0 Select compare register 1 Select capture register Remark: Remark: R/W 7 After reset: TR1OPT0 TMRn Option Register 0 (TRnOPT0) (1/2) Bit TR1CCS0 is only valid in the free-running mode. In all other modes, this bit is invalid. n = 0, 1 User's Manual U16580EE3V1UD00 333 Chapter 10 Figure 10-19: 16-bit Inverter Timer/Counter R TMRn Option Register 0 (TRnOPT0) (2/2) TRnCMS Compare Register Transfer Timing Mode Selection 0 Reload mode (batch rewrite): When the TRnCCR1 register is written to, all the registers are updated at the next reload timing (reload). Even if registers other than the TRnCCR1 register are written, reload is not executed. 1 Anytime rewrite mode: Each register is updated independently, and when write access is performed to a compare register, the register is updated to the value used during anytime write access. Several clocks are required until the value is transferred to the register following write. (Refer to 10.4.2 (1) Anytime rewrite.) Remark: The TRnCMS bit is valid only in the high-accuracy T-PWM mode, In all other modes it is invalid and has to be cleared (TRnCMS = 0). TRnCUF Timer R Counter Up/Down Detection Flag 0 The timer counter is in up count state. 1 The timer counter is in down count state. Remark: The TRnCUF bit is valid only in the high-accuracy T-PWM mode and triangular wave PWM mode. In all other modes, it is invalid (TRnCUF = 0). TRnOVF Timer R Overflow Detection Flag 0 No overflow occurrence (after bit was cleared) 1 Overflow occurrence Remarks: 1. The TRnOVF bit is set (1) when the 16-bit counter value overflows from FFFFH to 0000H. 2. The TRnOVF bit is cleared (0) when either 0 is written to it, or TRnCE = 0 is set. 3. When TRnOVF bit is set (1), an overflow interrupt (INTTRnOV) is simultaneously output. Cautions: 1. Overflow can only occur in the free-running mode and the T-PWM mode. If, in the high-accuracy T-PWM mode, the set conditions for the TRnDTC0 and TRnDTC1 registers are incorrect, the TRnOVF bit may be set (1). 2. When TRnOVF = 1, even if the TRnOVF bit and the TRnOPT0 register are read, the TRnOVF bit is not cleared. 3. The TRnOVF bit can be read and written, but even if "1" is written to TRnOVF bit from the CPU, this is ignored. Remark: 334 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (9) TMRn option register 1 (TRnOPT1) The TRnOPT1 register is an 8-bit register used to enable/disable peak/valley interrupts and set interrupt thinning out. This register can be read and written in 16-bit or 8-bit units. RESET input clears this register to 00H. Cautions: 1. The TRnOPT1 register write method is as follows. * In high-accuracy T-PWM mode: Anytime write, or reload write * In mode other than high-accuracy T-PWM mode: Reload write 2. Do not set TRnICE = 0 and TRnIOE = 0. Since reload does not occur when TRnICE, TRnIOE = 00, the TRnOPT1 register, which is a reload write register, stops being updated. Figure 10-20: After reset: TRnOPT1 00H TMRn Option Register 1 (TRnOPT1) (1/2) R/W Address: TR0OPT1 FFFFF58EH TR1OPT1 FFFFF5CEH 7 6 5 4 3 2 1 0 TRnICE TRnIOE TRnRDE TRnID4 TRnID3 TRnID2 TRnID1 TRnID0 (n = 0, 1) TRnICE 0 Disable peak interrupt (INTTRnCD) output in the counter's peak timing Interrupt thinning out is not performed. Reload operation is disabled in the counter's peak timing. 1 Enable peak interrupt (INTTRnCD) in the counter's peak timing Interrupt thinning out is performed. Reload operation is enabled in the counter's peak timing. Remark: Bit TRnICE is valid only in the PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. TRnIOE Valley Interrupt (INTTRnOD) Control 0 Disable valley interrupt (INTTRnOD) output in the counter's valley timing Reload operation is disabled in the counter's valley timing. 1 Enable valley interrupt (INTTRnOD) output in the counter's valley timing Reload operation is enabled in the counter's valley timing. Remark: Remark: Peak Interrupts (INTTRnCD) Control Bit TRnIOE is valid only in the high-accuracy T-PWM mode and triangular wave PWM mode. n = 0, 1 User's Manual U16580EE3V1UD00 335 Chapter 10 Figure 10-20: 16-bit Inverter Timer/Counter R TMRn Option Register 1 (TRnOPT1) (2/2) TRnRDE Reload Timing Thinning Out control 0 Don't perform reload thinning out Reload timing occurs at each peak/valley. 1 Perform reload thinning out Reload timing occurs at the same interval as interrupt thinning out. Remark: Bit TRnRDE is valid only in the PWM mode, high-accuracy T-PWM mode, triangular wave PWM output mode, and PWM mode with dead time. TRnID4 TRnID3 TRnID2 TRnID1 TRnID0 Interrupt Thinning Out Rate 0 0 0 0 0 No thinning out 0 0 0 0 1 1/2 0 0 0 1 0 1/3 0 * * * 0 * * * 0 * * * 1 * * * 1 * * * 1/4 * * * 1 1 1 0 1 1/30 1 1 1 1 0 1/31 1 1 1 1 1 1/32 Caution: If, when TRnCE = 1, the TRnOPT1 register is write accessed (including same value to bits TRnID4 to TRnID0), the interrupt thinning out counter is cleared. Remark: Remark: 336 Bits TRnID0 to TRnID4 are valid only in the PWM mode, high-accuracy T-PWM mode, triangular wave PWM mode, and PWM mode with dead time. n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (10) TMRn option register 2 (TRnOPT2) The TRnOPT2 register is an 8-bit register that controls A/D conversion trigger output (TRnADTRG0 signal). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: The settings of the TRnCCR5 and TRnCCR4 registers have an influence on the PWM output of pins TORn5 and TORn4 at the same time as the TRnADTRG0 signal output. Therefore, if setting bits TRnAT05 to TRnAT02, it is recommended to set the TRnOPT3 register as follows. * In the triangular wave PWM mode, when setting TRnAT05 = 1, set TRnOE5 = 0. * In the PWM mode and triangular wave PWM mode, when setting TRnAT04 = 1, set TRnOE5 = 0. * In the triangular wave PWM mode, when setting TRnAT03 = 1, set TRnOE4 = 0 * In the PWM mode and the triangular wave PWM mode, when setting TRnAT02 = 1, set TRnOE4 = 0. Figure 10-21: After reset: TRnOPT2 00H TMRn Option Register 2 (TRnOPT2) (1/2) R/W 7 6 0 0 Address: 5 4 TR0OPT2 FFFFF588H TR1OPT2 FFFFF5C8H 3 2 1 0 TRnAT05 TRnAT04 TRnAT03 TRnAT02 TRnAT01 TRnAT00 (n = 0, 1) TRnAT05 TRnAT04 A/D Converter Trigger Signal (TRnADTRG0) Generation with Occurrence of Compare Match Interrupt (INTTRnCCR5) 0 0 No trigger signal is generated when INTTRnCCR5 occurs. 0 1 Trigger signal is generated, when INTTRnCCR5 occurs and TMRn is counting up. 1 0 Trigger signal is generated, when INTTRnCCR5 occurs and TMRn is counting down. 1 1 Trigger signal is generated, when INTTRnCCR5 occurs in any state (TMRn is counting up or down) Cautions: 1. Bit TRnAT05 can be set to 1 only in the triangular wave PWM mode and high-accuracy T-PWM mode. In all other modes, be sure to set this bit to 0. 2. Bit TRnAT04 can be set to 1 only in the PWM mode, triangular wave PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. In all other modes, be sure to set this bit to 0. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 337 Chapter 10 Figure 10-21: TRnAT03 TRnAT02 16-bit Inverter Timer/Counter R TMRn Option Register 2 (TRnOPT2) (2/2) A/D Converter Trigger Signal (TRnADTRG0) Generation with Occurrence of Compare Match Interrupt (INTTRnCCR4) 0 0 No trigger signal is generated when INTTRnCCR4 occurs. 0 1 Trigger signal is generated, when INTTRnCCR4 occurs and TMRn is counting up. 1 0 Trigger signal is generated, when INTTRnCCR4 occurs and TMRn is counting down. 1 1 Trigger signal is generated, when INTTRnCCR4 occurs in any state (TMRn is counting up or down) Cautions: 1. Bit TRnAT03 can be set to 1 only in the triangular wave PWM mode and high-accuracy T-PWM mode. In all other modes, be sure to set this bit to 0. 2. Bit TRnAT02 can be set to 1 only in the PWM mode, high-accuracy T-PWM mode, triangular wave PWM mode, and PWM mode with dead time. In all other modes, be sure to set this bit to 0. TRnAT01 A/D Converter Trigger Signal (TRnADTRG0) Generation with Occurrence of Peak Interrupt (INTTRnCD) 0 No trigger signal is generated when peak interrupt (INTTRnCD) occurs. 1 Trigger signal is generated when peak interrupt (INTTRnCD) occurs after thinning out. Caution: Bit TRnAT01 can be set to 1 only in the PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. In all other modes, be sure to set this bit to 0. Remark: When bit TRnAT01 is set (1) the trigger signal coincides with the peak interrupt (INTTRnCD) controlled by the TRnOPT1 register (including thinning out). TRnAT00 A/D Converter Trigger Signal (TRnADTRG0) Generation with Occurrence of Valley Interrupt (INTTRnOD) 0 No trigger signal is generated when valley interrupt (INTTRnOD) occurs. 1 Trigger signal is generated when valley interrupt (INTTRnOD) occurs after thinning out. Caution: Bit TRnAT00 can be set to 1 only in the high-accuracy T-PWM mode and triangular wave PWM mode. In all other modes, be sure to set this bit to 0. Remark: Remark: 338 When bit TRnAT00 is set (1) the trigger signal coincides with the valley interrupt (INTTRnOD) controlled by the TRnOPT1 register (including thinning out). n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (11) TMRn option register 3 (TRnOPT3) The TRnOPT3 register is an 8-bit register that controls A/D conversion trigger output (signal TRnADTRG1). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: The settings of the TRnCCR5 and TRnCCR4 registers have an influence on the PWM outputs of pins TORn5, TORn4 at the same time as the TRnADTRG0 signal output. Therefore, if setting bits TRnAT15 to TRnAT12, it is recommended to set the TRnOPT3 register as follows. * In the triangular wave PWM mode, when setting TRnAT15 = 1, set TRnOE5 = 0. * In the PWM mode and triangular wave PWM mode, when setting TRnAT14 = 1, set TRnOE5 = 0. * In the triangular wave PWM mode, when setting TRnAT13 = 1, set TRnOE4 = 0 * In the PWM mode and the triangular wave PWM mode, when setting TRnAT12 = 1, set TRnOE4 = 0. Figure 10-22: After reset: TRnOPT3 00H TMRn Option Register 3 (TRnOPT3) (1/2) R/W 7 6 0 0 Address: 5 4 TR0OPT3 FFFFF589H TR1OPT3 FFFFF5C9H 3 2 1 0 TRnAT15 TRnAT14 TRnAT13 TRnAT12 TRnAT11 TRnAT10 (n = 0, 1) TRnAT15 TRnAT14 A/D Converter Trigger Signal (TRnADTRG1) Generation with Occurrence of Compare Match Interrupt (INTTRnCCR5) 0 0 No trigger signal is generated when INTTRnCCR5 occurs. 0 1 Trigger signal is generated, when INTTRnCCR5 occurs and TMRn is counting up. 1 0 Trigger signal is generated, when INTTRnCCR5 occurs and TMRn is counting down. 1 1 Trigger signal is generated, when INTTRnCCR5 occurs in any state (TMRn is counting up or down) Cautions: 1. Bit TRnAT15 can be set to 1 only in the triangular wave PWM mode and high-accuracy T-PWM mode. In all other modes, be sure to set this bit to 0. 2. Bit TRnAT14 can be set to 1 only in the PWM mode, triangular wave PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. In all other modes, be sure to set this bit to 0. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 339 Chapter 10 Figure 10-22: 16-bit Inverter Timer/Counter R TMRn Option Register 3 (TRnOPT3) Format (2/2) TRnAT13 TRnAT12 A/D Converter Trigger Signal (TRnADTRG1) Generation with Occurrence of Compare Match Interrupt (INTTRnCCR4) 0 0 No trigger signal is generated when INTTRnCCR4 occurs. 0 1 Trigger signal is generated, when INTTRnCCR4 occurs and TMRn is counting up. 1 0 Trigger signal is generated, when INTTRnCCR4 occurs and TMRn is counting down. 1 1 Trigger signal is generated, when INTTRnCCR4 occurs in any state (TMRn is counting up or down) Cautions: 1. Bit TRnAT13 can be set to 1 only in the triangular wave PWM mode and high-accuracy T-PWM mode. In all other modes, be sure to set this bit to 0. 2. Bit TRnAT12 can be set to 1 only in the PWM mode, high-accuracy T-PWM mode, triangular wave PWM mode, and PWM mode with dead time. In all other modes, be sure to set this bit to 0. TRnAT11 A/D Converter Trigger Signal (TRnADTRG1) Generation with Occurrence of Peak Interrupt (INTTRnCD) 0 No trigger signal is generated when peak interrupt (INTTRnCD) occurs. 1 Trigger signal is generated when peak interrupt (INTTRnCD) occurs after thinning out. Caution: Bit TRnAT11 can be set to 1 only in the PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. In all other modes, be sure to set this bit to 0. Remark: When bit TRnAT11 is set (1) the trigger signal coincides with the peak interrupt (INTTRnCD) controlled by the TRnOPT1 register (including thinning out). TRnAT10 A/D Converter Trigger Signal (TRnADTRG1) Generation with Occurrence of Valley Interrupt (INTTRnOD) 0 No trigger signal is generated when valley interrupt (INTTRnOD) occurs. 1 Trigger signal is generated when valley interrupt (INTTRnOD) occurs after thinning out. Caution: Bit TRnAT10 can be set to 1 only in the high-accuracy T-PWM mode and triangular wave PWM mode. In all other modes, be sure to set this bit to 0. Remark: Remark: 340 When bit TRnAT10 is set (1) the trigger signal coincides with the valley interrupt (INTTRnOD) controlled by the TRnOPT1 register (including thinning out). n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (12) TMRn option register 6 (TRnOPT6) The TRnOPT6 register is an 8-bit register that controls the various flags of timer Rn. This register can be read and written in 8-bit or 1-bit units. RESET input or setting TRnCE = 0 clears this register to 00H. Remark: For the functions of the various flags, refer to 10.6 Figure 10-23: After reset: TRnOPT6 00H Flags. TMRn Option Register 6 (TRnOPT6) R/W Address: TR0OPT6 FFFFF58CH TR1OPT6 FFFFF5CCH 7 6 5 4 3 2 1 0 0 0 0 0 0 TRnTBF TRnSUF TRnRSF (n = 0, 1) TRnTBF True Bar Active Detection Flag 0 Normal phase and inverted phase are not simultaneously active. 1 Normal phase and inverted phase are simultaneously active. This flag detects when the normal phase and inverted phase are simultaneously active, while any of bits TRnTBA2 to TRnTBA0 of the TRnIOC4 register is 1. When bits TRnTBA2 to TRnTBA0 = 000B, simultaneous active is not detected. Remarks: 1. The TRnTBF flag is set (1) upon detection that any of the normal phases (TORn1, TORn3, TORn5) and inverted phases (TORn2, TORn4, TORn6) are simultaneously active, and an error interrupt (INTTRnER) is output at such time. 2. This flag can be cleared by writing "0" to it. TRnSUF Timer R Sub-Counter Up/Down Detection Flag 0 Sub-counter is counting up 1 Sub-counter is counting down The TRnSUF flag detects sub-counter counting from 0000H until (TRnCCR0 register value - 2) as up count, and counting from TRnCCR0 register value until 0002H as down count. Remarks: 1. The TRnSUF flag is a read-only flag. 2. The TRnSUF flag is valid only in the high-accuracy T-PWM mode. TRnRSF Reload Suspension Flag 0 Write access to TRnCCR0 to TRnCCR5 and TRnOPT1 registers is enabled (no reload request, or completion of reload). 1 Write access to TRnCCR0 to TRnCCR5 and TRnOPT1 registers is disabled (reload request was output). The TRnRSF flag indicates output of a reload request. It indicates that the data to be transferred next will be held in the TRnCCR0 to TRnCCR5 and TRnOPT1 registers. The TRnRSF flag is set (1) upon write to the TRnCCR1 register, and cleared (0) upon reload completion. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 341 Chapter 10 16-bit Inverter Timer/Counter R (13) TMRn option register 7 (TRnOPT7) The TRnOPT7 register is an 8-bit register that controls time output switching. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 10-24: After reset: TRnOPT7 00H TMRn Option Register 7 (TRnOPT7) R/W Address: TR0OPT7 FFFFF58DH TR1OPT7 FFFFF5CDH 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TRnTOS (n = 0, 1) TRnTOS Timer Output (TORn0) Switching Control 0 Output counter's (TRnCNT) up/down count flag to TORn0 pin 1 Output sub-counter's (TRnSBC) up/down count flag to TORn0 pin When TRnTOS = 0, the status of bit TRnCUF of the TRnOPT0 register is output to pin TORn0. When TRnTOS = 1, the status of bit TRnSUF of the TRnOPT6 register is output to the TORn0 pin. Remark: Remark: 342 The TRnTOS bit is valid only in the high-accuracy T-PWM mode. n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.4 Basic Operation 10.4.1 Basic counter operation This section describes the basic operation of the 16-bit counter. For details, refer to the description of the operation of each mode. (1) Count start operation The 16-bit counter of timer R starts counting from initial value FFFFH in all the modes except the high-accuracy T-PWM mode. The counter counts up FFFFH, 0000H, 0001H, 0002H, 0003H, ... For the count operation in the high-accuracy T-PWM mode refer to section 10.10.9 10.10.9. (2) Clear operation The 16-bit counter is cleared to 0000H upon a match between the 16-bit counter and the compare register. Counting immediately following the start of count operation and counting from FFFFH to 0000H in the case of overflow are not detected as clear operations. (3) Overflow operation 16-bit counter overflow occurs when the value of the 16-bit counter changes from FFFFH to 0000H. When overflow occurs, bit TRnOVF of the TRnOPT0 register is set (to 1), and an interrupt (INTTRnOV) is output. No overflow interrupt (INTTRnOV) is output under the following conditions. * Immediately after count operation start * When compare value is matched and cleared at FFFFH Caution: (4) Be sure to check that the overflow flag (TRnOVF) is set to 1 following output of the overflow interrupt (INTTRnOV). Counter read operation during count operation In the case of timer R, the value of the 16-bit counter can be read by the TRnCNT register during count operation. User's Manual U16580EE3V1UD00 343 Chapter 10 (5) 16-bit Inverter Timer/Counter R Interrupt operation In the case of timer R, the following interrupts are output. * INTTRnCC0: Functions as TRnCCRn0 buffer register match interrupt. * INTTRnCC1: Functions as TRnCCRn1 buffer register match interrupt. * INTTRnCC2: Functions as TRnCCRn2 buffer register match interrupt. * INTTRnCC3: Functions as TRnCCRn3 buffer register match interrupt. * INTTRnCC4: Functions as TRnCCRn4 buffer register match interrupt. * INTTRnCC5: Functions as TRnCCRn5 buffer register match interrupt. * INTTRnCD: Functions as a peak interrupt at the timing when the counter switches from down count to up count. * INTTRnOD: Functions as a valley interrupt at the timing when the counter switches from up count to down count. * INTTRnOV: Functions as an overflow interrupt. * INTTRnER: Functions as an normal phase/inverted phase simultaneous active detection interrupt. Remark: 344 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.4.2 Compare register rewrite operation In the PWM mode, high-accuracy T-PWM mode, PWM mode with dead time, external trigger pulse output mode, and triangular wave PWM mode, the reload function is valid. (In all other modes, reload-related settings are invalid.) The compare/control registers with the reload function are listed below. * TRnCCR0 to TRnCCR5 * TRnOPT1 Compare registers with the reload function can be rewritten in the following modes. * Anytime rewrite mode In this mode, each compare register is updated independently, and when a compare register is written to, the register is updated to the value written during anytime write access. * Reload mode (batch rewrite) When the TRnCCR1 register is written to, all the registers are updated at the next reload timing (reload). Reload does not occur even if a register other than the TRnCCR1 register is written to. A reload request flag (TRnRSF) is provided. The compare register can be rewritten using DMA transfer. DMA transfer is performed as follows. Address Register Name DMA Transfer Sequence FFFFF590H TR0CCR5 FFFFF592H TR0CCR4 FFFFF594H - Note FFFFF596H - Note FFFFF598H TR0CCR0 FFFFF59AH TR0CCR3 FFFFF59CH TR0CCR2 FFFFF59EH TR0CCR1 Address Register Name DMA Transfer Sequence FFFFF5D0H TR1CCR5 FFFFF5D2H TR1CCR4 FFFFF5D4H - Note FFFFF5D6H - Note FFFFF5D8H TR1CCR0 FFFFF5DAH TR1CCR3 FFFFF5DCH TR1CCR2 FFFFF5DEH TR1CCR1 Note: Dummy data transfer User's Manual U16580EE3V1UD00 345 Chapter 10 16-bit Inverter Timer/Counter R For details about the interrupt thinning out function specified by setting the TRnOPT1 register, refer to 10.7 Interrupt Thinning Out Function. Mode Rewrite Timing Interval mode Anytime rewrite External event count mode Anytime rewrite External trigger pulse output mode Reload One-shot pulse mode Anytime rewrite PWM mode Reload Free-running mode Anytime rewrite Pulse width measurement mode Reload Triangular wave PWM mode Reload Note 1 High-accuracy T-PWM mode Anytime rewrite, Reload Note 2 PWM mode with dead time Reload Notes: 1. Rewrite is performed upon valley interrupt. 2. Set with TRnOPT0 register bit TRnCMS = 0, TRnOPT1 register bit TRnRDE = 0 346 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (1) Anytime rewrite Anytime rewrite is set by setting TRnOPT0 register bit TRnCMS = 1. The TRnOPT1 register bit TRnRDE setting is ignored. In this mode, the value written to each compare register is immediately transferred to the internal buffer register and compared to the counter value. Following write to a compare register (TRnCCR0 register, etc.), the value is transferred to the internal buffer register after the lapse of 4 clocks (fTMRn). However, since only the TRnCCR1 register has a 2-stage configuration, the actual transfer timing is after the lapse of 5 clocks (fTMRn). Figure 10-25: Anytime Rewrite Timing D01 D01 D02 D21 Counter D21 D11 D11 D31 D21 D12 D12 D31 D31 D31 TRnCE TRnCCR0 TRnCCR0 buffer D01 0000H D02 D01 D02 INTTRnCC0 D11 TRnCCR1 TRnCCR1 buffer 0000H D12 D11 D12 INTTRnCC1 TRnCCR2 TRnCCR2 buffer D21 0000H D21 INTTRnCC2 D31 TRnCCR3 TRnCCR3 buffer 0000H D31 INTTRnCC3 TRnRSF Remarks: 1. D01, D02: D11, D12: D21: D31: L TRnCCR0 register setting value (0000H to FFFFH) TRnCCR1 register setting value (0000H to FFFFH) TRnCCR2 register setting value (0000H to FFFFH) TRnCCR3 register setting value (0000H to FFFFH) 2. Timing chart using interval timer mode as an example 3. n = 0, 1 User's Manual U16580EE3V1UD00 347 Chapter 10 16-bit Inverter Timer/Counter R (a) Cautions related to rewriting TRnCCR0 register in high-accuracy T-PWM mode When the TRnCCR0 register is rewritten during operation using the anytime rewrite function, anytime transfer of the value to the TRnCCR0 buffer register is not performed. The timing is shown below. "a" d1 "c" "b" d1 Counter TRnCCR0 "a" TRnCCR0 buffer Remark: "b" "a" "c" "b" "c" d1: TRnDTC1 setting value Following write to the TRnCCR0 register, the value of the TRnCCR0 register is transferred to the TRnCCR0 buffer register at the next peak or at the valley timing. Since TRnCMS = 1 (anytime rewrite), the settings of bits TRnIOE, TRnICE, TRnRDE, and TRnID4 to TRnID0 have no influence. (b) Cautions related to rewriting of TRnCCR1 to TRnCCR3 registers "i" Counter TRnCCR1,2,3 "i" "i" "i" "i" <1> <2> <3> <4> <1> <2> <3> <4> Rewrite in <1> interval (rewrite before match occurrence) In the case of rewrite before a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs, a match with the counter occurs following rewrite and the rewrite value is instantly reflected. Counter TRnCCR1 TRnCCR1 buffer TORn1 "i" "i" "i" "i" "k" "k" "k" "k" TORn2 348 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R If a value smaller than the counter value is written before match occurrence, no match occurs, so the following output wave results. Counter "i" TRnCCR1 TRnCCR1 buffer TORn1 "i" "r" "r" "r" "r" "i" "i" TORn2 Forced rise If no match occurs, the timer output remains unchanged. However, even if a match does not occur the timer output is forcibly changed to normal phase active level at peaks. Rewrite in <2> interval (rewrite after match occurrence) In the case of rewrite after a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs, further match occurrences are ignored, so the rewrite value is not reflected. Counter TRnCCR1 TRnCCR1 buffer TORn1 "i" "i" "i" "k" "k" "k" "k" "k" "k" TORn2 INTTRnCC1 *Matches due to rewrite after match occurrence are ignored, and the timer output remains unchanged. *The INTTRnCC1 signal becomes valid from the next match after up/down count is switched and the timer output changes. However, a match interrupt is output upon INTTRnCC1 interrupt output. User's Manual U16580EE3V1UD00 349 Chapter 10 16-bit Inverter Timer/Counter R Rewrite in <3> interval (rewrite before match occurrence) In the case of rewrite before a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs, a match with the counter occurs following rewrite and the rewrite value is instantly reflected. Counter TRnCCR1 TRnCCR1 buffer TORn1 "i" "i" "k" "k" "k" "k" "k" "i" TORn2 If a value larger than the counter value is written before match occurrence, no match occurs, so the following output wave results. Counter TRnCCR1 TRnCCR1 buffer TORn1 TORn2 "i" "i" "i" "r" "r" "r" "r" "r" Forced fall If no match occurs, the timer output remains unchanged. However, even if a match occurs, the timer output is forcibly changed to normal phase inactive level at valleys. 350 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Rewrite in <4> interval (rewrite after match occurrence) In the case of rewrite after a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs, further match occurrences are ignored, so the rewrite value is not reflected. Counter TRnCCR1 TRnCCR1 buffer TORn1 "i" "i" "i" "k" "k" "k" "k" "k" "i" TORn2 INTTRnCC1 *Matches due to rewrite after match occurrence are ignored, and the timer output remains unchanged. *The INTTRnCC1 signal becomes valid from the next match after up/down count is switched and the timer output changes. However, a match interrupt is output upon INTTRnCC1 interrupt output. (c) Cautions related to rewriting TRnOPT1 Since the internal interrupt thinning out counter is cleared when the TRnOPT1 register is written to, the interrupt output interval may temporarily become longer. User's Manual U16580EE3V1UD00 351 Chapter 10 (2) 16-bit Inverter Timer/Counter R Batch rewrite (reload mode) Batch rewrite is set by setting TRnOPT0 register bit TRnCMS = 0, TRnOPT1 register bit TRnRDE = 0, TRnICE = 1 (reload enabled at peaks), and TRnIOE = 1 (reload enabled at valleys). In this mode, the values written to the various compare registers are all transferred at the same time to the respective buffer registers at the reload timing. Figure 10-26: Basic Operation Flow during Batch Rewrite START Initial settings Timer operation enable (TRnCE = 1) Transfer of values of TRnCCR0 to TRnCCR3 to buffers TRnCCR0 to TRnCCR3 Read TRnRSF 1 TRnRSF 0 Rewrite TRnCCR0 Rewrite TRnCCR2 Any order Rewrite TRnCCR3 Rewrite TRnCCR1 *Match between counter and TRnCCR0 Reload enable INTTRnCC0 *Counter clear & start *Transfer of values of TRnCCR0 to TRnCCR3 to TRnCCR0 buffer Caution: Write access to the TRnCCR1 register includes also the reload enable operation. Therefore, rewrite the TRnCCR1 register after rewriting the other TRnCCR registers. Remarks: 1. This sample flow chart is for the PWM mode. 2. n = 0, 1 352 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-27: Batch Rewrite Timing (1/2) Counter Reload rewrite timing Reload upon TRnCCR1 write TRnCCR0 TRnCCR0 buffer TRnCCR1 TRnCCR1 buffer TRnCCR2 TRnCCR2 buffer TRnCCR3 TRnCCR3 buffer TRnCCR4 TRnCCR4 buffer TRnCCR5 TRnCCR5 buffer TRnOPT1 TRnOPT1 buffer Batch update at reload timing INTTRnCD0 INTTRnOD TRnRSF Setting of reload hold flag User's Manual U16580EE3V1UD00 Flag clearing following reload 353 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-27: Batch Rewrite Timing (2/2) Counter Reload upon TRnCCR1 write TRnCCR0 TSnCCR0 buffer TRnCCR1 TSnCCR1 buffer TRnCCR2 TSnCCR2 buffer TRnCCR3 TSnCCR3 buffer TRnCCR4 TSnCCR4 buffer TRnCCR5 TSnCCR5 buffer TRnOPT1 TSnOPT1 buffer Batch update at reload timing INTTRnCD0 TRnRSF 354 Setting of reload hold flag User's Manual U16580EE3V1UD00 Flag clearing following reload Chapter 10 16-bit Inverter Timer/Counter R (a) TRnCCR0 register rewrite operation in high-accuracy T-PWM mode When rewriting the TRnCCR0 register in the batch rewrite mode, the output waveform changes according to whether reload occurs at a peak or at a valley (TRnICE = 1, TRnIOE = 1 settings). Counter <1> <2> <1> <2> Rewrite in <1> interval (rewrite during up count) Since the next reload timing becomes the peak point, the cycle on the down count side changes and an asymmetrical triangular waveform is output. Also, since the cycle changes, reset the duty value as necessary. "m" Counter "n d1 "i" d1" value loaded to counter "k" "k" "k" "k" "k" "k" Reloadable timing TRnCCR0 TRnCCR0 buffer TRnCCR1 TRnCCR1 buffer TORn1 "m" "n" "m" "n" "i" "k" "i" "k" TORn2 INTTRnCD INTTRnOD Remark: d1: TRnDTC1 setting value User's Manual U16580EE3V1UD00 355 Chapter 10 16-bit Inverter Timer/Counter R "r "m" "i" Counter d1" value loaded to counter "r d1" d1 "k" "k" Reloadable timing TRnCCR0 TRnCCR0 buffer TRnCCR1 "m" "r" "m" "r" "i" "k" TRnCCR1 buffer TORn1 TORn2 INTTRnCD "k" "i" INTTRnOD Remark: d1: TRnDTC1 setting value The counter loads the TRnCCR0 value minus "d1" upon occurrence of reload in the high-accuracy T-PWM mode. As a result, the expected waveform can be output even if the cycle value is changed at the peak reload timing. Rewrite in <2> interval (rewrite during down count) Since the next reload timing becomes the valley point, the cycle value changes from the next cycle and the asymmetrical triangular waveform output is held. Since the cycle changes, be sure to set again the duty value as required. "m Counter "i" d1" "i" "n d1" "k" Reloadable timing TRnCCR0 TRnCCR0 buffer TRnCCR1 TRnCCR1 buffer TORn1 TORn2 "m" "n" "m" "n" "k" "i" "i" "k" INTTRnCD INTTRnOD Remark: 356 d1: TRnDTC1 setting value User's Manual U16580EE3V1UD00 "k" "k" "k" Chapter 10 16-bit Inverter Timer/Counter R (b) TRnCCR1 to TRnCCR3 register rewrite operation in high-accuracy T-PWM mode Counter "r" "i" "r" "k" Reloadable timing TRnCCR1 TRnCCR1 buffer TORn1 TORn2 "i" "k" "i" "r" "r" "k" INTTRnCC1 <1> Remark: <2> <1> <2> When TRnDTC0 = 0, TRnDTC1 = 0 Rewrite in <1> interval (rewrite during up count) Since reload is performed at the peak interrupt timing, an asymmetric triangular waveform is output. Rewrite in <2> interval (rewrite during down count) Since reload is performed at the valley interrupt timing, an asymmetric triangular waveform is output. User's Manual U16580EE3V1UD00 357 Chapter 10 16-bit Inverter Timer/Counter R 10.4.3 List of outputs in each mode (1) Timer outputs in each mode The timer outputs (pins TORn0 to TORn7) in each mode are listed below. Table 10-3: Operation Mode List of Timer Outputs in Each Mode (1/2) TORn0 TORn1 TORn2 TORn3 Interval mode Toggle output upon TRnCCR0 compare match Toggle output upon TRnCCR1 compare match Toggle output upon TRnCCR2 compare match Toggle output upon TRnCCR3 compare match External event count mode Toggle output upon TRnCCR0 compare match Toggle output upon TRnCCR1 compare match Toggle output upon TRnCCR2 compare match Toggle output upon TRnCCR3 compare match External trigger pulse Toggle output upon output mode CCR0 compare match or external trigger input External trigger pulse External trigger pulse External trigger pulse waveform output waveform output waveform output One-shot pulse mode Active at count start. Inactive upon TRnCCR0 match. Active upon TRnCCR1 match. Inactive upon TRnCCR0 match. Active upon TRnCCR2 match. Inactive upon TRnCCR0 match. Active upon TRnCCR3 match. Inactive upon TRnCCR0 match. PWM mode Toggle output upon TRnCCR0 compare match PWM output upon TRnCCR1 compare match PWM output upon TRnCCR2 compare match PWM output upon TRnCCR3 compare match Free-running mode Toggle output upon TRnCCR0 compare match Toggle output upon TRnCCR1 compare match Toggle output upon TRnCCR2 compare match Toggle output upon TRnCCR2 compare match Pulse width measurement mode - - - - Triangular wave PWM mode Inactive during up count. Active during down count. PWM output upon TRnCCR1 compare match PWM output upon TRnCCR2 compare match High-accuracy T-PWM mode Inactive during counter or sub-counter up count. Active during down count. PWM output (with dead time) upon TRnCCR1 compare match Inverted phase output PWM output (with to TORn1 dead time) upon TRnCCR2 compare match PWM mode with dead time Toggle output upon TRnCCR0 compare match PWM output (with dead time) upon TRnCCR1 compare match Inverted phase output PWM output (with to TORn1 dead time) upon TRnCCR2 compare match 358 User's Manual U16580EE3V1UD00 PWM output upon TRnCCR3 compare match Chapter 10 16-bit Inverter Timer/Counter R Table 10-3: Operation Mode List of Timer Outputs in Each Mode (2/2) TORn4 TORn5 TORn6 TORn7 Interval mode Toggle output upon TRnCCR4 compare match Toggle output upon TRnCCR5 compare match - - External event count mode Toggle output upon TRnCCR4 compare match Toggle output upon TRnCCR5 compare match - - External trigger pulse External trigger pulse External trigger pulse output mode waveform output waveform output - - One-shot pulse mode High upon TRnCCR4 High upon TRnCCR5 match. Inactive upon match. Inactive upon TRnCCR0 match. TRnCCR0 match. - - PWM mode PWM output upon TRnCCR4 compare match PWM output upon TRnCCR5 compare match - Free-running mode Toggle output upon TRnCCR4 compare match Toggle output upon TRnCCR5 compare match - - - - Pulse width measurement mode - PWM output upon TRnCCR5 compare match - Pulse output upon A/D conversion trigger Note Triangular wave PWM mode PWM output upon TRnCCR4 compare match Pulse output upon A/D conversion trigger Note High-accuracy T-PWM mode Inverted phase output PWM output (with to TORn3 dead time) upon TRnCCR3 compare match Inverted phase output Pulse output upon to TORn5 A/D conversion trigger Note PWM mode with dead time Inverted phase output PWM output (with to TORn3 dead time) upon TRnCCR3 compare match Inverted phase output Pulse output upon to TORn5 A/D conversion trigger Note Note: For details on TORn7, refer to 10.4.3 (a) TORn7 pin output control. User's Manual U16580EE3V1UD00 359 Chapter 10 16-bit Inverter Timer/Counter R (a) TORn7 pin output control The A/D conversion signals can be output to pin TORn7. Pin TORn7 is set (to 1) by the TRnADTRG0 signal trigger, and it is reset (to 0) by the TRnADTRG1 signal trigger. If the TRnADTRG0 trigger occurs while pin TORn7 is set (to 1), its set (1) status is maintained. If the TRnADTRG1 trigger occurs while pin TORn7 is reset (0), the (0) status is maintained. If the TRnADTRG0 and TRnADTRG1 signal triggers occur simultaneously, pin TORn7 is reset (to 0). Figure 10-28: TORn7 Pin Output Timing 1 TRnCNT TRnCCR5 Case 1 TRnADT0 TRnADT1 TORn7 Case 2 TRnADT0 TRnADT1 TORn7 Case 3 TRnCCR4 TRnADT0 TRnADT1 TORn7 Remark: 360 Case 1: When TRnCCR4 < TRnCCR5, TRnOPT2 = 04H, TRnOPT3 = 10H Case 2: When TRnCCR4 < TRnCCR5, TRnOPT2 = 04H, TRnOPT3 = 20H Case 3: When TRnCCR4 < TRnCCR5, TRnOPT2 = 08H, TRnOPT3 = 10H User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) Interrupts in each mode The interrupts in each mode (INTTRnCC0 to INTTRnCC5, INTTRnOV, INTTRnER) are listed below. Table 10-4: Operation Mode Interval mode List of Interrupts in Each Mode (1/2) INTTRnCC0 INTTRnCC1 INTTRnCC2 INTTRnCC3 TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt External event count mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt External trigger pulse output mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt One-shot pulse mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt PWM mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt Free-running mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt Pulse width measurement mode TIR10 capture interrupt TIR11 capture interrupt TIR12 capture interrupt TIR13 capture interrupt Triangular wave PWM mode TIR10 capture interrupt TIR11 capture interrupt TIR12 capture interrupt TIR13 capture interrupt High-accuracy T-PWM mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt Note 1 Note 2 Note 2 Note 2 PWM mode with dead time TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare TRnCCR3 compare match interrupt match interrupt match interrupt match interrupt Note 3 Note 3 Note 3 Notes: 1. A compare match interrupt is output when the TRnDTC1 register is set to 000H. INTTRnCD can be used as the peak interrupt. 2. If set in the range of 0000H TRnCCRm < TRnDTC0, (TRnCCR0 - TRnDTC1)< TRnCCRm TRnCCR0 (m = 1 to 5), no compare match interrupt is output. 3. If set to TRnCCR0 < TRnCCRm (m to 1 to 5), no compare match interrupt is output. Remarks: 1. "-" in the table indicates inactive level output. 2. n = 0, 1 User's Manual U16580EE3V1UD00 361 Chapter 10 Table 10-4: Operation Mode 16-bit Inverter Timer/Counter R List of Interrupts in Each Mode (2/2) INTTRnOV INTTRnER TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt - - External event count mode TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt - - External trigger pulse output mode TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt - - One-shot pulse mode TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt - - PWM mode TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt - Free-running mode TRnCCR4 compare TRnCCR5 compare Overflow interrupt match interrupt match interrupt Interval mode INTTRnCC4 Pulse width measurement mode INTTRnCC5 - - TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt High-accuracy T-PWM mode TRnCCR4 compare TRnCCR5 compare Overflow interrupt match interrupt match interrupt Note 3 - Error interrupt Error interrupt Note 1 PWM mode with dead time TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt Note 2 - Overflow interrupt Triangular wave PWM mode Note 1 Error interrupt - Error interrupt Note 2 Notes: 1. If set in the range of 0000H TRnCCRm < TRnDTC0, (TRnCCR0 - TRnDTC1) < TRnCCRm TRnCCR0 (m = 1 to 5), no compare match interrupt is output. 2. If set to TRnCCR0 < TRnCCRm (m = 1 to 5), no compare match interrupt is output. 3. If a setting error has been made for TRnCCR0, TRnDTC0, TRnDTC1, an overflow interrupt (INTTRnOV) is output. Remarks: 1. "-" in the table indicates inactive level output. 2. n = 0, 1 362 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (3) A/D conversion triggers, peak interrupts, and valley interrupts in each mode The A/D conversion triggers, peak interrupts, and valley interrupts in each mode are listed below. Table 10-5: List of A/D Conversion Triggers, Peak Interrupts and Valley Interrupts in Each Mode Operation Mode TRnADTRG0 TRnADTRG1 INTTRnCD INTTRnOD Interval mode - - - - External event count mode - - - - External trigger pulse output mode - - - - One-shot pulse mode - - - - Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 Free-running mode - - - - Pulse width measurement mode - - - - Triangular wave PWM mode Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 - Valley interrupt at counter valley (upon switching from down to up count) High-accuracy T-PWM mode Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 Select from interrupts Peak interrupt INTTRnCD, INTTRnCC4, INTTRnCC5 PWM mode with dead time Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 Select from interrupts INTTRnCD, INTTRnCC4, INTTRnCC5 PWM mode Peak interrupt at same timing as INTTRnCC0 interrupt Peak interrupt at same timing as INTTRnCC0 interrupt - Valley interrupt at counter valley (upon switching from down to up count) - Remarks: 1. The INTTRnCD interrupt and INTTRnOD interrupt are the occurrence conditions following interrupt thinning out. 2. n = 0, 1 User's Manual U16580EE3V1UD00 363 Chapter 10 16-bit Inverter Timer/Counter R 10.5 Match Interrupts Match interrupts consist of compare match interrupts (INTTRnCC0 to INTTRnCC5), peak interrupts (INTTRnCD), and valley interrupts (INTTRnOD). For details about error interrupts, refer to 10.9 Error Interrupts. Compare match interrupts (INTTRnCC0 to INTTRnCC5) are interrupts that occur following a match between the TRnCCR0 to TRnCCR5 registers and the counter, and are output in all modes (no operation mode restrictions). Peak interrupts (INTTRnCD) are output in the PWM mode, triangular wave PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. If the counter is a triangular wave operation mode (triangular wave PWM mode, high-accuracy PWM mode), a peak interrupt is output when the counter switches from up count to down count. If the counter is in a saw tooth wave operation mode (PWM mode, PWM mode with dead time), a peak interrupt occurs upon a match between the counter and the TRnCCR0 register (same timing as INTTRnCC0 interrupt). Valley interrupts occur when the counter switches from down count to up count in the triangular wave PWM mode and high-accuracy T-PWM mode. Figure 10-29: Interrupt Signal Output Example (1/2) FFFFH x=p k j Counter x d1 k k j j i i i TRnDTC0 0H TRnCCR0 p (for cycle setting) TRnCCR1 TRnCCR2 i (U phase duty) TRnCCR3 k (W phase duty) TRnDTC0 d0 TRnDTC1 d1 j (V phase duty) INTTRnCC1 INTTRnCC2 INTTRnCC3 INTTRnCD0 (peak interrupt) INTTRnOD (valley interrupt) 364 User's Manual U16580EE3V1UD00 k Chapter 10 16-bit Inverter Timer/Counter R Figure 10-29: Interrupt Signal Output Example (2/2) FFFFH p p Counter 0H TRnCCR0 p TRnCCR1 TRnCCR2 i TRnCCR3 k TRnCCR3 l j INTTRnCC0 INTTRnCC1 INTTRnCC2 INTTRnCC3 INTTRnCC4 INTTRnCD0 (peak interrupt) INTTRnOD (valley interrupt) User's Manual U16580EE3V1UD00 365 Chapter 10 16-bit Inverter Timer/Counter R 10.5.1 Compare match interrupt related cautions (1) Cautions in high-accuracy T-PWM mode Compare match interrupts occur upon a match between the counter and a compare register (TRnCCR0 to TRnCCR5). However, in the high-accuracy T-PWM mode, the compare register can be set exceeding the counter's count operation range. Therefore, under the following conditions, no compare interrupt is output. * Restrictions related to compare match interrupt with TRnCCR0 register (INTTRnCC0) In the high-accuracy T-PWM mode, when TRnDTC1 000H, no compare match interrupt (INTTRnCC0) is output. (Use INTTRnOD (valley interrupt) and INTTRnCD (peak interrupt) as the cycle interrupts.) * Restrictions related to TRnCCR1 to TRnCCR3 register In the high-accuracy T-PWM mode, if set in the range of 0000H TRnCCRm < TRnDTC0, (TRnCCR0 - TRnDTC1) < TRnCCRm TRnCCR0, no interrupt occurs upon a match between the compare value and the counter. TRnSBC TRnCCR0 TRnCCR0 -TRnDTC1 TRnCCRm setting range in which no INTTRnCC1m interrupt occurs TRnCNT TRnCCRm setting range in which INTTRnCC1m interrupt occurs TRnDTC0 TRnCCRm setting range in which no INTTRnCC1m interrupt occurs 0000H Remark: m = 1 to 3 * Restrictions related to TRnCCR4 and TRnCCR5 registers In the high-accuracy T-PWM mode, if set in the range of 0000H TRnCCR4, TRnCCR5 < TRnDTC0, (TRnCCR0 - TRnDTC1) < TRnCCR4, TRnCCR5 TRnCCR0, no compare match interrupt is output since no match between the compare value and counter occurs. When TRnCCR4 and TRnCCR5 registers are used as trigger causes for A/D triggers, perform setting in the range of TRnDTC0 TRnCCR4, TRnCCR5 (TRnCCR0 - TRnDTC1). TRnSBC TRnCCR0 TRnCCR0 -TRnDTC1 TRnCNT Setting range of TRnCCR4 or TRnCCR5, in which INTTRnCC4 or INTTRnCC5 interrupts occur TRnDTC0 0000H 366 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) Cautions in PWM mode with dead time Compare match interrupts are output upon a match between the counter and compare registers (TRnCCR0 to TRnCCR5). However, in the high-accuracy T-PWM mode, the compare register can be set exceeding the counter's count operation range. Therefore, under the following conditions, no compare interrupt is output. * Restrictions related to TRnCCRm In the PWM mode with dead time, if setting is performed in the following range, no match between the compare value and counter occurs, and no compare match interrupt is output: When TRnCCR0 < TRnCCRm (TRnCCR0 + TRnDTC0), TRnCCR4, TRnCCR5 registers are used as trigger causes for A/D triggers, perform settings with TRnCCR4, TRnCCR5 TRnCCR0. TRnCCR0 +TRnDTC0 TRnSBC TRnCCR0 TRnCNT Setting range in which INTTRnCCm interrupts are not output Setting range in which INTTRnCCm interrupts are output 0000H Remark: m = 1 to 5 User's Manual U16580EE3V1UD00 367 Chapter 10 16-bit Inverter Timer/Counter R 10.6 Flags 10.6.1 Up count flags Timer Rn has two counters, a counter and a sub-counter. TRnCUF is the counter's up/down status flag. It operates in the triangular wave PWM mode and highaccuracy T-PWM mode, and is fixed to 0 in all other modes. TRnSUF is the sub-counter's up/down status flag. It operates in the high-accuracy T-PWM mode, and is fixed to 0 in all other modes. For both TRnCUF and TRnSUF, 0 indicates the up count status, and 1 indicates the down count status. Figure 10-30: FFFEH Up Count Flags Timings (1/2) TRnCCR0 X=p d1 Sub-counter x Counter TRnDTC0 0H TRnCUF TRnSUF In the triangular wave PWM mode, the values of TRnCUF are as follows. 0 counter < TRnCCR0+1 ... 0 (up count) TRnCCR0+1 counter > 0 ... 1 (down count) In the high-accuracy T-PWM mode, the values of TRnCUF/TRnSUF are as follows. [TRnCUF] TRnDTC0 counter < (TRnCCR0 - TRnDTC1) ...0 (up count) TRnCCR0-TRnDTC1 counter > TRnDTC0 ... 1 (down count) [TRnSUF] 0 sub-counter < TRnCCR0 ...0 (up count) TRnCCR0 sub-counter > 0 ...1 (down count) 368 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-30: Up Count Flags Timings (2/2) TRnCCR0TRnDTC1 TSnCCR0 TRnDTC0 Counter 0000H Sub-counter TRnCUF TRnSUF TORn0 TORn0 TRnTOS = 0 sub-counter up/down status output to TORn0 TRnTOS = 1 sub-counter up/down status output to TORn0 10.6.2 Normal phase/inverted phase simultaneous active detection flag Timer Rn has a flag (TRnTBF) that detects normal phase/inverted phase simultaneous active states. The TRnTBF flag is valid in the PWM mode, triangular wave PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. Figure 10-31: Normal Phase/Inverted Phase Simultaneous Active Detection Flag Timing Counter TORn1 TORn1 TORn2 TORn2 TRnTBA0 TRnTBA0 "1" INTTRnER "1" INTTRnER TRnTBF TRnTBF 0 write clear Set after 1 base clock 0 write clear Set after 1 base clock User's Manual U16580EE3V1UD00 369 Chapter 10 16-bit Inverter Timer/Counter R 10.6.3 Reload hold flag In the case of timer Rn, the reload hold flag (TRnRSF) is set to "1" upon occurrence of a reload request (when the TRnCCR1 register is written to). When reload occurs and the values are transferred to all the buffer registers, the reload hold flag is cleared to "0". The TRnRSF flag is valid in the following operation modes. * External trigger pulse output mode * PWM mode * Triangular wave PWM mode * High-accuracy T-PWM mode (TRnCMS = 0) * PWM mode with dead time Caution: The TRnRSF flag is set to "1" following the lapse of 4 base clocks after TRnCCR1 register write completion. Figure 10-32: TRnCCR1 TRnCCR1 buffers x TRnCCR1 y x Reload Hold Flag Timings x TRnCCR1 buffers y TRnRSF y TRnRSF Reload timing TRnCCR1 TRnCCR1 buffers y x Reload timing x y x y TRnRSF Reload thinning out period 370 Reload timing User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.7 Interrupt Thinning Out Function The operations related to the interrupt thinning out function are indicated below. * The interrupts subject to thinning out are INTTRnCD (peak interrupt) and INTTRnOD (valley interrupt). * TRnOPT1 register bit TRnICE is used to enable INTTRnCD interrupt output and to specify thinning out count targets. * TRnOPT1 register bit TRnIOE is used to enable INTTRnOD interrupt output and to specify thinning out count targets. * TRnOPT2 register bit TRnRDE is used to specify reload thinning Yes/No. * If thinning out Yes is specified, reload is executed at the same timing as interrupt output following thinning out. * If thinning out No is specified, reload is executed at the reload timing after write access to the TRnCCR1 register. * The reload/anytime rewrite method can be specified with TRnOPT0 register bit TRnCMS. * When TRnCMS = 0, the register value is updated in synchronization with reload, but when TRnCMS = 1, the register value is updated immediately after write access. Caution: When write access is performed to the TRnOPT1 register, the internal thinning out counter is cleared when the register value is updated. Therefore, the interrupt interval may temporarily become longer than expected. To prevent this, it is recommended to set TRnCSM = 0 and TRnRDE = 1, and to change the interrupt thinning out count with the reloaded setting according to interrupt thinning out. Using this method, the interrupt interval is kept the same as the setting value. User's Manual U16580EE3V1UD00 371 Chapter 10 16-bit Inverter Timer/Counter R 10.7.1 Operation of interrupt thinning out function Figure 10-33: Interrupt Thinning Out Operations (1/2) (a) when TRnICE = 1, TRnIOE = 1 (peak/valley interrupt output) Counter TRnID4-0 = 00H (no th inning out ) INTTRnCD INTTRnOD TRnID4-0 = 01H (mask 1 ) INTTRnCD INTTRnOD TRnID4-0 = 02H (mask 2 ) INTTRnCD INTTRnOD TRnID4-0 = 03H (mask 3 ) INTTRnCD INTTRnOD TRnID4-0 = 04H (mask 4 ) INTTRnCD INTTRnOD TRnID4-0 = 05H (mask 5 ) INTTRnCD INTTRnOD TRnID4-0 = 06H (mask 6 ) INTTRnCD INTTRnOD 372 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-33: Interrupt Thinning Out Operations (2/2) (b) when TRnICE = 1, TRnIOE = 0 (peak interrupt only output) Counter TRnID4-0 = 00H (no th inning out ) INTTRnCD INTTRnOD TRnID4-0 = 01H (mask 1) INTTRnCD INTTRnOD TRnID4-0 = 02H (mask 2) INTTRnCD INTTRnOD TRnID4-0 = 03H (mask 3) INTTRnCD INTTRnOD TRnID4-0 = 04H (mask 4) INTTRnCD INTTRnOD (c) when TRnICE = 0, TRnIOE = 1 (valley interrupt only output) Counter TRnID4-0 = 00H (no t hinni ng out) INTTRnCD INTTRnOD TRnID4-0 = 01H (mask 1) INTTRnCD INTTRnOD TRnID4-0 = 02H (mask 2) INTTRnCD INTTRnOD TRnID4-0 = 03H (mask 3) INTTRnCD INTTRnOD TRnID4-0 = 04H (mask 4) INTTRnCD INTTRnOD User's Manual U16580EE3V1UD00 373 Chapter 10 16-bit Inverter Timer/Counter R 10.7.2 Operation examples when peak interrupts and valley interrupts occur alternately (1) Register settings Set both TRnOPT1 register bit TRnICE and TRnOPT1 register bit TRnIOE to 1. (2) Operation example Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (1/2) (a) when TRnCMS = 0, TRnRDE = 1 (Reload Thinning Out Control) (Recommended Settings) Counter INTTRnCD INTTRnOD 04 02 TRnIDS4 to 0 Reloa d* 02 TRnID4 to 0 04 Clear Interrupt thinning out counter 00 01 00 02 01 02 00 01 02 03 04 00 01 02 03 04 * Reload is executed at the thinned out interrupt output timing. All other reload timings are ignored. (b) when TRnCMS = 0, TRnRDE = 0 (No Reload Control) Counter INTTRnCD INTTRnOD TRnIDS4 to 0 02 04 Relo ad * TRnID4 to 0 02 04 Clear Interrupt thinning out counter 00 01 02 00 01 00 01 02 03 04 00 01 02 03 * Reload is executed at the reload timing after rewrite. 374 User's Manual U16580EE3V1UD00 04 00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (2/2) (c) when TRnCMS = 1, TRnRDE = x (anytime rewrite) Counter INTTRnCD INTTRnOD 02 TRnIDS4 to 0 04 Instantly reflected 02 TRnID4 to 0 04 Clear Interrupt thinning out counter 00 01 02 00 00 01 02 03 04 00 01 02 03 04 00 01 * Instantly reflected after rewrite. The reload timing is ignored. * The clear timing is transfer to the buffer, not register rewrite. 10.7.3 Interrupt thinning out function during counter saw tooth wave operation The operations related to the interrupt thinning out function during counter saw tooth wave operation (PWM mode, PWM mode with dead time) are indicated below. * The interrupt subject to thinning out is INTTRnCD (peak interrupt). The saw tooth wave operation occurs upon a match between the TRnCCR0 register and counter occurs. * TRnOPT1 register bit TRnICE is used to enable INTTRnCD interrupt output and to specify thinning out count targets. * The TRnOPT1 register bit TRnIOE setting is invalid. INTTRnOD interrupt output is prohibited. * TRnOPT1 register bit TRnRDE is used to specify reload thinning out Yes/No. * If thinning out Yes is specified, reload is executed at the same timing as interrupt output following thinning out. * If thinning out No is specified, reload is executed at the reload timing after write access to the TRnCCR1 register. Caution: When write access is performed to the TRnOPT1 register, the internal thinning out counter is cleared when the register value is updated. Therefore, the interrupt interval may temporarily become longer than expected. To prevent this, it is recommended to set TRnCSM = 0 and TRnRDE = 1, and to change the interrupt thinning out count with the reloaded setting according to interrupt thinning out. Using this method, the interrupt interval is kept the same as the setting value. User's Manual U16580EE3V1UD00 375 Chapter 10 16-bit Inverter Timer/Counter R 10.8 A/D Conversion Trigger Function This section describes the operation of the A/D conversion triggers output in the PWM mode, triangular wave PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. In these modes, the TRnCCR4 and TRnCCR5 registers are used as match interrupts and for the A/D conversion trigger function, with no influence on timer outputs in terms of the compare operation. For the A/D conversion triggers that can be output in each mode, refer to 10.4.3 (3) A/D conversion triggers, peak interrupts, and valley interrupts in each mode. Figure 10-35: A/D Conversion Trigger Output Controller TRnAT [05 04 03 02 01 00] Peak of TRnCNT Valley of TRnCNT TRnICE Thinning out circuit TRnIOE Thinning out circuit INTTRnOD INTTRnCD0 TRnADTRG0 INTTRnCC4 TRnCUF INTTRnCC5 TRnCUF TRnAT [15 14 13 12 11 10] S R TORn7 TRnADTRG1 The above figure shows the A/D conversion trigger controller. As shown in this figure, it is possible to select and perform OR output of compare match interrupts (INTTRnCC5, INTTRnCC4) and peak interrupts (INTTRnCD), valley interrupts (INTTRnOD) interrupt signals, sub-counter peak timing, and sub-counter valley timing. In the case of timer R, there are two identical A/D conversion trigger controllers, and each one can be controlled independently. 376 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.8.1 A/D conversion trigger operation Timer R has a function for generating A/D conversion start triggers (TRnADTRG0, TRnADTRG1 signals), freely selecting 4 trigger sources. The following 4 triggers sources are provided, which can be specified with TRnOPT2 register bits TRnAT05 to TRnAT00 and TRnOPT3 register bits TRnAT15 to TRnAT10. Here, control of the TRnADTRG0 using TRnAT05 to TRnAT00 is described. The same type of control can be achieved for the TRnADTRG1 signal with control bits TRnAT15 to TRnAT10 (1) TRnADTRG0 signal output control * TRnOPT2 register TRnAT00 = 1: Output of A/D conversion trigger upon valley interrupt (INTTRnOD) output * TRnOPT2 register TRnAT01 = 1: Output of A/D conversion trigger upon peak interrupt (INTTRnCD) output * TRnOPT2 register TRnAT02 = 1: A/D conversion trigger outputtable upon compare match interrupt (INTTRnCC4) during counter up count * TRnOPT2 register TRnAT03 = 1: A/D conversion trigger outputtable upon compare match interrupt (INTTRnCC4) during counter down count * TRnOPT2 register TRnAT04 = 1: A/D conversion trigger outputtable upon compare match interrupt (INTTRnCC5) during counter up count * TRnOPT2 register TRnAT05 = 1: A/D conversion trigger outputtable upon compare match interrupt (INTTRnCC5) during counter down count The A/D conversion start trigger signals selected with bits TRnAT05 to TRnAT00 are all ORed and output to the TRnADTRG0 pin. The peak and valley interrupts (INTTRnOD, INTTRnCD) selected with bits TRnAT00 and TRnAT01 are the signals after interrupt thinning out. Therefore, they are output at the timing when interrupt thinning out control is received, and when interrupt output enable (bits TRnICE and TRnIOE) is not enabled, neither is any A/D conversion start trigger output. Moreover, TRnOPT2 register bits TRnAT05 to TRnAT00 can be rewritten during operation. When the A/D conversion start trigger setting bit is rewritten during operation, this is instantly reflected to the output status of the A/D conversion start trigger. These control bits do not have a reload function and are write accessed only in the anytime write mode. User's Manual U16580EE3V1UD00 377 Chapter 10 Figure 10-36: 16-bit Inverter Timer/Counter R A/D Conversion Trigger Timings (1/2) (a) when TRnICE = 1, TRnIOE = 1, TRnID4-TRnID0 = 00H (No Interrupt Thinning Out) Counter INTTRnCD INTTRnOD INTTRnCC4 INTTRnCC5 TRnCUF [When TRnAT05 to 00 = 000001] Output INTTRnOD TRnADTRG0 [When TRnAT05 to 00 = 000010] Output INTTRnCD TRnADTRG0 [When TRnAT05 to 00 = 000100] Output INTTRnCC4 during up count TRnADTRG0 [When TRnAT05 to 00 = 001000] Output INTTRnCC4 during down count TRnADTRG0 [When TRnAT05 to 00 = 010000] Output INTTRnCC5 during up count TRnADTRG0 [When TRnAT05 to 00 = 100000] Output INTTRnCC5 during down count TRnADTRG0 [When TRnAT05 to 00 = 000011] ... Setting at which A/D conversion start trigger is output for both peaks and valleys TRnADTRG0 [When TRnAT05 to 00 = 100100] Perform ORed output o INTTRnCC4 and INTTRnCC5 ... Setting at which A/D conversion start trigger is output for both up/down count upon match interrupt TRnADTRG0 378 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-36: A/D Conversion Trigger Timings (2/2) (b) when TRnICE = 0, TRnIOE = 1, TRnID4 to TRnID0 = 02H (Interrupt Thinning Out) Counter INTTRnCD INTTRnOD [When TRnAT05-00 = 000011] Both INTTRnCD and INTTRnOD are selected, but peak not output due to interrupt thinning out specification. TRnADTRG0 (c) 0when TRnICE = 0, TRnIOE = 1, TRnID4 to TRnID0 = 02H (Interrupt Thinning Out) Counter INTTRnCD INTTRnOD INTTRnCC4 INTTRnCC5 TRnCUF [When TRnAT05-00 = 000101] ... INTTRnCD is thinned out, but INTTRnCC4 is not. TRnADTRG0 (2) Cautions related to A/D conversion triggers * In the PWM mode and PWM mode with dead time, no valley interrupt (INTTRnOD) is output. Only peak interrupts (INTTRnCD) are valid. User's Manual U16580EE3V1UD00 379 Chapter 10 16-bit Inverter Timer/Counter R 10.9 Error Interrupts 10.9.1 Error interrupt and error signal output functions Timer R has an error interrupt (INTTRnER) and an error signal output (TRnER). As the errors detected with timer R, normal phase/inverted phase simultaneous active (fault of dead time controller) are detected as errors in the high-accuracy T-PWM mode, PWM mode with dead time, and PWM mode. Regarding normal phase/inverted phase simultaneous active errors, following error occurrence, the error occurrence can be confirmed by reading bit TRnTBF of the TRnOPT6 register. Moreover, detection ON/OFF switching control in each phase (TORn1/TORn2, TORn3/TORn4, TORn5/ TORn6) is possible using bits TRnTBA2 to TRnTBA0 of the TRnIOC4 register. The possibility of normal phase/inverted phase simultaneous active error detection in each mode is indicated below. Mode Remark: : x: Interval mode x External event count mode x External trigger pulse output mode x One-shot pulse mode x PWM mode Free-running mode x Pulse width measurement mode x Triangular wave PWM mode High-accuracy T-PWM mode PWM mode with dead time Error detection possible Error detection not possible Figure 10-37: TORn1 Normal Phase/Inverted Phase Simultaneous Active Detection Error Interrupt (INTTRnER) and Error Signal (TRnER) Output Controller TRnTBA [2 1 0] TRnOL1 TORn2 TRnOL2 TORn3 TRnER TRnOL3 INTTRnER TORn4 TRnOL4 TORn5 TRnOL5 TORn6 TRnOL6 TRnEOC Error detection possible mode TRnCE Output of the error signal (TRnER) due to normal phase/inverted phase simultaneous active error is active level during detection of normal phase/inverted phase simultaneous active. 380 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (1) In PWM mode The case of normal phase/inverted phase simultaneous active in the PWM mode is described below. As shown in the figure below, an error interrupt (INTTRnER) is output when the TRnCCR1 and TRnCCR2 registers are set so that pins TORn1 and TORn2 simultaneously output "H". Similarly, an error interrupt (INTTRnER) is output when the TRnCCR3 and TRnCCR4 registers are set so that pins TORn3 and TORn4 simultaneously output "H". Figure 10-38: Error Interrupt and Error Signal Output Controller in PWM mode TRnCCR1 TRnCCR4 TRnCCR2 TRnCCR3 TRnCCR0 TRnCCR2 TRnCCR3 TRnCCR1 TRnCCR4 TRnCCR2 TRnCCR3 TRnCCR2 TRnCCR3 TRnCCR2 TRnCCR3 TRnCCR1 TRnCCR4 TRnCCR1 TRnCCR4 TORn1 TORn2 TORn3 TORn4 INTTRnER If the output active level is switched by manipulating TRnIOC0 register bits TRnOL1 and TRnOL2, the following results. When TRnOL1 = 0, When TRnOL1 = 1, When TRnOL1 = 0, When TRnOL1 = 1, TRnOL2 = 0 TRnOL2 = 0 TRnOL2 = 1 TRnOL2 = 1 TRnCNT TORn1 TRnCNT TRnCNT TRnCNT TORn1 TORn1 TORn1 TORn2 TORn2 TORn2 TORn2 INTTRnER INTTRnER INTTRnER INTTRnER User's Manual U16580EE3V1UD00 381 Chapter 10 (2) 16-bit Inverter Timer/Counter R In triangular wave PWM mode The case of normal phase/inverted phase simultaneous active in the triangular wave PWM mode is described below. As shown in the figure below, an error output (INTTRnER) is output when the TRnCCR0 and TRnCCR1 registers are set so that pins TORn1 and TORn2 simultaneously output "H". Similarly, an error interrupt (INTTRnER) is output when the TRnCCR3 and TRnCCR4 registers are set so that pins TORn3 and TORn4 simultaneously output "H". Figure 10-39: Error Interrupt and Error Signal Output Controller in triangular wave PWM mode TRnCCR1 TRnCCR4 TRnCCR2 TRnCCR3 TRnCCR1 TRnCCR4 TRnCCR2 TRnCCR3 TORn1 TORn2 TORn3 TORn4 INTTRnER 382 User's Manual U16580EE3V1UD00 TRnCCR1 TRnCCR4 Chapter 10 16-bit Inverter Timer/Counter R (3) In high-accuracy T-PWM mode/PWM mode with dead time In the high-accuracy T-PWM mode and PWM mode with dead time, no error occurs except when the dead time setting is "0". If an error occurs, this is likely due to an internal circuit fault. Figure 10-40: Error Interrupt and Error Signal Output Controller in High-Accuracy T-PWM Mode / PWM Mode with Dead Time Counter TORn1 TORn2 INTTRnER "L" TRnTBF A glitch may occur during normal phase/inverted phase switching. The detection flag (TRnTBF) is not set. Counter TORn1 TORn2 INTTRnER TRnTBF "L" A glitch may occur during normal phase/inverted phase switching. The detection flag (TRnTBF) is not set. User's Manual U16580EE3V1UD00 383 Chapter 10 16-bit Inverter Timer/Counter R 10.10 Operation in Each Mode 10.10.1 Interval timer mode (1) Outline of interval timer mode In the interval timer mode, a compare match interrupt (INTTRnCC0) occurs and the counter is cleared upon a match between the setting value of the TRnCCR0 register and the counter value. The occurrence interval for this counter and TRnCCR0 register match interrupt becomes the interval time. In the interval timer mode, the counter is cleared only upon a match between the counter and the value of the TRnCCR0 register. Counter clearing using the TRnCCR1 to TRnCCR5 registers is not performed. However, the setting values of the TRnCCR1 to TRnCCR5 registers are compared to the counter values transferred to the TRnCCR1 to TRnCCR5 buffer registers and compare match interrupts (INTTRnCC1 to INTTRnCCR5) are output. The TRnCCR0 to TRnCCR5 registers can be rewritten using the anytime write method, regardless of the value of bit TRnCE. Pins TORn0 to TORn7 are toggle output controlled when bits TRnOE0 to TRnOE7 are set to 1. Figure 10-41: Basic Operation Flow in Interval Timer Mode START Initial settings *Clock selection (TRnCTL0: TRnCKS2 to TRnCKS0) *Interval mode setting (TRnCTL1: TRnMD3 to TRnMD0 = 0000) *Compare register setting (TRnCCR0 to TRnCCR5) Timer operation enable (TRnCE = 1) Transfer of TRnCCR0 to TRnCCR5 values to TRnCCR0 to TRnCCR5 buffers Match between counter and TRnCCR1 to Note TRnCCR5 buffer values INTTRnCC1 to INTTRnCC5 occurrence Match between counter and INTTRnCC0 occurrence TRnCCR0 buffer value, counter clear & start Note: In the case of a match between the counter and TRnCCR1 to TRnCCR5 registers, the counter is not cleared. 384 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Chapter 10 (2) 16-bit Inverter Timer/Counter R Interval timer mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Compare value TRnCCR1 to TRnCCR3 Reload Possible Compare value TRnCCR4, TRnCCR5 Reload Possible Compare value (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output pins Pin Function TORnm Toggle output upon TRnCCRm register compare match (m = 0 to 5) TORn6, TORn7 - (d) Interrupts Interrupt Function INTTRnCCm TRnCCRm register compare match (m = 0 to 5) INTTRnOV - INTTRnER - User's Manual U16580EE3V1UD00 385 Chapter 10 Figure 10-42: 16-bit Inverter Timer/Counter R Basic Timing in Interval Timer Mode (1/2) (a) When D1>D2>D3, only value of TRnCCR0 register is rewritten, TORn0 and TORn1 are not output (TRnOE0, 1 = 0, TRnOL0 = 0, TRnOL1 = 1) FFFFH D1 D1 D2 D3 Counter D3 D3 TRnCE TRnCCR0 D1 TRnCCR1 D 2 D3 INTTRnCC0 INTTRnCC1 A A A: Interval time (D1 + 1) B count clock TORn0 Low TORn1 High A: Interval time (D2 + 1) Remarks: 1. D1, D2: Setting values of TRnCCR0 register (0000H to FFFFH) D3: Setting values of TRnCCR1 register (0000H to FFFFH) 2. Interval time = (Dm + 1) x (count clock cycle) 3. m = 1 to 3, n = 0, 1 386 User's Manual U16580EE3V1UD00 count clock Chapter 10 16-bit Inverter Timer/Counter R Figure 10-42: Basic Timing in Interval Timer Mode (2/2) (b) When D1 = D2, values of TRnCCR0 and TRnCCR1 registers not rewritten, TORn1 output performed (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH D1 = D2 D1 = D2 D1 = D2 Counter TRnCE TRnCCR0 D1 TRnCCR1 D2 INTTRnCC0 INTTRnCC1 TORn0 TORn1 Interval time Interval time Interval time Remarks: 1. D1: Setting value of TRnCCR0 register (0000H to FFFFH) D2: Setting value of TRnCCR1 register (0000H to FFFFH) 2. Interval time = (Dm + 1) x (count clock cycle) 3. TORn0, TORn1 toggle time = (Dm + 1) x (count clock cycle) 4. m = 1, 2, n = 0, 1 User's Manual U16580EE3V1UD00 387 Chapter 10 16-bit Inverter Timer/Counter R 10.10.2 External event count mode (1) Outline of external event count mode In the external event count mode, count up starts upon external event input (TEVTRn pin). (The external event input (TEVTRn) is used as the count clock, regardless of bit TRnEEE of the TRnCTL1 register.) In the external event count mode, the counter is cleared only upon a match between the counter and the value of the TRnCCR0 register. Counter clearing using the TRnCCR1 to TRnCCR5 registers is not performed. However, the values of the TRnCCR1 to TRnCCR5 registers are transferred to the TRnCCR1 to TRnCCR5 buffer registers, compared to the counter value, and compare match interrupts (INTTRnCC1to INTRnCCR5) are output. The TRnCCR0 to TRnCCR5 registers can be rewritten with the anytime write method, regardless of the value of bit TRnCE. Pins TORn1 to TORn7 are toggle output controlled when bits TRnOE1 to TRnOE7 are set to 1. When a compare register TRnCCR0 to TRnCCR5 is not used, it is recommended to set it contents to FFFFH. [External event count operation flow] <1> TRnCTL1 register bits TRnMD3 to TRnMD0 = 0001B (mode setting) Edge detection set with TRnIOC2 register bits TRnEES1 and TRnEES0 (TRnEES1, TRnEES0 = setting other than 00B) <2> TRnCTL0 register bit TRnCE = 1 (count enable) <3> TEVTRn pin input edge detection (count-up start) Cautions: 1. In case of the external event count mode, when the content of the TRnCCR0 register is set to m, the number of TEVTRn pin input edge detection times is m+1. 2. Do not set the value of the TRnCCR0 register to 0000H in external event count mode. 3. When a TRnCCR1 to TRnCCR5 register value is set to 0000H in external event count mode the corresponding interrupt (INTTRnCC1 to INTTRnCC5) does not occur immediately after start, but after the first overflow of the timer (FFFFH to 0000H). 4. TORn0 pin output cannot be used in external event count mode. Alternatively use the interval timer mode (refer to section 10.10.1 "Interval timer mode" on page 384) and set TPnEEE = 1 in conjunction with TOPn0 pin output. Remark: 388 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) External event count mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Anytime rewrite Possible Compare value TRnCCR1 to TRnCCR3 Anytime rewrite Possible Compare value TRnCCR4, TRnCCR5 Anytime rewrite Possible Compare value (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output pins Pin Function TORnm Toggle output upon TRnCCRm register compare match (m = 0 to 5) TORn6, TORn7 - (d) Interrupts Interrupt Function INTTRnCCm TRnCCRm register compare match (m = 0 to 5) INTTRnOV - INTTRnER - User's Manual U16580EE3V1UD00 389 Chapter 10 Figure 10-43: 16-bit Inverter Timer/Counter R Basic Operation Timing in External Event Count Mode (1/4) (a) When D1>D2>D3, only value of TRnCCR0 register is rewritten, TORn0 and TORn1 are not output. The signal input from TEVTRn and internally synchronized is counted as the count clock (TRnOE0, 1 = 0, TRnOL0 = 0, TRnOL1 = 1) FFFFH D1 D1 D2 Counter D3 D3 D3 TRnCE D1 TRnCCR0 TRnCCR1 D 2 D3 INTTRnCC0 INTTRnCC1 TORn0 Low TORn1 High TEVTRn Remarks: 1. D1, D2: Setting values of TRnCCR0 register (0000H to FFFFH) D3: Setting value of TRnCCR1 register (0000H to FFFFH) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 390 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-43: Basic Operation Timing in External Event Count Mode (2/4) (b) When D1 = D2, TRnCCR0 and TRnCCR1 register values are not rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH D1 = D2 D1 = D2 D1 = D2 Counter TRnCE TRnCCR0 D1 TRnCCR1 D2 INTTRnCC0 INTTRnCC1 TORn0 TORn1 TEVTRn Remarks: 1. D1: Setting value of TRnCCR0 register (0000H to FFFFH) D2: Setting value of TRnCCR1 register (0000H to FFFFH) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 User's Manual U16580EE3V1UD00 391 Chapter 10 Figure 10-43: 16-bit Inverter Timer/Counter R Basic Operation Timing in External Event Count Mode (3/4) (c) When D1 = D2, TRnCCR0 and TRnCCR1 register values are not rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH Counter 0000H TRnCE TRnCCR0 0000H TRnCCR1 0000H INTTRnCC0 INTTRnCC1 TORn0 TORn1 Remarks: 1. D1: Setting value of TRnCCR0 register (0000H) D2: Setting value of TRnCCR1 register (0000H) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 392 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-43: Basic Operation Timing in External Event Count Mode (4/4) (d) When D1 = D2, TRnCCR0, TRnCCR1 register values are not rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH Counter 0001H TRnCE TRnCCR0 0001H TRnCCR1 0000H INTTRnCC0 INTTRnCC1 TORn0 TORn1 Remarks: 1. D1: Setting value of TRnCCR0 register (0001H) D2: Setting value of TRnCCR1 register (0000H) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 User's Manual U16580EE3V1UD00 393 Chapter 10 16-bit Inverter Timer/Counter R 10.10.3 External trigger pulse output mode (TMR1 only) (1) Outline of external trigger pulse output mode When, in the external trigger pulse mode, the duty is set to the TR1CCR1 to TR1CCR5 registers, the cycle is set to the TR1CCR0 register, and TR1CE = 1 is set, external trigger input (TTRGR1 pin) wait results, with the counter remaining stopped at FFFFH. Upon detection of the valid edge of external trigger input (TTRGR1 pin), or when the TR1EST bit of the TR1CTL1 register is set, count up starts. An external trigger pulse is output from pins TOR11 to TOR15, and toggle output is performed from pin TOR10 upon a match with the TR1CCR0 register. Moreover, during the count operation, upon a match between the counter and the TR1CCR0 register, a compare match interrupt (INTTR1CC0) is output, and upon a match between the counter and TR1CCR1 to TR1CCR5 registers, compare match interrupts (INTTR1CC1 to INTTR1CC5) are output. The TR1CCR0 to TR1CCR5 registers can be rewritten during count operation. Compare register reload is performed at the timing when the counter value and the TR1CCR0 register match. However, when write access to the TR1CCR1 register is performed, the next reload timing becomes valid, so that even if wishing to rewrite only the value of the TR1CCR0 register, write the same value to the TR1CCR1 register. In this case, reload is not performed even if only the TR1CCR0 register is rewritten. If, during operation in the external trigger pulse output mode, the external trigger (TTRGR1 pin) edge is detected several times, or if the TR1EST bit of the TR1CTL1 register is set (to 1), the counter is cleared and count up is resumed. Moreover, if at this time, the TOR11 to TOR15 pins are in the low level status, the TOR11 to TOR15 pin outputs become high level when an external trigger is input. If the TOR11 pin is in the high level status, it remains high level even if external trigger input occurs. In the external trigger pulse output mode, the TR1CCR0 to TR1CCR3 registers have their function fixed as compare registers, so the capture function cannot be used. Caution: 394 In the external trigger pulse mode, the external event clock input (TEVTR1) is prohibited (TR1CTL1.TR1EEE = 0). User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) External trigger pulse output mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TR1CCR0 Reload Possible Cycle TR1CCR1 to TR1CCR3 Reload Possible Duty TR1CCR4, TR1CCR5 Reload Possible Duty (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 Counter clear & start through external trigger input TEVTR1 Timer count through external event count input (c) Output pins Pin Function TOR10 Toggle output upon TR1CCR0 register compare match or external trigger input TOR1m External trigger pulse waveform output (m = 1 to 5) TOR16, TOR17 - (d) Interrupts Interrupt Function INTTR1CCm TR1CCRm register compare match (m = 0 to 5) INTTR1OV - INTTR1ER - User's Manual U16580EE3V1UD00 395 Chapter 10 Figure 10-44: 16-bit Inverter Timer/Counter R Basic Operation Flow in External Trigger Pulse Output Mode START Initial settings *Clock selection (TR1CTL1. TR1EEE = 0) (TR1CTL0. TR1CKS2 to TR1CKS0) *External trigger pulse output mode setting (TR1CTL1. TR1MD3 to TR1MD0 = 0010) *Compare register setting (TR1CCR0 to TR1CCR5) External trigger (TTRGR1 pin) input Counter clear & start Timer operation enable (TR1CE = 1) Transfer of valu es of TR1CCR0 to TR1CCR5 to buffers TR1CCR0 to TR1CCR5 External trigger (TTRGR1 pin) input Counter starts counting. Match between counter and Note TR1CCR1 to TR1CCR5 Match between counter and TR1CCR0, counter clear & start INTTR1CC1 to INTTR1CC5 occurrence INTTR1CC0 occurrence Note: The counter is not cleared upon a match between the counter and the TR1CCR1 to TR1CCR5 buffer register. 396 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-45: Basic Operation Timing in External Trigger Pulse Output Mode (a) When values of TR1CCR0 and TR1CCR1 registers are rewritten, TOR10 and TOR11 are output (TR1OE0, 1 = 1, TR1OL0, 1 = 0) FFFFH D01 D02 D12 Counter D11 TR1CE External trigger (TTRGR1 pin) TR1CCR0 D01 TR1CCR0 buffer 0000H D02 D01 D11 TR1CCR1 0000H TR1CCR1 D02 D12 D11 D12 buffer TOR11 toggle output TOR10 toggle output TR1RSF flag Remarks: 1. D01, D02: Setting values of TR1CCR0 register (0000H to FFFFH) D11, D12: Setting values of TR1CCR1 register (0000H to FFFFH) 2. TOR11 (PWM) duty = (setting value of TR1CCR1 register) x (count clock cycle) TOR11 (PWM) cycle = (setting value of TR1CCR0 register + 1) x (count clock cycle) 3. Pin TOR10 is toggled when the counter is cleared immediately following count start. User's Manual U16580EE3V1UD00 397 Chapter 10 16-bit Inverter Timer/Counter R 10.10.4 One-shot pulse mode (1) Outline of one-shot pulse mode When, in the one-shot pulse mode, the duty is set to the TRnCCR0 register, the output duty delay value is set to the TRnCCR1 to TRnCCR5 registers, and bit TRnCE of the TRnCTL0 register is set to 1, external trigger input (TTRGR1 pin of TMR1) wait results, with the counter remaining stopped at FFFFH. Upon detection of the valid edge of external trigger input (TTRGR1 pin of TMR1), or when bit TRnEST of the TRnCTL0 register is set to 1, count up starts. The TORn1 to TORn5 pins become high level upon a match between the counter and TRnCCR1 to TRnCCR5 registers. Moreover, upon a match between the counter and TRnCCR0 register, the TORn1 to TORn5 pins become low level, and the counter is cleared to 0000H and then stops. The TORn0 pin performs toggle output during the count operation upon a match between the counter and the TRnCCR0 buffer register. Moreover, upon a match between the counter and TRnCCR0 register during count operation, a compare match interrupt (INTTRnCC0) is output, and upon a match between the counter and TRnCCR1 to TRnCCR5 buffer registers, compare match interrupts (INTTRnCC1 to INTTRnCCR5) are output. The TRnCCR0 and TRnCCR1 registers can be rewritten using the anytime write method, regardless of the value of bit TRnCE. Even a trigger is input during the counter operation, it is ignored. Be sure to input the second trigger when the counter is stopped at 0000H. In the one-shot pulse mode, registers TRnCCR0 to TRnCCR3 have their function fixed as compare registers, so the capture function cannot be used. [One-shot pulse operation flow] <1> TRnCTL1 register bits TRnMD3 to TRnMD0 = 0011B (One-shot pulse mode) <2> TRnCCR0 register setting (duty setting), TRnIOC0 register bit TRnOE1 = 1 (TORn1 pin output enable) <3> TRnCTL0 register bit TRnCE = 1 (counter operation enable):TORn1 = Low-level output <4> TRnCTL1 register bit TRnEST = 1 or TTRGR1 pin edge detection of TMR1 (count-up start): TORn1 = Low-level output <5> Match between counter value and TRnCCR1 buffer register: TORn1 = High-level output <6> Match between counter value and TRnCCR0 buffer register:TORn1 = Low-level output, count clear <7> Count stop: TORn1 = Low-level output <8> TRnCE = 0 (operation reset) <9> <1> to <2> can be in any order. Caution: 398 In the one-shot pulse mode, set bit TRnEEE of the TRnCTL1 register to 0. User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) One-shot pulse mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Anytime rewrite Possible Cycle TRnCCR1 to TRnCCR3 Anytime rewrite Possible Output delay value TRnCCR4, TRnCCR5 Anytime rewrite Possible Output delay value (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 Counter start through external trigger input TEVTR1 - (c) Output pins Pin Function TORn0 Active at count start, inactive upon TRnCCR0 register match TORnm Active upon TRnCCRm register match, inactive upon TRnCCR0 register match (m = 1 to 5) TORn6, TORn7 - (d) Interrupts Interrupt Function INTTRnCCm TRnCCRm register compare match INTTRnOV - INTTRnER - User's Manual U16580EE3V1UD00 399 Chapter 10 Figure 10-46: 16-bit Inverter Timer/Counter R Basic Operation Flow in One-Shot Pulse Mode START Initial settings * Clock selection (TRnCTL1: TRnEEE = 0) (TRnCTL0: TRnCKS2 to TRnCKS0) * One-shot pulse mode setting (TRnCTL1: TRnMD2 to TRnMD0 = 011) * Compare register setting (TRnCCR0 to TRnCCR5) Timer operation enable (TRnCE = 1) Transfer of values of TRnCCR0 to TRnCCR5 to buffers TRnCCR0 to TRnCCR5 Trigger wait status, counter in standby at FFFFH External trigger input (TTRGR1 pin of TMR1), or TRnEST = 1 Counter starts counting. Trigger wait status, co unter in standby at 0000H Match between counter and buffers TRnCCR1 to TRnCCR5 Note Match between counter and buffer TRnCCR0, counter clear INTTRnCC1 to INTTRnCC5 occurrence INTTRnCC0 occurrence Note: The counter is not cleared upon a match between the counter and the TRnCCR1 to TRnCCR5 buffer registers. Caution: The counter is not cleared even if trigger input is realized while the counter counts up, and the trigger input is ignored. Remark: n = 0, 1 400 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-47: Basic Operation Timing in One-Shot Pulse Mode (a) (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH D0 Note1 Counter D1 D0 D0 D1 D1 TRnCE TRnEST External trigger (TTRGR1 pin Note2) TRnCCR0 D0 TRnCCR0 buffer 0000H TRnCCR1 D0 D1 TRnCCR1 buffer 0000H D1 INTTRnCC0 INTTRnCC1 TORn1 one-shot pulse output TORn0 Notes: 1. Count up starts when the value of TRnEST becomes 1 or TTRGRn is input. 2. Trigger input available for TMR1 only (n = 1). Remarks: 1. D0: Setting value of TRnCCR0 register (0000H to FFFFH) D1: Setting value of TRnCCR1 register (0000H to FFFFH) 2. TORn1 (output delay) = (setting value of TRnCCR1 register) x (count clock cycle) TORn1 (output pulse width) = {(setting value of TRnCCR0 register +1) - (setting value of TRnCCR1 register)} x (count clock cycle) 3. n = 0, 1 User's Manual U16580EE3V1UD00 401 Chapter 10 16-bit Inverter Timer/Counter R 10.10.5 PWM mode (1) Outline of PWM mode When, in the PWM mode, the duty is set to the TRnCCR1 to TRnCCR5 registers, the cycle is set to the TRnCCR0 register, and TRnCE = 1 is set, variable duty PWM output is performed from pins TORn1 to TORn5. Simultaneously with the start of count up operation, pins TORn1 to TORn5 becomes high level, and upon a match between the counter and the TRnCCR1 to TRnCCR5 registers, becomes low level. Next, the TORn1 to TORn5 pins become high level upon a match with the TRnCCR0 register. The TORn0 pin performs toggle output upon a match with the TRnCCR0 buffer register. During count operation, a compare match interrupt (INTTRnCC0) is output upon a match between the counter and TRnCCR0 register, and compare match interrupts (INTTRnCC1 to INTTRnCC5) are output upon a match between the counter and TRnCCR1 to TRnCCR5 registers. The TRnCCR0 to TRnCCR5 registers can be rewritten during count operation. Compare register reload occurs upon a match between the counter value and the TRnCCR0 buffer register. However, since the next reload timing becomes valid when the TRnCCR1 register is written to, write the same value to the TRnCCR1 register even when wishing to rewrite only the value of the TRnCCR0 register. Reloading is not performed if only the TRnCCR0 register is rewritten. In the PWM mode, the TRnCCR0 to TRnCCR3 registers have their function fixed as compare registers, so the capture function cannot be used. 402 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) PWM mode operation list (a) Compare register Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Cycle TRnCCR1 to TRnCCR3 Reload Possible Duty TRnCCR4, TRnCCR5 Reload Possible Duty (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output pins Pin Function TORn0 Toggle output upon TRnCCR0 register compare match TORnm PWM output upon TRnCCRm register compare match (m = 1 to 5) TORn6 - TORn7 Pulse output through A/D conversion trigger (d) Interrupts Interrupt Function INTTRnCCm TRnCCRm register compare match INTTRnOV - INTTRnER Error User's Manual U16580EE3V1UD00 403 Chapter 10 Figure 10-48: 16-bit Inverter Timer/Counter R Basic Operation Mode in PWM Mode (1/2) (a) When values of TRnCCR0 to TRnCCR5 registers are rewritten during timer operation START Initial settings * Clock selection (TRnCTL0: TRnCKS2 to TRnCKS0) * PWM mode setting (TRnCTL1: TRnMD3 to TRnMD0 = 0100) * Compare register setting (TRnCCR0 to TRnCCR5) Timer operation enable Transfer of value of TRnCCRm to TRnCCRm buffer TORn1 to TORn5 output low level upon a match between counter and TRnCCR1 to TRnCCR5 bffers. Upon a match between counter and TRnCCR0 buffer, counter clear & start, and TORn1 to TORn5 output high level. Remark: 404 INTTRnCC1 to INTTRnCC5 occurrence INTTRnCC0 occurrence n = 0, 1 m = 0 to 5 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-48: Basic Operation Flow in PWM Mode (2/2) (b) When values of TRnCCR0 to TRnCCR5 registers are rewritten during timer operation START Initial settings * Clock selection (TRnCTl0: TRnCKS2 to TRnCKS0) * PWM mode setting (TRnCTl1: TRnMD3 to TRnMD0 = 0100) * Compare register setting (TRnCCR0 to TRnCCR5) Timer operation enable (TRnCE = 1) Transfer of value of TRnCCRm to TRnCCRm buffer INTTRnCC1 to INTTRnCC5 occurrence Upon a match between counter and TRnCCR1 to TRnCCR5, TORn1 to TORn5 output low level Upon a match between counter and TRnCCR0, counter clear & start, and TORn1 to TORn5 output high level. TRnCCR0 rewrite INTTRnCC0 occurrence <1> Upon a match between counter and TRnCCR1 to TRnCCR5 buffers, <2> TORn1 to TORn5 output low level. TRnCCR1 rewrite * * * Note <3> Match between TRnCCR0 buffer and counter Counter clear & start Value of TRnCCRm is reloaded to CCRm buffer. INTTRnCC1 to INTTRnCC5 occurrence Reload enable INTTRnCC0 occurrence Note: Regarding the sequence, the timing of <2> may differ depending on the <1> or <3> rewrite timing, the value of the TRnCCR1 register, etc., but of <1> and <3>, always make <3> the last. Remark: n = 0, 1 m = 0 to 5 User's Manual U16580EE3V1UD00 405 Chapter 10 Figure 10-49: 16-bit Inverter Timer/Counter R Basic Operation Timing in PWM Mode (1/2) (a) When only value of TRnCCR1 is rewritten, and TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH D00 D00 D00 D00 D11 D10 Counter D10 D12 TRnCE TRnCCR0 TRnCCR0 buffer D00 0000H TRnCCR1 TRnCCR1 buffer D00 D10 0000H D11 D10 D12 D11 D13 D12 D13 TORn1 TORn0 TRnRSF flag Remarks: 1. D00: Setting value of TRnCCR0 register (0000H to FFFFH) D10, D11, D12, D13: Setting values of TRnCCR1 register (0000H to FFFFH) 2. TORn1 (PWM) duty = (setting value of TRnCCR1 register) x (count clock cycle) TORn1 (PWM) cycle = (setting value of TRnCCR0 register + 1) x (count clock cycle) TORn0 is toggled immediately following counter start and at (setting value of TRnCCR0 register + 1) x (count clock cycle) 3. n = 0, 1 406 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-49: Basic Operation Timing in PWM Mode (2/2) (b) When values of TRnCCR0 and TRnCCR1 register are rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH D00 D01 D01 D11 D11 Counter D02 D12 D10 TRnCE TRnCCR0 D00 D01 D02 D03 Note TRnCCR0 buffer 0000H D00 D01 D02 D03 Write same value TRnCCR1 D10 D11 D12 D12 Note TRnCCR1 buffer 0000H D10 D11 D12 D12 TORn1 TORn0 TRnRSF flag Note: The TRnCCR1 register was not written to, so transfer to the TRnCCR0 buffer register was not performed. Held until the next reload timing. Remarks: 1. D00, D01, D02, D03: Setting values of TRnCCR0 register (0000H to FFFFH) D10, D11, D12, D13: Setting values of TRnCCR1 register (0000H to FFFFH) 2. The TORn0 and TORn1 pins become high level at timer count start. 3. n = 0, 1 User's Manual U16580EE3V1UD00 407 Chapter 10 16-bit Inverter Timer/Counter R 10.10.6 Free-running mode (1) Outline of free-running mode The operation timing of the free-running mode is shown below. The operation for bits TRnCCS0 to TRnCCS3 of register TRnOPT0 is specified. Figure 10-50: Basic Operation Flow in Free-Running Mode START Initial settings * Clock selection (TRnCTL0: TRnCKS2 to TRnCKS0) * Free-running mode setting (TRnCTL1: TRnMD3 to TRnMD0 = 0101) TRnCCS1, TRnCCS0 settings TRnCCS1 = 0 TRnCCS0 = 0 TRnCCS1 = 0 TRnCCS0 = 0 Timer operation enable (TRnCE = 1) TIRn0 edge detection settings (TRnIS1, TRnIS0) TRnCCS1 = 1 TRnCCS0 = 1 TIRn1 edge detection settings (TRnIS3, TRnIS2) Transfer of values of TRnCCR0 and TRnCCR1 to TRnCCR0 and TRnCCR1 buffers Timer operation enable (TRnCE = 1) Transfer of value of TRnCCR1 to TRnCCR1 buffer Match between TRnCCR1 buffer and counter Match between TRnCCR0 buffer and counter Timer operation enable (TRnCE = 1) Transfer of value of TRnCCR0 to TRnCCR0 buffer Match between TRnCCR1 buffer and counter TIRn1 edge detection, capture of counter value to TRnCCR1 TIRn0 edge detection, capture of counter value to TRnCCR0 Match between TRnCCR1 buffer and counter TRnCCS1 = 1 TRnCCS0 = 1 TIRn1 and TIRn0 edge detection settings (TRnIS3, TRnIS2) Timer operation enable (TRnCE = 1) TIRn1 edge detection, capture of counter value to TRnCCR1 TIRn0 edge detection, capture of counter value to TRnCCR0 Counter overflow Counter overflow Counter overflow Counter overflow Remarks: 1. This is an example when using the TRnCCR0 and TRnCCR1 registers. When using the TRnCCR2 and TRnCCR3 registers, the operation is controlled in the same manner via bits TRnCCS3 and TRnCCS2. 2. n = 0, 1 408 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (2) Free-running mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Anytime rewriteNote 1 PossibleNote 1 Capture or compare value TRnCCR1 to TRnCCR3 Anytime rewriteNote 1 PossibleNote 1 Capture or compare value Anytime rewrite Possible Compare value TRnCCR4, TRnCCR5 (b) Input pins Pin Function TIR1m Input capture trigger, transfer counter value to TR1CCRm register (m = 0 to 3)Note 2 TTRGR1 - TEVTR1 - (c) Output pins Pin Function TORnm TORn6, TORn7 Toggle output upon TRnCCRm register compare match (m = 0 to 5)Note 1 - (d) Interrupts Interrupt Function INTTRnCCm TRnCCRm register compare match (m = 0 to 5)Note 1, or occurrence of TIR1m capture input signal (m = 0 to 3)Note 2 INTTRnOV Overflow INTTRnER - Notes: 1. When compare function is selected for the corresponding TR1CCRm register of TMR1. For TMR0 the compare function is permitted only for TR0CCRm registers (m = 0 to 3). 2. When capture function is selected for the corresponding TR1CCRm register of TMR1 (m =0 to 3) User's Manual U16580EE3V1UD00 409 Chapter 10 (3) 16-bit Inverter Timer/Counter R Compare function (TRnCCS1 = 0, TRnCCS0 = 0) When TRnCTL0 register bit TRnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTRnOV) is output when the counter value changes from FFFFH to 0000H, and the counter is cleared. The count operation is performed in the free-running mode until TRnCE = 0 is set. Moreover, during count operation, a compare match interrupt (INTTRnCC0) is output upon a match between the counter and TRnCCR0 buffer register, and a compare match interrupt (INTTRnCC1) is output upon a match between the counter and TRnCCR1 buffer register. The TRnCCR0 and TRnCCR1 registers can be rewritten using the anytime write method, regardless of the value of the TRnCE bit. The TORn0 and TORn1 pins are toggle output controlled when bits register TRnOE0 and TRnOE1 of the TRnIOC0 register are set to 1. 410 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-51: Basic Operation Timing in Free-Running Mode (Compare Function) When values of TRnCCR0 and TRnCCR1 registers are rewritten, TORn0, TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH D01 D11 D11 D00 Counter D00 D10 TRnCE TRnCCR0 D00 TRnCCR0 0000H buffer D01 D00 D01 INTTRnCC0 TRnCCR1 D10 TRnCCR1 buffer 0000H D10 D11 D11 INTTRnCC1 TORn0 TORn1 INTTRnOV TRnOVF TRnOVF 0 write clear TRnOVF 0 write clear Remarks: 1. D00, D01: Setting values of TRnCCR0 register (0000H to FFFFH) D10, D11: Setting values of TRnCCR1 register (0000H to FFFFH) 2. TORn0 (toggle) width = (setting value of TRnCCR0 register + 1) x (count clock cycle) 3. TORn1 (toggle) width = (setting value of TRnCCR1 register + 1) x (count clock cycle) 4. Pins TORn0 and TORn1 become high level at count start. 5. n = 0, 1 User's Manual U16580EE3V1UD00 411 Chapter 10 (4) 16-bit Inverter Timer/Counter R Capture function (TRnCCS1 = 1, TRnCCS0 = 1) When TRnCTL0 register bit TRnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTRnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared. The count operation is performed in the free-running mode until TRnCE = 0 is set. When, during count operation, the counter value is captured to the TRnCCR0 and TRnCCR1 registers through detection of the valid edge of capture input (TIRn1, TIRn0), a capture interrupt (INTTRnCC0, INTTRnCC1) is output. Regarding capture in the vicinity of overflow (FFFFH), judgment is possible with the overflow flag (TRnOVF). However, judgment with the TRnOVF flag is not possible when the capture trigger interval is such that it includes two overflow occurrences (2 or more free-running cycles). Cautions: 1. In free-running mode the external event clock input (TEVTR1) is prohibited (TR1CTL1.TR1EEE = 0). 2. When an internal count clock fXX/16 (TRnCTL0.TRnCKS2-0) is selected in freerunning mode, the TRnCCR0 and TRnCCR1 registers are used as capture registers, the a value of FFFFH will be captured if a valid signal edge is input before the first count up. Figure 10-52: Basic Operation Timing in Free-Running Mode (Capture Function) When TORn0, TORn1 are not output (TRnOE0, 1 = 0, TRnOL0, 1 = 0) FFFFH D10 D02 D00 D12 D01 Counter D11 D03 TRnCE TIRn0 TRnCCR0 0000H D00 D01 D02 D03 TIRn1 0000H TRnCCR1 D10 D11 D12 Remarks: 1. D00, D01: Values captured to TRnCCR0 register (0000H to FFFFH) D10, D11: Values captured to TRnCCR1 register (0000H to FFFFH) 2. TIRn0: Setting to rising edge detection (TRnIOC1 register bits TRnIS1, TRnIS0 = 01) TIRn1: Setting to falling edge detection (TRnIOC1 register bits TRnIS3, TRnIS2 = 10) 3. n = 0, 1 412 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (5) Compare/capture function (TRnCCS1 = 0, TRnCCS0 = 1) When TRnCTL0 register bit TRnCE is set to 1, the counter counts from 0000H to FFFFH, an overflow interrupt (INTTRnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared. The count operation is performed in the free-running mode until TRnCE = 0 is set. The TRnCCR1 register is used as a compare register, and as the interval function upon a match between the counter and TRnCCR1 register, a compare match interrupt (INTTRnCC1) is output. Since the TRnCCR0 register is set to the capture function, the TORn0 pin cannot be controlled even when TRnIOC0 register bit TRnOE0 is set to 1. Cautions: 1. In free-running mode the external event clock input (TEVTR1) is prohibited (TR1CTL1.TR1EEE = 0). 2. When an internal count clock fXX/16 (TRnCTL0.TRnCKS2-0) is selected in freerunning mode, and TRnCCR0 register is used as capture register, the a value of FFFFH will be captured if a valid signal edge is input before the first count up. Figure 10-53: Basic Operation Timing in Free-Running Mode (Compare/Capture Function) When value of TRnCCR1 is rewritten, TORn0, TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH D02 D00 D03 D10 D12 Counter D01 D11 D11 TRnCE TIRn0 0000H TRnCCR0 D01 D00 D02 D03 INTTRnCC0 capture interrupt D10 TRnCCR1 TRnCCR1 buffer 0000H D10 D11 D11 D12 D12 INTTRnCC1 Match interrupt INTTRnOV overflow interrupt TORn0 Low TORn1 Remarks: 1. D00, D01: Setting values of TRnCCR1 register (0000H to FFFFH) D10, D11, D12, D13, D14, D15: Values captured to TRnCCR0 register (0000H to FFFFH) 2. TIRn0: Setting to rising edge detection (TRnIOC1 register bits TtnIS1, TtnIS0 = 11) 3. n = 0, 1 User's Manual U16580EE3V1UD00 413 Chapter 10 (6) 16-bit Inverter Timer/Counter R Overflow flag When, in the free-running mode, the counter overflows from FFFFH to 0000H, the overflow flag (TRnOVF) is set to "1", and an overflow interrupt (INTTRnOV) is output. The overflow flag is cleared through 0 write from the CPU. (The overflow flag is not cleared by just being read.) 414 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.10.7 Pulse width measurement mode (TMR1 only) (1) Outline of pulse width measurement mode In the pulse width measurement mode, counting is performed in the free-running mode. The counter value is saved to the TR1CCR0 register, and the counter is cleared to 0000H. As a result, the external input pulse width can be measured. However, when measuring a long pulse width that exceeds counter overflow, perform judgment with the overflow flag. Measurement of pulses during which overflow occurs twice or more is not possible, so adjust the counter's operating frequency. Even in the case of TIR11 to TIR13 pin edge detection, pulse width measurement can be similarly performed by using the TR1CCR1 to TR1CCR3 registers. Figure 10-54: Basic Operation Timing in Pulse Width Measurement Mode (TR1OE0, 1 = 0, TR1OL0, 1 = 0) FFFFH FFFFH D01 Counter D03 D02 D00 TR1CE TIR10 TR1CCR0 0000H D00 D01 D02 D03 INTTR1CC0 TR1OVF Cleared through 0 write from CPU INTTR1OV Remarks: 1. D00, D01, D02, D03: Values captured to TR1CCR0 register (0000H to FFFFH) 2. TIR10: Setting to rising edge/falling edge (both edges) detection (TRnIOC1 register bits TR1IS1, TR1IS0 = 1B) Cautions: 1. In the pulse width measurement mode the external event clock input (TEVTR1) is prohibited (TR1CTL1.TR1EEE = 0). 2. When an internal count clock fXX/16 (TP1CTL0.TP1CKS2-0) is selected in pulse width measurement mode, and a valid signal edge is input before the first count up, the a value of FFFFH will be captured in the corresponding TP1CCR0 or TP1CCR1 register. User's Manual U16580EE3V1UD00 415 Chapter 10 (2) 16-bit Inverter Timer/Counter R Pulse width measurement mode operation list (a) Compare register Register Rewrite Method Rewrite during Operation Function TR1CCR0 - - Capture value TR1CCR1 to TR1CCR3 - - Capture value TR1CCR4, TR1CCR5 - - - (b) Input pins Pin Function TIR1m Input capture trigger, transfer counter value to TR1CCRm register (m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output pins Pin Function TOR10 to TOR15 - TOR16, TOR17 - (d) Interrupts Interrupt 416 Function INTTR1CCm TIR1m capture (m = 0 to 3) INTTR1CC4, INTTR1CC5 - INTTR1OV Overflow INTTR1ER - User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.10.8 Triangular wave PWM mode (1) Outline of triangular wave PWM mode In the triangular wave PWM mode, similarly to in the PWM mode, when the duty is set to the TRnCCR1 to TRnCCR5 registers, the cycle is set to the TRnCCR0 register, and TRnCE = 1 is set, variable duty and cycle type triangular wave PWM output is performed from pins TORn1 to TORn5. The TORn0 pin is toggle output upon a match with the TRnCCR0 buffer register and upon counter underflow. Upon a match between the counter and TRnCCR0 register during count operation, compare match interrupts (INTTRnCC0 to INTTRnCC5) are output, and upon a match between the counter and TRnCCR1 to TRnCCR5 registers, a compare match interrupt (INTTRnCC1) is output. Moreover, upon counter underflow, an overflow interrupt (INTTRnOV) is output. The TRnCCR0 to TRnCCR5 registers can be rewritten during count operation. Compare register reload occurs upon a match between the counter value and the TRnCCR0 buffer register. However, since the next reload timing becomes valid when the TRnCCR1 register is written to, write the same value to the TRnCCR1 register even when wishing to rewrite only the value of the TRnCCR0 register. Reloading is not performed if only the TRnCCR0 register is rewritten. The reload timing is the underflow timing. In the triangular wave PWM mode, the TRnCCR0 to TRnCCR3 registers have their function fixed as compare registers, so the capture function cannot be used. Remark: In the triangular wave PWM mode, set the TRnCCR0 register to a value of 0 TRnCCR0 FFFEH. User's Manual U16580EE3V1UD00 417 Chapter 10 (2) 16-bit Inverter Timer/Counter R Triangular wave PWM mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible 1/2 of cycle TRnCCR1 to TRnCCR3 Reload Possible 1/2 of duty TRnCCR4, TRnCCR5 Reload Possible 1/2 of duty (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output pins Pin Function TORn0 Inactive during counter up count, active during down count TORnm PWM output upon TRnCCRm register compare match (m = 0 to 5) TORn6 - TORn7 Pulse output through A/D conversion trigger (d) Interrupts Interrupt 418 Function INTTRnCCm TRnCCRm register compare match (m = 0 to 5) INTTRnOV - INTTRnER Error User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-55: Basic Operation Timing in Triangular Wave PWM Mode When TORn0, TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH FFFFH D00 D00 D00 Counter D10 D10 D10 TRnCE TRnCCR0 TRnCCR1 0000H D00 0000H D10 INTTRnCC0 INTTRnCC1 INTTRnOV TORn0 TORn1 Remark: n = 0, 1 User's Manual U16580EE3V1UD00 419 Chapter 10 16-bit Inverter Timer/Counter R 10.10.9 High-accuracy T-PWM mode (1) Outline of high-accuracy T-PWM mode The high-accuracy T-PWM mode generates 6-phase PWM using four 16-bit counters (up/down, 2 counts, 15 real bits) and 16-bit compare registers (LSB = additional pulse control). The carrier wave cycle calculated with "TRnCCR0-TRnDTC0-TRnDTC1" is set to the TRnCCR0 register. The duty of the U phase, V phase, and W phase voltage data signal is set with the TRnCCR1 to TRnCCR3 registers. The dead time is set with the TRnDTC0 and TRnDTC1 registers, and the TRnDTC0 register can be used to set the inverted phase (OFF) normal phase (ON) dead time, while the TRnDTC1 register can be used to set the normal phase (OFF) inverted phase (ON) dead time. The counter operation consists in performing up count with the TRnDTC0 register value as the minimum value, and upon a match with the maximum value indicated by "TRnCCR0-TRnDTC1", performing down count. The 10-bit counters for dead time generation (TRnDTT1 to TRnDTT3) load the setting values of the TRnDTC0 and TRnDTC1 registers upon a match between the counter and the TRnCCR1 to TRnCCR3 registers, and perform down-count. Upon a match between the 16-bit counter and the TRnCCR1 to TRnCCR3 registers, INTTRnCC1 to INTTRnCC3, which are used as the respective compare match interrupt signals, are output. (In the 0% output vicinity and 100% output vicinity, no interrupt signal may be output.) Figure 10-56: High-Accuracy T-PWM Mode Block Diagram TRnCNT TRnSBC Load (16-bit up/down counter - 2) (16-bit up/down counter - 2) U/D U/D Sel0 Sel1 TRnDTC0 SEL TRnCCR0 buffer TRnTOS INTTRnOD (valley interrupt) TRnCCR0-TRnDTC1 0000H INTTRnCD0 (peak interrupt) TRnDTT1 Load TRnDTT4 TRnCCR1 (U phase output data) TRnDTT2 Load TRnDTT5 TRnCCR2 (V phase output data) TRnDTT3 Load TRnDTT6 TRnCCR3 (W phase output data) TRnDTC0 420 TRnDTC1 User's Manual U16580EE3V1UD00 SEL TORn0 TO1 TORn1(U) TO2 TORn2(U) TO3 TORn3(V) TO4 TORn4(V) TO5 TORn5(W) TO6 TORn6(W) Chapter 10 16-bit Inverter Timer/Counter R (2) High-accuracy T-PWM mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload, Anytime rewrite Possible Cycle TRnCCR1 to TRnCCR3 Reload, Anytime rewrite Possible PWM duty TRnCCR4, TRnCCR5 Reload, Anytime rewrite Possible PWM duty (selectable as A/D conversion trigger) (b) Input pins Pin Function TIR1m -(m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output Pins Pin Function TORn0 Inactive during counter or sub-counter up count, active during down count TORn1 PWM output upon TRnCCR1 compare match (with dead time) TORn2 Inverted output to TORn1 TORn3 PWM output upon TRnCCR2 compare match (with dead time) TORn4 Inverted output to TORn3 TORn5 PWM output upon TRnCCR3 compare match (with dead time) TORn6 Inverted output to TORn5 TORn7 Pulse output through A/D conversion trigger (d) Interrupts Interrupt Function INTTRnCCR0 INTTRnCCR0 compare INTTRnCC1 to INTTRnCC5 TRnCCR1 to TRnCCR5 compare match INTTRnOV OverflowNote 2 INTTRnER Error INTTRnOD Through interrupt INTTRnCD Peak interrupt matchNote 1 Notes: 1. Only when TRnDTC1 = 000H 2. When TRnCCR0, TRnDTC0, and TRnDTC1 registers are incorrectly set. User's Manual U16580EE3V1UD00 421 Chapter 10 (3) 16-bit Inverter Timer/Counter R High-accuracy T-PWM mode settings (a) Mode settings The high-accuracy T-PWM mode is selected by setting TRnCTL1 register bits TRnMD4 to 0 = 1000B. (b) Output level/output enable settings Set bits TRnOL0-TRnOL7 and TRnOE0-TRnOE7 of the TRnIOC0, TRnIOC3 registers, to enable output level/output enable. Pin TORn0 indicates the counter's and sub-counter's up count/down count status. The counter/ sub-counter can be switched with TRnOPT7 register bit TRnTOR. Pin TORn7 is the external A/D conversion output pin. Set this pin as required. (c) Error interrupt output enable Set error interrupt output enable upon detection of normal phase/inverted phase simultaneous active. Error interrupt output is enabled by setting TRnIOC4 register bit TRnEOC to "1". In the high-accuracy T-PWM mode, when the dead time setting is other than "000H", the error interrupt (INTTRnER) never goes active, regardless of which value the TRnCCR0 to TRnCCR3 registers are set. However, an error may be detected upon the occurrence of a timer Rn internal circuit fault. If the dead time setting is "000H", a glitch may occur upon occurrence of an error interrupt (INTTRnER) at the normal phase and inverted phase switch timing. (d) Rewrite timing for registers with reload function Batch rewrite/anytime rewrite can be set for registers with the reload function. This setting is performed with TRnOPT0 register bit RnCMS. (The default is "0" batch rewrite). To perform batch rewrite, be sure to set TRnOPT1 register bit TRnICE or TRnIOE. (If bit TRnICE and bit TRnIOE are both "0", the reload timing does not occur.) If anytime rewrite is selected, unintended output may occur depending on the rewrite timing. (When using the anytime rewrite function, refer to cautions (a) to (c) in 10.4.2 (1) Anytime rewrite.) (e) Interrupt and thinning out function settings The interrupt and thinning out function settings are performed with the TRnOPT1 register. If a peak interrupt (INTTRnCD) is required, set bit TRnICE to 1. If a valley interrupt (INTTRnOD) is required, set bit TRnIOE to 1. To use the thinning out function for peak/valley interrupts, perform settings with the TRnID4 to TRnID0 registers. (f) Reload thinning out function setting To set the reload timing to the same timing as the interrupt timing, set TRnOPT1 register bit TRnRDE to 1. 422 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (g) A/D conversion trigger output settings To set A/D conversion trigger 0 (TRnADTRG0 signal), set TRnOPT2 register bits TRnAT05 to TRnAT00. With bits TRnAT05 to TRnAT00, peak interrupt (INTTRnCD) and valley interrupt (INTTRnOD) enable/disable is performed at the TRnCCR5 register match timing (counter up count/down count), and the TRnCCR4 register match timing (counter up count/down count). To set A/D conversion trigger 1 (TRnADTRG1 signal), set TRnOPT3 register bits TRnAT15 to TRnAT10. With bits TRnAT15 to TRnAT10, peak interrupt (INTTRnCD) and valley interrupt (INTTRnOD) enable/disable is performed at the TRnCCR5 register match timing (counter up count/down count), and TRnCCR4 register match timing (counter up count/down count). Set the TRnCCR4 and TRnCCR5 registers' compare values. For the TRnADTRG0 and TRnADTRG1 signals, also perform the thinning out function setting. Caution: To use the TORn7 pin, correctly perform the TRnOPT2 and TRnOPT3 register and the TRnCCR4 and TRnCCR5 register settings. (h) Dead time settings The dead time settings are performed with the TRnDTC0 and TRnDTC1 registers. The dead time can be obtained with counter operation clock cycle (P) x TRnDTC0, TRnDTC1. The time until TORn2,TORn4,TORn6 pin inactive change TORn1,TORn3,TORn5 pin active change can be set with the TRnDTC0 register. The time until TORn1,TORn3,TORn5 pin inactive change TORn2,TORn4,TORn6 pin active change can be set with the TRnDTC1 register. (i) Carrier wave cycle For the carrier wave cycle, set the TRnCCR0 register using the following equation. TRnCCR0 = (carrier wave cycle/ counter operation clock cycle) + TRnDTC1 + TRnDTC0 For the setting value of the TRnCCR0 register, meet the following conditions keeping in mind the dead time. TRnCCR0 > 3 x MAX (TRnDTC0, TRnDTC1) + MIN (TRnDTC0, TRnDTC1) TRnCCR0 FFFEH (MAX(A,B) indicates the larger value of A and B, and MIN(A,B) indicates the smaller value of A and B.) (j) Duty (PWM width) setting For the duty setting, perform the U phase, V phase, and W phase settings with the TRnCCR1 to TRnCCR3 registers. The setting range of the TRnCCR1 to TRnCCR3 registers is 0000H TRnCCR1, TRnCCR2, TRnCCR3 TRnCCR0 + 1. Do not set TRnCCR0 + 2 < TRnCCR1, TRnCCR2, TRnCCR3. LSB (Least Significant Bit) of the TRnCCR1 to TRnCCR3 registers means the additional pulse setting. For example, if TRnCCR1 = 0003H is set, compare to when TRnCCR1 = 0002H is set, the inverted phase (pin TORn2) change is an 1-count clock delay (during counter up count). User's Manual U16580EE3V1UD00 423 Chapter 10 (4) 16-bit Inverter Timer/Counter R Counter operation in high-accuracy T-PWM mode At initial value FFFEH, the TRnDTC0 value is loaded to the counter immediately after TRnCE = 1 is set, and the counter counts up in +2 steps. Then, upon a match with TRnCCR0 to TRnDTC1, the counter counts down in -2 steps. The counter operation is as follows. Figure 10-57: Counter Operation in High-Accuracy T-PWM Mode TRnCE = "1" FFFEH TRnCCR0 TRnCCR0TRnDTC1 TRnCNT +2 count 2 count TRnDTC0 0000H Remark: Minimum counter value: Maximum counter value: Carrier wave cycle: TRnDTC0 TRnCCR0 - TRnDTC1 (TRnCCR0-TRnDTC0-TRnDTC1) x count clock cycle At initial value FFFEH, the value of TRnDTC0 register is loaded to the sub-counter immediately after TRnCE = 1 is set. Then, until a match with 0000H, the sub-counter counts down in -2 steps, and the counter value is loaded to the sub-counter at the counter's up count down count switch timing. The TRnDTC0 register goes on counting up, and upon a match with the TRnCCR0 register, starts counting down in -2 steps. At the same time, upon a match between the counter and the TRnDTC0 register, the counter value is loaded and down count is continued. The sub-counter operation is as follows. Figure 10-58: FFFEH Sub-Counter Operation in High-Accuracy T-PWM Mode TRnCE = "1" Load TRnCCR0 TRnCCR0TRnDTC1 TRnSBC TRnCNT +2 count 2 count TRnDTC0 0000H 424 Load User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (5) Basic operation in high-accuracy T-PWM mode The Figure 10-59 shows the timing chart when TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H, and the TRnCCR1 register is set from 0000H to 0010H (one part only shown). In this example, TRnOL6 to TRnOL1 = 000000B is set. If TRnCCR1 > TRnDTC0, pin TORn2 changes with the following compare match. Since TRnCCR1 = (TRnDTC0-0001H) is an additional pulse, compared to when TRnCCR1 = (TRnDTC0 - 0002H), pin TORn2 changes with an 1 count clock delay. Figure 10-59: Timer Output Example When TRnCE = 1 Is Set (Initial) (High-Accuracy T-PWM Mode) Counter FFFE 000200040006 0008 000A 000C 000A 0008000600040002 0004 Sub-counter FFFE 0002 00000002000400060008 000E 0010 000E 000C 000A 0000 TRnCE TRnCUF TRnSUF TRnCCR0 0010H (for cycle setting) TRnDTC0 002H (for dead time setting) TRnDTC1 004H (for dead time setting) [TRnCCR1 = 0000H] TORn1 TORn2 [TRnCCR1 = 0001H] TORn1 TORn2 [TRnCCR1 = 0002H] TORn1 TD0 TORn2 [TRnCCR1 = 0004H] TORn1 TORn2 [TRnCCR1 = 0008H] TORn1 TD0 TD0 TD1 TORn2 [TRnCCR1 = 000AH] TORn1 "L" TD1 TORn2 [TRnCCR1 = 000CH] TORn1 "L" TD1 TORn2 [TRnCCR1 = 000EH] TORn1 "L" TS1 TORn2 [TRnCCR1 = 0010H] TORn1 TORn2 Remarks: 1. TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H 2. TD0: Time depends on dead time setting of TRnDTC0 register TD1: Time depends on dead time setting of TRnDTC1 register TS1: Time is determined through sub-counter compare, when sub-counter value > counter value 3. n = 0, 1 User's Manual U16580EE3V1UD00 425 Chapter 10 16-bit Inverter Timer/Counter R The Figure 10-60 shows the timing chart when TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H, and the TRnCCR1 register is set from 0000H to 0010H (one part only shown). In this example, TRnOL6 to TRnOL1 = 000000B is set. As can be seen in this figure, a normal phase (pin TORn1) that is active (high level) is output when 0000H TRnCCR1 (TRnCCR0 - TRnDTC0 + 0001H). Also, the inverted phase (pin TORn0) that is active (high level) is output when (TRnDTC0 + TRnDTC1) < TRnCCR1 TRnCCR0. Figure 10-60: Timer Output Example During Operation (High-Accuracy T-PWM Mode) Counter 00040002 00040006 0008 000A 000C 000A 0008000600040002 00040006 Sub-counter 000C 000A 00000002000400060008 000E 0010 000E 000C 000A 0000 0002 TRnCE TRnCUF TRnSUF TRnCCR0 0010H (for cycle setting) TRnDTC0 002H (for dead time setting) TRnDTC1 004H (for dead time setting) [TRnCCR1 = 0000H] TORn1 TORn2 "L" [TRnCCR1 = 0001H] TORn1 TORn2 "L" [TRnCCR1 = 0002H] TD0 TORn1 TORn2 "L" [TRnCCR1 = 0004H] TORn1 TORn2 [TRnCCR1 = 0008H] TORn1 TD0 TD0 TD1 TORn2 [TRnCCR1 = 000AH] TORn1 "L" TD1 TORn2 [TRnCCR1 = 000CH] TORn1 "L" TORn2 [TRnCCR1 = 000EH] TORn1 "L" TD1 TS1 TORn2 [TRnCCR1 = 0010H] TORn1 TORn2 Remarks: 1. TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H 2. TD0: Time depends on dead time setting of TRnDTC0 register TD1: Time depends on dead time setting of TRnDTC1 register TS0: Time is determined through sub-counter compare, when sub-counter value < counter value TS1: Time is determined through sub-counter compare, when sub-counter value > counter value 3. n = 0, 1 426 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (6) Additional pulse control in high-accuracy T-PWM mode In the high-accuracy T-PWM mode, additional pulse can be set by setting the LSB of the duty setting registers (TRnCCR1 to TRnCCR3) to "1". With the additional pulse control function, finer duty control can be performed (higher accuracy). TORn1 pin output examples are provided below for when additional pulse control is and is not performed. The settings used here are TRnCCR = 12, TRnDTC0, and TRnDTC1 = 0. Figure 10-61: TORn1 Pin Output Example When Performing Additional Pulse Control 1 Count clock Counter value 0 2 2 4 3 6 4 8 5 6 7 10 12 10 TRnCCR1 = 0 12 TRnCCR1 = 1 11 TRnCCR1 = 2 10 TRnCCR1 = 3 8 TRnCCR1 = 5 7 TRnCCR1 = 6 6 TRnCCR1 = 7 5 TRnCCR1 = 9 8 9 6 10 4 11 2 12 0 2 4 9 TRnCCR1 = 4 TRnCCR1 = 8 8 4 3 TRnCCR1 = 10 2 TRnCCR1 = 11 1 TRnCCR1 = 12 0 Remarks: 1. TRnCCR0 = 12, TRnDTC0 = 0, TRnDTC1 = 0 2. n = 0, 1 The locations where additional pulse control is performed are when an odd value has been set to the TRnCCR1 register. In the above figure, the arrows and numbers indicate the duty width of the TORn1 pin output within 1 cycle. As can be seen in the above figure, when additional pulse control is performed, the output width (duty ratio) of pin TORn1 can be controlled in 1 count clock steps from 12 clocks to 0 clocks. User's Manual U16580EE3V1UD00 427 Chapter 10 Figure 10-62: 16-bit Inverter Timer/Counter R TORn1 Pin Output Example When Additional Pulse Control Is Not Performed 1 Count clock 0 2 2 4 3 4 6 5 8 10 6 12 TRnCCR1 = 0 12 TRnCCR1 = 2 10 TRnCCR1 = 4 8 TRnCCR1 = 6 6 TRnCCR1 = 8 4 TRnCCR1 = 10 2 TRnCCR1 = 12 0 7 10 8 8 9 10 6 4 11 12 2 0 2 4 Remarks: 1. TRnCCR0 = 12, TRnDTC0 = 0, TRnDTC1 = 0 2. n = 0, 1 The figure above is an example when additional pulse control is not performed. In the above figure, the arrows and numbers indicate the duty width of the TORn1 pin output within 1 cycle. When additional pulse control is not performed, the output width of pin TORn1 can be controlled in 2 count clock steps from 12 clocks to 0 clocks. In this case, the duty change amount is larger compared to when additional pulse control is performed. 428 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (7) Caution on timer output in high-accuracy T-PWM mode There are cautions for TRnCCR1 to TRnCCR3 as follows when varying 6-phase PWM duty by using reload (batch rewrite). (a) In case of TRnCCR0 + 2 TRnCCRm (Setting prohibited) Figure 10-63a shows the case when the value of "TRnCCR0 + 2 or more" is set to the TRnCCR1 register. When the TRnCCR1 register setting is changed like this, a match between the 16-bit counter and TRnCCR1 register does not occur thereafter. Therefore, the TORn1 pin output level is forcibly changed to inactive level at the following 16-bit sub-counter trough timing. Output will be switched at 16-bit sub-counter peak/trough timing after that. Figure 10-63: Timings of Timer Output in High-accuracy T-PWM mode (1/3) (a) Output When TRnCCR0 + 2 TRnCCR1 16-bit sub-counter 16-bit counter x x y y xx x y x x 0000H TRnCCR1 x y TORn1 TORn2 Reload timing Output is toggled at a peak/trough timing of 16-bit sub-counter when TRnCCR1 > TRnCCR0 + 1 Note: m = 1 to 3 User's Manual U16580EE3V1UD00 429 Chapter 10 16-bit Inverter Timer/Counter R (b) In case of rewriting from TRnCCRm = 0000H to TRnCCRm = TRnCCR0 Figure 10-63b shows the output waveform where the TRnCCR1 register setting is changed from 100% output to 0% output. The TORn1 pin output is inverted upon a match between the TRnCCR1 register and 16-bit sub-counter, and the TORn2 pin output is inverted after the dead time count. Figure 10-63: Timings of Timer Output in High-accuracy T-PWM mode (2/3) (b) Output When Rewriting from TRnCCR1 = 0000H to TRnCCR1 = TRnCCR0 16-bit sub-counter n 16-bit counter 0000H 0000H TRnCCR1 n = TRnCCR0 TORn1 TORn2 Output is inverted upon a match between 16-bit sub-counter and TRnCCR1 Reload timing Note: m = 1 to 3 (c) In case of rewriting from "TRnDTC0 + TRnDTC1 < TRnCCRm < TRnCCR0 - TRnDTC0 - TRnDTC1" to "TRnCCRm < TRnDTC0 + TRnDTC1" Figure 10-63c shows the output waveform when rewriting the TRnCCR1 register from x (TRnDTC0 + TRnDTC1 < x < TRnCCR0 - TRnDTC0 - TRnDTC1) to y (y < TRnDTC0 + TRnDTC1). In this case, the TORn1 pin output becomes active when the TORn1 pin set condition occurs upon a match between the 16-bit counter (or 16-bit sub-counter) and the TRnCCR1 register immediately after reload (batch rewrite). (c) Output When Rewriting from TRnDTC0 + TRnDTC1 < TRnCCR1 < TRnCCR0 - TRnDTC0 - TRnDTC1 to TRnCCR1 < TRnDTC0 + TRnDTC1 16-bit sub-counter 16-bit counter x x x x y y 0000H TRnCCR1 x y TORn1 TORn2 Reload timing Note: m = 1 to 3 430 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (d) In case of rewriting from "TRnDTC0 + TRnDTC1 < TRnCCRm < TRnCCR0 - TRnDTC0 - TRnDTC1" to "TRnCCR0 - TRnDTC1 + 1 < TRnCCRm < TRnCCR0" Figure 10-63d shows the output waveform when rewriting the TRnCCR1 register from x (TRnDTC0 + TRnDTC1 < x < TRnCCR0 - TRnDTC0 - TRnDTC1) to y (TRnCCR0 - TRnDTC0 - TRnDTC1 < TRnDTC0 < TRnCCR0). In this case, the TORn2 pin output becomes inactive (high level) when the TORn2 pin set condition occurs upon a match between the 16-bit counter (or 16bit sub-counter) and TRnCCRm register immediately after batch rewrite. Figure 10-63: Timings of Timer Output in High-accuracy T-PWM mode (3/3) (d) Output When Rewriting from "TRnDTC0 + TRnDTC1 < TRnCCR1 < TRnCCR0 - TRnDTC0 - TRnDTC1" to "TRnCCR0 - TRnDTC1 + 1 < TRnCCR1 < TRnCCR0" 16-bit sub-counter 16-bit counter x x y y y x 0000H TRnCCR1 x y TORn1 TORn2 Reload timing Note: m = 1 to 3 User's Manual U16580EE3V1UD00 431 Chapter 10 (8) 16-bit Inverter Timer/Counter R Timer output change after compare register updating Timer output is affected when the compare register value is updated during reload execution. The timer output level is changed at any timing listed in Tables 10-1 and 10-2. Table 10-1: Positive Phase Operation Condition List Operation Symbol Condition Set ST1 Match between counting up near the 16-bit sub-counter trough and compare register values (< TRnDTC0) Clear RT1 Match between counting down near the 16-bit sub-counter trough and compare register values (< TRnDTC0) Set ST2 At completion of dead time counter (TRnDTC0) operation Clear RT2 When 16-bit counter value matches with compare register value during count-down operation Set ST3 100% output for PWM duty Clear RT3 When no match occurs until 16-bit sub-counter counts down to 0000H Clear RT4 TRnCCR0 and TRnDTC0 settings are changed at a reload timing. Though neither a match (nor a match interrupt) occurs between TRnCCR0 and TRnDTC0, the operation is cleared by special processing. Clear RT5 The operation is cleared upon a match between peripheral 16-bit sub-counter peak and compare register values in positive phase active level. Table 10-2: Negative Phase Operation Condition List Operation Symbol Set SB1 Match between counting down near the 16-bit sub-counter peak and compare register values (> TRnCCR0 - TRnDTC1) Clear RB1 Match between counting up near the 16-bit sub-counter peak and compare register values (> TRnCCR0 - TRnDTC1) Set SB2 At completion of dead time counter (TRnDTC1) operation Clear RB2 When 16-bit counter value matches with compare register value during count-up operation Set SB3 100% output for PWM duty Clear RB3 When no match occurs until 16-bit sub-counter counts up to TRnCCR0 Clear RB4 TRnCCR0 and TRnDTC0 settings are changed at a reload timing. Though neither a match (nor a match interrupt) occurs between TRnCCR0 and TRnDTC1, the operation is cleared by special processing. Clear RB5 The operation is cleared upon a match between peripheral 16-bit sub-counter trough and compare register values in negative phase active level. 432 Condition User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Table 10-3: Compare Register Value After Trough Reload (TRnDTC0 < TRnDTC1) Compare Register Value Immediately Before Trough Reload 0000H Figure 10-64: Compare Register Value After Trough Reload (TRnDTC0 < TRnDTC1) Figure No. 0000H < TRnCCR1 to TRnCCR3 < TRnDTC0 Figureaa TRnCCR1 to TRnCCR3 = 0000H, TRnDTC0 + 1 Figureab TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 TRnDTC0 x 2 Figure 10-64c TRnDTC0 x 2 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC0 - TRnDTC1 Figure 10-64d TRnCCR0 - TRnDTC0 - TRnDTC1 TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 Figure 10-64e TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 < TRnCCR0 Figure 10-64f TRnCCR1 to TRnCCR3 = TRnCCR0 Figure 10-64g Timer Output Change after Compare Register Updating Timings (1/3) (a) TRnCCR1 to TRnCCR3 = 0000H 0000H < TRnCCR1 to TRnCCR3 < TRnDTC0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST3 RT1 "L" ST1 RT1 ST1 (b) TRnCCR1 to TRnCCR3 = 0000H TRnCCR1 to TRnCCR3 = TRnDTC0, TRnDTC0 + 1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST3 "L" RT4 ST1 RT1 User's Manual U16580EE3V1UD00 ST1 433 Chapter 10 Figure 10-64: 16-bit Inverter Timer/Counter R Timer Output Change after Compare Register Updating Timings (2/3) (c) TRnCCR1 to TRnCCR3 = 0000H TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnDTC0 x 2 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 ST3 ST2 RT2 TORn2, TORn5, "L" TORn6 ST2 RT2 RB2 RB2 When the values of TRnCCR1 to TRnCCR3 are changed from "0000H TRnCCR1 to TRnCCR3 < TRnDTC0" to "TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnDTC0 x 2", the positive phase will be 100% output for one cycle, as shown in Figure 10-64c. To prevent this phenomenon, change "0000H TRnCCR1 to TRnCCR3 < TRnDTC0" to "TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnDTC x 2" through TRnDTC0, or directly change "0000H TRnCCR1 to TRnCCR3 < TRnDTC0" to "TRnDTC0 x 2 TRnCCR1 to TRnCCR3". (d) TRnCCR1 to TRnCCR3 = 0000H TRnDTC0 x 2 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 - TRnDTC0 16-bit sub-counter TRnCCR1 to TRnCCR3 TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 434 ST3 RT3 SB2 RB2 ST2 RT2 ST2 RT2 SB2 User's Manual U16580EE3V1UD00 RB2 SB2 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-64: Timer Output Change after Compare Register Updating Timings (3/3) (e) TRnCCR1 to TRnCCR3 = 0000H TRnCCR0 - TRnDTC1 - TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST3 RT3 SB2 RT2 RT2 RB2 SB2 RB2 SB2 (f) TRnCCR1 to TRnCCR3 = 0000H TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST3 RT3 SB2 RB1 SB1 RB1 SB1 (g) TRnCCR1 to TRnCCR3 = 0000H TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST3 RT3 SB3 SB3 SB2 User's Manual U16580EE3V1UD00 435 Chapter 10 Table 10-4: Compare Register Value Immediately Before Trough Reload TRnCCR0 16-bit Inverter Timer/Counter R Compare Register Value After Trough Reload Compare Register Value After Trough Reload Figure No. TRnCCR1 to TRnCCR3 = 0000H Figure 10-65a 0000H < TRnCCR1 to TRnCCR3 < TRnDTC0 Figure 10-65b TRnCCR1 to TRnCCR3 = TRnDTC0, TRnDTC0 + 1 Figure 10-65c TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 < TRnDTC0 + TRnDTC1 Figure 10-65d TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC0 - TRnDTC1 Figure 10-65e TRnCCR0 - TRnDTC0 - TRnDTC1 TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 Figure 10-65f TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 < TRnCCR0 Figure 10-65g Figure 10-65: Compare Register Value After Trough Reload Timing (1/3) (a) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR1 to TRnCCR3 = 0000H TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST3 ST2 SB3 RB5 (b) TRnCCR1 to TRnCCR3 = TRnCCR0 0000H < TRnCCR1 to TRnCCR3 < TRnDTC0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST2 RT1 ST1 SB3 RB5 436 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-65: Compare Register Value After Trough Reload Timing (2/3) (c) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR1 to TRnCCR3 = TRnDTC0, TRnDTC0 + 1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST2 RT1 ST1 SB3 RB5 (d) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 TRnDTC0 + TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST2 RT2 ST2 SB3 RB2 (e) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 - TRnDTC0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 ST2 RT2 ST2 RT2 SB3 RB2 SB2 User's Manual U16580EE3V1UD00 RB2 SB2 437 Chapter 10 Figure 10-65: 16-bit Inverter Timer/Counter R Compare Register Value After Trough Reload Timing (3/3) (f) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR0 - TRnDTC1 - TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, "L" TORn5 TORn2, TORn4, TORn6 RT2 RT2 SB3 RB2 SB2 RB2 SB2 (g) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC0 - TRnDTC1 - TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, "L" TORn5 TORn2, TORn4, TORn6 SB3 RB1 Table 10-5: Compare Register Value Immediately Before Peak Reload TRnCCR0 438 SB1 RB1 SB1 Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) Figure No. TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 < TRnCCR0 Figure 10-66a TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 Figure 10-66b TRnCCR0 - TRnDTC1 x 2 TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 Figure 10-66c TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 x 2 Figure 10-66d TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 < TRnDTC0 + TRnDTC1 Figure 10-66e 0000H < TRnCCR1 to TRnCCR3 TRnDTC0 + TRnDTC1 Figure 10-66f TRnCCR1 to TRnCCR3 = 0000H Figure 10-66g User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (1/3) (a) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, "L" TORn5 TORn2, TORn4, SB3 TORn6 RB1 SB1 RB1 SB1 (b) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR1 to TRnCCR3 = TRnDTC0 - TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, "L" TORn5 TORn2, TORn4, TORn6 SB3 RB4 SB1 RB1 User's Manual U16580EE3V1UD00 SB1 439 Chapter 10 Figure 10-66: 16-bit Inverter Timer/Counter R Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (2/3) (c) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR0 - TRnDTC1 x 2 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 When the values of TRnCCR1 to TRnCCR3 are changed from "TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 TRnCCR0" to "TRnCCR0 - TRnDTC1 x 2 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1", the negative phase will be 100% output for one cycle, as shown in figure below. To prevent this phenomenon, change "TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 TRnCCR0" to "TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnDT1 x 2" through "TRnCCR0 - TRnDTC1", or directly change "TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0" to "TRnCCR1 to TRnCCR3 TRnCCR0 - TRnDTC1 x 2". TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit sub-counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, "L" TORn5 TORn2, TORn4, TORn6 RT2 RT2 SB3 SB1 RB1 SB1 RB1 (d) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 x 2 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 ST2 RT2 TORn2, TORn4, TORn6 440 ST2 ST2 RT2 SB3 RB3 SB2 RB2 User's Manual U16580EE3V1UD00 SB2 RB2 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (3/3) (e) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 TRnDTC0 + TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 ST2 TORn2, TORn4, TORn6 RT2 ST2 ST2 RT2 SB3 RB2 RB3 RB2 (f) TRnCCR1 to TRnCCR3 = TRnCCR0 0000H < TRnCCR1 to TRnCCR3 TRnDTC0 + 1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 ST2 TORn2, TORn4, TORn6 RT1 ST1 RT1 ST1 SB3 RB3 (g) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR1 to TRnCCR3 = 0000H TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 ST2 TORn2, TORn4, TORn6 ST3 ST3 SB3 RB3 User's Manual U16580EE3V1UD00 441 Chapter 10 Table 10-6: Compare Register Value Immediately Before Peak Reload 16-bit Inverter Timer/Counter R Compare Register Value After Trough Reload Compare Register Value After Trough Reload 0000H Figure No. TRnCCR1 to TRnCCR3 = TRnCCR0 Figure 10-67a TRnCCR0 - TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 Figure 10-67b TRnCCR1 to TRnCCR3 = TRnCCR0 - TRnDTC1 Figure 10-67c TRnCCR0 - TRnDTC0 - TRnDTC1 TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 Figure 10-67d TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC0 - TRnDTC1 Figure 10-67e TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 TRnDTC0 + TRnDTC1 Figure 10-67f 0000H < TRnCCR1 to TRnCCR3 TRnDTC0 + 1 Figure 10-67g Figure 10-67: Compare Register Value After Trough Reload (1/3) (a) TRnCCR1 to TRnCCR3 = 0000H TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 RT5 TORn2, TORn4, TORn6 SB2 (b) TRTRnCCR1 to TRnCCR3 = 0000H TRnCCR0 - TRnDTC1 < TRTRnCCR1 to TRnCCR3 < TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 442 RT5 SB2 RB1 SB1 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-67: Compare Register Value After Trough Reload (2/3) (c) TRnCCR1 to TRnCCR3 = 0000H TRnCCR1 to TRnCCR3 = TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 RT1 SB2 RB1 SB1 RB1 (d) TRnCCR1 to TRnCCR3 = 0000H TRnCCR0 - TRnDTC0 - TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 - TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 RT1 RT1 SB2 RB2 SB2 RB2 (e) TRnCCR1 to TRnCCR3 = 0000H TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 TRnCCR0 - TRnDTC0 - TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4, TORn6 RT2 ST2 SB2 RB2 User's Manual U16580EE3V1UD00 RT2 ST2 SB2 RB2 443 Chapter 10 Figure 10-67: 16-bit Inverter Timer/Counter R Compare Register Value After Trough Reload (3/3) (f) TRnCCR1 to TRnCCR3 = 0000H TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 < TRnDTC0 + TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit sub-counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 RT2 TORn2, TORn4, "L" TORn6 ST2 RT2 ST2 RB2 RB2 (g) TRnCCR1 to TRnCCR3 = 0000H 0000H < TRnCCR1 to TRnCCR3 TRnDTC0 + 1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 RT1 ST1 TORn2, TORn4, "L" TORn6 444 User's Manual U16580EE3V1UD00 RT1 ST1 Chapter 10 16-bit Inverter Timer/Counter R (9) Dead time control in high-accuracy T-PWM mode In the high-accuracy T-PWM mode, the TRnCCR1 to TRnCCR3 registers are used for duty setting and the TRnCCR0 register is used for cycle setting. By using these four registers, duty variable type 6-phase PWM waveform can be output. To implement dead time control, there are three 10bit down-counters that synchronously operate with the count clock of the 16-bit counter, and two dead time setting registers (TRnDTC0, TRnDTC1). The TRnDTC0 register is used to set the dead time from when a negative phase changes to inactive until a positive phase changes to active. The TRnDTC1 register is used to set the dead time from when a positive phase changes to inactive until a negative phase changes to active. The output waveform in case of TRnDTC0 = x, TRnDTC1 = y is shown below. Figure 10-68: TRnCCR2 16-bit counter Output Waveform Example When Dead Time Is Set 16-bit sub-counter TRnCCR1 TRnCCR2 TRnDTC0 = "x" TRnDTC1 = "y" SnCCR2 TRnCCR1 TRnCCR1 TRnCCR3 TRnCCR1 TRnCCR3 TRnCCR3 TRnDTT1 TORn1 x TORn2 y x y x y x TRnDTT2 TORn3 "L" TORn4 TRnDTT3 "L" TORn5 TORn6 "L" User's Manual U16580EE3V1UD00 445 Chapter 10 16-bit Inverter Timer/Counter R (10) Cautions on dead time control in high-accuracy T-PWM mode (a) Rewriting of TRnDTC0 and TRnDTC1 registers The setting of the dead time in the TRnDTC0, TRnDTC1 registers can be rewritten during operation. Note the following cautions when rewriting the dead time setting during operation. Cautions: 1. Rewrite the TRnDTC0 and TRnDTC1 registers when using the reload function (TRnCMS = 0). 2. When the TRnDTC0 and TRnDTC1 registers are rewritten, carrier-wave cycles will be changed. In cases where carrier-wave cycles should not be changed, rewrite the TRnCCR0 register value at the same time as changing the TRnDTC0 and TRnDTC1 registers. 3. Rewriting is prohibited when TRnCMS = 1. 4. In case of changing TRnCCR0 and TRnCCR1 at a 16-bit counter peak: Match interrupts (INTTRnCC1 to INTTRnCC5) will not occur immediately after reload execution if the values set in the TRnCCR1 to TRnCCR5 register matches with and TRnCCR0 - TRnDTC1 (the new maximum value of main counter) after updating. Figure 10-69: 16-bit sub-counter Reload execution TRnCCR0 TRnCCR0 to TRnDTC1 Dead Time Control in High-Accuracy T-PWM Mode TRnCCR1 16-bit counter 0000H INTTRnCC1 5. In case of changing TR0DTC0 at a 16-bit counter trough: Match interrupts (INTTRnCC1 to INTTRnCC5) will not occur immediately after reload execution if the values set in the TRnCCR1 to TRnCCR5 register match with TR0DTC0 (the new minimum value of main counter) after updating. TRnCCR0 16-bit sub-counter Reload execution 16-bit counter TRnCCR1 TRnDTC0 0000H INTTRnCC1 446 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (11) Caution on rewriting cycles in high-accuracy T-PWM mode In high-accuracy T-PWM mode, setting conditions for the TRnCCR0, TRnDTC0, and TRnDTC1 registers are as follows. * 3 x MAX (TRnDTC0, TRnDTC1) + MIN (TRnDTC0, TRnDTC1) < TRnCCR0 0002H < TRnCCR0 FFFEH * MAX (A, B) indicates the greater value of A and B, and MIN (A, B) indicates the smaller value of A and B. Figure 10-70 shows an operation example when the setting range is exceeded. This example shows the case where the TRnDTC0 register is set out of the range "TRnDTC0 TRnCCR0 - TRnDTC1". Though the 16-bit counter executes count-down operation, the countdown operation is executed from 0000H because no match occurs. In this case, the count operation continues by loading the TRnDTC0 register setting value. However, no match with TRnCCR0 - TRnDTC1 occurs in the count-up operation, thus the 16-bit counter overflows. In this case, the count operation continues by loading the TRnDTC0 register setting value again. An overflow interrupt (INTTRnOV) occurs when the 16-bit counter loads the TRnDTC0 register setting value from 0000H or when an overflow occurs at FFFEH, and then the TRnOVF flag is set. An overflow interrupt (INTTRnOV) does not occur if the TRnCCR0, TRnDTC0, and TRnDTC1 registers are set correctly, so this can be used for detecting incorrect settings. Figure 10-70: Operation Example Setting Is Out of Range FFFEH 16-bit counter 16-bit sub-counter TRnCCR0 to TRnDTC1 TRnDTC0 0000H Changed to "TRnDTC0 TRnCCR0 TRnDTC1" (out of settable range) INTTRnOV User's Manual U16580EE3V1UD00 447 Chapter 10 16-bit Inverter Timer/Counter R (12) Error interrupt (INTTRnER) in high-accuracy T-PWM mode The positive/negative simultaneous active detection function can be used in the high-accuracy T-PWM mode. Error interrupts (INTTRnER) do not occur in the high-accuracy T-PWM mode. In case of occurrence, the internal circuits may be damaged. Figure 10-71: Error Interrupt Operation Example 16-bit counter TORn1 TORn2 INTTRnER TRnTBF Damage occurrence in TORn2 control circuit Error interrupt output 448 Positive/negative simultaneous active detection flag set "0" write clear User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R 10.10.10 PWM mode with dead time (1) Outline of PWM mode with dead time In the PWM mode with dead time, 6-phase PWM is generated using the 16-bit counter's saw tooth wave operation and four 16-bit counters. The counter's maximum value is set with the TRnCCR0 register. The duties of the U phase, V phase, and W phase voltage data signals are set with the TRnCCR1 to TRnCCR3 registers. The dead time is set with the TRnDTC0 and TRnDTC1 registers, and the dead time for inverted phase normal phase and the dead time for normal phase inverted phase can be independently set with the TRnDTC0 register and TRnDTC1 register, respectively. The counter's operation consists in performing up count with 0000H as the minimum value, and when the maximum value (cycle) indicated by the TRnCCR0 register is matched, the counter is cleared (0000H), and the counter continues up-count operation. The 10-bit dead time counters (TRnDTT1 to TRnDTT3) reload the setting value of the TRnDTC0 and TRnDTC1 registers upon a match between the counter and the TRnCCR1 to TRnCCR3 registers, and perform down count. Upon a match between the 16-bit counter and the TRnCCR0 to TRnCCR3 registers, the corresponding compare match interrupts (INTTRnCC1 to INTTRnCC3) are output. Figure 10-72: Block Diagram in PWM Mode With Dead Time TRnCNT CLEAR LOAD TRnSBC (16-bit up counter + 1) TRnCCR0 (16-bit up counter + 1) SEL TRnCCR0+TRnDTC0 INTTRnCC0 INTTRnCD0 TRnDTT1 TO1 TORn1(U) TO2 TORn2(U) TO3 TORn3(V) TO4 TORn4(V) (10-bit counter) TRnCCR1 LOAD 0001H (U phase output data) TRnDTT2 (10-bit counter) TRnCCR2 LOAD 0001H (V phase output data) TO5 TORn5(W) TO6 TORn6(W) TRnDTT3 TRnCCR3 (10-bit counter) LOAD 0001H (W phase output data) TRnDTC0,1 (Dead time value) User's Manual U16580EE3V1UD00 449 Chapter 10 (2) 16-bit Inverter Timer/Counter R PWM mode with dead time operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Cycle TRnCCR1 to TRnCCR3 Reload Possible PWM duty TRnCCR4, TRnCCR5 Reload Possible PWM duty (b) Input pins Pin Function TIR1m - (m = 0 to 3) TTRGR1 - TEVTR1 - (c) Output pins Pin Function TORn0 Toggle output upon TRnCCR0 register compare match TORn1 PWM output (with dead time) upon TRnCCR1 register compare match TORn2 Inverted phase output to TORn1 TORn3 PWM output (with dead time) upon TRnCCR2 register compare match TORn4 Inverted phase output to TORn3 TORn5 PWM output (with dead time) upon TRnCCR3 register compare match TORn6 Inverted phase output to TORn5 TORn7 Pulse output through A/D conversion trigger (d) Interrupts Interrupt 450 Function INTTRnCCm TRnCCRm register compare match (m = 0 to 5) INTTRnOV - INTTRnER Error User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-73: Output Waveform Example in PWM Mode with Dead Time FFFFH m k j Counter j i i 0H m (for cycle setting) TRnCCR0 TRnCCR1 TRnCCR2 i (U phase duty) TRnCCR3 k (W phase duty) TRnDTC0 d0 TRnDTC1 d1 j (V phase duty) TRnDTT1 d0 TRnDTT2 d0 TRnDTT3 d0 d1 d0 d1 d0 d1 d1 d1 d0 TORn1 TORn2 TORn3 TORn4 TORn5 TORn6 U phase output width = i - d0 U phase output width = i + d1 V phase output width = j - d0 V phase output width = j + d1 W phase output width = k - d0 W phase output width = k + d1 Remarks: 1. The maximum value that can be set to the TRnCCR1 to TRnCCR3 registers is TRnCCR0 + TRnDTC0. 2. If "0000H" is set to the TRnCCR1 to TRnCCR3 registers, PWM is output with 0% duty. 3. If TRnCCR0 + TRnDTC0 is set to the TRnCCR1 to TRnCCR3 registers, PWM is output with 100% duty. 4. The maximum value of the TRnCCR0 register is FFFFH - TRnDTC0. 5. Perform setting so as to satisfy condition FFFFH > TRnCCR0 + TRnDTC0. User's Manual U16580EE3V1UD00 451 Chapter 10 (3) 16-bit Inverter Timer/Counter R PWM mode with dead time settings (a) Mode setting The PWM mode with dead time is set by setting TRnCTL1 register bits TRnMD4 to TRnMD0 = 1001. (b) Output level/output enable settings Output level/output enable is set by setting the TRnOL0 to TRnOL7 and TRnOE0 to TRnOE7 bits of the TRnIOC0 and TRnIOC3 registers. Pin TORn0 performs toggle output upon cycle match (match between the counter and the TRnCCR0 register). Pin TORn7 is the output for A/D conversion. Set this pin as required. (c) Error output enable Set error output enable when normal phase/inverted phase simultaneous active is detected. Error output is enabled by setting TRnIOC4 register bit TRnEOC to 1. Moreover, the pin for detecting simultaneous active can also be set, by setting TRnIOC4 register bits TRnTBA2 to TRnTBA0. In the PWM mode with dead time, INTTRnER does not become active, regardless of which value the user sets to the TRnCCR0 to TRnCCR3 registers, except when the dead time setting is 0. When an error occurs, this indicates an internal circuit fault. (d) Interrupt and thinning out function settings A peak interrupt (INTTRnCD) occurs upon a match between the TRnCCR0 register and the counter (bit TRnIOE control is invalid). To output a peak interrupt, set TRnICE = 1. Use of the thinning out function for peak interrupts is done with the TRnID4 to TRnID0 registers. (e) Reload thinning out function setting To set the reload timing to the same timing as the interrupt timing, set TRnOPT1 register bit TRnRDE to 1. The reload timing occurs when TRnICE = 1. (f) A/D conversion trigger output setting A/D conversion trigger 0 (TRnADTRG0 signal) is set with TRnOPT2 register bits TRnAT04, TRnAT02, and TRnAT01. The TRnCCR5 register match timing, TRnCCR4 register match timing, and peak interrupt (INTTRnCD) enable/disable settings are performed with bits TRnAT04, TRnAT02, and TRnAT01. Do not set TRnAT05, TRnAT03, and TRnAT00 to "1". A/D conversion trigger 1 (TRnADTRG1 signal) is set with TRnOPT3 register bits TRnAT14, TRnAT12, and TRnAT11. The TRnCCR5 register match timing, TRnCCR4 register match timing, and peak interrupt (INTTRnCD) enable/disable settings are performed with bits TRnAT14, TRnAT12, and TRnAT11. Do not set bits TRnAT15, TRnAT13, and TRnAT10 to "1". Set the compare values of the TRnCCR4 and TRnCCR5 registers. 452 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R (g) Dead time settings The dead time settings are performed with the TRnDTC0 and TRnDTC1 registers. The dead time can be obtained with count clock cycle x TRnDTC0,TRnDTC1. The time until TORn2, TORn4, TORn6 pin inactive change TORn1, TORn3, TORn5 pin active change can be set with the TRnDTC0 register. The time until TORn1,TORn3,TORn5 pin inactive change TORn2, TORn4, TORn6 pin active change can be set with the TRnDTC1 register. (h) PWM cycle, duty (PWM width) setting The duty is set with the TRnCCR1 to TRnCCR3 registers. The setting range of the TRnCCR1 to TRnCCR3 registers is 0000H TRnCCRm (TRnCCR0 + TRnDTC0) The TRnCCR0 and TRnDTC0 registers must be set so as to satisfy TRnCCR0 + TRnDTC0 < FFFFH. Remark: (4) n = 0, 1 m = 1 to 3 Operation in PWM mode with dead time The figure shows the timing chart when TRnCCR0 = 0007H, TRnDTC0 = 0002H, TRnDTC1 = 0002H, and the TRnCCR0 register is set to 0000H to 0007H (one part). When the compare value of the TRnCCR1 register is incremented/decremented by 1 at a time, the PWM width is incremented/decremented 1 count clock at a time, but at the points indicated by arrows in the figure, incrementing/decrementing is done by TRnDTC1+1 count clock. This occurs when the TRnCCR1 register is rewritten from the setting value of the TRnDTC0 register to TRnDTC0+0001H (because dead time control is required). User's Manual U16580EE3V1UD00 453 Chapter 10 Figure 10-74: 16-bit Inverter Timer/Counter R Timer Output Example When TRnCE = 1 Is Set (Initial) (PWM mode with Dead Time) Counter FFFF 0000 000100020003000400050006 00070000000100020003 0004 Sub-counter FFFF 000800090002 00030004 000500060007000800090002 00030004 TRnCE TRnCCR0 0007H (for cycle setting) TRnDTC0 002H (for dead time setting) TRnDTC1 002H (for dead time setting) [TRnCCR1 = 0000H] TORn1 "L" TORn2 [TRnCCR1 = 0001H] TORn1 "L" "H" TORn2 [TRnCCR1 = 0002H] TORn1 "L" TORn2 [TRnCCR1 = 0003H] TORn1 TORn2 [TRnCCR1 = 0004H] TORn1 TORn2 [TRnCCR1 = 0005H] TORn1 TORn2 [TRnCCR1 = 0007H] TORn1 TORn2 "L" [TRnCCR1 = 0009H] TORn1 TORn2 "L" [TRnCCR1 = 000AH] TORn1 TORn2 "L" (5) Dead time control in PWM mode with dead time In the PWM mode with dead time, compare registers (TRnCCR1 to TRnCCR3) are used as the duty setting registers, and another compare register (TRnCCR0) is used as the cycle setting register. Through the use of these four registers, a variable duty 6-phase PWM waveform is output. To realize dead time control, three 10-bit down counters that operate in synchronization with the counter's count clock, and dead time setting registers (TRnDTC0, TRnDTC1) are provided. The TRnDTC0 register is used to set the dead time from when the inverted phase becomes inactive to when the normal phase becomes active, and the TRnDTC1 register is used to set the dead time from when the normal phase becomes inactive to when the inverted phase becomes active. The following figure shows an output example when TRnDTC0 = x, TRnDTC1 = y. 454 User's Manual U16580EE3V1UD00 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-75: Output Waveform Example in PWM Mode with Dead Time TRnCCR0 Counter TRnDTC0 = "x" TRnDTC1 = "y" TRnDTT1, 2, 3 TORn1, 3, 5 TORn2, 4, 6 x y x y User's Manual U16580EE3V1UD00 x y 455 Chapter 10 (6) 16-bit Inverter Timer/Counter R Error interrupt (INTTRnER) in PWM mode with dead time In the PWM mode with dead time, the normal phase/inverted phase simultaneous active detection function can be used. When using the PWM mode with dead time, no error interrupt (INTTRnER) is output as long as no hardware fault occurs (except when TRnDTC0, TRnDTC1 = 0000H is set). Also, when TRnDTC0, TRnDTC1 = 000H is set, glitches may occur upon error interrupt (INTTRnER) output. In this case, the occurrence of glitches during error interrupt (INTTRnER) output can be prevented by setting bit TRnEOC to 0. Figure 10-76: Error Interrupt (INTTRnER) in PWM Mode with Dead Time Counter TORn1 TORn2 INTTRnER TRnTBF "L" Glitches may occur during normal/inverted phase switching. The detection flag (TRnTBF) is not set. 456 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.1 Features Timer T (TMT) is a 16-bit timer/event counter that provides general-purpose functions. Timer T can perform the following operations. * Interval timer function * External event count function * One-shot pulse output function * External trigger pulse function * 16-bit accuracy PWM output function * Free-running function * Pulse width measurement function * 2-phase encoder function * Triangular wave PWM output function * Offset trigger generation function 11.2 Function Outline * Capture trigger input signal x 2 * Encoder input signal x 2 * Encoder clear signal x 1 * External trigger input signal x 1 * External event input x 1 * Readable counter x 1 * Count write buffer x 1 * Capture/compare reload register x 2 * Capture/compare match interrupt x 2 * Timer Output (TO) x 2 * Capture/compare match signal x 2 * Overflow interrupt x 1 * Encoder clear interrupt x 1 User's Manual U16580EE3V1UD00 457 Chapter 11 16-bit Timer/Event Counter T 11.3 Configuration Timer T is configured of the following hardware. Table 11-1: Item Timer T Configuration Configuration Counter 16-bit counter Registers TMTn capture/compare registers 0, 1 (TTnCCR0, TTnCCR1) TMTn counter read buffer register (TTnCNT) TMTn counter write buffer register (TTnTCW) TTnCCR0 buffer register, TTnCCR1 buffer register Timer input pins 7 (TITn0, TITn1, TEVTTn, TTRGTn, TENCTn0, TENCTn1, TECRTn)Note Timer output pins 2 (TOTn0, TOTn1)Note Timer input signals Timer output signals TTnEQC0, TTnEQC1 Control registers TMTn control registers 0, 1 (TTnCTL0 to TTnCTL2) TMTn I/O control registers 0 to 2 (TTnIOC0 to TTnIOC3) TMTn option registers 0, 1 (TTnOPT0 to TTnOPT2) Interrupts Compare match interrupt (INTTTnCC0, INTTTnCC1) Overflow interrupt (INTTTnOV) Encoder clear interrupt (INTTTnEC) Note: Alternate-function pins Remark: 458 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T Table 11-2: Address Register Name List of Timer T Registers Symbol R/W Manipulable Bit Units 1 8 After Reset 16 FFFFF690H TMT0 control register 0 TT0CTL0 R/W x x 00H FFFFF691H TMT0 control register 1 TT0CTL1 R/W x x 00H FFFFF692H TMT0 control register 2 TT0CTL2 R/W x x 00H FFFFF693H TMT0 I/O control register 0 TT0IOC0 R/W x x 00H FFFFF694H TMT0I/O control register 1 TT0IOC1 R/W x x 00H FFFFF695H TMT0 I/O control register 2 TT0IOC2 R/W x x 00H FFFFF696H TMT0 I/O control register 3 TT0IOC3 R/W x x 00H FFFFF697H TMT0 option register 0 TT0OPT0 R/W x x 00H FFFFF698H TMT0 option register 1 TT0OPT1 R/W x x 00H FFFFF699H TMT0 option register 2 TT0OPT2 R/W x x 00H FFFFF69AH TMT0 capture/compare register 0 TT0CCR0 R/W x 0000H FFFFF69CH TMT0 capture/compare register 1 TT0CCR1 R/W x 0000H FFFFF69EH TMT0 counter read buffer register TT0CNT R x 0000HNote FFFFF990H TMT0 counter write buffer register TT0TCW R/W x 0000H FFFFF6A0H TMT1 control register 0 TT1CTL0 R/W x x 00H FFFFF6A1H TMT1 control register 1 TT1CTL1 R/W x x 00H FFFFF6A2H TMT1 control register 2 TT1CTL2 R/W x x 00H FFFFF6A3H TMT1 I/O control register 0 TT1IOC0 R/W x x 00H FFFFF6A4H TMT1I/O control register 1 TT1IOC1 R/W x x 00H FFFFF6A5H TMT1 I/O control register 2 TT1IOC2 R/W x x 00H FFFFF6A6H TMT1 I/O control register 3 TT1IOC3 R/W x x 00H FFFFF6A7H TMT1 option register 0 TT1OPT1 R/W x x 00H FFFFF6A8H TMT1 option register 1 TT1OPT1 R/W x x 00H FFFFF6A9H TMT1 option register 2 TT1OPT2 R/W x x 00H FFFFF6AAH TMT1 capture/compare register 0 TT1CCR0 R/W x 0000H FFFFF6ACH TMT1 capture/compare register 1 TT1CCR1 R/W x 0000H FFFFF6AEH TMT1 counter read buffer register TT1CNT R x 0000HNote FFFFF9A0H TMT1 counter write buffer register TT1TCW R/W x 0000H Note: When TTnCE = 0 Remark: n = 0, 1 User's Manual U16580EE3V1UD00 459 Chapter 11 16-bit Timer/Event Counter T Figure 11-1: Block Diagram of Timer T Internal bus TTnCCR1 TTnCCR0 LOAD LOAD TO Control TOTn0 TOTn1 TTnCCR1 buffer TTnCCR0 buffer TTnEQC1/ INTTTnCC1 /2 /4 /8 /16 /32 /64 TTnEQC0/ INTTTnCC0 Clock generator INTTTnOV Counter Control /256 /1024 TENCTn0 TENCTn1 LOAD Counter COUNT UP/DOWN Clear Clear INTTTnEC Encoder clock generator LOAD TTnTCW TTRGTn TEVTTn TECRTn TITn1 TITn0 Edge detector TTnCCR1 TTnCCR0 TTnCNT Internal bus Remark: 460 n = 0, 1 m = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 (1) 16-bit Timer/Event Counter T TMTn capture/compare register 0 (TTnCCR0) The TTnCCR0 register is a 16-bit register that functions both as a capture register and as a compare register. This register can be read and written in 16-bit units only. Reset input clears this register to 0000H. Figure 11-2: After reset: 15 TMTn Capture/Compare Register 0 (TTnCCR0) 0000H 14 13 R/W 12 11 Address: 10 9 8 TT0CCR0 FFFFF69AH, TT1CCR0 FFFFF6AAH 7 6 5 4 3 2 1 0 TTnCCR0 The capture and compare functions are as follows in each mode. Table 11-3: Operation Mode Capture/Compare Functions in Each Mode Capture/Compare Setting of Rewriting Method TTnCCR0 Register during Compare Counter Clear Function Interval mode Compare only Anytime write Compare match External event count mode Compare only Anytime write Compare match External trigger pulse output mode Compare only Batch write (Reload) Compare match One-shot pulse mode Compare only Anytime write Compare match PWM mode Compare only Batch write (Reload) Compare match Free-running mode Capture/compare selectable Anytime write - Pulse width measurement mode Capture only - External input (TITn0 pin) Triangular wave PWM mode Compare only Batch write (Reload)Note 1 Compare match Encoder compare mode Compare only Anytime write Depends on set conditionNote 2 Offset trigger generation mode Capture only - External input (TITn0 pin) Notes: 1. The batch write reload timing is the counter underflow timing only. 2. The condition is set with the TTnECM0 and TTnECM1 bits of the TTnCTL2 register. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 461 Chapter 11 16-bit Timer/Event Counter T * Use as compare register When TTnCE = 1, the TTnCCR0 register rewrite method differs according to the operation mode. Refer to Table 11-3: Capture/Compare Functions in Each Mode. (For details about the compare register rewrite operation, refer to 11.5.2 Method for writing to compare register.) * Use as capture register The counter value is saved to the TTnCR0 register upon TITn0 pin input edge detection. The function to clear counters following capture differs according to the operation mode. Refer to Table 11-3: Capture/Compare Functions in Each Mode. (2) TMTn capture/compare register 1 (TTnCCR1) The TTnCCR1 register is a 16-bit register that functions both as a capture register and a compare register. This register can be read and written in 16-bit units only. Reset input clears this register to 0000H. Figure 11-3: After reset: 15 0000H 14 13 TMTn Capture/Compare Register 1 (TTnCCR1) R/W 12 11 Address: 10 9 8 TT0CCR1 FFFFF69CH, TT1CCR1 FFFFF6ACH 7 6 5 TTnCCR1 462 User's Manual U16580EE3V1UD00 4 3 2 1 0 Chapter 11 16-bit Timer/Event Counter T The capture/compare functions in each operation mode are as follows. Table 11-4: Operation Mode Capture/Compare Functions in Each Mode Capture/Compare Setting of Rewriting Method Counter Clear Function TTnCCR1 Register during Compare Interval mode Compare only Anytime write - External event count mode Compare only Anytime write - External trigger pulse output mode Compare only Batch write (Reload) - One-shot pulse mode Compare only Anytime write - PWM mode Compare only Batch write (Reload) - Free-running mode Capture/compare selectable Anytime write Pulse width measurement mode Capture only Triangular wave PWM mode Compare only Batch write (Reload)Note 1 Encoder compare mode Compare only Anytime write Offset trigger generation mode Compare only Batch write (Reload)Note 3 - External input (TITn1 pin) Depends on set conditionsNote 2 - Notes: 1. The batch write reload timing is the counter underflow occurrence timing only. 2. The conditions are set with bits TTnECM0 and TTnECM1 of TTnCTL2 register. 3. The batch write reload timing is the counter's 0000H clear timing only. Remark: n = 0, 1 * Use as compare register When TTnCE = 1, the write method of register TTnCCR1 differs according to the operation mode. Refer to Table 11-4: Capture/Compare Functions in Each Mode. (For details about the compare register rewrite operation, refer to 11.5.2 Method for writing to compare register.) * Use as capture register The counter value upon TITn1 pin input edge detection is saved to the TTnCCR1 register. The function to clear the counter following capture also differs according to the mode. Refer to Table 11-4: Capture/Compare Functions in Each Mode. User's Manual U16580EE3V1UD00 463 Chapter 11 (3) 16-bit Timer/Event Counter T TMTn counter write buffer register (TTnTCW) The TTnTCW register is a write buffer register that can write the counter value. The setting value is valid only in the encoder compare mode, encoder capture mode. In all other modes, the setting value is invalid. This register can be read and written in 16-bit units. Reset input clears this register to 0000H. Remark: When TTnECC of register TTnCTL2 = 0, the setting value is loaded to the counter when the TTnCE bit is set (to 1). (When TTnECC = 1, the counter holds its value, so it is not reloaded.) Figure 11-4: After reset: 15 0000H 14 13 TMTn Counter Write Buffer Register (TTnTCW) R/W 12 11 Address: 10 9 8 TT0TCW FFFFF990H, TT1TCW FFFFF9A0H 7 6 5 4 3 2 1 0 TTnTCW (4) TMTn counter read buffer register (TTnCNT) The TTnCNT register is a read buffer register that can read the counter value. This register can be read in 16-bit units only. Reset input clears this register to 0000H. Remark: When, in the encoder compare mode, encoder capture mode, the value of the TTnCE bit is changed from "1" to "0", the value that can be read by the TTnCNT register differs according to the following conditions. * When bit TTnECC of the TTnCTL2 register = 0, 0000H can be read. * When bit TTnECC = 1, the value held when bit TTnCE was cleared to "0" can be read. Figure 11-5: After reset: 15 0000H 14 13 TMTn Counter Read Buffer Register (TTnCNT) R/W 12 11 Address: 10 9 8 TT0CNT FFFFF69EH, TT1CNT FFFFF6AEH 7 6 5 TTnCNT 464 User's Manual U16580EE3V1UD00 4 3 2 1 0 Chapter 11 16-bit Timer/Event Counter T 11.4 Control Registers (1) TMTn control register 0 (TTnCTL0) TTnCTL0 is an 8-bit register that controls the operation of TMTn. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Reset input clears this register to 00H. When TTnCE = 1, only the TTnCE bit of the TTnCTL0 register can be changed. Perform write access to the other bits using the same values. Figure 11-6: After reset: TTnCTL0 00H TMTn Control Register 0 (TTnCTL0) (1/2) R/W Address: TT0CTL0 FFFFF690H, TT1CTL0 FFFFF6A0H 7 6 5 4 3 TTnCE 0 0 0 0 2 1 0 TTnCKS2 TTnCKS1 TTnCKS0 (n = 0, 1) TRnCE TMTn Operation Control 0 Internal operating clock operation disabled (TMTn reset asynchronously) 1 Internal operating clock operation enabled When bit TTnCE is set to "0", the internal operation clock of TMTn stops (fixed to low level), and TMTn is reset asynchronously. When bit TTnCE is set to "1", the internal operation of TMTn is enabled from when bit TTnCE was set to "1" and count-up is performed. The time until count-up is as listed in Table TMTn Count Clock and Time Until Count-Up. Remarks: 1. In the encoder compare mode, encoder capture mode, the functions that are reset when TTnCE = 0 and TTnECC = 1 are as follows. * Compare match detector (interrupt output low level) * Timer output (Output inactive level) * Edge detector for other than pins TENCTn0, TENCTn1, and TECRTn 2. The following functions are not reset. * Counter * Flags in TTnOPT1 register * TTnCCR0 buffer, TTnCCR1 buffer register, counter read buffer register * TENCTn0, TENCTn1, TECRTn pin edge detector 3. In modes other than the above, (in which TTnECC is fixed to 0), the functions that are reset by TTnCE = 0 are as follows. * Internal registers other than registers that can be written from the CPU, and internal latch circuits Remark: n = 0, 1 User's Manual U16580EE3V1UD00 465 Chapter 11 Figure 11-6: 16-bit Timer/Event Counter T TMTn Control Register 0 (TTnCTL0) (2/2) TTnCKS2 TTnCKS1 TTnCKS0 Internal Count Clock Selection 0 0 0 fXX/2 0 0 1 fXX/4 0 1 0 fXX/8 0 1 1 fXX/16 1 0 0 fXX/32 1 0 1 fXX/64 1 1 0 fXX/256 1 1 1 fXX/1024 Table 11-5: TMTn Count Clock and Count Delay Count Clocks TTnCKS2 TTnCKS1 TTnCKS0 fXX/2 0 0 0 fXX/4 0 0 1 fXX/8 0 1 0 fXX/16 0 1 1 fXX/32 1 0 0 fXX/64 1 0 1 fXX/256 1 1 0 fXX/1024 1 1 1 Count Delay Minimum Maximum 3 base clocks 4 base clocks 4 base clocks 5 base clocks + 1 count clock Remarks: 1. fXX: System clock 2. fTMTn: Base clock of TMTn (fTMTn = fXX/2) 3. n = 0, 1 466 User's Manual U16580EE3V1UD00 Chapter 11 (2) 16-bit Timer/Event Counter T TMTn control register 1 (TTnCTL1) The TTnCTL1 register is an 8-bit register that controls the operation of TMTn. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnCTL1 register when TTnCE = 0. When TTnCE = 1, the bits other than bit TTnEST (TTnEEE, TTnMD3 to TTnMD0, TTnSYE) can be write accessed using the same value. Caution: In the one-shot pulse mode and external trigger pulse output mode, write access using "1", the same value as that of bit TTnEST, functions as one trigger. Figure 11-7: After reset: TTnCTL1 00H TMTn Control Register 1 (TTnCTL1) (1/2) R/W Address: TR0CTL1 FFFFF691H, TR1CTL1 FFFFF6A1H 7 6 5 4 3 2 1 0 0 TTnEST TTnEEE 0 TTnMD3 TTnMD2 TTnMD1 TTnMD0 (n = 0, 1) TTnEST Software Trigger Control 0 No operation 1 Enable software trigger control * In one-shot pulse mode (One-shot pulse software trigger) Can be made to function as a software trigger by setting TTnETS to 1 when TTnCE = 1. Always write TTnEST = 1 when TTnCE = 1. * In external trigger pulse output mode (Pulse output software trigger) Remark: TTnEEE "0" is always read out from the TTnEST bit. Count Clock Selection 0 Use of clock selected with bits TTnCKS2 to TTnCKS0 of TTnCTL0 register 1 Use of external clock (TEVTTn pin input edge) Specification of the valid edge when TTnEEE = 1 (external clock: TEVTTn pin) is set with bits TTnEES1 and TTnEES0 of TTnIOC2 register.) Remark: The setting of bit TTnEEE is invalid in the external event count mode, encoder compare mode, encoder capture mode, encoder capture/compare mode. Caution: Rewrite the TTnEEE bit only when TTnCE = 0. (The same value can be written when TTnCE = 1.) The operation is not guaranteed if rewriting is performed when TTnCE = 1. If rewriting was mistakenly performed, set TTnCE = 0 and then set the bit again. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 467 Chapter 11 Figure 11-7: 16-bit Timer/Event Counter T TMTn Control Register 1 (TTnCTL1) (2/2) TTnMD3 TTnMD2 TTnMD1 TTnMD0 0 0 0 0 Interval mode 0 0 0 1 External event count mode 0 0 1 0 External trigger pulse output mode 0 0 1 1 One-shot pulse mode 0 1 0 0 PWM mode 0 1 0 1 Free-running mode 0 1 1 0 Pulse width measurement mode 0 1 1 1 Triangular wave PWM mode 1 0 0 0 Encoder compare mode 1 1 0 0 Offset trigger generation mode Other than above Timer Mode Setting prohibited Caution: Rewrite the TTnMD3 to TTnMD0 bits only when TTnCE = 0. (The same value can be written when TTnCE = 1.) The operation is not guaranteed if rewriting is performed when TTnCE = 1. If rewriting was mistakenly performed, set TTnCE = 0. Remark: n = 0, 1 468 User's Manual U16580EE3V1UD00 Chapter 11 (3) 16-bit Timer/Event Counter T TMTn control register 2 (TTnCTL2) The TTnCTL2 register is an 8-bit register that controls the operation of TMTn. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. The settings of the TTnCTL2 register are valid only in the encoder compare mode. The settings of this register are invalid in all other modes. Set the TTnCTL2 register when TTnCE = 0. When TTnCE = 1, write access to the TTnCTL2 register can be performed with the same value. Figure 11-8: After reset: TTnCTL2 00H TMTn Control Register 2 (TTnCTL2) (1/2) R/W Address: 7 6 5 TTnECC 0 0 TR0CTL1 FFFFF692H, TR1CTL1 FFFFF6A2H 4 3 2 1 0 TTnLDE TTnECM1 TTnECM0 TTnUDS1 TTnUDS0 (n = 0, 1) TTnECC Selection of Initialization/Hold of Counter Value when TTnCE = 0 0 Initialize counter value when TTnCE = 0 1 Hold counter value when TTnCE = 0 When TTnECC = 0, setting TTnCE = 0 causes the counter to be reset to FFFFH, the capture registers (TTnCCR0/TTnCCR1) to be reset to 0000H, and the encoder-dedicated flags (TTnEOF/TTnEUF/TTnESF) to be reset to 0. When TTnECC = 0, the value of the TTnTCW register is loaded to the counter when TTnCE is set from 0 to 1. When TTnECC = 1, setting TTnCE = 0 causes the values of the counter, capture registers (TTnCCR0/TTnCCR1), and encoder dedicated flags (TTnEOF/TTnEUF/TTnESF) to be held. When TTnECC = 1, the value of the TTnTCW register is not loaded to the counter. Remark: The setting of bit TTnECC is valid in the encoder compare mode. TTnLDE 0 Disable transfer of compare setting value to counter 1 Enable transfer of compare setting value (TTnCCR0) to counter when underflow occurs Remark: The setting of bit TTnLDE is valid in the encoder compare mode and bits TTnECM1 and TTnECM0 are set as follows. * TTnECM1 = 0, TTnECM0 = 0 or 1 TTnECM1 Encoder Clear Mode on Match of Counter and TTnCCR1 Register 0 No clear condition 1 When the counter and TTnCCR1 register match, clear the counter if the next count is a down count (TTnESF = 1) Remark: Remark: Encoder Load Enable The setting of bit TTnECM1 is valid in the encoder compare mode. n = 0, 1 User's Manual U16580EE3V1UD00 469 Chapter 11 Figure 11-8: TTnECM0 16-bit Timer/Event Counter T TMTn Control Register 2 (TTnCTL2) (2/2) Encoder Clear Mode on Match of Counter and TTnCCR0 Register 0 No clear condition 1 When the counter and TTnCCR0 register match, clear the counter if the next count is a down count (TTnESF = 0) Remark: The setting of bit TTnECM0 is valid in the encoder compare mode. TTnUDS1 TTnUDS0 Encoder Operation Mode 0 0 Upon detection of the valid edge of the A phase of encoder input (TENCTn0 pin), the following count operation is performed in the B phase of encoder input. * When "high", count down. * When "low", count up. 0 1 Count up upon detection of valid edge of A phase of encoder input (TENCTn0 pin). Count down upon detection of valid edge of B phase of encoder input (TENCTn1 pin). 1 0 Count up at rising edge of A phase of encoder input (TENCTn0 pin). Count down at falling edge of A phase of encoder input. However, count operation is performed only when B phase of encoder input (TENCTn1 pin) is "low". 1 1 Detection of both edges of phase A of encoder input (TENCTn0 pin)/phase B of encoder input (TENCTn1 pin). Judgment of count operation based on combination of detection edge and input level. Remarks: 1. When bits TTnUDS1 and TTnUDS0 are set to 10B or 11B, the settings of bits TTnEIS1 and TTnEIS0 of the TTnIOC3 register are invalid, and these bits are fixed to the setting for detection of both edges. 2. n = 0, 1 470 User's Manual U16580EE3V1UD00 Chapter 11 (4) 16-bit Timer/Event Counter T TMTn I/O control register 0 (TTnIOC0) The TTnIOC0 register is an 8-bit register that controls timer output (TOTn0 and TOTn1 pins). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnIOC0 register when TTnCE = 0. When TTnCE = 1, write access to the TTnIOC0 register can be performed using the same value. Figure 11-9: After reset: TTnIOC0 00H TMTn I/O Control Register 0 (TTnIOC0) R/W Address: TR0IOC0 FFFFF693H, TR1IOC0 FFFFF6A3H 7 6 5 4 3 2 1 0 0 0 0 0 TTnOL1 TTnOE1 TTnOL0 TTnOE0 (n = 0, 1) TTnOLm 0 Normal output (Low level, when output is inactive.) 1 Inverted output (High level, when output is inactive.) TTnOEm Remark: Timer Output Level Setting (TOTnm pin) Timer Output Control (TOTnm pin) 0 Timer output disabled (TOTnm pin output is fixed to inactive level.) 1 Timer output enabled (A pulse can be output from the TOTnm pin.) n = 0, 1 m = 0, 1 User's Manual U16580EE3V1UD00 471 Chapter 11 (5) 16-bit Timer/Event Counter T TMTn I/O control register 1 (TTnIOC1) The TTnIOC1 register is an 8-bit register that controls the valid edge of capture input (TITn1 and TITn0 pins). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnIOC1 register when TTnCE = 0. When TTnCE = 1, write access to the TTnIOC1 register can be performed using the same value. Figure 11-10: After reset: TTnIOC1 00H TMTn I/O Control Register 1 (TTnIOC1) R/W Address: TT0IOC1 FFFFF694H, TT1IOC1 FFFFF6A4H 7 6 5 4 3 2 1 0 0 0 0 0 TTnIS3 TTnIS2 TTnIS1 TTnIS0 TTnIS3 TTnIS2 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection (n = 0, 1) Capture Input (TITn1) Valid Edge Setting Capture operation is performed and capture interrupt (INTTTnCC1) is output upon edge detection. Remark: The setting of bits TTnIS3 and TTnIS2 are valid in the free-running mode and pulse width measurement mode. TTnIS1 TTnIS0 Capture Input (TITn0) Valid Edge Setting 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Capture operation is performed and capture interrupt (INTTTnCC0) is output upon edge detection. Remark: Remark: 472 The setting of bits TTnIS1 and TTnIS0 are valid in the free-running mode and pulse width measurement mode. n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 (6) 16-bit Timer/Event Counter T TMTn I/O control register 2 (TTnIOC2) The TTnIOC2 register is an 8-bit register that controls the valid edge of external event count input (TEVTTn pin) and external trigger input (TTRGTn pin). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnIOC2 register when TTnCE = 0. When TTnCE = 1, write access to the TTnIOC2 register can be performed using the same value. Figure 11-11: After reset: TTnIOC2 00H TMTn I/O Control Register 2 (TTnIOC2) R/W Address: 7 6 5 4 0 0 0 0 TT0IOC2 FFFFF695H, TT1IOC2 FFFFF6A5H 3 2 1 0 TTnEES1 TTnEES0 TTnETS1 TTnETS0 (n = 0, 1) TT1EES1 TT1EES0 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Remark: The settings of bits TTnEES1 and TTnEES0 are valid in the external event count mode, or when bit TTnEEE of the TTnCTL1 register = 1. TT1ETS1 TT1ETS0 External Trigger Input (TTRGTn) Valid Edge Setting 0 0 No edge detection (capture operation invalid) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both, rising and falling edge detection Remark: Remark: External Event Counter Input (TEVTTn) Valid Edge Setting The settings of bits TTnETS1 and TTnETS0 are valid in the external trigger pulse output mode and the one-shot pulse mode. n = 0, 1 User's Manual U16580EE3V1UD00 473 Chapter 11 (7) 16-bit Timer/Event Counter T TMTn I/O control register 3 (TTnIOC3) The TTnIOC3 register is an 8-bit register that controls the valid edge of encoder clear input (TECRTn pin) and encoder input (TENCTn1 and TENCTn0 pins). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnIOC3 register when TTnCE = 0. When TTnCE = 1, write access to the TTnIOC2 register can be performed using the same value. Figure 11-12: After reset: TTnIOC3 00H TMTn I/O Control Register 3 (TTnIOC3) (1/2) R/W Address: 7 6 5 4 TTnSCE TTnZCL TTnBCL TTnACL TT0IOC3 FFFFF696H, TT1IOC3 FFFFF6A6H 3 2 1 TTnECS1 TTnECS0 TTnEIS1 0 TTnEIS0 (n = 0, 1) TTnSCE Selects the encoder counter clear method 0 Clear upon detection of edge of TECRTn pin 1 Clear upon match of clear condition level When TTnSCE = 1, the counter is cleared to 0000H if all the conditions set with bits TTnZCL, TTnBCL, and TTnACL are matched. When TTnSCE = 1, the settings of bits TTnECS1 and TTnECS0 are invalid, so no encoder clear interrupt (INTTTnEC) is output. When TTnSCE = 0, the settings of bits TTnZCL, TTnBCL, and TTnACL are invalid. The settings of bits TTnECS1 and TTnECS0 become valid, and the encoder clear interrupt (INTTTnEC) is output. Caution: When TTnSCE = 1, be sure to set bits TTnUDS1, and TTnUDS0 of the TTnCTL2 register to 10B or 11B. TTnZCL 0 Clear condition = Low level 1 Clear condition = High level Remark: TTnBCL Sets the clear level for the B phase of encoder input (TENCTn1 pin) Clear condition = Low level 1 Clear condition = High level TTnACL The TTnBCL bit is valid when TTnSCE = 1. Sets the clear level for the A phase of encoder input (TENCTn0 pin) 0 Clear condition = Low level 1 Clear condition = High level Remark: 474 The TTnZCL bit is valid when TTnSCE = 1. 0 Remark: Remark: Sets the clear level for the Z phase of encoder input (TECRTn pin) The TTnACL bit is valid when TTnSCE = 1. n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-12: TTnECS1 TTnECS0 16-bit Timer/Event Counter T TMTn I/O Control Register 3 (TTnIOC3) (2/2) Set the valid edge of encoder clear input (TECRTn pin) 0 0 No edge detection 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both rising and falling edge detection The encoder clear interrupt (INTTTnEC) is output upon detection of the valid edge set with bits TTnECS1, TTnECS0. Caution: When TTnSCE = 1, the encoder clear interrupt (INTTTnEC) is not output. Remark: Bits TTnECS1 and TTnECS0 are valid in the encoder compare mode and when TTnSCE = 0. TTnEIS1 TTnEIS0 0 0 No edge detection 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both rising and falling edge detection Remark: Remark: Set the valid edge of the encoder input signal (TENCTn1/TENCTn0 pins) Bits TTnEIS1 and TTnEIS0 are valid when bits TTnUDS1 and TTnUDS0 of register TTnCTL2 are "00B" or "01B". n = 0, 1 User's Manual U16580EE3V1UD00 475 Chapter 11 (8) 16-bit Timer/Event Counter T TMTn option register 0 (TTnOPT0) The TTnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the bits of the TTnOPT0 register other than TTnOVF when TTnCE = 0. When TTnCE = 1, write access of bits of the TTnOPT0 register other than TTnOVF can be performed using the same value. Figure 11-13: After reset: TTnOPT0 00H TMTn Option Register 0 (TTnOPT0) R/W 7 6 0 0 Address: 5 4 TTnCCS1 TTnCCS0 TT0OPT0 FFFFF697H, TT1OPT1 FFFFF6A7H 3 2 1 0 0 0 0 TTnOVF (n = 0, 1) TTnCCS1 Specifies the operation mode of register TTnCCR1 0 Operation as compare register 1 Operation as capture register Remark: TTnCCS0 The setting of bit TTnCCS1 is valid in the free-running mode only. Specifies the operation mode of register TTnCCR0 0 Operation as compare register 1 Operation as capture register Remark: The setting of bit TTnCCS0 is valid in the free-running mode only. TTnOVF Flag that indicates TMTn overflow 0 No overflow occurrence after timer restart or flag reset 1 Overflow occurrence In the free-running mode, pulse width measurement mode, and offset trigger generation mode, if the counter value is counted up from FFFFH, overflow occurs, the TTnOVF flag is set (1), and the counter is cleared to 0000H. The counter is also cleared by writing 0. At the same time that the TTnOVF flag is set (1), an overflow interrupt (INTTTnOV) occurs. If 0 is written to the TTnOVF flag, or if TTnECC = 0 and TTnCE = 0 are set, the counter is cleared. Remark: Overflow does not occur during compare match & clear operation for counter value FFFFH and compare value FFFFH. Cautions: 1. If overflow occurs in the encoder compare mode, the encoder-dedicated overflow flag (TTnEOF) is set, and the overflow flag (TTnOVF) is not set. At this time, the overflow interrupt (INTTTnOV) is output. 2. When TTnOVF = 1, the TTnOVF flag is not cleared even if the TTnOVF flag and TTnOPT0 register are read. 3. The TTnOVF flag can be read and written, but even if 1 is written to the TTnOVF flag from the CPU, this is invalid. Remark: 476 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 (9) 16-bit Timer/Event Counter T TMTn option register 1 (TTnOPT1) The TTnOPT1 register is an 8-bit register that detects encoder-dedicated underflow, overflow, and counter up/down operation. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. The setting of the TTnOPT1 register is valid only in the encoder compare mode. In all other modes, the setting value is invalid. Figure 11-14: After reset: TTnOPT1 00H TMTn Option Register 1 (TTnOPT1) (1/2) R/W Address: TT0OPT1 FFFFF698H, TT1OPT1 FFFFF6A8H 7 6 5 4 3 2 1 0 0 0 0 0 0 TTnEUF TTnEOF TTnESF (n = 0, 1) TTnEUF Indication of Encoder Underflow 0 No underflow indicated 1 Indicates counter underflow in the encoder compare mode If the counter value is counted down from 0000H, underflow occurs, the OVF flag is set (to 1), and the counter is set to FFFFH. When the TTnEUF flag is set (to 1), an overflow interrupt (INTTTnOV) occurs at the same time. The TTnEUF flag is cleared (to 0) under the following conditions. * When 0 is written by CPU instruction * When TTnCE = 0 is set while TTnECC = 0 Cautions: 1. The TTnEUF flag is not cleared even if it is read. 2. The TTnEUF flag can be read and written, but even if 1 is written to the TTnEUF flag, this is invalid. Remark: Remark: When bit TTnECC of the TTnCTL2 register is 1, the flag status is held even if the value of bit TTnCE is changed from 1 to 0. n = 0, 1 User's Manual U16580EE3V1UD00 477 Chapter 11 Figure 11-14: 16-bit Timer/Event Counter T TMTn Option Register 1 (TTnOPT1) (2/2) TTnEOF Indication of Encoder Overflow 0 No overflow indicated 1 Indicates counter overflow in the encoder compare mode If the counter value is counted up from FFFFH, overflow occurs, the OVF flag is set (1), and the counter is cleared to 0000H. At the same time that the TTnEOF flag is set (1), an overflow interrupt (INTTTnOV) occurs. However, the TTnOVF flag is not set (to 1). The TTnEOF flag is cleared (0) under the following conditions. * When 0 is written by CPU instruction * When TTnCE = 0 is set while TTnECC = 0 Cautions: 1. The TTnEOF flag is not cleared even if it is read. 2. The TTnEOF flag can be read and written, but even if 1 is written to the TTnEOF flag from the CPU, this is invalid. Remark: When bit TTnECC of the TTnCTL2 register is 1, the flag status is held even if the value of bit TTnCE is changed from 1 to 0. TTnESF Indication of Encoder Count Direction 0 Indicates the up count operation of the counter in the encoder compare mode. 1 Indicates the down count operation of the counter in the encoder compare mode. The TTnESF flag is cleared (to 0) under the following conditions. * When TTnCE = 0 is set while TTnECC = 0 Remark: Remark: 478 When bit TTnECC of the TTnCTL2 register is 1, the flag status is held even if the value of bit TTnCE is changed from 1 to 0. n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T (10) TMTn option register 2 (TTnOPT2) The TTnOPT2 register is an 8-bit register that indicates the reload request status when performing write access to compare registers using the reload method. This register can only be read in 8-bit or 1-bit units. Reset input clears this register to 00H. The read contents of the TTnOPT2 register are valid only in the external trigger pulse mode, PWM MODE, and offset trigger generation using the reload method. In all other modes, the read contents are 0. Figure 11-15: After reset: TTnOPT2 00H TMTn Option Register 2 (TTnOPT2) R/W Address: TT0OPT2 FFFFF699H, TT1OPT2 FFFFF6A9H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TTnRSF (n = 0, 1) TTnRSF Reload Status Flag 0 No reload request, or reload completed 1 Reload request was output It indicates that the data to be transferred next is held pending in the TTnCCR0 and TTnCCR1 registers. The TTnRSF flag is set (1) by writing to the TTnCCR1 register, and it is cleared (0) upon reload completion. Caution: When TTnRSF = 1, do not perform write access to the TTnCCR0 and TTnCCR1 registers. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 479 Chapter 11 16-bit Timer/Event Counter T 11.5 Basic Operation 11.5.1 Basic counter operation This section describes the basic operation of the counter. For details, refer to chapter 11.6 in Each Mode. (1) Operation Counter start operation (a) Encoder compare mode The count operation is controlled by the phases of pins TENCTn0 and TENCTn1. When TTnCE = 0 and TTnECC = 0, the counter is initialized by the TTnTCW register and the count operation is started. (The setting value of the TTnTCW register is loaded to the counter at the timing when TTnCE changes from 0 to 1.) (b) Triangular wave PWM MODE The counter starts counting from initial value FFFFH. It counts up FFFFH, 0000H, 0001H, 0002H, 0003H... Following count up operation, the counter counts down upon a match with the TTnCCR0 register. (c) Modes other than the above The counter starts counting from initial value FFFFH. It counts up FFFFH, 0000H, 0001H, 0002H, 0003H... (2) Counter clear operation There are the following five counter clear causes. * Clear through match between counter value and compare setting value. * Capture and clear through capture input * Counter clear through encoder clear input (TECRTn pin) * Counter clear through match with clear condition level * Clear through clear signal input (TTnSYCI) for synchronization function during slave operation Remark: 480 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T Table 11-6: Counter Clear Operation Operation Mode Clear Cause TTnCCR0 TTnCCR1 Other Interval mode Compare match - - External event count mode Compare match - - External trigger pulse output mode Compare match - External trigger (TTRGTn pin) One-shot pulse mode Compare match - - PWM mode Compare match - - Free-running mode - - - Pulse width measurement mode - - External input (TITn0 and TITn1 pins) - - Triangular wave PWM mode Compare match Encoder compare mode Depends on set conditionsNote Offset trigger generation mode Depends on set conditionsNote - - Pin TECRTn, clear condition level match External input (TITn0 pin) Note: Conditions are set with bits TTnECM0 and TTnECM1 of the TTnCTL2 register. (3) Counter reset and hold operations In the encoder compare mode, counter value hold is controlled with bit TTnECC of the TTnCTL2 register. If TTnCE = 0 is set when TTnECC = 0, the counter is reset to 0000H. The setting value of the TTnTCW register is loaded to the counter when TTnCE = 1 is set next. If TTnCE = 0 is set when TTnECC = 1, the counter value is held as is. Counting resumes from the held value when TTnCE = 1 is set next. (4) Counter read operation during counter operation In TMT, the counter value can be read during count operation using the TTnCNT register. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 481 Chapter 11 (5) 16-bit Timer/Event Counter T Overflow operation Counter overflow occurs in the free-running mode, pulse width measurement mode, encoder compare mode and offset trigger generation mode. Overflow occurs when the counter value changes from FFFFH to 0000H. In the free-running mode, pulse width measurement mode, offset trigger generation mode, the overflow flag (TTnOVF) is set to 1 and an overflow interrupt (INTTTnOV) is output. At this time, the TTnEOF flag is not set. In the encoder compare mode, the encoder dedicated overflow flag (TTnEOF) is set to 1 and an overflow interrupt (INTTTnOV) occurs. At this time, the TTnOVF flag is not set. Under the following conditions, overflow does not occur. * When the counter value changes from initial setting FFFFH to 0000H immediately after counting start * When FFFFH is set to the compare register, and the counter is cleared to 0000H upon a match between the counter value and the compare setting value. * When, in the pulse width measurement mode and offset trigger generation mode, capture operation is performed for counter value FFFFH, and the counter is cleared to 0000H. (6) Underflow operation Counter underflow occurs in the triangular wave PWM Mode and encoder compare mode. Underflow occurs when the counter value changes from 0000H to FFFFH. When underflow occurs in the triangular wave PWM mode, an overflow interrupt (INTTTnOV) occurs. At this time, the TTnOVF flag is not set. In the encoder compare mode, the encoder dedicated underflow flag (TTnEUF) is set to 1, and an overflow interrupt (INTTTnOV) occurs. Underflow does not occur during count down immediately following counter start. (7) Description of interrupt signal operation In TMT, the following interrupt signals are output. Name Occurrence Cause INTTTnCC0 * Match between counter and setting value of TTnCCR0 register * Capture to TTnCCR0 register due to TITn0 pin input INTTTnCC1 * Match between counter and setting value of TTnCCR1 register * Capture to TTnCCR1 register due to TITn1 pin input INTTTnOV Overflow and underflow occurrence INTTTnECNote Counter clearing through TECRTn pin Note: In the encoder compare mode, when TTnSCE = 0, an encoder clear interrupt (INTTTnEC) is output. Remark: 482 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.5.2 Method for writing to compare register The TTnCCR0 and TTnCCR1 registers can be rewritten during timer operation (TTnCE = 1). There are two write modes (anytime write, reload), depending on the mode. (1) Anytime rewrite method When the TTnCCR0 and TTnCCR1 registers are written during timer operation, the write value is immediately transferred to the TTnCCR0 buffer register and TTnCCR1 buffer register and is used as the value to be compared with the counter. Figure 11-16: Basic Operation Flow for Anytime Rewrite START Initial settings Timer operation enable (TTnCE = 1) Values of TTnCCR0 and TTnCCR1 are transferred to buffers TTnCCR0 and TTnCCR1. TTnCCR0 rewrite Transfer to buffer TTnCCR0 TTnCCR1 rewrite Transfer to buffer TTnCCR1 * Match between TTnCCR0 value and counter * Counter clear & start INTTTnCC0 occurrence Remarks: 1. The interval mode is used as an example. 2. n = 0, 1 User's Manual U16580EE3V1UD00 483 Chapter 11 Figure 11-17: 16-bit Timer/Event Counter T Basic Anytime Rewrite Operation Timing D01 D01 D02 Counter D11 D11 D12 D12 TTnCE D01 TTnCCR0 TTnCCR0 buffer 0000H TTnCCR1 TTnCCR1 buffer D02 D01 D11 0000H D12 D11 INTTTnCC0 INTTTnCC1 Remarks: 1. D01, D02: Setting values of TTnCCR0 register (0000H to FFFFH) D11, D12: Setting values of TTnCCR1 register (0000H to FFFFH) 2. The interval mode is used as an example. 3. n = 0, 1 484 D02 User's Manual U16580EE3V1UD00 D12 Chapter 11 (2) 16-bit Timer/Event Counter T Reload method (Batch rewrite) When TTnCCR0, TTnCCR1 register write is performed during timer operation, the written value is used as the comparison value for the counter via the TTnCCR0 and TTnCCR1 buffer registers. Under the reload method, rewrite the TTnCCR0 register before the TTnCCR0 register value is matched, and next, write to the TTnCCR1 register. Then, when the TTnCCR0 register is matched or the counter is cleared to 0000H through external input, the values of the TTnCCR0 register and TTnCCR1 register are reloaded. By writing to the TTnCCR1 register, the value becomes valid at the next reload timing. Therefore, even if wishing to rewrite only the value of the TTnCCR0, rewrite the same value to the TTnCCR1 register to make the next reload valid. Figure 11-18: Basic Operation Flow for Reload (Batch Rewrite) START Initial settings Timer operation enable (TT0CE = 1) Values of TTnCCR0 and TTnCCR1 are transferred to buffers TTnCCR0 and TTnCCR1. TTnCCR0 rewrite Reload enable TTnCCR1 rewrite * Match between TTnCCR0 value and counter * Counter clear & start * Reload of value of TTnCCR0 and TTnCCR1 to TTnCCR0 and TTnCCR1 buffers Caution: INTTTnCC0 occurrence Rewrite to the TTnCCR1 register includes enabling reload. Therefore, rewrite the TTnCCR1 register after rewriting the TTnCCR0 register. Remarks: 1. The PWM mode is used as an example. 2. n = 0, 1 User's Manual U16580EE3V1UD00 485 Chapter 11 Figure 11-19: 16-bit Timer/Event Counter T Basic Reload Operation Timing D01 D02 D11 Counter D12 D03 D02 D12 D12 D12 TTnCE TTnCCR0 TTnCCR0 buffer D01 D01 0000H D03 D03 D02 Note TTnCCR1 TTnCCR1 buffer D02 D11 0000H Write same value D12 D12 D11 D12 D12 Note INTTTnCC0 INTTTnCC1 Note: Since the TTnCCR1 register is not written to, reloading is not performed even if TTnCCR0 is rewritten. Remarks: 1. D01, D02, D03: Setting values of TTnCCR0 register (0000H to FFFFH) D11, D12: Setting values of TTnCCR1 register (0000H to FFFFH) 2. The PWM mode is used as an example. 3. n = 0, 1 Table 11-7: Capture/Compare Rewrite Methods in Each Mode Operation Mode Capture/Compare Rewrite Method TTnCCR0 Interval mode TTnCCR1 Compare only (Anytime write type) External event count mode External trigger pulse output mode Compare only (Reload type) One-shot pulse mode Compare only (Anytime write type) PWM mode Compare only (Reload type) Free-running mode Capture/compare selectable (When compare is selected, anytime write type) Pulse width measurement mode Capture only Triangular wave PWM mode Compare only (Reload type) Encoder compare mode Compare only (Anytime write type) Offset trigger generation mode Capture only 486 Compare only (Reload type) User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.6 Operation in Each Mode 11.6.1 Interval timer mode In the interval timer mode, a compare match interrupt (INTTTnCC0) occurs and the counter is cleared upon a match between the setting value of the TTnCCR0 register and the counter value. The occurrence interval for this counter and TTnCCR0 register match interrupt becomes the interval time. In the interval timer mode, the counter is cleared only upon a match between the counter and the value of the TTnCCR0 register. Counter clearing using the TTnCCR1 register is not performed. However, the setting value of the TTnCCR1 is compared to the counter value transferred to the TTnCCR1 buffer register and a compare match interrupt (INTTTnCC1) is output. The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method, regardless of the value of bit TTnCE. Pins TOTn0 and TOTn1 are toggle output controlled when bits TTnOE0 and TTnOE1 are set to 1. Figure 11-20: Basic Operation Flow in Interval Timer Mode START Initial settings * Clock selection (TTnCTL0: TTnCKS2 to TTnCKS0) * Interval mode setting (TTnCTL1: TTnMD3 to TTnMD0 = 0000) * Compare register setting (TTnCCR0, TTnCCR1) Timer operation enable (TTnCE = 1) Transfer of TTnCCR0 and TTnCCR1 values to TTnCCR0 and TTnCCR1 buffers Match between counter and TTnCCR1 Note buffer value Match between counter and TTnCCR0 buffer value, counter clear & start INTTTnCC1 occurrence INTTTnCC0 occurrence Note: In the case of a match between the counter and TTnCCR1 register, the counter is not cleared. User's Manual U16580EE3V1UD00 487 Chapter 11 Figure 11-21: 16-bit Timer/Event Counter T Basic Timing in Interval Timer Mode (1/2) (a) When D1>D2>D3, only value of TTnCCR0 register is rewritten, TOTn0 and TOTn1 are not output (TTnOE0, 1 = 0, TTnOL0 = 0, TTnOL1 = 1) FFFFH D1 D1 D2 Counter D3 D3 D3 TTnCE TTnCCR0 D1 TTnCCR1 D 2 D3 INTTTnCC0 INTTTnCC1 A A B A: Interval time (D1 + 1) count clock TOTn0 Low TOTn1 High A: Interval time (D2 + 1) count clock Remarks: 1. D1, D2: Setting values of TTnCCR0 register (0000H to FFFFH) D3: Setting values of TTnCCR1 register (0000H to FFFFH) 2. Interval time = (Dm + 1) x (count clock cycle) 3. m = 1 to 3, n = 0, 1 488 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-21: 16-bit Timer/Event Counter T Basic Timing in Interval Timer Mode (2/2) (b) When D1 = D2, values of TTnCCR0 and TTnCCR1 registers not rewritten, TOTn1 output performed (TTnOE0, 1 = 1, TTnOL0 = 0, TTnOL1 = 1) FFFFH D1 = D2 D1 = D2 D1 = D2 Counter TTnCE TTnCCR0 D1 TTnCCR1 D2 INTTTnCC0 INTTTnCC1 TOTn0 TOTn1 Interval time Interval time Interval time Remarks: 1. D1: Setting value of TTnCCR0 register (0000H to FFFFH) D2: Setting value of TTnCCR1 register (0000H to FFFFH) 2. Interval time = (Dm + 1) x (count clock cycle) 3. TOTn0, TOTn1 toggle time = (Dm + 1) x (count clock cycle) 4. m = 1, 2, n = 0, 1 User's Manual U16580EE3V1UD00 489 Chapter 11 16-bit Timer/Event Counter T 11.6.2 External event count mode In the external event count mode, count up starts upon external event input (TEVTTn pin). (The external event input (TEVTTn) is used as the count clock, regardless of bit TTnEEE of the TTnCTL1 register.) In the external event count mode, the counter is cleared only upon a match between the counter and the value of the TTnCCR0 register. Counter clearing using the TTnCCR1 register does not work. However, the value of the TTnCCR1 register is transferred to the TTnCCR1 buffer register, compared to the counter value, and a compare match interrupt (INTTTnCC1) is output. The TTnCCR0 and TTnCCR1 registers can be rewritten with the anytime write method, regardless of the value of bit TTnCE. Pin TOTn1 toggles output controlled when bit TTnOE1 is set to 1. When using only one compare register channel, it is recommended to set the TTnCCR1 register to FFFFH. [External event count operation flow] <1> TTnCTL1 register bits TTnMD3 to TTnMD0 = 0001B (mode setting) Edge detection set with TTnIOC2 register bits TTnEES1 and TTnEES0 (TTnEES1, TTnEES0 = setting other than 01B) <2> TTnCTL0 register bit TTnCE = 1 (count enable) <3> TEVTTn pin input edge detection (count-up start) Cautions: 1. In external event count mode, when the content of the TTnCCR0 register is set to m, the number of TEVTTn pin input edge detection times is m+1. 2. In external event count mode, do not send the TTnCCR0 register to 0000H. 3. When the TTnCCR1 register value is set to 0000H in external event count mode the corresponding interrupt (INTTTnCC1) does not occur immediately after start, but after the first overflow of the timer (FFFFH to 0000H). 4. TOTn0 pin output cannot be used during external event count mode. Alternatively use the interval timer mode (refer to chapter 11.6.1 "Interval timer mode" on page 487) and set TTnEEE = 1 in conjunction with TOTn0 pin output. Remark: 490 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-22: 16-bit Timer/Event Counter T Basic Operation Timing in External Event Count Mode (1/4) (a) When D1>D2>D3, only value of TTnCCR0 register is rewritten, TOTn0 and TOTn1 are not output. The signal input from TEVTTn and internally synchronized is counted as the count clock (TTnOE1 = 0, TTnOL0 = 0, TTnOL1 = 1) FFFFH D1 D1 D2 Counter D3 D3 D3 TTnCE TTnCCR0 TTnCCR1 D1 D 2 D3 INTTTnCC0 INTTTnCC1 TOTn1 High TEVTTn Remarks: 1. D1, D2: Setting values of TTnCCR0 register (0000H to FFFFH) D3: Setting value of TTnCCR1 register (0000H to FFFFH) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 User's Manual U16580EE3V1UD00 491 Chapter 11 Figure 11-22: 16-bit Timer/Event Counter T Operation Timing in External Event Count Mode (2/4) (b) When D1 = D2, TTnCCR0 and TTnCCR1 register values are not rewritten, TOTn0 and TOTn1 are output (TTnOE1 = 1, TTnOL0 = 0, TTnOL1 = 1) FFFFH D1 = D2 D1 = D2 C o u n te r TTnCE TTnC CR0 D1 TTnC CR1 D2 IN T T T n C C 0 IN T T T n C C 1 TO Tn1 TEVTTn Remarks: 1. D1: Setting value of TTnCCR0 register (0000H to FFFFH) D2: Setting value of TTnCCR1 register (0000H to FFFFH) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 492 User's Manual U16580EE3V1UD00 D1 = D2 Chapter 11 Figure 11-22: 16-bit Timer/Event Counter T Operation Timing in External Event Count Mode (3/4) (c) When D1 = D2, TTnCCR0 and TTnCCR1 register values are not rewritten, TOTn0 and TOTn1 are output (TTnOE1 = 1, TTnOL0 = 0, TTnOL1 = 1) FFFFH C o u n te r 0000H TTnCE TTnC CR0 0000H TTnC CR1 0000H IN T T T n C C 0 IN T T T n C C 1 TO Tn1 Remarks: 1. D1: Setting value of TTnCCR0 register (0000H) D2: Setting value of TTnCCR1 register (0000H) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 User's Manual U16580EE3V1UD00 493 Chapter 11 Figure 11-22: 16-bit Timer/Event Counter T Basic Operation Timing in External Event Count Mode (4/4) (d) When D1 = D2, TTnCCR0, TTnCCR1 register values are not rewritten, TOTn0 and TOTn1 are output (TTnOE1 = 1, TTnOL0 = 0, TTnOL1 = 1) FFFFH C o u n te r 0001H TTnCE TTnC CR0 0001H TTnC CR1 0000H IN T T T n C C 0 IN T T T n C C 1 TO Tn1 Remarks: 1. D1: Setting value of TTnCCR0 register (0001H) D2: Setting value of TTnCCR1 register (0000H) 2. Number of event counts = (Dm + 1) (m = 1, 2) 3. n = 0, 1 494 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.6.3 External trigger pulse output mode When, in the external trigger pulse mode, the duty is set to the TTnCCR1 register, the cycle is set to the TTnCCR0 register, and TTnCE = 1 is set, external trigger input (TTRGTn pin) wait results, with the counter remaining stopped at FFFFH. Upon detection of the valid edge of external trigger input (TTRGTn pin), or when the TTnEST bit of the TTnCTL1 register is set, count up starts. An external trigger pulse is output from pin TOTn1, and toggle output is performed from pin TOTn0 upon a match with the TTnCCR0 register. Moreover, during the count operation, upon a match between the counter and the TTnCCR0 register, a compare match interrupt (INTTTnCC0) is output, and upon a match between the counter and TTnCCR1 register, a compare match interrupt (INTTTnCC1) is output. The TTnCCR0 and TTnCCR1 registers can be rewritten during count operation. Compare register reload is performed at the timing when the counter value and the TTnCCR0 register match. However, when write access to the TTnCCR1 register is performed, the next reload timing becomes valid, so that even if wishing to rewrite only the value of the TTnCCR0 register, write the same value to the TTnCCR1 register. In this case, reload is not performed even if only the TTnCCR0 register is rewritten. If, during operation in the external trigger pulse output mode, the external trigger (TTRGTn pin) edge is detected several times, or if the TTnEST bit of the TTnCTL1 register is set (to 1), the counter is cleared and count up is resumed. Moreover, if at this time, the TOTn1 pin is in the low level status, the TOTn1 pin output becomes high level when an external trigger is input. If the TOTn1 pin is in the high level status, it remains high level even if external trigger input occurs. In the external trigger pulse output mode, the TTnCCR0 and TTnCCR1 registers have their function fixed as compare registers, so the capture function cannot be used. Caution: In the external trigger pulse output mode, the external event clock input (TEVTTn) is prohibited (TTnCTL1.TTnEEE = 0). Remark: n = 0, 1 User's Manual U16580EE3V1UD00 495 Chapter 11 Figure 11-23: 16-bit Timer/Event Counter T Basic Operation Flow in External Trigger Pulse Output Mode START Initial settings * Clock selection (TTnCTL1: TTnEEE = 0) (TTnCTL0: TTnCKS2 to TTnCKS0) * External trigger pulse output mode setting (TTnCTL1: TTnMD3 to TTnMD0 = 0010) * Compare register setting (TTnCCR0, TTnCCR1) External trigger (TTRGTn pin) input Counter clear & start Timer operation enable (TTnCE = 1) Transfer of values of TTnCCR0 and TTnCCR1 to buffers TTnCCR0 and TTnCCR1 External trigger (TTRGTn pin) input Counter starts counting. Match between counter and Note TTnCCR1 ITTTnCC1 occurrence Match between counter and TTnCCR0, counter clear & start ITTTnCC0 occurrence Note: The counter is not cleared upon a match between the counter and the TTnCCR1 buffer register. Remark: 496 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-24: 16-bit Timer/Event Counter T Basic Operation Timing in External Trigger Pulse Output Mode (a) When values of TTnCCR0 and TTnCCR1 registers are rewritten, TOTn0 and TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH D01 D02 D12 Counter D11 TTnCE External trigger (TTRGTn pin) TTnCCR0 TTnCCR0 buffer D01 0000H D01 D11 TTnCCR1 TTnCCR1 D02 0000H D02 D12 D11 D12 buffer TOTn1 toggle output TOTn0 toggle output TTnRSF flag Remarks: 1. D01, D02: Setting values of TTnCCR0 register (0000H to FFFFH) D11, D12: Setting values of TTnCCR1 register (0000H to FFFFH) 2. TOTn1 (PWM) duty = (setting value of TTnCCR1 register) x (count clock cycle) TOTn1 (PWM) cycle = (setting value of TTnCCR0 register + 1) x (count clock cycle) 3. Pin TOTn0 is toggled when the counter is cleared immediately following count start. 4. n = 0, 1 User's Manual U16580EE3V1UD00 497 Chapter 11 16-bit Timer/Event Counter T 11.6.4 One-shot pulse mode When, in the one-shot pulse mode, the duty is set to the TTnCCR0 register, the output duty delay value is set to the TTnCCR1 register, and bit TTnCE of the TTnCTL0 register is set to 1, external trigger input (TTRGTn pin) wait results, with the counter remaining stopped at FFFFH. Upon detection of the valid edge of external trigger input (TTRGTn pin), or when bit TTnEST of the TTnCTL0 register is set to 1, count up starts. The TOTn1 pin becomes high level upon a match between the counter and TTnCCR1 register. Moreover, upon a match between the counter and TTnCCR0 register, the TOTn1 pin becomes low level, and the counter is cleared to 0000H and then stops. The TOTn0 pin performs toggle output during the count operation upon a match between the counter and the TTnCCR0 buffer register. Moreover, upon a match between the counter and TTnCCR0 register during count operation, a compare match interrupt (INTTTnCC0) is output, and upon a match between the counter and TTnCCR1 buffer register, a compare match interrupt (INTTTnCC1) is output. The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method, regardless of the value of bit TTnCE. Even if a trigger is input during the counter operation, it is ignored. Be sure to input the second trigger when the counter is stopped at 0000H. In the one-shot pulse mode, registers TTnCCR0 and TTnCCR1 have their function fixed as compare registers, so the capture function cannot be used. [One-shot pulse operation flow] <1> TTnCTL1 register bits TTnMD3 to TTnMD0 = 0011B (One-shot pulse mode) <2> TTnCCR0 register setting (duty setting), TTnIOC0 register bit TTnOE1 = 1 (TOTn1 pin output enable) <3> TTnCTL0 register bit TTnCE = 1 (counter operation enable): TOTn1 = Low-level output <4> TTnCTL1 register bit TTnEST = 1 or TTRGTn pin edge detection (count-up start): TOTn1 = Low-level output <5> Match between counter value and TTnCCR1 buffer register: TOTn1 = High-level output <6> Match between counter value and TTnCCR0 buffer register: TOTn1 = Low-level output, count clear <7> Count stop: TOTn1 = Low-level output <8> TTnCE = 0 (operation reset) <1> to <2> can be in any order. Caution: 498 In the one-shot pulse mode, the external event clock input (TEVTTn) is prohibited (TTnCTL1.TTnEEE = 0). User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-25: 16-bit Timer/Event Counter T Basic Operation Flow in One-Shot Pulse Mode START Initial settings * Clock selection (TTnCTL1: TTnEEE = 0) (TTnCTL0: TTnCKS2 to TTnCKS0) * One-shot pulse mode setting (TTnCTL1: TTnMD2 to TTnMD0 = 011) * Compare register setting (TTnCCR0, TTnCCR1) Timer operation enable (TTnCE = 1) Transfer of values of TTnCCR0 and TTnCCR1 to buffers TTnCCR0 and TTnCCR1 Trigger wait status, counter in standby at FFFFH External trigger (TTRGTn pin) input, or TTnEST = 1 Counter starts counting. Trigger wait status, counter in standby at 0000H Match between counter and buffer TTnCCR1 Note Match between counter and buffer TTnCCR0, counter clear INTTTnCC1 occurrence INTTTnCC0 occurrence Note: The counter is not cleared upon a match between the counter and the TTnCCR1 buffer register. Caution: The counter is not cleared even if trigger input is realized while the counter counts up, and the trigger input is ignored. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 499 Chapter 11 Figure 11-26: 16-bit Timer/Event Counter T Basic Operation Timing in One-Shot Pulse Mode (a) (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH D0 Note Counter D1 D0 D1 D0 D1 TTnCE TTnEST External trigger (TTRGTn pin) TTnCCR0 TTnCCR0 buffer D0 0000H TTnCCR1 TTnCCR1 buffer D0 D1 0000H D1 INTTTnCC0 INTTTnCC1 TOTn1 one-shot pulse output TOTn0 Note: Count up starts when the value of TTnEST becomes 1 or TTRGTn is input. Remarks: 1. D0: Setting value of TTnCCR0 register (0000H to FFFFH) D1: Setting value of TTnCCR1 register (0000H to FFFFH) 2. TOTn1 (output delay) = (setting value of TTnCCR1 register) x (count clock cycle) TOTn1 (output pulse width) = {(setting value of TTnCCR0 register +1) (setting value of TTnCCR1 register)} x (count clock cycle) 3. n = 0, 1 500 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.6.5 PWM mode When, in the PWM mode, the duty is set to the TTnCCR1 register, the cycle is set to the TTnCCR0 register, and TTnCE = 1 is set, variable duty PWM output is performed from pin TOTn1. Simultaneously with the start of count up operation, pin TOTn1 becomes high level, and upon a match between the counter and the TTnCCR1 register, becomes low level. Next, the TOTn1 pin becomes high level upon a match with the TTnCCR0 register. The TOTn0 pin performs toggle output upon a match with the TTnCCR0 buffer register. During count operation, a compare match interrupt (INTTTnCC0) is output upon a match between the counter and TTnCCR0 register, and a compare match interrupt (INTTTnCC1) is output upon a match between the counter and TTnCCR1 register. The TTnCCR0 and TTnCCR1 registers can be rewritten during count operation. Compare register reload occurs upon a match between the counter value and the TTnCCR0 buffer register. However, since the next reload timing becomes valid when the TTnCCR1 register is written to, write the same value to the TTnCCR1 register even when wishing to rewrite only the value of the TTnCCR0 register. Reloading is not performed if only the TTnCCR0 register is rewritten. In the PWM mode, the TTnCCR0 and TTnCCR1 registers have their function fixed as compare registers, so the capture function cannot be used. Figure 11-27: Basic Operation Mode in PWM Mode (1/2) (a) When values of TTnCCR0 and TTnCCR1 registers are rewritten during timer operation START Initial settings * Clock selection (TTnCTL0: TTnCKS2 to TTnCKS0) * PWM mode setting (TTnCTL1: TTnMD3 to TTnMD0 = 0100) * Compare register setting (TTnCCR0, TTnCCR1) Timer operation enable Transfer of value of TTnCCRm to TTnCCRm buffer Remark: TOTn1 outputs low level upon a match between counter and TTnCCR1 buffer. INTTTnCC1 occurrence Upon a match between counter and TTnCCR0 buffer, counter clear & start, and TOTn1 outputs high level. INTTTnCC0 occurrence n = 0, 1 m = 0, 1 User's Manual U16580EE3V1UD00 501 Chapter 11 Figure 11-27: 16-bit Timer/Event Counter T Basic Operation Flow in PWM Mode (2/2) (b) When values of TTnCCR0 and TTnCCR1 registers are rewritten during timer operation START Initial settings * Clock selection (TTnCTl0: TTnCKS2 to TTnCKS0) * PWM mode setting (TTnCTl1: TTnMD3 to TTnMD0 = 0100) * Compare register setting (TTnCCR0, TTnCCR1) Timer operation enable (TTnCE = 1) Transfer of value of TTnCCRm to TTnCCRm buffer INTTTnCC1 occurrence Upon a match between counter and TTnCCR1, TOTn1 outputs low level Upon a match between counter and TTnCCR0, counter clear & start, and TOTn1 outputs high level. * * * INTTTnCC0 occurrence TTnCCR0 rewrite <1> Upon a match between counter and TTnCCR1 buffer, TOTn1 outputs low level. <2> TTnCCR1 rewrite <3> INTTTnCC1 occurrence Note Match between TTnCCR0 buffer and counter Counter clear & start Value of TTnCCRm is reloaded to CCRm buffer. Reload enable INTTTnCC0 occurrence Note: Regarding the sequence, the timing of <2> may differ depending on the <1> or <3> rewrite timing, the value of the TTnCCR1 register, etc., but of <1> and <3>, always make <3> the last. Remark: 502 n = 0, 1 m = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-28: 16-bit Timer/Event Counter T Basic Operation Timing in PWM Mode (1/2) (a) When only value of TTnCCR1 is rewritten, and TOTn0 and TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH D00 D00 D00 D00 D11 D10 D10 Counter D12 TTnCE TTnCCR0 TTnCCR0 buffer D00 0000H TTnCCR1 TTnCCR1 buffer D00 D10 0000H D11 D10 D12 D11 D13 D12 D13 TOTn1 TOTn0 TTnRSF flag Remarks: 1. D00: Setting value of TTnCCR0 register (0000H to FFFFH) D10, D11, D12, D13: Setting values of TTnCCR1 register (0000H to FFFFH) 2. TOTn1 (PWM) duty = (setting value of TTnCCR1 register) x (count clock cycle) TOTn1 (PWM) cycle = (setting value of TTnCCR0 register + 1) x (count clock cycle) 3. TOTn0 is toggled immediately following counter start and at (setting value of TTnCCR0 register + 1) x (count clock cycle) 4. n = 0, 1 User's Manual U16580EE3V1UD00 503 Chapter 11 Figure 11-28: 16-bit Timer/Event Counter T Basic Operation Timing in PWM Mode (2/2) (b) When values of TTnCCR0 and TTnCCR1 register are rewritten, TOTn0 and TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH D00 D01 D01 D11 D11 Counter D02 D12 D10 TTnCE TTnCCR0 D00 D01 D02 D03 Note TTnCCR0 buffer 0000H D00 D01 D02 D03 Write same va TTnCCR1 D10 D11 D12 D12 Note TTnCCR1 buffer 0000H D10 D11 D12 D12 TOTn1 TOTn0 TTnRSF flag Note: The TTnCCR1 register was not written to, so transfer to the TTnCCR0 buffer register was not performed. Held until the next reload timing. Remarks: 1. D00, D01, D02, D03: Setting values of TTnCCR0 register (0000H to FFFFH) D10, D11, D12, D13: Setting values of TTnCCR1 register (0000H to FFFFH) 2. The TOTn0 and TOTn1 pins become high level at timer count start. 3. n = 0, 1 504 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.6.6 Free-running mode The operation timing of the free-running mode is shown below. The operation for bits TTnCCS1 and TTnCCS0 of register TTnOPT0 is specified. Figure 11-29: Basic Operation Flow in Free-Running Mode START Initial settings * Clock selection (TTnCTL0: TTnCKS2 to TTnCKS0) * Free-running mode setting (TTnCTL1: TTnMD3 to TTnMD0 = 0101) TTnCCS1, TTnCCS0 settings TTnCCS1 = 0 TTnCCS0 = 0 Timer operation enable (TTnCE = 1) Transfer of values of TTnCCR0 and TTnCCR1 to TTnCCR0 and TTnCCR1 buffers TTnCCS1 = 0 TTnCCS0 = 0 TITn0 edge detection settings (TTnIS1, TTnIS0) Timer operation enable (TTnCE = 1) Transfer of value of TTnCCR1 to TTnCCR1 buffer Match between TTnCCR1 buffer and counter Match between TTnCCR0 buffer and counter TTnCCS1 = 1 TTnCCS0 = 1 TITn1 edge detection settings (TTnIS3, TTnIS2) Timer operation enable (TTnCE = 1) TTnCCS1 = 1 TTnCCS0 = 1 TITn1 and TITn0 edge detection settings (TTnIS3, TTnIS2) Timer operation enable (TTnCE = 1) Transfer of value of TTnCCR0 to TTnCCR0 buffer Match between TTnCCR1 buffer and counter TITn1 edge detection, capture of counter value to TTnCCR1 TITn0 edge detection, capture of counter value to TTnCCR0 Match between TTnCCR1 buffer and counter TITn1 edge detection, capture of counter value to TTnCCR1 TITn0 edge detection, capture of counter value to TTnCCR0 Counter overflow Counter overflow Counter overflow Remark: Counter overflow n = 0, 1 User's Manual U16580EE3V1UD00 505 Chapter 11 (1) 16-bit Timer/Event Counter T Compare function (TTnCCS1 = 0, TTnCCS0 = 0) When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTTnOV) is output when the counter value changes from FFFFH to 0000H, and the counter is cleared. The count operation is performed in the free-running mode until TTnCE = 0 is set. Moreover, during count operation, a compare match interrupt (INTTTnCC0) is output upon a match between the counter and TTnCCR0 buffer register, and a compare match interrupt (INTTTnCC1) is output upon a match between the counter and TTnCCR1 buffer register. The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method, regardless of the value of the TTnCE bit. The TOTn0 and TOTn1 pins are toggle output controlled when bits register TTnOE0 and TTnOE1 of the TTnIOC0 register are set to 1. 506 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-30: 16-bit Timer/Event Counter T Basic Operation Timing in Free-Running Mode (Compare Function) (a) When values of TTnCCR0 and TTnCCR1 registers are rewritten, TOTn0, TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH D01 D11 D11 D00 Counter D00 D10 TTnCE D00 TTnCCR0 TTnCCR0 buffer 0000H D01 D00 D01 INTTTnCC0 TTnCCR1 TTnCCR1 buffer D10 0000H D10 D11 D11 INTTTnCC1 TOTn0 TOTn1 INTTTnOV TTnOVF TTnOVF 0 write clear TTnOVF 0 write clear Remarks: 1. D00, D01: Setting values of TTnCCR0 register (0000H to FFFFH) D10, D11: Setting values of TTnCCR1 register (0000H to FFFFH) 2. TOTn0 (toggle) width = (setting value of TTnCCR0 register + 1) x (count clock cycle) 3. TOTn1 (toggle) width = (setting value of TTnCCR1 register + 1) x (count clock cycle) 4. Pins TOTn0 and TOTn1 become high level at count start. 5. n = 0, 1 User's Manual U16580EE3V1UD00 507 Chapter 11 (2) 16-bit Timer/Event Counter T Capture function (TTnCCS1 = 1, TTnCCS0 = 1) When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTTnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared. The count operation is performed in the free-running mode until TTnCE = 0 is set. When, during count operation, the counter value is captured to the TTnCCR0 and TTnCCR1 registers through detection of the valid edge of capture input (TITn1, TITn0), a capture interrupt (INTTTnCC0, INTTTnCC1) is output. Regarding capture in the vicinity of overflow (FFFFH), judgment is possible with the overflow flag (TTnOVF). However, judgment with the TTnOVF flag is not possible when the capture trigger interval is such that it includes two overflow occurrences (2 or more free-running cycles). Cautions: 1. In free-running mode the external event clock input (TEVTTn) is prohibited (TTnCTL1.TTnEEE = 0). 2. When an internal count clock fXX/16 (TTnCTL0.TTnCKS2-0) is selected in freerunning mode, the TTnCCR0 and TTnCCR1 registers are used as capture registers, the a value of FFFFH will be captured if a valid signal edge is input before the first count up. Figure 11-31: Basic Operation Timing in Free-Running Mode (Capture Function) (a) When TOTn0, TOTn1 are not output (TTnOE0, 1 = 0, TTnOL0, 1 = 0) FFFFH D10 D02 D00 D12 D01 Counter D11 D03 TTnCE TITn0 TTnCCR0 0000H D00 D01 D02 D03 TITn1 TTnCCR1 0000H D10 D11 D12 Remarks: 1. D00, D01: Values captured to TTnCCR0 register (0000H to FFFFH) D10, D11: Values captured to TTnCCR1 register (0000H to FFFFH) 2. TITn0: Setting to rising edge detection (TTnIOC1 register bits TTnIS1, TTnIS0 = 01) TITn1: Setting to falling edge detection (TTnIOC1 register bits TTnIS3, TTnIS2 = 10) 3. n = 0, 1 508 User's Manual U16580EE3V1UD00 Chapter 11 (3) 16-bit Timer/Event Counter T Compare/capture function (TTnCCS1 = 0, TTnCCS0 = 1) When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH, an overflow interrupt (INTTTnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared. The count operation is performed in the free-running mode until TTnCE = 0 is set. The TTnCCR1 register is used as a compare register, and as the interval function upon a match between the counter and TTnCCR1 register, a compare match interrupt (INTTTnCC1) is output. Since the TTnCCR0 register is set to the capture function, the TOTn0 pin cannot be controlled even when TTnIOC0 register bit TTnOE0 is set to 1. Cautions: 1. In free-running mode the external event clock input (TEVTTn) is prohibited (TTnCTL1.TTnEEE = 0). 2. When an internal count clock fXX/16 (TTnCTL0.TTnCKS2-0) is selected in freerunning mode, and TTnCCR0 register is used as capture register, the a value of FFFFH will be captured if a valid signal edge is input before the first count up. Figure 11-32: Basic Operation Timing in Free-Running Mode (Compare/Capture Function) (a) When value of TTnCCR1 is rewritten, TOTn0, TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH D02 D00 D03 D10 D12 Counter D01 D11 D11 TTnCE TITn0 0000H TTnCCR0 D01 D00 D02 D03 INTTTnCC0 capture interrupt D10 TTnCCR1 TTnCCR1 buffer 0000H D10 D11 D11 D12 D12 INTTTnCC1 Match interrupt INTTTnOV overflow interrupt TOTn0 Low TOTn1 Remarks: 1. D00, D01: Setting values of TTnCCR1 register (0000H to FFFFH) D10, D11, D12, D13, D14, D15: Values captured to TTnCCR0 register (0000H to FFFFH) 2. TITn0: Setting to rising edge detection (TTnIOC1 register bits TtnIS1, TtnIS0 = 11) 3. n = 0, 1 User's Manual U16580EE3V1UD00 509 Chapter 11 (4) 16-bit Timer/Event Counter T Overflow flag When, in the free-running mode, the counter overflows from FFFFH to 0000H, the overflow flag (TTnOVF) is set to "1", and an overflow interrupt (INTTTnOV) is output. The overflow flag is cleared through 0 write from the CPU. (The overflow flag is not cleared by just being read.) 510 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T 11.6.7 Pulse width measurement mode In the pulse width measurement mode, counting is performed in the free-running mode. The counter value is saved to the TTnCCR0 register, and the counter is cleared to 0000H. As a result, the external input pulse width can be measured. However, when measuring a long pulse width that exceeds counter overflow, perform judgment with the overflow flag. Measurement of pulses during which overflow occurs twice or more is not possible, so adjust the counter's operating frequency. Even in the case of TITn1 pin edge detection, pulse width measurement can be similarly performed by using the TTnCCR1 register. Cautions: 1. In the pulse width measurement mode the external event clock input (TEVTTn) is prohibited (TTnCTL1.TTnEEE = 0). 2. When an internal count clock fXX/16 (TTnCTL0.TTnCKS2-0) is selected in pulse width measurement mode, and a valid signal edge is input before the first count up, the a value of FFFFH will be captured in the corresponding TTnCCR0 or TTnCCR1 register. Figure 11-33: Basic Operation Timing in Pulse Width Measurement Mode (a) (TTnOE0, 1 = 0, TTnOL0, 1 = 0) FFFFH FFFFH D01 Counter D03 D02 D00 TTnCE TITn0 TTnCCR0 0000H D00 D01 D02 D03 INTTTnCC0 TTnOVF Cleared through 0 write from CPU INTTTnOV Remarks: 1. D00, D01, D02, D03: Values captured to TTnCCR0 register (0000H to FFFFH) 2. TITn0: Setting to rising edge/falling edge (both edges) detection (TTnIOC1 register bits TTnIS1, TTnIS0 = 1B) 3. n = 0, 1 User's Manual U16580EE3V1UD00 511 Chapter 11 16-bit Timer/Event Counter T 11.6.8 Triangular wave PWM mode In the triangular wave PWM mode, similarly to in the PWM mode, when the duty is set to the TTnCCR1 register, the cycle is set to the TTnCCR0 register, and TTnCE = 1 is set, variable duty and cycle type triangular wave PWM output is performed from pin TOTn1. The TOTn0 pin is toggle output upon a match with the TTnCCR0 buffer register and upon counter underflow. Upon a match between the counter and TTnCCR0 register during count operation, a compare match interrupt (INTTTnCC0) is output, and upon a match between the counter and TTnCCR1 register, a compare match interrupt (INTTTnCC1) is output. Moreover, upon counter underflow, an overflow interrupt (INTTTnOV) is output. The TTnCCR0 and TTnCCR1 registers can be rewritten during count operation. Compare register reload occurs upon a match between the counter value and the TTnCCR0 buffer register. However, since the next reload timing becomes valid when the TTnCCR1 register is written to, write the same value to the TTnCCR1 register even when wishing to rewrite only the value of the TTnCCR0 register. Reloading is not performed if only the TTnCCR0 register is rewritten. The reload timing is the underflow timing. In the triangular wave PWM mode, the TTnCCR0 and TTnCCR1 registers have their function fixed as compare registers, so the capture function cannot be used. Remark: 512 In the triangular wave PWM mode, set the TTnCCR0 register to a value of 0 TTnCCR0 FFFEH. User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-34: 16-bit Timer/Event Counter T Basic Operation Timing in Triangular Wave PWM Mode (a) When TOTn0, TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH FFFFH D00 D00 D00 Counter D10 D10 D10 TTnCE TTnCCR0 TTnCCR1 0000H D00 0000H D10 INTTTnCC0 INTTTnCC1 INTTTnOV TOTn0 TOTn1 Remark: n = 0, 1 User's Manual U16580EE3V1UD00 513 Chapter 11 16-bit Timer/Event Counter T 11.6.9 Encoder count function The encoder compare mode is provided as follows. Mode Encoder compare mode (1) TTnCCR0 register TTnCCR1 register Compare only Compare only Counter up/down control Counter up/down control is performed and the counter is operated according to the phase of signals TENCTn0 and TENCTn1 from the encoder and the set conditions of bits TTnUDS1 and TTnUDS0 of the TTnCTL2 register. (2) Basic operation To use the TTnCCR0 and TTnCCR1 registers are compare-only registers, enable rewrite during timer operation. The rewrite method is anytime write. A compare match interrupt (INTTTnCC0) is output upon a match between the counter and TTnCCR0 register. A compare match interrupt (INTTTnCC1) is output upon a match between the counter and TTnCCR1 register. (3) Counter clear operation Clearing of the counter to 0000H is performed under the following conditions. Clear Condition 514 Method whereby counter is cleared to 0000H upon match with compare register (setting of TTnCTL2 register bits TTnECM1, TTnECM0) Method whereby counter is cleared to 0000H upon detection of edge of pin TECRT0 (setting of bits TTnECS1, TTnECS0 when TTnIOC3 register bit TTnSCE = 0) Method whereby counter is cleared to 0000H by special clear function of encoder (setting of bits TTnZCL, TTnBCL, TTnACL when TTnIOC3 register bit TTnSCE = 1) User's Manual U16580EE3V1UD00 Chapter 11 (4) 16-bit Timer/Event Counter T Control through TTnCTL2 register The settings of the TTnCTL2 register in the encoder compare mode (TTnMD3 to TTnMD0 = 1000B) are as follows. TTnMD3 to 0 TTnUDS1 to 0 TTnECM1 TTnECM0 TTnLDE Clear Load 1000B All settings possible 00B 01B 10B 11B 0 0 0 - 1 1 0 TTnCCR0 * 1 1 - 0 Invalid TTnCCR1 - 1 Invalid TTnCCR0 TTnCCR1 - * In the case of bits TTnUDS1 and TTnUDS0, up/down judgment control is performed for the phase input from pins TENCTn0 and TENCTn1. * In the case of bits TTnECM1 and TTnECM0, counter clear control is performed upon a match between the counter value and the compare setting value. Bits TTnECM1 and TTnECM0 are valid in modes where the TTnCCR0 or TTnCCR1 register is used as a compare-only register. These bits are invalid in modes where the TTnCCR0 or TTnCCR1 register is used as a capture-only register. * The TTnLDE bit controls the function to load to the counter the setting value of the TTnCCR0 register upon occurrence of counter underflow. Bit TTnLDE is valid only when the TTnECm bit setting is 00B, 01B, in a mode where the TTnCCR0 or TTnCCR1 register is used as a compare-only register. In the case of all other settings, bit TTnLDE is invalid even if manipulated. As an example of the use of the encoder count function, counter operation becomes possible between the setting values of registers 0000H to TTnCCR0 by using the counter load functions (TTnLDE = 1) indicated with "*" in the table, and the function for clearing the counter to 0000H in case the count operation following a match with the TTnCCR0 buffer register is up count (TTnECM0 = 1). (Refer to 11.6.9 (4) (c) Counter load function for TTnCCR0 register setting value upon underflow (bit TTnLDE of register TTnCTL2))). User's Manual U16580EE3V1UD00 515 Chapter 11 16-bit Timer/Event Counter T (a) Up/down count selection specification (TTnCTL2 register bits TTnUDS1, TTnUDS0) Counter up/down is judged according to the settings of bits TTnUDS1 and TTnUDS0, and the phases input from pins TENCTn0 and TENCTn1. Bits TTnUDS1 and TTnUDS0 are valid only in the encoder compare mode. <1> TTnCTL2: TTnUDS1, 0 = 00B (count judgment mode 1) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Rising edge High level Down Low level Up Falling edge Both edges Rising edge Falling edge Both edges Operation example: TTnIOC3: TTnEIS3 to 2 TTnIOC3: TTnEIS1 to 0 = 10B Figure 11-35: TENCTn1 pin input TENCTn0 pin input Edge detection specification invalid Rising edge detection Encoder Count Function Up/Down Count Selection Specification Timings (1/6) (a) Timing 1 TENCTn0 TENCTn1 Counter 0007 0006 0005 0004 Down count 0005 0006 0007 Up count Remarks: 1. Counting is performed when the edges of the TENCTn0/TENCTn1 pin inputs overlap. 2. n = 0, 1 516 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T <2> TTnCTL2: TTnUDS1, 0 = 01B (count judgment mode 2) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Low level Rising edge Down Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge Low level Up Falling edge Both edges Rising edge High level Falling edge Both edges Simultaneous pin TENCTn0/TENCTn1 inputs Hold Operation example: TTnIOC3: TTnEIS3, 2 = 10B TTnIOC3: TTnEIS1, 0 = 10B Figure 11-35: TENCTn1 pin input TENCTn0 pin input Rising edge detection Rising edge detection Encoder Count Function Up/Down Count Selection Specification Timings (2/6) (b) Timing 2 TENCTn0 TENCTn1 Counter 0006 0007 Up count 0008 0007 Hold 0006 0005 Down count Remarks: 1. The count value is held when the edges of the TENCTn0/TENCTn1 pin inputs overlap. 2. n = 0, 1 User's Manual U16580EE3V1UD00 517 Chapter 11 16-bit Timer/Event Counter T <3> TTnCTL2: TTnUDS1, 0 = 10B (count judgment mode 3) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Low level Falling edge Hold Rising edge Low level Down High level Rising edge Hold Falling edge High level Rising edge High level High level Falling edge Falling edge Low level Up Low level Rising edge Hold Rising edge Rising edge Hold Falling edge Rising edge Rising edge Falling edge Down Falling edge Falling edge Up Operation example: TTnIOC3: TTnEIS3 to 0 (Pins TENCTn1, TENCTn0) Edge detection specification invalid Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (3/6) (c) Timing 3 TENCTn0 TENCTn1 Counter 0007 Down count Remark: 518 0006 0005 0006 0005 0006 0005 Up Down Up Down n = 0, 1 User's Manual U16580EE3V1UD00 0006 Up count 0007 Chapter 11 16-bit Timer/Event Counter T <4> TTnCTL2: TTnUDS1, 0 = 11B (count judgment mode 4) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Low level Falling edge Down Rising edge Low level High level Rising edge Falling edge High level Rising edge High level High level Falling edge Falling edge Low level Low level Rising edge Up Simultaneous pin TENCTn0/TENCTn1 inputs Hold Operation example 1: TTnIOC2: TTnEIS3 to 0 (pins TENCTn1, TENCTn0) edge detection specification invalid Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (4/6) (d) Timing 4 TENCTn0 TENCTn1 Counter 03 04 05 06 07 08 09 0A Up count Remark: 09 08 07 06 05 Down count n = 0, 1 User's Manual U16580EE3V1UD00 519 Chapter 11 16-bit Timer/Event Counter T Operation example 2: TTnIOC2: TTnEIS3 to 0 (pins TENCTn1, TENCTn0) edge detection specification invalid. Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (5/6) (e) Timing 5 TENCTn0 TENCTn1 Counter 03 05 04 Up count 06 Hold 07 08 Up count 07 06 05 Down count 06 Up count Remarks: 1. The count value is held when the edges of the TENCTn0/TENCTn1 pin inputs overlap. 2. n = 0, 1 520 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T (b) Counter clear condition setting upon match between counter value and compare setting value (TTnCTL2 register bits TTnECM1, TTnECM0) Counter operation is performed according to the setting values of these bits upon a match between the counter value and the compare setting value. <1> TTnECM1, 0 = 00B Counter clear is not performed upon a match between the counter and compare values. <2> TTnECM1, 0 = 01B Counter clear is performed upon a match between the counter and the TTnCCR0 register. Next count Operation Description Up count Clear counter to 0000H. Down count Down count the counter value. <3> TTnECM1, 0 = 10B Operation is performed under the following conditions upon a match between the counter and TTnCCR1 register. Next Count Operation Description Up count Up count the counter value. Down count Clear counter to 0000H. <4> TTnECM1, 0 = 11B * Operation is performed under the following conditions upon a match between the counter and TTnCCR0 register. Next count Operation Description Up count Clear counter to 0000H. Down count Down count the counter value. * Operation is performed under the following conditions upon a match between the counter and TTnCCR1 register. Next count Operation Description Up count Up count the counter value. Down count Clear counter to 0000H. Caution: In encoder compare mode (TTnMD3 to TTnMD0 bits = 1000B), if the compare registers (TTnCCR0, TTnCCR1) are set to the same value of TTnTCW register when TTnECC bit = 0, the timer cannot perform the comparison with the compare registers (TTnCCR0, TTnCCR1) and TTnTCW register (which is the start value of TTnCNT). In this case the "encoder clear mode on match of counter and compare register" does not work at the start timing (TTnECM0 = 1, and/or TTnECM1 = 1). User's Manual U16580EE3V1UD00 521 Chapter 11 16-bit Timer/Event Counter T (c) Counter load function for TTnCCR0 register setting value upon underflow (bit TTnLDE of register TTnCTL2)) The setting value of the TTnCCR0 register can be loaded to the counter upon counter underflow, by setting TTnLDE = 1. Bit TTnLDE is only valid in the encoder compare mode. Count operation between 0000H and setting value of TTnCCR0 register setting Set TTnLDE = 1, TTnECM1, 0 = 01B and perform count operation. When TTnECM0 = 1, the counter is cleared to 0000H if the next count following a match between the counter and TTnCCR0 register is up count. When TTnLDE = 1, the setting value of the TTnCCR0 register is loaded to the counter upon underflow. Therefore, the setting value of the TTnCCR0 register is used as the maximum count value and count operation can be realized within 0000H-TTnCCR0 register setting values. Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (6/6) (f) Timing 6 Match between counter value and TTnCCR0 setting value Counter underflow TTnCCR0 Counter 0000H Counter cleared to 0000H Remark: 522 TTnCCR0 setting value loaded to counter n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 (5) 16-bit Timer/Event Counter T Counter clearing to 0000H through encoder clear input (pin TECRTn) (TTnIOC3 register bits TTnSCE, TTnECS1, TTnECS0) There are two methods to clear the counter to 0000H through TECRTn pin input, and encoder clear input is controlled by bit TTnSCE. Bits TTnZCL, TTnBCL, TTnACL, TTnECS1, and TTnECS0 are controlled by the setting of bit TTnSCE. These clear methods are valid in the encoder compare mode. TTnSCE TTnZCL TTnBCL TTnACL TTnECS1, 0 Method 0 Invalid Invalid Invalid <1> 1 Invalid <2> <1> Method to clear counter to 0000H through detection of valid edge of TECRTn pin input (TTnSCE = 0) When TTnSCE = 0, the counter is cleared to 0000H in synchronization with the internal operation clock upon detection of the valid edge set through TECRTn pin input edge detection specification. At this time, an encoder clear interrupt (INTTTnEC) is output. When TTnSCE = 0, the setting of bits TTnZCL, TTnBCL, and TTnACL are invalid. Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (1/4) (a) When TTnSCE = 0, TTnECS1, 0 = 01B, TTnUDS = 11B are Set Base clock TENCTn0 TENCTn1 TECRTn Count signal m Counter m +1 0 1 2 INTTTnEC Counter clear Remark: n = 0, 1 User's Manual U16580EE3V1UD00 523 Chapter 11 16-bit Timer/Event Counter T <2> Method to clear counter to 0000H through detection of level clear condition (TTnSCE = 1) When TTnSCE = 1, the counter is cleared to 0000H according to the clear condition level of pins TECRTn, TENCTn1, and TENCTn0 set with bits TTnZCL, TTnBCL, and TTnACL. At this time, no encoder clear interrupt (INTTTnEC) is output. When TTnSCE = 1, the settings of bits TTnECS1 and TTnECS0 are invalid. Operation example: When TTnSCE = 1, TTnCLA = 1, TTnCLB = 0, TTnCLZ = 1, TTnUDS = 11B are set <Clear condition level> TECRTn pin: High level, TENCTn1 pin: Low level, TENCTn0 pin: High level Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (2/4) (b) when TECRTn Pin Input Is Delayed from TENCTn1 Pin Input during Up Count Signal after edge detection TENCTn0 H TENCTn1 L TECRTn H Base clock Counter m+1 m 0 Count clock When "m+1" set to TTnCCR0 m+1 TTnCCR0 Compare match interrupt not output INTTTnCC0 When "0000H" set to TTnCCR1 TTnCCR1 0 INTTTnCC1 When "m" set to TTnCCR0 TTnCCR0 m INTTTnCC0 Remark: 524 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-36: 16-bit Timer/Event Counter T Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (3/4) (c) when TECRTn Pin Input and TENCTn1 Pin Input Occur Simultaneously During Up Count Signal after edge detection TENCTn0 H TENCTn1 L TECRTn H Base clock Counter m 0 Count clock (d) when TECRTn Pin Input Occurs Earlier Than TENCTn1 Pin Input During Up Count Signal after edge detection TENCTn0 H TENCTn1 L TECRTn H Base clock Counter m 0 Count clock No miscount occurs due to TECRTn pin input delay because the clear condition is set according to the levels of pins TENCTn0, TENCTn1 and TECRTn, and the counter is cleared to 0000H upon clear condition detection. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 525 Chapter 11 16-bit Timer/Event Counter T Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (4/4) (e) when TECRTn Pin Input Occurs Later Than TENCTn1 Pin Input During Down Count Signal after edge detection TENCTn0 H TENCTn1 L TECRTn H Base clock m Counter m-1 0 Count clock When "m-1" set to TTnCCR0 m-1 TTnCCR0 Compare match interrupt not output INTTTnCC0 When "0000H" set to TTnCCR1 TTnCCR1 0 INTTTnCC1 When "m" set to TTnCR0 TTnCCR0 m INTTTnCC0 No miscount occurs due to the TECRTn pin input delay during down count, similarly to during up count. Remark: 526 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 (6) 16-bit Timer/Event Counter T Counter hold through bit TTnECC (a) Initial counter operation through bit TTnECC setting Figure 11-37: Counter Hold through Bit TTnECC Timings (1/5) (a) Count operation when TTnECC = 0 is set Base clock TTnECC Low TTnCE Internal count signal Counter FFFFH m m+1 m TTnTCW The setting value of the TTnTCW register is loaded to the counter and count operation is performed from the setting value of the TTnTCW register. (Initial value 0000H of TTnTCW register) (b) Count operation when TTnECC = 1 is set Base clock TTnECC High TTnCE Internal count signal Counter TTnTCW FFFFH 0000H m Since the setting value of the TTnTCW register is not loaded to the counter, the count operation is performed from initial value FFFFH. As the initial operation, it is recommended to set TTnECC = 0 and load to the counter the value set to the TTnTCW register, then start the count operation. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 527 Chapter 11 16-bit Timer/Event Counter T (b) Bit TTnECC rewrite timing and its influence on counter <1> When setting value of bit TTnECC is rewritten 0 1 0 when TTnCE = 1 Even if bit TTnECC rewrite is performed while TTnCE = 1, this has no influence on the counter operation. Judgment as whether to hold or reset the counter value is performed while TTnCE = 0. Moreover, judgment as to whether to load the setting value of the TTnTCW register to the counter is performed at the timing when the value of bit TTnCE changes from 0 to 1. Figure 11-37: Counter Hold through Bit TTnECC Timings (2/5) (c) when setting value of bit TTnECC is rewritten 0 1 0 when TTnCE = 1 TTnECC L TTnCE H No influence on operation L L L H Internal count signal Counter TCW TCW FFFFH Start ENC-Mode TCW Load Counter Start new ENC-Mode reset TCW Load Count Not Hold <2> When setting value of bit TTnECC is rewritten 1 0 1 while TTnCE = 0 The counter is reset when the setting value of bit TTnECC is changed from 1 to 0 while TTnCE = 0. Then, when TTnECC = 1 is set again and the value of bit TTnCE is changed from 0 to 1, counting restarts from the counter's initial value FFFFH, without the setting value of the TTnTCW being loaded to the counter. (d) when setting value of bit TTnECC is rewritten 1 0 1 while TTnCE = 0 TTnECC H L TTnCE L L H H Internal count signal Counter N FFFFH Counter Counter hold reset Remark: 528 Change ENC-Mode TCW not load n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 16-bit Timer/Event Counter T (c) Rewrite timing of bit TTnECC When TTnCE = 0 and TTnECC = 0, setting TTnCE = 1 causes the setting value of the TTnTCW register to be loaded to the counter. Perform rewrite of the TTnECC bit after the operation clock has become valid (after several clocks: TBD), following setting of TTnCE = 1. If bit TTnECC is rewritten before the operation clock becomes valid, counting starts from FFFFH without loading the setting value of the TTnTCW register to the counter. Figure 11-37: Counter Hold through Bit TTnECC Timings (3/5) (e) Basic Timing in Encoder Compare Mode (1) < Register setting conditions> * * * TTnCTL0: TTnMD3 to 0 = 1000B TTnCTL1: TTnUDS1, 0 = 00B TTnCTL1: TTnECM1, 0 = 01B * TTnCTL1: TTnLDE = 1 * TTnIOC3: TTnEIS1, 0 = 01B * TTnIOC3: TTnSCE = 0, TTnECS1-0 = 00B Encoder compare mode Judgment of up/down count with count judgment mode 1 Counter clear upon match between counter value and TTnCCR0 buffer register Loading of setting value of TTnCCR0 register (p) upon underflow occurrence Detection of rising edge of TENCTn0 and TENCTn1 pin inputs Valid edge detection clear (no edge specified) p Encoder counter q Down count Up count TENCTn0 TENCTn1 TTnCCR0 p TTnCCR1 q INTTTnCC0 INTTTnCC1 TTnESF TTnEUF Count clear Load to counter Load to counter Since TTnUDS1, 0 and TTnEIS1, 0 that control the count operation are set to 00B and 01B (rising edge detection), respectively, the counter is operated through detection of the phase of pin TENCTn1 upon detection of the rising edge of TENCTn0 pin input. A compare match interrupt (INTTTnCC0) is output upon a match between the counter value and the TTnCCR0 compare register (p). At this time, the counter is cleared to 0000H if the next count operation is up count. A compare match interrupt (INTTTnCC1) is output upon a match between the counter value and the TTnCCR1 buffer register (q). The counter is not cleared upon a match between the counter value and the TTnCCR1 register. If underflow occurs when TTnLDE = 1 is set, the setting value of the TTnCCR0 buffer register (m) is loaded to the counter. A count operation is possible between 0000H and the setting value of the TTnCCR0 register by setting TTnLDE = 1 and TTnECM0 = 1. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 529 Chapter 11 Figure 11-37: 16-bit Timer/Event Counter T Counter Hold through Bit TTnECC Timings (4/5) (f) Basic Timing in Encoder Compare Mode (2) <Setting conditions> * * TTnCTL0: TTnMD3 to 0 = 1000B TTnCTL1: TTnUDS1, 0 = 11B * TTnCTL1: TTnECM1, 0 = 00B * TTnCTL1: TTnLDE = 0 * TTnIOC3: TTnSCE = 0, TTnECS1-0 = 01B TTnCCR0 Encoder counter TTnCCR1 Encoder compare mode Judgment of up/down count with count judgment mode 4 No clear operation upon match between counter value and compare No loading of setting value of TTnCCR0 register (p) to counter Valid edge detection clear (rising edge specified) p 0000H q TENCTn0 TENCTn1 TECRTn TTnCCR0 p TTnCCR1 q INTTTnCC0 INTTTnCC1 TTnESF Since TTnUDS1, 0 that control the count operation are set to 11B, the counter is operated through detection of the phase of pins TENCTn0 and TENCTn1. A compare match interrupt (INTTTnCC0) is output upon a match between the counter value and the TTnCCR0 buffer register (p). A compare match interrupt (INTTTnCC1) is output upon a match between the counter value and the TTnCCR1 buffer register (q). The counter is not cleared upon a match with the TTnCCR0 register or the TTnCCR1 register. Clearing of the counter to 0000H is done upon detection of the valid edge of the encoder clear input (pin TECRTn) when TTnSCE = 0. When TTnECS = 01B is set, the counter is cleared to 0000H in synchronization with the operation clock, following detection of the rising edge of the TECRTn pin input. Remark: 530 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-37: 16-bit Timer/Event Counter T Counter Hold through Bit TTnECC Timings (5/5) (g) Basic Timing in Encoder Compare Mode (3) <Setting conditions> * * TTnCTL0: TTnMD3 to 0 = 1000B TTnCTL1: TTnUDS1 to 0 = 11B * TTnCTL1: TTnECM1 to 0 = 11B * TTnIOC3: TTnSCE = 0, TTnECS1 to 0 = 00B TTnCCR0 Encoder counter TTnCCR1 Encoder compare mode Judgment of up/down count with count judgment mode 4 Counter clear upon match between counter value and TTnCCR0 buffer register Counter clear upon match between counter value and TTnCCR1 buffer register (Since TTnCTL1: TTnECM1 to 0 = 11B, the setting of bit TTnLDE is invalid.) Valid edge detection clear (no edge specified) p 0000H q Up count Down count TENCTn0 TENCTn1 TTnCCR0 p TTnCCR1 q INTTTnCC0 INTTTnCC1 TTnESF Counter clear Match interrupt output Counter clear Match interrupt output Since TTnUDS1, 0 that control the count operation are set to 11B, the counter is operated through detection of the phase of pins TENCTn0 and TENCTn1. A compare match interrupt (INTTTnCC0) is output upon a match between the counter value and the TTnCCR0 buffer (p). At this time, the counter is cleared to 0000H if the next count operation is up count. A compare match interrupt (INTTTnCC1) is output upon a match between the counter value and the TTnCCR1 buffer (q). At this time, the counter is cleared to 0000H if the next count operation is down count. Remark: n = 0, 1 User's Manual U16580EE3V1UD00 531 Chapter 11 16-bit Timer/Event Counter T 11.6.10 Offset trigger generation mode In the offset trigger generation mode, the count value is saved to the capture register (TTnCCR0) upon detection of the valid edge of the TITn0 pin, and a capture interrupt (INTTTnCC0) is output. The counter is cleared to 0000H by capture input. (Counter clear operation is not performed using the TTnCCR1 register.) The TTnCCR0 register and the TTnCCR1 register have their functions fixed as a capture register and a compare register, respectively. The TTnCCR1 register can be rewritten during count operation. Regarding compare register reload, the capture & clear timing upon detection of TITn0 pin input serves as the reload timing. During count operation, a capture interrupt (INTTTnCC0) is output upon capture to the TTnCCR0 register through TITn0 pin input, and a compare match interrupt (INTTTnCC1) is output upon a match between the counter and the TTnCCR1 register. The TOTn0 pin becomes the level set with bit TTnOL0. If TTnOL0 = 0, a low level is output a and if TTnOL0 = 1, a high level is output. The TOTn1 pin is reset upon a match between the counter and the TTnCCR1 register, and is set when the counter is cleared to 0000H. Cautions: 1. In the offset trigger generation mode the external event clock input (TEVTTn) is prohibited (TTnCTL1.TTnEEE = 0). 2. When an internal count clock fXX/16 (TTnCTL0.TTnCKS2-0) is selected in offset trigger generation mode, and a valid signal edge is input to TITn0 before the first count up, the a value of FFFFH will be captured in the TTnCCR0 register. 532 User's Manual U16580EE3V1UD00 Chapter 11 Figure 11-38: 16-bit Timer/Event Counter T Basic Timing in Offset Trigger Generation Mode j i n n k m 0000H TTnCCR0 XXXX TTnCCR1 m TTnCCB1 m i j k n n TITn0 INTTTnCC0 INTTTICC1 TOTn0 Fixed (according to setting value of TTnOL0) TOTn1 Compare match interrupt Remark: Capture interrupt Compare Capture match interrupt interrupt Capture interrupt Compare match interrupt n = 0, 1 In the offset trigger generation mode, the setting value of the TTnCCR1 register is reloaded to the TTnCCR1 buffer register upon detection of the valid edge of pin TITn0. Until the edge of the TITn0 pin input is detected, the value of the TTnCCR1 register is not reloaded to the TTnCCR1 buffer register, even if this value is changed. Pin TOTn1 is set when the counter is cleared to 0000H upon detection of the valid edge of pin TITn0, and it is reset upon a match between the counter value and the TTnCCR1 register. Therefore, pin TOTn1 remains high level if the valid edge of the TITn0 pin input is detected before a match with the TTnCCR1 register occurs. User's Manual U16580EE3V1UD00 533 Chapter 11 534 16-bit Timer/Event Counter T User's Manual U16580EE3V1UD00 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (PD70F3187 only) 12.1 Features Timer ENC10 (TMENC10) is a 16-bit up/down counter that performs the following operations. * General-purpose timer mode: - Free-running timer - PWM output * Up/down counter mode - UDC mode A - UDC mode B Remark: TMENC10 is available on PD70F3187 only. 12.2 Function Outline * Compare register x 2 * Capture/compare register x 2 * Interrupt request source - Capture/compare match interrupt x 2 - Compare match interrupt x 2 - Overflow interrupt x 1 - Underflow interrupt x 1 * Capture request signal x 2 - The TMENC10 value can be latched using the valid edge of the TICC10, TICC11 pins corresponding to the capture/compare register as the capture trigger. * Base clock (fCLK) = fXX/4 (fCLK = 16 MHz @ fXX = 64 MHz) * Count clocks selectable through division by prescaler * 2-phase encoder input The 2-phase encoder signal from external is used as the count clock of the timer counter with the external clock input pins (TIUD1, TCUD1). The counter mode can be selected from among the four following modes. Mode 1: Counts the input pulses of the count pulse input pin. Up/down is specified by the level of one more input pin. Mode 2: Counts up/down using the respective input pulses of the up count pulse input pin and down count pulse input pin. Mode 3: Counts up/down using the phase relationship of the pulses input to 2 pins. Mode 4: Counts up/down using the phase relationship of the pulses input to 2 pins. Counting is done using the respective rising edges and the falling edges of the pulses. User's Manual U16580EE3V1UD00 535 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) * PWM output function - In the general-purpose timer mode, 16-bit resolution PWM output can be output from the TO1 pin. * Timer clear - The following timer clear operations are performed according to the mode that is used. (a) General-purpose timer mode: Timer clear operation is possible upon occurrence of match with CM100 set value. (b) Up/down counter mode: The timer clear operation can be selected from among the following four conditions. - Timer clear performed upon occurrence of match with CM100 set value during TMENC10 up count operation, and timer clear performed upon occurrence of match with CM101 set value during TMENC10 down count operation. - Timer clear performed only by external input. - Timer clear performed upon occurrence of match between TMENC10 count value and CM100 set value. - Timer clear performed upon occurrence of external input and match between TMENC10 count value and CM100 set value. * External pulse output (TO1) x 1 Remark: 536 fXX: Internal system clock User's Manual U16580EE3V1UD00 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.3 Basic Configuration The basic configuration is shown below. Table 12-1: Remark: Timer ENC10 Configuration List Timer Count Clock Register Read/Write Generated Interrupt Signal Capture Trigger Timer ENC10 fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512 TMENC10 Read/write INTOVF INTUDF - CM100 Read/write INTCM10 - CM101 Read/write INTCM11 - CC100 Read/write INTCC10 TICC10 CC101 Read/write INTCC11 TICC11 fXX: Internal system clock User's Manual U16580EE3V1UD00 537 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Figure 12-1 shows the block diagram of timer ENC10. Figure 12-1: Block Diagram of Timer ENC10 (TMENC10) Internal bus Edge detector CC10 CC11 TCLR1/ TICC10 Edge detector TCUD1/ TICC11 Edge detector TM1UBD CMD Clear 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 TM10 clear controller Edge detector Selector INTCC10 Selector INTCC11 TCLR TM1OVF TM1UDF INTOVF INTUDF TMENC1 fXX/4 Output control TIUD1 Edge detector ENMD MSEL CM10 CM11 RLEN ALVT1 TO1 INTCM10 INTCM11 CLR1, CLR0 Internal bus Note: The TICC11 interrupt is the signal of the interrupt from the TICC11 pin or the interrupt from the TICC10 pin, selected by the CSL bit of the CSL1 register. Remark: 538 fXX: Internal system clock User's Manual U16580EE3V1UD00 Chapter 12 (1) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Timer ENC10 (TMENC10) TMENC10 is a 2-phase encoder input up/down counter and general-purpose timer. It can be read/written in 16-bit units. Reset input clears TMENC10 to 0000H. Cautions: 1. Write to TMENC10 is enabled only when the TM1CE bit of the TMC10 register is "0" (count operation disabled). 2. It is prohibited to clear the CMD bit (general-purpose timer mode) to 0 and to set the MSEL bit (UDC mode B) of the TUM register to 1. 3. Continuous reading of TMENC10 is prohibited. If TMENC10 is continuously read, the second value read may differ from the actual value. If TMENC1n must be read twice, be sure to read another register between the first and the second read operation. 4. Writing the same value to the TMENC10, CC100, and CC101 registers, and the STATUS10 register is prohibited. Writing the same value to the CCR10, TUM10, TMC10, SESA10, and PRM10 registers, and CM100 and CM101 registers is permitted (writing the same value is guaranteed even during a count operation). Figure 12-2: After reset: 15 0000H 14 13 R/W 12 11 Timer ENC10 (TMENC10) Address: 10 9 8 FFFFF6B0H 7 6 5 4 3 2 1 0 TMENC10 TMENC10 start and stop is controlled by the TM1CE bit of timer control register 10 (TMC10). The TMENC10 operation consists of the following two modes. (a) General-purpose timer mode In the general-purpose timer mode, TMENC10 operates as a 16-bit interval timer, free-running timer, or for PWM output. Counting is performed based on the clock selected by software. Division by the prescaler can be selected for the count clock from among fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, or fXX/512 with bits PRM102 to PRM100 of prescaler mode register 10 (PRM10) (fXX: internal system clock). (b) Up/down counter mode (UDC mode) In the UDC mode, TMENC10 functions as a 16-bit up/down counter, counting based on the TCUD1 and TIUD1 input signals. Two operation modes can be set with the MSEL bit of the TUM register for this mode. * UDC mode A (when CMD bit = 1, MSEL bit = 0) TMENC10 can be cleared by setting the CLR1 and CLR0 bits of the TMC10 register. * UDC mode B (when CMD bit = 1, MSEL bit = 1) TMENC10 is cleared upon match with CM100 during TMENC10 up count operation. TMENC10 is cleared upon match with CM101 during TMENC10 down count operation. User's Manual U16580EE3V1UD00 539 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) When the TM1CE bit of the TMC10 register is "1", TMENC10 counts up when the operation mode is the general-purpose mode, and counts up/down when the operation mode is the UDC mode. The conditions for clearing the TMENC10 are classified as follows depending on the operation mode. Table 12-2: Operation Mode Timer ENC10 (TMENC10) Clear Conditions TUM10 Register TMC10 Register TMENC10 Clear CMD Bit MSEL Bit ENMD Bit CLR1 Bit CLR0 Bit General-purpose timer mode 0 UDC mode A 1 UDC mode B 1 0 0 1 0 x x Clearing not performed 1 x x Cleared upon match with CM100 set value x 0 0 Cleared only by TCLR1 input x 0 1 Cleared upon match with CM1n0 set value during up count operation x 1 0 Cleared by TCLR1 input or upon match with CM100 set value during up count operation x 1 1 Clearing not performed x x x Cleared upon match with CM100 set value during up count operation or upon match with CM101 set value during down count operation Settings other than the above Remark: 540 Setting prohibited x: Indicates that the set value of that bit is ignored. User's Manual U16580EE3V1UD00 Chapter 12 (2) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Compare register 100 (CM100) CM100 is a 16-bit register that always compares its value with the value of TMENC10. When the value of a compare register matches the value of TMENC10, an interrupt signal is generated. The interrupt generation timing in the various modes is described below. * In the general-purpose timer mode (CMD bit of TUM10 register = 0) and UDC mode A (MSEL bit of TUM10 register = 0), an interrupt signal (INTCM10) is always generated upon occurrence of a match. * In UDC mode B (MSEL bit of TUM10 register = 1), an interrupt signal (INTCM10) is generated only upon occurrence of a match during up count operation. This register can be read/written in 16-bit units. Reset input clears this register to 0000H. Caution: When the TM1CE bit of the TMC10 register is 1, it is prohibited to overwrite the value of the CM100 register. Figure 12-3: After reset: 15 0000H 14 13 Compare Register 100 (CM100) R/W 12 11 Address: 10 9 8 FFFFF6B2H 7 6 5 4 3 2 1 0 CM100 User's Manual U16580EE3V1UD00 541 Chapter 12 (3) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Compare register 101 (CM101) CM101 is a 16-bit register that always compares its value with the value of TMENC10. When the value of a compare register matches the value of TMENC10, an interrupt signal is generated. The interrupt generation timing in the various modes is described below. * In the general-purpose timer mode (CMD bit of TUM10 register = 0) and UDC mode A (MSEL bit of TUM10 register = 0), an interrupt signal (INTCM11) is always generated upon occurrence of a match. * In UDC mode B (MSEL bit of TUMn register = 1), an interrupt signal (INTCM11) is generated only upon occurrence of a match during down count operation. This register can be read/written in 16-bit units. Reset input clears this register to 0000H. Caution: When the TM1CE bit of the TMC10 register is 1, it is prohibited to overwrite the value of the CM101 register. Figure 12-4: After reset: 15 0000H 14 13 Compare Register 101 (CM101) R/W 12 11 Address: 10 9 8 FFFFF6B4H 7 6 5 CM101 542 User's Manual U16580EE3V1UD00 4 3 2 1 0 Chapter 12 (4) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture/compare register 100 (CC100) CC100 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCR). This register can be read/written in 16-bit units. Reset input clears this register to 0000H. Cautions: 1. When used as a capture register (CMS0 bit of CCR register = 0), write access is prohibited. 2. When used as a compare register (CMS0 bit of CCR register = 1) and the TM1CE bit of the TMC10 register is 1, overwriting the CC100 register values is prohibited. 3. When the TM1CE bit of the TMC10 register is 0, the capture trigger is disabled. 4. When the operation mode is changed from capture register to compare register, set a new compare value. 5. Continuous reading of CC100 is prohibited. If CC100 is continuously read, the second read value may differ from the actual value. If CC100 must be read twice, be sure to read another register between the first and the second read operation. Figure 12-5: After reset: 15 0000H 14 13 Capture/Compare Register 100 (CC100) R/W 12 11 Address: 10 9 8 FFFFF6B6H 7 6 5 4 3 2 1 0 CC100 (a) When set as a capture register When CC100 is set as a capture register, the valid edge of the corresponding external TICC10 signal is detected as the capture trigger. TMENC10 latches the count value in synchronization with the capture trigger (capture operation). The latched value is held in the capture register until the next capture operation. The valid edge of external interrupts (rising edge, falling edge, both edges) is selected with signal edge selection register 10 (SESA10). When the CC100 register is specified as a capture register, an INTCC10 interrupt is generated upon detection of the valid edge of the external TICC10 signal. (b) When set as a compare register When CC100 is set as a compare register, it always compares its own value with the value of TMENC10. If the value of CC100 matches the value of the TMENC10, CC100 generates an interrupt signal (INTCC10). User's Manual U16580EE3V1UD00 543 Chapter 12 (5) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture/compare register 101 (CC101) CC101 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register (CCR). This register can be read/written in 16-bit units. Reset input clears this register to 0000H. Cautions: 1. When used as a capture register (CMS1 bit of CCR register = 0), write access is prohibited. 2. When used as a compare register (CMS1 bit of CCRn register = 1) and the TM1CE bit of the TMC10 register is 1, overwriting the CC101 register values is prohibited. 3. When the TM1CE bit of the TMC10 register is 0, the capture trigger is disabled. 4. When the operation mode is changed from capture register to compare register, set a new compare value. 5. Continuous reading of CC101 is prohibited. If CC101 is continuously read, the second read value may differ from the actual value. If CC101 must be read twice, be sure to read another register between the first and the second read operation. Figure 12-6: After reset: 15 0000H 14 13 Capture/Compare Register 101 (CC101) R/W 12 11 Address: 10 9 8 FFFFF6B8H 7 6 5 4 3 2 1 0 CC101 (a) When set as a capture register When CC101 is set as a capture register, the valid edge of the corresponding external TICC11 signal is detected as the capture trigger. TMENC10 latches the count value in synchronization with the capture trigger (capture operation). The latched value is held in the capture register until the next capture operation. The valid edge of external interrupts (rising edge, falling edge, both edges) is selected with signal edge selection register 10 (SESA10). When the CC101 register is specified as a capture register, an INTCC11 interrupt is generated upon detection of the valid edge of the external TICC11 signal. (b) When set as a compare register When CC101 is set as a compare register, it always compares its own value with the value of TMENC10. If the value of CC101 matches the value of the TMENC10, CC101 generates an interrupt signal (INTCC11). 544 User's Manual U16580EE3V1UD00 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.4 Control Registers (1) Timer unit mode register 10 (TUM10) The TUM10 register is an 8-bit register used to specify the TMENC10 operation mode or to control the operation of the PWM output pin. This register can be read/written in 8-bit or 1-bit units. Reset input clears this register to 00H. Cautions: 1. Changing the value of the TUM10 register during TMENC10 operation (TM1CE bit of TMC register = 1) is prohibited. 2. When the CMD bit = 0 (general-purpose timer mode), setting MSEL bit = 1 (UDC mode B) is prohibited. Figure 12-7: After reset: TUM10 00H Timer Unit Mode Register 10 (TUM10) R/W Address: FFFFF6BBH 7 6 5 4 3 2 1 0 CMD 0 0 0 TOE ALVT1 0 MSEL CMD TMENC10 Operation Mode Specification 0 General-purpose timer mode (up count) 1 UDC mode (up/down count) TOE Timer Output (TO1) Control 0 Timer output disabled 1 Timer output enabled When CMD bit = 1 (UDC mode), timer output is not performed regardless of the setting of the TOE bit. At this time, timer output consists of the inverted phase level of the level set by the ALVT1 bit. ALVT1 Active Level Specification for Timer Output (TO1) 0 Active level is high level 1 Active level is low level When CMD bit = 1 (UDC mode), timer output is not performed regardless of the setting of the TOE bit. At this time, timer output consists of the inverted phase level of the level set by the ALVT1 bit. MSEL Mode Selection in UDC Mode (Up/Down Count) 0 UDC mode A. TMENC10 can be cleared by setting the CLR1, CLR0 bits of the TMC10 register. 1 UDC mode B. TMENC10 is cleared in the following cases. * Upon match with CM100 during TMENC10 up count operation * Upon match with CM101 during TMENC10 down count operation When UDC mode B is set, the ENMD, CLR1, and CLR0 bits of the TMC10 register become invalid. User's Manual U16580EE3V1UD00 545 Chapter 12 (2) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Timer control register 10 (TMC10) The TMC10 register is used to enable/disable TMENC10 operation and to set transfer and timer clear operations. This register can be read/written in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution: Changing the values of the TMC10 register bits other than the TM1CE bit during TMENC10 operation (TM1CE bit = 1) is prohibited. Figure 12-8: After reset: TMC10 00H Timer Control Register 10 (TMC10) (1/2) R/W Address: FFFFF6BCH 7 6 5 4 3 2 1 0 0 TM1CE 0 0 RLEN ENMD CLR1 CLR0 TM1CE TMENC10 Operation Control 0 Count operation disabled 1 Count operation enabled RLEN Transfer Operation Control in UDC Mode A 0 Transfer operation from CM100 register to TMENC10 disabled 1 Transfer operation from CM100 register to TMENC10 enabled * When RLEN = 1, the value set to CM100 is transferred to TMENC10 upon occurrence of TMENC10 underflow. * When the CMD bit of the TUM10 register = 0 (general-purpose timer mode), the RLEN bit settings are invalid, and a transfer operation is not executed even if the RLEN bit is set to 1. * When the MSEL bit of the TUM10 register = 1 (UDC mode B), the RLEN bit settings are invalid, and a transfer operation is not executed even if the RLEN bit is set to 1. ENMD Clear Operation Control in General Purpose Mode 0 Clear disabled (free-running mode) Clearing is not performed even when TMENC10 and CM100 values match. 1 Clear enabled Clearing is performed upon match of TMENC10 and CM100 values. When the CMD bit of the TUM10 register = 1 (UDC mode), the ENMD bit setting becomes invalid. 546 User's Manual U16580EE3V1UD00 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Figure 12-8: Timer Control Register 10 (TMC10) (2/2) CLR1 CLR0 Clear Operation Control in UDC Mode A 0 0 Clear only by external input (TCLR1) 0 1 Clear upon match of TMENC10 count value and CM100 set value 1 0 Clear by TCLR1 input or upon match of TMENC10 count value and CM100 set value 1 1 No clearing * Clearing by match of the TMENC10 count value and CM100 set value is valid only during TMENC10 up count operation (TMENC10 is not cleared during TMENC10 down count operation). * When the CMD bit of the TUM10 register = 0 (general-purpose timer mode), the CLR1 and CLR0 bit settings are invalid. * When the MSEL bit of the TUM10 register = 1 (UDC mode B), the CLR1 and CLR0 bit settings are invalid. * When clearing by TCLR1n has been enabled with bits CLR1 and CLR0, clearing is performed whether the value of the TM1CEn bit is 1 or 0. User's Manual U16580EE3V1UD00 547 Chapter 12 (3) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture/compare control register 10 (CCR10) The CCR10 register specifies the operation mode of the capture/compare registers (CC100, CC101). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Cautions: 1. Overwriting the CCR10 register during TMENC10 operation (TM1CE bit = 1) is prohibited. 2. The TCUD1 pin is used for the UDC mode and shared with the external capture input pin TICC11. Therefore, in the UDC mode, the external capture function cannot be used. 3. The TCLR1 pin is used for the UDC mode and alternately shared with the external capture input pin TICC10. Therefore, when the TCLR1 input is used in UDC mode A, the external capture function cannot be used. Figure 12-9: After reset: CCR10 00H R/W Address: FFFFF6BAH 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CMS1 CMS0 CMS1 CC101 Operation Mode Specification 0 CC101 operates as capture register 1 CC101 operates as compare register CMS0 548 Capture/Compare Control Register 10(CCR10) CC100 Operation Mode Specification 0 CC100 operates as capture register 1 CC100 operates as compare register User's Manual U16580EE3V1UD00 Chapter 12 (4) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Signal edge selection register 10 (SESA10) The SESA10 register specifies the valid edge of external interrupt requests from external pins (TICC10, TICC11, TCLR1). The valid edge (rising edge, falling edge, or both edges) can be specified independently for each pin. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Cautions: 1. Changing the values of the SESA10 register bits during TMENC10 operation (TM1CE bit = 1) is prohibited. 2. Be sure to set (1) the TM1CE bit of timer control register 1 (TMC10) even when TMENC10 is not used and the TICC10 and TICC11 pins are used as external interrupts INTCC10 and INTCC11 respectively. 3. Before setting the trigger mode of the TICC10, TICC11, and TCLR1n pins, set the PM10 and PMC10 registers. If the PM10 and PMC10 registers are set after the SESA10 register has been set, an illegal interrupt, incorrect counting, and incorrect clearing may occur, depending on the timing of setting the PM10 and PMC10 registers. Figure 12-10: After reset: SESA10 Signal Edge Selection Register 10 (SESA10) (1/2) 00H R/W 7 6 TESUD1 TESUD0 TIUD, TCUD1 Address: 5 4 CESUD1 CESUD0 TCLR1 FFFFF6BDH 3 2 1 0 IES111 IES110 IES101 IES100 TICC11 capture trigger TESUD1 TESUD0 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges TICC10 capture trigger Valid Edge Specification of TIUD1 and TCUD1 Pins * The set values of the TESUD1 and TESUD0 bits are only valid in UDC mode A and UDC mode B. * If mode 4 is specified as the operation mode of TMENC10 (specified with PRM102 to PRM100 bits of PRM10 register), the valid edge specifications for the TIUD1 and TCUD1 pins (TESUD1 and TESUD0 bits) are not valid. CESUD1 CESUD0 Valid Edge and Level Specification of TCLR1 Pins 0 0 Falling edge (TMENC10 cleared after edge detection) 0 1 Rising edge (TMENC10 cleared after edge detection) 1 0 Low level (TMENC10 clear status held) 1 1 High level (TMENC10 clear status held) The set values of the CESUD1 and CESUD0 bits are valid only in UDC mode A. User's Manual U16580EE3V1UD00 549 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Figure 12-10: Signal Edge Selection Register 10 (SESA10) (2/2) IES111 IES110 Valid Edge Specification of TICC11 Capture Trigger Input Pin 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges A valid edge on the TICC11 pin triggers the capture register CC101. Simultaneously an interrupt (INTCC11) is generated. IES101 IES100 Valid Edge Specification of TICC10 Capture Trigger Input Pin 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both, rising and falling edges A valid edge on the TICC10 pin triggers the capture register CC100. Simultaneously an interrupt (INTCC10) is generated. 550 User's Manual U16580EE3V1UD00 Chapter 12 (5) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Prescaler mode register 10 (PRM10) The PRM register is used to perform the following selections. * Selection of count clock in the general-purpose timer mode (CMD bit of TUM10 register = 0) * Selection of count operation mode in the UDC mode (CMD bit = 1) This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 07H. Cautions: 1. Overwriting the PRM10 register during TMENC10 operation (TM1CE bit = 1) is prohibited. 2. When the CMD bit of the TUM10 register = 1 (UDC mode), setting the values of the PRM2 to PRM0 bits to 000B, 001B, 010B, and 011B is prohibited. 3. When TMENC10 is in mode 4, specification of the valid edge for the TIUD1 and TCUD1 pins is invalid. Figure 12-11: After reset: PRM10 07H Prescaler Mode Register 10 (PRM10) R/W Address: FFFFF6BEH 7 6 5 4 3 2 1 0 0 0 0 0 0 PRM102 PRM101 PRM100 PRM102 PRM101 PRM100 CMD = 0 Count Clock Remark: CMD = 1 Count Clock UDC Mode 0 0 0 Setting prohibited Setting prohibited 0 0 1 fXX/8 0 1 0 fXX/16 0 1 1 fXX/32 1 0 0 fXX/64 1 0 1 fXX/128 Mode 2 1 1 0 fXX/256 Mode 3 1 1 1 fXX/512 Mode 4 TIUD1 Mode 1 fXX: Internal system clock (a) In general-purpose timer mode (CMD bit = 0) The count clock is fixed to the internal clock. The clock rate of TMENC10 is specified by the PRM102 to PRM100 bits. User's Manual U16580EE3V1UD00 551 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (b) UDC mode (CMD bit = 1) The TMENC10 count triggers in the UDC mode are as follows. Operation Mode 552 TMENC10 Operation Mode 1 Down count when TCUD1 = high level Up count when TCUD1 = low level Mode 2 Up count upon detection of valid edge of TIUD1 input Down count upon detection of valid edge of TCUD1 input Mode 3 Automatic judgment by TCUD1 input level upon detection of valid edge of TIUD1 input Mode 4 Automatic judgment upon detection of both edges of TIUD1 input and both edges of TCUD1 input User's Manual U16580EE3V1UD00 Chapter 12 (6) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Status register 10 (STATUS10) The STATUS10 register indicates the operating status of TMENC10. This register is read-only in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution: Overwriting the STATUS10 register during TMENC10 operation (TM1CE bit = 1) is prohibited. Figure 12-12: After reset: STATUS10 00H R/W Status Register 10 (STATUS10) Address: FFFFF6BFH 7 6 5 4 3 2 0 0 0 0 0 TM1UDF TM1UDF 1 0 TM1OVF TM1UBD TMENC10 Underflow Flag 0 No TMENC10 count underflow 1 TMENC10 count underflow The TM1UDF bit is cleared (0) upon completion of read access to the STATUS10 register from the CPU. TM1OVF TMENC10 Overflow Flag 0 No TMENC10 count overflow 1 TMENC10 count overflow The TM1OVF bit is cleared (0) upon completion of read access to the STATUS10 register from the CPU. TM1UBD TMENC10 Up/Down Counter Operation Status 0 TMENC10 up count in progress 1 TMENC10 down count in progress The state of the TM1UBD bit differs according to the mode as follows. * The TM1UBD bit is fixed to 0 when the CMD bit of the TUM10 register = 0 (generalpurpose timer mode). * The TM1UBD bit indicates the TMENC10 up/down count status when the CMD bit of the TUM register = 1 (UDC mode) User's Manual U16580EE3V1UD00 553 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.5 Operation 12.5.1 Basic operation The following two operation modes can be selected for TMENC10. (1) General-purpose timer mode (CMD bit of TUM10 register = 0) In the general-purpose timer mode, the TMENC10 operates either as a 16-bit interval timer or as a PWM output timer (count operation is up count only). The count clock to TMENC10 is selected by prescaler mode register 10 (PRM10). (2) Up/down counter mode (UDC mode) (CMD bit of TUM10 register = 1) In the UDC mode, TMENC10 operates as a 16-bit up/down counter. External clock input (TIUD1, TCUD1 pins) set by PRM10 register setting is used as the TMENC10 count clock. The UDC mode is further divided into two modes according to the TMENC10 clear conditions. * UDC mode A (TUM10 register's CMD bit = 1, MSEL bit = 0) The TMENC10 clear source can be selected as external clear input (TCLR1), the internal signal indicating a match between the TMENC10 count value and the CM100 set value during an up count operation, or the logical sum (OR) of the two signals, using the CLR1 and CLR0 bits of the TMC10 register. TMENC10 can transfer (reload) the value of CM100 upon occurrence of TMENC10 underflow, when the RLEN bit of the TMC10 register is set (1). * UDC mode B (TUM10 register's CMD bit = 1, MSEL bit = 1) The status of TMENC10 after a match of the TMENC10 count value and CM100 set value is as follows. <1> In case of an up count operation, TMENC10 is cleared (0000H), and the INTCM10 interrupt is generated. <2> In case of a down count operation, the TMENC10 count value is decremented (-1). The status of TMENC10 after a match of the TMENC10 count value and CM101 set value is as follows. <1> In case of an up count operation, the TMENC10 count value is incremented (+1). <2> In case of a down count operation, TMENC10 is cleared (0000H), and the INTCM11 interrupt is generated. 554 User's Manual U16580EE3V1UD00 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.5.2 Operation in general-purpose timer mode TMENC10 can perform the following operations in the general-purpose timer mode. (1) Interval operation TMENC10 and CM100 always compare their values and the INTCM10 interrupt is generated upon occurrence of a match. TMENC10 is cleared (0000H) at the count clock following the match. Furthermore, when one more count clock is input, TMENC10 counts up to 0001H. The interval time can be calculated by the following formula. Interval time = (CM100 value + 1) x TMENC10 count clock rate Caution: (2) Interval operation can be achieved by setting the ENMD bit of the TMC register to 1. Free-running operation TMENC10 performs full count operation from 0000H to FFFFH, and after the TM1OVF bit of the STATUS10 register is set (1), TMENC10 is cleared and resumes counting. The free-running cycle can be calculated by the following formula. Free-running cycle = 65,536 x TMENC10 count clock rate Caution: (3) The free-running operation can be achieved by setting the ENMD bit of the TMC register to 0. Compare function TMENC10 connects two compare register (CM100, CM101) channels and two capture/compare register (CC100, CC101) channels. When the TMENC10 count value and the set value of one of the compare registers match, a match interrupt (INTCM10, INTCM11, INTCC10Note, INTCC11Note) is output. Particularly in the case of an interval operation, TMENC10 is cleared upon generation of the INTCM10 interrupt. Note: This match interrupt is generated when CC100 and CC101 are set to the compare register mode. User's Manual U16580EE3V1UD00 555 Chapter 12 (4) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture function TMENC10 connects two capture/compare register (CC100, CC101) channels. When CC100 and CC101 are set to the capture register mode, the value of TMENC10 is captured in synchronization with the corresponding capture trigger signal. Furthermore, an interrupt request (INTCC10, INTCC11) is generated by the TICC10, TICC11 input signals. Table 12-3: Remark: Capture Trigger Signal to 16-Bit Capture Register Capture Register Capture Trigger Signal CC100 TICC10 CC101 TICC11 CC100 and CC101 are capture/compare registers. Which of these registers is used is specified with capture/compare control register 1 (CCR10). The valid edge of the capture trigger is specified by signal edge selection register 10 (SESA10). If both the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the input pulse width from external. If a single edge is selected as the capture trigger, the input pulse cycle can be measured. (5) PWM output operation PWM output operation is performed from the TO1 pin by setting TMENC10 to the general-purpose timer mode (CMD bit of the TUM10 register = 0). The resolution is 16 bits, and the count clock can be selected from among seven internal clocks (fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512). Figure 12-13: TMENC10 Block Diagram (During PWM Output Operation) fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 TMENC1 (16 bits) Compare register (CM10) Compare register (CM11) 556 ALVT1 16 16 Remark: INTCM10 Clear S TUM1 register Q TO1n R INTCM11 fXX: Internal system clock User's Manual U16580EE3V1UD00 Chapter 12 * 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Description of operation The PWM output cycle is specified by using the compare register CM100. When the value of this register matches the value of TMENC10, the INTCM10 interrupt is generated, and TMENC10 is cleared at the next count clock after the match. The required PWM output duty is set by using the compare register CM101. Figure 12-14: PWM Signal Output Example (When ALVT10 Bit = 0 Is Set) CM10 set value TMENC1 CM11 set value TO1 INTCM10 INTCM11 Cautions: 1. Changing the values of the CM100 and CM101 registers is prohibited during TMENC10 operation (TM1CE bit of TMC10 register = 1). 2. Changing the value of the ALVT1 bit of the TUM register is prohibited during TMENC10 operation. 3. PWM signal output is performed from the second PWM cycle after the TM1CE bit is set (1). User's Manual U16580EE3V1UD00 557 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.5.3 Operation in UDC mode (1) Overview of operation in UDC mode The count clock input to TMENC10 in the UDC mode (CMD bit of TUM10 register = 1) can only be externally input from the TIUD1 and TCUD1 pins. Up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1 and TCUD1 pin inputs according to the PRM10 register setting (there is a total of four choices). Table 12-4: PRM10 Register List of Count Operations in UDC Mode Operation Mode TM1n Operation PRM102 PRM101 PRM100 1 0 0 Mode 1 Down count when TCUD1 = high level Up count when TCUD1 = low level 1 0 1 Mode 2 Up count upon detection of valid edge of TIUD1 input Down count upon detection of valid edge of TCUD1 input 1 1 0 Mode 3 Automatic judgment in TCUD1 input level upon detection of valid edge of TIUD1 input 1 1 1 Mode 4 Automatic judgment upon detection of both edges of TIUD1 input and both edges of TCUD1 input The UDC mode is further divided into two modes according to the TMENC10 clear conditions (count operation is performed only with TIUD1, TCUD1 input in both modes). * UDC mode A (TUM register's CMD bit = 1, MSEL bit = 0) The TMENC10 clear source can be selected as only external clear input (TCLR1), a match signal between the TMENC10 count value and the CM100 set value during up count operation, or logical sum (OR) of the two signals, using bits CLR1 and CLR0 of the TMC10 register. TMENC10 can transfer (reload) the value of CM100 upon occurrence of TMENC10 underflow, when the RLEN bit of the TMC10 register is set (1). * UDC mode B (TUMn register's CMD bit = 1, MSEL bit = 1) The status of TMENC10 after match of the TMENC10 count value and CM100 set value is as follows. <1> In case of an up count operation, TMENC10 is cleared (0000H), and the INTCM10 interrupt is generated. <2> In case of a down count operation, the TMENC10 count value is decremented (-1). The status of TMENC10 after match of the TMENC10 count value and CM101 set value is as follows. <1> In case of an up count operation, the TMENC10 count value is incremented (+1). <2> In case of a down count operation, TMENC10 is cleared (0000H), and the INTCM11 interrupt is generated. 558 User's Manual U16580EE3V1UD00 Chapter 12 (2) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Up/down count operation in UDC mode TMENC10 up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1 and TCUD1 pin inputs according to the PRM register setting. (a) Mode 1 (PRM12 to PRM10 bits = 100B) In mode 1, the following count operations are performed based on the level of the TCUD1 pin upon detection of the valid edge of the TIUD1 pin. * TMENC10 down count operation when TCUD1 pin = high level * TMENC10 up count operation when TCUD1 pin = low level Figure 12-15: Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin) TIUD1 TCUD1 TMENC1 0007H 0006H 0005H 0004H 0005H Down count Figure 12-16: 0006H 0007H Up count Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin): In Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing TIUD1 TCUD1 TMENC1 0007H 0006H 0005H 0004H 0005H Down count User's Manual U16580EE3V1UD00 0006H 0007H Up count 559 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (b) Mode 2 (PRM102 to PRM100 bits = 101B) The count conditions in mode 2 are as follows. * TMENC10 up count upon detection of valid edge of TIUD1 pin * TMENC10 down count upon detection of valid edge of TCUD1 pin Caution: If the count clock is simultaneously input to the TIUD1 pin and the TCUD1 pin, count operation is not performed and the immediately preceding value is held. Figure 12-17: Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1, TCUD1 Pins) TIUD1 TCUD1 TMENC1 0006H 0007H Up count 560 0008H 0007H Hold value User's Manual U16580EE3V1UD00 0006H Down count 0005H Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (c) Mode 3 (PRM102 to PRM100 bits = 110B) In mode 3, when two signals 90 degrees out of phase are input to the TIUD1 and TCUD1 pins, the level of the TCUD1 pin is sampled at the timing of the valid edge of the TIUD1 pin (refer to Figure 12-18). If the TCUD1 pin level sampled at the valid edge timing of the TIUD1 pin is low, TMENC10 counts down. If the TCUD1 pin level sampled at the valid edge timing of the TIUD1 pin is high, TMENC10 counts up. Figure 12-18: Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin) TIUD1 TCUD1 TMENC1 0007H 0008H 0009H 000AH Up count Figure 12-19: 0009H 0008H 0007H Down count Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin): In Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing TIUD1 TCUD1 TMENC1 0007H 0008H 0009H Up count 000AH 0009H 0008H 0007H Down count User's Manual U16580EE3V1UD00 561 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (d) Mode 4 (PRM102 to PRM100 bits = 111B) In mode 4, when two signals out of phase are input to the TIUD1 and TCUD1 pins, up/down operation is automatically judged and counting is performed according to the timing shown in Figure 12-20. In mode 4, counting is executed at both the rising and falling edges of the two signals input to the TIUD1 and TCUD1 pins. Therefore, TMENC10 counts four times per cycle of an input signal (x 4 count). Figure 12-20: Mode 4 TIUD1 TCUD1 TMENC1 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 0009H 0008H 0007H 0006H 0005H Up count Down count Cautions: 1. When mode 4 is specified as the operation mode of TMENC10, the valid edge specifications for pins TIUD1 and TCUD1 are not valid. 2. If the TIUD1 pin edge and TCUD1 pin edge are input simultaneously in mode 4, TMENC10 continues the same count operation (up or down) it was performing immediately before the input. 562 User's Manual U16580EE3V1UD00 Chapter 12 (3) 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Operation in UDC mode A (a) Interval operation The operations at the count clock following a match of the TMENC10 count value and the CM100 set value are as follows. * In case of up count operation: TMENC10 is cleared (0000H) and the INTCM10 interrupt is generated. * In case of down count operation: The TMENC10 count value is decremented (-1) and the INTCM10 interrupt is generated. Remark: The interval operation can be combined with the transfer operation. (b) Transfer operation The operations at the next count clock after the count value of TMENC10 becomes 0000H during TMENC10 count down operation are as follows. * In case of down count operation: The data held in CM100 is transferred. * In case of up count operation: The TMENC10 count value is incremented (+1). Remarks: 1. Transfer enable/disable can be set with the RLEN bit of the TMC10 register. 2. The transfer operation can be combined with the interval operation. Figure 12-21: Example of TMENC10 Operation When Interval Operation and Transfer Operation are Combined CM10 set value TMENC1 count value 0000H TMENC1 and CM10 match & timer clear TMENC1 underflow & CM10 data transfer Up count Down count User's Manual U16580EE3V1UD00 563 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (c) Compare function TM1n connects two compare register (CM100, CM101) channels and two capture/compare register (CC100, CC101) channels. When the TMENC10 count value and the set value of one of the compare registers match, a match interrupt (INTCM10, INTCM11, INTCC10Note, INTCC11Note) is output. Note: This match interrupt is generated when CC100 and CC101 are set to the compare register mode. (d) Capture function TMENC10 connects two capture/compare register (CC100, CC101) channels. When CC100 and CC101 are set to the capture register mode, the value of TMENC10 is captured in synchronization with the corresponding capture trigger signal. When the TMENC10 is set to the capture register mode, a capture interrupt (INTCC10, INTCC11) is generated upon detection of the valid edge. (4) Operation in UDC mode B (a) Basic operation The operations at the next count clock after the count value of TMENC10 and the CM100 set value match when TMENC10 is in UDC mode B are as follows. * In case of up count operation: TMENC10 is cleared (0000H) and the INTCM10 interrupt is generated. * In case of down count operation: The TMENC10 count value is decremented (-1). The operations at the next count clock after the count value of TMENC10 and the CM101 set value match when TMENC10 is in UDC mode B are as follows. * In case of up count operation: The TMENC10 count value is incremented (+1). * In case of down count operation: TMENC10 is cleared (0000H) and the INTCM11 interrupt is generated. Figure 12-22: Example of TM1Operation in UDC Mode CM10 set value Clear TMENC1 count value Clear TMENC1 not cleared if count clock counts down following match CM11 set value 564 User's Manual U16580EE3V1UD00 TMENC1 not cleared if count clock counts up following match Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (b) Compare function TMENC10 connects two compare register (CM100, CM101) channels and two capture/compare register (CC100, CC101) channels. When the TMENC10 count value and the set value of one of the compare registers match, a match interrupt (INTCM10 (only during up count operation), INTCM11 (only during down count operation), INTCC10Note, INTCC11Note) is output. Note: This match interrupt is generated when CC100 and CC101 are set to the compare register mode. (c) Capture function TMENC10 connects two capture/compare register (CC100, CC101) channels. When CC100 and CC101 are set to the capture register mode, the value of TMENC10 is captured in synchronization with the corresponding capture trigger signal. When the TMENC10 is set to the capture register mode, a capture interrupt (INTCC10, INTCC11) is generated upon detection of the valid edge. User's Manual U16580EE3V1UD00 565 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.6 Supplementary Description of Internal Operation 12.6.1 Clearing of count value in UDC mode B When TMENC10 is in UDC mode B, the count value clear operation is as follows. * In case of TMENC10 up count operation: TMENC10 is cleared upon match with CM100 * In case of TMENC10 down count operation: TMENC10 is cleared upon match with CM101 Figure 12-23: Clear Operation upon Match with CM100 During TMENC10 Up Count Operation Clear TMENC1 (Not clear TMENC1) Count clock (rising edge set as valid edge) TMENC1 FFFEH FFFFH CM10 0000H 0001H (FFFEH) (FFFDH) FFFFH Up count Remark: Up count (Down count) Items between parentheses in the above figure apply to down count operation. Figure 12-24: Clear Operation upon Match with CM101 during TMENC10 Down Count Operation Clear TMENC1 (Not clear TMENC1) Count clock (rising edge set as valid edge) TMENC1 00FFH 00FEH CM11 0000H FFFFH (00FFH) (0100H) 00FEH Up count Remark: 566 Down count (Up count) Items between parentheses in the above figure apply to up count operation. User's Manual U16580EE3V1UD00 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.6.2 Clearing of count value upon occurrence of compare match The internal operation during TMENC10 clear operation upon occurrence of a compare match is as follows. Figure 12-25: Count Value Clear Operation upon Compare Match Clear TMENC1 (Not clear TMENC1) Count clock (rising edge set as valid edge) TMENC1 FFFEH FFFFH CM10 0000H 0001H (FFFEH) (FFFDH) FFFFH Up count Caution: Remark: Up count (Down count) The operations at the next count clock after the count value of TMENC10 and the CM100 set value match are as follows. * In case of up count: Clear operation is performed. * In case of down count: Clear operation is not performed. Items between parentheses in the above figure apply to down count operation. 12.6.3 Transfer operation The internal operation during TMENC10 transfer operation is as follows. Figure 12-26: Internal Operation During Transfer Operation Transfer operation is performed. (Transfer operation is not performed.) Count clock (rising edge set as valid edge) TMENC1 0001H 0000H CM10 FFFFH FFFEH (0001H) (0002H) FFFFH Down count Caution: Remark: Down count (Up count) The count operations after the TMENC10 count value becomes 0000H are as follows. * In case of down count: Transfer operation is performed. * In case of up count: Transfer operation is not performed. Items between parentheses in the above figure apply to up count operation. User's Manual U16580EE3V1UD00 567 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.6.4 Interrupt signal output upon compare match An interrupt signal is output when the count value of TMENC10 matches the set value of the CM100, CM101, CC10Note, or CC11Note register. The interrupt generation timing is as follows. Note: When CC100 and CC101 are set to the compare register mode. Figure 12-27: Interrupt Output upon Compare Match (CM101 with Operation Mode set to General-Purpose Timer Mode and Count Clock Set to fXX/8) fXX/4 Count clock TMENC1 0007H 0008H CM11 0009H 000AH 000BH 0009H Internal match signal INTCM11 Remark: fCLK: Base clock An interrupt signal such as illustrated in Figure 12-27 is output at the next count following match of the TMENC10 count value and the set value of a corresponding compare register. 12.6.5 TM1UBD flag (bit 0 of STATUS register) operation In the UDC mode (CMD bit of TUM register = 1), the TM1UBD flag changes as follows during TMENC10 up/down count operation at every internal operation clock. Figure 12-28: TM1UBDn Flag Operation Count clock TMENC1 0000H 0001H 0000H 0001H 0000H TM1UBD 568 User's Manual U16580EE3V1UD00 0001H Chapter 13 Auxiliary Frequency Output Function (AFO) 13.1 Features * Frequency up to 8 Mbps * Programmable frequency output * Interval timer function * Interrupt request signal (INTBRG2) 13.2 Configuration The AFO function includes the following hardware. Table 13-1: AFO Configuration Item Control registers Configuration Prescaler mode registers 2 (PRSM2) Prescaler compare registers 2 (PRSCM2) Figure 13-1: fXX fXX/2 fXX/4 fXX/8 Block Diagram of Auxiliary Frequency Output Function 8-bit Counter Output Control AFO INTBRG2 PRSCM2 User's Manual U16580EE3V1UD00 569 Chapter 13 Auxiliary Frequency Output Function (AFO) 13.3 Control Registers (1) Prescaler mode register 2 (PRSM2) The PRSM2 register controls generation of a baud rate signal for the AFO function. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 13-2: After reset: 00H 7 PRSM2 Prescaler Mode Register 2 (PRSM2) R/W Address: FFFFFDE0H 6 5 4 3 2 1 0 0 0 BGCE2 0 0 BGCS21 BGCS20 BGCE2 Baud Rate Generator Output Control 0 Disabled 1 Enabled Baud Rate Generator Clock Selection (fBGCS2) Setting Value (k) BGCS21 BGCS20 0 0 fXX 0 0 1 fXX/2 1 1 0 fXX/4 2 1 1 fXX/8 3 Cautions: 1. Do not rewrite the PRSM2 register during operation. 2. Set the BGCS21, BGCS20 bits before setting the BGCE2 bit to 1. 570 User's Manual U16580EE3V1UD00 Chapter 13 (2) Auxiliary Frequency Output Function (AFO) Prescaler compare registers 2 (PRSCM2) The PRSCM2 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 13-3: After reset: 00H 7 PRSCM2 Prescaler Compare Register 2 (PRSCM2) R/W 6 Address: 5 FFFFFDE1H 4 3 2 1 0 PRSCM27 PRSCM26 PRSCM25 PRSCM24 PRSCM23 PRSCM22 PRSCM21 PRSCM20 PRSCM PRSCM PRSCM PRSCM PRSCM PRSCM PRSCM PRSCM AFO Clock 27 26 25 24 23 22 21 20 N 0 0 0 0 0 0 0 0 fBGSC2/256 256 0 0 0 0 0 0 0 1 fBGSC2 1 0 0 0 0 0 0 1 0 fBGSC2/2 2 : : : : : : : : : : 1 1 1 1 1 1 0 0 fBGSC2/252 252 1 1 1 1 1 1 0 1 fBGSC2/253 253 1 1 1 1 1 1 1 0 fBGSC2/254 254 1 1 1 1 1 1 1 1 fBGSC2/255 255 Cautions: 1. Do not rewrite the PRSCM2 register during operation. 2. Set the PRSCM2 register before setting the BGCE2 bit of the PRSM2 register to 1. 3. Do not set the AFO clock to a higher frequency than 8 MHz. Remark: fBGCS2: Clock frequency selected by the BGCS21, BGCS20 bits of the PRSM2 register. User's Manual U16580EE3V1UD00 571 Chapter 13 Auxiliary Frequency Output Function (AFO) 13.4 Operation 13.4.1 Auxiliary frequency output The auxiliary frequency output (AFO) is enabled as soon as the shared port (P75) is set into control output mode by setting bit 5 of the PM7 register to 0 and bit 5 of the PMC7 register to 1. 13.4.2 Auxiliary frequency generation The auxiliary frequency output clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. f BGCS2 f XX f AFO = ------------------ = ------------------------k Nx2 2 xNx2 Remarks: 1. fAFO: AFO clock 2. fBGCS2: Clock frequency selected by the BGCS21, BGCS20 bits of the PRSM2 register. 3. fXX: Main clock oscillation frequency 4. k: PRSM2 register setting value (2 k 5) 5. N: PRSCMm register setting value (1 to 255), when PRSCM2 = 01H to FFH, or N = 256, when PRSCM2 = 00H. 13.4.3 Interval timer function The AFO function can be used as interval timer regardless whether the auxiliary frequency output is used or not. For this purpose an interrupt request signal (INTBRG2) is assigned, which can be handled like any maskable interrupt. 572 User's Manual U16580EE3V1UD00 Chapter 14 A/D Converter 14.1 Features * Analog input: 2 x 10 channels (ANI00 to ANI09, ANI10 to ANI19) * 10-bit resolution * On-chip A/D conversion result register (ADCRn0 to ADCRn9): * A/D conversion trigger mode - A/D trigger mode - Timer trigger mode - External trigger mode * Successive approximation method * DMA transfer support of A/D conversion result to internal RAM Remark: 10 bits x 10 n = 0, 1 User's Manual U16580EE3V1UD00 573 Chapter 14 A/D Converter 14.2 Configuration The A/D converter of the V850E/PH2 adopts the successive approximation method, and uses A/D converter n mode registers 0, 1, 2 (ADMn0, ADMn1, ADMn2), and the A/D conversion result register (ADCRn0 to ADCRn9) to perform A/D conversion operations (n = 0, 1). (1) Input circuit The input circuit selects the analog input (ANIn0 to ANIn9) according to the mode set by the ADMn0, ADMn1, and ADMn2 registers. (2) C-Array Holds the charge of the differential voltage between the voltage input from the analog input pins (ANIn0 to ANIn9) and the reference voltage (1/2 AVDD), and redistributes the sampled charges. (3) C-Dummy This block holds the reference voltage (1/2 AVDD) and assigns the reference of the comparator input. (4) Voltage comparator The voltage comparator compares the C-Array comparison potential with the C-Dummy reference potential. (5) A/D conversion result register (ADCRnm), A/D conversion result register nH (ADCRnmH) (n = 0, 1)(m = 0 to 9) ADCRnm is a 10-bit register that holds A/D conversion results. Each time A/D conversion is completed, the conversion results are loaded from the successive approximation register (SAR). RESET input makes this register undefined. (6) A/D conversion result register for DMA transfer (ADDMAn) (n = 0, 1) ADDMAn is a 16-bit register that holds the last 10-bit A/D conversion result and an over rung flag for indicating a DMA transfer failure. (7) ANIn0 to ANIn9 pins (n = 0, 1) These are 10-channel analog input pins for the A/D converter n. They input the analog signals to be A/D converted. Caution: (8) Make sure that the voltages input to ANIn0 to ANIn9 do not exceed the rated values. If a voltage higher than AVDD or lower than AVSSn (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined, and the conversion values of the other channels may also be affected. AVREFn pins (n = 0, 1) This is the pin for inputting the reference voltage of the A/D converter. It converts signals input to the ANIn0 to ANIn9 pins to digital signals based on the voltage applied between AVSSn and AVREFn. 574 User's Manual U16580EE3V1UD00 Chapter 14 (9) A/D Converter AVSSn pin (n = 0, 1) This is the ground pin of the A/D converter. Always use this pin at the same potential as that of the EVSS pin even when the A/D converter is not used. (10) AVDD pin This is the analog power supply pin of both A/D converters (ADC0, ADC1). Figure 14-1: Block Diagram of A/D Converter (ADCn) ANIn0 Comparator ANIn1 ANIn4 ANIn5 ANIn6 Input circuit ANIn2 ANIn3 AVREFn C-Dummy AVDD AVSSn C-Array ANIn7 ANIn8 ANIn9 Successive approximation register (SAR) ADDMAn fXX/4 Trigger events from TMR0 Trigger events from TMR1 ADCRn1 (ADCRn1H) Edge detection ADTRGn ADCRn2 (ADCRn2H) Controller TR0ADTRG0 TR0ADTRG1 INTTR0OD INTTR0CD TR1ADTRG0 TR1ADTRG1 ADCRn0 (ADCRn0H) ADCRn3 (ADCRn3H) ADCRn4 (ADCRn4H) ADCRn5 (ADCRn5H) Trigger selector ADCRn6 (ADCRn6H) ADCRn7 (ADCRn7H) ADCRn8 (ADCRn8H) INTTR1OD INTTR1CD ADCRn9 (ADCRn9H) INTADn ADDMARQn Remarks: 1. fXX: Main clock 2. n = 0, 1 Cautions: 1. If there is noise at the analog input pins (ANIn0 to ANIn9) or at the reference voltage input pin (AVREFn), that noise may generate an illegal conversion result. Software processing will be needed to avoid a negative effect on the system from this illegal conversion result. An example of this software processing is shown below. * Take the average result of a number of A/D conversions and use that as the A/D conversion result. * Execute a number of A/D conversions consecutively and use those results, omitting any exceptional results that may have been obtained. 2. Do not apply a voltage outside the AVSSn to AVREFn range to the pins that are used as A/D converter input pins. User's Manual U16580EE3V1UD00 575 Chapter 14 A/D Converter 14.3 Control Registers (1) A/D converter n mode register 0 (ADMn0) The ADMn0 register is an 8-bit register that specifies the operation mode, and executes conversion operations. This register can be read or written in 8-bit or 1-bit units. However, bit 6 can only be read. Writing this bit is ignored. Reset input sets this register to 00H. Cautions: 1. When the ADCEn bit is 1 in the timer trigger mode and external trigger mode, the trigger signal standby state is set. To clear the ADCEn bit, write 0 or reset. In the A/D trigger mode, the conversion trigger is set by writing 1 to the ADCEn bit. After the operation, when the mode is changed to the timer trigger mode or external trigger mode without clearing the ADCEn bit, the trigger input standby state is set immediately after changing the register. 2. Changing the setting of the BSn and MSn bits is prohibited while A/D conversion is enabled (ADCEn bit = 1). 3. When data is written to the ADMn0 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning. Figure 14-2: After reset: ADMn0 00H A/D Converter n Mode Register 0 (ADMn0) R/W Address: ADM00 FFFFF200H, ADM10 FFFFF240H 7 6 5 4 3 2 1 0 ADCEn ADCSn BSn MSn 0 0 0 0 (n = 0, 1) ADCEn A/D Conversion Operation Control of ADCn 0 Disables A/D conversion operation of ADCn 1 Enables A/D conversion operation ADCn ADCSn A/D Conversion Status Flag of ADCn 0 A/D conversion of ADCn is stopped 1 A/D conversion of ADCn is operating BSn ADCn Buffer Mode Specification 0 1-buffer mode 1 4-buffer mode MSn Remark: 576 ADCn Operation Mode Specification 0 Scan mode 1 Select mode n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 14 (2) A/D Converter A/D converter n mode register 1 (ADMn1) The ADMn1 register is an 8-bit register that specifies the conversion operation time and trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Cautions: 1. Changing the setting of the EGAn1, EGAn0, and FRn3 to FRn0 bits is prohibited while A/D conversion is enabled (ADCEn bit of the ADMn0 register = 1). 2. When data is written to the ADMn1 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning. Figure 14-3: After reset: ADMn1 00H A/D Converter n Mode Register 1 (ADMn1) (1/2) R/W Address: ADM01 FFFFF201H, ADM11 FFFFF241H 7 6 5 4 3 2 1 0 EGAn1 EGAn0 TRGn1 TRGn0 FRn3 FRn2 FRn1 FRn0 EGAn1 EGAn0 0 0 No edge detected (does not operate as external trigger) 0 1 Falling edge detected 1 0 Rising edge detected 1 1 Both edges, falling and rising edge detected TRGn1 TRGn0 0 0 A/D trigger mode 0 1 Timer trigger mode 1 0 External trigger mode 1 1 Setting prohibited (n = 0, 1) Remark: Valid Edge Specification of External Trigger Input (ADTRGn) ADCn Trigger Mode Specification n = 0, 1 User's Manual U16580EE3V1UD00 577 Chapter 14 A/D Converter Figure 14-3: FRn3 FRn2 A/D Converter n Mode Register 1 (ADMn1) (2/2) FRn1 FRn0 Number of conversion clocks Conversion Operation TimeNote 1 fXX = 64 MHz A/D Stabilization TimeNote 2 0 0 0 0 128 2.0 s 64/fXX 0 0 0 1 256 4.0 s 128/fXX 0 0 1 0 384 6.0 s 160/fXX 0 0 1 1 512 8.0 s 160/fXX 0 1 0 0 640 160/fXX 0 1 0 1 768 Setting prohibited Others than above 160/fXX Setting prohibited Notes: 1. Set the conversion operation time in the range of 2 to 10 s. 2. After the ADCEn bit is set from 0 to 1 to secure the stabilization time of the A/D converter, conversion is started after the A/D stabilization time has elapsed only before the first A/D conversion is executed. Cautions: 1. Do not change the set value of the A/D conversion time (FRn3 to FRn0 bits) during an A/D conversion operation (ADCEn bit = 1). To change the value, clear the ADCEn bit to 0. 2. When the trigger mode (TRGn1 and TGRn0 bits) is changed midway, A/D conversion can be started immediately without having to secure the A/D stabilization time by re-setting the ADCE bit to 1. Remarks: 1. fXX: Main clock 2. n = 0, 1 578 User's Manual U16580EE3V1UD00 Chapter 14 (3) A/D Converter A/D converter n mode register 2 (ADMn2) The ADMn2 register is an 8-bit register that specifies the analog input pin of the A/D converter n (n = 0, 1). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Cautions: 1. If a channel for which no analog input pin exists is specified, the result of A/D conversion is undefined. 2. Changing the setting of the ANISn3 to ANISn0 bits is prohibited while A/D conversion is enabled (ADCEn bit of the ADMn0 register = 1). 3. When data is written to the ADMn2 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning. Figure 14-4: After reset: ADMn2 00H A/D Converter n Mode Register 2 (ADMn2) R/W Address: ADM01 FFFFF201H, ADM11 FFFFF241H 7 6 5 4 3 2 1 0 0 0 0 0 ANISn3 ANISn2 ANISn1 ANIn0 ANISn ANISn ANISn ANISn (n = 0, 1) Specification of Analog Input Pins for A/D Conversion Select Mode 0 0 0 0 ANIn0 ANIn0 0 0 0 1 ANIn1 ANIn0, ANIn1 0 0 1 0 ANIn2 ANIn0 to ANIn2 0 0 1 1 ANIn3 ANIn0 to ANIn3 0 1 0 0 ANIn4 ANIn0 to ANIn4 0 1 0 1 ANIn5 ANIn0 to ANIn5 0 1 1 0 ANIn6 ANIn0 to ANIn6 0 1 1 1 ANIn7 ANIn0 to ANIn7 1 0 0 0 ANIn8 ANIn0 to ANIn8 1 0 0 1 ANIn9 ANIn0 to ANIn9 Others than above Remark: Scan Mode Setting prohibited n = 0, 1 User's Manual U16580EE3V1UD00 579 Chapter 14 A/D Converter (4) A/D converter n trigger source select register (ADTRSELn) The ADTRSELn register is an 8-bit register that specifies the timer trigger signal in the timer trigger mode (TRGn1, TRGn0 bits of ADMn1 register = 01B). This register can be read or written in 8-bit units. Reset input sets this register to 00H. Caution: Before changing the setting of the ADTRSELn register, stop the A/D conversion operation (by clearing the ADCEn bit of the ADMn0 register to 0). The operation is not guaranteed if the setting of the ADTRSELn register is changed while A/D conversion is enabled (ADCEn bit = 1). Figure 14-5: After reset: ADTRSELn A/D Converter n Trigger Source Select Register (ADTRSELn) 00H R/W Address: ADTRSEL0 FFFFF270H, ADTRSEL1 FFFFF272H 7 6 5 4 3 2 1 0 0 0 0 0 TSELn3 TSELn2 TSELn1 TSELn0 TSELn3 TSELn2 TSELn2 TSELn0 0 0 0 0 None. All trigger sources are ignored. 0 0 0 1 TR0ADTRG0 signal (from TMR0) 0 0 1 0 TR0ADTRG1 signal (from TMR0) 0 0 1 1 TR1ADTRG0 signal (from TMR1) 0 1 0 0 TR1ADTRG1 signal (from TMR1) 0 1 0 1 INTTR0OD interrupt (from TMR0) 0 1 1 0 INTTR0CD interrupt (from TMR0) 0 1 1 1 INTTR1OD interrupt (from TMR1) 1 0 0 0 INTTR1CD interrupt (from TMR1) (n = 0, 1) Others than above Remark: 580 Trigger Source Selection in Timer Trigger Mode Setting prohibited n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 14 (5) A/D Converter A/D conversion result registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) The ADCRnm register is a 10-bit register holding the A/D conversion results (n = 0, 1)(m = 0 to 9). These registers are read-only in 16-bit or 8-bit units. When 16-bit access is performed, the ADCRnm register is specified, and when 8 bit access is performed, the ADCRnmH register holding the higher 8 bits of the conversion result is specified. When reading the 10-bit data of the A/D conversion results from the ADCRnm register, only the higher 10 bits are valid and the lower 6 bits are always read as 0. Reset input causes an undefined register content. Figure 14-6: A/D Conversion Result Registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) After reset: Undefined 15 14 R 13 12 Address: 11 10 9 8 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 ADCR08 ADCR09 7 FFFFF210H, ADCR10 FFFFF212H, ADCR11 FFFFF214H, ADCR12 FFFFF216H, ADCR13 FFFFF218H, ADCR14 FFFFF21AH, ADCR15 FFFFF21CH, ADCR16 FFFFF21EH, ADCR17 FFFFF220H, ADCR18 FFFFF222H, ADCR19 6 ADnm9 ADnm8 ADnm7 ADnm6 ADnm5 ADnm4 ADnm3 ADnm2 ADnm1 ADnm0 ADCRnm FFFFF250H, FFFFF252H, FFFFF254H, FFFFF256H, FFFFF258H, FFFFF25AH, FFFFF25CH, FFFFF25EH, FFFFF260H, FFFFF262H, 5 4 3 2 1 0 0 0 0 0 0 0 ADCRnmH After reset: ADCRnmH Remark: Undefined R Address: ADCR00H ADCR01H ADCR02H ADCR03H ADCR04H ADCR05H ADCR06H ADCR07H ADCR08H ADCR09H FFFFF210H, ADCR10H FFFFF250H, FFFFF212H, ADCR11H FFFFF252H, FFFFF214H, ADCR12H FFFFF254H, FFFFF216H, ADCR13H FFFFF256H, FFFFF218H, ADCR14H FFFFF258H, FFFFF21AH, ADCR15H FFFFF25AH, FFFFF21CH, ADCR16H FFFFF25CH, FFFFF21EH, ADCR17H FFFFF25EH, FFFFF220H, ADCR18H FFFFF260H, FFFFF222H, ADCR19H FFFFF262H, 7 6 5 4 3 2 1 0 ADnm9 ADnm8 ADnm7 ADnm6 ADnm5 ADnm4 ADnm3 ADnm2 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 581 Chapter 14 A/D Converter The correspondence between each analog input pin and the ADCRnm register is shown in Table 14-1 below. Table 14-1: Assignment of A/D Conversion Result Registers to Analog Input Pins Analog Input Pin Assignment of A/D Conversion Result Registers Select 1 Buffer Mode/ Scan Mode ANIn0 ADCRn0, ADCRn0H ANIn1 ADCRn1, ADCRn1H ANIn2 ADCRn2, ADCRn2H ANIn3 ADCRn3, ADCRn3H ANIn4 ADCRn4, ADCRn4H ANIn5 ADCRn5, ADCRn5H ANIn6 ADCRn6, ADCRn6H ANIn7 ADCRn7, ADCRn7H ANIn8 ADCRn8, ADCRn8H ANIn9 ADCRn9, ADCRn9H Select 4 Buffer Mode ADCRn0 to ADCRn3, ADCRn0H to ADCRn3H ADCRn4 to ADCRn7, ADCRn4H to ADCRn7H ADCRn8 to ADCRn9, ADCRn8H to ADCRn9H The relationship between the analog voltage input to the analog input pins (ANIn0 to ANIn9) and the A/D conversion result (of the A/D conversion result register (ADCRnm)) is as follows: V IN ADCR = INT ------------------ x 1024 + 0,5 AV REF or, AV REF AV REF ( ADCR - 0,5 ) x ------------------ V IN < ( ADCR + 0,5 ) x -----------------1024 1024 INT( ): VIN: AVREF: ADCR: Function that returns the integer value Analog input voltage AVREF pin voltage Value of A/D conversion result register (ADCRnm) Figure 14-7 shows the relationship between the analog input voltage and the A/D conversion results. Remark: 582 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-7: A/D Converter Relationship Between Analog Input Voltage and A/D Conversion Results 1023 1022 A/D conversion 1021 results (ADCRnm) 3 2 1 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF Remark: n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 583 Chapter 14 A/D Converter (6) A/D conversion result register n for DMA (ADDMAn) The ADDMAn register is a 16-bit register holding the result of the latest A/D conversion operation, and is used for DMA transfer of ADCn results into the internal RAM. It has an overrun detection flag indicating an overrun situation of the DMA transfer mechanism (n = 0, 1). This register is read-only in 16-bit units. Reset input causes an undefined register content. Caution: Do not read the ADDMAn register by CPU during DMA transfer activities. If this register is read by CPU, overflow detection cannot be ensured. Figure 14-8: A/D Conversion Result Registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) After reset: Undefined 15 ADDMAn 14 13 R 12 11 Address: 10 9 8 ADDMA0 FFFFF224H, ADDMA1 FFFFF264H 7 6 ADDMA ADDMA ADDMA ADDMA ADDMA ADDMA ADDMA ADDMA ADDMA ADDMA n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 ADDMAn9 to ADDMAn0 000H to 3FFH ODFn 5 4 3 2 1 0 0 0 0 0 0 ODFn A/D Conversion Result for DMA Transfer Latest A/D conversion result value Overrun Detection Flag 0 No A/D conversion result overrun was detected. 1 At least one A/D conversion result was overrun since the last read of the ADDMAn register. * The ODFn flag is used for indicating a DMA transfer failure of the A/D conversion results. * The ODFn flag is cleared (0), when the A/D conversion is stopped (ADCEn bit of the ADMn0 register is cleared to 0). Remark: 584 n = 0, 1 User's Manual U16580EE3V1UD00 Chapter 14 A/D Converter 14.4 Operation 14.4.1 Basic operation A/D conversion is executed by the following procedure. <1> The selection of the analog input and specification of the operation mode, trigger mode, etc. should be specified using the ADMn0, ADMn1 or ADMn2 registersNote 1 (n = 0, 1). When the ADCEn bit of the ADMn0 register is set to 1, A/D conversion starts in the A/D trigger mode. In the timer trigger mode and external trigger mode, the trigger standby stateNote 2 is set. <2> When A/D conversion is started, the C-array voltage on the analog input side and the C-array voltage on the reference side are compared by the comparator. <3> When the comparison of the 10 bits ends, the conversion results are stored in the ADCRnm register. When A/D conversion has been performed the specified number of times, the A/D conversion end interrupt (INTADn) is generated (n = 0, 1), (m = 0 to 9). Notes: 1. If the setting of the ADMn0, ADMn1 or ADMn2 registers (n = 0, 1) is changed during A/D conversion, the operation immediately before is stopped, and the result of the conversion is not stored in the ADCRnm register (m = 0 to 9). The A/D conversion operation is then initialized, and conversion is executed from the beginning again. 2. During the timer trigger mode and external trigger mode, if the ADCEn bit of the ADMn0 register is set to 1, the mode changes to the trigger standby state. The A/D conversion operation is started by the trigger signal (ADCSn bit in the ADMn0 register = 1), and the trigger standby state (ADCSn bit = 0) is returned when the A/D conversion operation ends. User's Manual U16580EE3V1UD00 585 Chapter 14 A/D Converter 14.4.2 Operation mode and trigger mode Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADMn0 and ADMn1registers. The following table shows the relationship between the operation mode and trigger mode. Table 14-2: Relationship Between Operation Mode and Trigger Mode Trigger Mode A/D trigger Operation Mode Select ADMn0 ADMn1 1 buffer xx010000B xx000xxxB 4 buffers xx110000B Scan Timer trigger Select xx000000B 1 buffer xx010000B 4 buffers xx110000B Scan External trigger Select Scan (1) Register Set Value xx010xxxB xx000000B 1 buffer xx010000B 4 buffers xx110000B xx100xxxB xx000000B Trigger mode There are three types of trigger modes that serve as the start timing of A/D conversion processing: A/D trigger mode, timer trigger mode, and external trigger mode. These trigger modes are set by the TRGn1 and TRGn0 bits of the ADMn1 register. (a) A/D trigger mode This mode starts the conversion timing of the analog input set to the ANIn0 to ANIn9 pins, and by setting the ADCEn bit of the ADMn0 register to 1, starts A/D conversion. Unless the ADCEn bit is cleared to 0 after conversion, the next conversion operation is repeated. If data is written to the ADMn0 to ADMn2 registers during conversion, conversion is stopped and then executed from the beginning again. (b) Timer trigger mode This mode specifies the conversion timing of the analog input set for the ANIn0 to ANIn9 pins using signals from the inverter timer R (TMR0, TMR1). The ADTRSELn register specifies the analog input conversion timing by selecting either one of the A/D converter trigger signals (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1) or one of the top and bottom reversal interrupts (INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) connected to the 16-bit inverter timer R (TMR0, TMR1). If the ADCEn bit of the ADMn0 register is set to 1, the A/D converter waits for an event input (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, or INTTR1OD), and starts conversion when the event occurs (ADCSn bit of the ADMn0 register = 1). When conversion has finished, the converter waits for an event input again (ADCSn bit = 0). If data is written to the ADMn0 to ADMn2 registers during conversion, conversion is stopped and then executed from the beginning again. 586 User's Manual U16580EE3V1UD00 Chapter 14 A/D Converter (c) External trigger mode This mode specifies the conversion timing of the analog input to the ANIn0 to ANIn9 pins using the ADTRGn pin. The EGAn1 and EGAn0 bits of the ADMn1 register are used to specify the valid edge to be input to the ADTRGn pin. When the ADCEn bit of the ADMn0 register is set to 1, the A/D converter waits for an external trigger (ADTRGn), and starts conversion when the valid edge of ADTRGn is detected (ADCSn bit of the ADMn0 register = 1). When the converter has finished its conversion operation, it waits for an external trigger again (ADCSn bit = 0). If the valid edge is detected at the ADTRGn pin during conversion, conversion is executed from the beginning again. If data is written to the ADMn0 to ADMn2 registers during conversion, conversion is stopped and then executed from the beginning again. (2) Operation mode There are two operation modes that set the ANIn0 to ANIn9 pins: select mode and scan mode. The select mode has sub-modes that consist of 1-buffer mode and 4-buffer mode. These modes are set by the BSn and MSn bits of the ADMn0 register. (a) Select mode In this mode, one analog input specified by the ADMn2 register is A/D converted. The conversion results are stored in the ADCRnm register corresponding to the analog input (ANInm). For this mode, the 1-buffer mode and 4-buffer mode are provided for storing the A/D conversion results (m = 0 to 9). * 1-buffer mode In this mode, one analog input specified by the ADM2 register is A/D converted. The conversion results are stored in the ADCRnm register corresponding to the analog input (ANInm) (m = 0 to 9). The ANInm and ADCRnm register correspond one to one, and an A/D conversion end interrupt (INTADn) is generated each time one A/D conversion ends. After conversion has finished, the next conversion operation is repeated, unless the ADCEn bit of the ADMn0 register is cleared to 0. User's Manual U16580EE3V1UD00 587 Chapter 14 A/D Converter Figure 14-9: Select Mode Operation Timing: 1-Buffer Mode (ANIn1) ANIn1 (input) Data 1 A/D conversion Data 1 (ANIn1) Data 2 Data 3 Data 4 Data 5 Data 2 (ANIn1) Data 3 (ANIn1) Data 4 (ANIn1) Data 5 (ANIn1) Data 1 (ANIn1) ADCRn1 register Data 2 (ANIn1) Data 3 (ANIn1) Data 4 (ANIn1) Data 6 Data 6 (ANIn1) Data 5 (ANIn1) INTADn interrupt Conversion ADCEn bit set start (ADMn0 register setting) ADCEn bit set ADCEn bit set Conversion ADCEn start bit set (ADMn0 register setting) Analog input ADCRnm register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 Remark: 588 ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 Chapter 14 A/D Converter * 4-buffer mode In this mode, one analog input is A/D converted and the results are stored in the ADCRnm registers. The A/D conversion end interrupt (INTADn) is generated when the four A/D conversions end (m = 0 to 3 when one of the analog input channels ANIn0 to ANIn3 is specified, m = 4 to 7 when one of analog input channels ANIn4 to ANIn7 is specified, and m = 8 to 9 when one of the analog input channels ANIn8 or ANIn9 is specified). After conversion has finished, the next conversion operation is repeated, unless the ADCEn bit of the ADM0 register is cleared to 0. Figure 14-10: Select Mode Operation Timing: 4-Buffer Mode (ANIn2) ANIn2 (input) A/D conversion Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 (ANIn2) Data 2 (ANIn2) Data 3 (ANIn2) Data 4 (ANIn2) Data 5 (ANIn2) Data 6 (ANIn2) Data 1 (ANIn2) ADCRn0 Data 2 (ANIn2) ADCRn1 Data 3 (ANIn2) ADCRn2 ADCRnm register Data 4 (ANIn2) ADCRn3 Data 5 (ANIn2) ADCRn0 INTADn interrupt Conversion start (ADMn0 register setting) Conversion start (ADMn0 register setting) Analog input ADCRnm register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 Remark: ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 589 Chapter 14 A/D Converter (b) Scan mode In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRnm register corresponding to the analog input (m = 0 to 9). When the conversion of the specified analog input ends, the A/D conversion end interrupt (INTADn) is generated. After conversion has finished, the next conversion operation is repeated, unless the ADCEn bit of the ADMn0 register is cleared to 0. Figure 14-11: Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3) ANIn0 (input) Data 1 Data 5 ANIn1 (input) Data 6 Data 2 ANIn2 (input) Data 3 ANIn3 (input) Data 4 Data 1 (ANIn0) A/D conversion ADCRnm register Data 2 (ANIn1) Data 3 (ANIn2) Data 4 (ANIn3) Data 1 (ANIn0) ADCR0 Data 2 (ANIn1) ADCR1 Data 3 (ANIn2) ADCR2 Data 5 (ANIn0) Data 4 (ANIn3) ADCR3 Data 6 (ANIn1) Data 5 (ANIn0) ADCR0 INTADn interrupt Conversion start (ADMn0 register setting) Conversion start (ADMn0 register setting) Analog input ADCRnm register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 Remark: 590 ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 Chapter 14 A/D Converter 14.5 Operation in A/D Trigger Mode When the ADCEn bit of the ADMn0 register is set to 1, A/D conversion is started. 14.5.1 Select mode operation In this mode, the analog input specified by the ADMn2 register is A/D converted. The conversion results are stored in the ADCRnm register corresponding to the analog input. In the select mode, the 1-buffer mode and 4-buffer mode are supported according to the storing method of the A/D conversion results (n = 0, 1), (m = 0 to 9). (1) 1-buffer mode (A/D trigger select: 1 buffer) In this mode, one analog input is A/D converted once. The conversion results are stored in one ADCRn register. The analog input and ADCRn register correspond one to one. Each time an A/D conversion is executed, an A/D conversion end interrupt (INTAD) is generated and A/D conversion ends. The next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. Table 14-3: Correspondence Between Analog Input Pins and ADCRnm Register (A/D Trigger Select: 1 Buffer) Analog Input ANInm A/D Conversion Result Register ADCRnm This mode is most appropriate for applications in which the results of each first-time A/D conversion are read. Figure 14-12: ADMn2 Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 <1> <2> <3> <4> Remark: ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 The ADCEn bit of ADMn0 register is set to 1 (enable) ANIn2 is A/D converted The conversion result is stored in ADCRn2 register The INTAD interrupt is generated n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 591 Chapter 14 A/D Converter (2) 4-buffer mode (A/D trigger select: 4 buffers) In this mode, one analog input is A/D converted four times (two times for analog input ANIn8 or ANIn9) and the results are stored in the ADCRnm register. When the 4th A/D conversion ends, an A/D conversion end interrupt (INTADn) is generated and the A/D conversion is stopped. The next conversion operation is repeated, unless the ADCEn bit of the ADMn0 register is cleared to 0. Table 14-4: Correspondence Between Analog Input Pins and ADCRnm Register (A/D Trigger Select: 4 Buffers) Analog Input ANI0 to ANI3 A/D Conversion Result Register ADCRn0 (1st time) ADCRn1 (2nd time) ADCRn2 (3rd time) ADCRn3 (4th time) ANI4 to ANI7 ADCRn4 (1st time) ADCRn5 (2nd time) ADCRn6 (3rd time) ADCRn7 (4th time) ANIn8, ANIn9 ADCRn8 (1st time) ADCRn9 (2nd time) This mode is suitable for applications in which the average of the A/D conversion results is calculated. 592 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-13: ADMn2 A/D Converter Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers) ANIn0 ADCRn0 ANIn1 ADCRn1 ADCRn2 ANIn2 A/D converter (ADCn) ANIn3 ANIn4 (x4) ADCRn3 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2> ANIn3 is A/D converted <3> The conversion result is stored in ADCRn0 register <4> ANIn3 is A/D converted <5> The conversion result is stored in ADCRn1 register <6> ANIn3 is A/D converted <7> The conversion result is stored in ADCRn2 register <8> ANIn3 is A/D converted <9> The conversion result is stored in ADCRn3 register <10> The INTAD interrupt is generated Remark: n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 593 Chapter 14 A/D Converter 14.5.2 Scan mode operations In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRnm register corresponding to the analog input (m = 0 to 9). When conversion of all the specified analog input ends, the A/D conversion end interrupt (INTADn) is generated, and A/D conversion is stopped. The next conversion operation is repeated, unless the ADCEn bit of the ADMn0 register is cleared to 0. Table 14-5: Correspondence Between Analog Input Pins and ADCRnm Register (A/D Trigger Scan) Analog Input ANIn0 A/D Conversion Result Register ADCRn0 ANInmNote ADCRnm Note: Set by the ANISn3 to ANISn0 bits of the ADMn2 register. This mode is most appropriate for applications in which multiple analog inputs are constantly monitored. 594 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-14: ADMn2 A/D Converter Example of Scan Mode Operation (A/D Trigger Scan) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2> ANIn0 is A/D converted <3> The conversion result is stored in ADCRn0 <4> ANIn1 is A/D converted <5> The conversion result is stored in ADCRn1 <6> ANIn2 is A/D converted <7> The conversion result is stored in ADCRn2 <8> ANIn3 is A/D converted <9> The conversion result is stored in ADCRn3 <10> ANIn4 is A/D converted <11> The conversion result is stored in ADCRn4 <12> ANIn5 is A/D converted <13> The conversion result is stored in ADCRn5 <14> The INTAD interrupt is generated Remark: n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 595 Chapter 14 A/D Converter 14.6 Operation in Timer Trigger Mode In this mode, the conversion timing of the analog input signal set by the ANIn0 to ANIn9 pins is defined by a timer event signal (A/D converter trigger signal, or top and bottom reversal interrupt) of the inverter timers R0 and R1 (TMR0, TMR1). The analog input conversion timing is generated when an A/D converter trigger signal from the timers (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1), or a top or bottom reversal interrupt (INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) is generated by inverter timer R0 or R1 (TMR0 or TMR1). When the ADCEn bit of the ADMn0 register is set to 1, the A/D converter waits for the signal (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1) or interrupt (INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD), and starts conversion when the timer event occurs (ADCSn bit of the ADMn0 register = 1). When conversion is finished, the converter waits for a timer event signal again (ADCSn bit = 0). If the timer event signal occurs during conversion, the conversion operation is executed from the beginning again. If data is written to the ADMn0 to ADMn2 registers during conversion, the conversion operation is stopped and executed from the beginning again. 14.6.1 Select mode operation In this mode, an analog input (ANIn0 to ANIn9) specified by the ADMn2 register is A/D converted. The conversion results are stored in the ADCRnm register corresponding to the analog input. In the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storing method of the A/D conversion results. (1) 1-buffer mode operation (timer trigger select: 1 buffer) In this mode, one analog input is A/D converted once and the conversion results are stored in one ADCRnm register. One analog input is A/D converted once using the trigger of the timer event signals (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) and the results are stored in one ADCRnm register. An A/D conversion end interrupt (INTADn) is generated for each A/D conversion. Unless the ADCEn bit of the ADMn0 register is cleared to 0, A/D conversion is repeated each time a timer event signal is generated. 596 User's Manual U16580EE3V1UD00 Chapter 14 Table 14-6: Correspondence Between Analog Input Pins and ADCRnm Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer)) Trigger Analog Input Timer event signal (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) Remark: A/D Converter A/D Conversion Result Register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 n = 0, 1 m = 0 to 9 Figure 14-15: Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (ANIn1) TR0ADTRG0 ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 <1> <2> <3> <4> <5> Remark: ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 The ADCEn bit of ADMn0 register is set to 1 (enable) The TR0ADTRG0 signal is generated ANIn1 is A/D converted The conversion result is stored in ADCRn1 The INTADn interrupt is generated n = 0, 1 User's Manual U16580EE3V1UD00 597 Chapter 14 A/D Converter (2) 4-buffer mode operation (timer trigger select: 4 buffers) In this mode, A/D conversion of one analog input is executed four times, and the results are stored in the ADCRnm register. One analog input is A/D converted four times using the timer event signals (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) as a trigger, and the results are stored in four ADCRnm registers. The A/D conversion end interrupt (INTADn) is generated when the four A/D conversions end. After conversion has finished, the next conversion is repeated when a timer event signal is generated, unless the ADCEn bit of the ADMn0 register is cleared to 0. This mode is suitable for applications in which the average of the A/D conversion results is calculated. Table 14-7: Correspondence Between Analog Input Pins and ADCRnm Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers)) Trigger Analog Input Timer event signal (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) ANI0 to ANI3 A/D Conversion Result Register ADCRn0 (1st time) ADCRn1 (2nd time) ADCRn2 (3rd time) ADCRn3 (4th time) ANI4 to ANI7 ADCRn4 (1st time) ADCRn5 (2nd time) ADCRn6 (3rd time) ADCRn7 (4th time) ANIn8, ANIn9 ADCRn8 (1st time) ADCRn9 (2nd time) Remark: 598 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-16: A/D Converter Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANIn3) TR0ADTRG0 (x4) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 (x4) A/D converter ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2> The TR0ADTRG0 signal is generated <3> ANIn3 is A/D converted <4> The conversion result is stored in ADCR0 <5> ANIn3 is A/D converted <6> The conversion result is stored in ADCR1 <7> ANIn3 is A/D converted <8> The conversion result is stored in ADCR2 <9> ANIn3 is A/D converted <10> The conversion result is stored in ADCR3 <11> The INTADn interrupt is generated Remark: n = 0, 1 User's Manual U16580EE3V1UD00 599 Chapter 14 A/D Converter 14.6.2 Scan mode operation In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin and are A/D converted the specified number of times using the timer event signal as a trigger. The result of conversion is stored in the ADCRnm register corresponding to the analog input. When all the specified analog input signals have been converted, an A/D conversion end interrupt (INTADn) occurs. After conversion has finished, the A/D converter waits for a trigger unless the ADCEn bit of the ADMn0 register is cleared to 0. When a timer event occurs again, the converter starts A/D conversion again, starting from the ANIn0 input. This mode is most appropriate for applications in which multiple analog inputs are constantly monitored. Table 14-8: Remark: 600 Correspondence Between Analog Input Pins and ADCRnm Register (Scan Mode (Timer Trigger Scan)) Trigger Analog Input A/D Conversion Result Register Timer event signal (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-17: TR0ADTRG0 A/D Converter Example of Scan Mode Operation (Timer Trigger Scan) (ANIn0 to ANIn4) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2> The TR0ADTRG0 signal is generated <3> ANIn0 is A/D converted <4> The conversion result is stored in ADCRn0 <5> ANIn1 is A/D converted <6> The conversion result is stored in ADCRn1 <7> ANIn2 is A/D converted <8> The conversion result is stored in ADCRn2 <9> ANIn3 is A/D converted <10> The conversion result is stored in ADCRn3 <11> ANIn4 is A/D converted <12> The conversion result is stored in ADCRn4 <13> The INTADn interrupt is generated Remark: n = 0, 1 User's Manual U16580EE3V1UD00 601 Chapter 14 A/D Converter 14.7 Operation in External Trigger Mode In this mode, the conversion timing of the analog signals input to the ANIn0 to ANIn9 pins is specified by the ADTRGn pin. Detection of the valid edge at the ADTRGn input pin is specified by using the EGAn1 and EGAn0 bits of the ADMn1 register. When the ADCEn bit of the ADMn0 register is set to 1, the A/D converter waits for an external trigger (ADTRGn), and starts conversion when the valid edge of ADTRGn is detected (ADCSn bit of the ADMn0 register = 1). When the converter has ended conversion, it waits for the external trigger again (ADCSn bit = 0). If the valid edge is detected at the ADTRGn pin during conversion, conversion is executed from the beginning again. If data is written to the ADMn0 to ADMn2 registers during conversion, conversion is stopped and executed from the beginning again. 14.7.1 Select mode operations In this mode, one analog input (ANIn0 to ANIn9) specified by the ADMn2 register is A/D converted. The conversion results are stored in the ADCRnm register corresponding to the analog input. In the select mode, there are two select modes: 1-buffer mode and 4-buffer mode, according to the storing method of the conversion results. (1) 1-buffer mode (external trigger select: 1 buffer) In this mode, one analog input is A/D converted using the ADTRGn signal as a trigger. The conversion results are stored in one ADCRnm register. The analog input and the A/D conversion results register correspond one to one. The A/D conversion end interrupt (INTADn) is generated for each A/D conversion, and A/D conversion is stopped. Table 14-9: Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Select: 1 Buffer) Trigger ADTRGn signal Analog Input ANInm A/D Conversion Result Register ADCRnm While the ADCEn bit of the ADMn0 register is 1, A/D conversion is repeated every time a trigger is input from the ADTRGn pin. This mode is most appropriate for applications in which the results are read after each A/D conversion. 602 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-18: A/D Converter Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (ANIn1) ADTRGn ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ANIn3 <1> <2> <3> <4> <5> Remark: ADCRn2 A/D converter (ADCn) ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 The ADCEn bit of ADMn0 is set to 1 (enable) The external trigger is generated ANIn1 is A/D converted The conversion result is stored in ADCRn1 The INTADn interrupt is generated n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 603 Chapter 14 A/D Converter (2) 4-buffer mode (external trigger select: 4 buffers) In this mode, one analog input is A/D converted four times using the ADTRGn signal as a trigger and the results are stored in the ADCRnm register. The A/D conversion end interrupt (INTADn) is generated and A/D conversion is stopped after the 4th A/D conversion. Table 14-10: Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Select: 4 Buffers)) Trigger ADTRGn signal Analog Input ANI0 to ANI3 A/D Conversion Result Register ADCRn0 (1st time) ADCRn1 (2nd time) ADCRn2 (3rd time) ADCRn3 (4th time) ANI4 to ANI7 ADCRn4 (1st time) ADCRn5 (2nd time) ADCRn6 (3rd time) ADCRn7 (4th time) ANIn8, ANIn9 ADCRn8 (1st time) ADCRn9 (2nd time) While the ADCEn bit of the ADMn0 register is 1, A/D conversion is started when a trigger is input from the ADTRGn pin. This mode is suitable for applications in which the average of the A/D conversion results is calculated. 604 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-19: A/D Converter Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (ANIn2) ANIn0 ADTRGn (x4) ANIn1 ANIn2 ANIn3 ANIn4 ADCRn0 ADCRn1 (x4) ADCRn2 A/D converter (ADCn) ADCRn3 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2> The external trigger is generated <3> ANIn3 is A/D converted <4> The conversion result is stored in ADCR0 <5> ANIn3 is A/D converted <6> The conversion result is stored in ADCR1 <7> ANIn3 is A/D converted <8> The conversion result is stored in ADCR2 <9> ANIn3 is A/D converted <10> The conversion result is stored in ADCR3 <11> The INTADn interrupt is generated Remark: n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 605 Chapter 14 A/D Converter 14.7.2 Scan mode operation In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin using the ADTRGn signal as a trigger, and A/D converted. The A/D conversion results are stored in the ADCRnm register corresponding to the analog input ANInm (n = 0, 1)(m = 0 to 9). When conversion of all the specified analog inputs has ended, the A/D conversion end interrupt (INTADn) is generated.n Unless the ADCE bit of the ADMn0 register is cleared to 0 after end of conversion, the A/D converter waits for a trigger. The converter starts A/D conversion from the ANIn0 input when a trigger is input to the ADTRGn pin again. Table 14-11: Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Scan) Trigger ADTRGn signal Analog Input A/D Conversion Result Register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 When a trigger is input to the ADTRGn pin while the ADCEn bit of the ADMn0 register is 1, A/D conversion is started again. This is most appropriate for applications in which multiple analog inputs are constantly monitored. Remark: 606 n = 0, 1 m = 0 to 9 User's Manual U16580EE3V1UD00 Chapter 14 Figure 14-20: ADTRGn A/D Converter Example of Scan Mode Operation (External Trigger Scan) (ANIn0 to ANIn3) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ANIn4 A/D converter (ADCn) ADCRn3 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2> The external trigger is generated <3> ANIn0 is A/D converted <4> The conversion result is stored in ADCRn0 <5> ANIn1 is A/D converted <6> The conversion result is stored in ADCRn1 <7> ANIn2 is A/D converted <8> The conversion result is stored in ADCRn2 <9> ANIn3 is A/D converted <10> The conversion result is stored in ADCRn3 <11> The INTADn interrupt is generated Remark: n = 0, 1 User's Manual U16580EE3V1UD00 607 Chapter 14 A/D Converter 14.8 Precautions (1) Stopping conversion operation When the ADCEn bit of the ADMn0 register is cleared to 0 during a conversion operation, the conversion operation stops and the conversion results are not stored in the ADCRnm register (n = 0, 1), (m = 0 to 9). (2) External/timer trigger interval Set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion time specified by the FRn3 to FRn0 bits of the ADMn1 register. When 0 < interval conversion operation time When the following external trigger or timer trigger is input during a conversion operation, the conversion operation is aborted and the conversion starts according to the last external trigger input or timer trigger input. When conversion operations are aborted, the conversion results are not stored in the ADCRnm register (n = 0, 1) (m = 0 to 9). However, the number of times the trigger has been input is counted. When an interrupt occurs, the values that have been converted are stored in the ADCRnm register. (3) Operation in HALT mode A/D conversion continues in the HALT mode. When this mode is released by NMI input or unmasked maskable interrupt input (see section 8.3.2 (2) "Releasing HALT mode" on page 258), the ADMn0, ADMn1, and ADMn2 registers as well as the ADCRnm register hold the value (n = 0, 1) (m = 0 to 9). (4) Input range of ANIn0 to ANIn9 Use the input voltage at ANIn0 to ANIn9 within the specified range. If a voltage outside the range of AVREF is input to any of these pins (even within the absolute maximum rating range), the converted value of the channel is undefined. In addition, the converted value of the other channels may also be affected. (5) Conflicts (a) Conflict between writing A/D conversion result registers (ADCRnm, ADCRnmH) at end of conversion and reading ADCRnm and ADCRnmH registers by instruction Reading the ADCRnm and ADCRnmH registers takes precedence. After these registers have been read, the new conversion result is written to the ADCRnm and ADCRnmH registers. (b) Conflict between writing ADCRnm and ADCRnmH at end of conversion and input of external trigger signal The external trigger signal is not accepted during A/D conversion. Therefore, it is not accepted while ADCRnm and ADCRnmH are being written. (c) Conflict between writing ADCRnm and ADCRnmH at end of conversion and writing ADMn1 or ADMn2 register If ADMn1 or ADMn2 register is written immediately after ADCRnm and ADCRnmH have been written on completion of A/D conversion, the conversion result is written to the ADCRnm and ADCRnmH registers, but the A/D conversion end interrupt (INTADn) may not occur depending on the timing. 608 User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.1 Features * Transfer speed: 16 bps to 2000 kbps * Full-duplex communication: Internal UARTC receive data register n (UCnRX) Internal UARTC transmit data register n (UCnTX) * 2-pin configuration: TXDCn: Transmit data output pin RXDCn: Receive data input pin * Receive error output function - Parity error - Framing error - Overrun error * Interrupt sources: 3 - Receive error interrupt (INTUCnRE) - Reception complete interrupt (INTUCnR) - Transmission enable interrupt (INTUCnT) * Character length: 7, 8 bits * Parity function: Odd, even, 0, none * Transmission stop bit: 1, 2 bits * On-chip dedicated baud rate generator * MSB/LSB-first transfer selectable * Transmit/receive data level inversion possible * 13 to 20 bits selectable for the SBF (Sync Break Field) in the LIN (Local Interconnect Network) communication format * Recognition of 11 bits or more possible for SBF reception in LIN communication format * SBF reception flag provided * Extension bit operation possible (uses parity bit as 9th data bit) * Transfer and reception status flags Remark: n = 0, 1 User's Manual U16580EE3V1UD00 609 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.2 Configuration (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register used to specify the asynchronous serial interface operation. (2) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register used to select the input clock for the asynchronous serial interface. (3) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register used to control the baud rate for the asynchronous serial interface. (4) UARTCn option control register 0 (UCnOPT0) The UCnOPT0 register is an 8-bit register used to control serial transfer for the asynchronous serial interface. (5) UARTCn option control register 1 (UCnOPT1) The UCnOPT1 register is an 8-bit register used to control the extension bit operation. (6) UARTCn status register (UCnSTR) The UCnSTR register consists of flags indicating the error contents when a reception error occurs. Each one of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the UCnSTR register. (7) UARTCn status register 1 (UCnSTR1) The UCnSTR1 register indicates the operating status during a reception. (8) UARTCn receive shift register This is a shift register used to convert the serial data input to the RXDCn pin into parallel data. Upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the UCnRX register. This register cannot be manipulated directly. (9) UARTCn receive data register (UCnRX) The UCnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the highest bit (when LSB first received). In the reception enabled status, receive data is transferred from the UARTCn receive shift register to the UCnRX register in synchronization with the completion of shift-in processing of 1 frame. Transfer to the UCnRX register also causes reception complete interrupt (INTUCnR) to be output. (10) UARTCn transmit shift register The transmit shift register is a shift register used to convert the parallel data transferred from the UCnTX register into serial data. When 1 byte of data is transferred from the UCnTX register, the shift register data is output from the TXDCn pin. This register cannot be manipulated directly. 610 User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) (11) UARTCn transmit data register (UCnTX) The UCnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UCnTX register. When data can be written to the UCnTX register (when data of one frame is transferred from the UCnTX register to the UARTCn transmit shift register), the transmission enable interrupt (INUCnT) is generated. Figure 15-1: Block Diagram of Asynchronous Serial Interface n Internal bus INTUCnT INTUCnR INTUCnRE UCnRX Transmission unit UCnTX Receive shift register Reception controller Transmission controller Transmit shift register Filter Baud rate generator Baud rate generator Selector TXDCn RXDCn Selector Clock selector fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXX/2048 fXX/8192 Reception unit UCnCTL1 UCnCTL2 UCnCTL0 UCnSTR UCnSTR1 UCnOTP0 UCnOTP1 Internal bus Remarks: 1. n = 0, 1 2. fXX: Internal system clock User's Manual U16580EE3V1UD00 611 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.3 Control Registers (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 10H. Caution: Be sure to set the UCnPWR bit = 1 and the UCnRXE bit = 1 while the RXDCn pin is high level (when UCnRDL bit of UCnOP0 register = 0). If the UCnPWR bit = 1 and the UCnRXE bit = 1 are set while the RXDCn pin is low level, reception will inadvertently start. Figure 15-2: After reset: 10H 7 UCnCTL0 UARTCn Control Register 0 (UCnCTL0) (1/2) R/W 6 UCnPWR UCnTXE Address: UC0CTL0 FFFFFA00H, UC1CTL0 FFFFFA20H 5 4 3 2 1 0 UCnRXE UCnDIR UCnPS1 UCnPS0 UCnCL UCnSL (n = 0, 1) UCnPWR UARTCn Operation Control 0 Stops clock operation (UARTCn reset asynchronously) 1 Enables operating clock operation Operating clock control and UARTCn asynchronous reset are performed with the UCnPWR bit. The TXDCn pin output is fixed to high level by setting the UCnPWR bit to 0. UCnTXE Transmission Operation Enable 0 Stops transmission operation 1 Enables transmission operation * The TXDCn pin output is fixed to high level by setting the UCnPWR bit to 0. Since the UCnTXE bit is initialized by the operating clock, to initialize the transmission unit, set UCnTXE from 0 to 1, and 2 clocks later, the transmission enabled status is entered. * When UCnPWR bit = 0, the value written to the UCnTXE bit is ignored. UCnRXE Reception Operation Enable 0 Stops reception operation 1 Enables reception operation * The receive operation is stopped by setting the UCnRXE bit to 0. Therefore, even if the prescribed data is transferred, no reception completion interrupt is output and the UARTCn reception data register (UCnRX) is not updated. Since the UCnRXE bit is synchronized using the operating clock, to initialize the reception unit, set UCnRXE from 0 to 1, and 2 clocks later, the reception enabled status is entered. * When UCnPWR bit = 0, the value written to the UCnRXE bit is ignored. 612 User's Manual U16580EE3V1UD00 Chapter 15 Figure 15-2: Asynchronous Serial Interface C (UARTC) UARTCn Control Register 0 (UCnCTL0) (2/2) UCnDIR Transfer Direction Selection 0 MSB-first transfer 1 LSB-first transfer This bit can be rewritten only when UCnPWR bit = 0 or UCnTXE bit = UCnRXE bit = 0. UCnPS1 UCnPS0 Parity Selection During Transmission During Reception 0 0 No parity output Reception with no parity 0 1 0 parity output Reception with 0 parity 1 0 Odd parity output Odd parity check 1 1 Even parity output Even parity check * These bits can be rewritten only when UCnPWR bit = 0 or UCnTXE bit = UCnRXE bit = 0. * If "Reception with 0 parity" is selected during reception, a parity check is not performed. Therefore, since the UCnPE bit of the UCnSTA0 register is not set, no error interrupt is output. * When transmission and reception are performed in the LIN format, set the UCnPS1 and UCnPS0 bits to 00B. UCnCL Data Character Length Specification 0 7 bits 1 8 bits This bit can be rewritten only when UCnPWR bit = 0 or UCnTXE bit = UCnRXE bit = 0. UCnSL Stop Bit Length Specification 0 1 bit 1 2 bits This bit can be rewritten only when UCnPWR bit = 0 or UCnTXE bit = UCnRXE bit = 0. Remark: For details of parity, see 15.5.9 "Parity types and operations" on page 637. User's Manual U16580EE3V1UD00 613 Chapter 15 (2) Asynchronous Serial Interface C (UARTC) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register that selects the UARTCn base clock (fXCLK). This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 15-3: After reset: UCnCTL1 00H UARTCn Control Register 1 (UCnCTL1) R/W Address: 7 6 5 4 0 0 0 0 UC0CTL1 FFFFFA01H, UC1CTL1 FFFFFA21H 3 2 1 UCnCKS3 UCnCKS2 UCnCKS1 UCnCKS0 (n = 0, 1) Base clock (fXCLK) selection UCnCKS3 UCnCKS2 UCnCKS1 UCnCKS0 Remark: 614 0 0 0 0 0 fXX/2 0 0 0 1 fXX/4 0 0 1 0 fXX/8 0 0 1 1 fXX/16 0 1 0 0 fXX/32 0 1 0 1 fXX/64 0 1 1 0 fXX/128 0 1 1 1 fXX/256 1 - 0 0 fXX/512 1 - 0 1 fXX/1024 1 - 1 0 fXX/2048 1 - 1 1 fXX/8192 fXX: Internal system clock User's Manual U16580EE3V1UD00 Chapter 15 (3) Asynchronous Serial Interface C (UARTC) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register that specifies the divisor to control the baud rate (serial transfer speed) clock of UARTCn. This register can be read or written in 8-bit units. Reset input sets this register to FFH. Figure 15-4: After reset: UCnCTL2 FFH UARTCn Control Register 2 (UCnCTL2) R/W Address: UC0CTL2 FFFFFA02H, UC1CTL2 FFFFFA22H 7 6 5 4 3 2 1 0 UCnBRS7 UCnBRS6 UCnBRS5 UCnBRS4 UCnBRS3 UCnBRS2 UCnBRS1 UCnBRS0 (n = 0, 1) UCn UCn UCn UCn UCn UCn UCn UCn Default BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRS0 (k) Remark: Serial clock 0 0 0 0 0 0 - - - Setting prohibited 0 0 0 0 0 1 0 0 4 fXCLK/4 0 0 0 0 0 1 0 1 5 fXCLK/5 0 0 0 0 0 1 1 0 6 fXCLK/6 : : : : : : : : : : 1 1 1 1 1 1 0 0 252 fXCLK/252 1 1 1 1 1 1 0 1 253 fXCLK/253 1 1 1 1 1 1 1 0 254 fXCLK/254 1 1 1 1 1 1 1 1 255 fXCLK/255 fXCLK: Clock frequency selected by the UCnCKS3 to UCnCKS0 bits of the UCnCTL1 register User's Manual U16580EE3V1UD00 615 Chapter 15 (4) Asynchronous Serial Interface C (UARTC) UARTCn option control register 0 (UCnOPT0) The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 14H. Figure 15-5: After reset: UCnOPT0 UARTCn Option Control Register 0 (UCnOPT0) (1/2) 14H R/W 7 6 UCnSRF UCnSRT Address: 5 4 UC0OPT0 FFFFFA03H, UC1OPT0 FFFFFA23H 3 2 1 UCnSTT UCnSLS2 UCnSLS1 UCnSLS0 UCnTDL 0 UCnRDL (n = 0, 1) UCnSRF SBF Reception Flag 0 When UCnPWR of UCnCTL0 register = 0 and UCnRXE of UCnCTL0 register = 0 are set. Also upon normal end of SBF reception. 1 During SBF reception * SBF (Sync Brake Field) reception is judged during LIN communication. * The UCnSRF bit is held high when a SBF reception error occurs, and then SBF reception is started again. UCnSRT SBF Reception Trigger 0 - 1 SBF reception trigger * This is the SBF reception trigger bit during LIN communication, and when read, "0" is always read. For SBF reception, set the UCnSRT bit (to 1) to enable reception. * Set the UCnSRT bit after setting the UCnPWR bit of the UCnCTL0 register to 1 and the UCnRXE bit of the UCnCTL0 register to 1. UCnSTT SBF Transmission Trigger 0 - 1 SBF transmission trigger * This is the SBF transmission trigger bit during LIN communication, and when read, "0" is always read. * Set the UCnSRT bit after setting the UCnPWR bit of the UCnCTL0 register to 1 and the UCnRXE bit of the UCnCTL0 register to 1. 616 User's Manual U16580EE3V1UD00 Chapter 15 Figure 15-5: Asynchronous Serial Interface C (UARTC) UARTCn Option Control Register 0 (UCnOPT0) (2/2) UCnSLS2 UCnSLS1 UCnSLS0 SBF Length Selection 1 0 1 13-bit output (reset value) 1 0 0 14-bit output 1 1 1 15-bit output 0 1 0 16-bit output 0 0 1 17-bit output 0 0 0 18-bit output 0 1 1 19-bit output 1 1 0 20-bit output This register can be set when the UCnPWR bit of the UCnCTL0 register is 0 or when the UCnRXE bit of the UCnCTL0 register is 0. UCnTDL Transmit Data Level 0 Normal output of transfer data 1 Inverted output of transfer data * The value of the TXDCn pin can be inverted using the UCnTDL bit. * This bit can be set when the UCnPWR bit of the UCnCTL0 register is 0 or when the UCnTXE bit of the UCnCTL0 register is 0. UCnRDL Receive Data Level 0 Normal input of transfer data 1 Inverted input of transfer data * The value of the RXDCn pin can be inverted using the UCnRDL bit. * This bit can be set when the UCnPWR bit of the UCnCTL0 register is 0 or the UCnRXE bit of the UCnCTL0 register is 0. User's Manual U16580EE3V1UD00 617 Chapter 15 (5) Asynchronous Serial Interface C (UARTC) UARTCn option control register 1 (UCnOPT1) The UCnOPT1 register is an 8-bit register that controls the extension bit operation of the UARTCn. The register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 15-6: After reset: UCnOPT1 00H UARTCn Option Control Register 1 (UCnOPT1) R/W Address: UC0OPT1 FFFFFA0AH, UC1OPT1 FFFFFA2AH 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 UCnEBE (n = 0, 1) UCnEBE Extension Bit Operation Enable 0 Extension bit operation disabled. Transfer data length set by UCnCL bit of the UCnCTL0 register. 1 Extension bit operation enabled. * During extension bit operation a 9-th data bit is sent or received instead of the parity bit. * Extension bit operation is only effective when the parity selection is set to no parity (UCnPS1, UCnPS0 bits = 00B), and the character length is set to 8 bits (UCnCL bit = 1). In all other cases the setting of UCnEBE bit is ignored. 618 User's Manual U16580EE3V1UD00 Chapter 15 Table 15-1: Asynchronous Serial Interface C (UARTC) Relation between UARTCn Register Settings and Data Format Register Bit Settings UCnEBE UCnPS1 UCnPS0 0 0 0 other than 00B 1 0 0 other than 00B Data Format UCnCL UCnSL D0 - D6 D7 D8 D9 0 0 Data Stop 0 1 Data Stop Stop 1 0 Data Data Stop 1 1 Data Data Stop 0 0 Data Parity Stop 0 1 Data Parity Stop Stop 1 0 Data Data Parity Stop 1 1 Data Data Parity Stop 0 0 Data Stop 0 1 Data Stop Stop 1 0 Data Data DataNote Stop 1 1 Data Data DataNote Stop 0 0 Data Parity Stop 0 1 Data Parity Stop Stop 1 0 Data Data Parity Stop 1 1 Data Data Parity Stop D10 Stop Stop Stop Stop Note: Insertion of extension bit User's Manual U16580EE3V1UD00 619 Chapter 15 (6) Asynchronous Serial Interface C (UARTC) UARTCn status register (UCnSTR) The UCnSTR register is an 8-bit register that displays the UARTCn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UCnTSF bit is a read-only bit, while the UCnPE, UCnFE, and UCnOVE bits can both be read and written. However, these bits can only be cleared by writing 0 and they cannot be set by writing 1. (If 1 is written to them, the hold status is entered.) The initialization conditions are shown below. Register/Bit UCnSTR register Reset input UCnPWR bit of UCnCTL0 register = 0 UCnTSF bit UCnTXE bit of UCnCTL0 register = 0 UCnPE, UCnFE, UCnOVE bits 0 write UCnRXE bit of UCnCTL0 register = 0 Figure 15-7: After reset: UCnSTR Initialization Conditions 00H UARTCn Status Register (UCnSTR) (1/2) R/W Address: UC0STR FFFFFA04H, UC1STR FFFFFA24H 7 6 5 4 3 2 1 0 UCnTSF 0 0 0 0 UCnPE UCnFE UCnOVE (n = 0, 1) UCnTSF Transfer Status Flag 0 * When UCnPWR bit of UCnCTL0 register = 0 or UCnTXE bit of UCnCTL0 register = 0 has been set. * When, following transfer completion, there was no next data transfer from UCnTX 1 Write to UCnTXB bit The UCnTSF bit is always 1 when performing continuous transmission. When initializing the transmission unit, check that the UCnTSF bit = 0 before performing initialization. The transmit data is not guaranteed when initialization is performed while UCnTSF bit = 1. UCnPE Parity Error Flag 0 * When UCnPWR bit of UCnCTL0 register = 0 or UCnRXE bit of UCnCTL0 register = 0 has been set. * When 0 has been written 1 * When parity of data and parity bit do not match during reception. * The operation of the UCnPE bit is controlled by the settings of the UCnPS1 and UCnPS0 bits of the UCnCTL0 register. * The UCnPE bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the hold status is entered. 620 User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-7: UCnFE UARTCn Status Register (UCnSTR) (2/2) Framing Error Flag 0 * When UCnPWR bit of UCnCTL0 register = 0 or UCnRXE bit of UCnCTL0 register = 0 has been set * When 0 has been written 1 When no stop bit is detected during reception * Only the first bit of the receive data stop bits is checked, regardless of the value of the UCnSL bit of the UCnCTL0 register. * The UCnFE bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the hold status is entered. UCnOVE Overrun Error Flag 0 * When UCnPWR bit of UCnCTL0 register = 0 or UCnRXE bit of UCnCTL0 register = 0 has been set. * When 0 has been written 1 When receive data has been set to the UCnRXB register and the next receive operation is completed before that receive data has been read * When an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. * The UCnOVE bit can be both read and written, but it can only be cleared by writing 0 to it. When 1 is written to this bit, the hold status is entered. User's Manual U16580EE3V1UD00 621 Chapter 15 (7) Asynchronous Serial Interface C (UARTC) UARTCn status register 1 (UCnSTR1) The UCnSTR1 register is an 8-bit register that displays the UARTCn reception status. The register is read only, and be read in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 15-8: After reset: UCnSTR1 00H UARTCn Status Register 1 (UCnSTR1) R Address: UC0STR1 FFFFFA0BH, UC1STR1 FFFFFA2BH 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 UCnRSF (n = 0, 1) UCnRSF Receive Status Flag 0 * When UCnPWR bit of UCnCTL0 register = 0 or UCnRXE bit of UCnCTL0 register = 0 has been set. * When the stop bit has been detected. 1 During reception, when the start bit has been detected. The UCnRSF flag is set (1) by the start bit detection, and it is cleared (0) by detection of the first stop bit condition. In case of a two stop bit setting (UCnSL bit of UCnCTL0 register = 1), the UCnRSF flag is cleared during the first stop bit timing, simultaneously with the reception complete interrupt timing (INTUCnR) 622 User's Manual U16580EE3V1UD00 Chapter 15 (8) Asynchronous Serial Interface C (UARTC) UARTCn receive data register (UCnRX, UCnRXL) The UCnRX register is a 16-bit buffer register that stores parallel data converted by receive shift register. It is overlayed by an 8-bit register UCnRXL on the lower 8 bits, which stores the lower byte of the received data. The data stored in the receive shift register is transferred to the UCnRX register upon completion of reception of one data frame. When extension bit operation is enabled (UCnEBE bit of UCnOPT1 register = 1) the 9th data bit is received in bit 8 of the UCnRX register. When the extension bit operation is disabled (UCnEBE bit = 0) the data bits are received in the lower byte of the UCnRX register. The lower byte can be read also by 8-bit access of the UCnRXL register. During LSB-first reception when the data length has been specified as 7 bits and th extension bit operation is disabled, the receive data is transferred to bits 6 to 0 of the UXnRXL register and the MSB always becomes 0. During MSB-first reception, the receive data is transferred to bits 7 to 1 of the UCnRXL register and the LSB always becomes 0. When an overrun error (UCnOVE bit = 1) occurs, the receive data at this time is not transferred to the UCnRX and UXnRXL register respectively. The UCnRX register is read-only, in 16-bit units. The UCnRXL register is read-only, in 8-bit units. In addition to reset input, the UCnRX register can be set to 1FFH, and the UCnRXL register can be set to FFH respectively, by clearing the UCnPWR bit of the UCnCTL0 register to 0. Figure 15-9: After reset: UCnRX UARTCn Receive Data Register (UCnRX, UCnRXL) 1FFH R Address: 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 UC0RX FFFFFA06H, UC1RX FFFFFA26H 7 6 5 4 3 2 1 0 (n = 0, 1) UCnRXL After reset: FFH 7 R 6 Address: 5 4 UC0RXL FFFFFA06H, UC1RXL FFFFFA26H 3 2 1 0 UCnRXL (n = 0, 1) User's Manual U16580EE3V1UD00 623 Chapter 15 (9) Asynchronous Serial Interface C (UARTC) UARTCn transmit data register (UCnTX, UCnTXL) The UCnTX register is a 16-bit buffer register used to set transmit data. It is overlayed by an 8-bit register UCnTXL on the lower 8 bits. The UCnTXL register is used for setting the transmit data when 7-bit or 8-bit data character length is specified (UCnEBE bit = 0). The UCnTX register can be read or written in 16-bit units. The UCnTXL register can be read or written in 8-bit units. Reset input sets the UCnTX register to 1FFH, and the UCnTXL register to FFH. Figure 15-10: After reset: UCnTX UARTCn Transmit Data Register (UCnTX, UCnTXL) 1FFH R/W Address: 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 UC0TX FFFFFA08H, UC1TX FFFFFA28H 7 6 5 4 3 2 1 0 (n = 0, 1) UCnTXL After reset: FFH 7 R/W 6 Address: 5 4 UC0TXL FFFFFA08H, UC1TXL FFFFFA28H 3 UCnTXL (n = 0, 1) 624 User's Manual U16580EE3V1UD00 2 1 0 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.4 Interrupt Requests The following three interrupt requests are generated from UARTCn. * Receive error interrupt (INTUCnRE) * Reception complete interrupt (INTUCnR) * Transmission enable interrupt (INTUCnT) The default priority for these three interrupt requests is highest for the receive error interrupt, followed by the reception complete interrupt, and the transmission enable interrupt. Table 15-2: Default Priorities of UARTCn Interrupts Interrupt Receive error (INTUCnRE) (1) Priority High Reception complete (INTUCnR) Transmission enable (INTUCnT) Low Receive error interrupt (INTUCnRE) A receive error interrupt is generated when one or more of the three types of receive errors (parity error, framing error, or overrun error) occur. (refer to 15.3 (6) UARTCn status register (UCnSTR)) (2) Reception complete interrupt (INTUCnR) A reception complete interrupt is output when data is shifted into the UARTCn receive shift register and transferred to the UCnRX register in the reception enabled status. A reception complete interrupt will not be generated when a reception error has occurred. No reception complete interrupt is generated in the reception disabled status. (3) Transmission enable interrupt (INTUCnT) A transmission enable interrupt is generated when transmit data is transferred from the UCnTX register to the UARTCn transmit shift register in the transmission enabled status. User's Manual U16580EE3V1UD00 625 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5 Operation 15.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-11, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UCnCTL0 register. UARTCn features additionally the extension bit operation for a ninth transfer data bit, which can be specified in the UCnOPT1 register. Moreover, control of UART output/inverted output for the TXDCn bit is performed using the UCnTDL bit of the UCnOPT0 register. * Start bit 1 bit * Character bits 7 bits/8 bits/9 bits * Parity bit Even parity/odd parity/0 parity/no parityNote * Stop bit 1 bit/2 bits Note: Extension bit operation presumes no parity setting. Figure 15-11: UARTC Transmit/Receive Data Format (1/2) (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDCn inversion 1 data frame Start bit 626 D7 D6 D5 D4 D3 D2 D1 D0 User's Manual U16580EE3V1UD00 Parity Stop bit bit Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-11: UARTC Transmit/Receive Data Format (2/2) (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop bit bit bit (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit (f) 9-bit data length, LSB first, no parity, 1 stop bit, transfer data: 155H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 User's Manual U16580EE3V1UD00 D8 Stop bit 627 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.2 SBF transmission/reception format The UARTC has a SBF (Sync Break Field) transmission/reception control function to enable use of the LIN (Local Interconnect Network) function. Figure 15-12: Wake-up signal frame LIN Transmission Manipulation Outline Synch break field Synch field Note 2 13 bits 55H transmission DATA field DATA field Check SUM field Data transmission Data transmission Data transmission Ident field Sleep bus Note 3 8 bits Note 1 Data transmission TXDCn (output) SBF transmissionNote 4 INTUCnR interrupt Notes: 1. The interval between each field is controlled by software. 2. SBF output is performed by hardware. The output width is the bit length set by bits UCnSBL2 to UCnSBL0 of the UCnOPT0 register. If even finer output width adjustments are required, such adjustments can be performed using bits UCnBRS7 to UCnBRS0 of the UCnCTLn register. 3. 80H transfer in the 8-bit mode is substituted for the wake-up signal frame. 4. A transmission enable interrupt (INTUCnT) is output at the start of each transmission. The INTUCnT signal is also output at the start of each SBF transmission. 628 User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-13: Wake-up signal frame LIN Reception Manipulation Outline Synch break field Synch field Ident field DATA field Note 2 13 bits SF reception ID reception Data transmission DATA field Check SUM field Sleep bus TXDCn (output) Disable Enable Data Note 5 transmission Data transmission SBF reception Note 3 Reception interrupt (INTUCnR) Note 1 Edge detection Note 4 Capture timer Disable Enable Notes: 1. The wakeup signal is sent by the pin edge detector, UARTC is enabled, and the SBF reception mode is set. 2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon detection of SBF reception of less than 11 bits, a SBF reception error is judged, no interrupt signal is output, and the mode returns to the SBF reception mode. 3. If SBF reception ends normally, an interrupt signal is output. The timer is enabled by a SBF reception complete interrupt. Moreover, error detection for the UCnOVE, UCnPE, and UCnFE bits of the UCnSTR register is suppressed and UART communication error detection processing and UARTCn receive shift register and data transfer of the UCnRX register are not performed. The UARTCn receive shift register holds the initial value, FFH. 4. The RXDCn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. The value of the UCnCTL2 register obtained by compensating the baud rate error after dropping UARTC enable is set again, causing the status to become the reception status. 5. Check-sum field distinctions are made by software. The UARTC is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. User's Manual U16580EE3V1UD00 629 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.3 SBF transmit operation When the UCnPWR bit = the UCnTXE bit of the UCnCTL0 register = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UCnSTT bit of UCnOPT0 register). Thereafter, a low-level width of bits 13 to 20 specified by the UCnSLS2 to UCnSLS0 bits of the UCnOPT0 register is output. A transmission enable interrupt (INTUCnT) is generated upon SBF transmission start. Following the end of SBF transmission, the UCnSTT bit is automatically cleared. Thereafter, the UART transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to the UCnTX register, or until the SBF transmission trigger (UCnSTT bit) is set. Figure 15-14: 1 2 3 4 SBF Transmission Timing 5 6 7 8 9 10 INTUCnT interrupt Setting of UCnSTT bit 630 User's Manual U16580EE3V1UD00 11 12 13 Stop bit Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.4 SBF receive operation The reception enabled status is achieved by setting the UCnPWR bit of the UCnCTL0 register to 1 and then setting the UCnRX bit of the UCnCTL0 register to 1. The SBF reception wait status is set by setting the SBF reception trigger (UCnSRT bit of the UCnOPT0 register) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start bit detection is performed. Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception complete interrupt (INTUCnR) is output. Error detection for the UCnOVE, UCnPE, and UCnFE bits of the UCnSTR register is suppressed and UART communication error detection processing is not performed. Moreover, UARTCn reception shift register and data transfer of the UCnRX register are not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to. The UCnSRF bit is not cleared at this time. Figure 15-15: SBF Reception Timing (a) Normal SBF reception (detection of stop bit in more than 10.5 bits) 1 2 3 4 5 6 7 8 9 10 11 11.5 UCnSRF INTUCnR interrupt (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) 1 2 3 4 5 6 7 8 9 10 10.5 UCnSRF INTUCnR interrupt User's Manual U16580EE3V1UD00 631 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.5 UART transmit operation The transmission enabled status is set by setting the UCnTXE bit of the UCnCTL0 register to 1, after UCnPWR bit was set to 1, and transmission is started by writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added. The data in the UCnTX register is transferred to the UARTCn transmit shift register upon the start of the transmit operation. A transmission enable interrupt (INTUCnT) is generated upon completion of transmission of the data of the UCnTX register to the UARTCn transmit shift register, and thereafter the contents of the UARTCn transmit shift register are output to the TXDCn pin LSB first. Write of the next transmit data to the UCnTX register is enabled by generating the INTUCnT signal. Continuous transmission is enabled by writing the data to be transmitted next to the UCnTX register during transfer. Start bit Figure 15-16: UART Transmission D0 D3 D1 D2 D4 D5 D6 D7 Parity Stop bit bit INTUCnT Remark: 632 If new data is written to the UCnTX register due to a transmission enable interrupt (INTUCnT) before the complete frame has been transferred, the next transmission enable interrupt occurs at that time the stop bit begins. User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.6 Continuous transmit operation UARTCn can write the next transmit data to the UCnTX register when the UARTCn transmit shift register starts the shift operation. The transfer timing of the UARTCn transmit shift register can be judged from the transmission enable interrupt (INTUCnT). Transmission can be performed without interruption even during interrupt processing following the transmission of 1 data frame via the INTUCnT signal, and an efficient communication rate can thus be achieved. During continuous transmission, overrun (the completion of the next transmission before the first transmission completion processing has been executed) may occur. An overrun can be detected by incorporating a program that can count the number of transmit data and by referencing transfer status flag (UCnTSF bit of UCnSTR register). Caution: During continuous transmission execution, perform initialization after checking that the UCnTSF bit is 0. The transmit data cannot be guaranteed when initialization is performed when the UCnTSF bit is 1. Figure 15-17: Continuous Transmission Processing Flow Start Register settings UCnTX write Occurrence of transmission interrupt? No Yes Required number of writes performed? No Yes End User's Manual U16580EE3V1UD00 633 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-18: Continuous Transfer Operation Timing (a) Transmission start Start TXDCn UCnTX Data (1) Parity Start Data (2) Parity Data (2) Data (1) Transmission shift register Stop Stop Start Data (3) Data (2) Data (1) INTUCnT UCnTSF (b) Transmission end TXDCn UCnTX Transmission shift register Parity Stop Start Data (n - 1) Data (n - 1) Parity Stop Start Parity Stop Data (n) Data (n - 1) Data (n) INTUCnT UCnTSF UCnPWR or UCnTXE 634 Data (n) User's Manual U16580EE3V1UD00 FF Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.7 UART receive operation The reception wait status is set by setting the UCnPWR bit of the UCnCTL0 register to 1 and then setting the UCnRX bit of the UCnCTL0 register to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine. First, an 8-bit counter starts upon detection of the falling edge of the RXDCn pin. When the 8-bit counter has counted the UCnCTL2 register setting value, the level of the RXDCn pin is monitored again (corresponds to the mark in Figure 15-19). If the RXDCn pin is low level at this time too, a start bit is recognized. After a start bit has been recognized, the receive operation starts, and serial data is saved to the UARTCn receive shift register according to the set baud rate. Additionally the UCnRSF flag of UCnSTR1 register is set (1) to indicate the receive operation status. When the reception complete interrupt (INTUCnR) is output upon reception of the stop bit, the data of the UARTCn receive shift register is written to the UCnRX register, and the UCnRSF flag is cleared (0) simultaneously. However, if an overrun error occurs (UCnOVE bit = 1), the receive data at this time is not written to the UCnRX register, and a reception error interrupt (INTUCnRE) is output. Even if a parity error (UCnPE bit = 1) or a framing error (UCnFE bit = 1) occurs during reception, reception continues until the stop bit reception position, but a reception error interrupt (INTUCnRE) is output following reception completion. Figure 15-19: Start bit D0 D1 D2 UART Reception Timing D3 D4 D5 D6 D7 Parity Stop bit bit INTUCnR UCnRX UCnRSF Cautions: 1. Be sure to read the UCnRX register even when a reception error occurs. If the UCnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. The operation during reception is performed assuming that there is only one stop bit. A second stop bit is ignored. User's Manual U16580EE3V1UD00 635 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.8 Receive error Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. A data reception result error flag is set to the UCnSTR register and a reception error interrupt (INTUCnRE) is output. During reception error interrupt processing, it is possible to ascertain which error occurred during reception by reading the contents of the UCnSTR register. The reception error flag is cleared by writing 0 to it. Table 15-3: Error Flag Reception Error Causes Reception Error Cause UCnPE Parity error Received parity bit does not match the setting UCnFE Framing error Stop bit not detected UCnOVE Overrun error Reception of next data completed before data was read from receive buffer Cautions: 1. In case of a reception error the reception complete interrupt (INTUCnR) is not generated. Instead of this a reception error interrupt (INTUCnRE) can be received. 2. Be sure to read the UCnRX register even when a reception error occurs. If the UCnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 636 User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.9 Parity types and operations Caution: When using the LIN function, fix the UCnPS1 and UCnPS0 bits of the UCnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect "1" bit errors (odd count). In the case of 0 parity and no parity, errors cannot be detected. (1) Even parity (a) During transmission The number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so as to be an even number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 1 * Even number of bits whose value is "1" among transmit data: 0 (b) During reception The number of bits whose value is "1" among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (2) Odd parity (a) During transmission Opposite to even parity, the number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so that it is an odd number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 0 * Even number of bits whose value is "1" among transmit data: 1 (b) During reception The number of bits whose value is "1" among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (3) 0 parity During transmission, the parity bit is always made 0, regardless of the transmit data. During reception, parity bit check is not performed. Therefore, no parity error is generated, regardless of whether the parity bit is 0 or 1. (4) No parity No parity bit is added to the transmit data. Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit. User's Manual U16580EE3V1UD00 637 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.10 Receive data noise filter This filter performs the RXDCn pin sampling using the internal system clock (fXX/2). When the same sampling value is read twice, the match detector output changes and sampling as the input data is performed. Moreover, since the circuit is as shown in Figure 15-20, the processing that goes on within the receive operation is delayed by 2 clocks in relation to the external signal status. Figure 15-20: Noise Filter Circuit fXX/2 RXDCn In Q I Match detector 638 n Q LD_EN User's Manual U16580EE3V1UD00 Receive data signal Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6 Dedicated Baud Rate Generator 15.6.1 Baud rate generator configuration The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. There is an 8-bit counter for transmission and another one for reception. Figure 15-21: Configuration of Baud Rate Generator UCnPWR fXX/2 fXX/4 fXX/8 UCnPWR, UCnTXEn (or UCnRXE) fXX/16 fXX/32 fXX/64 Selector fXX/128 Clock 8-bit counter (fXCLK) fXX/256 fXX/512 fXX/1024 fXX/2048 Match detector fXX/8192 UCnCTL1: UCnCKS3 to UCnCKS0 1/2 Baud rate UCnCTL2: UCnBRS7 to UCnBRS0 Remarks: 1. n = 0, 1 2. fXX: Internal system clock (1) Base clock (Clock) When the UCnPWR bit of the UCnCTL0 register is 1, the clock selected by bits UCnCKS3 to UCnCKS0 of the UCnCTL1 register is supplied to the 8-bit counter. This clock is called the base clock (Clock) and its frequency is called fXCLK. When the UCnPWR bit = 0, the clock is fixed to the low level. (2) Serial clock generation A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register (n = 0, 1). The base clock is selected by UCnCKS3 to UCnCKS0 bits of the UCnCTL1 register. The frequency division value for the 8-bit counter can be set using bits UCnBRS7 to UCnBRS0 of the UCnCTL2 register. User's Manual U16580EE3V1UD00 639 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.2 Baud rate The baud rate is obtained by the following equation. Baud rate = fXCLK 2xk [bps] fXCLK = Frequency of base clock (Clock) selected by bits UCnCKS3 to UCnCKS0 of UCnCTL1 register k = Value set using bits UCnBRS7 to UCnBRS0 of UCnCTL2 register (k = 4, 5, 6,..., 255) 15.6.3 Baud rate error The baud rate error is obtained by the following equation. baud rate (baud rate with error) - 1 x 100 [ % ] Error = Actual --------------------------------------------------------------------------------------------------- Desired baud rate (correct baud rate) Cautions: 1. The baud rate error during transmission must be within the error tolerance on the receiving side. 2. The baud rate error during reception must satisfy the range indicated in section 15.6.5 "Allowable baud rate range during reception" on page 642. Example Base clock (fXCLK) frequency = 16 MHz = 16,000,000 Hz Setting value of bits UCnBRS7 to UCnBRS0 of UCnCTL2 register = 00110100B (k = 52) Target baud rate = 153,600 Baud rate = 16,000,000/ (2 x 52) = 153,846 [bps] Error = (153,846/153,600 - 1) x 100 = 0.160 [%] 640 User's Manual U16580EE3V1UD00 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.4 Baud rate setting example Remark: Table 15-4: Baud Rate Generator Setting Data Baud Rate [bps] fXX = 64 MHz UCnCTL1 UCnCTL2 Error [%] 50 0BH 4EH 0.16 300 09H 68H 0.16 600 08H 68H 0.16 1200 07H 68H 0.16 2400 06H 68H 0.16 4800 05H 68H 0.16 9600 04H 68H 0.16 10400 04H 60H 0.16 19200 03H 68H 0.16 31250 02H 80H 0.00 38400 02H 68H 0.16 56000 01H 8FH -0.10 76800 01H 68H 0.16 125000 01H 40H 0.00 153600 01H 34H 0.16 250000 01H 20H 0.00 312500 00H 33H 0.39 1000000 00H 10H 0.00 2000000 00H 08H 0.00 fXX: Internal system clock Error: Baud rate error User's Manual U16580EE3V1UD00 641 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.5 Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution: The baud rate error during reception must be set within the allowable error range using the following equation. Figure 15-22: Allowable Baud Rate Range During Reception Latch timing UARTCn transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Parity bit Bit 7 Stop bit FLmax Remark: n = 0 to 2 As shown in Figure 15-22, the receive data latch timing is determined by the counter set using the UCnCTL2 register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. When this is applied to 11-bit reception, the following results in terms of logic. FL = (BR)-1 BR: UARTCn baud rate (n = 0, 1) k: UCnCTL2 setting value (n = 0, 1) FL: 1-bit data length Latch timing margin: 2 clocks Minimum allowable transfer rate: FLmin = 11 x FL - 642 k-2 2k x FL = 21k + 2 2k User's Manual U16580EE3V1UD00 FL Chapter 15 Asynchronous Serial Interface C (UARTC) Therefore, the maximum baud rate that can be received by the destination is as follows. 22k BRmax = (FLmin/11)-1 = 21k + 2 BR Similarly, obtaining the following maximum allowable transfer rate yields the following. k+2 21k - 2 10 x FLmax = 11 x FL x FL = FL 2 x k 2xk 11 FLmax = 21k - 2 FL x 11 20k Therefore, the minimum baud rate that can be received by the destination is as follows. 20k BRmin = (FLmax/11)-1 = BR 21k - 2 Obtaining the allowable baud rate error for UARTCn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. Table 15-5: Maximum/Minimum Allowable Baud Rate Error Divide Ratio (k) Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% Remarks: 1. The reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). The higher the input clock frequency and the larger the division ratio (k), the higher the accuracy is. 2. k: UCnCTL2 setting value (n = 0, 1) User's Manual U16580EE3V1UD00 643 Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.6 Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 clocks longer. However, timing initialization is performed through start bit detection by the receiving side, so this has no influence on the transfer result. Figure 15-23: Transfer Rate During Continuous Transfer Start bit of 2nd byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit Stop bit FL FLstp Assuming 1 bit data length: FL, stop bit length: FLstp, and base clock frequency: fXCLK, we obtain the following equation. FLstp = FL + 2/fXCLK Therefore, the transfer rate during continuous transmission is as follows. Transfer rate = 11 x FL + 2/fXCLK 644 User's Manual U16580EE3V1UD00 Start bit FL Bit 0 FL Chapter 16 Clocked Serial Interface B (CSIB) 16.1 Features * Transfer rate: Maximum 8 Mbps * Master mode and slave mode selectable * Serial clock and data phase switchable * Transmission data length: 8 to 16 bits (selectable in 1-bit units) * Transfer data MSB-first/LSB-first switchable * Transmission mode, reception mode, and transmission/reception mode selectable * 3-wire serial interface - SOBn: Serial data output - SIBn: Serial data input Serial clock output - SCKBn: * Slave select function supported Serial slave select input - SSBn: * Interrupt request signals x 3 - Reception error interrupt (INTCBnRE) - Reception complete interrupt (INTCBnR) - Transmission enable interrupt (INTCBnT) Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 16.2 Configuration CSIB includes the following hardware. Table 16-1: Item Registers CSIBn Configuration Configuration CSIBn receive data register (CBnRX) CSIBn transmit data register (CBnTX) Control registers CSIBn control register 0 (CBnCTL0) CSIBn control register 1 (CBnCTL1) CSIBn control register 2 (CBnCTL2) CSIBn status register (CBnSTR) User's Manual U16580EE3V1UD00 645 Chapter 16 Clocked Serial Interface B (CSIB) Figure 16-1: Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR SSBn INTCBnT INTCBnR INTCBnRE fBRG0 fBRG1 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Selector Controller Phase control CBnTX SCKBn SO latch SIBn Shift register CBnRX Remarks: 1. PD70F3187: PD70F3447: n = 0, 1 n=0 2. fXX: Internal system clock fBRG0: Clock from BRG0 fBRG1: Clock from BRG1 646 User's Manual U16580EE3V1UD00 Phase control SOBn Chapter 16 Clocked Serial Interface B (CSIB) (1) CSIBn receive data register (CBnRX, CBnRXL) The CBnRX register is a 16-bit buffer register that holds receive data. It is overlayed by an 8-bit register CBnRXL on the lower 8 bits, which is used when the transfer data length is 8 bits. The receive operation is started by reading the CBnRX or CBnRXL registers during reception enabled status. The CBnRX register is read-only, in 16-bit units. The CBnRXL register is read-only, in 8-bit units. Reset input clears the CBnRX register to 0000H, and the CBnRXL register to 00H accordingly. In addition to reset input, the CBnRX or CBnRXL registers can be initialized by clearing (0) the CBnPWR bit of the CBnCTL0 register. Figure 16-2: After reset: CSIBn Receive Data Register (CBnRX, CBnRXL) 0000H 15 14 R 13 12 Address: 11 10 9 8 CB0RX FFFFFD04H, CB1RX FFFFFD24HNote 7 6 5 4 3 2 1 0 CBnRX CBnRXL After reset: 00H 7 R 6 Address: 5 4 CB0RXL FFFFFD04H, CB1RXL FFFFFD24HNote 3 2 1 0 CBnRXL Note: Not available on PD70F3447 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 647 Chapter 16 (2) Clocked Serial Interface B (CSIB) CSIB transmit data register (CBnTX) The CBnTX register is a 16-bit buffer register used to write the CSIB transfer data. It is overlayed by an 8-bit register CBnTXL on the lower 8 bits, which is used when the transfer data length is 8 bits. The transmit operation is started by writing data to the CBnTX or CBnTXL registers during transmission enabled status. The CBnTX register can be read or written in 16-bit units. The CBnTXL register can be read or written in 8-bit units. Reset input clears the CBnTX register to 0000H, and the CBnRXL register to 00H accordingly. In addition to reset input, the CBnTX and CBnTXL registers can be initialized by clearing (to 0) the CBnPWR bit of the CBnCTL0 register. Figure 16-3: After reset: CSIBn Transmit Data Register (CBnTX, CBnTXL) 0000H 15 14 R/W 13 12 Address: 11 10 9 8 CB0TX FFFFFD06H, CB1TX FFFFFD26HNote 7 6 5 4 3 2 1 0 CBnTX CBnTXL After reset: 00H 7 R/W 6 Address: 5 4 CB0TXL FFFFFD06H, CB1TXL FFFFFD26HNote 3 CBnTXL Note: Not available on PD70F3447 Remark: 648 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 2 1 0 Chapter 16 Clocked Serial Interface B (CSIB) 16.3 Control Registers The following registers are used to control CSIB. * CSIBn control register 0 (CBnCTL0) * CSIBn control register 1 (CBnCTL1) * CSIBn control register 2 (CBnCTL2) * CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) The CBnCTL0 register is a register that controls the CSIB serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 01H. Caution: Be sure to set bit 3 to 0 when written to the CBnCTL0 register. Figure 16-4: After reset: 01H R/W 7 CBnCTL0 CBnPWR CSIBn Control Register 0 (CBnCTL0) (1/2) Address: CB0CTL0 FFFFFD00H, CB1CTL0 FFFFFD20HNote 2 6 5 4 3 2 1 0 CBnTXE Note 1 CBnRXE Note 1 CBnDIR Note 1 0 CBnSSE Note 1 CBnTMS Note 1 CBnSCE CBnPWR CSIBn Operation Control 0 Stops clock operation and reset the internal circuit 1 Enables operating clock operation The CBnPWR bit controls the CSIB operating clock and resets the internal circuit. Transmission Operation Enable CBnTXE Note 1 0 Stops transmission operation 1 Enables transmission operation The SOBn serial output pin is fixed to low level and communication is stopped by clearing the CBnTXE bit to 0. Reception Operation Enable CBnRXE Note 1 0 Stops reception operation 1 Enables reception operation When the CBnRXE bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to stop the receive operation, and the CBnRX register is not updated. Notes: 1. Rewrite is possible only when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be set at the same time. 2. Not available on PD70F3447 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 649 Chapter 16 Figure 16-4: Clocked Serial Interface B (CSIB) CSIBn Control Register 0 (CBnCTL0) (2/2) Transfer Direction Selection CBnDIR Note 0 MSB-first transfer 1 LSB-first transfer Slave Selection Operation Enable CBnSSE Note 0 Slave selection function disabled 1 Slave selection function enabled When the CSIBn serves as slave, it executes transmission/reception in synchronization with the clock only when a low level is input to the SSBn pin. Transfer Mode Selection CBnTMS Note 0 Single transfer mode 1 Continuous transfer mode When the CBnTMS bit = 0, the single transfer mode is entered, so continuous transmission/continuous reception are not supported. Even in the case of transmission only, an interrupt is output upon completion of reception transfer. CBnSCE Serial Clock Enable 0 Clock output stopped 1 Clock output enabled The transfer clock is stopped after the last data in the master reception mode. Clear (0) the CBnSCE bit prior to when the last data is read in the single transfer mode, and 1 clock before the completion of reception of the last data in the continuous transfer mode. The transfer clock can be output by setting the CBnSCE bit to 1 again after the last data has been read. Note: Rewrite is possible only when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be set at the same time. Remark: 650 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) (2) CSIBn control register 1 (CBnCTL1) The CBnCTL1 register is an 8-bit register that controls the CSIB serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution: The CBnCTL1 register can be rewritten when the CBnPWR bit of the CBnCTL0 register is 0 or when both the CBnTXE and CBnRXE bits are 0. Figure 16-5: After reset: CBnCTL1 00H CSIBn Control Register 1 (CBnCTL1) R/W Address: 7 6 5 4 0 0 0 CBnCKP CBnCKP CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD21HNote 2 3 2 1 0 CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 CBnDAP Specification of Data Transmission/Reception Timing in Relation to Clock Phase 0 0 SCKBn (I/O) D7 SOBn (output) D6 D5 D4 D3 D2 D1 D0 SIBn capture 0 1 SCKBn (I/O) SOBn (output) D7 D6 D5 D4 D3 D2 D1 D0 SIBn capture 1 0 SCKBn (I/O) D7 (output) D6 D5 D4 D3 D2 D1 D0 SIBn capture 1 1 SCKBn (I/O) (output) D7 D6 D5 D4 D3 D2 D1 D0 SIBn capture CBnCKS2 CBnCKS1 CBnCKS0 Base Clock (fXCCLK) Mode 0 0 0 fBRG0Note 1 Master mode 0 0 1 fBRG1Note 1 Master mode 0 1 0 fXX/8 Master mode 0 1 1 fXX/16 Master mode 1 0 0 fXX/32 Master mode 1 0 1 fXX/64 Master mode 1 1 0 fXX/128 Master mode 1 1 1 External clock (SCKBn) Slave mode Notes: 1. For details on the baud rate generator refer to 16.7 "Baud Rate Generator" on page 673. 2. Not available on PD70F3447 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 651 Chapter 16 (3) Clocked Serial Interface B (CSIB) CSIBn control register 2 (CBnCTL2) The CBnCTL2 register is an 8-bit register that controls the number of CSIB serial transfer bits. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Caution: The CBnCTL2 register can be rewritten only when the CBnPWR bit of the CBnCTL0 register is 0 or when both the CB0TXE and CB0RXE bits are 0. Figure 16-6: After reset: CBnCTL2 00H CSIBn Control Register 2 (CBnCTL2) R/W Address: CB0CTL2 FFFFFD02H, CB1CTL2 FFFFFD22HNote 7 6 5 4 3 2 1 0 0 0 0 0 CBnCL3 CBnCL2 CBnCL1 CBnCL0 CBnCL3 CBnCL2 CBnCL1 CBnCL0 0 0 0 0 8 bits 0 0 0 1 9 bits 0 0 1 0 10 bits 0 0 1 1 11 bits 0 1 0 0 12 bits 0 1 0 1 13 bits 0 1 1 0 14 bits 0 1 1 1 15 bits 1 x x x 16 bits Serial Register Bit Length Caution: If the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the LSB of the CBnTX and CBnRX registers. Remark: x: don't care Note: Not available on PD70F3447 Remark: 652 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) (a) Transfer data length function The CSIB transfer data length can be set in 1-bit units between 8 and 16 bits using bits CBnCL3 to CBnCL0 of the CBnCTL2 register. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB. Any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. Figure 16-7: Effect of Transfer Data Length Setting (a) Transfer bit length = 10 bits, MSB first SOBn SIBn 15 10 9 0 Insertion of 0 (b) Transfer bit length = 12 bits, LSB first SIBn 15 12 SOBn 11 0 Insertion of 0 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 653 Chapter 16 (4) Clocked Serial Interface B (CSIB) CSIBn status register (CBnSTR) The CBnSTR register is an 8-bit register that displays the CSIB status. This register can be read or written in 8-bit or 1-bit units, but the CBnSTF flag is a read-only. Reset input clears this register to 00H. In addition to reset input, the CBnSTR register can be initialized by clearing (0) the CBnPWR bit of the CBnCTL0 register. Figure 16-8: After reset: CBnSTR 00H CSIBn Status Register (CBnSTR) R/W Address: CB0CTL0 FFFFFD03H, CB1CTL0 FFFFFD23HNote 7 6 5 4 3 2 1 0 CBnTSF 0 0 0 0 0 0 CBnOVE CBnTSF CSIBn Operation Control 0 Idle status 1 Operating status During transmission, this register is set (1) when data is prepared in the CBnTX register, and during reception, it is set (1) when a dummy read of the CBnRX register is performed. The clear timing is after the edge of the last clock. CBnOVE Overrun Error Flag 0 No overrun 1 Overrun * An overrun error occurs when the next reception starts without performing a CPU read of the value of the CBnRX register upon completion of the receive operation. In this case the CBnOVE flag displays the overrun error occurrence status, and a reception error interrupt (INTCBnRE) is generated. * The CBnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it. Note: Not available on PD70F3447 Remark: 654 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.4 Operation 16.4.1 Single transfer mode (master mode, transmission/reception mode) Figure 16-9: Single Transfer Mode (Master Mode, Transmission/Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register write (55H) CBnRX register read (AAH) SCKBn pin CBnTX register 55H (transmit data) Shift register n ABH 56H ADH 5AH B5H 6AH D5H CBnRX register AAH 00H AAH 00H INTCBnR signal SIBn pin 1 0 1 0 1 0 1 0 (AAH) SOBn pin 0 1 0 1 0 1 0 1 (55H) <5> <1> <4> <2> <3> <6> <7> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnTXE and CBnRXE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/ reception enable status. <3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply. <4> Write transfer data to the CBnTX register (transmission start). <5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX (CBnRXL) register is possible. <6> Read the CBnRX register before clearing the CBnPWR bit to 0. <7> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of transmission/reception). To continue transfer, repeat steps <4> to <6> before <7>. Remarks: 1. The processing of steps <2> and <3> can be set simultaneously. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 655 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.2 Single transfer mode (master mode, transmission mode) Figure 16-10: Single Transfer Mode (Master Mode, Transmission Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register write (55H) SCKBn pin CBnTX register 55H (transmit data) Shift register n AAH 54H A8H 50H A0H 40H 80H 00H INTCBnR signal 0 SOBn pin SIBn pin 1 0 1 0 1 0 1 (55H) L CBnTSF bit <5> <1> <4> <2> <3> <6> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnTXE bit of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/reception enable status. <3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply. <4> Write transfer data to the CBnTX register (transmission start). <5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that writing the CBnTX (CBnTXL) register is possible. <6> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of transmission/reception). To continue transfer, repeat steps <4> and <5> before <6>. Remarks: 1. The processing of steps <2> and <3> can be set simultaneously. 2. PD70F3187: PD70F3447: 656 n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.3 Single transfer mode (master mode, reception mode) Figure 16-11: Single Transfer Mode (Master Mode, Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnRX register read (55H) CBnRX register read (AAH) SCKBn pin CBnRX register 55H (receive data) Shift register n ABH 56H ADH 5AH B5H 6AH D5H AAH 00H AAH 00H INTCBnR signal 1 SIBn pin SOBn pin 0 1 0 1 0 1 0 (AAH) L CBnSCE bit <5> <1> <4> <2> <3> <6> <7> <8> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnRXE bit of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the reception enabled status. <3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply. <4> Perform a dummy read of the CBnRX register (reception start trigger). <5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX (CBnRXL) register is possible. <6> Clear the CBnSCE bit of the CBnCTL0 register to 0 to set the reception end data status. <7> Read the CBnRX register before clearing the CBnPWR bit to 0. <8> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of reception). To continue transfer, repeat steps <4> and <5> before <6>. (At this time, <4> is not a dummy read, but a receive data read combined with the reception trigger.) Remarks: 1. The processing of steps <2> and <3> can be set simultaneously. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 657 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.4 Continuous mode (master mode, transmission/reception mode) Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 1, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register AAH 55H SCKBn pin SOBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 SIBn pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 INTCBnT signal INTCBnR signal Shift register n CCH 96H 00H 96H 00H SO latch CCH <1> <2> <3> <5> <4> <6> <6> <7> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnTXE and CBnRXE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/ reception enabled status. <3> Set the CBnPWR bit of the CBnCTL0 register is 1 to enable CSIB operating clock supply. <4> Write transfer data to the CBnTX register (transmission start). <5> The transmission enable interrupt (INTCBnT) is received and transfer data is written to the CBnTX register. <6> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX (CBnRXL) register is possible. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. <7> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of transmission/reception). To continue transfer, repeat steps <4> to <6> before <7>. Remark: 658 PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.5 Continuous mode (master mode, transmission mode) Figure 16-13: Continuous Mode (Master Mode, Transmission Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin SOBn pin 1 SIBn pin 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 L INTCBnT signal Shift register n 00H 00H SO latch CBnTX register 55H AAH CBnTSF bit <1> <2> <3> <5> <4> <6> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnTXE of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/reception enabled status. <3> Set the CBnPWR bit of the CBnCTL0 register is 1 to enable CSIB operating clock supply. <4> Write transfer data to the CBnTX register (transmission start). <5> The transmission enable interrupt (INTCBnT) is received and transfer data is written to the CBnTX register. <6> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of transmission/reception). To continue transfer, repeat steps <4> and <5> before <6>. Remark: PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 659 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.6 Continuous mode (master mode, reception mode) Figure 16-14: Continuous Mode (Master Mode, Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 1, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin CBnSCE bit SIBn pin 0 1 0 1 01 1 0 1 1 0 1 0 0 1 0 INTCnR signal Shift register n 55H CBnRX register 55H <1> <2> <3> <5> <4> <6> <5> AAH 00H AAH 00H <7> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnRXE bit of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the reception enabled status. <3> Set the CBnPWR bit of the CBnCTL0 register is 1 to enable CSIB operating clock supply. <4> Perform a dummy read of the CBnRX register (reception start trigger). <5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX (CBnRXL) register is possible. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. <6> Clear the CBnSCE bit of the CBnCTL0 register is 0 to set the reception end data status. <7> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of reception). To continue transfer, repeat steps <4> and <5> before <6>. Remark: 660 PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.7 Continuous reception mode (error) Figure 16-15: Continuous Reception Mode (Error) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 1, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin SIBn pin 0 1 0 1 0 1 01 1 1 0 1 0 0 1 0 INTCBnR signal INTCBnRE signal Shift register n AAH 00H 55H CBnRX register 55H CBnOVE flag <1> <2> <3> <5> <4> <6> <7> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnTXE and CBnRXE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/ reception enable status. <3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply. <4> Perform a dummy read of the CBnRX register (reception start trigger). <5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX (CBnRXL) register is possible. <6> If the data could not be read before the end of the next transfer, a receive error interrupt (INTCBnRE) is output and the CBnOVE flag of the CBnSTR register is set (1). The CBnRX register is read as error restore processing. <7> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIBn (end of reception). Remark: PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 661 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.8 Continuous mode (slave mode, transmission/reception mode) Figure 16-16: Continuous Mode (Slave Mode, Transmission/Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 1, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register AAH 55H SCKBn pin SOBn pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 SIBn pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 INTCBnT signal INTCBnR signal Shift register n CCH 96H 00H SO latch CBnRX register CCH <1> <2> <3> <5> <4> <6> 96H <6> 00H <7> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnTXE and CBnRXE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/ reception enabled status. <3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply. <4> Write the transfer data to the CBnTX register. <5> The transmission enable interrupt (INTCBnT) is received and the transfer data is written to the CBnTX register. <6> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX register is possible. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. <7> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of transmission/reception). To continue transfer, repeat steps <4> to <6> before <7>. Remark: 662 PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.9 Continuous mode (slave mode, reception mode) Figure 16-17: Continuous Mode (Slave Mode, Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin SIBn pin 0 1 0 1 01 1 0 1 1 0 1 0 0 1 0 INTCBnR signal Shift register n 55H CBnRX register AAH 00H AAH 00H 55H <1> <2> <3> <5> <4> <5> <6> <1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode. <2> Set the CBnRXE bit of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the reception enabled status. <3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply. <4> Perform a dummy read of the CBnRX register (reception start trigger). <5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX register is possible. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. <6> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop clock supply to CSIB (end of reception). To continue transfer, repeat steps <4> and <5> before <6>. Remark: PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 663 Chapter 16 Clocked Serial Interface B (CSIB) 16.4.10 Clock timing Figure 16-18: CSIBn Clock Timing (1/2) (a) CBnCKP = 0, CBnDAP = 0 SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF bit (b) CBnCKP = 1, CBnDAP = 0 SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF bit Remark: 664 PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) Figure 16-18: CSIBn Clock Timing (2/2) (c) CBnCKP = 0, CBnDAP = 1 SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF bit (d) CBnCKP = 1, CBnDAP = 1 SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF bit Remark: PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 665 Chapter 16 Clocked Serial Interface B (CSIB) 16.5 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnPWR bit of CBnCTL0 register = 0), the SCKBn pin output status is as follows. CBnCKP SCKBn Pin Output 0 Fixed to high level 1 Fixed to low level Remarks: 1. The SCKBn pin output changes when the CBnCKP bit of the CBnCTL1 register is rewritten. 2. PD70F3187: PD70F3447: (2) n = 0, 1 n=0 SOBn pin When CSIBn operation is disabled (CBnPWR bit = 0), the SOBn pin output status is as follows. CBnTXE CBnDAP CBnDIR SOBn Pin Output 0 x x Fixed to high level 1 0 x SOBn latch value (low level) 1 0 CBnTXn value (MSB) 1 CBnTXn value (LSB) Remarks: 1. The SOBn pin output changes when any one of the CBnTXE, CBnDAP, and CBnDIR bits of the CBnCTL1 register is rewritten. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 3. x: don't care 666 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.6 Operation Flow (1) Single transmission Figure 16-19: Operation Flow of Single Transmission START Note Initial settings (CBnCTL0 / CBnCTL1 registers etc.) CBnTX register write (Transfer start) No INTCBnR = 1 Yes Yes Transfer data exists? No END Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remark: PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 667 Chapter 16 (2) Clocked Serial Interface B (CSIB) Single reception (master) Figure 16-20: Operation Flow of Single Reception (Master) START Note Initial settings (CBnCTL0 / CBnCTL1 registers etc.) Dummy read of CBnRX register No INTCBnR = 1 Yes Yes Last data? CBnCTL0.CBnSCE bit = 0 No CBnRX register read CBnRX register read CBnCTL0.CBnSCE bit = 1 END Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remark: 668 PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) (3) Single reception (slave) Figure 16-21: Operation Flow of Single Reception (Slave) START Note Initial settings (CBnCTL0 / CBnCTL1 registers etc.) Dummy read of CBnRX register No INTCBnR = 1 Yes CBnRX register read No Last data? Yes END Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remark: PD70F3187: n = 0, 1 PD70F3447: n = 0 User's Manual U16580EE3V1UD00 669 Chapter 16 (4) Clocked Serial Interface B (CSIB) Continuous transmission Figure 16-22: Operation Flow of Continuous Transmission START Note Initial settings (CBnCTL0 / CBnCTL1 registers etc.) CBnTX register write (transfer start) No INTCBnT = 1 Yes Data to be transferred next exists? Yes No END Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remarks: 1. The steps below the broken line constitute the transmission flow. Execute only steps below the broken line when starting the second and subsequent transmissions. 2. PD70F3187: PD70F3447: 670 n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) (5) Continuous reception (master) Figure 16-23: Operation Flow of Continuous Reception (Master) START Note Initial settings (CBnCTL0 / CBnCTL1 registers etc.) Dummy read of CBnRX register No INTCBnR = 1 Yes Yes CBnCTL0.CBnSCE bit = 0 Data currently received = last data? No CBnRX register read CBnRX register read No INTCBnR = 1 Yes CBnRX register read CBnCTL0.CBnSCE bit = 1 END Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remarks: 1. The steps below the broken line constitute the transmission flow. Execute only steps below the broken line when starting the second and subsequent transmissions. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 671 Chapter 16 (6) Clocked Serial Interface B (CSIB) Continuous reception (slave) Figure 16-24: Operation Flow of Continuous Reception (Slave) START Note Initial settings (CBnCTL0 / CBnCTL1 registers etc.) Dummy read of CBnRX register No INTCBnR = 1 Yes CBnRX register read No Last data? Yes END Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remarks: 1. The steps below the broken line constitute the transmission flow. Execute only steps below the broken line when starting the second and subsequent transmissions. 2. PD70F3187: PD70F3447: 672 n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) 16.7 Baud Rate Generator 16.7.1 Configuration Figure 16-25: Block Diagram of Baud Rate Generators 0 and 1 (BRG0, BRG1) fXX/8 fXX/16 fXX/32 fXX/64 8-bit Counter BRGOUTm Output Control INTBRGm PRSCMm The baud rate generators 0 and 1 (BRG0, BRG1) and CSIB0 and CSIB1 are connected as shown in the following block diagram. Figure 16-26: Block Diagram of CSIBn Baud Rate Generators BRGOUT0 fXX/4 BRG0 CSIB0 Note CSIB1 fXX/4 BRG1 BRGOUT1 INTBRG0 INTBRG1 Note: Not available on PD70F3447 Remarks: 1. An unused baud rate generator (BRGm) can be employed as interval timer generating a dedicated interrupt request (INTBRGm). 2. m = 0, 1 User's Manual U16580EE3V1UD00 673 Chapter 16 Clocked Serial Interface B (CSIB) 16.7.2 Control registers (1) Prescaler mode registers 0 and 1 (PRSM0, PRSM1) The PRSMm register controls generation of a baud rate signal for CSIB (m = 0, 1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 16-27: After reset: Prescaler Mode Registers 0 and 1 (PRSM0, PRSM1) 00H 7 PRSMm R/W Address: PRSM0 FFFFFDC0H, PRSM1 FFFFFDD0H 6 5 4 3 2 0 0 BGCEm 0 0 1 0 BGCSm1 BGCSm0 (m = 0, 1) BGCEm Baud Rate Generator Output Control 0 Disabled 1 Enabled BGCSm1 BGCSm0 Baud Rate Generator Clock Selection (fBGCSm) Setting Value (k) 0 0 fXX/4 2 0 1 fXX/8 3 1 0 fXX/16 4 1 1 fXX/32 5 Cautions: 1. Do not rewrite the PRSMm register during operation. 2. Set the BGCSm1, BGCSm0 bits before setting the BGCEm bit to 1. Remark: 674 m = 0, 1 User's Manual U16580EE3V1UD00 Chapter 16 Clocked Serial Interface B (CSIB) (2) Prescaler compare registers 0 and 1 (PRSCM0, PRSCM1) The PRSCMm register is an 8-bit compare register (m = 0, 1). This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 16-28: After reset: PRSCMm Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1) 00H R/W Address: PRSM0 FFFFFDC1H, PRSM1 FFFFFDD1H 7 6 5 4 3 2 1 0 PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0 (m = 0, 1) PRSCM PRSCM PRSCM PRSCM PRSCM PRSCM PRSCM PRSCM m7 m6 m5 m4 m3 m2 m1 m0 Serial Clock N 0 0 0 0 0 0 0 0 fBGSCm/512 256 0 0 0 0 0 0 0 1 fBGSCm/2 1 0 0 0 0 0 0 1 0 fBGSCm/4 2 : : : : : : : : : : 1 1 1 1 1 1 0 0 fBGSCm/504 252 1 1 1 1 1 1 0 1 fBGSCm/506 253 1 1 1 1 1 1 1 0 fBGSCm/508 254 1 1 1 1 1 1 1 1 fBGSCm/510 255 Cautions: 1. Do not rewrite the PRSCMm register during operation. 2. Set the PRSCMm register before setting the BGCEm bit of the PRSMm register to 1. Remarks: 1. fBGCSm: Clock frequency selected by the BGCSm1, BGCSm0 bits of the PRSMm register. 2. m = 0, 1 User's Manual U16580EE3V1UD00 675 Chapter 16 Clocked Serial Interface B (CSIB) 16.7.3 Baud rate generation The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. f BGCSm f XX = ------------------------f BRGm = -------------------k Nx2 2 xNx2 Remarks: 1. fBRGm: BRGm count clock 2. fBGCSm: Clock frequency selected by the BGCSm1, BGCSm0 bits of the PRSMm register. 3. fXX: Main clock oscillation frequency 4. k: PRSMm register setting value (2 k 5) 5. N: PRSCMm register setting value (1 to 255), when PRSCMm = 01H to FFH, or N = 256, when PRSCMm = 00H. 6. m = 0, 1 16.8 Cautions In communication modes where CBnCTL1.CBnDAP bit = 1, the CBnSTR.CBnTSF bit is cleared half a SCKBn clock after occurrence of a reception completion interrupt (INTCBnR). In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1), and the next transfer is not started. Also if reception-only communication (CBnCTL0.CBnTXE bit = 0, CBnCTL0.CBnRXE bit = 1) is set, the next transfer is not started even if the receive data is read during communication (CBnTSF bit = 1). Therefore, when using the single transfer mode with communication modes where CBnCTL1.CBnDAP bit = 1, pay particular attention to the following: * To start the next transmission, first confirm that CBnTSF bit = 0, and then write the transmit data to the CBnTX register. * To perform the next reception continuously in reception-only mode (CBnTXE = 0, CBnRXE = 1), confirm that CBnTSF bit = 0, and then read the CBnRX register. If communication is supported by DMA transfer function, only communication modes with CBnDAP bit = 0 should be used. 676 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.1 Features * Transfer rate: Maximum 8 Mbps * Master mode and slave mode selectable * Serial clock and data phase switchable * Transmission data length: 8 to 16 bits (selectable in 1-bit units) * Transfer data MSB-first/LSB-first switchable * Transmission mode, reception mode, and transmission/reception mode selectable * 3-wire serial interface - SO3n: Serial data output - SI3n: Serial data input Serial clock I/O - SCK3n: * Four external chips select signal outputs (SCS3n0 to SCS3n3) * Interrupt request signals x 2 - Transmission/reception completion interrupt (INTC3n) - CSIBUFn overflow interrupt (INTC3nOVF) * Sixteen on-chip 20-bit transmit/receive buffers (CSIBUFn) * On-chip dedicated baud rate generator Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 677 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.2 Configuration CSI3n is controlled by the clocked serial interface mode register 3n (CSIM3n). (1) Clocked serial interface mode register 3n (CSIM3n) The CSIM3n register is an 8-bit register for specifying the operation of CSI3n. (2) Clocked serial interface clock select register 3n (CSIC30, CSIC31) The CSIC3n register is an 8-bit register for controlling the operation clock and operating mode of CSI3n. (3) Serial I/O shift register 3n (SIO3n) The SIO3n register is an 8-bit register for converting between serial data and parallel data. SIO3n is used for both transmission and reception. Data is shifted in (reception) or shifted out (transmission) beginning at either the MSB side or the LSB side. (4) Receive data buffer register 3n (SIRB3n) The SIRB3n register is a 16-bit buffer register that stores receive data. This register is also divided into two registers: the higher 8 bits (SIRB3nH) and lower 8 bits (SIRB3nL). (5) Chip select CSI buffer register 3n (SFCS3n) The SFCS3n register is a 16-bit buffer register that stores chip select data. The lower 8 bits can also be accessed by an 8-bit buffer register (SFCS3nL). (6) Transmit data CSI buffer register 3n (SFDB3n) The SFDB3n register is a 16-bit buffer register that stores transmit data. This register is also divided into two registers: the higher 8 bits (SFDB3nH) and lower 8 bits (SFDB3nL). (7) CSIBUF status register 3n (SFA3n) The SFA3n register is an 8-bit register that indicates the status of CSI data buffer register n (CSIBUFn) or the transfer status. (8) Transfer data length select register 3n (CSIL3n) The CSIL3n register is an 8-bit register that selects the CSI3n transfer data length. (9) Transfer data number specification register 3n (SFN3n) The SFN3n register is an 8-bit register that sets the number of CSI3n transfer data in consecutive mode. (10) CSI data buffer register n (CSIBUFn) By consecutively writing transmit data to the SFDB3n register from where it is transferred, the data can be stored in the CSIBUFn register while the CSIBUFn pointer for writing is automatically incremented (CSIBUFn). The CSIBUFn is a 16-bit buffer register. Remark: 678 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Figure 17-1: Clocked Serial Interface 3 (CSI3) Block Diagram of Clocked Serial Interface 3n (CSI3n) Chip Select CSI buffer register 3n (SFCS3n) CSIBUF status register 3n (SFA3n) Transmit data CSI buffer register 3n (SFDB3n) INTC3nOVF Transfer data control 19 16 15 0 SCS3n0 CSI data buffer register n (CSIBUFn) Chip Select Control SCS3n1 SCS3n2 SCS3n3 Shift register n (SIO3n) SI3n SCK3n SCK3n Selector fXX SO3n Receive data buffer register 3n (SIRB3n) Prescaler BRG3n output fXCLK INTC3n Transfer control MDLn2 MDLn1 MDLn0 CKS3n2 CKS3n1 CKS3n0 Clocked serial interface clock select register 3n (CSIC3n) Remarks: 1. PD70F3187: PD70F3447: n = 0, 1 n=0 2. fXX: Main clock fXCLK: Basic clock selected by CKS3n2 to CKS3n0 bits of CSIC3n register User's Manual U16580EE3V1UD00 679 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.3 Control Registers (1) Clocked serial interface mode registers 3n (CSIM3n) The CSIM3n register controls the operation of CSI3n (n = 0, 1). This registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Cautions: 1. Writing the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits is enabled only when CTXEn bit = 0 and CRXEn bit = 0. 2. To use CSI3n, be sure to set the external pins related to the CSI3n function to control the mode and set the CSIC3n register. Then set the CSICAEn bit to 1 before setting the other bits. Figure 17-2: After reset: CSIM3n Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2) 00H R/W Address: CSIM30 FFFFFD40H, CSIM31 FFFFFD60HNote 7 6 5 4 3 2 1 0 CSICAEn CTXEn CRXEn TRMDn DIRn CSITn CSWEn CSMDn CSICAEn CSI3n Operation Clock Control 0 Stops clock supply to CSI3n 1 Supplies clock to CSI3n Cautions: 1. The CSI3n unit is reset when the CSICAEn bit = 0, and CSI3n is stopped. To operate CSI3n, first set the CSICAEn bit to 1. 2. When rewriting the CSICAEn bit from 0 to 1 or from 1 to 0, simultaneously rewriting the bits other than the CSICAEn bit of the CSIM3n register is prohibited. When the CSICAEn bit = 0, rewriting the bits other than the CSICAEn bit of the CSIM3n register, and the SFDB3n, SFDB3nL, and SFA3n registers is prohibited. CTXEn Transmission Operation Enable 0 Disables transmission 1 Enables transmission Caution: The CTXEn bit is reset when the CSICAEn bit is cleared to 0. CRXEn Reception Operation Enable 0 Disables reception 1 Enables reception Caution: The CRXEn bit is reset when the CSICAEn bit is cleared to 0. Note: Not available on PD70F3447 Remark: 680 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Figure 17-2: Clocked Serial Interface 3 (CSI3) Clocked Serial Interface Mode Register 3n (CSIM3n) (2/2) TRMDn Transfer Mode Specification 0 Single mode 1 Consecutive mode DIRn Transfer Direction Specification 0 MSB-first transfer 1 LSB-first transfer Specifies the transfer direction when data is written from the SFDB3n register to the CSIBUFn register or read from the SIRB3n and CSIBUFn registers. CSITn Transmission Completion Interrupt (INTC3n) Control 0 No delay 1 Delay mode (The interrupt request signal is delayed by half a cycle.) Cautions: 1. The delay mode (CSIT bit = 1) is valid only in the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B). In the slave mode (CKS3n2 to CKS3n0 bits = 111B), do not set the delay mode. If the delay mode is set, INTC3n is not affected by the CSITn bit. 2. If the CSITn bit is set to 1 in the consecutive mode (TRMDn bit = 1), the INTC3n interrupt is not output except when the last data set by the SFNn3 to SFNn0 bits of the SFN3n register is transferred, but a delay of half a clock can be inserted between each data transferred. CSWEn Transfer Wait Control 0 Disables transfer wait. 1 Enables transfer wait (1 wait cycle inserted on starting transfer). Caution: Inserting a transfer wait cycle (CSWEn bit = 1) is valid only in the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B). In the slave mode (CKS3n2 to CKS3n0 bits = 111B), do not insert a transfer wait cycle. If set, a transfer wait cycle is not inserted. CSMDn Chip Select Mode Specification 0 Disables inactive level setting of chip select outputs (SCS3n0 to SCS3n3) during transfer wait. 1 Enables inactive level setting of chip select outputs (SCS3n0 to SCS3n3) during transfer wait. Caution: The CSMDn bit setting is valid only when the transfer wait is enabled (CSWEn bit = 1) and the master mode is specified (CKS3n0 bits of the CSIC3n register other than 111B). In all other cases the CSMDn bit setting is invalid and no inactive level setting of chip select outputs between two consecutive transfers takes place. Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 681 Chapter 17 (2) Clocked Serial Interface 3 (CSI3) Clocked serial interface clock select register 3n (CSIC3n) The CSIC3n register is an 8-bit register that controls the operation clock and operating mode of CSI3n. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 07H. Caution: Data can be written to the CSIC3n register only when the CTXEn bit = 0 and CRXEn bit = 0 in the CSIM3n register. Figure 17-3: After reset: CSIC3n Clocked Serial Interface Clock Select Register 3n (CSIC3n) (1/3) 07H R/W Address: CSIC30 FFFFFD41H, CSIC31 FFFFFD61HNote 7 6 5 4 3 2 1 0 MDLn2 MDLn1 MDLn0 CKPn DAPn CKS3n2 CKS3n1 CKS3n0 MDLn2 MDLn1 MDLn0 Set Value (N) 0 0 0 - BRG3n stop mode (power save) 0 0 1 1 fXCLK/2 0 1 0 2 fXCLK/4 0 1 1 3 fXCLK/6 1 0 0 4 fXCLK/8 1 0 1 5 fXCLK/10 1 1 0 6 fXCLK/12 1 1 1 7 fXCLK/14 Transfer Clock (BRG3n Output Signal) Caution: In the slave mode (CKS3n2 to CKS3n0 bits = 111B), it is recommended to clear the MDLn2 to MDLn0 bits to 000 (BRG3n stop mode). Note: Not available on PD70F3447 Remark: 682 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Figure 17-3: Clocked Serial Interface 3 (CSI3) Clocked Serial Interface Clock Select Register 3n (CSIC3n) (2/3) CKPn DAPn 0 0 Specification of Data Transmission/Reception Timing in Relation to Clock Phase SCK3n (I/O) D7 SO3n (output) D6 D5 D4 D3 D2 D1 D0 SI3n capture 0 1 SCK3n (I/O) SO3n (output) D7 D6 D5 D4 D3 D2 D1 D0 SI3n capture 1Note 0 SCK3n (I/O) SO3n (output) D7 D6 D5 D4 D3 D2 D1 D0 SI3n capture 1Note 1 SCK3n (I/O) SO3n (output) D7 D6 D5 D4 D3 D2 D1 D0 SI3n capture Note: If the CKPn bit is set to 1 in the master mode (CKS3n2 to CKS3n0 bits are other than 111B), the SCK3n pin outputs a low level when it is inactive. If the CTXEn bit of the CSIM3n register is cleared to 0 (disabling transmission) and CRXEn bit is cleared to 0 (disabling reception), the SCK3n pin outputs a high level. Therefore, take the following measures to fix the SCK3n pin to low level when CSI3n is not used. [SCK3n pin] <1> Clear the corresponding port bit (P82 of the P8 register for CSI30, or P92 of the P9 register for CSI31) to 0: The port output level is set to low. <2> Clear the corresponding bit in the port mode register (PM82 of the PM8 register for CSI30, or PM92 of the PM9 register for CSI31) to 0: The pin is set into output mode. <3> Clear the corresponding bit in the port mode control register (PMC82 of the PMC8 register for CSI30, or PMC92 of the PMC9 register for CSI31) to 0: The pin is set into port mode (fixed to low-level output). <4> Clear the CTXEn and CRXEn bits of the CSIM3n register to 0: Transmission and reception are disabled. <5> Set the CTXEn or CRXEn bit of the CSIM3n register to 1: Transmission or reception is enabled (both transmission and reception can also be enabled). <6> Set the corresponding bit in the port mode control register (PMC82 of the PMC8 register for CSI30, or PMC92 of the PMC9 register for CSI31) to 1: The pin is set in the control mode (SCK3n pin output). Because the register set values <1> and <2> are retained, control can be performed only by <3> to <6> once they have been set. Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 683 Chapter 17 Figure 17-3: Clocked Serial Interface 3 (CSI3) Clocked Serial Interface Clock Select Register 3n (CSIC3n) (3/3) CKS3n2 CKS3n1 CKS3n0 Set Value (k) Basic Clock (fXCLK) 0 0 0 0 fXX Master mode 0 0 1 1 fXX/2 Master mode 0 1 0 2 fXX/4 Master mode 0 1 1 3 fXX/8 Master mode 1 0 0 4 fXX/16 Master mode 1 0 1 5 fXX/32 Master mode 1 1 0 6 fXX/64 Master mode 1 1 1 - External clock (SCK3n) Slave mode Remarks: 1. fXX: Main clock 2. PD70F3187: PD70F3447: 684 n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Mode Chapter 17 (3) Clocked Serial Interface 3 (CSI3) Receive data buffer register 3n (SIRB3n, SIRB3nL, SIRB3nH) The SIRB3n register is a 16-bit buffer register that stores receive data. It is overlayed by an 8-bit buffer register SIRB3nL on the lower 8 bits, and an 8-bit buffer register SIRB3nH on the higher 8 bits. By consecutively reading this register in the consecutive mode (TRMDn bit of the CSIM3n register = 1), the received data in the CSIBUFn register can be sequentially read while the CSIBUFn pointer for reading is incremented. In the single mode (TRMDn bit of the CSIM3n register = 0), received data is read by reading the SIRB3n register and it is judged that the SIRB3n register has become empty. The SIRB3n register is read-only, in 16-bit units. The SIRB3nL and SIRB3nH registers are read-only, in 8-bit units. Reset input clears the SIRB3n register to 0000H, and the SIRB3nL and SIRB3nH registers to 00H accordingly. In addition to reset input, the SIRB3n as well as the SIRB3nL and SIRB3nH registers are initialized by clearing (to 0) the CSICAEn bit of the CSIM3n register. Figure 17-4: After reset: 0000HNote1 15 SIRB3n Receive Data Buffer Register 3n (SIRB3n, SIRB3nL, SIRB3nH) 14 13 R 12 Address: 11 10 9 8 SIRB30 FFFFFD42H, SIRB31 FFFFFD62HNote2 7 6 5 4 After reset: 1 0 00HNote1 SIRB3nL R Address: SIRB30L FFFFFD42H, SIRB31L FFFFFD62HNote2 7 6 5 4 3 2 1 0 SIRBn7 SIRBn6 SIRBn5 SIRBn4 SIRBn3 SIRBn2 SIRBn1 SIRBn0 After reset: SIRB3nH 2 SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 SIRB3nH SIRB3nL 3 00HNote1 R Address: SIRB30H FFFFFD43H, SIRB31H FFFFFD63HNote2 7 6 5 4 3 2 1 0 SIRBn15 SIRBn14 SIRBn13 SIRBn12 SIRBn11 SIRBn10 SIRBn9 SIRBn8 Notes: 1. In consecutive mode (TRMDn bit of the CSIM3n register = 1): Undefined 2. Not available on PD70F3447 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 685 Chapter 17 (4) Clocked Serial Interface 3 (CSI3) Chip select CSI buffer register 3n (SFCS3n, SFCS3nL) The SFCS3n register is a 16-bit buffer register that stores transmit data. It is overlayed by an 8-bit buffer register SFCS3nL on the lower 8 bits. When chip select data is written to the SFCS3n (SFCS3nL) register, the data is stored in the CSIBUFn register following the CSIBUFn pointer for writing. The store operation is executed after next write of the transmit data CSI buffer register SFDB3n (SFDB3nL). When the data of this register is read, the value of the transmit data written last is read. The SFCS3n register can be read or written in 16-bit units. The SFCS3nL register can be read or written, in 8-bit or 1-bit units. Reset input clears the SFCS3n register to FFFFH, and the SFCS3nL register to FFH accordingly. Figure 17-5: After reset: FFFFH 15 SFCS3n Chip Select CSI Buffer Register 3n (SFCS3n, SFCS3nL) 14 R/W 13 12 11 Address: 10 9 8 SFCS30 FFFFFD44H, SFCS31 FFFFFD64HNote 7 6 5 4 3 2 1 0 SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS SFCS n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 SFCS3nL After reset: SFCS3nL FFH RW Address: SFCS30L FFFFFD44H, SFCS31L FFFFFD64HNote 7 6 5 4 3 2 1 0 SFCSn7 SFCSn6 SFCSn5 SFCSn4 SFCSn3 SFCSn2 SFCSn1 SFCSn0 Note: Not available on PD70F3447 Remark: 686 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 (5) Clocked Serial Interface 3 (CSI3) Transmit data CSI buffer register 3n (SFDB3n, SFDB3nL, SFDB3nH) The SFDB3n register is a 16-bit buffer register that stores transmit data. It is overlayed by an 8-bit buffer register SFDB3nL on the lower 8 bits, and an 8-bit buffer register SFDB3nH on the higher 8 bits. When transmit data is written to the SFDB3n register, the data is sequentially stored in the CSIBUFn register while the CSIBUFn pointer for writing is incremented. When the data of this register is read, the value of the transmit data written last is read. The SFDB3n register can be read or written in 16-bit units. The SFDB3nL and SFDB3nH registers can be read or written, in 8-bit or 1-bit units. Reset input clears the SFDB3n register to 0000H, and the SFDB3nL and SFDB3nH registers to 00H accordingly. Figure 17-6: After reset: Transmit Data CSI Buffer Register 3n (SFDB3n, SFDB3nL, SFDB3nH) 0000H 15 14 R/W 13 12 Address: 11 10 9 8 SFDB30 FFFFFD46H, SFDB31 FFFFFD66HNote 7 6 5 4 3 2 1 0 SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 SFDB3n SFDB3nH After reset: SFDB3nL 00H Address: SFDB30L FFFFFD46H, SFDB31L FFFFFD66HNote 7 6 5 4 3 2 1 0 SFDBn7 SFDBn6 SFDBn5 SFDBn4 SFDBn3 SFDBn2 SFDBn1 SFDBn0 After reset: 00H 7 SFDB3nH RW SFDB3nL R/W 6 Address: 5 4 SFDB30H FFFFFD47H, SFDB31H FFFFFD67HNote 3 2 1 SFDBn15 SFDBn14 SFDBn13 SFDBn12 SFDBn11 SFDBn10 SFDBn9 0 SFDBn8 Note: Not available on PD70F3447 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 687 Chapter 17 (6) Clocked Serial Interface 3 (CSI3) CSIBUF status register 3n (SFA3n) The SFA3n register indicates the status of the CSIBUFn register or the transfer status. This register can be read or written in 8-bit or 1-bit units (however, bits 6 to 0 can only be read. They do not change even if they are written). Reset input clears the register to 20H. Cautions: 1. Reading the SFA3n register is prohibited when the CSICAEn bit of the CSIM3n register is cleared (0). 2. Because the values of the SFFULn, SFEMPn, CSOTn, and SFPn3 to SFPn0 bits may change at any time during transfer, their values during transfer may differ from the actual values. Especially, use the CSOTn bit independently (do not use this bit in relation with the other bits). To detect the end of transfer by the SFA3n register, check to see if the SFEMPn bit is 1 after the data to be transferred has been written to the CSIBUFn register. 3. If the SFA3n register is read immediately after data has been written to the SFDB3n and SFDB3nL registers, the values of the SFFULn, SFEMPn, and SFPn3 to SFPn0 bits do not change in time. 4. If the SFA3n register is read before the SFFULn bit is set to 1 and the 17th data is written, the CSIBUFn overflow interrupt (INTC3nOVF) is generated. Figure 17-7: After reset: SFA3n 00H CSIBUF Status Register 3n (SFA3n)(1/3) R/W Address: SFA30 FFFFFD48H, SFA31 FFFFFD68HNote 7 6 5 4 3 2 1 0 FPCLRn SFFULn SFEMPn CSOTn SFPn3 SFPn2 SFPn1 SFPn0 FPCLRn CSIBUFn Pointer Clear Operation 0 No operation 1 Clear all CSIBUFn pointers Cautions: 1. This bit is always 0 when it is read. 2. If 1 is written to the FPCLRn bit in the middle of transfer, transfer is aborted. Because all the CSIBUFn pointers are cleared to 0, the remaining data in the CSIBUFn register is ignored. If 1 is written to the FPCLRn bit, be sure to read the SFA3n register to check to see if all the CSIBUFn pointers have been correctly cleared to 0 (SFFULn bit = 0, SFEMPn bit = 1, SFPn3 to SFPn0 bits = 0000B). Nothing happens even if 0 is written to the FPCLRn bit. Note: Not available on PD70F3447 Remark: 688 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Figure 17-7: Clocked Serial Interface 3 (CSI3) CSIBUF Status Register 3n (SFA3n)(2/3) SFFULn CSIBUFn Full Status Flag 0 CSIBUFn register has a vacancy 1 CSIBUFn is full Cautions: 1. This bit is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLR bit is set to 1. 2. If transfer of 16 data is specified in the consecutive mode (TRMDn bit of the CSIM3n register = 1) (SFNn3 to SFNn0 bits of the SFN3n register = 0000B), the SFFULn bit is set to 1 in the same way as in the single mode (TRMDn bit of the CSIM3n register = 0) when 16 data are in the CSIBUFn register. If even one of the data has been completely transferred, the SFFULn bit is cleared to 0. However, this does not mean that the CSIBUFn register has a vacancy. SFEMPn CSIBUFn Empty Status Flag 0 Data is in CSIBUFn register 1 CSIBUFn is empty Cautions: 1. This flag is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLR bit is set to 1. 2. If the data written to the CSIBUFn register has been transferred in the consecutive mode (TRMDn bit of the CSIM3n register = 1), the SFEMP bit is set to 1 in the same way as in the single mode (TRMDn bit of the CSIM3n register = 0) even if receive data is stored in the CSIBUF register. CSOTn Transfer Status Flag 0 Idle status 1 Transfer or transfer start processing in progress Cautions: 1. This flag is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLRn bit is set to 1, or when the CTXEn and CRXEn bits of the CSIM3n register are cleared to 0. 2. This flag is set (1) from when transfer is started until there is no more transfer data in the CSIBUFn register in the single mode (TRMDn bit of the CSIM3n register = 0) or until the specified number of data has been transferred in the consecutive mode (TRMDn bit of the CSIM3n register = 1). Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 689 Chapter 17 Figure 17-7: Clocked Serial Interface 3 (CSI3) CSIBUF Status Register 3n (SFA3n)(3/3) SFPn3 SFPn2 SFPn1 SFPn0 CSIBUFn Pointer Status 0H to FH (0 to 15) * In the single mode (TRMDn bit of the CSIM3n register = 0), the "number of transfer data remaining in CSIBUFn register (CSIBUFn pointer value for writing - CSIBUFn pointer value for SIO3n loading)" can be read. * In the consecutive mode (TRMDn bit of the CSIM3n register = 1), the "number of data completely transferred (value of CSIBUFn pointer for SIO3n loading/storing)" can be read. If the SFPn3 to SFPn0 bits are 0H, however, the number of transferred data is as follows, depending on the setting of the SFEMPn bit. When SFEMPn bit = 0: Number of transferred data = 0 When SFEMPn bit = 1: Number of transferred data = 16 or status before starting transfer (before writing transfer data) Caution: These bits are cleared to 0 in synchronization with the operating clock when the FPCLRn bit = 1. However, the values of these bits are held until the CSICAEn bit of the CSIM3n register is cleared to 0 or the FPCLRn bit is set to 1. Remark: 690 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 (7) Clocked Serial Interface 3 (CSI3) Transfer data length select register 3n (CSIL3n) The CSIL3n register is used to select the transfer data length of CSI3n. This register can be read or written in 8-bit or 1-bit units. Reset input clears the register to 00H. Caution: The CSIL3n register may be transferring data when the CTXEn or CRXEn bit of the CSIM3n register is 1. Before writing data to the CSIL3n register, be sure to clear the CTXEn and CRXEn bits to 0. Figure 17-8: After reset: CSIL3n Transfer Data Length Select Register 3n (CSIL3n) 00H R/W Address: CSIL30 FFFFFD49H, CSIL31 FFFFFD69HNote 7 6 5 4 3 2 1 0 CSLVn3 CSLVn2 CSLVn1 CSLVn0 CCLn3 CCLn2 CCLn1 CCLn0 CSLVnm Chip Select Output (SCS3nm) Level Setting (n = 0, 1; m = 0 to 3) 0 Active level of SCSnm output is low level 1 Active level of SCSnm output is high level CCLn3 CCLn2 CCLn1 CCLn0 0 0 0 0 16 bits 1 0 0 0 8 bits 1 0 0 1 9 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits Other than above Transfer Data Length Setting prohibited Caution: If a transfer data length other than 16 bits is specified (CCLn3 to CCLn0 bits = 0000), an undefined value is read to the higher excess bits of the SIRB3n and CSIBUFn registers (see 10.3.5 (3) Data transfer direction specification function). Note: Not available on PD70F3447 Remarks: 1. PD70F3187: PD70F3447: n = 0, 1 n=0 2. m = 0 to 3 User's Manual U16580EE3V1UD00 691 Chapter 17 (8) Clocked Serial Interface 3 (CSI3) Transfer data number specification register 3n (SFN3n) The SFN3n register is used to set the number of transfer data of CSI3n in the consecutive mode (TRMDn bit of the CSIM3n register = 1). This register can be read or written in 8-bit or 1-bit units. Figure 17-9: After reset: SFN3n Transfer Data Number Specification Register 3n (SFN3n) 00H R/W Address: SFN30 FFFFFD49H, SFN31 FFFFFD69HNote 7 6 5 4 3 2 1 0 0 0 0 0 SFNn3 SFNn2 SFNn1 SFNn0 SFNn3 SFNn2 SFNn1 SFNn0 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Number of Transfer Data Caution: Writing data exceeding the value set by the SFNn3 to SFNn0 bits (number of CSI3n transfer data) to the CSIBUFn register is prohibited (data is ignored even if written). Note: Not available on PD70F3447 Remark: 692 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.4 Dedicated Baud Rate Generator 3n (BRG3n) The transfer clock of CSI3n can be selected from the output of a dedicated baud rate generator (BRG3n) or external clock (n = 0, 1). The serial clock source is specified by the CSIC3n register. In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), BRG3n is selected as the clock source. (1) Transfer clock Figure 17-10: Transfer Clock of CSI3n SCK3n Selector fXX Transfer clock fXCLK Prescaler BRG3n (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14) MDLn2 MDLn1 MDLn0 CKS3n2 CKS3n1 CKS3n0 Clocked serial interface clock select register 3n (CSIC3n) Remarks: 1. PD70F3187: PD70F3447: n = 0, 1 n=0 Main clock 2. fXX: fXCLK: Basic clock selected by CSIC3n register User's Manual U16580EE3V1UD00 693 Chapter 17 (2) Clocked Serial Interface 3 (CSI3) Baud rate The baud rate is calculated by the following expression. f XX Baud rate = ---------------------------- [bps] (k + 1) Nx2 Remarks: 1. fXX: Main clock 2. k: Value set by CKS3n2 to CKS3n0 bits of CSIC3n register (0 k 6) 3. N: Value set by MDLn2 to MDLn0 bits of CSIC3n register (1 N 7) Cautions: 1. If the CKS3n2 to CKS3n0 bits of the CSIC3n register are cleared to 000B, setting the MDLn2 to MDLn0 bits of the CSIC3n register to 001B is prohibited. 2. Because the maximum transfer rate in the master mode (CKS3n2 to CKS3n0 bits other than 111B) is 8 Mbps, do not exceed this value. Example: When the main clock fXX is 64 MHz, the maximum transfer rate is set when the CKS3n2 to CKS3n0 bits = 000B and the MDLn2 to MDLn0 bits = 100B. 694 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5 Operation 17.5.1 Operation modes Table 17-1: TRMDn Bit Single mode CKS3n2 to CKS3n0 Bits Operation Modes CTXEn and CRXEn Bits DIRn Bit CSITn Bit Master mode Transmission/ reception/ transmission and reception MSB/LSB first INTC3n delay mode enabled/ disabled CSWEn Bit Transfer wait disabled Transfer wait enabled CSMDn Bit Intermediate inactive level of chip select outputs disabled Intermediate inactive level of chip select outputs enabled Consecutive mode Slave mode - Master mode INTC3n delay mode enabled/ disabled - Transfer wait disabled Transfer wait enabled - Intermediate inactive level of chip select outputs disabled Intermediate inactive level of chip select outputs enabled Slave mode - - Remarks: 1. CTXEn bit: Bit 6 of CSIM3n register CRXEn bit: Bit 5 of CSIM3n register TRMDn bit: Bit 4 of CSIM3n register DIRn bit: Bit 3 of CSIM3n register CSITn bit: Bit 2 of CSIM3n register CSWEn bit: Bit 1 of CSIM3n register CSMDn bit: Bit 0 of CSIM3n register CKS3n2 to CKS3n0 bits: Bits 2 to 0 of CSIC3n register 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 695 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.2 Function of CSI data buffer register (CSIBUFn) By consecutively writing the transmit data to the SFCS3n register and the SFDB3n register from where it is transferred, the data can be stored in the CSIBUFn register while the CSIBUFn pointer for writing is automatically incremented (the CSIBUFn register size is 20 bits x 16) (n = 0, 1). When the chip select outputs SCS3n0 to SCS3n3 are used, write SFCS3n register before the SFDB3n register. However, in slave mode the chip select outputs SCS3n0 to SCSS3n3 keep the inactive level and therefore writing to the SFCS3n register is not necessary. The condition under which transfer is to be started (SFEMPn bit of the SFA3n register = 0) is satisfied when data is written to the lower 8 bits of the SFDB3n register (or SFDB3nL register). If a transfer data length of 9 bits or more is specified (CCLn3 to CCLn0 bits of the CSIL3n register = 0000B, or 1001B to 1111B), data must be written to the SFDB3n register in 16-bit units or to the SFDB3nH and SFDB3nL registers, in that order, in 8-bit units. If the transfer data length is set to 8 bits (CCLn3 to CCLn0 bits = 1000B), data must be written to the SFDB3nL register in 8-bit units or to the SFDB3n register in 16-bit units. If data is written to the SFDB3nL register in 16-bit units, however, the higher 8 bits of the data (of the SFDB3nH register) are ignored and not transferred. The SFFULn bit of the SFA3n register is set to 1 when 16 data exist in the CSIBUFn register and outputs a CSIBUFn overflow interrupt (INTC3nOVF) when the SFFULn bit = 1 and when the 17th transfer data is written. Sixteen data exist in the CSIBUFn register in the single mode (TRMDn bit of the CSIM3n register = 0) when "CSIBUFn pointer value for writing = CSIBUFn pointer value for SIO3n loading, and SFFULn bit = 1". When the CSIBUFn pointer for SIO3n loading is incremented after completion of transfer, the CSIBUFn register has a vacancy of one data (in the consecutive mode (TRMDn bit = 1), the CSIBUFn register does not have a vacancy even if one data has been transferred). Figure 17-11: 19 Function of CSI Data Buffer Register n (CSIBUFn) 16 15 0 CSI data buffer register n (CSIBUFn) 15 CS data 4 Transfer data 4 CS data 3 Transfer data 3 CS data 2 Transfer data 2 CS data 1 Transfer data 1 0 CS data 0 Transfer data 0 15 8 7 8 7 4 3 0 Incremented SIO3n load CSIBUFn pointer Incremented 0 696 0 Transmit data CSI buffer register 3n (SFDB3n) CSIBUF status register 3n (SFA3n) Chip select CSI buffer register 3n (SFCS3n) PD70F3187: PD70F3447: 4 3 SFDB3nL SFCS3n3 to SFCS3n0 Remark: 7 SFPn3 to SFPn0 SFDB3nH 15 Write CSIBUFn pointer n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.3 Data transfer direction specification function The data transfer direction can be changed by using the DIRn bit of the CSIM3n register (n = 0, 1). (1) MSB first (DIRn bit = 0) Figure 17-12: Data Transfer Direction Specification (MSB first) (a) Transfer direction: MSB first, Transfer data length: 8 Bits SCK3n (I/O) SI3n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO3n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 (b) Writing from SFDB3n register to CSIBUFn register 15 8 7 0 SFDB3n Data CSIBUFn 00H SIO3n SO3n SI3n (c) Reading from CSIBUFn register or SFDB3n register 15 SFDB3n (read value) 8 7 Undefined value 0 Data CSIBUFn or SIRB3n SIO3n SO3n Remark: PD70F3187: PD70F3447: SI3n n = 0, 1 n=0 User's Manual U16580EE3V1UD00 697 Chapter 17 (2) Clocked Serial Interface 3 (CSI3) LSB first (DIRn bit = 1) Figure 17-13: Data Transfer Direction Specification (LSB first) (a) Transfer direction: LSB first, Transfer data length: 8 Bits SCK3n (I/O) SI3n (input) DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO3n (output) DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 (b) Writing from SFDB3n register to CSIBUFn register 15 8 7 0 SFDB3n Data CSIBUFn 00H SIO3n SO3n SI3n (c) Reading from CSIBUFn register or SFDB3n register 15 SFDB3n (read value) 8 7 0 Data 00H CSIBUFn or SIRB3n SIO3n SO3n Remark: 698 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 SI3n Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.4 Transfer data length changing function The transfer data length can be set from 8 to 16 bits in 1-bit units, by using the CCLn3 to CCLn0 bits of the CSIL3n register (n = 1, 0). Figure 17-14: Transfer Data Length Changing Function Transfer Data Length: 16 Bits (CCLn3 to CCLn0 Bits of CSIL3n Register = 0000B), Transfer Direction: MSB First (DIRn Bit of CSIM3n Register = 0) SCK3n (I/O) SI3n (input) DI15 DI14 DI13 DI12 DI2 DI1 DI0 SO3n (output) DO15 DO14 DO13 DO12 DO2 DO1 DO0 Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 699 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.5 Function to select serial clock and data phase The serial clock and data phase can be changed by using the CKPn and DAPn bits of the CSIC3n register (n = 0, 1). Figure 17-15: Clock Timing (a) When CKPn bit = 0, DAPn bit = 0 SCK3n SI3n capture D7 SO3n D6 D5 D4 D3 D2 D0 D1 INTC3n interrupt (b) When CKPn bit = 0, DAPn bit = 1 SCK3n SI3n capture SO3n D7 D6 D5 D4 D3 D2 D1 D0 INTC3n interrupt (c) When CKPn bit = 1, DAPn bit = 0 SCK3n SI3n capture D7 SO3n D6 D5 D4 D3 D2 D1 D0 INTC3n interrupt (d) When CKPn bit = 1, DAPn bit = 1 SCK3n SI3n capture SO3n D7 D6 D5 D4 D3 D2 INTC3n interrupt Remark: 700 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 D1 D0 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.6 Master mode The master mode is set and data is transferred with the transfer clock output to the SCK3n pin when the CKS3n2 to CKS3n0 bits of the CSIC3n register are set to a value other than 111B (SCK3n pin input is invalid) (n = 0, 1). The default output level of the SCK3n pin is high when the CKPn bit of the CSIC3n register is 0, and low when the CKPn bit is 1. In master mode the chip select outputs (SCS3n0 to SCS3n3) are effective. Figure 17-16: Master Mode CKPn and DAPn Bits of CSIC3n Register = 00B, Active Level of CS Outputs: Low Level (CSLVn3 to CSLVn0 Bits of CSIL3n Register = 0000B) Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits of CSIL3n Register = 1000B) SCK3n (output) SI3n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO3n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCS3n0 to SCS3n3 (output) Remark: PD70F3187: PD70F3447: CS data n = 0, 1 n=0 User's Manual U16580EE3V1UD00 701 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.7 Slave mode The slave mode is set when the CKS3n2 to CKS3n0 bits of the CSIC3n register are set to 111B, and data is transferred with the transfer clock input to the SCK3n pin (in the slave mode, it is recommended to set the MDLn2 to MDLn0 bits of the CSIC3n register to 000B and set the BRGn stop mode) (n = 0, 1). The chip select outputs (SCS3n0 to SCS3n3) are ineffective in slave mode, the output levels are fixed to inactive level (chip select outputs are effective in master mode only). Figure 17-17: Slave Mode CKPn and DAPn Bits of CSIC3n Register = 00B, Active Level of CS Outputs: Low Level (CSLVn3 to CSLVn0 Bits of CSIL3n Register = 0000B) Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits of CSIL3n Register = 1000B) SCK3n (input) SI3n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO3n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCS3n0 to SCS3n3 (output) H (inactive level) The conditions under which data can be transferred in the slave mode are listed in the table below. Table 17-2: Conditions Under Which Data Can Be Transferred in Slave Mode Transfer Mode Single mode Consecutive mode CTXEn Bit CRXEn Bit Transmission mode 1 0 Data is in CSIBUFn register (SFEMPn bit = 0). - Reception mode 0 1 Dummy data is in CSIBUFn register (SFEMPn bit = 0). SIRB3n register or SIO3n register is empty. Transmission/ reception mode 1 1 Data is in CSIBUFn register (SFEMPn bit = 0). Transmission mode 1 0 Data is in CSIBUFn register (SFEMPn bit = 0). - Reception mode 0 1 Dummy data is in CSIBUFn register (SFEMPn bit = 0). - Transmission/ reception mode 1 1 Data is in CSIBUFn register (SFEMPn bit = 0). - Remarks: 1. CTXEn bit: CRXEn bit: SFEMPn bit: 2. PD70F3187: PD70F3447: 702 CSIBUFn Register Bit 6 of CSIM3n register Bit 5 of CSIM3n register Bit 5 of SFA3n register n = 0, 1 n=0 User's Manual U16580EE3V1UD00 SIRB3n Register and SIO3n Register Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.8 Transfer clock selection function In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), the bit transfer rate can be selected by setting the CKS3n2 to CKS3n0 and MDLn2 to MDLn0 bits of the CSIC3n register (ref. to 17.3 (2) Clocked serial interface clock select register 3n (CSIC30, CSIC31)). 17.5.9 Single mode The single mode is set when the TRMDn bit of the CSIM3n register is 0 (PD70F3187: n = 0, 1, PD70F3447: n = 0). In this mode, transfer is started when the CTXEn bit or CRXEn bit is set to 1 and when data is in the CSIBUFn register (SFEMPn bit = 0 in the SFA3n register). If no data is in the CSIBUFn register (SFEMPn bit = 1), transfer is kept waiting until a given start condition is satisfied. When data is written to the CSIBUFn register while the CTXEn or CRXEn bit is 1, the CSOTn bit of the SFA3n register (transfer status flag) is set to 1, and the chip select data (CS data) corresponding to SIO3n load CSIBUFn pointer is transferred to the chip select output buffer. However, in slave mode (CKS3n2 to CKS3n0 bits of the CSIC3n register = 111B) the chip select outputs (SCS3n0 to SCS3n3) keep always the inactive level. If transfer is not in the wait status, the transfer data indicated by the SIO3n load CSIBUFn pointer is loaded from the CSIBUFn register to the SIO3n register, and transfer processing is started. If the SIRB3n register is empty when one data has been transferred in the reception mode or transmission/reception mode, the received data is stored from the SIO3n register to the SIRB3n register, the transmission/reception completion interrupt (INTC3n) is output, and the SIO3n load CSIBUFn pointer is incremented. If the SIRB3n register is not empty, the next transfer processing is started. However, storing the receive data in the SIRB3n register, outputting the INTC3n interrupt, and incrementing the SIO3n load CSIBUFn pointer are held pending, until the previously received data is read from the SIRB3n register and the SIRB3n register becomes empty. In the transmission mode, the INTC3n interrupt is output and the SIO3n load pointer is incremented when transfer processing of one data has been completed (the SIRB3n register is always empty because no data is stored from the SIO3n register to the SIRB3n register). In all modes (transmission, reception, and transmission/reception modes), if the CSIBUFn register is empty (write CSIBUFn pointer value = SIO3n load CSIBUFn pointer value) when transfer processing of one data has been completed, the CSOTn bit is cleared to 0. The value of the "number of remaining data in the CSIBUFn register (write CSIBUFn pointer - SIO3n load pointer)" can always be read from the SFPn3 to SFPn0 bits of the SFA3n register. Caution: When writing data to the SFDB3n register, be sure to confirm that the SFFULn bit of the SFA3n register is 0. Even if data is written to this register when SFFULn bit is 1, the CSIBUFn overflow interrupt (INTC3nOVF) is output, and the written data is ignored. User's Manual U16580EE3V1UD00 703 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-18: 19 Single Mode 16 15 0 CSI data buffer register n (CSIBUFn) 15 SCS3n0 SCS3n1 SCS3n2 SCS3n3 Note Chip select output buffer CS data 4 Transfer data 4 CS data 3 Transfer data 3 CS data 2 Transfer data 2 CS data 1 Transfer data 1 0 CS data 0 Transfer data 0 Write CSIBUFn pointer Incremented SIO3n load CSIBUFn pointer Incremented Difference 15 8 7 8 7 4 3 0 7 4 3 0 SFDB3nL SFPn3 to SFPn0 Transmit data CSI buffer register 3n (SFDB3n) CSIBUF status register 3n (SFA3n) SFDB3nH 15 0 SFCS3n3 to SFCS3n0 Chip select CSI buffer register 3n (SFCS3n) SO3n SIO3n SIRB3n Note: Transfer of CS data will be performed in master mode only. Remark: 704 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 SI3n Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.10 Consecutive mode The consecutive mode is set when the TRMDn bit of the CSIM3n register is 1 (PD70F3187: n = 0, 1, PD70F3447: n = 0). In this mode, transfer is started when the CTXEn bit or CRXEn bit is 1 and when data is in the CSIBUFn register (SFEMPn bit of the SFA3n register = 0). At this time, set the number of transfer data in advance by using the SFNn3 to SFNn0 bits of the SFN3n register. Seventeen or more transfer data cannot be set. If 17 or more transfer data are written to the CSIBUFn register, the excess data are ignored and not transferred. Do not write data exceeding the number of transfer data specified by the SFNn3 to SFNn0 bits of the SFN3n register to the CSIBUFn register. If no data is in the CSIBUFn register (SFEMPn bit = 1), transfer is kept waiting until a given start condition is satisfied. If data is written to the CSIBUFn register when the CTXEn or CRXEn bit is 1, the CSOTn bit (transfer status flag) of the SFA3n register is set to 1 and the chip select data (CS data) according to the SIO3n load/store CSIBUFn pointer is transferred to the chip select output buffer. However, in slave mode (CKS3n2 to CKS3n0 bits of the CSIC3n register = 111B) the chip select outputs (SCS3n0 to SCS3n3) keep always the inactive level. If transfer is not in the wait status, the transfer data indicated by the SIO3n load/store CSIBUFn pointer is loaded from the CSIBUFn register to SIO3n register. Then transfer processing is started. When transfer processing of one data is completed in the reception mode or transmission/reception mode, the received data is overwritten from the SIO3n register to the transfer data in the CSIBUFn register indicated by the SIO3n load/store CSIBUFn pointer, and then the pointer is incremented. By consecutively reading the transfer data from the SIRB3n register after all data in the CSIBUFn register have been transferred (when the INTC3n interrupt has occurred), the receive data can be sequentially read while the read CSIBUFn pointer is incremented. In the transmission mode, the SIO3n load/store CSIBUFn pointer is incremented when transfer processing of one data has been completed. In all modes (transmission, reception, and transmission/reception modes), when data has been transferred by the value set by the SFNn3 to SFNn0 bits of the SFN3n register, the CSOTn bit is cleared to 0 and the transmission/reception completion interrupt (INTC3n) is output. To transfer the next data, be sure to write 1 to the FPCLRn bit of the SFA3n register and clear all the CSIBUFn pointers to 0. The "number of transferred data (SIO3n load/store CSIBUFn pointer value)" can always be read from the SFPn3 to SFPn0 bits of the SFA3n register. Caution: The SFA3n register is in the same status when transfer data is written (before start of transfer) after the CSIBUFn pointer is cleared (FPCLRn bit of the SFA3n register = 1) and when 16 data have been transferred (SFFULn bit = 0, SFEMPn bit = 1, SFPn3 to SFPn0 bits = 0000B). User's Manual U16580EE3V1UD00 705 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-19: 19 Consecutive Mode 16 15 0 CSI data buffer register n (CSIBUFn) 15 SCS3n0 SCS3n1 SCS3n2 SCS3n3 Note Chip select output buffer Write CSIBUFn pointer CS data 3 Transfer data 3 CS data 2 Transfer data 2 CS data 1 Transfer data 1 0 CS data 0 Transfer data 0 15 8 7 8 7 4 3 0 Incremented Read CSIBUFn pointer 0 7 4 3 0 SFDB3nL SFPn3 to SFPn0 Transmit data CSI buffer register 3n (SFDB3n) CSIBUF status register 3n (SFA3n) SFDB3nH 15 SIO3n load/store CSIBUFn pointer SFCS3n3 to SFCS3n0 Chip select CSI buffer register 3n (SFCS3n) SO3n SIO3n SIRB3n Note: Transfer of CS data will be performed in master mode only. Remark: 706 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Incremented SI3n Incremented Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.11 Transmission mode The transmission mode is set when the CTXEn bit of the CSIM3n register is set to 1 and the CRXEn bit is cleared to 0. In this mode, transmission is started by a trigger that writes transmit data to the SFDB3n register or sets the CTXEn bit to 1 when transmit data is in the SFDB3n register (n = 0, 1). Even in the single mode (TRMDn bit of the CSIM3n register = 0), whether the SIRB3n or SIO3n register is empty has nothing to do with starting transmission. The value input to the SI3n pin during transmission is latched in the shift register (SIO3n) but is not transferred to the SIRB3n and CSIBUFn registers at the end of transmission. The transmission/reception completion interrupt (INTC3n) occurs immediately after data is sent out from the SIO3n register. 17.5.12 Reception mode The reception mode is set when the CTXEn bit of the CSIM3n register is cleared to 0 and CRXEn bit is set to 1. In this mode, reception is started by using the processing of writing dummy data to the SFDB3n register as a trigger (n = 0, 1). In the single mode (TRMDn bit of the CSIM3n register = 0), however, the condition of starting reception includes that the SIRB3n or SIO3n register is empty. (If reception to the SIO3n register is completed when the previously received data is held in the SIRB3n register without being read, the previously received data is read from the SIRB3n register and the wait status continues until the SIRB3n register becomes empty.) The SO3n pin outputs a low level. The transmission/reception completion interrupt (INTC3n) occurs immediately after receive data is transferred from the SIO3n register to the SIRB3n register. 17.5.13 Transmission/reception mode The transmission/reception mode is set when both the CTXEn and CRXEn bits of the CSIM3n register are set to 1. In this mode, transmission/reception is started by using the processing to write transmit data to the SFDB3n register as a trigger (n = 0, 1). In the single mode (TRMDn bit of the CSIM3n register = 0), however, the condition of starting transmission/reception includes that the SIRB3n or SIO3n register is empty. (If reception to the SIO3n register is completed when the previously received data is held in the SIRB3n register without being read, the previously received data is read from the SIRB3n register and the wait status continues until the SIRB3n register becomes empty.) Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 707 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.14 Delay control of transmission/reception completion interrupt (INTC3n) In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), occurrence of the transmission/reception completion interrupt (INTC3n) can be delayed by half a clock (1/2 serial clock), depending on the setting of the CSITn bit of the CSIM3n register (CSITn bit = 1). The CSITn bit is valid only in the master mode. In the slave mode (CKS3n2 to CKS3n0 bits = 111B), setting the CSITn bit to 1 is prohibited (even if set, the INTC3n interrupt is not affected). Caution: If the CSITn bit of the CSIM3n register is set to 1 in the consecutive mode (TRMDn bit of the CSIM3n register = 1), the INTC3n interrupt is not output at the end of data other than the last data set by the SFNn3 to SFNn0 bits of the SFN3n register, but a delay of half a clock can be inserted between each data transfer. Figure 17-20: Delay Control of Transmission/Reception Completion Interrupt (INTC3n): CSITn Bit of the CSIM3n Register = 1, CSWEn Bit of the CSIM3n Register = 0, CKPn and DAPn Bits of the CSIC3n Register = 00B, Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits of the CSIL3n Register = 1000B) Delay SCK3n (output) SI3n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI7 SO3n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO7 INTC3n interrupt Delay Remark: 708 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.15 Transfer wait function In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), starting transfer can be delayed by one clock, depending on the setting of the CSWEn bit of the CSIM3n register (CSWEn bit = 1). The CSWEn bit is valid only in the master mode. In the slave mode (CKS3n2 to CKS3n0 bits = 111B), setting the CSWEn bit to 1 is prohibited (even if set, transfer wait is not inserted). When the transfer wait function is enabled (CSWEn bit = 1), the chip select outputs can be During transfer wait (CSWE bit = 1) the chip select outputs (SCS3n0 to SCS3n3) can be configured for an intermediate inactive level output of half a clock period by setting the CSMDn bit of the CSIM3n register to 1. Figure 17-21: Transfer Wait Function (1/3) (a) Transfer Wait Enabled (CSWEn Bit = 1), INTC3n Delay Disabled (CSITn Bit = 0), CKPn and DAPn Bits = 00B, Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) Intermediate Inactive Chip Select Level Disabled (CSMDn = 0) Wait SCK3n (output) SI3n (input) DI7 DI6 DI5 DI1 DI0 DI7 SO3n (output) DO7 DO6 DO5 DO1 DO0 DO7 INTC3n interrupt SCS3n0 to SCS3n3 (outputs) Remark: PD70F3187: PD70F3447: CS data CS data n = 0, 1 n=0 User's Manual U16580EE3V1UD00 709 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-21: Transfer Wait Function (2/3) (b) Transfer Wait Enabled (CSWEn Bit = 1), INTC3n Delay Disabled (CSITn Bit = 0), CKPn and DAPn Bits = 00B, Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B), Intermediate Inactive Chip Select Level Enabled (CSMDn = 1) Wait SCK3n (output) SI3n (input) DI7 DI6 DI5 DI1 DI0 DI7 SO3n (output) DO7 DO6 DO5 DO1 DO0 DO7 INTC3n interrupt SCS3n0 to SCS3n3 (outputs) CS data CS data <1> <2> Remarks: 1. When the CSIBUFn register is empty at the time of <1>, the chip select pins output an inactive level and maintain it. When the CSIBUFn register is not empty at the time of <1>, the chip select pins output an inactive level up to the time of <2>, and output subsequently the succeeding chip select data Moreover, in single mode (TRMDn bit of the CSIM3n register = 0) the chip select pins output an inactive level from the time <1> and held it pending until the previously receive data is read from the SIRB3n register and the SIRB3n register becomes empty. 2. PD70F3187: PD70F3447: 710 n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-21: Transfer Wait Function (3/3) (c) Transfer Wait Enabled (CSWEn Bit = 1), INTC3n Delay Enabled (CSITn Bit = 1), CKPn and DAPn Bits = 00B, Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B), Intermediate Inactive Chip Select Level Disabled (CSMDn = 0) Delay Wait SCK3n (output) SI3n (input) DI7 DI6 DI5 DI1 DI0 DI7 SO3n (output) DO7 DO6 DO5 DO1 DO0 DO7 INTC3n interrupt SCS3n0 to SCS3n3 (outputs) CS data CS data Delay Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 711 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.16 Output pins (1) SCK3n pin The SCK3n pin outputs a high level when both the CTXEn and CRXEn bits of the CSIM3n register are 0 (n = 0, 1). In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), this pin outputs the default level when the FPCLRn bit of the SFA3n register is set to 1. In the slave mode (CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register), the default output level of the SCK3n pin is fixed to the high level. Table 17-3: CKPn Bit 0 1 Default Output Level of SCK3n Pin CKS3n2 to CKS3n0 Bits Default Output Level of SCK3n Pin 111B (slave mode) High levelNote Other than 111B (master mode) High level 111B (slave mode) High level Other than 111B (master mode) Low level Note: Default value after reset, or value when CSICAEn bit of the CSIM3n register is cleared to 0. Remarks: 1. The output of the SCK3n pin changes if the CKPn bit is rewritten in the master mode. 2. PD70F3187: PD70F3447: (2) n = 0, 1 n=0 SO3n pin The SO3n pin outputs a low level when both the CTXEn and CRXEn bits of the CSIM3n register are 0 (n = 0, 1). This pin outputs a low level when the FPCLRn bit of the SFA3n register is set to 1 (the previous value is retained only in the slave mode (CKS3n2 to CKS3n0 bits of the CSIC3n register = 111B) and when the DAPn bit of the CSIC3n register is 0). Table 17-4: Default Output Level of SO3n Pin Default Output Level of SO3n Pin Low levelNote Note: Default value after reset, or value when CSICAEn bit of the CSIM3n register is cleared to 0 Remark: 712 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 (3) Clocked Serial Interface 3 (CSI3) SCS3n0 to SCS3n3 pins The SCS3n0 to SCS3n3 pins output the default level when both the CTXEn and CRXEn bits of the CSIM3n register are 0, or when the CSICAEn bit of the CSIM3n register is cleared to 0 (n = 0, 1). These pins output the default level when the FPCLRn bit of the SFA3n register is set to 1. In slave mode these pins output always the default level (inactive level). Table 17-5: Default Output Level of SCS3n0 to SCS3n3 Pins CSLVn Bit Default Output Level of SCS3n0 to SCS3n3 Pins 0 High 1 Low level levelNote Note: Default value after reset. Remark: PD70F3187: PD70F3447: n = 0, 1 n=0 17.5.17 CSIBUFn overflow interrupt signal (INTC3nOVF) The INTC3nOVF interrupt is output when 16 data exist in the CSIBUFn register and when the 17th data is written (to the SFDB3n or SFDB3nL register). The 17th data is not written but ignored. In the single mode (TRMDn bit of the CSIM3n register = 0), 16 data exist in the CSIBUFn register when "write CSIBUFn pointer value = SIO3n load CSIBUFn pointer value" and SFFULn bit of the SFA3n register = 1. When transfer is completed and the SIO3n load CSIBUFn pointer is incremented, the CSIBUFn register has one vacancy (the CSIBUFn register has no vacancy even when transfer of one data has been completed in the consecutive mode (TRMDn bit = 1)). User's Manual U16580EE3V1UD00 713 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6 Operating Procedures 17.6.1 Single mode (master mode, transmission mode) Figure 17-22: Single Mode (Master Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CSIBUF3n [1] AAH CSIBUF3n [2] CCH SCK3n pin SO3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 H (inactive) CS0 1 1 0 0 1 1 0 0 CS1 CS2 CSOTn flag INTC3n signal SFP3 to SFP0 bits 0H <1> <5> <2> <3> <4> 1H <6> 2H 1H 0H <6> 1H <6> 0H <7> Note Note: During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0) in order to start the transfer. Remark: 714 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <6> Confirm that the SFFULn bit of the SFA3n register is 0, and then write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is 0. <7> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit of the SFA3n register is 1, and disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Remarks: 1. To execute a further transfer, repeat <6> before <7>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 715 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.2 Single mode (master mode, reception mode) Figure 17-23: Single Mode (Master Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CRXEn bit SFDB3n register write SFEMPn flag dummy CSIBUF3n [0] dummy CSIBUF3n [1] dummy CSIBUF3n [2] SCK3n pin SI3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 H (inactive) CS0 1 1 0 0 1 1 0 0 CS1 CS2 CSOTn flag INTC3n signal SIRB3n register CCH AAH 55H SIRB3n register read SFP3 to SFP0 bits 0H <1> <5> <2> <3> <4> 1H <6> 2H <6> 0H 1H <7> Note 1 0H 1H <6> <7> <7> <8> Note 2 Notes: 1. While the SIRB3n register is full a new transfer start of reception from the slave is put on hold until the SIRB3n register is read. 2. During this period a reception from the slave is put on hold until at least one dummy transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0) in order to start the transfer. Remark: 716 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 <1> <2> <3> <4> <5> <6> <7> <8> Clocked Serial Interface 3 (CSI3) When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. Confirm that the SFFULn bit of the SFA3n register is 0, and then write first CS data to the SFCS3n register and subsequently write dummy transfer data to the SFDB3n register (reception start trigger). If it is clearly known that the SFFULn bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is 0. Confirm that the INTC3n interrupt has occurred, and then read the SIRB3n register. Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1, and disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Remarks: 1. To execute a further transfer, repeat <6> and <7> before <8>. Perform writing dummy transfer data in <6> every time transfer is executed. 2. The SO3n pin output is fixed to low level (default value). 3. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 717 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.3 Single mode (master mode, transmission/reception mode) Figure 17-24: Single Mode (Master Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit, CRXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CSIBUF3n [1] AAH CSIBUF3n [2] 33H SCK3n pin SO3n pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 SI3n pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 CS0 CS2 SCS3n0 to SCS3n3 pins H (inactive) CS1 CSOTn flag INTC3n signal SIRB3n register 99H 96H CCH SIRB3n register read SFP3 to SFP0 bits 0H <1> <5> <2> <3> <4> 1H <6> 2H <6> 0H 1H <7> Note 1 0H 1H <6> <7> <7> <8> Note 2 Notes: 1. While the SIRB3n register is full a new transfer start of reception from the slave is put on hold until the SIRB3n register is read. 2. During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0) in order to start the transfer. Remark: 718 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 <1> <2> <3> <4> <5> <6> <7> <8> Clocked Serial Interface 3 (CSI3) When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting the CTXEn and CRXEn bits to 1. Confirm that the SFFULn bit of the SFA3n register is 0, and then write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is 0. Confirm that the INTC3n interrupt has occurred, and then read the SIRB3n register. Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1, and disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Remarks: 1. To execute a further transfer, repeat <6> before <7>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 719 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.4 Single mode (slave mode, transmission mode) Figure 17-25: Single Mode (Slave Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CSIBUF3n [1] AAH CSIBUF3n [2] CCH SCK3n pin SO3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 H (inactive level) CSOTn flag INTC3n signal SFP3 to SFP0 bits 0H 1H <6> <1> <5> <2> <3> Note <4> 2H 1H 0H 1H <6> <6> 0H <7> Note Note: During this period a transmission to the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0). Remark: 720 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <6> Confirm that the SFFULn bit of the SFA3n register is 0, and then write transfer data to the SFDB3n register. Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always output the inactive level, writing of CS data to the SFCS3n register is not necessary. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is 0. <7> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1, and disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Remarks: 1. To execute a further transfer, repeat <6> before <7>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 721 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.5 Single mode (slave mode, reception mode) Figure 17-26: Single Mode (Slave Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CRXEn bit SFDB3n register write SFEMPn flag dummy CSIBUF3n [0] dummy CSIBUF3n [1] dummy CSIBUF3n [2] SCK3n pin SI3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 H (inactive level) CSOTn flag INTC3n signal SIRB3n register CCH AAH 55H SIRB3n register read SFP3 to SFP0 bits 0H 1H <1> <5> <6> <2> <3> Note 1 <4> 2H <6> 0H 1H 1H <7> <7><6> 0H <7> <8> Note 1 Note 2 Notes: 1. During this period a transmission/reception from the master will be ignored until at least one dummy transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0). 2. While the SIRB3n register is full a new reception from the master will be ignored until the SIRB3n register is read. Remark: 722 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 <1> <2> <3> <4> <5> <6> <7> <8> Clocked Serial Interface 3 (CSI3) When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. Confirm that the SFFULn bit of the SFA3n register is 0, and then write dummy transfer data to the SFDB3n register (reception start trigger). Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always output the inactive level, writing of CS data to the SFCS3n register is not necessary. If it is clearly known that the SFFULn bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is 0. Confirm that the INTC3n interrupt has occurred, and then read the SIRB3n register. Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1, and disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Remarks: 1. To execute a further transfer, repeat <6> and <7> before <8>. Perform writing dummy transfer data in <6> every time transfer is executed. 2. The SO3n pin output is fixed to low level (default value). 3. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 723 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.6 Single mode (slave mode, transmission/reception mode) Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit, CRXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CSIBUF3n [1] AAH CSIBUF3n [2] 33H SCK3n pin SO3n pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 SI3n pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 SCS3n0 to SCS3n3 pins H (inactive level) CSOTn flag INTC3n signal SIRB3n register 99H 96H CCH SIRB3n register read SFP3 to SFP0 bits 0H 1H <6> <1> <5> <2> <3> Note 1 <4> 2H <6> 0H 1H <7> 0H 1H <6> <7> <7> <8> Note 1 Note 2 Notes: 1. During this period a transmission/reception from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0). 2. While the SIRB3n register is full a new transmission/reception from the master will be ignored until the SIRB3n register is read. Remark: 724 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 <1> <2> <3> <4> <5> <6> <7> <8> Clocked Serial Interface 3 (CSI3) When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting the CTXEn and CRXEn bits to 1. Confirm that the SFFULn bit of the SFA3n register is 0, and then write transfer data to the SFDB3n register. Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always output the inactive level, writing of CS data to the SFCS3n register is not necessary. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is 0. Confirm that the INTC3n interrupt has occurred, and then read the SIRB3n register. Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1, and disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Remarks: 1. To execute a further transfer, repeat <6> and <7> before <8>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 725 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.7 Consecutive mode (master mode, transmission mode) Figure 17-28: Consecutive Mode (Master Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CSIBUF3n [1] AAH CSIBUF3n [2] CCH SCK3n pin SO3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 H (inactive) CS0 1 1 0 0 1 1 0 0 CS1 CS2 CSOTn flag INTC3n signal SFN3 to SFN0 bits SFP3 to SFP0 bits 3H 0H <1> <5> <7> <2> <6> <3> <4> 1H 3H 2H <7> <7> 0H <8> <10> <9> Note Note: During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0) in order to start the transfer. 726 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <6> Set the number of data to be transmitted by using the SFNn3 to SFNn0 bits of the SFN3n register. <7> Write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register. Writing data exceeding the set value of the SFN3n register is prohibited. <8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <9> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <10> Disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Remarks: 1. To execute a further transfer, repeat <6> to <9> before <10>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 727 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.8 Consecutive mode (master mode, reception mode) Figure 17-29: Consecutive Mode (Master Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CRXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] dummy CSIBUF3n [1] 55H dummy AAH CSIBUF3n [2] dummy CCH SCK3n pin SI3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 H (inactive) CS0 1 1 0 0 1 1 0 0 CS1 CS2 CSOTn flag INTC3n signal SIRB3n register read SFN3 to SFN0 bits SFP3 to SFP0 bits 3H 0H <7> <1> <5> <6> <2> <3> <4> 1H 3H 2H <7> <7> Note 0H <8> <8> <11> <8> <9> <10> Note: During this period a reception from the slave is put on hold until at least one dummy transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0) in order to start the transfer. Remark: 728 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. <6> Set the number of data to be received by using the SFNn3 to SFNn0 bits of the SFN3n register. <7> Write first CS data to the SFCS3n register and subsequently write dummy transfer data to the SFDB3n register (reception start trigger). Writing dummy data exceeding the set value of the SFN3n register is prohibited. <8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then read the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <9> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <11> Disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Remarks: 1. To execute a further transfer, repeat <6> to <10> before <11>. Perform writing dummy transfer data in <7> every time transfer is executed. 2. The SO3n pin output is fixed to low level (default value). 3. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 729 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.9 Consecutive mode (master mode, transmission/reception mode) Figure 17-30: Consecutive Mode (Master Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit, CRXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CCH CSIBUF3n [1] 96H AAH CSIBUF3n [2] 33H 99H SCK3n pin SO3n pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 SI3n pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 SCS3n0 to SCS3n3 pins H (inactive) CS0 CS1 CS2 CSOTn flag INTC3n signal SIRB3n register read SFN3 to SFN0 bits SFP3 to SFP0 bits 3H 0H <7> <1> <5> <6> <2> <3> <4> 1H 3H 2H <7> <7> Note 0H <8> <8> <11> <8> <9> <10> Note: During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0) in order to start the transfer. Remark: 730 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting both the CTXEn and CRXEn bits to 1. <6> Set the number of data to be transmitted/received by using the SFNn3 to SFNn0 bits of the SFN3n register. <7> Write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register. Writing data exceeding the set value of the SFN3n register is prohibited. <8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then read the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <9> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <11> Disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Remarks: 1. To execute a further transfer, repeat <6> to <10> before <11>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 731 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.10 Consecutive mode (slave mode, transmission mode) Figure 17-31: Consecutive Mode (Slave Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CSIBUF3n [1] AAH CSIBUF3n [2] CCH SCK3n pin SO3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 H (inactive) CSOTn flag INTC3n signal SFN3 to SFN0 bits SFP3 to SFP0 bits 3H 0H <1> <5> <7> <2> <6> <3> <4> 1H <7> 3H 2H <7> 0H <8> <10> <9> Note Note: During this period a reception request from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0). Remark: 732 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <6> Set the number of data to be transmitted by using the SFNn3 to SFNn0 bits of the SFN3n register. <7> Write transfer data to the SFDB3n register. Writing data exceeding the set value of the SFN3n register is prohibited. Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always output the inactive level, writing of CS data to the SFCS3n register is not necessary. <8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <9> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <10> Disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Remarks: 1. To execute a further transfer, repeat <6> to <9> before <10>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 733 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.11 Consecutive mode (slave mode, reception mode) Figure 17-32: Consecutive Mode (Slave Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CRXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] dummy CSIBUF3n [1] 55H dummy AAH dummy CSIBUF3n [2] CCH SCK3n pin SI3n pin SCS3n0 to SCS3n3 pins 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 H (inactive) CSOTn flag INTC3n signal SIRB3n register read SFN3 to SFN0 bits SFP3 to SFP0 bits 3H 0H <7> <1> <5> <6> <2> <3> <4> 1H <7> 3H 2H <7> Note 0H <8> <8> <11> <8> <9> <10> Note: During this period a transmission from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0). Remark: 734 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. <6> Set the number of data to be received by using the SFNn3 to SFNn0 bits of the SFN3n register. <7> Write dummy transfer data to the SFDB3n register (reception start trigger). Writing dummy data exceeding the set value of the SFN3n register is prohibited. Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always output the inactive level, writing of CS data to the SFCS3n register is not necessary. <8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then read the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <9> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <11> Disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Remarks: 1. To execute a further transfer, repeat <6> to <10> before <11>. Perform writing dummy transfer data in <7> every time transfer is executed. 2. The SO3n pin output is fixed to low level (default value). 3. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 735 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.12 Consecutive mode (in slave mode and transmission/reception mode) Figure 17-33: Consecutive Mode (Slave Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B) CTXEn bit, CRXEn bit SFDB3n register write SFEMPn flag CSIBUF3n [0] 55H CCH CSIBUF3n [1] 96H AAH CSIBUF3n [2] 33H 99H SCK3n pin SO3n pin 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 SI3n pin 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 SCS3n0 to SCS3n3 pins H (inactive) CSOTn flag INTC3n signal SIRB3n register read SFN3 to SFN0 bits SFP3 to SFP0 bits 3H 0H <7> <1> <5> <6> <2> <3> <4> 1H <7> 3H 2H <7> Note 0H <8> <8> <11> <8> <9> <10> Note: During this period a transmission/reception from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of SFA3n register = 0). Remark: 736 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> <2> <3> <4> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. Specify the transfer mode by setting the CSIC3n and CSIL3n registers. Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting both the CTXEn and CRXEn bits to 1. <6> Set the number of data to be transmitted/received by using the SFNn3 to SFNn0 bits of the SFN3n register. <7> Write transfer data to the SFDB3n register. Writing data exceeding the set value of the SFN3n register is prohibited. Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always output the inactive level, writing of CS data to the SFCS3n register is not necessary. <8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then read the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <9> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <11> Disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Remarks: 1. To execute a further transfer, repeat <6> to <10> before <11>. 2. PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 737 Chapter 17 Clocked Serial Interface 3 (CSI3) 17.7 Cautions The following points must be observed when using CSI3n. Cautions: 1. The CSI3n unit is reset and CSI3n is stopped when the CSICAEn bit of the CSIM3n register is cleared to 0. To operate CSI3n, first set the CSICAEn bit to 1. Usually, before clearing the CSICAEn bit to 0, clear both the CTXEn and CRXEn bits to 0 (after the end of transfer). 2. Be sure to write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0 before enabling transfer by setting the CTXEn or CRXEn bit of the CSIM3n register to 1. If the CTXEn or CRXEn bit is set to 1 without clearing the pointers, and if the previously transferred data remains in the CSIBUFn register, transferring that data is immediately started. If transfer data is set to the CSIBUFn register before transfer is enabled, transfer is started as soon as the CTXEn or CRXEn bit is set to 1. 3. If the SFA3n register is read immediately after data has been written to the SFDB3n and SFDB3nL registers, the SFFULn, SFEMPn, and SFPn3 to SFPn0 bits of the SFA3n register may not change their values in time. If the SFA3n register is read before the SFFULn bit is set to 1 and a 17th data is written, the CSIBUFn overflow interrupt (INTC3nOVF) occurs. 4. When using CSI3n in configuration with DMA transfer, observe that only single mode is permitted (TRMDn bit of CSIM3n register = 0), and chip select CSI registers (SFCS3n, SFCS3nL) are not supported. Remark: 738 PD70F3187: PD70F3447: n = 0, 1 n=0 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller The V850E/PH2 microcontrollers feature an on-chip n-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The number of channels is given in the table below: PD70F3447 uPD70F3187 1 2 Channels Names CAN0 CAN0 to CAN1 Throughout this chapter, the individual channels of CAN are identified by "n", for example, C0GMCTRL for the CAN0 global control register. Throughout this chapter, the CAN message buffer registers are identified by "m" (m = 0 to 31), for example C0MDATA4m for CAN0 message data byte 4 of message buffer register m. 18.1 Features * Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) * Standard frame and extended frame transmission/reception enabled * Transfer rate: 1 Mbps max. (if CAN clock input 8 MHz, for 32 channels) * 32 message buffers per channel * Receive/transmit history list function * Automatic block transmission function * Multi-buffer receive block function * Mask setting of four patterns is possible for each channel User's Manual U16580EE3V1UD00 739 Chapter 18 AFCAN Controller 18.1.1 Overview of functions Table 18-1 presents an overview of the CAN Controller functions. Table 18-1: Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Baud rate Maximum 1 Mbps (CAN clock input 8 MHz) Data storage Storing messages in the CAN RAM Number of messages * 32 message buffers per channel * Each message buffer can be set to be either a transmit message buffer or a receive message buffer. Message reception * Unique ID can be set to each message buffer. * Mask setting of four patterns is possible for each channel. * A receive completion interrupt is generated each time a message is received and stored in a message buffer. * Two or more receive message buffers can be used as a FIFO receive buffer (multi-buffer receive block function). * Receive history list function Message transmission * Unique ID can be set to each message buffer. * Transmit completion interrupt for each message buffer * Message buffer number 0 to 7 specified as the transmit message buffer can be set for automatic block transfer. Message transmission interval is programmable (automatic block transmission function (hereafter referred to as "ABT")). * Transmission history list function Remote frame processing Remote frame processing by transmit message buffer Time stamp function * The time stamp function can be set for a message reception when a 16-bit timer is used in combination. * Time stamp capture trigger can be selected (SOF or EOF in a CAN message frame can be detected.). * The time stamp function can be set for a transmit message. Diagnostic function * * * * * * Readable error counters "Valid protocol operation flag" for verification of bus connections Receive-only mode Single-shot mode CAN protocol error type decoding Self-test mode Release from bus-off state * Forced release from bus-off (by ignoring timing constraint) possible by software. * No automatic release from bus-off (software must re-enable). Power save mode 740 * CAN Sleep mode (can be woken up by CAN bus) * CAN Stop mode (cannot be woken up by CAN bus) User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.1.2 Configuration The CAN Controller is composed of the following four blocks. * NPB interface This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU. * MAC (Memory Access Controller) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module. * CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings. * CAN RAM This is the CAN memory functional block, which is used to store message IDs, message data, etc. Figure 18-1: Block Diagram of CAN Module CPU Interrupt request NPB (NEC Peripheral I/O Bus) INTTRXn INTRECn INTERRn INTWUPn CAN bus CAN module MCM (Message Control Module) CAN Protocol Layer CANTXn CANRXn CAN transceiver CAN_H CAN_L CAN RAM Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 C1MASK1 C1MASK2 C1MASK3 C1MASK4 ... NPB interface Message buffer m User's Manual U16580EE3V1UD00 741 Chapter 18 AFCAN Controller 18.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control. The composition of these layers is illustrated below. Figure 18-2: * Logical link control (LLC) Higher Data link layer Note Lower Composition of Layers * Medium access control (MAC) Physical layer * Acceptance filtering * Overload report * Recovery management * Data capsuled/not capsuled * Frame coding (stuffing/no stuffing) * Medium access management * Error detection * Error report * Acknowledgement * Seriated/not seriated Prescription of signal level and bit description Note: CAN Controller specification 18.2.1 Frame format (1) Standard format frame * The standard format frame uses 11-bit identifiers, which means that it can handle up to 2,048 messages. (2) Extended format frame * The extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of messages that can be handled to 2,048 x 218 messages. * An extended format frame is set when "recessive level" (CMOS level of "1") is set for both the SRR and IDE bits in the arbitration field. 742 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 18-2: Frame Type (1) Frame types Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame Frame used to delay the next data frame or remote frame Bus value The bus values are divided into dominant and recessive. * Dominant level is indicated by logical 0. * Recessive level is indicated by logical 1. * When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 18.2.3 Data frame and remote frame (1) Data frame A data frame is composed of seven fields. Figure 18-3: Data Frame Data frame R D <1> <2> <3> <4> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) Note: D: Dominant = 0 R: Recessive = 1 User's Manual U16580EE3V1UD00 743 Chapter 18 (2) AFCAN Controller Remote frame A remote frame is composed of six fields. Figure 18-4: Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Notes: 1. The data field is not transferred even if the control field's data length code is not "0000B". 2. D: Dominant = 0 R: Recessive = 1 (3) Description of fields (a) Start of frame (SOF) The start of frame field is located at the start of a data frame or remote frame. Figure 18-5: (Interframe space or bus idle) Start of frame (SOF) Start of frame (Arbitration field) R D 1 bit Note: D: Dominant = 0 R: Recessive = 1 * If dominant level is detected in the bus idle state, a hard-synchronization is performed (the current TQ is assigned to be the SYNC segment). * If dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a SOF. If recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbance only. No error frame is generated in such case. 744 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller (b) Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 18-6: Arbitration field (in standard format mode) Arbitration field (Control field) R D Identifier RTR ID28 * * * * * * * * * * * * * * * * * * * * * * * * * * ID18 (11 bits) (1 bit) IDE (r1) r0 (1 bit) Cautions: 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Note: D: Dominant = 0 R: Recessive = 1 Figure 18-7: Arbitration field (in extended format mode) Arbitration field (Control field) R D Identifier SRR IDE Identifier RTR r1 r0 ID28 * * * * * * * * * * * * * * * * * * * ID18 ID17 * * * * * * * * * * * * * * * * * * * * * * ID0 (11 bits) (1 bit) (1 bit) (18 bits) (1 bit) Cautions: 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Note: D: Dominant = 0 R: Recessive = 1 Table 18-3: RTR frame settings Frame Type RTR Bit Data frame 0 (D) Remote frame 1 (R) User's Manual U16580EE3V1UD00 745 Chapter 18 Table 18-4: AFCAN Controller Frame format setting (IDE bit) and number of identifier (ID) bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None 0 (D) 11 bits Extended format mode 1 (R) 1 (R) 29 bits (c) Control field The control field sets "DLC" as the number of data bytes in the data field (DLC = 0 to 8). Figure 18-8: (Arbitration field) Control field Control field (Data field) R D RTR r1 (IDE) r0 DLC3 DLC2 DLC1 DLC0 Note: D: Dominant = 0 R: Recessive = 1 In a standard format frame, the control field's IDE bit is the same as the r1 bit. Table 18-5: Data length setting Data Length Code DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes Other than above Caution: 746 Data Byte Count 8 bytes regardless of the value of DLC3 to DLC0 In the remote frame, there is no data field even if the data length code is not 0000B. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller (d) Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 18-9: (Control field) Data field Data field (CRC field) R D Data 0 (8 bits) MSB Data 7 (8 bits) MSB LSB LSB Note: D: Dominant = 0 R: Recessive = 1 (e) CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. Figure 18-10: (Data field or control field) CRC field CRC field (ACK field) R D CRC sequence (15 bits) CRC delimiter (1 bit) Note: D: Dominant = 0 R: Recessive = 1 * The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as follows. P(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 * Transmitting node: Transmits the CRC sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. * Receiving node: Compares the CRC sequence calculated using data bits that exclude the stuffing bits in the receive data with the CRC sequence in the CRC field. If the two CRC sequences do not match, the node issues an error frame. User's Manual U16580EE3V1UD00 747 Chapter 18 AFCAN Controller (f) ACK field The ACK field is used to acknowledge normal reception. Figure 18-11: (CRC field) ACK field ACK field (End of frame) R D ACK slot (1 bit) ACK delimiter (1 bit) Note: D: Dominant = 0 R: Recessive = 1 * If no CRC error is detected, the receiving node sets the ACK slot to the dominant level. * The transmitting node outputs two recessive-level bits. (g) End of frame (EOF) The end of frame field indicates the end of data frame/remote frame. Figure 18-12: (ACK field) End of frame End of frame (EOF) (Interframe space or overload frame) R D (7 bits) Note: D: Dominant = 0 R: Recessive = 1 748 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller (h) Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. * The bus state differs depending on the error status. - Error active node The interframe space consists of a 3-bit intermission field and a bus idle field. Figure 18-13: (Frame) Interframe space (error active node) Interframe space (Frame) R D Intermission (3 bits) Bus idle (0 to bits) Notes: 1. Bus idle: State in which the bus is not used by any node. 2. D: Dominant = 0 R: Recessive = 1 - Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. Figure 18-14: (Frame) R D Interframe space (error passive node) Interframe space Intermission (3 bits) Notes: 1. Bus idle: Suspend transmission: Suspend transmission (8 bits) (Frame) Bus idle (0 to bits) State in which the bus is not used by any node. Sequence of 8 recessive-level bits transmitted from the node in the error passive status. 2. D: Dominant = 0 R: Recessive = 1 Usually, the intermission field is 3 bits. If the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. User's Manual U16580EE3V1UD00 749 Chapter 18 * AFCAN Controller Operation in error status Table 18-6: Operation in error status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. 18.2.4 Error frame An error frame is output by a node that has detected an error. Figure 18-15: Error frame Error frame R D (<4>) <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<5>) Interframe space or overload frame Error delimiter Error flag 2 Error flag 1 Error bit Note: D: Dominant = 0 R: Recessive = 1 Table 18-7: No. <1> Name Definition of error frame fields Bit count Error flag 1 6 Definition Error active node: Error passive node: Outputs 6 dominant-level bits consecutively. Outputs 6 recessive-level bits consecutively. If another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> Error flag 2 0 to 6 Nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> Error delimiter 8 Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Error bit - The bit at which the error was detected. The error flag is output from the bit next to the error bit. In the case of a CRC error, this bit is output following the ACK delimiter. <5> Interframe space/overload frame - An interframe space or overload frame starts from here. 750 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.2.5 Overload frame An overload frame is transmitted under the following conditions. * When the receiving node has not completed the reception operation * If a dominant level is detected at the first two bits during intermission * If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter Note: The CAN is internally fast enough to process all received frames not generating overload frames. Figure 18-16: Overload frame Overload frame R D (<4>) <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<5>) Interframe space or overload frame Overload delimiter Overload flag Overload flag Frame Note: D: Dominant = 0 R: Recessive = 1 Table 18-8: No <1> <2> Name Definition of overload frame fields Bit count Overload flag 6 Overload flag from other node <4> <5> Frame Interframe space/overload frame Outputs 6 dominant-level bits consecutively. 0 to 6 The node that received an overload flag in the interframe space outputs an overload flag. 8 Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. - Output following an end of frame, error delimiter, or overload delimiter. Overload delimiter <3> Definition - An interframe space or overload frame starts from here. User's Manual U16580EE3V1UD00 751 Chapter 18 AFCAN Controller 18.3 Functions 18.3.1 Determining bus priority (1) * When a node starts transmission: During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: * The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). * The transmitting node compares its output arbitration field and the data level on the bus. Table 18-9: Determining bus priority Level match Level mismatch (3) * Continuous transmission Stops transmission at the bit where mismatch is detected and starts reception at the following bit Priority of data frame and remote frame When a data frame and a remote frame are on the bus, the data frame has priority because its RTR bit, the last bit in the arbitration field, carries a dominant level. Remark: If the extended-format data frame and the standard-format remote frame conflict on the bus (if ID28 to ID18 of both of them are the same), the standard-format remote frame takes priority. 18.3.2 Bit stuffing Bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues for 5 bits, in order to prevent a burst error. Table 18-10: 752 Bit stuffing Transmission During the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, 1 inverted-level bit of data is inserted before the following bit. Reception During the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, reception is continued after deleting the next bit. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 18.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 18.3.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function puts the CAN Controller in waiting mode to achieve low power consumption. The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access). 18.3.6 Error control function (1) Error types Table 18-11: Type Error types Description of error Detection method Detection condition Detection state Transmission/Reception Field/Frame Bit error Comparison of the output level and level on the bus (except stuff bit) Mismatch of levels Transmitting/ receiving node Bit that is outputting data on the bus at the start of frame to end of frame, error frame and overload frame. Stuff error Check of the receive data at the stuff bit 6 consecutive bits of the same output level Receiving node Start of frame to CRC sequence CRC error Comparison of the CRC sequence generated from the receive data and the received CRC sequence Mismatch of CRC Receiving node CRC field Form error Field/frame check of the fixed format Detection of fixed format violation Receiving node CRC delimiter ACK field End of frame Error frame Overload frame ACK error Check of the ACK slot by the transmitting node Detection of recessive level in ACK slot Transmitting node ACK slot User's Manual U16580EE3V1UD00 753 Chapter 18 (2) Output timing of error frame Table 18-12: Type (3) AFCAN Controller Output timing of error frame Output Timing Bit error, stuff error, form error, ACK error Error frame output is started at the timing of the bit following the detected error. CEC error Error frame output is started at the timing of the bit following the ACK delimiter. Processing in case of error The transmission node re-transmits the data frame or remote frame after the error frame. (However, it does not re-transmit the frame in the single-shot mode.) (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification: * Error active * Error passive * Bus-off These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error counter bits) and the REC6 to REC0 bits (reception error counter bits) as shown in Table 18-13, "Types of error states," on page 755. The present error state is indicated by the CAN module information register (CnINFO). When each error counter value becomes equal to or greater than the error warning level (96), the TECS0 or RECS0 bit of the CnINFO register is set to 1. In this case, the bus state must be tested because it is considered that the bus has a serious fault. An error counter value of 128 or more indicates an error passive state and the TECS1 or RECS1 bit of the CnINFO register is set to 1. * If the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the BOFF bit of the CnINFO register is set to 1. * If only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected only to the local station), ACK is not returned even if data is transmitted. Consequently, re-transmission of the error frame and data is repeated. In the error passive state, however, the transmission error counter is not incremented and the bus-off state is not reached. 754 User's Manual U16580EE3V1UD00 Chapter 18 Table 18-13: Type Error active Error passive Bus-off Operation Value of Error Counter AFCAN Controller Types of error states Indication of CnINFO Register Transmission 0 to 95 TECS1, TECS0 = 00 Reception 0 to 95 RECS1, RECS0 = 00 Transmission 96 to 127 TECS1, TECS0 = 01 Reception 96 to 127 RECS1, RECS0 = 01 Transmission 128 to 255 TECS1, TECS0 = 11 Reception 128 or more RECS1, RECS0 = 11 Transmission 256 or more (not indicated) Note BOFF = 1, TECS1, TECS0 = 11 Operation Specific to Error State Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error. Outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. Transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). Communication is not possible. Messages are not stored when receiving frames, however, the following operations of <1>, <2>, and <3> are done. <1> TSOUT toggles. <2> REC is incremented/decremented. <3> VALID bit is set. If the CAN module is entered to the initialization mode and then transition request to any operation mode is made, and when 11 consecutive recessive-level bits are detected 128 times, the error counter is reset to 0 and the error active state can be restored. Note: The value of the transmission error counter (TEC) is invalid when the BOFF bit is set to 1. If an error that increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the counter is not incremented and the bus-off state is assumed. User's Manual U16580EE3V1UD00 755 Chapter 18 AFCAN Controller (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 18-14: State Error counter Transmission error counter (TEC7 to TEC0 Bits) Reception error counter (REC6 to REC0 Bits) Receiving node detects an error (except bit error in the active error flag or overload flag). No change +1 (when REPS = 0) Receiving node detects dominant level following error flag of error frame. No change +8 (when REPS = 0) Transmitting node transmits an error flag. +8 [As exceptions, the error counter does not change in the following cases.] <1> ACK error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> A stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. No change Bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 No change Bit error detection while active error flag or overload flag is being output (error-active receiving node) No change +8 (REPS bit = 0) When the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominantlevel bits. When the node detects 8 consecutive dominant levels after a passive error flag +8 (transmitting) +8 (during reception, when REPS = 0) When the transmitting node has completed transmission without error (0 if error counter = 0) -1 No change When the receiving node has completed reception without error No change * -1 (1 REC6 to REC0 127, when REPS = 0) * 0 (REC6 to REC0 = 0, when REPS = 0) * Value of 119 to 127 is set (when REPS = 1) (c) Occurrence of bit error in intermission An overload frame is generated. Caution: 756 If an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. The value of the error counter is incremented after the error flag has been output. User's Manual U16580EE3V1UD00 Chapter 18 (5) AFCAN Controller Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTXDn) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1> A request to enter the CAN initialization mode <2> A request to enter a CAN operation mode (a)Recovery operation through normal recovery sequence (b)Forced recovery operation that skips recovery sequence (a) Recovery from bus-off state through normal recovery sequence The CAN module first issues a request to enter the initialization mode (refer too timing <1> in Figure 18-17, "Recovery from bus-off state through normal recovery sequence," on page 758). This request will be immediately acknowledged, and the OPMODE bits of the CnCTRL. register are cleared to 000B. Processing such as analyzing the fault that has caused the bus-off state, redefining the CAN module and message buffer using application software, or stopping the operation of the CAN module can be performed by clearing the GOM bit to 0. Next, the module requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in Figure 18-17). This starts an operation to recover the CAN module from the bus-off state. The conditions under which the module can recover from the bus-off state are defined by the CAN protocol ISO 11898, and it is necessary to detect 11 consecutive recessivelevel bits 128 times. At this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. When the recovery conditions are satisfied (refer to timing <3> in Figure 18-17), the CAN module can enter the operation mode it has requested. Until the CAN module enters this operation mode, it stays in the initialization mode. Completion to be requested operation mode can be confirmed by reading the OPMODE bits of the CnCTRL register. During the bus-off period and bus-off recovery sequence, the BOFF bit of the CnINFO register stays set (to 1). In the bus-off recovery sequence, the reception error counter (REC[6:0]) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. Therefore, the recovery state can be checked by reading REC[6:0]. Caution: In the bus-off recovery sequence, REC[6:0] counts up (+1) each time 11 consecutive recessive-level bits have been detected. Even during the bus-off period, the CAN module can enter the CAN sleep mode or CAN stop mode. To start the bus-off recovery sequence, it is necessary to transit to the initialization mode once. However, when the CAN module is in either CAN sleep mode or CAN stop mode, transition request to the initialization mode is not accepted, thus you have to release the CAN sleep mode first. In this case, as soon as the CAN sleep mode is released, the bus-off recovery sequence starts and no transition to initialization mode is necessary. If the can module detects a dominant edge on the CAN bus while in sleep mode even during bus-off, the sleep mode will be left and the bus-off recovery sequence will start. User's Manual U16580EE3V1UD00 757 Chapter 18 Figure 18-17: AFCAN Controller Recovery from bus-off state through normal recovery sequence TEC > FFH bus-off error-passive bus-off-recovery-sequence error-active BOFF bit in CnINFO register <1> OPMODE[2:0] in CnCTRL register (user writings) 00H OPMODE[2:0] in CnCTRL register (user readings) 00H <2> 00H 00H <3> TEC[7:0] in CnERC 80H TEC[7:0] FFH register REPS, REC[6:0] in CnERC register 00H 00H FFH < TEC [7:0] 00H REPS, REC[6:0] 80H 00H Undefined 00H TEC[7:0] < 80H 00H REPS, REC[6:0] < 80H (b) Forced recovery operation that skips bus-off recovery sequence The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. Here is the procedure. First, the CAN module requests to enter the initialization mode. For the operation and points to be noted at this time, "Recovery from bus-off state through normal recovery sequence" on page 757. Next, the module requests to enter an operation mode. At the same time, the CCERC bit of the CnCTRL register must be set to 1. As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the module immediately enters the operation mode. In this case, the module is connected to the CAN bus after it has monitored 11 consecutive recessive-level bits. For details, refer to the processing in <~Reference>Figure 18-54 on page 859. Caution: (6) This function is not defined by the CAN protocol ISO 11898. When using this function, thoroughly evaluate its effect on the network system. Initializing CAN module error counter register (CnERC) in initialization mode If it is necessary to initialize the CAN module error counter register (CnERC) and CAN module information register (CnINFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the CnCTRL register in the initialization mode. When initialization has been completed, the CCERC bit is automatically cleared to 0. Cautions: 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1 in a CAN operation mode, the CnERC and CnINFO registers are not initialized. 2. The CCERC bit can be set at the same time as the request to enter a CAN operation mode. 758 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a CAN protocol layer basic system clock (fTQ) derived from the CAN module system clock (fCANMOD), and divided by 1 to 256 ("CnBRP - CANn module bit rate prescaler register" on page 791). (2) Data bit time (8 to 25 time quanta) One data bit time is defined as shown in Figure 18-18: on page 759. The CAN Controller sets time segment 1, time segment 2, and re-Synchronization Jump Width (SJW) of data bit time, as shown in Figure 18-18. Time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN protocol specification. Time segment 2 is equivalent to phase segment 2. Figure 18-18: Segment setting Data bit time(DBT) Sync segment Prop segment Phase segment 1 Time segment 1(TSEG1) Phase segment 2 Time segment 2 (TSEG2) Sample point (SPT) Table 18-15: Segment name Segment setting Settable range Notes on setting to conform to CAN specification Time segment 1 (TSEG1) 2TQ to 15TQ - Time segment 2 (TSEG2) 1TQ to 8TQ IPT of the CAN controller is 0TQ. To conform to the CAN protocol specification, therefore, a length less or equal to phase segment 1 must be set here. This means that the length of time segment 1 minus 1TQ is the settable upper limit of time segment 2. Re-synchronization Jump Width (SJW) 1TQ to 4TQ The length of time segment 1 minus 1TQ or 4 TQ, whichever is smaller. Notes: 1. IPT: Information Processing Time 2. TQ: Time Quanta Reference: The CAN protocol specification defines the segments constituting the data bit time as shown in Figure18-19. User's Manual U16580EE3V1UD00 759 Chapter 18 Figure 18-19: AFCAN Controller Configuration of data bit time defined by CAN specification Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 SJW Sample point (SPT) Table 18-16: Configuration of data bit time defined by CAN specification Segment name Settable range Notes on setting to conform to CAN specification Sync segment (Synchronization segment) 1 This segment starts at the edge where the level changes from recessive to dominant when hardware synchronization is established. Prop segment Programmable to 1 to 8 or more This segment absorbs the delay of the output buffer, CAN bus, and input buffer. The length of this segment is set so that ACK is returned before the start of phase segment 1. Time of prop segment (Delay of output buffer) + 2 x (Delay of CAN bus) + (Delay of input buffer) Phase segment 1 Programmable to 1 to 8 Phase segment 2 Phase segment 1 or IPT, whichever greater This segment compensates for an error of data bit time. The longer this segment, the wider the permissible range but the slower the communication speed. SJW Programmable from 1TQ to length of segment 1 or 4TQ, whichever is smaller This width sets the upper limit of expansion or contraction of the phase segment during resynchronization. Note: IPT: Information Processing Time 760 User's Manual U16580EE3V1UD00 Chapter 18 (3) AFCAN Controller Synchronizing data bit * The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. * The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hardware synchronization This synchronization is established when the receiving node detects the start of frame in the interframe space. * When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the prop segment. In this case, synchronization is established regardless of SJW. Figure 18-20: Adjusting synchronization of data bit Interframe space Start of frame CAN bus Bit timing Sync segment Prop segment Phase segment 1 User's Manual U16580EE3V1UD00 Phase segment 2 761 Chapter 18 AFCAN Controller (b) Re-synchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). * The phase error of the edge is given by the relative position of the detected edge and sync segment. <Sign of phase error> 0: If the edge is within the sync segment Positive: If the edge is before the sample point (phase error) Negative: If the edge is after the sample point (phase error) If phase error is positive: Phase segment 1 is lengthened by specified SJW. If phase error is negative: Phase segment 2 is shortened by specified SJW. * The sample point of the data of the receiving node moves relatively due to the "discrepancy" in the baud rate between the transmitting node and receiving node. Figure 18-21: Re-synchronization If phase error is positive CAN bus Bit timing Sync segment Prop segment Phase segment 2 Phase segment 1 Sample point If phase error is negative CAN bus Bit timing Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point 762 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.4 Connection with Target System The CAN module has to be connected to the CAN bus using an external transceiver. Figure 18-22: Connection to CAN bus CTxDn CAN module CRxDn CANL Transceiver User's Manual U16580EE3V1UD00 CANH 763 Chapter 18 AFCAN Controller 18.5 Internal Registers of CAN Controller 18.5.1 CAN module register and message buffer addresses In this chapter all register and message buffer addresses are defined as address offsets to different base addresses. Since all registers are accessed via the programmable peripheral area the bottom address is defined by the BPC register (refer to <Peripheral-IO-Reference> or to <Peripheral-IO-Reference-2>). The addresses given in the following tables are offsets to the programmable peripheral area base address PBA. The setting of BPC is fixed to 8FFBH. This setting defines the programmable peripheral area base address PBA = 03FE C000H Table 18-17 lists all base addresses used throughout this chapter. Table 18-17: CAN #n Base address name CnRBaseAddr CAN module base addresses Base address of Address 0 C0RBaseAddr CAN0 registers PBA + 000H 0 C0MBaseAddr CAN0 message buffers PBA + 100H ... ... ... ... n CnRBaseAddr CAN # n registers PBA + n * 600H n CnMBaseAddr CAN #n message buffers PBA + n * 600H + 100H In the following <CnRBaseAddr> respectively <CnMBaseAddr> are used for the base address names for CAN channel n. 764 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.5.2 CAN Controller configuration Table 18-18: Item CAN global registers List of CAN Controller registers Register Name CANn global control register (CnGMCTRL) CANn global clock selection register (CnGMCS) CANn global automatic block transmission control register (CnGMABT) CANn global automatic block transmission delay setting register (CnGMABTD) CAN module registers CANn module mask 1 register (CnMASK1L, CnMASK1H) CANn module mask 2 register (CnMASK2L, CnMASK2H) CANn module mask3 register (CnMASK3L, CnMASK3H) CANn module mask 4 registers (CnMASK4L, CnMASK4H) CANn module control register (CnCTRL) CANn module last error information register (CnLEC) CANn module information register (CnINFO) CANn module error counter register (CnERC) CANn module interrupt enable register (CnIE) CANn module interrupt status register (CnINTS) CANn module bit rate prescaler register (CnBRP) CANn module bit rate register (CnBTR) CANn module last in-pointer register (CnLIPT) CANn module receive history list register (CnRGPT) CANn module last out-pointer register (CnLOPT) CANn module transmit history list register (CnTGPT) CANn module time stamp register (CnTS) Message buffer registers CANn message data byte 01 register m (CnMDATA01m) CANn message data byte 0 register m (CnMDATA0m) CANn message data byte 1 register m (CnMDATA1m) CANn message data byte 23 register m (CnMDATA23m) CANn message data byte 2 register m (CnMDATA2m) CANn message data byte 3 register m (CnMDATA3m) CANn message data byte 45 register m (CnMDATA45m) CANn message data byte 4 register m (CnMDATA4m) CANn message data byte 5 register m (CnMDATA5m) CANn message data byte 67 register m (CnMDATA67m) CANn message data byte 6 register m (CnMDATA6m) CANn message data byte 7 register m (CnMDATA7m) CANn message data length register m (CnMDLCm) CANn message configuration register m (CnMCONFm) CANn message ID register m (CnMIDLm, CnMIDHm) CANn message control register m (CnMCTRLm) User's Manual U16580EE3V1UD00 765 Chapter 18 AFCAN Controller 18.5.3 CAN registers overview (1) CAN module #n registers The following table lists the address offsets to the CAN #n register base address: CnRBaseAddr Table 18-19: Address offset CAN0 global and module registers Register name Symbol R/W Access 1-bit 8-bit After reset 16-bit 000H CAN #n global control register CnGMCTRL 002H CAN #n global clock selection register CnGMCS 006H CAN #n global automatic block transmission register CnGMABT 008H CAN #n global automatic block transmission delay register CnGMABTD 040H CAN #n module mask 1 register CnMASK1L Undefined CnMASK1H Undefined CnMASK2L Undefined CnMASK2H Undefined CnMASK3L Undefined CnMASK3H Undefined CnMASK4L Undefined CnMASK4H Undefined 0000H 042H 044H CAN #n module mask 2 register 046H 048H CAN #n module mask 3 register 04AH 04CH CAN #n module mask 4 register 04EH R/W 0FH 050H CAN #n module control register CnCTRL 052H CAN #n module last error code register CnLEC 053H CAN #n module information register CnINFO 054H CAN #n module error counter register CnERC 056H CAN #n module interrupt enable register CnIE 058H CAN #n module interrupt status register CnINTS 05AH CAN #n module bit-rate prescaler register CnBRP 05CH CAN #n module bit-rate register CnBTR 05EH CAN #n module last in-pointer register CnLIPT R 060H CAN #n module receive history list register CnRGPT R/W 062H CAN #n module last out-pointer register CnLOPT R 064H CAN #n module transmit history list register CnTGPT R/W 066H CAN #n module time stamp register CnTS R 0000H 0000H 00H 00H 00H R/W 0000H 0000H 0000H FFH 370FH Undefined xx02H Undefined xx02H 0000H The addresses in the following table denote the address offsets to the CAN #n message buffer base address: CnMBaseAddr, with m being the message buffer number. Example CAN0, message buffer m = 14 = EH, byte 6 C0MDATA614 has the address EH x 20H + 6H + C0MBaseAddr Note: The message buffer register number m in the register symbols has 2 digits, for example, C0MDATA01m = C0MDATA0100 for m = 0. 766 User's Manual U16580EE3V1UD00 Chapter 18 Table 18-20: Address offset AFCAN Controller CAN0 message buffer registers Register name Symbol R/W Access 1-bit mx20 H + 0 H 8-bit After reset 16bit CAN #n message data byte 01 register m CnMDATA01m mx20 H + 0 H CAN #n message data byte 0 register m CnMDATA0m Undefined mx20 H + 1 H CAN #n message data byte 1 register m CnMDATA1m Undefined CAN #n message data byte 23 register m CnMDATA23m mx20 H + 2 H CAN #n message data byte 2 register m CnMDATA2m Undefined mx20 H + 3 H CAN #n message data byte 3 register m CnMDATA3m Undefined CAN #n message data byte 45 register m CnMDATA45m mx20 H + 4 H CAN #n message data byte 4 register m CnMDATA4m Undefined mx20 H + 5 H CAN #n message data byte 5 register m CnMDATA5m Undefined CAN #n message data byte 67 register m CnMDATA67m mx20 H + 6 H CAN #n message data byte 6 register m CnMDATA6m Undefined mx20 H + 7 H CAN #n message data byte 7 register m CnMDATA7m Undefined mx20 H + 8 H CAN #n message data length register m CnMDLCm 0000 xxxx B mx20 H + 9 H CAN #n message configuration register m CnMCONFm Undefined mx20 H + A H CAN #n message identifier register m CnMIDLm Undefined CnMIDHm Undefined CnMCTRLm 0x00 0000 0000 0000 B mx20 H + 2 H mx20 H + 4 H mx20 H + 6 H mx20 H + C H mx20 H + E H CAN #n message control register m R/W Undefined Undefined Undefined Undefined 18.5.4 Register bit configuration Table 18-21: CAN global register bit configuration Address offsetNote Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 00H CnGMCTRL (W) 0 0 0 0 0 0 0 Clear GOM 0 0 0 0 0 0 Set EFSD Set GOM 0 0 0 0 0 0 EFSD GOM MBON 0 0 0 0 0 0 0 01H 00H CnGMCTRL (R) 01H 02H CnGMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0 06H CnGMABT (W) 0 0 0 0 0 0 0 Clear ABTTRG 0 0 0 0 0 0 Set ABTCLR Set ABTTRG 0 0 0 0 0 0 ABTCLR ABTTRG 0 0 0 0 0 0 0 0 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 07H 06H CnGMABT (R) 07H 08H CnGMABTD Note: Base address: <CnRBaseAddr> User's Manual U16580EE3V1UD00 767 Chapter 18 Table 18-22: Address offsetNote Symbol 40H CnMASK1L Bit 7/15 AFCAN Controller CAN module register bit configuration (1/2) Bit 6/14 Bit 5/13 CnMASK1H 0 0 0 CnMASK2L CnMASK2H CMID23 to CMID16 0 0 0 CnMASK3L CMID7 to CMID0 CnMASK3H CMID23 to CMID16 0 0 0 CnMASK4L CMID15 to CMID8 CnMASK4H 4FH 50H CnCTRL (W) 51H 50H CMID28 to CMID24 CMID7 to CMID0 4DH 4EH CMID28 to CMID24 CMID15 to CMID8 4BH 4CH CMID28 to CMID24 CMID7 to CMID0 49H 4AH CnCTRL (R) 51H CMID23 to CMID16 0 0 0 CMID28 to CMID24 0 Clear AL Clear VALID Clear PSMODE1 Clear PSMODE0 Clear OPMODE2 Clear OPMODE1 Clear OPMODE0 Set CCERC Set AL 0 Set PSMODE1 Set PSMODE0 Set OPMODE2 Set OPMODE1 Set OPMODE0 CCERC AL VALID PS MODE1 PS MODE0 OP MODE2 OP MODE1 OP MODE0 0 0 0 0 0 0 RSTAT TSTAT 52H CnLEC (W) 0 0 0 0 0 0 0 0 52H CnLEC (R) 0 0 0 0 0 LEC2 LEC1 LEC0 53H CnINFO 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 54H CnERC TEC7 to TEC0 55H 56H REC7 to REC0 CnIE (W) 57H 56H CnIE (R) 57H 58H CnINTS (W) 59H 58H CnINTS (R) 59H 5AH CnBRP 5CH CnBTR 5DH 5EH 768 Bit 0/8 CMID15 to CMID8 47H 48H Bit 1/9 CMID23 to CMID16 45H 46H Bit 2/10 CMID15 to CMID8 43H 44H Bit 3/11 CMID7 to CMID0 41H 42H Bit 4/12 CnLIPT 0 0 Clear CIE5 Clear CIE4 Clear CIE3 Clear CIE2 Clear CIE1 Clear CIE0 0 0 Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0 0 0 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 0 0 0 0 0 0 0 0 0 0 Clear CINTS5 Clear CINTS4 Clear CINTS3 Clear CINTS2 Clear CINTS1 Clear CINTS0 0 0 0 0 0 0 0 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 0 0 0 0 0 0 0 0 TQPRS7 to TQPRS0 0 0 0 0 0 0 SJW1, SJW0 TSEG13 to TSEG10 0 LIPT7 to LIPT0 User's Manual U16580EE3V1UD00 TSEG22 to TSEG20 Chapter 18 Table 18-22: AFCAN Controller CAN module register bit configuration (2/2) Address offsetNote Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 60H CnRGPT (W) 0 0 0 0 0 0 0 Clear ROVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHPM ROVF 61H 60H CnRGPT (R) 61H RGPT7 to RGPT0 F62H CnLOPT 64H CnTGPT (W) 65H 64H CnTGPT (R) LOPT7 to LOPT0 0 0 0 0 0 0 0 Clear TOVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THPM TOVF 65H 66H TGPT7 to TGPT0 CnTS (W) 67H 66H CnTS (R) 67H 68H to FFH 0 0 0 0 0 Clear TSLOCK Clear TSSEL Clear TSEN 0 0 0 0 0 Set TSLOCK Set TSSEL Set TSEN 0 0 0 0 0 TSLOCK TSSEL TSEN 0 0 0 0 0 0 0 0 - Access prohibited (reserved for future use) Note: Base address: <CnRBaseAddr> User's Manual U16580EE3V1UD00 769 Chapter 18 Table 18-23: Address offsetNote Symbol 0H CnMDATA01m Bit 7/15 AFCAN Controller Message buffer register bit configuration Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 MDLC3 MDLC2 MDLC1 MDLC0 Message data (byte 0) 1H Message data (byte 1) 0H CnMDATA0m Message data (byte 0) 1H CnMDATA1m Message data (byte 1) 2H CnMDATA23m Message data (byte 2) 3H Message data (byte 3) 2H CnMDATA2m Message data (byte 2) 3H CnMDATA3m Message data (byte 3) 4H CnMDATA45m Message data (byte 4) 5H Message data (byte 5) 4H CnMDATA4m Message data (byte 4) 5H CnMDATA5m Message data (byte 5) 6H CnMDATA67m Message data (byte 6) 7H Message data (byte 7) 6H CnMDATA6m Message data (byte 6) 7H CnMDATA7m Message data (byte 7) 8H CnMDLCm 9H CnMCONFm OWS RTR MT2 MT1 MT0 0 0 MA0 AH CnMIDLm ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE 0 0 ID28 ID27 ID26 ID25 ID24 0 0 0 Clear MOW Clear IE Clear DN Clear TRQ Clear RDY 0 0 0 0 Set IE 0 Set TRQ Set RDY 0 0 0 MOW IE DN TRQ RDY 0 0 MUC 0 0 0 0 0 BH CH CnMIDHm DH EH CnMCTRLm (W) FH EH FH CnMCTRLm (R) 0 Note: Base address: <CnMBaseAddr> Remark: 770 For calculation of the complete message buffer register addresses refer to "CAN registers overview" on page 766. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. * CANn global control register (CnGMCTRL) * CANn global automatic block transmission control register (CnGMABT) * CANn module control register (CnCTRL) * CANn module interrupt enable register (CnIE) * CANn module interrupt status register (CnINTS) * CANn module receive history list register (CnRGPT) * CANn module transmit history list register (CnTGPT) * CANn module time stamp register (CnTS) * CANn message control register (CnMCTRLm) All the 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 18-23 below to set or clear the lower 8 bits in these registers. Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the bit status after set/clear operation is specified in <~Reference>Figure 18-26). Figure 18-23 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. Figure 18-23: Example of bit setting/clearing operations 1 1 0 1 0 0 0 1 Write value 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 set 0 0 0 0 1 0 1 1 clear 1 1 0 1 1 0 0 0 Register's value after write operation 0 0 0 0 0 0 0 Set 0 Set 0 No change 0 No change 0 Clear 0 No change 0 Clear 0 Clear 0 Bit status Register's current value 0 0 0 0 0 0 0 1 1 User's Manual U16580EE3V1UD00 771 Chapter 18 (1) AFCAN Controller Bit Status After Bit Setting/Clearing Operations 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0 772 Set 0 ... 7 Clear 0 ... 7 Status of bit n after bit set/clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.7 Control Registers (1) CnGMCTRL - CANn global control register The CnGMCTRL register is used to control the operation of the CAN module. After reset: 0000H R/W Address: <CnRBaseAddr> + 000H (a) Read CnGMCTRL 15 14 13 12 11 10 9 8 MBON 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 EFSD GOM MBON Bit enabling access to message buffer register, transmit/receive history registers 0 Write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 Write access and read access to the message buffer register and the transmit/receive history list registers is enabled. Cautions: 1. While the MBON bit is cleared (to 0), software access to the message buffers (CnMDATA0m, CnMDATA1m, CnMDATA01m, CnMDATA2m, CnMDATA3m, CnMDATA23m, CnMDATA4m, CnMDATA5m, CnMDATA45m, CnMDATA6m, CnMDATA7m, CnMDATA67m, CnMDLCm, CnMCONFm, CnMIDLm, CnMIDHm, and CnMCTRLm), or registers related to transmit history or receive history (CnLOPT, CnTGPT, CnLIPT, and CnRGPT) is disabled. 2. This bit is read-only. Even if 1 is written to the MBON bit while it is 0, the value of the MBON bit does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. Remark: The MBON bit is cleared (to 0) when the CAN module enters CAN sleep mode / CAN stop mode, or when the GOM bit is cleared (to 0). The MBON bit is set (to 1) when the CAN sleep mode / CAN stop mode is released, or when the GOM bit is set (to 1). EFSD Caution: 0 Forced shut down by GOM bit = 0 disabled. 1 Forced shut down by GOM bit = 0 enabled. To request forced shut down, the GOM bit must be cleared to 0 in a subsequent, immediately following access after the EFSD bit has been set to 1. If access to another register (including reading the CnGMCTRL register) is executed without clearing the GOM bit immediately after the EFSD bit has been set to 1, the EFSD bit is forcibly cleared to 0, and the forced shut down request is invalid. GOM Caution: Bit enabling forced shut down Global operation mode bit 0 CAN module is disabled from operating. 1 CAN module is enabled to operate. The GOM can be cleared only in the initialization mode or immediately after EFSD bit is set (to 1). User's Manual U16580EE3V1UD00 773 Chapter 18 AFCAN Controller (b) Write 15 14 13 12 11 10 9 8 0 0 0 0 0 0 Set EFSD Set GOM 7 6 5 4 3 2 1 0 0 Clear GOM CnGMCTRL 0 0 0 Set EFSD 774 0 EFSD bit setting 0 No change in EFSD bit. 1 EFSD bit set to 1. Set GOM Clear GOM 0 1 GOM bit cleared to 0. 1 0 GOM bit set to 1. Other than above Caution: 0 GOM bit setting No change in GOM bit. Set the GOM bit and EFSD bit always separately. User's Manual U16580EE3V1UD00 0 Chapter 18 (2) AFCAN Controller CnGMCS - CANn global clock selection register The CnGMCS register is used to select the CAN module system clock. After reset: 0FH R/W CnGMCS Remark: Address: <CnRBaseAddr> + 002H 7 6 5 4 3 2 1 0 0 0 0 0 CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN module system clock (fCANMOD) 0 0 0 0 fCAN/1 0 0 0 1 fCAN/2 0 0 1 0 fCAN/3 0 0 1 1 fCAN/4 0 1 0 0 fCAN/5 0 1 0 1 fCAN/6 0 1 1 0 fCAN/7 0 1 1 1 fCAN/8 1 0 0 0 fCAN/9 1 0 0 1 fCAN/10 1 0 1 0 fCAN/11 1 0 1 1 fCAN/12 1 1 0 0 fCAN/13 1 1 0 1 fCAN/14 1 1 1 0 fCAN/15 1 1 1 1 fCAN/16 (Default value) fCAN = Clock supplied to CAN User's Manual U16580EE3V1UD00 775 Chapter 18 (3) AFCAN Controller CnGMABT - CANn global automatic block transmission control register The CnGMABT register is used to control the automatic block transmission (ABT) operation. After reset: 0000H R/W Address: <CnRBaseAddr> + 006H (a) Read 15 CnGMABT 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ABTCLR ABTTRG ABTCLR Automatic block transmission engine clear status bit 0 Clearing the automatic transmission engine is completed. 1 The automatic transmission engine is being cleared. Notes: 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. The operation is not guaranteed if the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1. 2. When the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the ABTCLR bit is automatically cleared to 0 as soon as the requested clearing processing is complete. ABTTRG Caution: 776 Automatic block transmission status bit 0 Automatic block transmission is stopped. 1 Automatic block transmission is under execution. Do not set the ABTTRG bit (ABTTRG = 1) in the initialization mode. If the ABTTRG bit is set in the initialization mode, the operation is not guaranteed after the CAN module has entered the normal operation mode with ABT. Do not set the ABTTRG bit (1) while the CnCTRL.TSTAT bit is set (1). Confirm TSTAT = 0 directly in advance before setting ABTTRG bit. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller (b) Write CnGMABT 15 14 13 12 11 10 9 8 0 0 0 0 0 0 Set ABTCLR Set ABTTRG 7 6 5 4 3 2 1 0 0 Clear ABTTRG 0 Caution: 0 0 0 0 0 Before changing the normal operation mode with ABT to the initialization mode, be sure to set the CnGMABT register to the default value (0000H) and confirm the CnGMABT register is surely initialized to the default value (0000H). Set ABTCLR Automatic block transmission engine clear request bit 0 The automatic block transmission engine is in idle status or under operation. 1 Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1. Set ABTTRG Clear ABTTRG 0 1 Request to stop automatic block transmission. 1 0 Request to start automatic block transmission. Other than above Automatic block transmission start bit No change in ABTTRG bit. User's Manual U16580EE3V1UD00 777 Chapter 18 (4) AFCAN Controller CnGMABTD - CANn global automatic block transmission delay register The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. After reset: 00H R/W CnGMABTD Address: <CnRBaseAddr> + 008H 7 6 5 4 3 2 1 0 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 ABTD3 ABTD2 ABTD1 ABTD0 0 0 0 0 0 DBT (default value) 0 0 0 1 25 DBT 0 0 1 0 26 DBT 0 0 1 1 27 DBT 0 1 0 0 28 DBT 0 1 0 1 29 DBT 0 1 1 0 210 DBT 0 1 1 1 211 DBT 1 0 0 0 212 DBT Other than above Data frame interval during automatic block transmission (Unit: Data bit time (DBT)) Setting prohibited Cautions: 1. Do not change the contents of the CnGMABTD register while the ABTTRG bit is set to 1. 2. The timing at which the ABT message is actually transmitted onto the CAN bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an ABT message (message buffers 8 to 31) is made. 778 User's Manual U16580EE3V1UD00 Chapter 18 (5) AFCAN Controller CnMASKaL, CnMASKaH - CANn module mask control register (a = 1 to 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the identifier (ID) comparison of a message and invalidating the ID of the masked part. (a) CANn module mask 1 register (CnMASK1L, CnMASK1H) After reset: Undefined CnMASK1L CnMASK1H R/W Address: CnMASK1L <CnRBaseAddr> + 040H CnMASK1H <CnRBaseAddr> + 042H 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 (b) CANn module mask 2 register (CnMASK2L, CnMASK2H) After reset: Undefined CnMASK2L CnMASK2H R/W Address: CnMASK2L <CnRBaseAddr> + 044H CnMASK2H <CnRBaseAddr> + 046H 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 (c) CANn module mask 3 register (CnMASK3L, CnMASK3H) After reset: Undefined CnMASK3L CnMASK3H R/W Address: CnMASK3L <CnRBaseAddr> + 048H CnMASK3H <CnRBaseAddr> + 04AH 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 User's Manual U16580EE3V1UD00 779 Chapter 18 AFCAN Controller (d) CANn module mask 4 register (CnMASK4L, CnMASK4H) After reset: Undefined CnMASK4L CnMASK4H R/W Address: CnMASK4L <CnRBaseAddr> + 04CH CnMASK4H <CnRBaseAddr> + 04EH 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID28 to CMID0 Mask pattern setting of ID bit 0 The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared with the ID bits of the received message frame. 1 The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared with the ID bits of the received message frame (they are masked). Note: Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message with a standard ID, the CMID17 to CMID0 bits are ignored. Therefore, only the CMID28 to CMID18 bits of the received ID are masked. The same mask can be used for both the standard and extended IDs. 780 User's Manual U16580EE3V1UD00 Chapter 18 (6) AFCAN Controller CnCTRL - CANn module control register The CnCTRL register is used to control the operation mode of the CAN module. After reset: 0000H R/W Address: CnCTRL <CnRBaseAddr> + 050H (a) Read 15 CnCTRL 14 13 12 11 10 9 8 0 0 0 0 0 0 RSTAT TSTAT 7 6 5 4 3 2 1 0 CCERC AL VALID PSMODE 1 RSTAT PSMODE OPMODE OPMODE OPMODE 0 2 1 0 Reception status bit 0 Reception is stopped. 1 Reception is in progress. Notes: 1. The RSTAT bit is set to 1 under the following conditions (timing) * The SOF bit of a receive frame is detected * On occurrence of arbitration loss during a transmit frame 2. The RSTAT bit is cleared to 0 under the following conditions (timing) * When a recessive level is detected at the second bit of the interframe space * On transition to the initialization mode at the first bit of the interframe space TSTAT Transmission status bit 0 Transmission is stopped. 1 Transmission is in progress. Notes: 1. The TSTAT bit is set to 1 under the following conditions (timing) * The SOF bit of a transmit frame is detected 2. The TSTAT bit is cleared to 0 under the following conditions (timing) * During transition to bus-off state * On occurrence of arbitration loss in transmit frame * On detection of recessive level at the second bit of the interframe space * On transition to the initialization mode at the first bit of the interframe space User's Manual U16580EE3V1UD00 781 Chapter 18 CCERC AFCAN Controller Error counter clear bit 0 The CnERC and CnINFO registers are not cleared in the initialization mode. 1 The CnERC and CnINFO registers are cleared in the initialization mode. Notes: 1. The CCERC bit is used to clear the CnERC and CnINFO registers for re-initialization or forced recovery from the bus-off state. This bit can be set to 1 only in the initialization mode. 2. When the CnERC and CnINFO registers have been cleared, the CCERC bit is also cleared to 0 automatically. 3. The CCERC bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. The CCERC bit is read-only in the CAN sleep mode or CAN stop mode. 5. The receive data may be corrupted in case of setting the CCERC bit to (1) immediately after entering the INIT mode from self-test mode. AL Bit to set operation in case of arbitration loss 0 Re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 Re-transmission is executed in case of an arbitration loss in the single-shot mode. Note: The AL bit is valid only in the single-shot mode. VALID Valid receive message frame detection bit 0 A valid message frame has not been received since the VALID bit was last cleared to 0. 1 A valid message frame has been received since the VALID bit was last cleared to 0. Notes: 1. Detection of a valid receive message frame is not dependent upon storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. Clear the VALID bit (0) before changing the initialization mode to an operation mode. 3. If only two CAN nodes are connected to the CAN bus with one transmitting a message frame in the normal mode and the other in the receive-only mode, the VALID bit is not set to 1 before the transmitting node enters the error passive state, because in receive-only mode no acknowledge is generated. 4. To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the VALID bit is cleared. If it is not cleared, perform clearing processing again. PSMODE1 PSMODE0 Power save mode 0 0 No power save mode is selected. 0 1 CAN sleep mode 1 0 Setting prohibited 1 1 CAN stop mode Cautions: 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored. 2. The MBON flag of CnGMCTRL must be checked after releasing a power save mode, prior to access the message buffers again. 3. CAN sleep mode requests are kept pending, until cancelled by software or entered on appropriate bus condition (bus idle). Software can check the actual status by reading PSMODE. 782 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller OPMODE2 OPMODE1 OPMODE0 Operation mode 0 0 0 No operation mode is selected (CAN module is in the initialization mode). 0 0 1 Normal operation mode 0 1 0 Normal operation mode with automatic block transmission function (normal operation mode with ABT) 0 1 1 Receive-only mode 1 0 0 Single-shot mode 1 0 1 Self-test mode Other than above Caution: Setting prohibited Transit to initialization mode or power saving modes may take some time. Be sure to verify the success of mode change by reading the values, before proceeding. Note: The OPMODE0 to OPMODE2 bits are read-only in the CAN sleep mode or CAN stop mode. (b) Write CnCTRL 15 14 13 12 11 10 9 8 Set CCERC Set AL 0 Set PSMODE 1 Set PSMODE 0 Set OPMODE 2 Set OPMODE 1 Set OPMODE 0 7 6 5 4 3 2 1 0 0 Clear AL Clear VALID Clear PSMODE 1 Clear PSMODE 0 Clear OPMODE 2 Clear OPMODE 1 Clear OPMODE 0 Set CCERC 1 Setting of CCERC bit CCERC bit is set to 1. Other than above CCERC bit is not changed. Set AL Clear AL 0 1 AL bit is cleared to 0. 1 0 AL bit is set to 1. Other than above Clear VALID Setting of AL bit AL bit is not changed. Setting of VALID bit 0 VALID bit is not changed. 1 VALID bit is cleared to 0. Set PSMODE0 Clear PSMODE0 0 1 PSMODE0 bit is cleared to 0. 1 0 PSMODE0 bit is set to 1. Other than above Setting of PSMODE0 bit PSMODE0 bit is not changed. User's Manual U16580EE3V1UD00 783 Chapter 18 Set PSMODE1 Clear PSMODE1 0 1 PSMODE1 bit is cleared to 0. 1 0 PSMODE1 bit is set to 1. Other than above Setting of PSMODE1 bit PSMODE1 bit is not changed. Set OPMODE0 Clear OPMODE0 0 1 OPMODE0 bit is cleared to 0. 1 0 OPMODE0 bit is set to 1. Other than above Setting of OPMODE0 bit OPMODE0 bit is not changed. Set OPMODE1 Clear OPMODE1 0 1 OPMODE1 bit is cleared to 0. 1 0 OPMODE1 bit is set to 1. Other than above Setting of OPMODE1 bit OPMODE1 bit is not changed. Set OPMODE2 Clear OPMODE2 0 1 OPMODE2 bit is cleared to 0. 1 0 OPMODE2 bit is set to 1. Other than above 784 AFCAN Controller Setting of OPMODE2 bit OPMODE2 bit is not changed. User's Manual U16580EE3V1UD00 Chapter 18 (7) AFCAN Controller CnLEC - CANn module last error information register The CnLEC register provides the error information of the CAN protocol. After reset: 00H R/W CnLEC Address: CnLEC <CnRBaseAddr> + 052H 7 6 5 4 3 2 1 0 0 0 0 0 0 LEC2 LEC1 LEC0 Notes: 1. The contents of the CnLEC register are not cleared when the CAN module changes from an operation mode to the initialization mode. 2. If an attempt is made to write a value other than 00H to the CnLEC register by software, the access is ignored. LEC2 LEC1 LEC0 Last CAN protocol error information 0 0 0 No error 0 0 1 Stuff error 0 1 0 Form error 0 1 1 ACK error 1 0 0 Bit error. (The CAN module tried to transmit a recessive-level bit as part of a transmit message (except the arbitration field), but the value on the CAN bus is a dominant-level bit.) 1 0 1 Bit error. (The CAN module tried to transmit a dominant-level bit as part of a transmit message, ACK bit, error frame, or overload frame, but the value on the CAN bus is a recessive-level bit.) 1 1 0 CRC error 1 1 1 Undefined User's Manual U16580EE3V1UD00 785 Chapter 18 (8) AFCAN Controller CnINFO - CANn module information register The CnINFO register indicates the status of the CAN module. After reset: 00H R/W CnINFO Address: CnINFO <CnRBaseAddr> + 053H 7 6 5 4 3 2 1 0 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off state bit 0 Not bus-off state (transmit error counter 255). (The value of the transmit counter is less than 256.) 1 Bus-off state (transmit error counter > 255). (The value of the transmit counter is 256 or more.) TECS1 TECS0 0 0 The value of the transmission error counter is less than that of the warning level (< 96). 0 1 The value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 Undefined 1 1 The value of the transmission error counter is in the range of the error passive or bus-off status ( 128). RECS1 RECS0 0 0 The value of the reception error counter is less than that of the warning level (< 96). 0 1 The value of the reception error counter is in the range of the warning level (96 to 127). 1 0 Undefined 1 1 The value of the reception error counter is in the error passive range ( 128). 786 Transmission error counter status bit Reception error counter status bit User's Manual U16580EE3V1UD00 Chapter 18 (9) AFCAN Controller CnERC - CANn module error counter register The CnERC register indicates the count value of the transmission/reception error counter. After reset: 0000H CnERC R Address: CnERC <CnRBaseAddr> + 054H 15 14 13 12 11 10 9 8 REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REPS Reception error passive status bit 0 The reception error counter is not the error passive range (< 128) 1 The reception error counter is in the error passive range ( 128) REC6 to REC0 Reception error counter bit 0 to 127 Number of reception errors. These bits reflect the status of the reception error counter. The number of errors is defined by the CAN protocol. Note: REC6 to REC0 of the reception error counter are invalid in the reception error passive state (RECS[1:0] = 11B). TEC7 to TEC0 Transmission error counter bit 0 to 255 Number of transmission errors. These bits reflect the status of the transmission error counter. The number of errors is defined by the CAN protocol. Note: The TEC7 to TEC0 bits of the transmission error counter are invalid in the bus-off state (BOFF = 1). User's Manual U16580EE3V1UD00 787 Chapter 18 AFCAN Controller (10) CnIE - CANn module interrupt enable register The CnIE register is used to enable or disable the interrupts of the CAN module. After reset: 0000H R/W Address: CnIE <CnRBaseAddr> + 056H (a) Read CnIE CIEx 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 CAN module interrupt enable bit 0 Output of the interrupt corresponding to interrupt status register CINTSx is disabled. 1 Output of the interrupt corresponding to interrupt status register CINTSx is enabled. (b) Write 15 CnIE 14 13 12 11 10 9 8 0 0 Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0 7 6 5 4 3 2 1 0 0 0 Clear CIE5 Clear CIE4 Clear CIE3 Clear CIE2 Clear CIE1 Clear CIE0 Set CIE5 Clear CIE5 0 1 CIE5 bit is cleared to 0. 1 0 CIE5 bit is set to 1. Other than above CIE5 bit is not changed. Set CIE4 Clear CIE4 0 1 CIE4 bit is cleared to 0. 1 0 CIE4 bit is set to 1. Other than above Setting of CIE4 bit CIE4 bit is not changed. Set CIE3 Clear CIE3 0 1 CIE3 bit is cleared to 0. 1 0 CIE3 bit is set to 1. Other than above Setting of CIE3 bit CIE3 bit is not changed. Set CIE2 Clear CIE2 0 1 CIE2 bit is cleared to 0. 1 0 CIE2 bit is set to 1. Other than above 788 Setting of CIE5 bit Setting of CIE2 bit CIE2 bit is not changed. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller Set CIE1 Clear CIE1 0 1 CIE1 bit is cleared to 0. 1 0 CIE1 bit is set to 1. Other than above Setting of CIE1 bit CIE1 bit is not changed. Set CIE0 Clear CIE0 0 1 CIE0 bit is cleared to 0. 1 0 CIE0 bit is set to 1. Other than above Setting of CIE0 bit CIE0 bit is not changed. User's Manual U16580EE3V1UD00 789 Chapter 18 AFCAN Controller (11) CnINTS - CANn module interrupt status register The CnINTS register indicates the interrupt status of the CAN module. After reset: 0000H R/W Address: CnINTS <CnRBaseAddr> + 058H (a) Read 15 CnINTS 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 CINTS5 to CINTS0 CAN interrupt status bit 0 No related interrupt source event is pending. 1 A related interrupt source event is pending. Interrupt status bit Related interrupt source event CINTS5 Wakeup interrupt from CAN sleep modeNote CINTS4 Arbitration loss interrupt CINTS3 CAN protocol error interrupt CINTS2 CAN error status interrupt CINTS1 Interrupt on completion of reception of valid message frame to message buffer m CINTS0 Interrupt on normal completion of transmission of message frame from message buffer m Note: The CINTS5 bit is set only when the CAN module is woken up from the CAN sleep mode by a CAN bus operation. The CINTS5 bit is not set when the CAN sleep mode has been released by software. (b) Write CnINTS 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 Clear CINTS5 Clear CINTS4 Clear CINTS3 Clear CINTS2 Clear CINTS1 Clear CINTS0 Clear CINTS5 to CINTS0 Caution: 790 Setting of CINTS5 to CINTS0 bits 0 CINTS5 to CINTS0 bits are not changed. 1 CINTS5 to CINTS0 bits are cleared to 0. Please clear the status bit of this register with software when the confirmation of each status is necessary in the interrupt processing, because these bits are not cleared automatically. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller (12) CnBRP - CANn module bit rate prescaler register The CnBRP register is used to select the CAN protocol layer basic system clock (fTQ). The communication baud rate is set to the CnBTR register. After reset: FFH CnBRP R/W Address: CnBRP <CnRBaseAddr> + 05AH 7 6 5 4 3 2 1 0 TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 CAN protocol layer base system clock (fTQ) TQPRS7 to TQPRS0 0 fCANMOD/1 1 fCANMOD/2 n fCANMOD/(n+1) : : 255 fCANMOD/256 (default value) Figure 18-24: CAN module clock CANn module clock selection register (CnGMCS) 0 fCAN 0 0 0 CCP3 CCP2 CCP1 CCP0 fCANMOD Prescaler Baud rate generator fTQ CANn bit-rate register (CnBTR) TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 CANn module bit-rate prescaler register (CnBRP) Note: fCAN: clock supplied to CAN fCANMOD: CAN module system clock CAN protocol layer basic system clock fTQ: Caution: The CnBRP register can be write-accessed only in the initialization mode. User's Manual U16580EE3V1UD00 791 Chapter 18 AFCAN Controller (13) CnBTR - CANn module bit rate register The CnBTR register is used to control the data bit time of the communication baud rate. After reset: 370FH CnBTR R/W Address: CnBTR <CnRBaseAddr> + 05CH 15 14 13 12 11 10 9 8 0 0 SJW1 SJW0 0 TSEG22 TSEG21 TSEG20 7 6 5 4 3 2 1 0 0 0 0 0 TSEG13 TSEG12 TSEG11 TSEG10 Figure 18-25: Data bit time Data bit time (DBT) Sync segment Prop segment Phase segment 1 Time segment 1 (TSEG1) SJW1 SJW0 0 0 1TQ 0 1 2TQ 1 0 3TQ 1 1 4TQ (default value) Time segment 2 (TSEG2) Sample point (SPT) Length of synchronization jump width TSEG22 TSEG21 TSEG20 792 Phase segment 2 Length of time segment 2 0 0 0 1TQ 0 0 1 2TQ 0 1 0 3TQ 0 1 1 4TQ 1 0 0 5TQ 1 0 1 6TQ 1 1 0 7TQ 1 1 1 8TQ (default value) User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 0 0 0 0 Setting prohibited 0 0 0 1 2TQNote 0 0 1 0 3TQNote 0 0 1 1 4TQ 0 1 0 0 5TQ 0 1 0 1 6TQ 0 1 1 0 7TQ 0 1 1 1 8TQ 1 0 0 0 9TQ 1 0 0 1 10TQ 1 0 1 0 11TQ 1 0 1 1 12TQ 1 1 0 0 13TQ 1 1 0 1 14TQ 1 1 1 0 15TQ 1 1 1 1 16TQ (default value) Note: This setting must not be made when the CnBRP register = 00H. Remark: TQ = 1/fTQ (fTQ: CAN protocol layer basic system clock) (14) CnLIPT - CANn module last in-pointer register The CnLIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. After reset: Undefined CnLIPT R Address: CnLIPT <CnRBaseAddr> + 05EH 7 6 5 4 3 2 1 0 LIPT7 LIPT6 LIPT5 LIPT4 LIPT3 LIPT2 LIPT1 LIPT0 LIPT7 to LIPT0 Last in-pointer register (CnLIPT) 0 to 31 When the CnLIPT register is read, the contents of the element indexed by the last in-pointer (LIPT) of the receive history list are read. These contents indicate the number of the message buffer in which a data frame or a remote frame was last stored. Note: The read value of the CnLIPT register is undefined if a data frame or a remote frame has never been stored in the message buffer. If the RHPM bit of the CnRGPT register is set to 1 after the CAN module has changed from the initialization mode to an operation mode, therefore, the read value of the CnLIPT register is undefined. User's Manual U16580EE3V1UD00 793 Chapter 18 AFCAN Controller (15) CnRGPT - CANn module receive history list register The CnRGPT register is used to read the receive history list. After reset: xx02H R/W Address: CnRGPT <CnRBaseAddr> + 060H (a) Read CnRGPT 15 14 13 12 11 10 9 8 RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RHPM ROVF RGPT7 to RGPT0 Receive history list read pointer 0 to 31 When the CnRGPT register is read, the contents of the element indexed by the receive history list get pointer (RGPT) of the receive history list are read. These contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. RHPMNote 1 Receive history list pointer match 0 The receive history list has at least one message buffer number that has not been read. 1 The receive history list has no message buffer numbers that have not been read. ROVFNote 2 Receive history list overflow bit 0 All the message buffer numbers that have not been read are preserved. All the numbers of the message buffers in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 At least 23 entries have been stored since the host processor has serviced the RHL last time (i.e. read CnRGPT). The first 22 entries are sequentially stored while the last entry can have been overwritten whenever newly received message is stored because all buffer numbers are stored at position LIPT-1 when ROVF bit is set. Thus the sequence of receptions can not be recovered completely now. Notes: 1. The read value of the RGPT0 to RGPT7 bits is invalid when the RHPM bit = 1. 2. If ROVF is set, RHPM is no longer cleared on message storage, but RHPM is still set, if all entries of CnRGPT are read by software. (b) Write CnRGPT 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear ROVF Clear ROVF 794 Setting of ROVF bit 0 ROVF bit is not changed. 1 ROVF bit is cleared to 0. User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller (16) CnLOPT - CANn module last out-pointer register The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. After reset: Undefined CnLOPT LOPT7 to LOPT0 0 to 31 R Address: CnLOPT <CnRBaseAddr> + 062H 7 6 5 4 3 2 1 0 LOPT7 LOPT6 LOPT5 LOPT4 LOPT3 LOPT2 LOPT1 LOPT0 Last out-pointer of transmit history list (LOPT) When the CnLOPT register is read, the contents of the element indexed by the last out-pointer (LOPT) of the receive history list are read. These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. Note: The value read from the CnLOPT register is undefined if a data frame or remote frame has never been transmitted from a message buffer. If the CnTGPT.THPM bit is set to 1 after the CAN module has changed from the initialization mode to an operation mode, therefore, the read value of the CnLOPT register is undefined. User's Manual U16580EE3V1UD00 795 Chapter 18 AFCAN Controller (17) CnTGPT - CANn module transmit history list register The CnTGPT register is used to read the transmit history list. After reset: xx02H R/W Address: CnTGPT <CnRBaseAddr> + 064H (a) Read CnTGPT TGPT7 to TGPT0 0 to 31 THPMNote 1 15 14 13 12 11 10 9 8 TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 THPM TOVF Transmit history list read pointer When the CnTGPT register is read, the contents of the element indexed by the read pointer (TGPT) of the transmit history list are read. These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. Transmit history pointer match 0 The transmit history list has at least one message buffer number that has not been read. 1 The transmit history list has no message buffer numbers that have not been read. TOVFNote 2 Transmit history list overflow bit 0 All the message buffer numbers that have not been read are preserved. All the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transmit history list has a vacant element). 1 At least 7 entries have been stored since the host processor has serviced the THL last time (i.e. read CnTGPT). The first 6 entries are sequentially stored while the last entry can have been overwritten whenever a message is newly transmitted because all buffer numbers are stored at position LOPT-1 when TOVF bit is set. Thus the sequence of transmissions can not be recovered completely now. Notes: 1. The read value of the TGPT0 to TGPT7 bits is invalid when the THPM bit = 1. 2. If TOVF is set, THPM is no longer cleared on message transmission, but THPM is still set, if all entries of CnTGPT are read by software. Remark: Transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal operation mode with ABT. (b) Write CnTGPT 796 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear TOVF User's Manual U16580EE3V1UD00 Chapter 18 Clear TOVF AFCAN Controller Setting of TOVF bit 0 TOVF bit is not changed. 1 TOVF bit is cleared to 0. (18) CnTS - CANn module time stamp register The CnTS register is used to control the time stamp function. After reset: 0000H R/W Address: CnTS <CnRBaseAddr> + 066H (a) Read CnTS 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 TSLOCK TSSEL TSEN Note: The lock function of the time stamp function must not be used when the CAN module is in the normal operation mode with ABT. TSLOCK Time stamp lock function enable bit 0 Time stamp lock function stopped. The TSOUT signal is toggled each time the selected time stamp capture event occurs. 1 Time stamp lock function enabled. The TSOUT signal is toggled each time the selected time stamp capture event occurs. However, the TSOUT output signal is locked when a data frame has been correctly received to message buffer 0Note. Note: The TSEN bit is automatically cleared to 0. TSSEL Time stamp capture event selection bit 0 The time capture event is SOF. 1 The time stamp capture event is the last bit of EOF. TSEN TSOUT operation setting bit 0 TSOUT toggle operation is disabled. 1 TSOUT toggle operation is enabled. User's Manual U16580EE3V1UD00 797 Chapter 18 AFCAN Controller (b) Write 15 14 13 12 11 10 9 8 0 0 0 0 0 Set TSLOCK Set TSSEL Set TSEN 7 6 5 4 3 2 1 0 0 0 0 0 0 Clear TSLOCK Clear TSSEL Clear TSEN Set TSLOCK Clear TSLOCK 0 1 TSLOCK bit is cleared to 0. 1 0 TSLOCK bit is set to 1. CnTS Other than above Setting of TSLOCK bit TSLOCK bit is not changed. Set TSSEL Clear TSSEL Setting of TSSEL bit 0 1 TSSEL bit is cleared to 0. 1 0 TSSEL bit is set to 1. Other than above TSSEL bit is not changed. Set TSEN Clear TSEN Setting of TSEN bit 0 1 TSEN bit is cleared to 0. 1 0 TSEN bit is set to 1. Other than above TSEN bit is not changed. (19) CnMDATAxm, CnMDATAzm - CANn message data byte register (x = 0 to 7, z = 01, 23, 45, 67) The CnMDATAxm, CnMDATAzm registers are used to store the data of a transmit/receive message. After reset: Undefined R/W Address: refer to "CAN registers overview" on page 766 The CnMDATAzm registers can access the CnMDATAxm registers in 16-bit units. 798 User's Manual U16580EE3V1UD00 Chapter 18 CnMDATA01m CnMDATA0m CnMDATA1m CnMDATA23m CnMDATA2m CnMDATA3m AFCAN Controller 15 14 13 12 11 10 9 8 MDATA01 15 MDATA01 14 MDATA01 13 MDATA01 12 MDATA01 11 MDATA01 10 MDATA01 9 MDATA01 8 7 6 5 4 3 2 1 0 MDATA01 7 MDATA01 6 MDATA01 5 MDATA01 4 MDATA01 3 MDATA01 2 MDATA01 1 MDATA01 0 7 6 5 4 3 2 1 0 MDATA0 7 MDATA0 6 MDATA0 5 MDATA0 4 MDATA0 3 MDATA0 2 MDATA0 1 MDATA0 0 7 6 5 4 3 2 1 0 MDATA1 7 MDATA1 6 MDATA1 5 MDATA1 4 MDATA1 3 MDATA1 2 MDATA1 1 MDATA1 0 15 14 13 12 11 10 9 8 MDATA23 15 MDATA23 14 MDATA23 13 MDATA23 12 MDATA23 11 MDATA23 10 MDATA23 9 MDATA23 8 7 6 5 4 3 2 1 0 MDATA23 7 MDATA23 6 MDATA23 5 MDATA23 4 MDATA23 3 MDATA23 2 MDATA23 1 MDATA23 0 7 6 5 4 3 2 1 0 MDATA2 7 MDATA2 6 MDATA2 5 MDATA2 4 MDATA2 3 MDATA2 2 MDATA2 1 MDATA2 0 7 6 5 4 3 2 1 0 MDATA3 7 MDATA3 6 MDATA3 5 MDATA3 4 MDATA3 3 MDATA3 2 MDATA3 1 MDATA3 0 User's Manual U16580EE3V1UD00 799 Chapter 18 CnMDATA45m CnMDATA4m CnMDATA5m CnMDATA67m CnMDATA6m CnMDATA7m 800 AFCAN Controller 15 14 13 12 11 10 9 8 MDATA45 15 MDATA45 14 MDATA45 13 MDATA45 12 MDATA45 11 MDATA45 10 MDATA45 9 MDATA45 8 7 6 5 4 3 2 1 0 MDATA45 7 MDATA45 6 MDATA45 5 MDATA45 4 MDATA45 3 MDATA45 2 MDATA45 1 MDATA45 0 7 6 5 4 3 2 1 0 MDATA4 7 MDATA4 6 MDATA4 5 MDATA4 4 MDATA4 3 MDATA4 2 MDATA4 1 MDATA4 0 7 6 5 4 3 2 1 0 MDATA5 7 MDATA5 6 MDATA5 5 MDATA5 4 MDATA5 3 MDATA5 2 MDATA5 1 MDATA5 0 15 14 13 12 11 10 9 8 MDATA67 15 MDATA67 14 MDATA67 13 MDATA67 12 MDATA67 11 MDATA67 10 MDATA67 9 MDATA67 8 7 6 5 4 3 2 1 0 MDATA67 7 MDATA67 6 MDATA67 5 MDATA67 4 MDATA67 3 MDATA67 2 MDATA67 1 MDATA67 0 7 6 5 4 3 2 1 0 MDATA6 7 MDATA6 6 MDATA6 5 MDATA6 4 MDATA6 3 MDATA6 2 MDATA6 1 MDATA6 0 7 6 5 4 3 2 1 0 MDATA7 7 MDATA7 6 MDATA7 5 MDATA7 4 MDATA7 3 MDATA7 2 MDATA7 1 MDATA7 0 User's Manual U16580EE3V1UD00 Chapter 18 (20) AFCAN Controller CnMDLCm - CANn message data length register m The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB CnMDLCm R/W Address: refer to "CAN registers overview" on page 766 7 6 5 4 3 2 1 0 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0 MDLC3 MDLC2 MDLC1 MDLC0 Data length of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 Setting prohibited (If these bits are set during transmission, 8-byte data is transmitted regardless of the set DLC value when a data frame is transmitted. However, the DLC actually transmitted to the CAN bus is the DLC value set to this register.)Note 1 1 0 1 1 1 1 0 1 1 1 1 Note: The data and DLC value actually transmitted to CAN bus are as follows. Type of transmit frame Length of transmit data DLC transmitted Data frame Number of bytes specified by DLC (However, 8 bytes if DLC 8) MDLC3 to MDLC0 bits Remote frame 0 bytes Caution 1. Be sure to set bits 7 to 4 to 0000B. 2. Receive data is stored in as many CnMDATAxm register as the number of bytes (however, the upper limit is 8) corresponding to DLC of the received frame. The CnMDATAxm register in which no data is stored is undefined. User's Manual U16580EE3V1UD00 801 Chapter 18 AFCAN Controller (21) CnMCONFm - CANn message configuration register m The CnMCONFm register is used to specify the type of the message buffer and to set a mask. After reset: Undefined CnMCONFm R/W Address: refer to "CAN registers overview" on page 766 7 6 5 4 3 2 1 0 OWS RTR MT2 MT1 MT0 0 0 MA0 OWS Overwrite control bit 0 The message buffer that has already received a data frameNote is not overwritten by a newly received data frame. The newly received data frame is discarded. 1 The message buffer that has already received a data frameNote is overwritten by a newly received data frame. Notes: 1. The "message buffer that has already received a data frame" is a receive message buffer whose the CnMCTRLm.DN bit has been set to 1. Remark: A remote frame is received and stored, regardless of the setting of OWS and DN. A remote frame that satisfies the other conditions (ID matches, RTR = 0, TRQ = 0) is always received and stored in the corresponding message buffer (interrupt generated, DN flag set, MDLC[3:0] updated, and recorded to the receive history list). RTR Remote frame request bitNote 0 Transmit a data frame. 1 Transmit a remote frame. Note: The RTR bit specifies the type of message frame that is transmitted from a message buffer defined as a transmit message buffer. Even if a valid remote frame has been received, the RTR bit of the transmit message buffer that has received the frame remains cleared to 0. Even if a remote frame whose ID matches has been received from the CAN bus with the RTR bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, DN flag set, the MDLC0 to MDLC3 bits updated, and recorded to the receive history list). MT2 MT1 MT0 0 0 0 Transmit message buffer 0 0 1 Receive message buffer (no mask setting) 0 1 0 Receive message buffer (mask 1 set) 0 1 1 Receive message buffer (mask 2 set) 1 0 0 Receive message buffer (mask 3 set) 1 0 1 Receive message buffer (mask 4 set) Other than above 802 Message buffer type setting bit Setting prohibited User's Manual U16580EE3V1UD00 Chapter 18 MA0 AFCAN Controller Message buffer assignment bit 0 Message buffer not used. 1 Message buffer used. Caution Be sure to write 0 to bits 2 and 1. (22) CnMIDLm, CnMIDHm - CANn message ID register m The CnMIDLm and CnMIDHm registers are used to set an identifier (ID). After reset: Undefined CnMIDLm CnMIDHm R/W Address: refer to "CAN registers overview" on page 766 15 14 13 12 11 10 9 8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15 14 13 12 11 10 9 8 IDE 0 0 ID28 ID27 ID26 ID25 ID24 7 6 5 4 3 2 1 0 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE Format mode specification bit 0 Standard format mode (ID28 to ID18: 11 bits)Note 1 Extended format mode (ID28 to ID0: 29 bits) Note: The ID17 to ID0 bits are not used. ID28 to ID0 Message ID ID28 to ID18 Standard ID value of 11 bits (when IDE = 0) ID28 to ID0 Extended ID value of 29 bits (when IDE = 1) Caution 1. Be sure to write 0 to bits 14 and 13 of the CnMIDHm register. 2. Be sure to align the ID value according to the given bit positions into this registers. Note that for standard ID, the ID value must be shifted to fit into ID28 to ID11 bit positions. User's Manual U16580EE3V1UD00 803 Chapter 18 AFCAN Controller (23) CnMCTRLm - CANn message control register m The CnMCTRLm register is used to control the operation of the message buffer. After reset: 00x000000 R/W 00000000B Address: refer to "CAN registers overview" on page 766 (a) Read CnMCTRLm 15 14 13 12 11 10 9 8 0 0 MUC 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 MOW IE DN TRQ RDY MUCNote Bit indicating that message buffer data is being updated 0 The CAN module is not updating the message buffer (reception and storage). 1 The CAN module is updating the message buffer (reception and storage). Note: The MUC bit is undefined until the first reception and storage is performed. MOWNote Message buffer overwrite status bit 0 The message buffer is not overwritten by a newly received data frame. 1 The message buffer is overwritten by a newly received data frame. Note: The MOW bit is not set to 1 even if a remote frame is received and stored in the transmit message buffer with the DN bit = 1. IE Message buffer interrupt request enable bit 0 Receive message buffer: Valid message reception completion interrupt disabled. Transmit message buffer: Normal message transmission completion interrupt disabled. 1 Receive message buffer: Valid message reception completion interrupt enabled. Transmit message buffer: Normal message transmission completion interrupt enabled. DN 804 Message buffer data update bit 0 A data frame or remote frame is not stored in the message buffer. 1 A data frame or remote frame is stored in the message buffer. User's Manual U16580EE3V1UD00 Chapter 18 TRQ RDY AFCAN Controller Message buffer transmission request bit 0 No message frame transmitting request that is pending or being transmitted is in the message buffer. 1 The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Message buffer ready bit 0 The message buffer can be written by software. The CAN module cannot write to the message buffer. 1 Writing the message buffer by software is ignored (except a write access to the RDY, TRQ, DN, and MOW bits). The CAN module can write to the message buffer. (b) Write CnMCTRLm 15 14 13 12 11 10 9 8 0 0 0 0 Set IE 0 Set TRQ Set RDY 7 6 5 4 3 2 1 0 0 0 0 Clear MOW Clear IE Clear DN Clear TRQ Clear RDY Clear MOW Setting of MOW bit 0 MOW bit is not changed. 1 MOW bit is cleared to 0. Set IE Clear IE 0 1 IE bit is cleared to 0. 1 0 IE bit is set to 1. Other than above Clear DN Setting of IE bit IE bit is not changed. Setting of DN bit 1 DN bit is cleared to 0. 0 DN bit is not changed. User's Manual U16580EE3V1UD00 805 Chapter 18 AFCAN Controller Set TRQ Clear TRQ 0 1 TRQ bit is cleared to 0. 1 0 TRQ bit is set to 1. Other than above Setting of TRQ bit TRQ bit is not changed. Set RDY Clear RDY 0 1 RDY bit is cleared to 0. 1 0 RDY bit is set to 1. Other than above Setting of RDY bit RDY bit is not changed. Cautions: 1. Set IE bit and RDY bit always separately. 2. Do not set the DN bit to 1 by software. Be sure to write 0 to bit 10. 3. Do not set the TRQ bit and the RDY bit (1) at the same time. Set the RDY bit (1) before setting the TRQ bit. 4. Do not clear the RDY bit (0) during message transmission. Follow the transmission abort process about clearing the RDY bit (0) for redefinition of the message buffer. 5. Clear again when RDY bit is not cleared even if this bit is cleared. 6. Be sure that RDY is cleared before writing to the other message buffer registers, by checking the status of the RDY bit. 806 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.8 CAN Controller Initialization 18.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled. The CAN module is enabled by setting the GOM bit of the CnGMCTRL register. For the procedure of initializing the CAN module, refer to "Operation of CAN Controller" on page 840. 18.8.2 Initialization of message buffer After the CAN module is enabled, the message buffers contain undefined values. A minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the CAN module from the initialization mode to one of the operation modes. * Clear the RDY, TRQ, and DN bits of all CnMCTRLm registers to 0. * Clear the MA0 bit of all CnMCONFm registers to 0. * 18.8.3 Redefinition of message buffer Redefining a message buffer means changing the ID and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) To redefine message buffer in initialization mode Place the CAN module in the initialization mode once and then change the ID and control information of the message buffer in the initialization mode. After changing the ID and control information, set the CAN module to an operation mode. (2) To redefine message buffer during reception Perform redefinition as shown in <~Reference>Figure 18-38. (3) To redefine message buffer during transmission To rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (see "Transmission abort process except for in normal operation mode with automatic block transmission (ABT)" on page 820 and "Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT)" on page 821). Confirm that transmission has been aborted or completed, and then redefine the message buffer. After redefining the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. User's Manual U16580EE3V1UD00 807 Chapter 18 Figure 18-26: AFCAN Controller Setting transmission request (TRQ) to transmit message buffer after redefinition Redefinition completed Execute transmission? No Yes Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions: 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer. If the procedure in <~Reference>Figure 18-38 on page 843 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). If this happens, check that the ID and IDE received first and stored in the message buffer following redefinition are those stored after the message buffer has been redefined. If no ID and IDE are stored after redefinition, redefine the message buffer again. 2. When a message is transmitted, the transmission priority is checked in accordance with the ID, IDE, and RTR bits set to each transmit message buffer to which a transmission request was set. The transmit message buffer having the highest priority is selected for transmission. If the procedure in <~Reference>Figure 1826 on page 808 is not observed, a message with an ID not having the highest priority may be transmitted after redefinition. 18.8.4 Transition from Initialization Mode to Operation Mode The CAN module can be switched to the following operation modes. * Normal operation mode * Normal operation mode with ABT * Receive-only mode * Single-shot mode * Self-test mode 808 User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-27: AFCAN Controller Transition to operation modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H and CAN bus is busy. OPMODE[2:0] = 00H and CAN bus is busy. [Normal operation mode with ABT] OPMODE[2:0]=02H OPMODE[2:0] = 03H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 04H OPMODE[2:0] = 02H 0] = 00H s is busy. [Normal operation mode] OPMODE[2:0]=01H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 01H [Single-shot mode] OPMODE[2:0]=04H OPMODE[2:0] = 00H and interframe space INIT mode OPMODE[2:0] = 00H OPMODE[2:0] = 05H OPMODE[2:0] = 00H and interframe space OPMODE and CAN b [Self-test mode] OPMODE[2:0]=05H GOM = 1 All CAN modules are in INIT mode and GOM = 0 EFSD = 1 and GOM = 0 CAN module channel invalid RESET released RESET The transition from the initialization mode to an operation mode is controlled by the bit string OPMODE[2:0] in the CnCTRL register. Changing from one operation mode into another requires shifting to the initialization mode in between. Do not change one operation mode to another directly; otherwise the operation will not be guaranteed. Requests for transition from an operation mode to the initialization mode are held pending when the CAN bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the CAN module enters the initialization mode at the first bit in the interframe space (the values of the OPMODE[2:0] bits are changed to 000B). After issuing a request to change the mode to the initialization mode, read the OPMODE[2:0] bits until their value becomes 000B to confirm that the module has entered the initialization mode (see <~Reference>Figure 18-36 on page 841). 18.8.5 Resetting error counter CnERC of CAN module If it is necessary to reset the CAN module error counter CnERC and CAN module information register CnINFO when re-initialization or forced recovery from the bus-off status is made, set the CCERC bit of the CnCTRL register to 1 in the initialization mode. When this bit is set to 1, the CnERC and CnINFO registers are cleared to their default values. User's Manual U16580EE3V1UD00 809 Chapter 18 AFCAN Controller 18.9 Message Reception 18.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process). * Used as a message buffer (MA0 bit of CnMCONFm register set to 1.) * Set as a receive message buffer (MT[2:0] bits of CnMCONFm register are set to 001B, 010B, 011B, 100B, or 101B.) * Ready for reception (RDY bit of CnMCTRLm register is set to 1.) When two or more message buffers of the CAN module receive a message, the message is stored according to the priority explained below. The message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. For example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same ID, the received message is not stored in the message buffer linked to mask 1, even if that message buffer has not received a message and a message has already been received in the unmasked receive message buffer. In other words, when a condition has been set in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. This also applies when the message buffer with the highest priority is unable to store a message (i.e., when DN = 1 indicating that a message has already been received, but rewriting is disabled because OWS = 0). In this case, the message is not actually stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. Priority Storing Condition If Same ID Is Set 1 (high) Unmasked message buffer DN bit = 0 DN bit = 1 and OWS bit = 1 2 Message buffer linked to mask 1 DN bit = 0 DN bit = 1 and OWS bit = 1 3 Message buffer linked to mask 2 DN bit = 0 DN bit = 1 and OWS bit = 1 4 Message buffer linked to mask 3 DN bit = 0 DN bit = 1 and OWS bit = 1 5 (low) Message buffer linked to mask 4 DN bit = 0 DN bit = 1 and OWS bit = 1 18.9.2 Receive Data Read To keep data consistency when reading CAN message buffers, perform the data reading according to <~Reference>Figure 18-49 on page 854 to <~Reference>Figure 18-51 on page 856. During message reception, the CAN module sets DN of the CnMCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process. During this storage process, the MUC bit of the CnMCTRLm register of the message buffer is set. (Refer to <~Reference>Figure 18-28 on page 811.) The receive history list is also updated just before the storage process. In addition, during storage process (MUC = 1), the RDY bit of the CnMCTRL register of the message buffer is locked to avoid the coin- 810 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller cidental data WR by CPU. Note the storage process may be disturbed (delayed) when the CPU accesses the message buffer. Figure 18-28: (11) R0 (1) IDE ID RTR SOF CAN std ID format DN and MUC Bit Setting Period (for Standard ID Format) (1) (1) (1) Recessive DLC DATA0-DATA7 CRC (4) (0-64) (16) ACK EOF (2) IFS Dominant (7) Message Store MDATA,MDLC.MIDx- > MBUF DN MUC CINTS1 INTREC1 Operation of the CAN contoroller Set DN & MUC at the same time Set DN & clear MUC at the same timing 18.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding CnLIPT register and the receive history list get pointer (RGPT) with the corresponding CnRGPT register. The RHL is undefined immediately after the transition of the CAN module from the initialization mode to one of the operation modes. The CnLIPT register holds the contents of the RHL element indicated by the value of the LIPT pointer minus 1. By reading the CnLIPT register, therefore, the number of the message buffer that received and stored a data frame or remote frame first can be checked. The LIPT pointer is utilized as a write pointer that indicates to what part of the RHL a message buffer number is recorded. Any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the RHL element indicated by the LIPT pointer. Each time recording to the RHL has been completed, the LIPT pointer is automatically incremented. In this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. The RGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the RHL. This pointer indicates the first RHL element that the CPU has not read yet. By reading the CnRGPT register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. Each time a message buffer number is read from the CnRGPT register, the RGPT pointer is automatically incremented. If the value of the RGPT pointer matches the value of the LIPT pointer, the RHPM bit (receive history list pointer match) of the CnRGPT register is set to 1. This indicates that no message buffer number that has not been read remains in the RHL. If a new message buffer number is recorded, the LIPT pointer is incremented and because its value no longer matches the value of the RGPT pointer, the RHPM bit is cleared. In other words, the numbers of the unread message buffers exist in the RHL. User's Manual U16580EE3V1UD00 811 Chapter 18 AFCAN Controller If the LIPT pointer is incremented and matches the value of the RGPT pointer minus 1, the ROVF bit (receive history list overflow) of the CnRGPT register is set to 1. This indicates that the RHL is full of numbers of message buffers that have not been read. When further message reception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the newly received message. In this case, after the ROVF bit has been set (1), the recorded message buffer numbers in the RHL do not completely reflect the chronological order. However messages itself are not lost and can be located by CPU search in message buffer memory with the help of the DN-bit. Caution: If the history list is in the overflow condition (ROVF is set), reading the history list contents is still possible, until the history list is empty (indicated by RHPM flag set). Nevertheless, the history list remains in the overflow condition, until ROVF is cleared by software. If ROVF is not cleared, the RHPM flag will also not be updated (cleared) upon a message storage of newly received frame. This may lead to the situation, that RHPM indicates an empty history list, although a reception has taken place, while the history list is in the overflow state (ROVF and RHPM are set). As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered. Figure 18-29: Receive history list Receive history list(RHL) Receive history list (RHL) 23 23 22 22 Event: - message buffer 6, 9, 2 and 7 are read by host processor. - Newly received messages are stored in message buffer 3, 4 and 8. : : : Last in-message pointer(LIPT) 7 6 5 4 3 2 1 0 Message buffer 7 Message buffer 2 Message buffer 9 Message buffer 6 Receive history list get pointer (RGPT) : : : 7 6 Last in-message 5 pointer(LIPT) 4 3 2 1 : : : Last in-message pointer(LIPT) 7 Message buffer 5 6 Message buffer 8 5 4 3 Message buffer 4 2 Message buffer 6 Message buffer 11 Message buffer 10 1 0 Receive history list (RHL) Event: - reception in message buffer 13, 14 and 15 occurs. - Overflow situation occurs. 23 22 7 6 5 4 Message buffer 3 ROVF = 1 LIPT is blocked. Receive history list get pointer (RGPT) 0 Message buffer 1 Message buffer 9 Message buffer 4 Message buffer 3 Event: - 20 other messages are received. Message buffer 6 carries last received message. - Upon reception in message buffer 6, RHL is full. - ROVF is set. Receive history list(RHL) 23 22 Message buffer 8 3 2 Receive history list get pointer (RGPT) 1 0 Last in-message pointer(LIPT) Message buffer 1 Message buffer 9 Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 15 Message buffer 11 Message buffer 10 Receive history list get pointer (RGPT) ROVF = 1 LIPT is blocked. ROVF = 1 defines that LIPT equals RGPT - 1 while message buffer number stored to element indicated by LIPT - 1. 812 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer. While the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. However, this comparison is performed for any bit whose value is defined as 0 by the mask. For example, let us assume that all messages that have a standard-format ID, in which bits ID27 to ID25 are 0 and bits ID24 and ID22 are 1, are to be stored in message buffer 14. The procedure for this example is shown below. <1> Identifier to be stored in message buffer ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x Note: x = don't care <2> Identifier to be configured in message buffer 14 (example) (Using CnMIDL14 and CnMIDH14 registers) ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x x x x ID6 ID5 ID4 ID3 ID2 ID1 ID0 x x x x x x x Notes: 1. ID with the ID27 to ID25 bits cleared to 0 and the ID24 and ID22 bits set to 1 is registered (initialized) to message buffer 14. 2. Message buffer 14 is set as a standard format identifier that is linked to mask 1 (MT[2:0] of CnMCONF14 register are set to 010B). User's Manual U16580EE3V1UD00 813 Chapter 18 AFCAN Controller <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID2 8 CMID2 7 CMID2 6 CMID2 5 CMID2 4 CMID2 3 CMID2 2 CMID2 1 CMID2 0 CMID1 9 CMID1 8 1 0 0 0 0 1 0 1 1 1 1 CMID1 7 CMID1 6 CMID1 5 CMID1 4 CMID1 3 CMID1 2 CMID1 1 CMID1 0 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 1 1 1 1 1 1 1 1: Not compared (masked) 0: Compared The CMID27 to CMID24 and CMID22 bits are cleared to 0, and the CMID28, CMID23, and CMID21 to CMID0 bits are set to 1. 18.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type. These message buffers can be allocated anywhere in the message buffer memory, they do not even have to follow each other adjacently. Suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same ID is set to each message buffer. If the first message whose ID matches an ID of the message buffers is received, it is stored in message buffer 10. At this point, the DN bit of message buffer 10 is set, prohibiting overwriting the message buffer when subsequent messages are received. When the next message with a matching ID is received, it is received and stored in message buffer 11. Each time a message with a matching ID is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. Even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previously received matching-ID data. Whether a data block has been received and stored can be checked by setting the IE bit of the CnMCTRLm register of each message buffer. For example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. The IE bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the IE bit in message buffer k-1 is set to 1 (interrupts enabled). In this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that MBRB has become full. Alternatively, by clearing the IE bit of message buffers 0 to (k-3) and setting the IE bit of message buffer k-2, a warning that MBRB is about to overflow can be issued. The basic conditions of storing receive data in each message buffer for the MBRB are the same as the conditions of storing data in a single message buffer. Caution 1. MBRB can be configured for each of the same message buffer types. Therefore, even if a message buffer of another MBRB whose ID matches but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. MBRB does not have a ring buffer structure. Therefore, after a message is stored in the message buffer having the highest number in the MBRB configuration, a newly received message will not be stored in the message buffer having the lowest message buffer number. 3. MBRB operates based on the reception and storage conditions; there are no settings dedicated to MBRB, such as function enable bits. By setting the same message buffer type and ID to two or more message buffers, MBRB is automatically configured. 4. With MBRB, "matching ID" means "matching ID after mask". Even if the ID set to each message 814 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller buffer is not the same, if the ID that is masked by the mask register matches, it is considered a matching ID and the buffer that has this ID is treated as the storage destination of a message. 5. The priority between MBRBs is mentioned in the table on page 810. 18.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. * Used as a message buffer (MA0 bit of CnMCONFm register set to 1.) * Set as a transmit message buffer (MT[2:0] bits in CnMCONFm register set to 000B) * Ready for reception (RDY bit of CnMCTRLm register set to 1.) * Set to transmit message (RTR bit of CnMCONFm register is cleared to 0.) * Transmission request is not set. (TRQ bit of CnMCTRLm register is cleared to 0.) Upon acceptance of a remote frame, the following actions are executed if the ID of the received remote frame matches the ID of a message buffer that satisfies the above conditions. * The DLC[3:0] bit string in the CnMDLCm register store the received DLC value. * The CnMDATA0m to CnMDATA7m registers in the data area are not updated (data before reception is saved). * The DN bit of the CnMCTRLm register is set to 1. * The CINTS1 bit of the CnINTS register is set to 1 (if the IE bit in the CnMCTRLm register of the message buffer that receives and stores the frame is set to 1). * The receive completion interrupt (INTCnREC) is output (if the IE bit of the message buffer that receives and stores the frame is set to 1 and if the CIE1 bit of the CnIE register is set to 1). * The message buffer number is recorded in the receive history list. Caution When a message buffer is searched for receiving and storing a remote frame, overwrite control by the OWS bit of the CnMCONFm register of the message buffer and the DN bit of the CnMCTRLm register are not checked. The setting of OWS is ignored, and DN is set in any case. If more than one transmit message buffer has the same ID and the ID of the received remote frame matches that ID, the remote frame is stored in the transmit message buffer with the lowest message buffer number. User's Manual U16580EE3V1UD00 815 Chapter 18 AFCAN Controller 18.10 Message Transmission 18.10.1 Message transmission A message buffer with its TRQ bit set to 1 participates in the search for the most high-prioritized message when the following conditions are fulfilled. This behavior is valid for all operational modes. * Used as a message buffer (MA0 bit of CnMCONFm register set to 1B.) * Set as a transmit message buffer (MT[2:0] bits of CnMCONFm register set to 000B.) * Ready for transmission (RDY bit of CnMCTRLm register set to 1.) The CAN system is a multi-master communication system. In a system like this, the priority of message transmission is determined based on message identifiers (IDs). To facilitate transmission processing by software when there are several messages awaiting transmission, the CAN module uses hardware to check the ID of the message with the highest priority and automatically identifies that message. This eliminates the need for software-based priority control. Transmission priority is controlled by the identifier (ID). Figure 18-30: Message processing example Message No. Message waiting to be transmitted 0 1 ID = 120H 2 ID = 229H 3 4 5 ID = 223H 6 ID = 023H The CAN module transmits messages in the following sequence. 1. Message 6 2. Message 1 3. Message 8 4. Message 5 5. Message 2 7 8 ID = 123H 9 After the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the TRQ bit set to 1 in advance) is transmitted. If a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. If the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. If transmission of a message with a low priority has already started, however, the new transmission request is transmitted later. To solve this priority inversion effect, the software can perform a transmission abort request for the lower priority message. The highest priority is determined according to the following rules. 816 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller Priority Conditions Description 1 (high) Value of first 11 bits of ID [ID28 to ID18]: The message frame with the lowest value represented by the first 11 bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11bit standard ID has a higher priority than a message frame with a 29-bit extended ID. 2 Frame type A data frame with an 11-bit standard ID (RTR bit is cleared to 0) has a higher priority than a remote frame with a standard ID and a message frame with an extended ID. 3 ID type A message frame with a standard ID (IDE bit is cleared to 0) has a higher priority than a message frame with an extended ID. 4 Value of lower 18 bits of ID [ID17 to ID0]: If one or more transmission-pending extended ID message frame has equal values in the first 11 bits of the ID and the same frame type (equal RTR bit values), the message frame with the lowest value in the lower 18 bits of its extended ID is transmitted first. 5 (low) Message buffer number If two or more message buffers request transmission of message frames with the same ID, the message from the message buffer with the lowest message buffer number is transmitted first. Notes: 1. If the automatic block transmission request bit ABTTRG is set to 1 in the normal operation mode with ABT, the TRQ bit is set to 1 only for one message buffer in the ABT message buffer group. If the ABT mode was triggered by ABTTRG bit (1), one TRQ bit is set to 1 in the ABT area (buffer 0 through 7). Beyond this TRQ bit, the application can request transmissions (set TRQ bit to 1) for other TX-message buffers that do not belong to the ABT area. In that case an interval arbitration process (TX-search) evaluates all TX-message buffers with TRQ bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. If there are 2 or more identifiers that have the highest priority (i.e. identical identifiers), the message located at the lowest message buffer number is transmitted at first. Upon successful transmission of a message frame, the following operations are performed. * The TRQ flag of the corresponding transmit message buffer is automatically cleared to 0. * The transmission completion status bit CINTS0 of the CnINTS register is set to 1 (if the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1). * An interrupt request signal INTCnTRX is output (if the CIE0 bit of the CnIE register is set to 1 and if the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1). 2. When changing the contents of a transmit buffer, the RDY flag of this buffer must be cleared before updating the buffer contents. As during internal transfer actions, the RDY flag may be locked temporarily, the status of RDY must be checked by software, after changing it. 18.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the transmit history list get pointer (TGPT) with the corresponding CnTGPT register. The THL is undefined immediately after the transition of the CAN module from the initialization mode to one of the operation modes. The CnLOPT register holds the contents of the THL element indicated by the value of the LOPT pointer minus 1. By reading the CnLOPT register, therefore, the number of the message buffer that transmitted User's Manual U16580EE3V1UD00 817 Chapter 18 AFCAN Controller a data frame or remote frame first can be checked. The LOPT pointer is utilized as a write pointer that indicates to what part of the THL a message buffer number is recorded. Any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the THL element indicated by the LOPT pointer. Each time recording to the THL has been completed, the LOPT pointer is automatically incremented. In this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. The TGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the THL. This pointer indicates the first THL element that the CPU has not yet read. By reading the CnTGPT register by software, the number of a message buffer that has completed transmission can be read. Each time a message buffer number is read from the CnTGPT register, the TGPT pointer is automatically incremented. If the value of the TGPT pointer matches the value of the LOPT pointer, the THPM bit (transmit history list pointer match) of the CnTGPT register is set to 1. This indicates that no message buffer numbers that have not been read remain in the THL. If a new message buffer number is recorded, the LOPT pointer is incremented and because its value no longer matches the value of the TGPT pointer, the THPM bit is cleared. In other words, the numbers of the unread message buffers exist in the THL. If the LOPT pointer is incremented and matches the value of the TGPT pointer minus 1, the TOVF bit (transmit history list overflow) of the CnTGPT register is set to 1. This indicates that the THL is full of message buffer numbers that have not been read. If a new message is received and stored, the message buffer number recorded last is overwritten by the message buffer number that transmitted its message afterwards. In this case, after the TOVF bit has been set (1), therefore, the recorded message buffer numbers in the THL do not completely reflect the chronological order. However the other transmitted messages can be found by a CPU search applied to all transmit message buffers unless the CPU has not overwritten a transmit object in one of these buffers beforehand. In total up to six transmission completions can occur without overflowing the THL. Caution: 818 If the history list is in the overflow condition (TOVF is set), reading the history list contents is still possible, until the history list is empty (indicated by THPM flag set). Nevertheless, the history list remains in the overflow condition, until TOVF is cleared by software. If TOVF is not cleared, the THPM flag will also not be updated (cleared) upon successful transmission of a new message. This may lead to the situation, that THPM indicates an empty history list, although a successful transmission has taken place, while the history list is in the overflow state (TOVF and THPM are set). User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-31: AFCAN Controller Transmit history list Transmit history list(THL) Transmit history list(THL) 7 6 5 4 Last out-message 3 pointer(LOPT) 2 1 Message buffer 7 7 Event: - CPU confirms TX completion of message buffer 6, 9 and 2 - TX completion of message buffer 3 and 4 6 5 Last out- 4 message 3 pointer 2 (LOPT) 1 0 Message buffer 2 Message buffer 9 Message buffer 6 0 Transmit history list get pointer(TGPT) Message buffer 5 6 5 4 3 2 Last out-message 1 pointer(LOPT) 0 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Message buffer 10 Message buffer 6 Message buffer 7 Transmit history list get pointer(TGPT) Event: - message buffer 8, 5, 6 and 10 completes transmission - THL is full - TOVF is set Transmit history list(THL) Transmit history list(THL) 7 Message buffer 4 Message buffer 3 Event: - message buffer 11, 13 and 14 completes transmission. - Overflow situation occurs. Transmit history list get pointer(TGPT) TOVF = 1 LOPT is blocked 7 6 5 4 3 2 1 0 Last out-message pointer(LOPT) Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Message buffer 14 Message buffer 6 Transmit history list get pointer (TGPT) TOVF = 1 LOPT is blocked TOVF = 1 defines that LOPT equals TOPT - 1 while message buffer number stored to element indicated by LOPT - 1. 18.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7). By setting the OPMODE[2:0] bits of the CnCTRL register to 010B, "normal operation mode with automatic block transmission function" (hereafter referred to as ABT mode) can be selected. To issue an ABT transmission request, define the message buffers by software first. Set the MA0 bit (1) in all the message buffers used for ABT, and define all the buffers as transmit message buffers by setting the MA[2:0] bits to 000B. Be sure to set the same ID for the message buffers for ABT even when that ID is being used for all the message buffers. To use two or more IDs, set the ID of each message buffer by using the CnMIDLm and CnMIDHm registers. Set the CnMDLCm and CnMDATA0m to CnMDATA7m registers before issuing a transmission request for the ABT function. After initialization of message buffers for ABT is finished, the RDY bit needs to be set (1). In the ABT mode, the TRQ bit does not have to be manipulated by software. After the data for the ABT message buffers has been prepared, set the ABTTRG bit to 1. Automatic block transmission is then started. When ABT is started, the TRQ bit in the first message buffer (message buffer 0) is automatically set to 1. After transmission of the data of message buffer 0 is finished, the TRQ bit of the next message buffer, message buffer 1, is set automatically. In this way, transmission is executed successively. A delay time can be inserted by program in the interval in which the transmission request (TRQ) is automatically set while successive transmission is being executed. The delay time to be inserted is defined by the CnGMABTD register. The unit of the delay time is DBT (data bit time). DBT depends on the setting of the CnBRP and CnBTR registers. Among transmit objects within the ABT-area, the priority of the transmission ID is not evaluated. The data of message buffers 0 to 7 are sequentially transmitted. When transmission of the data frame from message buffer 7 has been completed, the ABTTRG bit is automatically cleared to 0 and the ABT operation is finished. If the RDY bit of an ABT message buffer is cleared during ABT, no data frame is transmitted from that buffer, ABT is stopped, and the ABTTRG bit is cleared. After that, transmission can be resumed from User's Manual U16580EE3V1UD00 819 Chapter 18 AFCAN Controller the message buffer where ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not resume transmission from the message buffer where ABT stopped, the internal ABT engine can be reset by setting the ABTCLR bit to 1 while ABT mode is stopped and the ABTTRG bit is cleared to 0. In this case, transmission is started from message buffer 0 if the ABTCLR bit is cleared to 0 and then the ABTTRG bit is set to 1. An interrupt can be used to check if data frames have been transmitted from all the message buffers for ABT. To do so, the IE bit of the CnMCTRLm register of each message buffer except the last message buffer needs to be cleared (0). If a transmit message buffer other than those used by the ABT function (message buffers 8 to 31) is assigned to a transmit message buffer, the message to be transmitted next is determined by the priority of the transmission ID of the ABT message buffer whose transmission is currently held pending and the transmission ID of the message buffers other than those used by the ABT function. Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). Cautions: 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed. 2. If the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the ABTCLR bit is automatically cleared immediately after the processing of the clearing request is completed. 3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the ABT mode. 4. Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal operation mode with ABT. Otherwise, the operation is not guaranteed. 5. The CnGMABTD register is used to set the delay time that is inserted in the period from completion of the preceding ABT message to setting of the TRQ bit for the next ABT message when the transmission requests are set in the order of message numbers for each message for ABT that is successively transmitted in the ABT mode. The timing at which the messages are actually transmitted onto the CAN bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other than the ABT messages (message buffers 8 to 31). 6. If a transmission request is made for a message other than an ABT message and if no delay time is inserted in the interval in which transmission requests for ABT are automatically set (CnGMABTD register = 00H), messages other than ABT messages may be transmitted not depending on their priority compared to the priority of the ABT message. 7. Do not clear the RDY bit to 0 when the ABTTRG bit = 1. 8. If a message is received from another node while normal operation mode with ABT is active, the TX-message from the ABT-area may be transmitted with delay of one frame although CnGMABTD register was set up with 00H. 18.10.4 Transmission abort process (1) Transmission abort process except for in normal operation mode with automatic block transmission (ABT) The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the TSTAT bit of the CnCTRL register and the CnTGPT register, which indicate the transmission status on the CAN bus (for details, refer to the processing in <~Reference>Figure 18-45 on page 850). 820 User's Manual U16580EE3V1UD00 Chapter 18 (2) AFCAN Controller Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT) The user can clear the ABTTRG bit of the CnGMABT register to 0 to abort a transmission request. After checking the ABTTRG bit of the CnGMABT register = 0, clear the TRQ bit of the CnMCTRLm register to 0. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the TSTAT bit of the CnCTRL register and the CnTGPT register, which indicate the transmission status on the CAN bus (for details, refer to the processing in <~Reference>Figure 18-46 on page 850). (3) Transmission abort process for ABT transmission in normal operation mode with automatic block transmission (ABT) To abort ABT that is already started, clear the ABTTRG bit of the CnGMABT register to 0. In this case, the ABTTRG bit remains 1 if an ABT message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. This aborts ABT. If the last transmission (before ABT) was successful, the normal operation mode with ABT is left with the internal ABT pointer pointing to the next message buffer to be transmitted. In the case of an erroneous transmission, the position of the internal ABT pointer depends on the status of the TRQ bit in the last transmitted message buffer. If the TRQ bit is set to 1 when clearing the ABTTRG bit is requested, the internal ABT pointer points to the last transmitted message buffer (for details, refer to the process in <~Reference>Figure 18-47 on page 852). If the TRQ bit is cleared to 0 when clearing the ABTTRG bit is requested, the internal ABT pointer is incremented (+1) and points to the next message buffer in the ABT area (for details, refer to the process in <~Reference>Figure 18-48 on page 853). Caution: Be sure to abort ABT by clearing ABTTRG bit to 0. The operation is not guaranteed if aborting transmission is requested by clearing RDY. When the normal operation mode with ABT is resumed after ABT has been aborted and the ABTTRG bit is set to 1, the next ABT message buffer to be transmitted can be determined from the following table. Status of TRQ of ABT message buffer Abort after successful transmission Abort after erroneous transmission Set (1) Next message buffer in the ABT areaNote Same message buffer in the ABT area Cleared (0) Note Next message buffer in the ABT area Next message buffer in the ABT areaNote Note: The above resumption operation can be performed only if a message buffer ready for ABT exists in the ABT area. For example, an abort request that is issued while ABT of message buffer 7 is in progress is regarded as completion of ABT, rather than abort, if transmission of message buffer 7 has been successfully completed, even if the ABTTRG bit is cleared to 0. If the RDY bit in the next message buffer in the ABT area is cleared to 0, the internal ABT pointer is retained, but the resumption operation is not performed even if the ABTTRG bit is set to 1, and ABT ends immediately. 18.10.5 Remote frame transmission Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame is transmitted via the RTR bit of the CnMCONFm register. Setting (1) the RTR bit sets remote frame transmission. User's Manual U16580EE3V1UD00 821 Chapter 18 AFCAN Controller 18.11 Power Saving Modes 18.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN Controller to stand-by mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered. In the CAN sleep mode, the CAN module does not transmit messages, even when transmission requests are issued or pending. (1) Entering CAN sleep mode The CPU issues a CAN sleep mode transition request by writing 01B to the PSMODE[1:0] bits of the CnCTRL register. This transition request is only acknowledged only under the following conditions. (i) The CAN module is already in one of the following operation modes * Normal operation mode * Normal operation mode with ABT * Receive-only mode * Single-shot mode * Self-test mode * CAN stop mode in all the above operation modes (ii) The CAN bus state is bus idle (the 4th bit in the interframe space is recessive)Note (iii) No transmission request is pending Note: If the CAN bus is fixed to dominant, the request for transition to the CAN sleep mode is held pending.Also the transition from CAN stop mode to CAN sleep mode is independent of the CAN bus state. Remark: If a sleep mode request is pending, and at the same time a message is received in a message box, the sleep mode request is not cancelled, but is executed right after message storage has been finished. This may result in AFCAN being in sleep mode, while the CPU would execute the RX interrupt routine. Therefore, the interrupt routine must check the access to the message buffers as well as reception history list registers by using the MBON flag, if sleep mode is used. If any one of the conditions mentioned above is not met, the CAN module will operate as follows. * If the CAN sleep mode is requested from the initialization mode, the CAN sleep mode transition request is ignored and the CAN module remains in the initialization mode. * If the CAN bus state is not bus idle (i.e., the CAN bus state is either transmitting or receiving) when the CAN sleep mode is requested in one of the operation modes, immediate transition to the CAN sleep mode is not possible. In this case, the CAN sleep mode transition request has to be held pending until the CAN bus state becomes bus idle (the 4th bit in the interframe space is recessive). In the time from the CAN sleep mode request to successful transition, the PSMODE[1:0] bits remain 00B. When the module has entered the CAN sleep mode, the PSMODE[1:0] bits are set to 01B. * If a request for transition to the initialization mode and a request for transition to the CAN sleep mode are made at the same time while the CAN module is in one of the operation modes, the request for the initialization mode is enabled. The CAN module enters the initialization mode at a 822 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller predetermined timing. At this time, the CAN sleep mode request is not held pending and is ignored. * Even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request. The sleep mode request is cancelled when the initialization mode is requested. When a pending request for initialization mode is present, a subsequent request for Sleep mode request is cancelled right at the point in time where it was submitted. (2) Status in CAN sleep mode The CAN module is in the following state after it enters the CAN sleep mode: * The internal operating clock is stopped and the power consumption is minimized. * The function to detect the falling edge of the CAN reception pin (CRXDn) remains in effect to wake up the CAN module from the CAN bus. * To wake up the CAN module from the CPU, data can be written to the PSMODE[1:0] bits of the CAN module control register (CnCTRL), but nothing can be written to other CAN module registers or bits. * The CAN module registers can be read, except for the CnLIPT, CnRGPT, CnLOPT, and CnTGPT registers. * The CAN message buffer registers cannot be written or read. * MBON bit of the CAN Global Control register (CnGMCTRL) is cleared. * A request for transition to the initialization mode is not acknowledged and is ignored. User's Manual U16580EE3V1UD00 823 Chapter 18 (3) AFCAN Controller Releasing CAN sleep mode The CAN sleep mode is released by the following events: * When the CPU writes 00B to the PSMODE[1:0] bits of the CnCTRL register * A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant) Caution Even if the falling edge belongs to the SOF of a receive message, this message will not be received and stored. If the CPU has turned off the clock supply to the CAN module while the CAN module was in sleep mode, even subsequently the CAN sleep mode will not be released and PSMODE [1:0] will remain 01B unless the clock to the CAN module is supplied again. In addition to this, the receive message will not be received after that. After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep mode was requested and the PSMODE[1:0] bits of the CnCTRL register must be reset by software to 00B. If the CAN sleep mode is released by a change in the CAN bus state, the CINTS5 bit of the CnINTS register is set to 1, regardless of the CIE bit of the CnIE register. After the CAN module is released from the CAN sleep mode, it participates in the CAN bus again by automatically detecting 11 consecutive recessive-level bits on the CAN bus. The user application has to wait until MBON = 1, before accessing message buffers again. When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep mode, that request is ignored; the CAN module has to be released from sleep mode by software first before entering the initialization mode. Caution 1. Be aware that the release of CAN sleep mode by CAN bus event, and thus the wake up interrupt may happen at any time, even right after requesting sleep mode, if a CAN bus event occurs. 2. Always reset the PSMODE[1:0] bits to 00B, when waking up from CAN sleep mode, before accessing any other registers of the CAN module. 3. Always clear the interrupt flag CINTS5, when waking up from CAN sleep mode. 18.11.2 CAN stop mode The CAN stop mode can be used to set the CAN Controller to stand-by mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode. The CAN stop mode can only be released (entering CAN sleep mode) by writing 01B to the PSMODE[1:0] bits of the CnCTRL register and not by a change in the CAN bus state. No message is transmitted even when transmission requests are issued or pending. (1) Entering CAN stop mode A CAN stop mode transition request is issued by writing 11B to the PSMODE[1:0] bits of the CnCTRL register. A CAN stop mode request is only acknowledged when the CAN module is in the CAN sleep mode. In all other modes, the request is ignored. Caution 824 To set the CAN module to the CAN stop mode, the module must be in the CAN sleep mode. To confirm that the module is in the sleep mode, check that the PSMODE[1:0] bits = 01B, and then request the CAN stop mode. If a bus change occurs at the CAN reception pin (CRXDn) while this process is being performed, the CAN sleep mode is automatically released. In this case, the CAN stop mode transition request cannot be acknowledged. User's Manual U16580EE3V1UD00 Chapter 18 (2) AFCAN Controller Status in CAN stop mode The CAN module is in the following state after it enters the CAN stop mode. * The internal operating clock is stopped and the power consumption is minimized. * To wake up the CAN module from the CPU, data can be written to the PSMODE[1:0] bits of the CAN module control register (CnCTRL), but nothing can be written to other CAN module registers or bits. * The CAN module registers can be read, except for the CnLIPT, CnRGPT, CnLOPT, and CnTGPT registers. * The CAN message buffer registers cannot be written or read. * MBON bit of the CAN Global Control register (CnGMCTRL) is cleared. * An initialization mode transition request is not acknowledged and is ignored. (3) Releasing CAN stop mode The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bits of the CnCTRL register. After releasing the CAN stop mode, the CAN module enters the CAN sleep mode. When the initialization mode is requested while the CAN module is in the CAN stop mode, that request is ignored; the CPU has to release the stop mode and subsequently CAN sleep mode before entering the initialization mode. It is impossible to enter the other operation mode directly from the CAN stop mode not entering the CAN sleep mode, that request is ignored. 18.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus. Here is an example for using the power saving modes. * First, put the CAN module in the CAN sleep mode (PSMODE[1:0] = 01B). Next, put the CPU in the power saving mode. If an edge transition from recessive to dominant is detected at the CAN reception pin (CRXDn) in this status, the CINTS5 bit in the CAN module is set to 1. If the CIE5 bit of the CnCTRL register is set to 1, a wakeup interrupt (INTWUPn) is generated. * The CAN module is automatically released from CAN sleep mode (PSMODE = 00B) and returns to normal operation mode. * The CPU, in response to INTWUPn, can release its own power saving mode and return to normal operation mode. To further reduce the power consumption of the CPU, the internal clocks-- including that of the CAN module--may be stopped. In this case, the operating clock supplied to the CAN module is stopped after the CAN module has been put in CAN sleep mode. Then the CPU enters a power saving mode in which the clock supplied to the CPU is stopped. * If an edge transition from recessive to dominant is detected at the CAN reception pin (CRXDn) in this status, the CAN module can set the CINTS5 bit to 1 and generate the wakeup interrupt (INTWUPn) even if it is not supplied with the clock. * The other functions, however, do not operate, because clock supply to the CAN module is stopped, and the module remains in CAN sleep mode. * The CPU, in response to INTWUPn User's Manual U16580EE3V1UD00 825 Chapter 18 AFCAN Controller - releases its power saving mode, - resumes supply of the internal clocks--including the clock to the CAN module--after the oscillation stabilization time has elapsed, and - starts instruction execution. * The CAN module is immediately released from the CAN sleep mode when clock supply is resumed, and returns to the normal operation mode (PSMODE = 00B). 826 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. After an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software. Table 18-1: Interrupt status bit List of CAN module interrupt sources Name Register Name Register Interrupt request signal 1 CINTS0 CnINTS CIE0Note CnIE INTCnTRX Message frame successfully transmitted from message buffer m 2 CINTS1 CnINTS CIE1Note CnIE INTCnREC Valid message frame reception in message buffer m 3 CINTS2 CnINTS CIE2 CnIE INTCnERR CAN module error state interrupt (Supplement 1) 4 CINTS3 CnINTS CIE3 CnIE CAN module protocol error interrupt (Supplement 2) 5 CINTS4 CnINTS CIE4 CnIE CAN module arbitration loss interrupt 6 CINTS5 CnINTS CIE5 CnIE No. Interrupt enable bit INTCnWUP Interrupt source description CAN module wakeup interrupt from CAN sleep mode (Supplement 3) Note: The IE bit (message buffer interrupt enable bit) in the CnMCTRL register of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process. Notes: 1. This interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 2. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs. 3. This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a falling edge is detected at the CAN reception pin (CAN bus transition from recessive to dominant). User's Manual U16580EE3V1UD00 827 Chapter 18 AFCAN Controller 18.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 18.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes. For example, this mode can be used for automatic baud-rate detection. The baud rate in the CAN module is changed until "valid reception" is detected, so that the baud rates in the module match ("valid reception" means a message frame has been received in the CAN protocol layer without occurrence of an error and with an appropriate ACK between nodes connected to the CAN bus). A valid reception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). The event of valid reception is indicated by setting the VALID bit of the CnCTRL register (1). Figure 18-32: CAN module terminal connection in receive-only mode CAN macro Tx Rx Fixed to the recessive level CTXDn CRXDn In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit requests issued for message buffers defined as transmit message buffers are held pending. In the receive-only mode, the CAN transmission pin (CTXDn) in the CAN module is fixed to the recessive level. Therefore, no active error flag can be transmitted from the CAN module to the CAN bus even when a CAN bus error is detected while receiving a message frame. Since no transmission can be issued from the CAN module, the transmission error counter the CnERC.TEC7 to CnERC.TEC0 bits are never updated. Therefore, a CAN module in the receive-only mode does not enter the bus-off state. Furthermore, in the receive-only mode ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame. Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus. Caution 828 If only two CAN nodes are connected to the CAN bus and one of them is User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller operating in the receive-only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. The transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). After the message frame for the 17th time is transmitted, the transmitting node generates a passive error flag. The receiving node in the receive-only mode detects the first valid message frame at this point, and the VALID bit is set to 1 for the first time. 18.13.2 Single-shot mode In the single-shot mode, automatic re-transmission as defined in the CAN protocol is switched off. (According to the CAN protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.) All other behavior of single shot mode is identical to normal operation mode. Features of single shot mode can not be used in combination with normal mode with ABT. The single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the AL bit of the CnCTRL register. When the AL bit is cleared to 0, retransmission upon arbitration loss and upon error occurrence is disabled. If the AL bit is set to 1, retransmission upon error occurrence is disabled, but re-transmission upon arbitration loss is enabled. As a consequence, the TRQ bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events: * Successful transmission of the message frame * Arbitration loss while sending the message frame * Error occurrence while sending the message frame The events arbitration loss and error occurrence can be distinguished by checking the CINTS4 and CINTS3 bits of the CnINTS register respectively, and the type of the error can be identified by reading the LEC[2:0] bits of the CnLEC register. Upon successful transmission of the message frame, the transmit completion interrupt bit CINTS0 of the CnINTS register is set to 1. If the CIE0 bit of the CnIE register is set to 1 at this time, an interrupt request signal is output. The single-shot mode can be used when emulating time-triggered communication methods (e.g., TTCAN level 1). Caution The AL bit is only valid in Single-shot mode. It does not influence the operation of re-transmission upon arbitration loss in the other operation modes. 18.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back. The CAN transmission pin (CTXDn) is fixed to the recessive level. If the falling edge on the CAN reception pin (CRXDn) is detected after the CAN module has entered the CAN sleep mode from the self-test mode, however, the module is released from the CAN sleep mode in the same manner as the other operation modes. To keep the module in the CAN sleep mode, use the CAN reception pin (CRXDn) as a port pin. User's Manual U16580EE3V1UD00 829 Chapter 18 Figure 18-33: AFCAN Controller CAN module terminal connection in self-test mode CAN macro Tx Rx Fixed to the recessive level CTXDn CRXDn 18.13.4 Receive/Transmit Operation in Each Operation Mode The following table shows outline of the receive/transmit operation in each operation mode. Transmiss ion of Transmiss Transmissi error/ ion of ACK on retry overload frame Operation Mode Transmissi on of data/ remote frame Automatic Block Transmissi on (ABT) Set of VALID bit Store Data to message buffer Initialization Mode No No No No No No No Normal Operation Mode Yes Yes Yes Yes No Yes Yes Normal Operation Mode with ABT Yes Yes Yes Yes Yes Yes Yes Receiveonly mode No No No No No Yes Yes Single-shot Mode Yes Yes Yes NoNote1 No Yes Yes Self-test Mode YesNote2 YesNote2 YesNote2 YesNote2 No YesNote2 YesNote2 Table 18-2: Outline of the Receive/Transmit in Each Operation Mode Notes: 1. When the arbitration lost occurs, control of re-transmission is possible by the AL bit of CnCTRL register. 2. Each signals are not generated to outside, but generated into the CAN module. 830 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller 18.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies). In some applications, however, a common time base over the network (= global time base) is needed. In order to build up a global time base, a time stamp function is used. The essential mechanism of a time stamp function is the capture of timer values triggered by signals on the CAN bus. 18.14.1 Time stamp function The CAN Controller supports the capturing of timer values triggered by a specific frame. An on-chip 16bit capture timer unit in a microcontroller system is used in addition to the CAN Controller. The 16-bit capture timer unit captures the timer value according to a trigger signal (TSOUT) for capturing that is output when a data frame is received from the CAN Controller. The CPU can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the CAN bus, by reading the captured value. The TSOUT signal can be selected from the following two event sources and is specified by the TSSEL bit of the CnTS register. * SOF event (start of frame) (TSSEL = 0) * EOF event (last bit of end of frame) (TSSEL = 1) The TSOUT signal is enabled by setting the TSEN bit of the CnTS register to 1. Figure 18-34: SOF Timing diagram of capture signal TSOUT SOF SOF SOF TSOUT t The TSOUT signal toggles its level upon occurrence of the selected event during data frame reception (in <~Reference>Figure 18-34, the SOF is used as the trigger event source). To capture a timer value by using the TSOUT signal, the capture timer unit must detect the capture signal at both the rising edge and falling edge. This time stamp function is controlled by the TSLOCK bit of the CnTS register. When TSLOCK is cleared to 0, the TSOUT signal toggles upon occurrence of the selected event. If TSLOCK is set to 1, the TSOUT signal toggles upon occurrence of the selected event, but the toggle is stopped as the TSEN bit is automatically cleared to 0 as soon as the message storing to the message buffer 0 starts. This suppresses the subsequent toggle occurrence by the TSOUT signal, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame. Toggle of the TSOUT signal does not stop when a data frame is received in a message buffer other than message buffer 0. For these reasons, a data frame cannot be received in message buffer 0 when the CAN module is in the normal operation mode with ABT, because message buffer 0 must be set as a transmit message buffer. In this operation mode, therefore, the function to stop toggle of the TSOUT signal by the TSLOCK bit cannot be used. User's Manual U16580EE3V1UD00 831 Chapter 18 AFCAN Controller 18.15 Baud Rate Settings 18.15.1 Baud rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN Controller, as follows. * 5TQ SPT (sampling point) 17 TQ SPT = TSEG1 + 1 * 8 TQ DBT (data bit time) 25 TQ DBT = TSEG1 + TSEG2 + 1TQ = TSEG2 + SPT * 1 TQ SJW (synchronization jump width) 4TQ SJW DBT - SPT * 4 TSEG1 16 [3 Setting value of TSEG1[3:0] 15] * 1 TSEG2 8 [0 Setting value of TSEG2[2:0] 7] Notes: 1. TQ = 1/fTQ (fTQ: CAN protocol layer basic system clock) 2. TSEG1[3:0] (Bits 3 to 0 of CAN bit rate register (CnBTR)) 3. TSEG2[2:0] (Bits 10 to 8 of CAN bit rate register (CnBTR)) 832 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller <~Reference>Table 18-3 shows the combinations of bit rates that satisfy the above conditions. Table 18-3: Settable bit rate combinations (1/3) CnBTR register setting value Valid bit rate setting Sampling point unit (%) DBT length SYNC SEGMENT PROP SEGMENT PHASE SEGMENT1 PHASE SEGMENT2 TSEG1 [3:0] TSEG2 [2:0] 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 User's Manual U16580EE3V1UD00 833 Chapter 18 Table 18-3: AFCAN Controller Settable bit rate combinations (2/3) CnBTR register setting value Valid bit rate setting Sampling point unit (%) DBT length SYNC SEGMENT PROP SEGMENT PHASE SEGMENT1 PHASE SEGMENT2 TSEG1 [3:0] TSEG2 [2:0] 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 834 User's Manual U16580EE3V1UD00 Chapter 18 Table 18-3: AFCAN Controller Settable bit rate combinations (3/3) CnBTR register setting value Valid bit rate setting Sampling point unit (%) DBT length SYNC SEGMENT PROP SEGMENT PHASE SEGMENT1 PHASE SEGMENT2 TSEG1 [3:0] TSEG2 [2:0] 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7Note 1 2 2 2 0011 001 71.4 7Note 1 4 1 1 0100 000 85.7 6Note 1 1 2 2 0010 001 66.7 6Note 1 3 1 1 0011 000 83.3 5Note 1 2 1 1 0010 000 80.0 Note 1 1 1 1 0001 000 75.0 4 Note: Setting with a DBT value of 7 or less is valid only when the value of the CnBRP register is other than 00H. Caution The values in <~Reference>Table 18-3 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. User's Manual U16580EE3V1UD00 835 Chapter 18 AFCAN Controller 18.15.2 Representative examples of baud rate settings <~Reference>Table 18-4 and <~Reference>Table 18-5 show representative examples of baud rate settings. Table 18-4: Representative examples of baud rate settings (fCANMOD = 8 MHz) (1/2) Set baud rate value (unit: kbps) Division ratio of CnBRP register CnBRP register set value 1000 1 1000 CnBTR register setting value Valid bit rate setting (unit: kbps) Length of DBT SYNC SEGMENT PROP SEGMENT TSEG1 [3:0] TSEG2 [2:0] 00000000 8 1 1 3 3 0011 010 62.5 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3 100 8 00000111 10 1 3 3 3 0101 010 70.0 836 PHASE PHASE SEGMENT1 SEGMENT2 Sampling point unit: (%) User's Manual U16580EE3V1UD00 Chapter 18 Table 18-4: Set baud rate value (unit: kbps) Division ratio of CnBRP register CnBRP register set value 100 8 100 AFCAN Controller Representative examples of baud rate settings (fCANMOD = 8 MHz) (2/2) CnBTR register setting value Valid bit rate setting (unit: kbps) Length of DBT SYNC SEGMENT PROP SEGMENT TSEG1 [3:0] TSEG2 [2:0] 00000111 10 1 5 2 2 0110 001 80.0 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 Caution PHASE PHASE SEGMENT1 SEGMENT2 Sampling point unit: (%) The values in <~Reference>Table 18-4 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. User's Manual U16580EE3V1UD00 837 Chapter 18 Table 18-5: Set baud rate value (unit: kbps) Division ratio of CnBRP register CnBRP register set value 1000 1 1000 AFCAN Controller Representative examples of baud rate settings (fCANMOD = 16 MHz) (1/2) CnBTR register setting value Valid bit rate setting (unit: kbps) Length of DBT SYNC SEGMENT PROP SEGMENT TSEG1 [3:0] TSEG2 [2:0] 00000000 16 1 1 7 7 0111 110 56.3 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0 838 PHASE PHASE SEGMENT1 SEGMENT2 Sampling point unit: (%) User's Manual U16580EE3V1UD00 Chapter 18 Table 18-5: Set baud rate value (unit: kbps) Division ratio of CnBRP register CnBRP register set value 83.3 8 83.3 AFCAN Controller Representative examples of baud rate settings (fCANMOD = 16 MHz) (2/2) CnBTR register setting value Valid bit rate setting (unit: kbps) Length of DBT SYNC SEGMENT PROP SEGMENT TSEG1 [3:0] TSEG2 [2:0] 00000111 24 1 7 8 8 1110 111 66.7 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 Caution PHASE PHASE SEGMENT1 SEGMENT2 Sampling point unit: (%) The values in <~Reference>Table 18-5 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. User's Manual U16580EE3V1UD00 839 Chapter 18 AFCAN Controller 18.16 Operation of CAN Controller The processing procedure for showing in this chapter is recommended processing procedure to operate CAN controller. Develop the program referring to recommended processing procedure in this chapter. Figure 18-35: Initialization START Set CnGMCS register. Set CnGMCTRL register (set GOM bit = 1) Set CnBRP register, CnBTR register. Set CnIE register. Set CnMASK register. Initialize message buffers. Set CnCTRL register (set OPMODE bit). END Note: OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-shot mode, self-test mode 840 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller Figure 18-36: Re-initialization START Clear OPMODE No INIT mode? Yes Set CnBRP register, CnBTR register Set CnIE register Set CnMASK register Initialize message buffers CnERC and CnINFO register clear? No Yes Set CCERC bit Set CnCTRL register (Set OPMODE) END Caution After setting the CAN module to the initialization mode, avoid setting the module to another operation mode immediately after. If it is necessary to immediately set the module to another operation mode, be sure to access registers other than the CnCTRL and CnGMCTRL registers (e.g., set a message buffer). Note: OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-shot mode, self-test mode User's Manual U16580EE3V1UD00 841 Chapter 18 Figure 18-37: AFCAN Controller Message buffer initialization START No RDY = 1? Yes Clear RDY bit RDY = 0? No Yes Set CnMCONFm register Set CnMIDHm register, CnMIDLm register Transmit message buffer? No Yes Set CnMDLCm register Clear CnMDATAm register Set CnMCTRLm register Set RDY bit END Caution 1. Before a message buffer is initialized, the RDY bit must be cleared. 2. Make the following settings for message buffers not used by the application. * Clear the RDY, TRQ, and DN bits of the CnMCTRLm register to 0. * Clear the MA0 bit of the CnMCONFm register to 0. <~Reference>Figure 18-38 shows the processing for a receive message buffer (MT[2:0] bits of CnMCONFm register = 001B to 101B). 842 User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-38: AFCAN Controller Message buffer redefinition START Clear VALID bit No RDY = 1? Yes Clear RDY bit RDY = 0? No Yes RSTAT = 0 or VALID = 1?Note1 No Yes Wait for 4 CAN data bitsNote2 Set message buffers Set RDY bit END Notes: 1. Confirm that a message is being received because RDY bit must be set after a message is completely received. 2. Avoid message buffer redefinition during store operation of message reception by waiting additional 4 CAN data bits. <~Reference>Figure 18-39 shows the processing for a transmit message buffer during transmission (MT[2:0] bits of CnMCONFm register = 000B). User's Manual U16580EE3V1UD00 843 Chapter 18 AFCAN Controller Figure 18-39: Message Buffer Redefinition during Transmission <~Reference>Figure 18-39 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B). START Transmit abort process Clear RDY bit RDY = 0? No Yes Data frame Data frame or remote frame? Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Remote frame Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set RDY bit Transmit? Yes Wait for 1CAN data bits Set TRQ bit END 844 User's Manual U16580EE3V1UD00 No Chapter 18 AFCAN Controller Figure 18-40: Message transmit processing <~Reference>Figure 18-40 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B) START TRQ = 0? No Yes Clear RDY bit RDY = 0? No Yes Data frame Data frame or remote frame? Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Remote frame Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set RDY bit Set TRQ bit END Cautions: 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. User's Manual U16580EE3V1UD00 845 Chapter 18 Figure 18-41: AFCAN Controller ABT Message transmit processing <~Reference>Figure 18-41 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B) START ABTTRG = 0? No Yes Clear RDY bit RDY = 0? No Yes Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set RDY bit Set all ABT transmit messages? No Yes TSTAT = 0? No Yes Set ABTTRG bit END Note: This processing (normal operation mode with ABT) can only be applied to message buffers 0 to 7. For message buffers other than the ABT message buffers, see <~Reference>Figure 18-40 on page 845. Caution 846 The ABTTRG bit should be set to 1 after the TSTAT bit is cleared to 0. Checking the TSTAT bit and setting the ABTTRG bit to 1 must be processed consecutively. User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-42: AFCAN Controller Transmission via interrupt (using CnLOPT register) START Transmit completion interrupt processing Read CnLOPT register Clear RDY bit RDY = 0? No Yes Data frame Data frame or remote frame? Set CnMDATAxm register Set CnMDLCm register, Clear RTR bit of CnMCONFm register. Set CnMIDLm and CnMIDHm registers Remote frame Set CnMDLCm register Set RTR bit of CnMCONFm register. Set CnMIDLm and CnMIDHm registers Set RDY bit Set TRQ bit END Cautions: 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. Remark: Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. It is recommended to cancel any sleep mode requests, before processing TX interrupts. User's Manual U16580EE3V1UD00 847 Chapter 18 Figure 18-43: AFCAN Controller Transmission via interrupt (using CnTGPT register) START Transmit completion interrupt processing Read CnTGPT register TOVF = 1? No Yes Clear TOVF bit Clear RDY bit No RDY = 0? Yes Data frame Remote frame Data frame or remote frame? Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set RDY bit Set TRQ bit THPM = 1? No Yes END Cautions: 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. Remarks: 1. Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. It is recommended to cancel any sleep mode requests, before processing TX interrupts. 2. If TOVF was set once, the transmit history list is inconsistent. Consider to scan all configured transmit buffers for completed transmissions. 848 User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-44: AFCAN Controller Transmission via software polling START No CINTS0 = 1? Yes Clear CINTS0 bit Read CnTGPT register No TOVF = 1? Yes Clear TOVF bit Clear RDY bit No RDY = 0? Yes Data frame Data frame or remote frame? Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register. Set CnMIDLm and CnMIDHm registers Remote frame Set CnMDLCm register Set RTR bit of CnMCONFm Set CnMIDLm and CnMIDHm registers Set RDY bit Set TRQ bit THPM = 1? No Yes END Cautions: 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. Remarks: 1. Also check the MBON flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. 2. If TOVF was set once, the transmit history list is inconsistent. Consider to scan all configured transmit buffers for completed transmissions. User's Manual U16580EE3V1UD00 849 Chapter 18 Figure 18-45: AFCAN Controller Transmission abort processing (Except Normal Operation Mode with ABT) START Clear TRQ bit Wait for 11 CAN data bitsNote TSTAT = 0? No Yes Read CnLOPT register Message buffer to be aborted matches CnLOPT register? Yes Transmission successful No Transmit abort request was successful END Note: There is a possibility of starting the transmission without being aborted even if TRQ bit is cleared, because the transmission request to protocol layer might already been accepted between 11 bits, total of interframe space (3 bits) and suspend transmission (8 bits). Cautions: 1. Clear the TRQ bit for aborting transmission request, not the RDY bit. 2. Before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. The TSTAT bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. Do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress. Figure 18-46: 850 Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller START Clear ABTTRG bit ABTTRG = 0? No Yes Clear TRQ bit Wait for 11 CAN data bits TSTAT = 0? No Yes Read CnLOPT register Message buffer to be aborted matches CnLOPT register? Yes Transmission successful No Transmit abort request was successful END Cautions: 1. Clear the TRQ bit for aborting transmission request, not the RDY bit. 2. Before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. The TSTAT bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. Do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress. User's Manual U16580EE3V1UD00 851 Chapter 18 AFCAN Controller <~Reference>Figure 18-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 18-47: Transmission abort processing (normal operation mode with ABT) START TSTAT = 0? No Yes Clear ABTTRG bit ABTTRG = 0? No Yes Clear TRQ bit of message buffer whose transmission was aborted Transmit abort Transmission start No Yes Set ABTCLR bit END Cautions: 1. Do not set any transmission requests while ABT transmission abort processing is in progress. 2. Make a CAN sleep mode/CAN stop mode transition request after the ABTTRG bit is cleared (after ABT mode is aborted) following the procedure shown in <~Reference>Figure 18-47 or <~Reference>Figure 18-48. When clearing a transmission request in an area other than the ABT area, follow the procedure shown in <~Reference>Figure 18-45 on page 850. 852 User's Manual U16580EE3V1UD00 Chapter 18 AFCAN Controller <~Reference>Figure 18-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 18-48: Transmission request abort processing (normal operation mode with ABT) START Clear TRQ bit of message buffer undergoing transmission Clear ABTTRG bit ABTTRG = 0? No Yes Transmit abort Transmission start pointer clear? No Yes Set ABTCLR bit END Cautions: 1. Do not set any transmission requests while ABT transmission abort processing is in progress. 2. Make a CAN sleep mode/CAN stop mode request after the ABTTRG bit is cleared (after ABT mode is stopped) following the procedure shown in <~Reference>Figure 18-47 or <~Reference>Figure 18-48. When clearing a transmission request in an area other than the ABT area, follow the procedure shown in <~Reference>Figure 18-45 on page 850. User's Manual U16580EE3V1UD00 853 Chapter 18 Figure 18-49: AFCAN Controller Reception via interrupt (using CnLIPT register) START Generation of receive completion interrupt Read CnLIPT register Clear DN bit Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm registers DN = 0 AND MUC = 0 Note No Yes END Note: Check the MUC and DN bits using one read access. Remark: 854 Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. It is recommended to cancel any sleep mode requests, before processing RX interrupts. User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-50: AFCAN Controller Reception via interrupt (using CnRGPT register) START Generation of receive completion interrupt Read CnRGPT register ROVF = 1? No Yes Clear ROVF bit Yes RHPM = 1? No Clear DN bit Read CnMDATAxm, CnMDLCm, CnMIDLm, CnMIDHm registers DN = 0 AND MUC = 0Note No Yes Correct data is read Illegal data is read END Note: Check the MUC and DN bits using one read access. Remarks: 1. Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. It is recommended to cancel any sleep mode requests, before processing RX interrupts. 2. If ROVF was set once, the receive history list is inconsistent. Consider to scan all configured receive buffers for receptions. User's Manual U16580EE3V1UD00 855 Chapter 18 Figure 18-51: AFCAN Controller Reception via software polling START CINTS1 = 1? No Yes Clear CINTS1 bit Read CnRGPT register ROVF = 1? No Yes Clear ROVF bit Yes RHPM = 1? No Clear DN bit Read CnMDATAxm, CnMDLCm, CnMIDLm, CnMIDHm registers DN = 0 AND MUC = 0Note No Yes Correct data is read Illegal data is read END Note: Check the MUC and DN bits using one read access. Remarks: 1. Also check the MBON flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. 2. If ROVF was set once, the receive history list is inconsistent. Consider to scan all configured receive buffers for receptions. 856 User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-52: AFCAN Controller Setting CAN sleep mode/stop mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit PSMODE0 = 1? No Yes CAN sleep mode Set PSMODE1 bit PSMODE1 = 1? No Yes Request CAN sleep mode again? Yes CAN stop mode No END Clear OPMODE No INIT mode? Yes Access to registers other than the CnCTRL and CnGMCTRL registers Set CnCTRL register (Set OPMODE) Clear CINTS5 bit Caution: To abort transmission before making a request for the CAN sleep mode, perform processing according to <~Reference>Figure 18-45 on page 850 and <~Reference>Figure 18-47 on page 852. User's Manual U16580EE3V1UD00 857 Chapter 18 Figure 18-53: AFCAN Controller Clear CAN sleep/stop mode START CAN stop mode Clear PSMODE1 bit CAN sleep mode Releasing CAN sleep mode by CAN bus activity Releasing CAN sleep mode by user Dominant edge on CAN detected Clear PSMODE0 bit Clear PSMODE0 bit Clear CINTS5 bit END 858 User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-54: AFCAN Controller Bus-Off recovery (Except Normal Operation Mode with ABT) START No BOFF = 1? Yes Clear all TRQ bits Note Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? No Yes Set CCERC bit Set CnCTRL register (Set OPMODE) Set CnCTRL register (Set OPMODE) Wait for recovery from bus off END Note: Clear all TRQ bits when re-initialization of message buffer is executed by clearing RDY bit before bus-off recovery sequence is started. Caution: When the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. Therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. Remark: OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-shot mode, self-test mode User's Manual U16580EE3V1UD00 859 Chapter 18 Figure 18-55: AFCAN Controller Bus-Off recovery (Normal Operation Mode with ABT) START No BOFF = 1? Yes Clear ABTTRG bit Clear all TRQ bits Note Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? No Yes Set CCERC bit Set CnCTRL register (Set OPMODE) Set CnCTRL register (Set OPMODE) Wait for recovery from bus off END Note: Clear all TRQ bits when re-initialization of message buffer is executed by clearing RDY bit before bus-off recovery sequence is started. Caution: When the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. Therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. Remark: OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-shot mode, self-test mode 860 User's Manual U16580EE3V1UD00 Chapter 18 Figure 18-56: AFCAN Controller Normal shutdown process START INIT mode Clear GOM bit GOM = 0? No Yes Shutdown successful GOM = 0, EFSD = 0 END Figure 18-57: Forced shutdown process START Set EFSD bit Must be a subsequent write Clear GOM bit No GOM = 0? Yes Shutdown successful GOM = 0, EFSD = 0 END Caution: Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit. User's Manual U16580EE3V1UD00 861 Chapter 18 AFCAN Controller Figure 18-58: Error handling START Error interrupt CINTS2 = 1? No Yes Check CAN module state (read CnINFO register) Clear CINTS2 bit No CINTS3 = 1? Yes Check CAN protocol error state (read CnLEC register) Clear CINTS3 bit CINTS4 = 1? Yes Clear CINTS4 bit END 862 User's Manual U16580EE3V1UD00 No Chapter 18 Figure 18-59: AFCAN Controller Setting CPU stand-by (from CAN sleep mode) STAR T Set PSMODE0 bit. PSMODE0 bit = 1? No Clear CINT S5 bit. Yes CANsleep mode Yes No CINTS5 bit = 1? MBON bit = 0? No Yes Set CPU standby mode. END Caution: Before the CPU is set in the CPU standby mode, please check if the CAN sleep mode has been reached. However, after check of the CAN sleep mode, until the CPU is set in the CPU standby mode, the CAN sleep mode may be cancelled by wakeup from CAN bus. User's Manual U16580EE3V1UD00 863 Chapter 18 Figure 18-60: AFCAN Controller Setting CPU stand-by (from CAN stop mode) STAR T Set PSMODE0 bit. PSMODE0 bit = 1? Clear CINT S5 bit. (Note) No Yes CANsleep mode Set PSMODE1 bit. No PSMODE1 bit = 1? Yes CANstop mode No MBON bit = 0? Yes Set CPU standby mode. END Note: During wakeup interrupts Caution: 864 The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bit of the CnCTRL register and not by a change in the CAN bus state. User's Manual U16580EE3V1UD00 Chapter 19 Random Number Generator (PD70F3187 only) PD70F3187 incorporates a hardware random number generator (RNG). The random number generator is not supported on PD70F3447. 19.1 Features * Random number sequence passing FIPS and Maurer test * Random number format: 16 bits * Seed generated by hardware 19.2 Configuration (1) Random number register (RNG) The RNG register is a 16-bit register that holds the random number. After read access to this register a certain time is required to generate the next random number. If a consecutive read access takes place before the new random number has been generated, the read access will be delayed. The RNG register is read-only, in 16-bit units. Reset input causes an undefined register content. Figure 19-1: After reset: 15 undefined 14 13 Random Number Register (RNG) R 12 11 Address: 10 9 8 FFFFF700H 7 6 5 4 3 2 1 0 RNG User's Manual U16580EE3V1UD00 865 Chapter 19 Random Number Generator (PD70F3187 only) 19.3 Operation 19.3.1 Access timing After read access to the RNG register it needs a certain time to generate the next random number. Moreover, when a consecutive read access takes place before the new random number has been generated, the read access will be delayed. The access timing to the RNG register is as follows. Single read access to RNG register (when VSWC register = 13H): T single = 102,5 f XX -1 Consecutive read access to RNG register: -1 T consecutive = T single + ( 1024 f XX ) 866 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.1 Features * Input-only ports: I/O ports: 5 136 * Input/Output direction can be specified in 1.bit units * Noise removal circuit provided for external interrupts and timer inputs * Edge detect function for external interrupts (rising-, falling-, both edges) * Security features for port 5 and 6 shared as 3-phase PWM timer outputs - Emergency shut off feature - Software protection feature User's Manual U16580EE3V1UD00 867 Chapter 20 Port Functions 20.2 Port Configuration The V850E/PH2 incorporates a total of 141 input/output ports (including 5 input-only ports) labelled port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, AL, AH, DH, DL, CS, CM, CT, and CD. The port configuration is shown in Figure 20-1 below. Figure 20-1: Port Configuration P00 Port 0 P04 P100 P102 Port 10 P10 Port 1 P17 PAL0 PAL15 Port AL P20 Port 2 P27 PAH0 Port AH PAH5 P30 Port 3 P37 PDL0 Port DL PDL15 P40 Port 4 P45 PDH0 Port DH PDH15 P50 Port 5 P57 P60 PCS0 PCS1 PCS3 PCS4 Port CS PCM0 PCM1 PCM6 PCM7 Port CM PCT4 PCT5 Port CT Port 6 P67 P70 Port 7 P75 P80 Port 8 P86 PCD2 Port CD P90 PCD5 Port 9 P96 868 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.2.1 Function of each port The port functions of V850E/PH2 are shown in the table below. The port type can vary for each individual bit of a port. In addition to their port functions, these pins are also shared with on-chip peripheral I/O pins in control mode. For the port types of each port, refer to Table 20-1 below. Table 20-1: Port Name Pin Name Port Type and Function Overview Port Function Function in Control Mode Port Type Port 0 P00 to P04 5-bit input only External interrupt input External A/D conversion start trigger input Emergency shut-off input 3, 15, 15A Port 1 P10 to P17 8-bit I/O port Timer I/O (TMP0, TMP1, TMP2, TMP3) 6 Port 2 P20 to P27 8-bit I/O port Timer I/O (TMP4, TMP5, TMP6, TMP7) 6 Port 3 P30 to P37 8-bit I/O port Serial interface I/O (UARTC0, UARTC1, AFCAN0, AFCAN1Note) 1S, 2, 9 Port 4 P40 to P45 6-bit I/O port Serial interface I/O (CSIB0, CSIB1Note) 1E, 2, 4C Port 5 P50 to P57 8-bit I/O port Timer output (TMR0) 11, 13 Port 6 P60 to P67 8-bit I/O port Timer I/O (TMR1) 12, 13, 14 Port 7 P70 to P75 6-bit I/O port Timer I/O (TMT0, TMT1) 6, 8 Port 8 P80 to P86 7-bit I/O port Serial interface I/O (CSI30) 1S, 2, 4, 5, 7 Port 9 P90 to P96 7-bit I/O port Serial interface I/O (CSI31Note) 1S, 2, 4, 5, 7 Port 10 P100 to P102 3-bit I/O port Timer I/O (TENC1Note, TMP8, TMR0, TMR1) 6, 10 Port AL PAL0 to PAL15 16-bit I/O port External address bus (A0-A15)Note 1 Port AH PAH0 to PAH5 6-bit I/O port External address bus (A16-A21)Note 1 Port DL PDL0 to PDL15 16-bit /IO port External data bus (D0-D15)Note 4C Port DH PDH0 to PDH15 16-bit I/O port External data bus (D16-D31)Note 4C Port CS PCS0, PCS1, PCS3, PCS4 4-bit I/O port External bus interface control signal output (CS0, CS1, CS3, CS4)Note 1 Port CM PCM0, PCM1, PCM6, PCM7 4-bit I/O port External bus interface control signal I/O (WAIT)Note 1, 2C Port CT PCT4, PCT5 2-bit I/O port External bus interface control signal output (RD, WR)Note 1 Port CD PCD2 to PCD5 4-bit I/O port External bus interface control signal output (BEN0-BEN3)Note 1 Note: Alternate control function not available on PD70F3447. User's Manual U16580EE3V1UD00 869 Chapter 20 Port Functions 20.2.2 Port types (1) Port type 1 Port type 1 provides a general purpose I/O port with peripheral output function. Figure 20-2: Port Type 1 WRPMC PMCmn WRPM Peripheral output function Selector Pmn RDIN Remark: 870 Pmn Selector WRPORT Selector NPB PMmn Address m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 (2) Port Functions Port type 1S Port type 1S provides a general purpose I/O port with peripheral output function. This type is similar to port type 1, but features a Schmitt trigger input buffer characteristic. Figure 20-3: Port Type 1S WRPMC PMCnm WRPM Peripheral output function Selector Pnm RDIN Remark: Pmn Selector WRPORT Selector NPB PMnm Address m: port number n: port bit number User's Manual U16580EE3V1UD00 871 Chapter 20 (3) Port Functions Port type 1E Port type 1E provides a general purpose I/O port with peripheral output function. In peripheral function mode a control signal is provided to enable or disable the output. Figure 20-4: Port Type 1E Peripheral output function enable WRPMC 1 = enabled 0 = Hi-Z Selector PMCmn WRPM Peripheral output function Selector Pmn RDIN Remark: 872 Pmn Selector WRPORT Selector NPB PMmn Address m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 (4) Port Functions Port type 2 Port type 2 provides a general purpose I/O port with peripheral input function. Figure 20-5: Port Type 2 WRPMC PMCmn WRPM NPB PMmn WRPORT Pmn Selector Selector Pmn Address RDIN Peripheral input function Remark: m: port number n: port bit number User's Manual U16580EE3V1UD00 873 Chapter 20 (5) Port Functions Port type 2A Port type 2A provides a general purpose I/O port with peripheral input function. This type is similar as port type 2, but in port mode the peripheral input function is forced to high level. Figure 20-6: Port Type 2A WRPMC PMCmn WRPM NPB PMmn WRPORT Pmn Selector Selector Pmn Address RDIN Peripheral input function Remark: 874 m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 (6) Port Functions Port type 2C Port type 2C provides a general purpose I/O port with peripheral input function. This type is similar to type 2, but features CMOS input buffer characteristic. Figure 20-7: Port Type 2C WRPMC PMCmn WRPM NPB PMmn WRPORT Pmn Selector Selector Pmn Address RDIN Peripheral input function Remark: m: port number n: port bit number User's Manual U16580EE3V1UD00 875 Chapter 20 (7) Port Functions Port type 3 Port type 3 provides a general purpose input port with NMI interrupt input function. Figure 20-8: Port Type 3 P00 RDIN Edge detection NPB NMI Filter WRINTM ESN0 Selector ESN1 RDINTM Address 876 User's Manual U16580EE3V1UD00 Chapter 20 (8) Port Functions Port type 4 Port type 4 provides a general purpose I/O port with peripheral I/O function. Peripheral output enable is controlled by the corresponding peripheral function. Figure 20-9: Port Type 4 Peripheral function output control WRPMC PMCmn WRPM Peripheral output function Selector Pmn Pmn Selector WRPORT Selector NPB PMmn Address RDIN Peripheral input function Remark: m: port number n: port bit number User's Manual U16580EE3V1UD00 877 Chapter 20 (9) Port Functions Port type 4C Port type 4 provides a general purpose I/O port with peripheral I/O function. Peripheral output enable is controlled by the corresponding peripheral function. Figure 20-10: Port Type 4C Peripheral function output control WRPMC PMCmn WRPM Peripheral output function Selector Pmn Pmn Selector WRPORT Selector NPB PMmn Address RDIN Peripheral input function Remark: 878 m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (10) Port type 5 Port type 5 provides a general purpose I/O port with peripheral I/O function. If the peripheral input function is disabled, the value of the peripheral input signal is fixed to low level. Figure 20-11: Port Type 5 WRPMC PMCmn WRPM Peripheral output function Selector Pmn Pmn Selector WRPORT Selector NPB PMmn Address RDIN Peripheral input function Remark: m: port number n: port bit number User's Manual U16580EE3V1UD00 879 Chapter 20 Port Functions (11) Port type 6 Port type 6 provides a general purpose I/O port with peripheral output function and digitally filtered peripheral input function. Figure 20-12: Port Type 6 WRPMC PMCmn WRPM Peripheral output function Selector Pmn Pmn Selector WRPORT Selector NPB PMmn Address RDIN Peripheral input function Filter CLK Remark: 880 m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (12) Port type 7 Port type 7 provides a general purpose I/O port with peripheral output function and external interrupt input capability. Figure 20-13: Port Type 7 WRPMC PMCmn WRPM PMmn Selector Peripheral output function NPB Selector Pmn RDIN Pmn Selector WRPORT Address Edge detection INTx Filter WRINTM ESx0 Selector ESx1 RDINTM Address Remark: m: port number n: port bit number x: external interrupt number User's Manual U16580EE3V1UD00 881 Chapter 20 Port Functions (13) Port type 8 Port type 8 provides a general purpose I/O port with digitally filtered peripheral input function and external interrupt input capability. Figure 20-14: Port Type 8 WRPMC PMCmn WRPM PMmn WRPORT Pmn NPB RDIN Selector Selector Pmn Address Peripheral input function Filter Edge detection INTx CLK WRINTM ESx0 Selector ESx1 RDINTM Address Remark: 882 m: port number n: port bit number x: external interrupt number User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (14) Port type 9 Port type 9 provides a general purpose I/O port with peripheral input function and external interrupt input capability. This type is similar to the port type 8, but input noise filter is bypassed for peripheral input function. Remark: The peripheral input signal provided by port type 9 is fixed to high level, if peripheral input function is disabled. Figure 20-15: Port Type 9 WRPMC PMCmn WRPM PMmn WRPORT Pmn NPB RDIN Selector Selector Pmn Address Peripheral input function Edge detection INTx Filter WRINTM ESx0 Selector ESx1 RDINTM Address Remark: m: port number n: port bit number x: external interrupt number User's Manual U16580EE3V1UD00 883 Chapter 20 Port Functions (15) Port type 10 Port type10 provides a general purpose I/O port with digitally filtered peripheral input function. Figure 20-16: Port Type 10 WRPMC PMCmn WRPM NPB PMmn WRPORT Pmn RDIN Peripheral input function Selector Selector Pmn Address Filter CLK Remark: 884 m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (16) Port type 11 Port type 11 provides a general purpose I/O port with peripheral output function. This type is similar to the port type 6, but all port registers are write protected against unintended change due to system or software malfunction. Writing to the port registers of type 11 is only possible immediately after a write access to the PRCMD register. Figure 20-17: Port Type 11 PRCMD WRPMC PMCmn WRPM Selector Pmn RDIN Remark: Pmn Selector Peripheral output function WRPORT Selector NPB PMmn Address m: port number n: port bit number User's Manual U16580EE3V1UD00 885 Chapter 20 Port Functions (17) Port type 12 Port type 12 provides a general purpose I/O port with digitally filtered peripheral input function and peripheral output function. This type is similar to the port logic type 1S, but all port registers are write protected against unintended change due to system or software malfunction. Writing to the port registers of type 12 is only possible immediately after a write access to the PRCMD register. Figure 20-18: Port Type 12 PRCMD WRPMC PMCmn WRPM Selector Pmn Pmn Selector Peripheral output function WRPORT Selector NPB PMmn Address RDIN Peripheral input function Filter CLK Remark: 886 m: port number n: port bit number User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (18) Port type 13 Port type 13 provides a general purpose I/O port with peripheral output function. This type is similar to the port logic type 11, but the output driver can be shut down immediately by the ESOx input signal (x = 0, 1). All port registers are write protected against unintended change due to system or software malfunction. Writing to the port registers of type 13 is only possible immediately after a write access to the PRCMD register. User's Manual U16580EE3V1UD00 887 Chapter 20 Port Functions Figure 20-19: Port Type 13 Analog filter ESOx "1"set request by active edge (pulse width 10ns) "1"set request by active level analog delay 10 ns PRCMD WRPESCn ESOxED0 ESOxED1 ESOxEN WRESOSTn NPB ESOxST WRPMC PMCmn WRPM Peripheral output function Selector Pmn Address RDIN Remark: 888 Pmn Selector WRPORT Selector PMmn m: port number n: port bit number x: index of ESO signal (x = 0, 1) User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (19) Port type 14 Port type 14 provides a general purpose I/O port with digitally filtered peripheral input function and peripheral output function. This type is similar to the port type 12, but the output driver can be shut down immediately by the ESOx input signal (x = 0, 1). All port registers are write protected against unintended change due to system or software malfunction. Writing to the port registers of type 13 is only possible immediately after a write access to the PRCMD register. User's Manual U16580EE3V1UD00 889 Chapter 20 Port Functions Figure 20-20: Port Type 14 Analog filter ESOx "1"set request by active edge (pulse width 10ns) "1"set request by active level analog delay 10 ns PRCMD WRPESCn ESOxED0 ESOxED1 ESOxEN WRESOSTn B NP ESOxST PRCMD WRPMC PMCmn WRPM Selector Pmn Pmn Selector Peripheral output function WRPORT Selector PMmn Address RDIN Peripheral input function Filter CLK Remark: 890 m: port number n: port bit number x: index of ESO signal (x = 0, 1) User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (20) Port type 15 Port type 15 provides a general purpose input port with external interrupt input function. This type is similar as port type 3. Difference is the additional filtered peripheral input function support. Figure 20-21: Port Type 15 Pnm Peripheral input function RDIN Edge detection NPB INTx Filter WRINTM CLK ESx0 Selector ESx1 RDINTM Address Remark: m: port number n: port bit number x: external interrupt number User's Manual U16580EE3V1UD00 891 Chapter 20 Port Functions (21) Port type 15A Port type 15A provides a general purpose input port with external interrupt input function. This type is similar as port type 15. Difference is the analog filter instead of digital filter. Figure 20-22: Port Type 15A Pnm Peripheral input function RDIN Edge detection NPB INTx Analog filter WRINTM ESx0 Selector ESx1 RDINTM Address Remark: 892 m: port number n: port bit number x: external interrupt number User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.2.3 Peripheral registers of I/O ports The following table lists the peripheral registers related to I/O ports. Table 20-2: Address Peripheral Registers of I/O Ports (1/3) Function Register Name Symbol Bit Units for Manipulation 1 Bit 8 Bits 16 Bits After Reset 0xFFFFF000 Port register port AL low byte PALL R/W R/W - 0xFFFFF000 Port register port AL PAL - - R/W 0xFFFFF001 Port register port AL high byte PALH R/W R/W - 0x00 0xFFFFF002 Port register port AH PAH R/W R/W - 0x00 0xFFFFF004 Port register port DL low byte PDLL R/W R/W - 0x00 0xFFFFF004 Port register port DL PDL - - R/W 0xFFFFF005 Port register port DL high byte PDLH R/W R/W - 0x00 0xFFFFF006 Port register port DH low byte PDHL R/W R/W - 0x00 0xFFFFF006 Port register port DH PDH - - R/W 0xFFFFF007 Port register port DH high byte PDHH R/W R/W - 0x00 0xFFFFF008 Port register port CS PCS R/W R/W - 0x00 0xFFFFF00A Port register port CT PCT R/W R/W - 0x00 0xFFFFF00C Port register port CM PCM R/W R/W - 0x00 0xFFFFF00E Port register port CD PCD R/W R/W - 0x00 0xFFFFF020 Port mode register Port mode AL low byte PMALL R/W R/W - 0xFF 0xFFFFF020 Port mode register Port mode AL PMAL - - R/W 0xFFFFF021 Port mode register Port mode AL high byte PMALH R/W R/W - 0xFF 0xFFFFF022 Port mode register Port mode AH PMAH R/W R/W - 0xFF 0xFFFFF024 Port mode register Port mode DL low byte PMDLL R/W R/W - 0xFF 0xFFFFF024 Port mode register Port mode DL PMDL - - R/W 0xFFFFF025 Port mode register Port mode DL high byte PMDLH R/W R/W - 0xFF 0xFFFFF026 Port mode register Port mode DH low byte PMDHL R/W R/W - 0xFF 0xFFFFF026 Port mode register Port mode DH - - R/W 0xFFFFF027 Port mode register Port mode DH high byte PMDHH R/W R/W - 0xFF 0xFFFFF028 Port mode register Port mode CS PMCS R/W R/W - 0xFF 0xFFFFF02A Port mode register Port mode CT PMCT R/W R/W - 0xFF 0xFFFFF02C Port mode register Port mode CM PMCM R/W R/W - 0xFF 0xFFFFF02E Port mode register Port mode CD PMCD R/W R/W - 0xFF 0xFFFFF040 Port mode control register Port mode control AL low byte PMCALL R/W R/W - 0x00 0xFFFFF040 Port mode control register Port mode control AL PMCAL - - R/W 0xFFFFF041 Port mode control register Port mode control AL high byte PMCALH R/W R/W - 0x00 0xFFFFF042 Port mode control register Port mode control AH PMCAH R/W R/W - 0x00 0xFFFFF044 Port mode control register Port mode control DL low byte PMCDLL R/W R/W - 0x00 PMDH User's Manual U16580EE3V1UD00 0x00 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0x0000 893 Chapter 20 Table 20-2: Address Port Functions Peripheral Registers of I/O Ports (2/3) Function Register Name Symbol Bit Units for Manipulation 1 Bit 8 Bits 16 Bits - - R/W After Reset 0xFFFFF044 Port mode control register Port mode control DL PMCDL 0xFFFFF045 Port mode control register Port mode control DL high byte PMCDLH R/W R/W - 0x00 0xFFFFF046 Port mode control register Port mode control DH low byte PMCDHL R/W R/W - 0x00 0xFFFFF046 Port mode control register Port mode control DH PMCDH - - R/W 0xFFFFF047 Port mode control register Port mode control DH high byte PMCDHH R/W R/W - 0x00 0xFFFFF048 Port mode control register Port mode control CS PMCCS R/W R/W - 0x00 0xFFFFF04A Port mode control register Port mode control CT PMCCT R/W R/W - 0x00 0xFFFFF04C Port mode control register Port mode control CM PMCCM R/W R/W - 0x00 0xFFFFF04E Port mode control register Port mode control CD PMCCD R/W R/W - 0x00 0xFFFFF400 Port register port 0 P0 R R - undef. 0xFFFFF402 Port register port 1 P1 R/W R/W - undef. 0xFFFFF404 Port register port 2 P2 R/W R/W - undef. 0xFFFFF406 Port register port 3 P3 R/W R/W - undef. 0xFFFFF408 Port register port 4 P4 R/W R/W - undef. 0xFFFFF40A Port register port 5 P5 R/W R/W - undef. 0xFFFFF40C Port register port 6 P6 R/W R/W - undef. 0xFFFFF40E Port register port 7 P7 R/W R/W - undef. 0xFFFFF410 Port register port 8 P8 R/W R/W - undef. 0xFFFFF412 Port register port 9 P9 R/W R/W - undef. 0xFFFFF414 Port register port 10 P10 R/W R/W - undef. 0xFFFFF422 Port mode register port 1 PM1 R/W R/W - 0xFF 0xFFFFF424 Port mode register port 2 PM2 R/W R/W - 0xFF 0xFFFFF426 Port mode register port 3 PM3 R/W R/W - 0xFF 0xFFFFF428 Port mode register port 4 PM4 R/W R/W - FFH 0xFFFFF42A Port mode register port 5 PM5 R/W R/W - 0xFF 0xFFFFF42C Port mode register port 6 PM6 R/W R/W - 0xFF 0xFFFFF42E Port mode register port 7 PM7 R/W R/W - FFH 0xFFFFF430 Port mode register port 8 PM8 R/W R/W - 0xFF 0xFFFFF432 Port mode register port 9 PM9 R/W R/W - FFH 0xFFFFF434 Port mode register port 10 PM10 R/W R/W - FFH 0xFFFFF442 Port mode control register port 1 PMC1 R/W R/W - 0x00 0xFFFFF444 Port mode control register port 2 PMC2 R/W R/W - 0x00 0xFFFFF446 Port mode control register port 3 PMC3 R/W R/W - 0x00 0xFFFFF448 Port mode control register port 4 PMC4 R/W R/W - 0x00 894 User's Manual U16580EE3V1UD00 0x0000 0x0000 Chapter 20 Table 20-2: Address Port Functions Peripheral Registers of I/O Ports (3/3) Function Register Name Symbol Bit Units for Manipulation 1 Bit 8 Bits 16 Bits After Reset 0xFFFFF44A Port mode control register port 5 PMC5 R/W R/W - 0x00 0xFFFFF44C Port mode control register port 6 PMC6 R/W R/W - 0x00 0xFFFFF44E Port mode control register port 7 PMC7 R/W R/W - 0x00 0xFFFFF450 Port mode control register port 8 PMC8 R/W R/W - 0x00 0xFFFFF452 Port mode control register port 9 PMC9 R/W R/W - 0x00 0xFFFFF454 Port mode control register port 10 PMC10 R/W R/W - 0x00 User's Manual U16580EE3V1UD00 895 Chapter 20 Port Functions 20.2.4 Peripheral registers of valid edge control The following table lists the peripheral registers related to valid edge control. Table 20-3: Address Peripheral Registers of Valid Edge Control Function Register Name Symbol Bit Units for Manipulation 1 Bit 8 Bits 16 Bits After Reset 0xFFFFF880 Interrupt mode register 0 INTM0 R/W R/W - 0x00 0xFFFFF882 Interrupt mode register 1 INTM1 R/W R/W - 0x00 0xFFFFF884 Interrupt mode register 2 INTM2 R/W R/W - 0x00 0xFFFFF886 Interrupt mode register 3 INTM3 R/W R/W - 0x00 0xFFFFF888 Port 5 emergency shut off control register PESC5 R/W R/W - 0x00 0xFFFFF88A Port 5 emergency shut off control register ESOST5 R/W R/W - 0x00 0xFFFFF88C Port 6 emergency shut off status register PESC6 R/W R/W - 0x00 0xFFFFF88E Port 6 emergency shut off status register ESOST6 R/W R/W - 0x00 896 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3 Port Pin Functions 20.3.1 Port 0 Port 0 is a 5-bit input only port. (1) Functions * Input data can be read in 1-bit units by using the port register 0 (P0). * The alternate functions shared with the input port functionality of port 0 are always enabled. Table 20-4: Port Port 0 (2) Alternate Function Pins and Port Types of Port 0 Alternate Function Remark Port Type P00 NMI Non maskable interrupt 3 P01 INTP0, ESO0 External interrupt request input, Emergency output shut off input (TMR0) P02 INTP1, ESO1 External interrupt request input, Emergency output shut off input (TMR1) P03 INTP2, ADTRG0 External interrupt request input, External A/D conversion start trigger (ADC0) P04 INTP3, ADTRG1 External interrupt request input, External A/D conversion start trigger (ADC1) 15A 15 Control registers (a) Port register 0 (P0) The port register 0 (P0) is an 8-bit register that reflects the input levels of port pins P00 to P04. This register is read-only in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-23: After reset: P0 Undefined R Address: FFFFF400H 7 6 5 4 3 2 1 0 0 0 0 P04 P03 P02 P01 P00 P0n Remark: Port Register 0 (P0) Input Data Control of Pin P0n 0 Low level is input 1 High level is input n = 0 to 4 User's Manual U16580EE3V1UD00 897 Chapter 20 Port Functions 20.3.2 Port 1 Port 1 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 1 (P1). * Input or output mode can be set in 1-bit units by using the port mode register 1 (PM1). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 1 (PMC1). Table 20-5: Port Port 1 898 Alternate Function Pins and Port Types of Port 1 Alternate Function Remark P10 TIP00, TEVTP1, TOP00 Timer input (TMP0/TMP1) Timer output (TMP0) P11 TIP01, TTRGP1, TOP01 Timer input (TMP0/TMP1) Timer output (TMP0) P12 TIP10, TTRGP0, TOP10 Timer input (TMP0/TMP1) Timer output (TMP1) P13 TIP11, TEVTP0, TOP11 Timer input (TMP0/TMP1) Timer output (TMP1) P14 TIP20, TEVTP3, TOP20 Timer input (TMP2/TMP3) Timer output (TMP2) P15 TIP21, TTRGP3, TOP21 Timer input (TMP2/TMP3) Timer output (TMP2) P16 TIP30, TTRGP2, TOP30 Timer input (TMP2/TMP3) Timer output (TMP3) P17 TIP31, TEVTP2, TOP31 Timer input (TMP2/TMP3) Timer output (TMP3) User's Manual U16580EE3V1UD00 Port Type 6 Chapter 20 (2) Port Functions Control registers (a) Port register 1 (P1) The P1 register 1 is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P10 to P17. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-24: After reset: P1 Undefined R/W Address: FFFFF402H 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 P1n Remark: Port Register 1 (P1) Input/Output Data Control of Pin P1n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0 to 7 (b) Port mode register 1 (PM1) The PM1 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-25: After reset: PM1 FFH R/W Address: FFFFF422H 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n Remark: Port Mode Register 1 (PM1) Input/Output Mode Control of Pin P1n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 7 User's Manual U16580EE3V1UD00 899 Chapter 20 Port Functions (c) Port mode control register 1 (PMC1) The PMC1 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-26: After reset: PMC1 00H Port Mode Control Register 1 (PMC1) (1/2) R/W FFFFF442H 7 6 5 4 3 2 1 0 PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 PMC17 Port/Control Mode Specification of Pin P17 0 I/O port mode 1 Control mode (alternate function) PM17 Function 0 TOP31 output mode 1 TIP31, TEVTP2 input mode PMC16 Port/Control Mode Specification of Pin P16 0 I/O port mode 1 Control mode (alternate function) PM16 Function 0 TOP30 output mode 1 TIP30, TTRGP2 input mode PMC15 Port/Control Mode Specification of Pin P15 0 I/O port mode 1 Control mode (alternate function) PM15 Function 0 TOP21 output mode 1 TIP21, TTRGP3 input mode PMC14 Port/Control Mode Specification of Pin P14 0 I/O port mode 1 Control mode (alternate function) PM14 900 Address: Function 0 TOP20 output mode 1 TIP20, TEVTP3 input mode User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-26: Port Functions Port Mode Control Register 1 (PMC1) (2/2) PMC13 Port/Control Mode Specification of Pin P13 0 I/O port mode 1 Control mode (alternate function) PM13 Function 0 TOP11 output mode 1 TIP11, TEVTP0 input mode PMC12 Port/Control Mode Specification of Pin P12 0 I/O port mode 1 Control mode (alternate function) PM12 Function 0 TOP10 output mode 1 TIP10, TTRGP0 input mode PMC11 Port/Control Mode Specification of Pin P11 0 I/O port mode 1 Control mode (alternate function) PM11 Function 0 TOP01 output mode 1 TIP01, TTRGP1 input mode PMC10 Port/Control Mode Specification of Pin P10 0 I/O port mode 1 Control mode (alternate function) PM10 Function 0 TOP00 output mode 1 TIP00, TEVTP1 input mode User's Manual U16580EE3V1UD00 901 Chapter 20 Port Functions 20.3.3 Port 2 Port 2 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 2 (P2). * Input or output mode can be set in 1-bit units by using the port mode register 2 (PM2). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 2 (PMC2). Table 20-6: Port Port 2 902 Alternate Function Pins and Port Types of Port 2 Alternate Function Remark P20 TIP40, TEVTP5, TOP40 Timer input (TMP4/TMP5) Timer output (TMP4 output) P21 TIP41, TTRGP5, TOP41 Timer input (TMP4/TMP5) Timer output (TMP4 output) P22 TIP50, TTRGP4, TOP50 Timer input (TMP4/TMP5) Timer output (TMP5 output) P23 TIP51, TEVTP4, TOP51 Timer input (TMP4/TMP5) Timer output (TMP5 output) P24 TIP60, TEVTP7, TOP60 Timer input (TMP6/TMP7) Timer output (TMP6 output) P25 TIP61, TTRGP7, TOP61 Timer input (TMP6/TMP7) Timer output (TMP6 output) P26 TIP70, TTRGP6, TOP70 Timer input (TMP6TMP7) Timer output (TMP7 output) P27 TIP71, TEVTP6, TOP71 Timer input (TMP6/TMP7) Timer output (TMP7 output) User's Manual U16580EE3V1UD00 Port Type 6 Chapter 20 (2) Port Functions Control registers (a) Port register 2 (P2) The P2 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P20 to P27. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-27: After reset: P2 Undefined R/W Address: FFFFF404H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 P2n Remark: Port Register 2 (P2) Input/Output Data Control of Pin P2n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0 to 7 (b) Port mode register 2 (PM2) The PM2 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-28: After reset: PM2 FFH R/W Address: FFFFF424H 7 6 5 4 3 2 1 0 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM2n Remark: Port Mode Register 2 (PM2) Input/Output Mode Control of Pin P2n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 7 PM2 is an 8 bit read/write register. It is the port mode register of Port 2. PM2 determines the input or output direction of the respective port pin. User's Manual U16580EE3V1UD00 903 Chapter 20 Port Functions (c) Port mode control register 2 (PMC2) The PMC2 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-29: After reset: PMC2 00H Port Mode Control Register 2 (PMC2) (1/2) R/W FFFFF444H 7 6 5 4 3 2 1 0 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 PMC27 Port/Control Mode Specification of Pin P27 0 I/O port mode 1 Control mode (alternate function) PM27 Function 0 TOP71 output mode 1 TIP71, TEVTP6 input mode PMC26 Port/Control Mode Specification of Pin P26 0 I/O port mode 1 Control mode (alternate function) PM26 Function 0 TOP70 output mode 1 TIP70, TTRGP6 input mode PMC25 Port/Control Mode Specification of Pin P25 0 I/O port mode 1 Control mode (alternate function) PM25 Function 0 TOP61 output mode 1 TIP61, TTRGP7 input mode PMC24 Port/Control Mode Specification of Pin P24 0 I/O port mode 1 Control mode (alternate function) PM24 904 Address: Function 0 TOP60 output mode 1 TIP60, TEVTP7 input mode User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-29: Port Functions Port Mode Control Register 1 (PMC2) (2/2) PMC23 Port/Control Mode Specification of Pin P23 0 I/O port mode 1 Control mode (alternate function) PM23 Function 0 TOP51 output mode 1 TIP51, TEVTP4 input mode PMC22 Port/Control Mode Specification of Pin P22 0 I/O port mode 1 Control mode (alternate function) PM22 Function 0 TOP50 output mode 1 TIP50, TTRGP4 input mode PMC21 Port/Control Mode Specification of Pin P21 0 I/O port mode 1 Control mode (alternate function) PM21 Function 0 TOP41 output mode 1 TIP41, TTRGP5 input mode PMC20 Port/Control Mode Specification of Pin P20 0 I/O port mode 1 Control mode (alternate function) PM20 Function 0 TOP40 output mode 1 TIP40, TEVTP5 input mode User's Manual U16580EE3V1UD00 905 Chapter 20 Port Functions 20.3.4 Port 3 Port 3 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 3 (P3). * Input or output mode can be set in 1-bit units by using the port mode register 3 (PM3). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 3 (PMC3). * The external interrupt request inputs shared with the input port functionality of port 3 are always enabled in input port mode. Table 20-7: Port Port 3 Alternate Function Pins and Port Types of Port 3 Alternate Function Remark P30 RXDC0, INTP4 Serial interface (UARTC0) input External interrupt request input P31 TXDC0 Serial interface (UARTC0) output P32 RXDC1, INTP5 Serial interface (UARTC1) input External interrupt request input P33 TXDC1 Serial interface (UARTC1) output 1S P34 FCRXD0 FCAN0 input 2A P35 FCTXD0 FCAN0 output 1S P36 FCRXD1Note FCAN1 inputNote 2A P37 FCTXD1Note FCAN1 outputNote 1S Note: Alternate function not available on PD70F3447. 906 Port Type User's Manual U16580EE3V1UD00 9 1S 9 Chapter 20 (2) Port Functions Control registers (a) Port register 3 (P3) The P3 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P30 to P37. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-30: After reset: P3 Undefined R/W Port Register 3 (P3) Address: FFFFF406H 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 P3n Input/Output Data Control of Pin P3n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 3 (PM3) The PM3 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-31: After reset: PM3 FFH R/W Address: FFFFF426H 7 6 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n Remark: Port Mode Register 3 (PM3) Input/Output Mode Control of Pin P3n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 7 User's Manual U16580EE3V1UD00 907 Chapter 20 Port Functions (c) Port mode control register 3 (PMC3) The PMC3 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Caution: On PD70F3447 do not set bits PMC34 and PMC36 to 1, since the corresponding alternate function is not available. Figure 20-32: After reset: PMC3 00H Port Mode Control Register 3 (PMC3) (1/2) R/W Address: FFFFF446H 7 6 5 4 3 2 1 0 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC37 Port/Control Mode Specification of Pin P37 0 I/O port mode 1 FCTXD1 output modeNote 2 PMC36 Port/Control Mode Specification of Pin P36 0 I/O port modeNote 1 1 FCRXD1 input modeNote 2 PMC35 Port/Control Mode Specification of Pin P35 0 I/O port mode 1 FCTXD0 output mode PMC34 Port/Control Mode Specification of Pin P34 0 I/O port modeNote 1 1 FCRXD0 input mode PMC33 Port/Control Mode Specification 0 I/O port mode 1 TXDC1 output mode Notes: 1. If this pin is set to port mode, the corresponding peripheral input signal (alternate function) is forced to high level internally. 2. Alternate function not available on PD70F3447. 908 User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-32: Port Mode Control Register 3 (PMC3) (2/2) PMC33 Port/Control Mode Specification of Pin P33 0 I/O port mode 1 TXDC1 output mode PMC32 0 Port/Control Mode Specification of Pin P32 I/O port modeNote PM32 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP5) RXDC1 input mode, External interrupt request input mode (INTP5) PMC31 Port/Control Mode Specification of Pin P31 0 I/O port mode 1 TXDC0 output mode PMC30 0 Port/Control Mode Specification of Pin P30 I/O port modeNote PM30 1 Port Functions Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP4) RXDC0 input mode, External interrupt request input mode (INTP4) Note: If this pin is set to port mode, the corresponding peripheral input signal (alternate function) is forced to high level internally. User's Manual U16580EE3V1UD00 909 Chapter 20 Port Functions 20.3.5 Port 4 Port 4 is a 6-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 4 (P4). * Input or output mode can be set in 1-bit units by using the port mode register 4 (PM4). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 4 (PMC4). Table 20-8: Port Port 4 Alternate Function Pins and Port Types of Port 4 Alternate Function Remark P40 SIB0 Serial interface (CSIB0) input P41 SOB0 Serial interface (CSIB0) output 1E P42 SCKB0 Serial interface (CSIB0) I/O 4C P43 SIB1Note Serial interface (CSIB1) inputNote 2 P44 SOB1Note Serial interface (CSIB1) outputNote 1E P45 SCKB1Note Serial interface (CSIB1) I/ONote 4C Note: Alternate function not available on PD70F3447. 910 Port Type User's Manual U16580EE3V1UD00 2 Chapter 20 (2) Port Functions Control registers (a) Port register 4 (P4) The P4 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P40 to P45. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-33: After reset: P4 Undefined R/W Port Register 4 (P4) Address: FFFFF408H 7 6 5 4 3 2 1 0 0 0 P45 P44 P43 P42 P41 P40 P4n Input/Output Data Control of Pin P4n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 4 (PM4) The PM4 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-34: After reset: PM4 FFH R/W Address: FFFFF428H 7 6 5 4 3 2 1 0 1 1 PM45 PM44 PM43 PM42 PM41 PM40 PM4n Remark: Port Mode Register 4 (PM4) Input/Output Mode Control of Pin P4n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 5 User's Manual U16580EE3V1UD00 911 Chapter 20 Port Functions (c) Port mode control register 4 (PMC4) The PMC4 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Caution: On PD70F3447 do not set bits PMC43 to PMC45 to 1, since the corresponding alternate function is not available. Figure 20-35: After reset: PMC4 00H Port Mode Control Register 4 (PMC4) R/W Address: FFFFF448H 7 6 5 4 3 2 1 0 0 0 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 PMC45 Port/Control Mode Specification of Pin P45 0 I/O port mode 1 SCKB1 I/O mode (input or output mode controlled by CSIB1)Note PMC44 Port/Control Mode Specification of Pin P44 0 I/O port mode 1 SOB1 output modeNote PMC43 Port/Control Mode Specification of Pin P43 0 I/O port mode 1 SIB1input modeNote PMC42 Port/Control Mode Specification of Pin P42 0 I/O port mode 1 SCKB0 I/O mode (input or output mode controlled by CSIB0) PMC41 Port/Control Mode Specification of Pin P41 0 I/O port mode 1 SOB0 output mode PMC40 Port/Control Mode Specification of Pin P40 0 I/O port mode 1 SIB0 input mode Note: Alternate function not available on PD70F3447. 912 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.6 Port 5 Port 5 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 5 (P5). * Input or output mode can be set in 1-bit units by using the port mode register 5 (PM5). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 5 (PMC5). * Emergency shut off by ES0 input signal of output buffers P51 to P56 can be controlled by port emergency shut off control register 5 (PESC5) and emergency shut off status register 5 (ESOST5). * Security feature to protect the timer output signals of TMR0 from unintended CPU interference. Registers P5, PM5, PMC5, PESC5 and ESOST5 can only be written in a special sequence. Table 20-9: Port Port 5 Alternate Function Pins and Port Types of Port 5 Alternate Function P50 TOR00 P51 TOR01 P52 TOR02 P53 TOR03 P54 TOR04 P55 TOR05 P56 TOR06 P57 TOR07 Remark Timer output (TMR0) Port Type 11 13 11 User's Manual U16580EE3V1UD00 913 Chapter 20 (2) Port Functions Control registers (a) Port register 5 (P5) The P5 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P50 to P57. Writing to the P5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the P5 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register P5. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-36: After reset: P5 Undefined R/W Port Register 5 (P5) Address: FFFFF40AH 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 P5n Input/Output Data Control of Pin P5n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 5 (PM5) The PM5 register is an 8-bit register that specifies the input or output mode. Writing to the PM5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PM5 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register PM5. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-37: After reset: PM5 FFH R/W 914 Address: FFFFF42AH 7 6 5 4 3 2 1 0 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM5n Remark: Port Mode Register 5 (PM5) Input/Output Mode Control of Pin P5n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 7 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (c) Port mode control register 5 (PMC5) The PMC5 register is an 8-bit register that specifies the port mode or control mode (alternate function). Writing to the PMC5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PMC5 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register PMC5. For details refer to 3.4.8 "Specific registers" on page 139. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-38: After reset: PMC5 00H R/W Address: FFFFF44AH 7 6 5 4 3 2 1 0 PMC57 PMC56 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC5n Remark: Port Mode Control Register 5 (PMC5)) Port/Control Mode Specification of Pin P5n 0 I/O port mode 1 TOR0n output mode n = 0 to 7 User's Manual U16580EE3V1UD00 915 Chapter 20 Port Functions (d) Port emergency shut off control register 5 (PESC5) The PESC5 register is an 8-bit register that controls the emergency shut off behaviour of output buffers of ports P51 to P56. Writing to the PESC5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PESC5 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register PESC5. For details refer to 3.4.8 "Specific registers" on page 139. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-39: After reset: PESC5 Port Emergency Shut Off Control Register 5 (PESC5) 00H R/W FFFFF888H 7 6 5 4 3 2 1 0 0 0 0 0 ESO0EN 0 ESO0ED1 ESO0EDO0 ESO0EN Emergency Output Shut Off Enable Control 0 Emergency shut off control by ESO0 input disabled 1 Emergency shut off control by ESO0 input enabled ESO0ED1 ESO0ED0 Caution: Address: Valid Edge Specification of Emergency Shut Off Input (ESO0) 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level State of the edge detection control bits ESO0ED1 and ESO0ED0 must not be changed while ESO0EN is set (1). Otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. Remarks: 1. The output buffers of ports P51 to P56 are forcibly disabled (high impedance output) as long as ESO0EN and ESO0ST are set to 1. 2. Setup of the emergency shut off function must be performed in the following sequence. Otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. <1> power on (All registers are reset) <2> PRCMD write (write protect released) <3> clear ESO0EN bit to 0 <4> PRCMD write (write protect released) <5> clear ESO0ST bit of ESOST5 register to 0 <6> PRCMD write (write protect released) <7> set ESO0ED0, ESO0ED1 bits <8> PRCMD write (write protect released) <9> set ESO0EN bit to 1 916 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (e) Port emergency shut off status register 5 (ESOST5) The ESOST5 register is an 8-bit register that indicates the emergency status control mode (alternate function). Writing to the ESOST5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the ESOST5 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register ESOST5. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-40: After reset: ESOST5 Port Emergency Shut Off Status Register 5 (ESOST5)) 00H R/W Address: FFFFF88AH 7 6 5 4 3 2 1 0 ESO0ST 0 0 0 0 0 0 0 ESO0ST Emergency Shut Off Status 0 No emergency shut off was triggered 1 Emergency shut off of output ports P51 to P56 triggered by ESO0 input Remarks: 1. Writing the emergency shut off status flag (ESO0ST) is only possible, if the ES0EN bit of the PESC5 register is cleared (0). 2. The ESO0ST flag can only be cleared by CPU to 0. Setting the ESO0ST flag to 1 is not possible. 3. The output buffers of P51 to P56 are forcibly disabled as long as ESO0EN and ESO0ST of the PESC5 register are set to 1. User's Manual U16580EE3V1UD00 917 Chapter 20 Port Functions 20.3.7 Port 6 Port 6 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 6 (P6). * Input or output mode can be set in 1-bit units by using the port mode register 6 (PM6). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 6 (PMC6). * Emergency shut off by ES0 input signal of output buffers P61 to P66 can be controlled by port emergency shut off control register 6 (PESC6) and emergency shut off status register 6 (ESOST6). * Security feature to protect the timer output signals of TMR0 from unintended CPU interference. Registers P6, PM6, PMC6, PESC6 and ESOST6 can only be written in a special sequence. Table 20-10: Port Port 6 918 Alternate Function Pins and Port Types of Port 6 Alternate Function P60 TOR10, TTRGR1 P61 TOR11, TIR10 P62 TOR12, TIR11 P63 TOR13, TIR12 P64 TOR14, TIR13 P65 TOR15 P66 TOR16 P67 TOR17, TEVTR1 Remark Timer I/O (TMR1) Port Type 12 14 Timer output (TMR1) 13 Timer I/O (TMR1) 12 User's Manual U16580EE3V1UD00 Chapter 20 (2) Port Functions Control registers (a) Port register 6 (P6) The P6 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P60 to P67. Writing to the P6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the P6 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register P6. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-41: After reset: P6 Undefined R/W Port Register 6 (P6) Address: FFFFF40CH 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 P6n Input/Output Data Control of Pin P6n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 6 (PM6) The PM6 register is an 8-bit register that specifies the input or output mode. Writing to the PM6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PM6 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register PM6. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-42: After reset: PM6 FFH R/W Address: FFFFF42CH 7 6 5 4 3 2 1 0 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM6n Remark: Port Mode Register 6 (PM6) Input/Output Mode Control of Pin P6n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 7 User's Manual U16580EE3V1UD00 919 Chapter 20 Port Functions (c) Port mode control register 6 (PMC6) The PMC6 register is an 8-bit register that specifies the port mode or control mode (alternate function). Writing to the PMC6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PMC6 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register PMC6. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-43: After reset: PMC6 00H Port Mode Control Register 6 (PMC6) (1/2) R/W Address: FFFFF44CH 7 6 5 4 3 2 1 0 PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 PMC67 Port/Control Mode Specification of Pin P67 0 I/O port mode 1 Control mode PM67 Function 0 TOR17 output mode 1 TTEVTR1 input mode PMC66 Port/Control Mode Specification of Pin P66 0 I/O port mode 1 TOR16 output mode PMC65 Port/Control Mode Specification of Pin P65 0 I/O port mode 1 TOR15 output mode PMC64 Port/Control Mode Specification of Pin P64 0 I/O port mode 1 Control mode PM64 920 Function 0 TOR14 output mode 1 TIR13 input mode User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-43: Port Functions Port Mode Control Register 6 (PMC6) (2/2) PMC63 Port/Control Mode Specification of Pin P63 0 I/O port mode 1 Control mode PM63 Function 0 TOR13 output mode 1 TIR12 input mode PMC62 Port/Control Mode Specification of Pin P62 0 I/O port mode 1 Control mode PM62 Function 0 TOR12 output mode 1 TIR11 input mode PMC61 Port/Control Mode Specification of Pin P61 0 I/O port mode 1 Control mode PM61 Function 0 TOR11 output mode 1 TIR10 input mode PMC60 Port/Control Mode Specification of Pin P60 0 I/O port mode 1 Control mode PM63 Remark: Function 0 TOR10 output mode 1 TTRGR1 input mode n = 0 to 7 User's Manual U16580EE3V1UD00 921 Chapter 20 Port Functions (d) Port emergency shut off control register 6 (PESC6) The PESC6 register is an 8-bit register that controls the emergency shut off behaviour of output buffers of ports P61 to P66. Writing to the PESC6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PESC6 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register PESC6. For details refer to 3.4.8 Specific registers. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-44: After reset: PESC6 Port Emergency Shut Off Control Register 6 (PESC6) 00H R/W FFFFF88CH 7 6 5 4 3 2 1 0 0 0 0 0 ESO0EN 0 ESO0ED1 ESO0EDO0 ESO1EN Emergency Output Shut Off Enable Control 0 Emergency shut off control by ESO1 input disabled 1 Emergency shut off control by ESO1 input enabled ESO1ED1 ESO1ED0 Caution: Address: Valid Edge Specification of Emergency Shut Off Input (ESO1) 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level State of the edge detection control bits ESO1ED1 and ESO1ED0 must not be changed while ESO1EN is set (1). Otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. Remarks: 1. The output buffers of ports P61 to P66 are forcibly disabled (high impedance output) as long as ESO1EN and ESO1ST are set to 1. 2. Setup of the emergency shut off function must be performed in the following sequence. Otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. <1> power on (All registers are reset) <2> PRCMD write (write protect released) <3> clear ESO1EN bit to 0 <4> PRCMD write (write protect released) <5> clear ESO1ST bit of ESOST6 register to 0 <6> PRCMD write (write protect released) <7> set ESO1ED0, ESO1ED1 bits <8> PRCMD write (write protect released) <9> set ESO1EN bit to 1 922 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (e) Port emergency shut off status register 6 (ESOST6) The ESOST6 register is an 8-bit register that indicates the emergency status control mode (alternate function). Writing to the ESOST6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the ESOST6 register is accepted. A read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register ESOST6. For details refer to 3.4.8 "Specific registers" on page 139. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-45: After reset: ESOST6 Port Emergency Shut Off Status Register 6 (ESOST6)) 00H R/W Address: FFFFF88EH 7 6 5 4 3 2 1 0 ESO1ST 0 0 0 0 0 0 0 ESO1ST Emergency Shut Off Status 0 No emergency shut off was triggered 1 Emergency shut off of output ports P61 to P66 triggered by ESO1 input Remarks: 1. Writing the emergency shut off status flag (ESO1ST) is only possible, if the ES1EN bit of the PESC6 register is cleared (0). 2. The ESO1ST flag can only be cleared by CPU to 0. Setting the ESO1ST flag to 1 is not possible. 3. The output buffers of P61 to P66 are forcibly disabled as long as ESO1EN and ESO1ST of the PESC6 register are set to 1. User's Manual U16580EE3V1UD00 923 Chapter 20 Port Functions 20.3.8 Port 7 Port 7 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 7 (P7). * Input or output mode can be set in 1-bit units by using the port mode register 7 (PM7). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 7 (PMC7). * The external interrupt request input shared with the input port functionality of port 7 is always enabled in input port mode. Table 20-11: Port Port 7 924 Alternate Function Pins and Port Types of Port 7 Alternate Function Remark Port Type P70 TIT00, TEVT1, TOT00 Timer input (TMT0, TMT1) Timer output (TMT0) P71 TIT01, TTRGT1, TOT01 Timer input (TMT0, TMT1) Timer output (TMT0) P72 TECRT0, INTP12 Timer input (TMT0), External interrupt request input 8 P73 TIT10, TTRGT0, TOT10 Timer input (TMT0, TMT1) Timer output (TMT1) 6 P74 TIT11, TEVT0, TOT11 Timer input (TMT0, TMT1) Timer output (TMT1) P75 TECRT1, AFO Timer input (TMT1) Auxiliary frequency output User's Manual U16580EE3V1UD00 6 Chapter 20 (2) Port Functions Control registers (a) Port register 7 (P7) The P7 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P70 to P75. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-46: After reset: P7 Undefined R/W Port Register 7 (P7) Address: FFFFF40EH 7 6 5 4 3 2 1 0 0 0 P75 P74 P73 P72 P71 P70 P7n Input/Output Data Control of Pin P7n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 4 (PM7) The PM7 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-47: After reset: PM7 FFH R/W Address: FFFFF42EH 7 6 5 4 3 2 1 0 1 1 PM75 PM74 PM73 PM72 PM71 PM70 PM7n Remark: Port Mode Register 7 (PM7) Input/Output Mode Control of Pin P7n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 5 User's Manual U16580EE3V1UD00 925 Chapter 20 Port Functions (c) Port mode control register 4 (PMC7) The PMC7 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-48: After reset: PMC7 00H Port Mode Control Register 7 (PMC7) (1/2) R/W Address: 7 6 5 4 3 2 1 0 0 0 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC75 Port/Control Mode Specification of Pin P75 0 I/O port mode 1 Control mode PM75 Function 0 AFO output mode 1 TECRT1 input mode PMC74 Port/Control Mode Specification of Pin P74 0 I/O port mode 1 Control mode PM74 Function 0 TOT11 output mode 1 TIT11 input mode, TEVTT0 input mode PMC73 Port/Control Mode Specification of Pin P73 0 I/O port mode 1 Control mode PM73 926 FFFFF44EH Function 0 TOT10 output mode 1 TIT10 input mode, TTRGT0 input mode User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-48: Port Mode Control Register 7 (PMC7) (2/2) PMC72 0 Port Functions Port/Control Mode Specification of Pin P72 I/O port mode PM72 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP12) TECRT0 input mode External interrupt request input mode (INTP12) PMC71 Port/Control Mode Specification of Pin P71 0 I/O port mode 1 Control mode PM71 Function 0 TOT01 output mode 1 TIT01, TTRGT1 input mode PMC70 Port/Control Mode Specification of Pin P70 0 I/O port mode 1 Control mode PM70 Function 0 TOT00 output mode 1 TIT00, TEVTT1 input mode User's Manual U16580EE3V1UD00 927 Chapter 20 Port Functions 20.3.9 Port 8 Port 8 is a 7-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 8 (P8). * Input or output mode can be set in 1-bit units by using the port mode register 8 (PM8). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 8 (PMC8). * The external interrupt request inputs shared with the input port functionality of port 8 are always enabled in input port mode. Table 20-12: Port Port 8 928 Alternate Function Pins and Port Types of Port 8 Alternate Function Remark Port Type P80 SI30 Serial interface (CSI30) input P81 SO30 Serial interface (CSI30) output P82 SCK30 Serial interface (CSI30) I/O 4 P83 SCS300, INTP6 Serial interface (CSI30) output, External interrupt request input 7 P84 SCS301, INTP7 Serial interface (CSI30) output, External interrupt request input P85 SCS302, INTP8 Serial interface (CSI30) output, External interrupt request input P86 SCS303, SSB0 Serial interface (CSI30) output, Serial interface (CSIB0) input User's Manual U16580EE3V1UD00 2 1S 5 Chapter 20 (2) Port Functions Control registers (a) Port register 8 (P8) The P8 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P80 to P86. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-49: After reset: P8 Undefined R/W Port Register 8 (P8) Address: FFFFF410H 7 6 5 4 3 2 1 0 0 P86 P85 P84 P83 P82 P81 P80 P8n Input/Output Data Control of Pin P8n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 8 (PM8) The PM8 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-50: After reset: PM8 FFH R/W Address: FFFFF430H 7 6 5 4 3 2 1 0 1 PM86 PM85 PM84 PM83 PM82 PM81 PM80 PM8n Remark: Port Mode Register 8 (PM8) Input/Output Mode Control of Pin P8n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 6 User's Manual U16580EE3V1UD00 929 Chapter 20 Port Functions (c) Port mode control register 8 (PMC8) The PMC8 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-51: After reset: PMC8 00H Port Mode Control Register 8 (PMC8) (1/2) R/W Address: FFFFF450H 7 6 5 4 3 2 1 0 0 PMC86 PMC85 PMC84 PMC83 PMC82 PMC81 PMC80 PMC86 Port/Control Mode Specification of Pin P86 0 I/O port mode 1 Control mode PM86 Function 0 SCS303 output mode 1 SSB0 input mode PMC85 0 Port/Control Mode Specification of Pin P85 I/O port mode PM85 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP8) Control mode PM85 Function 0 SCS302 output mode 1 External interrupt request input mode (INTP8) PMC84 0 Port/Control Mode Specification of Pin P84 I/O port mode PM84 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP7) Control mode PM84 930 Function 0 SCS301 output mode 1 External interrupt request input mode (INTP7) User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-51: Port Mode Control Register 8 (PMC8) (2/2) PMC83 0 Port Functions Port/Control Mode Specification of Pin P83 I/O port mode PM83 1 Function 0 Output 1 Input, External interrupt request input mode (INTP6) Control mode PM83 Function 0 SCS300 output mode 1 External interrupt request input mode (INTP6) PMC82 Port/Control Mode Specification of Pin P82 0 I/O port mode 1 SCK30 I/O mode PMC81 Port/Control Mode Specification of Pin P81 0 I/O port mode 1 SO30 output mode PMC80 Port/Control Mode Specification of Pin P80 0 I/O port mode 1 SI30 input mode User's Manual U16580EE3V1UD00 931 Chapter 20 Port Functions 20.3.10 Port 9 Port 9 is a 7-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 9 (P9). * Input or output mode can be set in 1-bit units by using the port mode register 9 (PM9). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 9 (PMC9). * The external interrupt request inputs shared with the input port functionality of port 9 are always enabled in input port mode. Table 20-13: Port Port 9 Alternate Function Pins and Port Types of Port 9 Alternate Function Remark P90 SI31Note Serial interface (CSI31) inputNote P91 SO31Note Serial interface (CSI31) outputNote P92 SCK31Note Serial interface (CSI31) I/ONote 4 P93 SCS310Note, INTP9 Serial interface (CSI31) outputNote, External interrupt request input 7 P94 SCS311Note, INTP10 Serial interface (CSI31) outputNote, External interrupt request input P95 SCS312Note, INTP11 Serial interface (CSI31) outputNote, External interrupt request input P96 SCS313Note, SSB1Note Serial interface (CSI31) outputNote, Serial interface (CSIB1) inputNote Note: Alternate function not available on PD70F3447. 932 Port Type User's Manual U16580EE3V1UD00 2 1S 5 Chapter 20 (2) Port Functions Control registers (a) Port register 9 (P9) The P9 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P90 to P96. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-52: After reset: P9 Undefined R/W Port Register 9 (P9) Address: FFFFF412H 7 6 5 4 3 2 1 0 0 P96 P95 P94 P93 P92 P91 P90 P9n Input/Output Data Control of Pin P9n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 9 (PM9) The PM9 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-53: After reset: PM9 FFH R/W Address: FFFFF432H 7 6 5 4 3 2 1 0 1 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM9n Remark: Port Mode Register 9 (PM9) Input/Output Mode Control of Pin P9n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 6 User's Manual U16580EE3V1UD00 933 Chapter 20 Port Functions (c) Port mode control register 9 (PMC9) The PMC9 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Caution: On PD70F3447 do not set bits PMC90 to PMC96 to 1, since the corresponding alternate function is not available. Figure 20-54: After reset: PMC9 00H Port Mode Control Register 9 (PMC9) (1/2) R/W Address: FFFFF452H 7 6 5 4 3 2 1 0 0 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC96 Port/Control Mode Specification of Pin P96 0 I/O port mode 1 Control modeNote PM96 Function 0 SCS313 output mode 1 SSB1 input mode PMC95 0 Port/Control Mode Specification of Pin P95 I/O port mode PM95 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP11) Control modeNote PM95 Function 0 SCS312 output mode 1 External interrupt request input mode (INTP11) Note: Alternate function not available on PD70F3447. 934 User's Manual U16580EE3V1UD00 Chapter 20 Figure 20-54: Port Mode Control Register 9 (PMC9) (2/2) PMC94 0 Port Functions Port/Control Mode Specification of Pin P94 I/O port mode PM94 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP10) Control modeNote PM94 Function 0 SCS311 output mode 1 External interrupt request input mode (INTP10) PMC93 0 Port/Control Mode Specification of Pin P93 I/O port modeNote PM93 1 Function 0 Output mode 1 Input mode, External interrupt request input mode (INTP9) Control modeNote PM93 Function 0 SCS310 output mode 1 External interrupt request input mode (INTP9) PMC92 Port/Control Mode Specification of Pin P92 0 I/O port mode 1 SCK31 I/O modeNote PMC91 Port/Control Mode Specification of Pin P91 0 I/O port mode 1 SO31 output modeNote PMC90 Port/Control Mode Specification of Pin P90 0 I/O port mode 1 SI31 input modeNote Note: Alternate function not available on PD70F3447. User's Manual U16580EE3V1UD00 935 Chapter 20 Port Functions 20.3.11 Port 10 Port 10 is a 3-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register 10 (P10). * Input or output mode can be set in 1-bit units by using the port mode register 10 (PM10). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 10 (PMC10). Table 20-14: Port Port 10 Alternate Function Pins and Port Types of Port 10 Alternate Function Remark P100 TCLR0Note, TICC00Note, TOP81 Timer input (ITENC0)Note Timer output (TMP8) 6 P101 TCUD0Note, TICC01Note Timer input (ITENC0)Note 10 P102 TIUD0Note, TO1Note Timer input (ITENC0)Note, Timer output (ITENC0)Note 6 Note: Alternate function not available on PD70F3447. 936 Port Type User's Manual U16580EE3V1UD00 Chapter 20 (2) Port Functions Control registers (a) Port register 10 (P10) The P10 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P100 to P105. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-55: After reset: P10 Undefined R/W Port Register 10 (P10) Address: FFFFF414H 7 6 5 4 3 2 1 0 0 0 0 0 0 P102 P101 P100 P10n Input/Output Data Control of Pin P10n 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output (b) Port mode register 10 (PM10) The PM10 register is an 8-bit register that specifies the input or output mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-56: After reset: PM10 FFH R/W Address: FFFFF434H 7 6 5 4 3 2 1 0 1 1 1 1 1 PM102 PM101 PM100 PM10n Remark: Port Mode Register 10 (PM10) Input/Output Mode Control of Pin P10n (in Port Mode) 0 Output mode 1 Input mode n = 0 to 2 User's Manual U16580EE3V1UD00 937 Chapter 20 Port Functions (c) Port mode control register 10 (PMC10) The PMC10 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Caution: On PD70F3447 do not set bits PMC100 and PMC101 to 1, since the corresponding alternate function is not available. Further do not set PMC102 to 1, when PM102 is set (1). Figure 20-57: After reset: PMC10 00H Port Mode Control Register 10 (PMC10) R/W Address: FFFFF454H 7 6 5 4 3 2 1 0 0 0 0 0 0 PMC102 PMC101 PMC100 PMC102 Port/Control Mode Specification of Pin P102 0 I/O port mode 1 Control mode PM102 Function 0 TOP81 output mode 1 TCLR0 input modeNote, TICC0 input modeNote PMC101 Port/Control Mode Specification of Pin P101 0 I/O port mode 1 TCUD0 input modeNote, TICC01 input modeNote PMC100 Port/Control Mode Specification of Pin P100 0 I/O port mode 1 Control modeNote PM100 Function 0 TO1 output mode 1 TIUD0 input mode Note: Alternate function not available on PD70F3447. 938 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.12 Port AL Port AL is a 16-bit I/O port that can be set to input or output mode in 1-bit units. When the higher 8 bits of port AL are used as port ALH (PALH) and the lower 8 bits as port ALL (PALL), port AL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register AL (PAL). * Input or output mode can be set in 1-bit units by using the port mode register AL (PMAL). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register AL (PMCAL). Table 20-15: Port Port AL Alternate Function Pins and Port Types of Port AL Alternate Function PAL0 A0 to A15Note to PAL15 Remark External address busNote Port Type 1 Note: Alternate function not available on PD70F3447. Caution: On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external address bus function only. Reprogramming of port AL to port mode is not possible in these modes. Reading and writing of the port register PAL and port mode register PMAL is possible but has no effect. Reading of the port mode control register PMCAL is possible and the result is always FFFFH. Writing of the port mode control register PMCAL is not possible. User's Manual U16580EE3V1UD00 939 Chapter 20 (2) Port Functions Control registers (a) Port register AL (PAL) The PAL register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins PAL0 to PAL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PAL register are used as PALH register, and the lower 8 bits as the PALL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-58: After reset: Undefined 15 PAL 14 R/W 13 12 Port Register AL(PAL) Address: 11 10 9 8 FFFFF000H 7 6 5 4 After reset: PALL After reset: Undefined 940 1 0 PALL R/W Address: FFFFF000H 7 6 5 4 3 2 1 0 PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 Undefined R/W Address: FFFFF001H 7 6 5 4 3 2 1 0 PAL15 PAL14 PAL13 PAL12 PAL11 PAL10 PAL9 PAL8 PALn Remark: 2 PAL15 PAL14 PAL13 PAL12 PAL11 PAL10 PAL9 PAL8 PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 PALH PALH 3 Input/Output Data Control of Pin PALn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0 to 15 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (b) Port mode register AL (PMAL) The PMAL register is a 16-bit register that specifies the input or output mode of port pins PAL0 to PAL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PMAL register are used as PMALH register, and the lower 8 bits as the PMALL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFFFH. Figure 20-59: After reset: FFFFH 15 PMAL 14 Port Mode Register AL(PMAL) R/W 13 12 Address: 11 10 9 8 FFFFF020H 7 6 5 4 PMALH After reset: PMALL FFH 1 0 PMALL R/W Address: FFFFF020H 6 5 4 3 2 1 0 PMAL7 PMAL6 PMAL5 PMAL4 PMAL3 PMAL2 PMAL1 PMAL0 FFH R/W Address: FFFFF021H 7 6 5 4 3 2 1 0 PMAL15 PMAL14 PMAL13 PMAL12 PMAL11 PMAL10 PMAL9 PMAL8 PMALn Remark: 2 7 After reset: PMALH 3 PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL PMAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Input/Output Mode Control of Pin PALn (in Port Mode) 0 Output mode 1 Input mode n = 0 to 15 User's Manual U16580EE3V1UD00 941 Chapter 20 Port Functions (c) Port AL mode control register The PMCAL register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of Port AL. This register can be read or written in 16-bit units. If the higher 8 bits of the PMCAL register are used as PMCALH register, and the lower 8 bits as the PMCALL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to 0000H in single-chip mode 0, and to FFFFH in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCALn bits to 1, since the corresponding alternate function is not available. Figure 20-60: After resetNote 1: PMCAL R/WNote 2 Address: 0000H/ FFFFH 15 14 13 Port Mode Control Register AL (PMCAL) 12 11 10 9 8 FFFFF040H 7 6 5 4 PMCALH After resetNote 1: PMCALL 2 1 0 PMCALL R/WNote 2 Address: 00H/FFH FFFFF040H 7 6 5 4 3 2 1 0 PMCAL7 PMCAL6 PMCAL5 PMCAL4 PMCAL3 PMCAL2 PMCAL1 PMCAL0 2 1 After resetNote 1: R/WNote 2 Address: 00H/FFH 7 PMCALH 3 PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCAL PMCA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L0 6 5 4 FFFFF041H 3 PMCAL15 PMCAL14 PMCAL13 PMCAL12 PMCAL11 PMCAL10 PMCAL9 PMCALn 0 PMCAL8 Port/Control Mode Specification of Pin PALn 0 I/O port mode 1 External address bus output mode (A15 to A0)Note 3 Notes: 1. In single-chip mode 0: 0000H, or 00H respectively In single-chip mode 1 and ROM-less mode (PD70F31187 only): FFFFH, or FFH respectively 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns FFFFH, or FFH respectively. 3. Alternate function not available on PD70F3447. Remark: 942 n = 0 to 15 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.13 Port AH Port AH is a 6-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register AH (PAH). * Input or output mode can be set in 1-bit units by using the port mode register AH (PMAH). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register AH (PMCAH). Table 20-16: Port Port AH Alternate Function Pins and Port Types of Port AH Alternate Function PAH0 to PAH5 A16 to A21Note Remark Port Type 1 External address busNote Note: Alternate function not available on PD70F3447. Caution: (2) On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external address bus function only. Reprogramming of port AH to port mode is not possible in these modes. Reading and writing of the port register PAH and port mode register PMAH is possible but has no effect. Reading of the port mode control register PMCAH is possible and the result is always 3FH. Writing of the port mode control register PMCAH is not possible. Control registers (a) Port register AH (PAH) The PAH register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins PAH0 to PAH5. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-61: After reset: PAH Undefined Address: FFFFF002H 7 6 5 4 3 2 1 0 0 0 PAH5 PAH4 PAH3 PAH2 PAH1 PAH0 PAHn Remark: R/W Port Register AH (PAH) Input/Output Data Control of Pin PAHn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0 to 5 User's Manual U16580EE3V1UD00 943 Chapter 20 Port Functions (b) Port mode register AH (PMAH) The PMAH register is an 8-bit register that specifies the input or output mode of port pins PAL0 to PAL15. This register can be read or written in 8-bit units. Reset input sets this register to FFH. Figure 20-62: After reset: PMAH FFH Port Mode Register AH (PMAH) R/W Address: FFFFF022H 7 6 5 4 3 2 1 0 1 1 PMAH5 PMAH4 PMAH3 PMAH2 PMAH1 PMAH0 PMAHn Input/Output Mode Control of Pin PAHn (in Port Mode) 0 Output mode 1 Input mode (c) Port mode control register AH (PMCAH) The PMCAHL register is an 8-bit register that specifies the port mode or control mode (alternate function) of Port AL. This register can be read or written in 8-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 3FH in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCAHn bits to 1, since the corresponding alternate function is not available. Figure 20-63: After resetNote 1: PMCAH Port Mode Control Register AH (PMCAH) R/WNote 2 Address: 00H/3FH 7 6 0 0 5 4 FFFFF042H 3 2 1 0 PMCAH5 PMCAH4 PMCAH3 PMCAH2 PMCAH1 PMCAH0 PMCAHn Port/Control Mode Specification of Pin PAHn 0 I/O port mode 1 External memory address bus output mode (A21 to A16)Note 3 Notes: 1. In single-chip mode 0: 00H In single-chip mode 1 and ROM-less mode (PD70F31187 only): 3FH 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns 3FH. 3. Alternate function not available on PD70F3447. Remark: 944 n = 0 to 5 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.14 Port DL Port DL is a 16-bit I/O port that can be set to input or output mode in 1-bit units. When the higher 8 bits of port DL are used as port DLH (PDLH) and the lower 8 bits as port DLL (PDLL), port DL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register DL (PDL). * Input or output mode can be set in 1-bit units by using the port mode register DL (PMDL). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register DL (PMCDL). Table 20-17: Port Port DL Alternate Function Pins and Port Types of Port DL Alternate Function PDL0 D0 to D15Note to PDL15 Remark External data busNote Port Type 4C Note: Alternate function not available on PD70F3447 Caution: On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external data bus function only. Reprogramming of port DL to port mode is not possible in these modes. Reading and writing of the port register PDL and port mode register PMDL is possible but has no effect. Reading of the port mode control register PMCDL is possible and the result is always FFFFH. Writing of the port mode control register PMCDL is not possible. User's Manual U16580EE3V1UD00 945 Chapter 20 (2) Port Functions Control registers (a) Port register DL (PDL) The PDL register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins PDL0 to PDL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PDL register are used as PDLH register, and the lower 8 bits as the PDLL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-64: After reset: Undefined 15 PDL 14 R/W 13 12 Port Register DL(PDL) Address: 11 10 9 8 FFFFF004H 7 6 5 4 After reset: Undefined 946 0 PDLL R/W Address: FFFFF004H 6 5 4 3 2 1 0 PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 Undefined R/W Address: FFFFF005H 7 6 5 4 3 2 1 0 PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDLn Remark: 1 7 After reset: PDLH 2 PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLH PDLL 3 Input/Output Data Control of Pin PDLn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0 to 15 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (b) Port mode register DL (PMDL) The PMDL register is a 16-bit register that specifies the input or output mode of port pins PDL0 to PDL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PMDL register are used as PMDLH register, and the lower 8 bits as the PMDLL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFFFH. Figure 20-65: After reset: FFFFH 15 PMDL 14 Port Mode Register DL(PMDL) R/W 13 12 Address: 11 10 9 8 FFFFF024H 7 6 5 4 PMDLH After reset: PMDLL FFH 1 0 PMDLL R/W Address: FFFFF024H 6 5 4 3 2 1 0 PMDL7 PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0 FFH R/W Address: FFFFF025H 7 6 5 4 3 2 1 0 PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 PMDL9 PMDL8 PMDLn Remark: 2 7 After reset: PMDLH 3 PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL PMDL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Input/Output Mode Control of Pin PDLn (in Port Mode) 0 Output mode 1 Input mode n = 0 to 15 User's Manual U16580EE3V1UD00 947 Chapter 20 Port Functions (c) Port mode control register DL (PMCDL) The PMCDL register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of Port DL. This register can be read or written in 16-bit units. If the higher 8 bits of the PMCDL register are used as PMCDLH register, and the lower 8 bits as the PMCDLL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to 0000H in single-chip mode 0, and to FFFFH in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCDLn bits to 1, since the corresponding alternate function is not available. Figure 20-66: After resetNote 1: 0000H/ FFFFH 15 PMCDL 14 13 12 Port Mode Control Register DL (PMCDL) R/WNote 2 Address: 11 10 9 8 FFFFF044H 7 6 5 4 PMCDLH After resetNote 1: 1 0 6 5 FFFFF044H 4 3 2 1 0 PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 After resetNote 1: R/WNote 2 Address: 00H/FFH 7 PMCDLH 2 PMCDLL R/WNote 2 Address: 00H/FFH 7 PMCDLL 3 PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCDL PMCD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L0 6 5 FFFFF045H 4 3 2 1 0 PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10 PMCDL9 PMCDL8 PMCDLn 0 1 Port/Control Mode Specification of Pin PDLn I/O port mode External data bus output mode (D15 to D0)Note 3 Notes: 1. In single-chip mode 0: 0000H, or 00H respectively In single-chip mode 1 and ROM-less mode (PD70F31187 only): FFFFH, or FFH respectively 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns FFFFH, or FFH respectively. 3. Alternate function not available on PD70F3447 Remark: 948 n = 0 to 15 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.15 Port DH Port DH is a 16-bit I/O port that can be set to input or output mode in 1-bit units. When the higher 8 bits of port DH are used as port DHH (PDHH) and the lower 8 bits as port DHL (PDHL), port DH becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register DH (PDH). * Input or output mode can be set in 1-bit units by using the port mode register DH (PMDH). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register DH (PMCDH). Table 20-18: Port Port DH Alternate Function Pins and Port Types of Port DH Alternate Function PDH0 D16 to D31Note to PDH15 Remark External data busNote Port Type 4C Note: Alternate function not available on PD70F3447. Caution: On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external data bus function only. Reprogramming of port DH to port mode is not possible in these modes. Reading and writing of the port register PDH and port mode register PMDH is possible but has no effect. Reading of the port mode control register PMCDH is possible and the result is always FFFFH. Writing of the port mode control register PMCDH is not possible. User's Manual U16580EE3V1UD00 949 Chapter 20 (2) Port Functions Control registers (a) Port register DH (PDH) The PDH register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins PDH0 to PDH15. This register can be read or written in 16-bit units. If the higher 8 bits of the PDH register are used as PDHH register, and the lower 8 bits as the PDHL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-67: After reset: Undefined 15 PDH 14 R/W 13 12 Port Register DH(PDH) Address: 11 10 9 8 FFFFF006H 7 6 5 4 After reset: Undefined 950 0 PDHL R/W Address: FFFFF006H 6 5 4 3 2 1 0 PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 Undefined R/W Address: FFFFF007H 7 6 5 4 3 2 1 0 PDH15 PDH14 PDH13 PDH12 PDH11 PDH10 PDH9 PDH8 PDHn Remark: 1 7 After reset: PDHH 2 PDH15 PDH14 PDH13 PDH12 PDH11 PDH10 PDH9 PDH8 PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 PDHH PDHL 3 Input/Output Data Control of Pin PDHn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0 to 15 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (b) Port mode register DH (PMDH) The PMDH register is a 16-bit register that specifies the input or output mode of port pins PDH0 to PDH15. This register can be read or written in 16-bit units. If the higher 8 bits of the PMDH register are used as PMDHH register, and the lower 8 bits as the PMDHL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFFFH. Figure 20-68: After reset: FFFFH 15 PMDH 14 Port Mode Register DH(PMDH) R/W 13 12 Address: 11 10 9 8 FFFFF026H 7 6 5 4 PMDHH After reset: PMDHL FFH 1 0 PMDHL R/W Address: FFFFF026H 6 5 4 3 2 1 0 PMDH7 PMDH6 PMDH5 PMDH4 PMDH3 PMDH2 PMDH1 PMDH0 2 1 0 PMDH9 PMDH8 FFH 7 R/W 6 Address: 5 4 FFFFF027H 3 PMDH15 PMDH14 PMDH13 PMDH12 PMDH11 PMDH10 PMDHn Remark: 2 7 After reset: PMDHH 3 PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH PMDH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Input/Output Mode Control of Pin PDHn (in Port Mode) 0 Output mode 1 Input mode n = 0 to 15 User's Manual U16580EE3V1UD00 951 Chapter 20 Port Functions (c) Port mode control register DH (PMCDH) The PMCDH register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of Port DH. This register can be read or written in 16-bit units. If the higher 8 bits of the PMCDH register are used as PMCDHH register, and the lower 8 bits as the PMCDHL register, however, these registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to 0000H in single-chip mode 0, and to FFFFH in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCDHn bits to 1, since the corresponding alternate function is not available. Figure 20-69: After resetNote 1: 0000H/ FFFFH 15 PMCDH 14 13 12 Port Mode Control Register DH (PMCDH) R/WNote 2 Address: 11 10 9 8 FFFFF046H 7 6 5 4 PMCDHH After resetNote 1: 1 0 6 5 4 FFFFF046H 3 2 1 0 PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 After resetNote 1: R/WNote 2 Address: 00H/FFH 7 PMCDHH 2 PMCDHL R/WNote 2 Address: 00H/FFH 7 PMCDHL 3 PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD PMCD H15 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 6 5 4 FFFFF047H 3 2 1 0 PMCDH15 PMCDH14 PMCDH13 PMCDH12 PMCDH11 PMCDH10 PMCDH9 PMCDH8 PMCDHn Port/Control Mode Specification of Pin PDHn 0 I/O port mode 1 External memory address bus output mode (D31 to D16)Note 3 Notes: 1. In single-chip mode 0: 0000H, or 00H respectively In single-chip mode 1 and ROM-less mode (PD70F31187 only): FFFFH, or FFH respectively 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns FFFFH, or FFH respectively. 3. Alternate function not available on PD70F3447. Remark: 952 n = 0 to 15 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.16 Port CS Port CS is a 4-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register CS (PCS). * Input or output mode can be set in 1-bit units by using the port mode register CS (PMCS). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register CS (PMCCS). Table 20-19: Port Port CS Alternate Function Pins and Port Types of Port CS Alternate Function PCS0 CS0Note to Note PCS5 CS1 Remark Port Type 1 Chip select signal outputNote CS3Note CS4Note Note: Alternate function not available on PD70F3447. Caution: (2) On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external control bus function only. Reprogramming of port CS to port mode is not possible in these modes. Reading and writing of the port register PCS and port mode register PMCS is possible but has no effect. Reading of the port mode control register PMCCS is possible and the result is always 1BH. Writing of the port mode control register PMCCS is not possible. Control registers (a) Port register CS (PCS) The PCS register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins PCS0, PCS1, PCS3 and PCS4. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-70: After reset: PCS Undefined Address: FFFFF008H 7 6 5 4 3 2 1 0 0 0 0 PCS4 PCS3 0 PCS1 PCS0 PCSn Remark: R/W Port Register CS (PCS) Input/Output Data Control of Pin PCSn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0, 1, 3, 4 User's Manual U16580EE3V1UD00 953 Chapter 20 Port Functions (b) Port mode register CS (PMCS) The PMCS register is an 8-bit register that specifies the input or output mode of port pins PCS0, PCS1, PCS3 and PCS4. This register can be read or written in 8-bit units. Reset input sets this register to FFH. Figure 20-71: After reset: PMCS FFH R/W Port Mode Register CS (PMCS) Address: FFFFF028H 7 6 5 4 3 2 1 0 1 1 1 PMCS4 PMCS3 1 PMCS1 PMCS0 PMCSn Input/Output Mode Control of Pin PCSn (in Port Mode) 0 Output mode 1 Input mode (c) Port mode control register CS (PMCCS) The PMCCSL register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCS0, PCS1, PCS3 and PCS4. This register can be read or written in 8-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 1BH in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCCSn bits to 1, since the corresponding alternate function is not available. Figure 20-72: After resetNote 1: PMCCS Port Mode Control Register CS (PMCCS) R/WNote 2 Address: 00H/3FH 7 6 5 0 0 0 PMCCSn 4 FFFFF048H 3 PMCCS4 PMCCS3 2 0 1 0 PMCCS1 PMCCS0 Port/Control Mode Specification of Pin PCSn 0 I/O port mode 1 Chip select signal output mode (CSn)Note 3 Notes: 1. In single-chip mode 0: 00H In single-chip mode 1 and ROM-less mode: 1BH 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns 1BH. 3. Alternate function not available on PD70F3447. Remark: 954 n = 0, 1, 3, 4 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.17 Port CT Port CT is a 2-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register CT (PCT). * Input or output mode can be set in 1-bit units by using the port mode register CT (PMCT). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register CT (PMCCT). Table 20-20: Port Port CT Alternate Function Pins and Port Types of Port CT Alternate Function Remark PCT4 RDNote Read strobe signal outputNote PCT5 WRNote Write strobe signal outputNote Port Type 1 Note: Alternate function not available on PD70F3447. Caution: (2) On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external control bus function only. Reprogramming of port CT to port mode is not possible in these modes. Reading and writing of the port register PCT and port mode register PMCT is possible but has no effect. Reading of the port mode control register PMCCT is possible and the result is always 30H. Writing of the port mode control register PMCCT is not possible. Control registers (a) Port register CT (PCT) The PCT register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins PCT4 and PCT5. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-73: After reset: PCT Undefined Address: FFFFF00AH 7 6 5 4 3 2 1 0 0 0 PCT5 PCT4 0 0 0 0 PCTn Remark: R/W Port Register CT (PCT) Input/Output Data Control of Pin PCTn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 4, 5 User's Manual U16580EE3V1UD00 955 Chapter 20 Port Functions (b) Port mode register CT (PMCT) The PMCT register is an 8-bit register that specifies the input or output mode of port pins PCT4 and PCT5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-74: After reset: PMCT FFH R/W Address: FFFFF02AH 7 6 5 4 3 2 1 0 1 1 PMCT5 PMCT4 1 1 1 1 PMCTn 956 Port Mode Register CT (PMCT) Input/Output Mode Control of Pin PCTn (in Port Mode) 0 Output mode 1 Input mode User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (c) Port mode control register CT (PMCCT) The PMCCTL register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCT4 and PCT5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 30H in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCCTn bits to 1, since the corresponding alternate function is not available. Figure 20-75: After resetNote 1: PMCCT Port Mode Control Register CT (PMCCT) R/WNote 2 Address: 00H/3FH 7 6 0 0 5 4 PMCCT5 PMCCT4 PMCCT5 0 FFFFF04AH 3 2 1 0 0 0 0 0 Port/Control Mode Specification of Pin PCT5 I/O port mode 1 Write strobe signal output mode (WR)Note 3 PMCCT4 Port/Control Mode Specification of Pin PCT4 0 1 I/O port mode Read strobe signal output mode (RD)Note 3 Notes: 1. In single-chip mode 0: 00H In single-chip mode 1 and ROM-less mode: 30H 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns 30H. 3. Alternate function not available on PD70F3447. Remark: n = 4, 5 User's Manual U16580EE3V1UD00 957 Chapter 20 Port Functions 20.3.18 Port CM Port CM is a 4-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register CM (PCM). * Input or output mode can be set in 1-bit units by using the port mode register CM (PMCM). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register CM (PMCCM). Table 20-21: Port Port CM Alternate Function Pins and Port Types of Port CM Alternate Function PCM0 WAITNote PCM1 - PCM6 - PCM7 - Remark Port Type 2C Wait insertion signal inputNote 1 Note: Alternate function not available on PD70F3447. Caution: (2) On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external control bus function only. Reprogramming of port CM to port mode is not possible in these modes. Reading and writing of the port register PCM and port mode register PMCM is possible but has no effect. Reading of the port mode control register PMCCM is possible and the result is always 01H. Writing of the port mode control register PMCCM is not possible. Control registers (a) Port register CM (PCM) The PCM register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins PCM0, PCM1, PCM6 and PCM7. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-76: After reset: PCM Undefined 958 Address: FFFFF00CH 7 6 5 4 3 2 1 0 PCM7 PCM6 0 0 0 0 PCM1 PCM0 PCMn Remark: R/W Port Register CM (PCM) Input/Output Data Control of Pin PCMn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 0, 1, 6, 7 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (b) Port mode register CM (PMCM) The PMCM register is an 8-bit register that specifies the input or output mode of port pins PCM0, PCM1, PCM6 and PCM7. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-77: After reset: PMCM FFH R/W Address: FFFFF02CH 7 6 5 4 3 2 1 0 PMCM7 PMCM6 1 1 1 1 PMCM1 PMCM0 PMCMn Remark: Port Mode Register CM (PMCM) Input/Output Mode Control of Pin PCMn (in Port Mode) 0 Output mode 1 Input mode n = 0, 1, 6, 7 User's Manual U16580EE3V1UD00 959 Chapter 20 Port Functions (c) Port mode control register CM (PMCCM) The PMCCML register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCM0, PCM1, PCM6 and PCM7. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 01H in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCCMn bits to 1, since the corresponding alternate function is not available. Figure 20-78: After resetNote 1: PMCCM Port Mode Control Register CM (PMCCM) R/WNote 2 Address: 00H/01H FFFFF04CH 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMCCM0 PMCCM0 0 1 Port/Control Mode Specification of Pin PCM0 I/O port mode Wait insertion signal input mode (WAIT)Note 3 Notes: 1. In single-chip mode 0: 00H In single-chip mode 1 and ROM-less mode: 01H 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns 01H. 3. Alternate function not available on PD70F3447. 960 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.3.19 Port CD Port CD is a 4-bit I/O port that can be set to input or output mode in 1-bit units. (1) Functions * Input/output data can be specified in 1-bit units by using the port register CD (PCD). * Input or output mode can be set in 1-bit units by using the port mode register CD (PMCD). * Port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register CD (PMCCD). Table 20-22: Port Port CD Alternate Function Pins and Port Types of Port CD Alternate Function PCD2 BEN0Note Remark Port Type 1 Byte enable signal outputNote PCD3 BEN1Note PCD4 BEN2Note PCD5 BEN3Note Note: Alternate function not available on PD70F3447. Caution: (2) On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this port has external control bus function only. Reprogramming of port CD to port mode is not possible in these modes. Reading and writing of the port register PCD and port mode register PMCD is possible but has no effect. Reading of the port mode control register PMCCD is possible and the result is always 3CH. Writing of the port mode control register PMCCD is not possible. Control registers (a) Port register CD (PCD) The PCD register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins PCD2 to PCD5. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content. Figure 20-79: After reset: PCD Undefined R/W Port Register CD (PCD) Address: FFFFF00EH 7 6 5 4 3 2 1 0 0 0 PCD5 PCD4 PCD3 PCD2 0 0 User's Manual U16580EE3V1UD00 961 Chapter 20 PCDn Remark: 962 Port Functions Input/Output Data Control of Pin PCDn 0 Input mode: Low level is input Output mode: Low level is output 1 Input mode: High level is input Output mode: High level is output n = 2 to 5 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions (b) Port mode register CD (PMCD) The PMCD register is an 8-bit register that specifies the input or output mode of port pins PCD2 to PCD5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH. Figure 20-80: After reset: PMCD FFH R/W Address: FFFFF02EH 7 6 5 4 3 2 1 0 1 1 PMCD5 PMCD4 PMCD3 PMCD2 1 1 PMCDn Remark: Port Mode Register CD (PMCD) Input/Output Mode Control of Pin PCDn (in Port Mode) 0 Output mode 1 Input mode n = 2 to 5 User's Manual U16580EE3V1UD00 963 Chapter 20 Port Functions (c) Port mode control register CD (PMCCD) The PMCCDL register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCD2 to PCD5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 3CH in ROM-less mode and single-chip mode 1. Caution: On PD70F3447 do not set PMCCDn bits to 1, since the corresponding alternate function is not available. Figure 20-81: After resetNote 1: PMCCD Port Mode Control Register CD (PMCCD) R/WNote 2 Address: 00H/3FH 7 6 0 0 5 4 FFFFF04EH 3 2 PMCCD5 PMCCD4 PMCCD3 PMCCD2 PMCCD5 1 0 0 0 Port/Control Mode Specification of Pin PCD5 0 I/O port mode 1 Bus enable signal output mode (BEN3)Note 3 PMCCD4 Port/Control Mode Specification of Pin PCD4 0 I/O port mode 1 Bus enable signal output mode (BEN2)Note 3 PMCCD3 Port/Control Mode Specification of Pin PCD3 0 I/O port mode 1 Bus enable signal output mode (BEN1)Note 3 PMCCD2 Port/Control Mode Specification of Pin PCD2 0 I/O port mode 1 Bus enable signal output mode (BEN0)Note 3 Notes: 1. In single-chip mode 0: 00H In single-chip mode 1 and ROM-less mode: 3CH 2. On the PD70F31187, in single-chip mode 1 or in ROM-less mode, this register can not be written. Reading is possible and returns 3CH. 3. Alternate function not available on PD70F3447. 964 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions 20.4 Noise Elimination A timing controller used to secure the noise elimination time is provided for the pins shown in Table 20-23 below. Input signals that change within the noise elimination time are not internally acknowledged. Table 20-23: Unit Noise Elimination (1/2) Pin Delay Type Noise Elimination Time Analog Delay Several 10 ns (typ.) P00/NMI Digital delay 4 to 5 clocks * Maskable Interrupt * Forced output stop function (TMR) * A/D converter (ADC) P01/INTP0/ESO0 P02/INTP1/ESO1 Analog Delay 60 ns to 200 ns P03/INTP2/ADTRG0 P04/INTP3/ADTRG1 Digital delay 4 to 5 clocks * Maskable Interrupt * Asynchronous serial Interface (UART C) P30/RXDC0/INTP4 P32/RXDC1/INTP5 * Maskable Interrupt * Clocked serial interface 3 (CSI3) P83/SCS300/INTP6 P84/SCS301/INTP7 P85/SCS302/INTP8 P93/SCS310Note 1/INTP9 P94/SCS311Note 1/INTP10 P95/SCS312Note 1/INTP11 Timer ENC (TMNEC10)Note 1 P100/TCLR0/TICC00/TOP81 Reset RESET On-chip debug DRST Non-maskable interrupt Sampling Clock fXX/16 (250 ns @ fXX = 64 MHz) fXX/64 (1 s @ fXX = 64 MHz) fXX/16 (250 ns @ fXX = 64 MHz) fXX/64 (1 s @ fXX = 64 MHz) Note 2 P101/TCUD0/TICC01Note 2 P102/TIUD0/TO1Note 2 Notes: 1. Not available on PD70F3447. 2. No noise elimination on PD70F3447 User's Manual U16580EE3V1UD00 965 Chapter 20 Table 20-23: Unit Port Functions Noise Elimination (2/2) Pin Timer P (TMP) P10/TIP00/TEVTP1/TOP00 P11/TIP01/TTRGP1/TOP01 P12/TIP10/TTRGP0/TOP10 P13/TIP11/TEVTP0/TOP11 P14/TIP20/TEVTP3/TOP20 P15/TIP21/TTRGP3/TOP21 P16/TIP30/TTRGP2/TOP30 P17/TIP31/TEVTP2/TOP31 P20/TIP40/TEVTP5/TOP40 P21/TIP41/TTRGP5/TOP41 P22/TIP50/TTRGP4/TOP50 P23/TIP51/TEVTP4/TOP51 P24/TIP60/TEVTP7/TOP60 P25/TIP61/TTRGP7/TOP61 P26/TIP70/TTRGP6/TOP70 P27/TIP71/TEVTP6/TOP71 Timer R (TMR) P60/TOR10/TTRGR1 P61/TOR11/TIR10 P62/TOR12/TIR11 P63/TOR13/TIR12 P64/TOR14/TIR13 P67/TOR17/TEVTR1 Timer T (TMT) P70/TIT00/TEVTT1/TOT00 P71/TIT01/TTRGT1/TOT01 P72/TECRT0/INTP12 P73/TIT10/TTRGT0/TOT10 P74/TIT11/TEVTT0/TOT11 P75/TECRT1/AFO Caution: 966 Delay Type Digital delay Noise Elimination Time 4 to 5 clocks Sampling Clock fXX/16 (250 ns @ fXX = 64 MHz) fXX/64 (1 s @ fXX = 64 MHz) The noise elimination function is valid only in the control mode (alternate function). User's Manual U16580EE3V1UD00 Chapter 20 (1) Port Functions Noise elimination control register (NRC) The NRC register is an 8-bit register that specifies the sampling clock that is used to eliminate digital noise of input pins. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Figure 20-82: After reset: NRC 00H Noise Elimination Control Register (NRC) (1/2) R/W Address: FFFFFtA0H 7 6 5 4 3 2 1 0 NRC7 NRC6 NRC5 NRC4 NRC3 NRC2 NRC1 NRC0 NRC7 Noise elimination clock setting for pin group 7Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) NRC6 Noise elimination clock setting for pin group 6Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) NRC5 Noise elimination clock setting for pin group 5Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) NRC4 Noise elimination clock setting for pin group 4Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) NRC3 Noise elimination clock setting for pin group 3Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) Note: Pin group 3: Pin group 4: Pin group 5: Pin group 6: Pin group 7: P10/TIP00/TEVTP1/TOP00, P11/TIP01/TTRGP1/TOP01, P12/TIP10/TTRGP0/TOP10, P13/TIP11/TEVTP0/TOP11 P14/TIP20/TEVTP3/TOP20, P15/TIP21/TTRGP3/TOP21, P16/TIP30/TTRGP2/TOP30, P17/TIP31/TEVTP2/TOP31 P20/TIP40/TEVTP5/TOP40, P21/TIP41/TTRGP5/TOP41, P22/TIP50/TTRGP4/TOP50, P23/TIP51/TEVTP4/TOP51 P24/TIP60/TEVTP7/TOP60, P25/TIP61/TTRGP7/TOP61, P26/TIP70/TTRGP6/TOP70, P27/TIP71/TEVTP6/TOP71 P60/TOR10/TTRGR1, P61/TOR11/TIR10, P62/TOR12/TIR11, P63/TOR13/TIR12, P64/TOR14/TIR13, P67/TOR17/TEVTR1 User's Manual U16580EE3V1UD00 967 Chapter 20 Figure 20-82: NRC2 Port Functions Noise Elimination Control Register (NRC) (2/2) Noise elimination clock setting for pin group 2Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) NRC1 Noise elimination clock setting for pin group 1Note 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) NRC0 Noise elimination clock setting for P00/NMI pin 0 fXX/16 (250 ns @ fXX = 64 MHz) 1 fXX/64 (1 s @ fXX = 64 MHz) Note: Pin group 1: (on PD70F31187) P03/INTP2/ADTRG0, P04/INTP3/ADTRG1, P30/RXDC0/INTP4, P32/RXDC1/INTP5, P83/SCS300/INTP6, P84/SCS301/INTP7, P85/SCS302/INTP8, P93/SCS310/INTP9, P94/SCS310/INTP10, P95/SCS310/INTP11 (on PD70F3447) P03/INTP2/ADTRG0, P04/INTP3/ADTRG1, P30/RXDC0/INTP4, P32/RXDC1/INTP5, P83/SCS300/INTP6, P84/SCS301/INTP7, P85/SCS302/INTP8, P93/INTP9, P94/INTP10,P95/INTP11 Pin group 2: (on PD70F31187) P100/TCLR0/TICC00/TOP81, P101/TCUD0/TICC01, P102/TIUD0/TO1, P70/TIT00/TEVTT1/TOT00, P71/TIT01/TTRGT1/TOT01, P72/TECRT0/INTP12, P73/TIT10/TTRGT0/TOT10, P74/TIT11/TEVTT0/TOT11, P75/TECRT1/AFO (on PD70F3447) P70/TIT00/TEVTT1/TOT00, P71/TIT01/TTRGT1/TOT01, P72/TECRT0/INTP12, P73/TIT10/TTRGT0/TOT10, P74/TIT11/TEVTT0/TOT11, P75/TECRT1/AFO Cautions: 1. If the input pulse lasts for the duration of 4 to 5 clocks, it is undefined whether the pulse is detected as a valid edge or eliminated as noise. So that the pulse is actually detected as a valid edge, the same pulse level must be input for the duration of 5 clocks or more. 2. If noise is generated in synchronization with the sampling clock, eliminate the noise by attaching a filter to the input pin. 3. Noise is not eliminated if the corresponding pin is used as normal input port pin. 968 User's Manual U16580EE3V1UD00 Chapter 20 Port Functions [MEMO] User's Manual U16580EE3V1UD00 969 Chapter 20 970 Port Functions User's Manual U16580EE3V1UD00 Chapter 21 Reset Function 21.1 Features * Reset function by RESET input * Forced reset function by DCU (refer to Chapter 23 page 977) * Reset generator (RG) eliminates noise from the RESET pin. "On-Chip Debug Function (OCD)" on 21.2 Configuration During a system reset, most pins (all except the DCK, DRST, DMS, DDI, DDO, RESET, X2, VDD10 to VDD15, VSS10 to VSS15, VDD30 to VDD37, VSS30 to VSS37, CVDD, CVSS, AVDD, AVREF0, AVREF1, AVSS0 and AVSS1 pins) enter the high-impedance state. Therefore, if an external device always requires a defined input level (e.g. external memory) a pull-up (or pull-down) resistor must be connected to each concerned output pin to prevent signal lines from floating. If no resistor is connected, the external device may be destroyed when these pins enter the high-impedance state. User's Manual U16580EE3V1UD00 971 Chapter 21 Reset Function 21.3 Operation When a low-level signal is input to the RESET pin, a system reset is effected and each on-chip hardware is initialized. When the RESET pin level changes from low to high, the oscillation stabilization time counter (OSTC) is started after analog delay by the reset generator. At that time the OSTC elapses, the PLL circuit will be enabled and the internal PLL stabilization time counter (PSTC) is started using the oscillator output clock (fX). After 214 oscillator clocks (fX) the PLL output clock becomes the system clock (fXX) and the internal system reset is released synchronously to the system clock. Figure 21-1: Reset Timing RESET System reset OSTC PSTC X1 (fX) PLL System clock (fXX) Analog delay Oscillation stabilization time PLL lock up time (214/ fX) CPU starts up Remarks: 1. If no clock is supplied to V850E/PH2 (i.e. the oscillator does not work) the internal system reset will not be released independently from input level of the external RESET pin. 2. The on-chip debug function can force the activation of the system reset independently from input level of the RESET pin. 972 User's Manual U16580EE3V1UD00 Chapter 22 Internal RAM Parity Check Function The V850E/PH2 microcontroller is provided with a parity check function for the internal RAM (iRAM). 22.1 Features * Maskable interrupt (INTPERR) on detection of parity error * Indication of internal RAM address of detected parity error * Indication of erroneous byte within 32-bit word 22.2 Operation Each byte of data stored in the internal RAM is checked by its parity bit. A maskable interrupt (INTPERR) is generated, if a parity mismatch is detected on iRAM read operation. In this case the address of the erroneous data is latched in the RAMPADD register and the erroneous byte(s) are indicated in the RAMERR register. Caution: Ensure that all internal RAM data is initialized on a word (32-bit) base by a write operation before first read access is made. It is important to initialize the whole memory word, even if only byte or half word is used. Otherwise a parity fail may be indicated mistakenly. User's Manual U16580EE3V1UD00 973 Chapter 22 Internal RAM Parity Check Function 22.3 Control Registers (1) Internal RAM parity error status register (RAMERR) The RAMERR register is an 8-bit register that reflects the parity error flags of the four bytes of one word (32 bits) in the internal RAM. The corresponding error flag (bits RAE0 to RAE3) is set and a maskable interrupt (INTPERR) is generated, if a parity error is detected during read access. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 22-1: After reset: RAMERR Internal RAM Parity Error Status Register (RAMERR) 00H R/W Address: 7 6 5 4 3 2 1 0 0 0 0 0 RAE3 RAE2 RAE1 RAE0 RAEn Internal RAM Parity Error Flag 0 No parity error detected in internal RAM. 1 Parity error detected in internal RAM for byte position n. Remark: 974 FFFFF4C0H n Bit Name Function 0 RAE0 Parity error caused by bits 0 to 7 1 RAE1 Parity error caused by bits 8 to 15 2 RAE2 Parity error caused by bits 16 to 23 3 RAE3 Parity error caused by bits 24 to 31 The RAEn bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. User's Manual U16580EE3V1UD00 Chapter 22 (2) Internal RAM Parity Check Function Internal RAM parity error address register (RAMPADD) The RAMPAD register is a 16-bit register that latches the internal RAM address causing the first parity error after hardware reset was released or RAMERR register was cleared. This register can be read or written in 16-bit units. Reset input clears this register to 8000H. Caution: Do not read the RAMPADD register, when all internal RAM parity error flags RAEn (n = 0 to 3) are cleared. If a parity error is detected and the RAMPADD register is read before the respective RAEn flag is set, the read value might be invalid. Figure 22-2: After reset: 8000H 15 RAMPADD 1 Internal RAM Parity Error Address Register (RAMPADD) 14 13 R/W 12 11 Address: 10 9 8 FFFFF4C2H 7 6 5 4 3 2 RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA RAMPA DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 RAMPAD14 to RAMPADD2 1 0 0 0 Internal RAM Parity Error Address Internal RAM address of the 32-bit word causing the parity error. Caution: Bit 15 of the RAMPADD register is always 1. This does not reflect the correct address bit 15 of the internal RAM, which starts at location FFF0000H. Remark: Bits 0 and 1 of the RAMPADD register are always 0, because the parity check function is aligned on 32-bit words. User's Manual U16580EE3V1UD00 975 Chapter 22 Internal RAM Parity Check Function [MEMO] 976 User's Manual U16580EE3V1UD00 Chapter 23 On-Chip Debug Function (OCD) An on-chip debug unit is provided in the V850E/PH2 microcontroller and realizes stand-alone on-chip debugging of the V850E/PH2 microcontroller by connecting a N-Wire type emulator. Caution: The debug function explained in this chapter is the function that can be realized by using the V850E/PH2 microcontroller, the NEC Electronics' IE-V850E1-CD-NW (N-Wire type emulator). When using a third-party N-Wire type emulator, refer to the manual for the debugger used. 23.1 Function Overview 23.1.1 On-chip debug unit type The on-chip debug unit incorporated in the V850E/PH2 microcontroller is RCU1 (run control unit 1). The on-chip unit incorporated differs depending on the microcontroller, and also features different functions. 23.1.2 Debug function For details of the debug function, refer to the corresponding debugger operation user's manual. (1) Debug interface This interface establishes communication with the host machine by using the DRST, DCK, DMS, DDI, and DDO signals, via a N-Wire type emulator. The communication specifications of N-Wire are used for this interface. It does not support a boundary scan function. (2) On-chip debug On-chip debugging can be performed by providing wiring and connectors for debugging on the target system. Connect a N-Wire type emulator to the emulator connector. (3) Forced reset function The V850E/PH2 can be forcibly reset. (4) Break reset function The CPU can be started in the debug mode immediately after resetting the CPU has been cleared. (5) Forced break function Execution of the user program can be forcibly stopped (however, the handler of the illegal instruction code exception (first address: 00000060H) cannot be used). (6) Hardware break function Two common instruction fetch/access breakpoints can be used. By using the instruction breakpoint, program execution can be suspended at an arbitrary address. By using the access breakpoint, program execution can be suspended by data-accessing an arbitrary address. User's Manual U16580EE3V1UD00 977 Chapter 23 (7) On-Chip Debug Function (OCD) Software break function In addition to the hardware break function, a software break function is available. Up to eight software breakpoints can be set in the internal ROM area. The number of software breakpoints that can be set in the internal RAM area differs depending on the debugger used. (8) Debug monitor function During debugging, a memory space for debugging that differs from the user memory space is used (background monitor format). The user program can be executed starting from any address. While execution of the user program is stopped, the user resources (such as memory and I/O) can be read or written, and the user program can be downloaded. (9) Mask function RESET, WAIT, NMI and all maskable interrupt request signals can be masked. (10) Timer function The execution time of the user program can be measured. 978 User's Manual U16580EE3V1UD00 Chapter 23 On-Chip Debug Function (OCD) 23.2 Connection with N-Wire Type Emulator To connect a N-Wire type emulator, it is necessary to mount an emulator connector and circuit for connection on the target system. Select either the KEL connector, MICTOR connector (Part number: 2-767004-2, distributor: Tyco Electronics AMP K.K.), or 2.54 mm pitch 20-pin general-purpose connector as the emulator connector. Connectors other than the KEL connector may not be supported, depending on the emulator, so when using a connector, refer to the manual of the emulator used. 23.2.1 KEL connector When the IE-V850E1-CD-NW is used, use of the following connector is recommended. Part number * 8830E-026-170S: Straight type * 8830E-026-170L: Right-angle type Figure 23-1: Connecting N-Wire Type Emulator (IE-V850E1-CD-NW (N-Wire Card)) Connector for emulator 8830E-026-170S IE-V850E1-CD-NW Host machine PCMCIA card slot Target system User's Manual U16580EE3V1UD00 979 Chapter 23 (1) On-Chip Debug Function (OCD) Pin configuration Figure 23-2 shows the pin configuration of the emulator connector (target system side), and Table 23-1 shows the pin functions. Figure 23-2: Pin Configuration of Emulator Connector (on Target System Side) Board edge B13 A13 B12 A12 B2 B1 A2 A1 (Top View) Caution: 980 Design the board based on the dimensions of the connector when actually mounting the connector on the board. User's Manual U16580EE3V1UD00 Chapter 23 On-Chip Debug Function (OCD) (2) Pin functions The following table shows the pin functions of the emulator connector (on the target system side). Table 23-1: Pin No. Pin Functions of Connector for IE-V850E1-CD-NW (on Target System Side) Pin Name I/O Pin Function A1 (Reserved 1) - (Connect to GND) A2 (Reserved 2) - (Connect to GND) A3 (Reserved 3) - (Connect to GND) A4 (Reserved 4) - (Connect to GND) A5 (Reserved 5) - (Connect to GND) A6 (Reserved 6) - (Connect to GND) A7 DDI Input Data input for N-Wire interface A8 DCK Input Clock input for N-Wire interface A9 DMS Input Transfer mode select input for N-Wire interface A10 DDO Output Data output for N-Wire interface A11 DRST Input On-chip debug unit reset input A12 (Reserved 7) - (Leave open) A13 FLMD0 Input Control signal for flash memory downloading B1 GND - - B2 GND - - B3 GND - - B4 GND - - B5 GND - - B6 GND - - B7 GND - - B8 GND - - B9 GND - - B10 GND - - B11 (Reserved 8) - (Connect to GND) B12 (Reserved 9) - (Connect to GND) B13 VDD - 3.3 V input (for monitoring power application to target) Cautions: 1. The processing of the pins not incorporated in the V850E/PH2 or unused pins depends on the emulator used. 2. The pattern on the target board must satisfy the following conditions. Remark: * Keep the pattern length to within 100 mm. * Shield the clock signal with GND. Input/output is as viewed from the device side. User's Manual U16580EE3V1UD00 981 Chapter 23 (3) On-Chip Debug Function (OCD) Recommended circuit example The following figure shows an example of the recommended circuit of the emulator connector (on the target system side). Figure 23-3: Example of Recommended Emulator Connection of V850E/PH2 3.3 V V850E/PH2 KEL connector 8830E-026-170S 4 x 4.7 k A1 A2 A3 A4 A5 A6 DDI DCK DMS DDO Note 4 DRST Note 1 Note 2 Note 1 22 Note 1 Note 1 (Open) Note 1 FLMD0 A7 A8 A9 A10 A11 A12 A13 (Reserved 1) (Reserved 2) (Reserved 3) (Reserved 4) (Reserved 5) (Reserved 6) DDI DCK DMS DDO DRST (Reserved 7) FLMD0 VDDNote 3 GND GND GND GND GND GND GND GND GND GND (Reserved 8) (Reserved 9) B13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 3.3 V B11 B12 50 k Notes: 1. Keep the pattern length to within 100 mm. 2. Shield the DCK signal with GND. 3. For detecting power supply to the target board. Connect to the N-Wire interface voltage. 4. When DRST pin is high level: On-chip debug mode When DRST pin is low level or open: Normal operation mode DRST pin is connected to VSS3 via an internal pull-down resistor Cautions: 1. The DDO signal is 3.3 V output, and the input level of the DDI, DCK, DMS, and DRST signals is TTL level. 2. A 3.3 V interface may not be supported, so a level shifter may be required by some N-Wire type emulators. Refer to the manual of the emulator used. Note that the IE-V850E1-CD-NW supports a 5 V interface. 982 User's Manual U16580EE3V1UD00 Chapter 23 On-Chip Debug Function (OCD) 23.3 Precautions <1> The flash memory of the device used in debugging is rewritten during debugging, so the number of flash memory rewrites cannot be guaranteed. Therefore, do not use the device used in debugging for a mass production product. <2> If a reset (RESET signal input from the target system or reset input by an internal reset source) occurs during RUN (program execution), the break function may malfunction. <3> Even if reset is masked by using the mask function, the I/O buffers (port pins, etc.) are set to the reset state when the RESET signal is input. <4> RESET signal input during a break is masked. User's Manual U16580EE3V1UD00 983 Chapter 23 On-Chip Debug Function (OCD) [MEMO] 984 User's Manual U16580EE3V1UD00 Chapter 24 Flash Memory The V850E/PH2 and has a 512 KB on-chip flash memory configured as 128 blocks of 4 KB block size. 24.1 Features * 4-byte/1-clock access (when instruction is fetched) * Capacity: - PD70F3481: 512 KB - PD70F3447: 384 KB * Block size: - PD70F3481: 128 blocks of 4 KB - PD70F3447: 96 blocks of 4 KB * Write voltage: Erase/write with single voltage * Rewriting method - Rewriting by communication with dedicated flash programmer via serial interface (on-board/offboard programming) - Rewriting flash memory by user program (self-programming) * 64 KB boot block cluster with write prohibit function supported (protection function) * Interrupts can be acknowledged during self programming. User's Manual U16580EE3V1UD00 985 Chapter 24 Flash Memory 24.2 Memory Configuration The internal flash memory area is divided into 4 KB blocks (128 blocks for PD70F3187, and 96 blocks for PD70F3447)and can be programmed/erased in block units. All the blocks can also be erased at once. Figure 24-1: Flash Memory Mapping of PD70F3187 FFF FFFFH FFF F000H FFF EFFFH FFF 8000H FFF 7FFFH FFF 0000H FFE FFFFH 0007 FFFFH On-chip peripheral I/O area (4 KB) Block 127 (4 KB) 0007 F000H 0007 EFFFH Use prohibited (28 KB) Block 126 (4 KB) 0007 E000H 0007 DFFFH Internal RAM area (32 KB) Block 125 (4 KB) 0007 D000H 0007 CFFFH Block 124 (4 KB) 0007 C000H 0007 BFFFH Block 123 (4 KB) 0007 B000H 0007 AFFFH Use prohibited Block 122 (4 KB) 0007 A000H 0007 9FFFH Block 121 (4 KB) 0007 9000H 0007 8FFFH 400 3FF 3FF 3FF 0000H FFFFH F000H EFFFH 0001 1000H 0001 0FFFH Block 16 (4 KB) On-chip peripheral I/O area mirror 0001 0000H 0000 FFFFH Block 15 (4 KB) Use prohibited 0000 F000H 0000 EFFFH 3FF 8000H 3FF 7FFFH Block 14 (4 KB) Internal RAM area mirror 0000 E000H 0000 DFFFH 3FF 0000H 3FE FFFFH Block 13 (4 KB) 0000 D000H 0000 CFFFH External memory area (47.9 MB) Note 100 0000H 0FF FFFFH 020 0000H 01F FFFFH 0000 4000H 0000 3FFFH Block 3 (4 KB) External memory area (14 MB) 0000 3000H 0000 2FFFH Block 2 (4 KB) 0000 2000H 0000 1FFFH Use prohibited 008 0000H 007 FFFFH Block 1 (4 KB) Internal flash memory area (512 KB) 0000 1000H 0000 0FFFH Block 0 (4 KB) 000 0000H 0000 0000H Note: Blocks 0 to 15 (64 KB): Boot block cluster 986 User's Manual U16580EE3V1UD00 Chapter 24 Figure 24-2: Flash Memory Flash Memory Mapping of PD70F3447 FFF FFFFH FFF F000H FFF EFFFH FFF 6000H FFF 5FFFH FFF 0000H FFE FFFFH 0005 FFFFH On-chip peripheral I/O area (4 KB) Block 95 (4 KB) 0005 F000H 0005 EFFFH Use prohibited (36 KB) Block 94 (4 KB) 0005 E000H 0005 DFFFH Internal RAM area (24 KB) Block 93 (4 KB) 0005 D000H 0005 CFFFH Block 92 (4 KB) 0005 C000H 0005 BFFFH Block 91 (4 KB) 0005 B000H 0005 AFFFH Use prohibited Block 90 (4 KB) 0005 A000H 0005 9FFFH Block 89 (4 KB) 0005 9000H 0005 8FFFH 400 3FF 3FF 3FF 0000H FFFFH F000H EFFFH 0001 1000H 0001 0FFFH Block 16 (4 KB) On-chip peripheral I/O area mirror 0001 0000H 0000 FFFFH Block 15 (4 KB) Use prohibited 0000 F000H 0000 EFFFH 3FF 6000H 3FF 5FFFH Block 14 (4 KB) Internal RAM area mirror 0000 E000H 0000 DFFFH 3FF 0000H 3FE FFFFH Block 13 (4 KB) 0000 D000H 0000 CFFFH External memory area (47.9 MB) Note 100 0000H 0FF FFFFH 020 0000H 01F FFFFH 0000 4000H 0000 3FFFH Block 3 (4 KB) External memory area (14 MB) 0000 3000H 0000 2FFFH Block 2 (4 KB) 0000 2000H 0000 1FFFH Use prohibited 006 0000H 005 FFFFH Block 1 (4 KB) Internal flash memory area (384 KB) 0000 1000H 0000 0FFFH Block 0 (4 KB) 000 0000H 0000 0000H Note: Blocks 0 to 15 (64 KB): Boot block cluster User's Manual U16580EE3V1UD00 987 Chapter 24 Flash Memory 24.3 Functional Outline The internal flash memory of the V850E/PH2 can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850E/PH2 has already been mounted on the target system or not (off-board/on-board programming). In addition, different functions are implemented to protect unwanted Flash access via the programmer interface and to protect the boot area from any unwanted modification The rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed or extended during or after production/shipment of the target system. Interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. Table 24-1: Rewrite Method Rewrite Method Functional Outline Off-board programming Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board. On-board programming Flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. Self-programming Flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on-board programming. (During self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. Therefore, the rewrite program must be transferred to the internal RAM or external memory in advance). parts of the self-programming program 988 User's Manual U16580EE3V1UD00 Operation Mode Flash memory programming mode Normal operation mode Chapter 24 Table 24-2: Function Flash Memory Basic Functions Functional Outline Support by On-Board/Off-Board Programming Self Programming Block erasure The contents of specified memory blocks are erased. yes yes Chip erasure The contents of the entire memory area are erased all at once. yes no Write Writing to specified addresses, and a verify check to see if write level is secured are performed. yes yes Verify/check sum Data read from the flash memory is compared with data transferred from the flash programmer. yes no (Can be read by user program) Blank check The erasure status of the entire memory is checked. yes yes Read The content of specified addresses can be read. yes yes Protection setting Setting of protection flags to prohibit programming interface commands (write, block erase, chip erase and read) and to prohibit boot block cluster modification via self-programming yes yes The following Table 24-3 lists the protection functions. After shipment no protection feature is set on the device. Furthermore, after chip erase by a dedicated programmer (PG-FP4) the protection is reset. Each protection function can be used in combination with the others at the same time. User's Manual U16580EE3V1UD00 989 Chapter 24 Table 24-3: Function Flash Memory Protection Functions Functional Outline Operation On-Board/Off-Board Programming Self-Programming Block erase command prohibit Execution of a block erase command on all blocks is prohibited. Setting of prohibition can be initialized by execution of a chip erase command. Block erase command: x Chip erase command: Program command: Chip erase command prohibit Execution of block erase and chip erase commands on all the blocks is prohibited. Once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. Block erase command: x Chip erase command: x Program command: Program command prohibit Write and block erase commands on all the blocks are prohibited. Setting of prohibition can be initialized by execution of the chip erase command. Block erase command: x Chip erase command: x Program command: Read command prohibit Read of memory content is prohibited. Read command: Remark: 990 x: Operation prohibited : Operation executable User's Manual U16580EE3V1UD00 x Can always be read or rewritten regardless of protection function setting Chapter 24 Flash Memory 24.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850E/PH2 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter. 24.4.1 Programming environment The following shows the environment required for writing programs to the flash memory of the V850E/PH2: Figure 24-3: Environment Required for Writing Programs to Flash Memory FLMD0 RS-232C FLMD1 XXXXXX XXXX STATUS PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx USB VSS1, VSS3 Dedicated flash programmer Host machine VDD1, VDD3 RESET V850E/PH2 UARTA0/CSIB0 A host machine is required for controlling the dedicated flash programmer. UARTC0 or CSIB0 is used for the interface between the dedicated flash programmer and the V850E/PH2 to perform writing, erasing, etc. A dedicated program adapter is required for off-board writing. User's Manual U16580EE3V1UD00 991 Chapter 24 Flash Memory 24.4.2 Communication mode Communication between the dedicated flash programmer and the V850E/PH2 is performed by serial communication using the UARTC0 or CSIB0 interfaces of the V850E/PH2. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 24-4: Communication with Dedicated Flash Programmer (UARTC0) XXXXXX XXXXX STATUS PG-FP4 (Flash Pro4) Dedicated flash programmer (2) FLMD0 FLMD1 FLMD1 VDD VDD3 VDD2 VDD1 XXXX Bxxxxx Cxxxxxx XXX YYY XXXX YYYY Axxxx FLMD0 GND VSS1, VSS3 RESET RESET RxD TXDC0 TxD RXDC0 V850E/PH2 CSIB0 Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 24-5: Communication with Dedicated Flash Programmer (CSIB0) FLMD0 FLMD1 FLMD1 VDD VDD3 VDD2 VDD1 XXXXXX XXXX Bxxxxx Cxxxxxx STATUS PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx FLMD0 GND Dedicated flash programmer RESET RESET SI SOB0 SO SIB0 SCK 992 VSS1, VSS3 SCKB0 User's Manual U16580EE3V1UD00 V850E/PH2 Chapter 24 CSIB0 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 24-6: Communication with Dedicated Flash Programmer (CSIB0 + HS) XXXXXX FLMD0 FLMD1 FLMD1 VDD VDD3 VDD2 VDD1 XXXX Bxxxxx FLMD0 Cxxxxxx STATUS PG-FP4 (Flash Pro4) XXXXX XXXX YYYY Axxxx XXX YYY (3) Flash Memory Dedicated flash programmer GND RESET VSS1, VSS3 RESET SI SOB0 SO SIB0 SCK HS V850E/PH2 SCKB0 PCM0 The dedicated flash programmer outputs the transfer clock, and the V850E/PH2 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850E/PH2. For details, refer to the PG-FP4 User's Manual (U15260E). User's Manual U16580EE3V1UD00 993 Chapter 24 Table 24-4: Signal Connections of Dedicated Flash Programmer (PG-FP4) PG-FP4 Signal Name Flash Memory I/O V850E/PH2 Pin Function Pin Name Processing for Connection UARTC0 CSIB0 CSIB0 + HS FLMD0 Output Write enable/disable FLMD0 FLMD1 Output Write enable/disable FLMD1 Note 1 Note 1 Note 1 VDD - VDD voltage generation/ Voltage monitor VDD3x Note 2 Note 2 Note 2 VDD2 - VDD2 voltage generation VDD1x x Note 3 x Note 2 x Note 2 GND - Ground VSS1x, VSS3x CLK Output Clock output X1, X2 x Note 4 x Note 3 x Note 3 RESET Output Reset signal RESET SI/RXD Input Receive signal SIB0/RXDC0 SO/TXD Output Transmit signal SOB0/TXDC0 SCK Output Transfer clock SCKB0 x Handshake signal PCM0 x x HS Input Notes: 1. Connect to GND via pull-down resistor. 2. Connect these pins to supply power from the PG-FP4. When power is supplied externally to the target board, the voltage is monitored by PG-FP4. 3. Connect these pins to supply power from the PG-FP4, or supply power externally to the target board. 4. Clock supply is provided by an oscillator on the target board. Clock supply from PG-FP4 is not supported for V850E/PH2. Remark: 994 : Must be connected. x: Do not need to be connected. User's Manual U16580EE3V1UD00 Chapter 24 Flash Memory 24.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 24-7: Procedure for Manipulating Flash Memory Start Supplies FLMD0 pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End? No Yes End User's Manual U16580EE3V1UD00 995 Chapter 24 Flash Memory 24.4.4 Selection of communication mode In the V850E/PH2, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 24-8: Selection of Communication Mode VDD1 ,VDD3 VDD1x ,VDD3x VSS1 ,VSS3 VDD3 RESET (input) VSS3 VDD3 FLMD1 (input) VSS3 VDD3 FLMD0 (input) VSS3 (Note) VDD3 RXDA0 (input) VSS3 VDD3 TXDA0 (output) VSS3 Power on Reset Oscillation released stabilized Communication mode selected Flash control command communication (erasure, write, etc.) Note: The number of clocks is as follows depending on the communication mode. Number of FLMD0 Pulses Communication Mode 0 UARTC0 8 CSIB0 11 CSIB0 + HS Others RFU Caution: 996 Remarks Communication rate: 9,600 bps (after reset), LSB first V850E/PH2 performs slave operation, MSB first Setting prohibited When UARTC0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse. User's Manual U16580EE3V1UD00 Chapter 24 Flash Memory 24.4.5 Communication commands The V850E/PH2 communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850E/PH2 are called "commands". The response signals sent from the V850E/PH2 to the dedicated flash programmer are called "response commands". Figure 24-9: Communication Commands Command XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx Response command Dedicated flash programmer V850E/PH2 The following shows the commands for flash memory control in the V850E/PH2. All of these commands are issued from the dedicated flash programmer, and the V850E/PH2 performs the processing corresponding to the commands. Table 24-5: Classification Communication Commands Command Name Support Function UARTC0 CSI0 CSI0 + HS Blank check Block blank check command Checks if the contents of the memory in the specified block have been correctly erased. Erase Chip erase command Erases the contents of the entire memory. Block erase command Erases the contents of the memory of the specified block. Write Write command Writes the specified address range, and executes a contents verify check. Verify Verify command Compares the contents of memory in the specified address range with data transferred from the flash programmer. Checksum command Reads the checksum in the specified address range. Read Read command Reads the specified address range. System setting, control Silicon signature command Reads silicon signature information. protection setting command Disables the chip erase command, enables the block erase command, and disables the write command. Remark: x: Operation not supported : Operation supported User's Manual U16580EE3V1UD00 997 Chapter 24 Flash Memory 24.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) FLMD0 pin In the normal operation mode, input a voltage of VSS3 level to the FLMD0 pin. In the flash memory programming mode, supply a write voltage of VDD3 level to the FLMD0 pin. Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD3 level must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, refer to the self-programming application note (U16929E). Figure 24-10: FLMD0 Pin Connection Example V850E/PH2 Dedicated flash programmer connection pin FLMD0 Pull-down resistor (RFLMD0) 998 User's Manual U16580EE3V1UD00 Chapter 24 (2) Flash Memory FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD3 is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 24-11: FLMD1 Pin Connection Example V850E/PH2 FLMD1 Other device Pull-down resistor (RFLMD1) Caution: If the VDD3 signal is input to the FLMD1 pin from another device during on-board writing and immediately after reset, isolate this signal. Table 24-6: Relationship Between FLMD0 and FLMD1 Pins and Operation Mode when Reset is Released FLMD0 FLMD1 0 Don't care VDD3 0 VDD3 VDD3 Operation Mode Normal operation mode Flash memory programming mode Setting prohibited User's Manual U16580EE3V1UD00 999 Chapter 24 (3) Flash Memory Serial interface pin The following shows the pins used by each serial interface. Table 24-7: Pins Used by Serial Interfaces Serial Interface UARTC0 CSIB0 CSIB0 + HS Used Pins TXDC0, RXDC0 SOB0, SIB0, SCKB0 SOB0, SIB0, SCKB0, PCM0 When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) Conflict of signals When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 24-12: Conflict of Signals (Serial Interface Input Pin) V850E/PH2 Conflict of signals Dedicated flash programmer connection pins Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side. 1000 User's Manual U16580EE3V1UD00 Chapter 24 Flash Memory (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 24-13: Malfunction of Other Device V850E/PH2 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the V850E/PH2 outputs affects the other device, isolate the signal on the other device side. V850E/PH2 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. User's Manual U16580EE3V1UD00 1001 Chapter 24 (4) Flash Memory RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 24-14: Conflict of Signals (RESET Pin) V850E/PH2 Conflict of signals Dedicated flash programmer connection pin RESET Reset signal generator Output pin In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side. (5) Port pins (including NMI) When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD3 via a resistor or connecting to VSS3 via a resistor. (6) Other signal pins Connect X1 and X2 in the same status as that in the normal operation mode. During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level. (7) Power supply Supply the same power (VDD1, VSS1, VDD3, VSS3, CVDD, CVSS, AVDD, AVSS, AVREF0, AVREF1) as in normal operation mode. 1002 User's Manual U16580EE3V1UD00 Chapter 24 Flash Memory 24.5 Rewriting by Self Programming 24.5.1 Overview The V850E/PH2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self-programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the field. Figure 24-15: Concept of Self Programming Application program Self programming library Flash function execution Flash information Flash macro service Erase, write Flash memory For further details, refer to the self-programming application note (U16929E). User's Manual U16580EE3V1UD00 1003 Chapter 24 Flash Memory 24.5.2 Features (1) Secure self-programming (boot swap function) The V850E/PH2 supports a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. By writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because a correct user program always exists in blocks 0 to 15. Since a program flow into and out of the 2nd boot block cluster (physical addresses: 10000H to 1FFFFH) is prohibited, the boot block swap has to be done twice. With this second swap the logical address will be relocated to the physical address. For further information refer to the application note "Self-Programming Library for embedded Single Voltage FLASH (U16929EE)". Caution: 1004 Program flow into and out of the 2nd boot block cluster (physical addresses 10000H to 1FFFH) is prohibited. Thus, when boot swap function is used, the boot block cluster has to be swapped twice. The user application has to ensure that the second swap will be performed even if the process was interrupted after the first swap. Therefore a dedicated mechanism has to be provided by the user application to check the boot swap status, e.g. by a signature. User's Manual U16580EE3V1UD00 Chapter 24 Figure 24-16: Flash Memory Rewriting Entire Memory Area (Boot Swap) Block m Block m Block 32 Block 32 Block 31 Block 32 Block 31 Block 16 Block 16 Block 16 Block 15 Block 15 Block 15 Block 0 Block 0 Block 0 Block m Block m Rewriting blocks 16 to 31 (2nd time overwrites origin boot block) (2) st 1 Boot swap Block 31 Rewriting blocks 16 to 31 Block 32 Remark: Block m nd 2 Boot swap Block 32 Block 31 Block 31 Block 16 Block 16 Block 15 Block 15 Block 0 Block 0 m = 127 for PD70F3187 m = 95 for PD70F3447 Interrupt support Instructions cannot be fetched from the flash memory during self programming. Conventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. With the V850E/PH2, a user handler can be registered to an entry RAM area by using a library function, so that interrupt servicing can be performed by internal RAM or external memory execution. User's Manual U16580EE3V1UD00 1005 Chapter 24 Flash Memory [MEMO] 1006 User's Manual U16580EE3V1UD00 Chapter 25 Electrical Specifications 25.1 Absolute Maximum Ratings Table 25-1: (TA = 25C, VSS1 Note 1 Parameter Supply voltage Absolute Maximum Ratings = 0 V) Ratings Unit VDD1 Symbol Note 2 Conditions -0.5 to +2.0 V VDD3 Note 4 -0.5 to +4.6 V -0.5 to +2.0 V CVDD AVDD VDD3 - 0.5 V < AVDD < VDD3 + 0.5 V -0.5 to +4.6 V VSS1 Note 1 -0.5 to +0.5 V VSS3 Note 3 -0.5 to +0.5 V -0.5 to +0.5 V CVSS AVSS Note 5 -0.5 to +0.5 V VI1 All pins except X1 pin, ANI00 to ANI19 pins VI1 < VDD3 + 0.3 V -0.5 to +4.6 V VI2 X1 pin VI2 < CVDD + 0.5 V -0.5 to +2.0 V Analog input voltage VIAN ANI00 to ANI19 pins AVDD = 3.0 V to 3.6 V -0.3 to AVDD + 0.3 V Analog reference input voltage AVREF0, AVREF1 -0.3 to AVDD + 0.3 V Output current, low IOL 4.0 mA Output current, high IOH Operating temperature TA Input voltage Per pin Total of all pins 100 mA Per pin -4.0 mA Total of all pins Storage temperature -100 mA PD70F3187 -40 to +85 C PD70F3187(A1) -40 to +110 C PD70F3187(A2) -40 to +125 C -65 to +150 C Tstg Notes: 1. VSS1 applied to VSS10 to VSS15 pins. 2. VDD1 applied to VDD10 to VDD15 pins. 3. VSS3 applied to VSS30 to VSS37 pins. 4. VDD3 applied to VDD30 to VDD37 pins. 5. AVSS applied to AVSS0 to AVSS1 pins. Cautions: 1. Do not directly connect output (or I/O) pins of IC products to each other, or to VDD, VSS, and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance. User's Manual U16580EE3V1UD00 1007 Chapter 25 Electrical Specifications 25.2 General Characteristics Unless specified otherwise, the following conditions are assumed for all characteristics in this chapter. VDD3x = AVDD = 3.0 V to 3.6 V VDD1x = CVDD = 1.35 V to 1.65 V VSS1x = CVSS = VSS3x = AVSSx = 0 V PD70F3187: TA = -40 C to +85 C PD70F3187(A1): TA = -40 C to +110 C PD70F3187(A2): TA = -40 C to +125 C 25.2.1 Capacitance Table 25-2: Capacitance (TA = 25C, VDD1x = CVDD = VDD3x = AVDD = VSS1x = CVSS = VSS3x = AVSSx = 0 V) Parameter Symbol Input capacitance CI Output capacitance CO I/O capacitance CIO Conditions MIN. TYP. fC = 1 MHz Un-measured pins returned to 0 V. MAX. Unit 15 pF 15 pF 15 pF MAX. Unit 25.2.2 Operating conditions Table 25-3: Parameter Internal system clock frequency 1008 Symbol fXX Operating Conditions Conditions MIN. fOSC = 16 MHz User's Manual U16580EE3V1UD00 TYP. 64 MHz Chapter 25 Electrical Specifications 25.2.3 Oscillator characteristics Figure 25-1: Oscillator Recommendations X1 X2 R' Qu C1' Remark: C2' Values of capacitors C1', C2' and R' depend on used crystal or resonator and must be specified in cooperation with the manufacturer. Cautions: 1. External clock input is prohibited. 2. Wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as CVSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Table 25-4: Parameter Symbol Oscillation frequency fOSC Oscillation stabilization time tOST Oscillator Characteristics Conditions MIN. TYP. MAX. 16 fOSC = 16 MHz User's Manual U16580EE3V1UD00 Unit MHz 4.096 ms 1009 Chapter 25 Electrical Specifications 25.3 DC Characteristics Unless specified otherwise, the following conditions are assumed for all characteristics in this chapter. VDD3x = AVDD = 3.0 V to 3.6 V VDD1x = CVDD = 1.35 V to 1.65 V VSS1x = CVSS = VSS3x = AVSSx = 0 V PD70F3187: TA = -40 C to +85 C PD70F3187(A1): TA = -40 C to +110 C PD70F3187(A2): TA = -40 C to +125 C Table 25-5: Parameter Input voltage, high Symbol DC Characteristics Conditions MIN. MAX. Unit 0.7 VDD3 VDD3 + 0.3 V -0.5 0.3 VDD3 V VIH1 PAL0 to PAL15, PAH0 to PAH5, PDL0 to PDL15, PDH0 to PDH15, PCS0, PCS1, PCS3, PCS4, PCD2 to PCD5, PCT4, PCT5, PCM0, PCM1, PCM6, PCM7, DCK, DMS, DDI, DDO VIH3 P00 to P04, P10 to P17, P20 to P27, P30 to P37, P40 to P45, P50 to P57, P60 to P67, P70 to P75, P80 to P86, P90 to P96, P100 to P102, RESET, MODE0 to MODE2, DRST VIL1 PAL0 to PAL15, PAH0 to PAH5, PDL0 to PDL15, PDH0 to PDH15, PCS0, PCS1, PCS3, PCS4, PCD2 to PCD5, PCT4, PCT5, PCM0, PCM1, PCM6, PCM7, DCK, DMS, DDI, DDO VIL3 P00 to P04, P10 to P17, P20 to P27, P30 to P37, P40 to P45, P50 to P57, P60 to P67, P70 to P75, P80 to P86, P90 to P96, P100 to P102, RESET, MODE0 to MODE2, DRST Output voltage, high VOH1 IOH = -2.5 mA VDD3 - 1.0 IOH = -100 A VDD3 - 0.4 Output voltage, low VOL1 Input voltage, low TYP. V V IOL = 2.5 mA 0.8 V IOL = 100 A 0.4 V VIH = VDD3, Note 1 10 A VIH = AVDD, Note 2 3 A VIL = 0 V, Note 1 -10 A VIL = 0 V, Note 2 -3 A Input leakage current, high ILIH Input leakage current, low ILIL Power supply current IDD1 VDD1 + CVDD 200 mA IDD3 VDD3, Note 3 50 mA Notes: 1. Pins other than analog input pins ANI00 to ANI19 2. Analog input pins ANI00 to ANI19 3. No external loads considered (CL = 0pF). External loads cause additional pin currents. Pin current for each pin can be calculated according to following formula: I[A] = 3.63 x CL [pF] x F [MHz] where CL is external load capacitance and F is the average pin toggle frequency. Load dependent pin currents must be summed up and added to IDD3. 1010 User's Manual U16580EE3V1UD00 Chapter 25 Electrical Specifications 25.4 AC Characteristics Unless specified otherwise, the following conditions are assumed for all characteristics in this chapter. VDD3x = AVDD = 3.0 V to 3.6 V VDD1x = CVDD = 1.35 V to 1.65 V VSS1x = CVSS = VSS3x = AVSSx = 0 V PD70F3187: TA = -40 C to +85 C PD70F3187(A1): TA = -40 C to +110 C PD70F3187(A2): TA = -40 C to +125 C Output pin load capacitance: CL = 35 pF Figure 25-2: AC Test Input/Output Waveform Test Points VDD5x 0.8 VDD5x 0.2 VDD5x 0V Test Points VDD3x 0.8 VDD3x 0.2 VDD3x 0V Figure 25-3: AC Test Load Condition DUT Load on test CL = 50 pF User's Manual U16580EE3V1UD00 1011 Chapter 25 Electrical Specifications 25.4.1 External asynchronous memory access read timing Table 25-6: External Asynchronous Memory Access Read Timing Parameter Symbol Data input set up time (vs. address) <10> MIN. MAX. Unit tSAID (2 + wAS + wD + w) T - 30 ns (1.5 + wD + w) T - 30 ns Data input set up time (vs. RD) <11> tSRDID RD Low level width <12> tWRDL (1.5 + wD + w) T - 15 ns RD High level width <13> tWRDH (0.5 + wAS + i) T - 15 ns Address, CSn RD delay time <14> tDARD (0.5 + wAS) T - 20 ns RD address delay time <15> tDRDA iT - 2 ns Data input hold time (vs. RD) <16> tHRDID 0 ns RD data output delay time <17> tDRDOD (1 + i) T - 15 ns WAIT set up time (vs. address) < 31 > tSAW WAIT high level width <32> tWWH Remarks: 1. T: 2. i: (1 + wAS) T- 30 T-2 2/fXX Number of idle states specified by BCC register 3. wAS: Number of waits specified by ASC register 4. wD: Number of waits specified by DWC1, DWC2 register; wD 1 5. w: Number of waits due to external wait signal (WAIT) 6. n = 0, 1, 3, 4 1012 User's Manual U16580EE3V1UD00 ns ns Chapter 25 Figure 25-4: Electrical Specifications External Asynchronous Memory Access Read Timing A0 to A21 (output) CSn BEN0 to BEN3 (output) WR <13> <12> <15> RD (output) <14> <11> <17> <16> <10> D0 to D31 (in/out) <31> <32> WAIT (input) User's Manual U16580EE3V1UD00 1013 Chapter 25 Electrical Specifications 25.4.2 External asynchronous memory access write timing Table 25-7: External Asynchronous Memory Access Write Timing Parameter Symbol MIN. MAX. Unit Address, CSn WR delay time <20> TDAWR (1 + wAS)T - 20 ns Address set up (vs. WR) <21> TSAWR (1.5 + wAS + wD + w) T - 10 ns WR address delay time <22> TDWRA (0.5 + i) T - 5 ns WR High level width <23> TWWRH (1.5 + i + wAS) T - 15 ns WR Low level width <24> TWWRL (0.5 + w + wD) T - 12 ns Data output set up time (vs. WR) <25> TSODWR (0.5 + wAS + wD + w) T - 15 ns Data output hold time (vs. WR) <26> THWROD ns WAIT set up time (vs. address) <31> TSAW WAIT high level width <32> TWWH Remarks: 1. T: 2. i: (0.5 + i) T - 15 (1 + wAS)T - 30 T-2 2/fXX Number of idle states specified by BCC register 3. wAS: Number of waits specified by ASC register 4. wD: Number of waits specified by DWC1, DWC2 register; wD 1 5. w: Number of waits due to external wait signal (WAIT) 6. n = 0, 1, 3, 4 1014 User's Manual U16580EE3V1UD00 ns ns Chapter 25 Figure 25-5: A0 to A21 CSn RD Electrical Specifications External Asynchronous Memory Access Write Timing (output) (output) <21> <20> <23> BEN0 to BEN3 <22> <24> (output) WR <25> <26> D0 to D31 (in/output) write write D0 to D31 (in/output) read write <31> WAIT <32> (input) User's Manual U16580EE3V1UD00 1015 Chapter 25 Electrical Specifications 25.4.3 Reset Timing (Power Up/Down Sequence) Table 25-8: Parameter Reset Timing Symbol MIN. RESET high-level width tWRSH 500 ns RESET low-level width tWRSL 500 ns VDD3x VDD1x power up delay tDVR 0 ns VDD3x VDD1x power down delay tDVF 0 ns RESET hold time tDVRR 1 s RESET setup time tDVRF 0 ns Figure 25-6: tWRSH MAX. Unit Reset Timing tWRSL RESET VDD3 VDD3 VDD1 VDD1 RESET t DVR Caution: 1016 t DVRR t DVRF tDVF Ensure that a valid RESET signal (low active) is applied to the RESET pin at any time if the voltage power of VDD1x is below its operating condition range. User's Manual U16580EE3V1UD00 Chapter 25 Electrical Specifications 25.4.4 Interrupt timing Table 25-9: Parameter NMI high-level width NMI low-level width INTPx high-level width INTPx low-level width Interrupt Timing Symbol Condition MIN. tWNIH NRC0 bit = 0 96 T + 10 ns NRC0 bit = 1 384 T + 10 ns NRC0 bit = 0 96 T + 10 ns NRC0 bit = 1 384 T + 10 ns NRC1 bit = 0 96 T + 10 ns NRC1 bit = 1 384 T + 10 ns NRC1 bit = 0 96 T + 10 ns NRC1 bit = 1 384 T + 10 ns tWNIL tWITH tWITL MAX. Unit INTP0, INTP1 high-level width tWTIH 500 ns INTP0, INTP1 low-level width tWTIL 500 ns Figure 25-7: Interrupt Timing t WNIH t WNIL t WITH t WITL NMI INTPx, INTPi User's Manual U16580EE3V1UD00 1017 Chapter 25 Electrical Specifications 25.5 Peripheral Characteristics Unless specified otherwise, the following conditions are assumed for all characteristics in this chapter. VDD3x = AVDD = 3.0 V to 3.6 V VDD1x = CVDD = 1.35 V to 1.65 V VSS1x = CVSS = VSS3x = AVSSx = 0 V PD70F3187: TA = -40 C to +85 C PD70F3187(A1): TA = -40 C to +110 C PD70F3187(A2): TA = -40 C to +125 C 25.5.1 Timer characteristics Table 25-10: Parameter TIPmn input high-level width TIPmn input low-level width Timer P Characteristics Symbol Condition MIN. tWTIPH NRCx bit = 0 96 T + 10 ns NRCx bit = 1 384 T + 10 ns NRCx bit = 0 96 T + 10 ns NRCx bit = 1 384 T + 10 ns tWTIPL Figure 25-8: t WTIPH MAX. Unit Timer P Characteristics t WTIPL TIPmn Remark: 1018 m = 0 to 7 n = 0 to 1 x = 3 to 6 (depending on the pin group the TIPmn belongs to, refer to 20.4 "Noise Elimination" on page 965). User's Manual U16580EE3V1UD00 Parameter TIR1n input high-level width TIR1n input low-level width TORmx to TORmy output delay Chapter 25 Electrical Specifications Table 25-11: Timer R Characteristics Symbol Condition MIN. tWTIRH NRC7 bit = 0 96 T + 10 ns NRC7 bit = 1 384 T + 10 ns NRC7 bit = 0 96 T + 10 ns NRC7 bit = 1 384 T + 10 ns tWTIRL tDTORTOR MAX. 15 Figure 25-9: Unit ns Timer R Characteristics t WTIRH t WTIRL t DTORTOR t DTORTOR TIRmn TORmx TORmy Remark: m = 0, 1 n = 0 to 3 x = 0 to 7, y = 0 to 7, x y User's Manual U16580EE3V1UD00 1019 Chapter 25 Electrical Specifications Table 25-12: Parameter TITmn input high-level width TITmn input low-level width Timer T Characteristics Symbol Condition MIN. tWTITH NRC2 bit = 0 96 T + 10 ns NRC2 bit = 1 384 T + 10 ns NRC2 bit = 0 96 T + 10 ns NRC2 bit = 1 384 T + 10 ns tWTITL Figure 25-10: t WTIPH Timer T Characteristics t WTIPL TIPmn Remark: 1020 m = 0, 1 n = 0, 1 User's Manual U16580EE3V1UD00 MAX. Unit Chapter 25 Electrical Specifications 25.5.2 Serial interface characteristics (1) Clocked serial interface B (CSIB) characteristics Table 25-13: CSIB Characteristics (Master Mode) CBnSCK2 to CBnSCK0 111B Parameter Symbol MIN. SCKBn output clock cycle time tCYSKM 125 ns SCKBn output high level width tWSKHM 0.5 tCYSKM - 10 ns SCKBn output low level width tWSKLM 0.5 tCYSKM - 10 ns SIBn input setup time (vs. SCKBn) tSSISKM 20 ns SIBn input hold time (vs. SCKBn) tHSKSIM 10 ns SOBn output delay (vs. SCKBn) tDSKSOM SOBn output hold time (vs. SCKBn) tHSKSOM Table 25-14: MAX. 10 0.5 tCYSKM - 10 Unit ns ns CSIB Characteristics (Slave Mode) CBnSCK2 to CBnSCK0 = 111B Parameter Symbol MIN. SCKBn input clock cycle time tCYSKS 125 ns SCKBn input high level width tWSKHS 0.5 tCYSKS - 10 ns SCKBn input low level width tWSKLS 0.5 tCYSKS - 10 ns SIBn input setup time (vs. SCKBn) tSSISKS 5 ns SIBn input hold time (vs. SCKBn) tHSKSIS 10 ns SOBn output delay (vs. SCKBn) tDSKSOS SOBn output hold time (vs. SCKBn) tHSKSOS Remark: MAX. 25 0.5 tCYSKS - 10 Unit ns ns n = 0, 1 User's Manual U16580EE3V1UD00 1021 Chapter 25 Electrical Specifications Figure 25-11: CSIB Timing in Master Mode (CKP, DAP bits = 00B or 11B) tCYSKM tWSKLM tWSKHM SCKBn tDSKSOM tHSKSOM SOBn tSSISKM tHSKSIM SIBn Figure 25-12: CSIB Timing in Master Mode (CKP, DAP bits = 01B or 10B) tCYSKM tWSKHM tWSKLM SCKBn tDSKSOM tHSKSOM SOBn tSSISKM tHSKSIM SIBn 1022 User's Manual U16580EE3V1UD00 Chapter 25 Figure 25-13: Electrical Specifications CSIB Timing in Slave Mode (CKP, DAP bits = 00B or 11B) tCYSKS tWSKLS tWSKHS SCKBn tDSKSOS tHSKSOS SOBn tSSISKS tHSKSIS SIBn Figure 25-14: CSIB Timing in Slave Mode (CKP, DAP bits = 01B or 10B) tCYSKS tWSKHS tWSKLS SCKBn tDSKSOS tHSKSOS SOBn tSSISKS tHSKSIS SIBn User's Manual U16580EE3V1UD00 1023 Chapter 25 Electrical Specifications (2) Clocked serial interface 3 (CSI3) timing Table 25-15: CSI3 Characteristics (Master Mode) CKS3n2 to CKS3n0 111B Parameter Symbol MIN. MAX. Unit 15.625 ns tCYSKM 125 ns SCK3n high level width tWSKHM 0.5 tCYSKM - 10 ns SCK3n low level width tWSKLM 0.5 tCYSKM - 10 ns SI3n setup time (vs. SCK3n) tSSISKM 20 ns SI3n hold time (vs. SCK3n) tHSKSIM 10 ns SO3n output delay (vs. SCK3n) tDSKSOM SO3n output hold time (vs. SCK3n) tHSKSOM 0.5 tCYSKM - 10 ns SCS3nm inactive width tWSKCSB 0.5 tCYSKM - 10 ns SCS3nm setup time (vs. SCK3n) tSCSZCK0 tCYK - 10 ns tSCSZCK1 tCYSKM + tCYK - 10 ns tSCSZCK2 tCYSKM - tCYK - 10 ns tHSKCSZ0 tCYK - 10 ns tHSKCSZ1 0.5 tCYSKM - 10 ns CSI3 operation clock cycle time tCYK SCK3n clock cycle time SCS3nm hold time (vs. SCK3n) Table 25-16: 10 ns CSI3 Characteristics (Slave Mode) CKS3n2 to CKS3n0 = 111B Parameter Symbol MIN. MAX. Unit 15.625 ns tCYSKS 125 ns SCK3n high level width tWSKHS 0.5 tCYSKS - 10 ns SCK3n low level width tWSKLS 0.5 tCYSKS - 10 ns SI3n setup time (vs. SCK3n) tSSISKS 5 ns SI3n hold time (vs. SCK3n) tHSKSIS 1.5 tCYK + 10 ns SO3n output delay (vs. SCK3n) tDSKSOS SO3n output hold time (vs. SCK3n) tHSKSOS CSI3 operation clock cycle time tCYK SCK3n clock cycle time Remark: 1024 25 0.5 tCYSKS - 10 n = 0, 1 m = 0 to 3 User's Manual U16580EE3V1UD00 ns ns Chapter 25 Figure 25-15: Electrical Specifications CSI3 Timing in Master Mode (CKP, DAP bits = 00B or 11B) tCYK Clock tCYSKM tWSKLM tWSKHM SCK3n tDSKSOM tHSKSOM SO3n tSSISKM tHSKSIM SI3n Figure 25-16: CSI3 Timing in Master Mode (CKP, DAP bits = 01B or 10B) tCYK Clock tCYSKM tWSKHM tWSKLM SCK3n tDSKSOM tHSKSOM SO3n tSSISKM tHSKSIM SI3n User's Manual U16580EE3V1UD00 1025 Chapter 25 Electrical Specifications Figure 25-17: CSI3 Timing in Slave Mode (CKP, DAP bits = 00B or 11B) tCYK Clock tCYSKS tWSKLS tWSKHS SCK3n tDSKSOS tHSKSOS SO3n tSSISKS tHSKSIS SI3n Figure 25-18: CSI3 Timing in Slave Mode (CKP, DAP bits = 01B or 10B) tCYK Clock tCYSKS tWSKHS tWSKLS SCK3n tDSKSOS tHSKSOS SO3n tSSISKS tHSKSIS SI3n 1026 User's Manual U16580EE3V1UD00 Chapter 25 Figure 25-19: Electrical Specifications CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 0, CSMD = 0) Continous transmission start (SO3n output timing) SCK3n tHSKCSZ0 tSCSZCK0 SCS3n0 to SCS3n3 INTCSI3n Figure 25-20: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 0) Continous transmission start (SO3n output timing) SCK3n tHSKCSZ0 tSCSZCK1 SCS3n0 to SCS3n3 INTCSI3n User's Manual U16580EE3V1UD00 1027 Chapter 25 Electrical Specifications Figure 25-21: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 1) Continous transmission start (SO3n output timing) SCK3n tHSKCSZ0 tWSKCSB tSCSZCK0 SCS3n0 to SCS3n3 INTCSI3n Figure 25-22: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 0, CSMD = 0) Continous transmission start (SO3n output timing) SCK3n tHSKCSZ1 SCS3n0 to SCS3n3 INTCSI3n 1028 User's Manual U16580EE3V1UD00 tSCSZCK0 Chapter 25 Figure 25-23: Electrical Specifications CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 0) Continous transmission start (SO3n output timing) SCK3n tHSKCSZ1 tSCSZCK1 SCS3n0 to SCS3n3 INTCSI3n Figure 25-24: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 1) Continous transmission start (SO3n output timing) SCK3n tHSKCSZ1 tWSKCSB tSCSZCK2 SCS3n0 to SCS3n3 INTCSI3n User's Manual U16580EE3V1UD00 1029 Chapter 25 Electrical Specifications 25.5.3 A/D Converter Characteristics Table 25-17: A/D Converter Characteristics Parameter Symbol Resolution - Overall error - MIN. TYP. MAX. Unit 10 Bit 4 LSB Conversion time TCONV 2 8 s Sampling time TSAM 0.375 1.5 s Analog input voltage VIAN AVSS AVDD V Analog supply current IAVDD 2.4 mA Reference voltage AVREF AVDD V Figure 25-25: AVDD Equivalent Circuit of Analog Inputs R1 R2 ANInm C1 Remark: C2 n = 0, 1 m = 0 to 9 Table 25-18: Parameter Equivalent circuit parameters 1030 C3 Analog Input Characteristics Symbol MIN. TYP. MAX. Unit R1 600 R2 160 C1 15 pF C2 3.5 pF C3 5.8 pF User's Manual U16580EE3V1UD00 Chapter 25 Electrical Specifications 25.6 Flash Programming Characteristics Unless specified otherwise, the following conditions are assumed for all characteristics in this chapter. VDD3x = AVDD = 3.0 V to 3.6 V VDD1x = CVDD = 1.35 V to 1.65 V VSS1x = CVSS = VSS3x = AVSSx = 0 V Table 25-19: Parameter Flash Memory Basic Characteristics Condition Symbol Number of rewrites CWRT Ambient programming temperature TAPRG Data retention time 6000 h key-on time Table 25-20: Parameter MIN. TYP. MAX. Unit 100 times/ block +100 C -40 15 years Flash Memory Programming Characteristics Symbol MIN. TYP. MAX. Unit Write time 30 300 s/ word Erase time 0.2 2 s User's Manual U16580EE3V1UD00 1031 Chapter 25 Electrical Specifications Table 25-21: Serial Write Operation Characteristics Parameter Symbol MIN. VDD setup time to FLMD0 tDRPSR 0 ns VDD setup time to RESET tDRRR 2 ms FLMD0 setup time to RESET tPSRRF 2 ms FLMD0 count start time from RESET tRFCF 10 ms FLMD0 count time tCOUNT FLMD0 counter high-level width/low-level width tCH/tCL Figure 25-26: TYP. 10 10 Serial Write Operation Characteristics VDD3 t COUNT 0V t CH VDD3 FLMD0 0V t RFCF t CL VDD1 VDD1x 0V t DRPSR t DRRR VDD3 VDD3x 0V 1032 User's Manual U16580EE3V1UD00 Unit ms s RESET (input) t PSRRF MAX. Chapter 26 Package Drawings Figure 26-1: 208-Pin Plastic QFP (Fine Pitch) (28 x 28) A B 156 157 105 104 detail of lead end S C D Q 208 1 R 53 52 F G H I J M P K N S S L M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 30.60.2 B 28.00.2 C 28.00.2 D 30.60.2 F 1.25 G 1.25 H 0.22 +0.05 -0.04 I 0.10 J K 0.5 (T.P.) 1.30.2 L 0.50.2 0.17 +0.03 -0.07 M N 0.10 P Q 3.20.1 0.40.1 R 55 S 3.8 MAX. P208GD-50-LML, MML, SML, WML-7 User's Manual U16580EE3V1UD00 1033 Chapter 26 Figure 26-2: Package Drawings 256-Pin Plastic BGA (Fine Pitch) (21 x 21) 256-PIN PLASTIC BGA (21x21) w S A D ZD ZE A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B E YWV U T R P NM L K J HG F E D CB A w S B INDEX MARK A y1 A2 S (UNIT:mm) S y A1 e S b x M S AB ITEM D DIMENSIONS 21.000.10 E 21.000.10 w 0.30 e 1.00 A 1.830.17 A1 0.500.10 A2 0.600.10 x 0.15 y 0.15 y1 0.35 ZD 1.00 ZE 1034 User's Manual U16580EE3V1UD00 1.33 b 1.00 P256F1-100-JN4 Chapter 27 Recommended Soldering Conditions Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device: Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended please consult NEC. Table 27-1: Soldering Method Soldering Conditions Soldering Condition Symbol of Recommended Soldering Condition Infrared reflow Package peak temperature: tbd C, Time: tbd seconds max. (tbd C min.), Number of times: tbd max., Number of days: tbd Note tbd VPS Package peak temperature: tbd C, Time: tbd seconds max. (tbdC min.), Number of times: tbd max., Number of days: tbdNote tbd Partial heating Pin temperature: tbd C max., Time: tbd seconds max. (per side of device) - Note: After that, prebaking is necessary at tbd C for tbd hours. The number of days refers to storage at 25C, 65% RH MAX after the dry pack has been opened. Caution: Do not use two or more soldering methods in combination (except partial heating method). User's Manual U16580EE3V1UD00 1035 Chapter 27 Recommended Soldering Conditions [MEMO] 1036 User's Manual U16580EE3V1UD00 Appendix A Index A A/D conversion result register n for DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 A/D conversion result registers n0 to n9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 A/D conversion result registers n0H to n9H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Operation in A/D trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Operation in external trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 Operation in timer trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 A/D converter n mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 A/D converter n mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 A/D converter n mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 A/D converter n trigger source select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 ADCRn0 to ADCRn9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 ADCRn0H to ADCRn9H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 ADDMAn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 Address wait control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 ADMn0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 ADMn1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 ADMn2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 ADTRSELn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 Anytime rewrite TMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 TMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345, 347 Anytime write TMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 AWC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 B Batch rewrite TMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 TMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345, 352 TMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Baud rate generator 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 BCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 BCT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 BCT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 BEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 BPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 BRG3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 BSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Bus clock dividing control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Bus control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 145 Bus cycle configuration registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Bus cycle control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Bus size configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Byte access (8 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 C CALLT base pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 CALLT execution status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 CAN (Controller area network) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 CAN Controller Baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 User's Manual U16580EE3V1UD00 1037 Appendix A Index Diagnosis functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 Interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 Register access type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 Special operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 Transition from initialization mode to operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 CAN protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 CANn global automatic block transmission control register (CnGMABT) . . . . . . . . . . . . . . . . . . . . . 776 CANn global automatic block transmission delay register (CnGMABTD) . . . . . . . . . . . . . . . . . . . . . 778 CANn global clock selection register (CnGMCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 CANn global control register (CnGMCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 CANn message configuration register m (CnMCONFm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 CANn message control register m (CnMCTRLm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 CANn message data byte register (CnMDATAxm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 CANn message data length register m (CnMDLCm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 CANn message ID register m (CnMIDLm, CnMIDHm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 CANn module bit rate prescaler register (CnBRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 CANn module bit rate register (CnBTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 CANn module control register (CnCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 CANn module error counter register (CnERC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 CANn module information register (CnINFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 CANn module interrupt enable register (CnIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 CANn module interrupt status register (CnINTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 CANn module last error information register (CnLEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 CANn module last in-pointer register (CnLIPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 CANn module last out-pointer register (CnLOPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 CANn module mask control register (CnMASKaL, CnMASKaH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 CANn module receive history list register (CnRGPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 CANn module time stamp register (CnTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 CANn module transmit history list register (CnTGPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 Capture/compare control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Capture/compare register 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Capture/compare register 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 CBnCTL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 CBnCTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 CBnCTL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 CBnRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 CBnRXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 CBnSTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 CBnTX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 CC100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 CC101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 CCR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 CG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Chip area selection control registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chip select CSI buffer register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 255 Clocked serial interface clock select register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 Clocked serial interface mode registers 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 CM100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 CM101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 CnBRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 CnBTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 1038 User's Manual U16580EE3V1UD00 Appendix A Index CnCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 CnERC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 CnGMABT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 CnGMABTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 CnGMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 CnGMCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 CnIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 CnINFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 CnINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 CnLEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 CnLIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 CnLOPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 CnMASKaH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 CnMASKaL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 CnMCONFm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 CnMCTRLm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 CnMDATAxm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 CnMDLCm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 CnMIDHm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 CnMIDLm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 CnRGPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 CnTGPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 CnTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 Compare register 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Compare register 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 85 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 CPU register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 CSC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 CSC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 CSIB transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 CSIBn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 CSIBn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 CSIBn control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 CSIBn receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 CSIBn status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 CSIBUF status register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 CSIC3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 CSIL3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 CSIM3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 CTBP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 CTPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 CTPSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 D Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Data wait control registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DBPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DBPSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Debug control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DMA data size control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DMA mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DMA status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DMA transfer A/D converter result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Forcible termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 User's Manual U16580EE3V1UD00 1039 Appendix A Index PWM timer reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Serial data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Serial data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DMA transfer count registers 0 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DMA transfer memory start address registers 0 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DMA transfer SFR start address registers 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DMA trigger factor registers 4 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DMA wait control registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 143 DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DMAMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DMAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DMAWC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 143 DMAWC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 143 DMDSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DTCR0 to DTCR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DTFR4 to DTFR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 DWC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DWC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 E ECR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 EFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 EIPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 EIPSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Endian configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Exception cause register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Exception status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Exception trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Exception/debug trap status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 External bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 F FEPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 FEPSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Flash memory programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Floating point arithmetic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Floating point arithmetic status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 G General-purpose registers (r0 to r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 H Halfword access (16 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 I ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 IMR0 to IMR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 In-service priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 INTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Internal RAM area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 1040 User's Manual U16580EE3V1UD00 Appendix A Index Internal ROM area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 219 Interrupt mask registers 0 to 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Interrupt mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228, 245 Interrupt mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Interrupt mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Interrupt mode register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Interrupt status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 INTM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228, 245 INTM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 INTM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 INTM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 INTUCnR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 INTUCnRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 INTUCnT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 ISPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 M MAR0 to MAR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Maskable interrupt status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 N NMI edge detection specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 NMI status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Noise removal time control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Non-maskable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Non-maskable interrupt status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Non-port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Normal operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 NP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 NRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 O On-chip peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 P PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Peripheral area selection control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 PHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 PICn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49, 61 Pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PRCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Prescaler compare registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 Prescaler compare registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 Prescaler mode register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 Prescaler mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 User's Manual U16580EE3V1UD00 1041 Appendix A Index Prescaler mode registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 PRM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 Processor command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Programmable peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 PRSCM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 PRSCM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 PRSCM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 PRSM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 PRSM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 PRSM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91, 228, 243, 251 R RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Real-time pulse unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Receive data buffer register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Reload TMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 TMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Reload mode TMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ROM-less mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 S SAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SAR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SESA10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 SFA3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 SFCS3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 SFCS3nL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 SFDB3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 SFDB3nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 SFDB3nL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 SFN3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 SFR area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Signal edge selection register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Single-chip modes 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SIRB3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 SIRB3nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 SIRB3nL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Software exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SRAM connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Status register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 STATUS10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 System status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 System wait control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 143 T Timer control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 1042 User's Manual U16580EE3V1UD00 Appendix A Index Timer ENC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Timer unit mode register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 TMC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 TMENC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 TMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 TMP input control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 TMP input control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 TMP input control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 TMPn capture/compare register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 TMPn capture/compare register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 TMPn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 TMPn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 TMPn counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 TMPn I/O control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 TMPn I/O control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 TMPn I/O control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 TMPn option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 TMR1 I/O control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 TMR1 I/O control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 TMRn capture/compare register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 TMRn capture/compare register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 TMRn capture/compare register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 TMRn capture/compare register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 TMRn compare register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 TMRn compare register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 TMRn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 TMRn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 TMRn counter read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 TMRn dead time setting register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 TMRn dead time setting register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 TMRn I/O control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 TMRn I/O control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 TMRn I/O control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 TMRn option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 TMRn option register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 TMRn option register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 TMRn option register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 TMRn option register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 TMRn option register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 TMRn sub-counter read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 TMTn capture/compare register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 TMTn capture/compare register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 TMTn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 TMTn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 TMTn control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 TMTn counter read buffer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 TMTn counter write buffer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 TMTn I/O control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 TMTn I/O control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 TMTn I/O control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 TMTn I/O control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 TMTn option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 TMTn option register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 TMTn option register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 TPIC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 TPIC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 TPIC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 TPnCCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 User's Manual U16580EE3V1UD00 1043 Appendix A Index TPnCCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 TPnCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 TPnCTL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 TPnCTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 TPnIOC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 TPnIOC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 TPnIOC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 TPnOPT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 TR1IOC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 TR1IOC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Transfer data length select register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 Transfer data number specification register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 Transmit data CSI buffer register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 TRnCCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 TRnCCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 TRnCCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 TRnCCR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 TRnCCR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 TRnCCR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 TRnCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 TRnCTL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 TRnCTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 TRnDTC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 TRnDTC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 TRnIOC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 TRnIOC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 TRnIOC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 TRnOPT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 TRnOPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 TRnOPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 TRnOPT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 TRnOPT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 TRnOPT7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 TRnSBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 TTnCCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 TTnCCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 TTnCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 TTnCTL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 TTnCTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 TTnCTL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 TTnIOC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 TTnIOC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 TTnIOC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 TTnIOC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 TTnOPT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 TTnOPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 TTnOPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 TTnTCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 TUM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 U UARTCn Receive error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Transmission enable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 UARTCn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 UARTCn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 UARTCn control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 UARTCn option control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 1044 User's Manual U16580EE3V1UD00 Appendix A Index UARTCn receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 UARTCn status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 UARTCn status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 UARTCn transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 UCnCTL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 UCnCTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 UCnCTL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 UCnOPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 UCnRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 UCnRXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 UCnSTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 UCnSTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 UCnTX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 UCnTXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 V VSWC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 143 W Word access (32 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 User's Manual U16580EE3V1UD00 1045 Appendix A Index [MEMO] 1046 User's Manual U16580EE3V1UD00 Appendix B Revision History The following shows the revision history up to present. Application portions signifies the chapter of each edition. (1/5) Edition No. EE2 Major items revised Revised Sections Due to the new guideline of wording and terminology, the nickname "PHOENIX-F" removed throughout the UM whole User's Manual "Burst flash memory" removed throughout the UM whole User's Manual BCLK (Burst clock output), STST and STNXT ((Burst control output) removed whole User's Manual 1.4 "Ordering Information", Note deleted 1.4, p.35 Figure 1-1 "Pin Configuration 208-pin Plastic LQFP" changed 1.5, p. 36 Table 1-1 "256-pin Plastic BGA" changed 1.5, p.38 Section "Pin identification" changed 1.5, p.40 Figure 1-3 "Internal Block Diagram" changed 1.6.1, p.41 Table 2-1 "Port Pins" changed 2.1, p.48 Table 2-2 "Non-Port Pins" changed 2.1, p.50, p.52 Table 3-5 "Peripheral I/O Registers" changed 3.4.6, p.101, 104, 107 Figure 3-20 "Programmable Peripheral Area Control Register BPC" bits 13 3.4.7 (1), p.112 and 12 changed 3.4.8 (1), Setting data to specific registers changed, Caution 2 added 3.4.8 (1), p.127 3.4.10, DMA wait control register 0 (DMAWC0) set value changed 3.4.10, p.130 Figure 4-11 "Bus Clock Dividing Control Register (DVC)" address value changed 4.7 (2), p.166 Table 3-5 "Peripheral I/O Registers" changed 3.4.6, p.101, 104, 107 Chapter 5.2 "Burst Mode Flash" removed 5.2, p.180 6.1 "Features of the DMA" added 6.1, p.181 Figure 6-1 "DMA Transfer Memory Start Address Registers 0 to 7 (MAR0 to 6.2 (1), p.182 MAR7)", Caution 2 added Figure 6-2 "DMA Transfer SFR Start Address Registers 2, 3 (SAR2, SAR3)", Caution added 6.2 (2), p.183 Figure 6-3 "DMA Transfer Count Registers 0 to 7 (DTCR0 to DTCR7)", Caution 3 deleted 6.2 (3), p.184 Figure 6-8 "Initialization of DMA Transfer for A/D Conversion Result" changed 6.4.1, p.189 Figure 6-9 "Operation of DMA Channel 0/1" added 6.4.1, p.190 Figure 6-10 "DMA Channel 0 and 1 Trigger Signal Timing", added 6.4.1, p.191 6.4.2 "DMA transfer of PWM timer reload (TMR0, TMR1)", DMA trigger count changed 6.4.2, p.192 Figure 6-11 "Initialization of DMA Transfer for TMRn Compare Registers", changed 6.4.2, p.193 Figure 6-12 "Operation of DMA Channel 2/3", added 6.4.2, p.194 Figure 6-13 "DMA Channel 2 and 3 Trigger Signal Timing", added 6.4.2, p.195 Table 6-2 "DMA Configuration of Serial Data Reception", DMA trigger factor changed 6.4.3 (1), p.196 User's Manual U16580EE3V1UD00 1047 Appendix B Revision History (2/5) Edition No. EE2 Major items revised Revised Sections Figure 6-14 "Initialization of DMA Transfer for Serial Data Reception" added 6.4.3 (1), p.197 Figure 6-15 "Operation of DMA Channel 4/5", added 6.4.3 (1), p.198 Figure 6-16 "DMA Channel 4 and 5 Trigger Signal Timing" added 6.4.3 (1), p.199 Table 6-3 "DMA Configuration of Serial Data Transmission", DMA trigger factor changed 6.4.3 (2), p. 200 Figure 6-17 "Initialization of DMA Transfer for Serial Data Transmission" added 6.4.3 (2), p. 201 Figure 6-18 "DMA Channel 6 and 7 Trigger Signal Timing", added 6.4.3 (2), p.202 Figure 6-19 "Operation of DMA Channel 6/7" added 6.4.3 (2), p.203 Figure 6-20 "CPU and DMA Controller Processing of DMA Transfer Termination (Example)" added 6.4.4, p.204 Table 6-4 "Relations Between DMA Trigger Factors and DMA Completion Interrupts", DMA trigger factor changed 6.5, p. 205 Figure 6-21 "Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts" added 6.5, p.206 Figure 7-10 "Interrupt Control Register (PICn)", value after reset and Man bit description changed 7.3.4, p.224 Figure 7-13 "Interrupt Service Priority Register (ISPR)", R/W changed to R 7.3.6, p.230 1048 Figure 7-15 "Interrupt Mode Register 0 (INTM0)", description of bits ESN1 and ESN0 added 7.3.8 (1), p.233 Figure 9-10 "TMPn Option Register 0 (TPnOPT0)", description of TPnOVF flag changed 9.4 (6), p.258 Figure 9-27 "Basic Operation Timing in PWM Mode", remark 2 changed 9.5.6, p.283, 284 10.3 (7) "TMRn I/O control register 4 (TRnIOC4)", description changed 10.3 (7), p.318 Figure 10-19 "TMRn Option Register 0 (TRnOPT0)" changed 10.3 (8), p.320 10.3 (11) "TMRn option register 3 (TRnOPT3)" Caution changed 10.3(11), p.325 Figure 10-35 "A/D Conversion Trigger Output Controller", changed 10.8, p.362 Figure 10-56 "High-Accuracy T-PWM Mode Block Diagram", changed 10.10.9 (1), p.405 10.10.9 (2) (d) "Interrupts" changed, Notes added 10.10.9 (2) (d), p.406 10.10.9 (7) "Caution on timer output in high-accuracy T-PWM mode", changed 10.10.9 (7), p.414-416 Table 10-1 "Positive Phase Operation Condition List" changed 10.10.9 (8), p.417 Table 10-2 "Negative Phase Operation Condition List" changed 10.10.9 (8), p.417 10.10.9 (8) "Timer output change after compare register updating", added 10.10.9 (8), p.417-429 10.10.9 (9) "Dead time control in high-accuracy T-PWM mode", changed 10.10.9 (9), p.430 10.10.9 (10) "Cautions on dead time control in high-accuracy T-PWM mode", added 10.10.9 (10), p.431 10.10.9 (11) "Caution on rewriting cycles in high-accuracy T-PWM mode", changed 10.10.9 (11), p.432 10.10.9 (12) "Error interrupt (INTTRnER) in high-accuracy T-PWM mode", changed 10.10.9 (12), p.433 Figure 10-72 "Block Diagram in PWM Mode With Dead Time", changed 10.10.10 (1), p.434 10.10.10 (3) (e) "Reload thinning out function setting", changed 10.10.10 (3) (e), p.437 Table 11-3 "Capture/Compare Functions in Each Mode" changed 11.3 (1), p.447 Table 11-4 "Capture/Compare Functions in Each Mode" changed 11.3 (2), p.449 User's Manual U16580EE3V1UD00 Appendix B Revision History (3/5) Edition No. EE2 Major items revised Revised Sections Figure 11-6 "TMTn Control Register 0 (TTnCTL0)", changed 11.4 (1), p.452 Figure 11-7 "TMTn Control Register 1 (TTnCTL1)", changed 11.4 (2), p.453 Figure 11-8 "TMTn Control Register 2 (TTnCTL2)", changed 11.4 (3), p.455-456 Figure 11-9 "TMTn I/O Control Register 0 (TTnIOC0)", changed 11.4 (4), p.457 Figure 11-11 "TMTn I/O Control Register 2 (TTnIOC2)", changed 11.4 (6), p.459 Figure 11-12 "TMTn I/O Control Register 3 (TTnIOC3)", changed 11.4 (7), p.460, 461 Figure 11-13 "TMTn Option Register 0 (TTnOPT0)", changed 11.4 (8), p.462 Figure 11-14 "TMTn Option Register 1 (TTnOPT1)" changed 11.4 (9), p.464 Table 11-6 "Counter Clear Operation" changed 11.5.1 (2), p.467 Table 11-7 "Capture/Compare Rewrite Methods in Each Mode" changed 11.5.2 82), p.472 11.6.9 "Encoder count function" changed 11.6.9, p.499-500 11.6.9 (6) (a) removed 11.6.9 (6), p.512 Figure 11-37 (a) removed, ((c) changed, (i) and (j) removed 11.6.9 (6), p. 512-518 Figure 11-38 "Basic Timing in Offset Trigger Generation Mode" changed 11.6.10, p.517 Figure 14-1 "Block Diagram of A/D Converter (ADCn)", changed 14.2, p.559 Figure 14-5 "A/D Converter n Trigger Source Select Register (ADTRSELn)", 14.3 (4), p.564 changed 14.4.2 (1) (b) "Timer trigger mode", bit names changed 14.4.2 (1) (b), p.570 14.6 "Operation in Timer Trigger Mode", timer event signals's names changed 14.6, p.580 14.6.1 (1) "1-buffer mode operation (timer trigger select: 1 buffer)", timer event signals's names changed 14.6.1 (1), p.580 Table 14-6 "Correspondence Between Analog Input Pins and ADCRnm Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer)", changed 14.6.1, p.581 Figure 14-15 "Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 14.6.1, p.581 Buffer) (ANIn1)", changed 14.6.1 (2) "4-buffer mode operation (timer trigger select: 4 buffers)", timer event signals's names changed 14.6.1 (2), p.582 Table 14-7 "Correspondence Between Analog Input Pins and ADCRnm Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers)", changed 14.6.1, p.582 Figure 14-16 "Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANIn3)", changed 14.6.1, p.583 Table 14-8 "Correspondence Between Analog Input Pins and ADCRnm Register (Scan Mode (Timer Trigger Scan))", changed 14.6.2, p.584 Figure 14-17 "Example of Scan Mode Operation (Timer Trigger Scan) (ANIn0 to ANIn4)", changed 14.6.2, p.585 Figure 15-4 "UARTCn Control Register 2 (UCnCTL2)", changed 15.3 (3), p.599 Figure 16-28 "Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1)", 16.7.2 (2), p.659 changed Figure 17-20 "Delay Control of Transmission/Reception Completion Interrupt (INTC3n)", changed 17.5.14, p.692 Figure 17-21 "Transfer Wait Function" (3/3), CSITn bit value changed from 0 to 1 17.5.15, p.695 Figure 18-24 "CAN Global Clock Selection Register (CnGMCS)", Bit 7 changed, Remark 1 changed 18.6.2, p.761 Table 20-1 "Port Type and Function Overview", Port CD changed 20.2.1, p.865 User's Manual U16580EE3V1UD00 1049 Appendix B Revision History (4/5) Edition No. EE2 Major items revised Revised Sections Table 20-2 "Peripheral Registers of I/O Ports", value after reset changed 20.2.3, p.890 Figure 20-32 "Port Mode Control Register 3 (PMC3)", bit PMC32 description changed 20.3.4 (2) (c), p.905 Figure 20-34 "Port Mode Register 4 (PM4)", bits 7 and 6 values changed from "0" to "1" 20.3.5 (2) (b), p.907 Figure 20-47 "Port Mode Register 7 (PM7)", bits 7 and 6 values changed from "0" to "1" 20.3.8 (2) (b), p.921 Figure 20-50 "Port Mode Register 8 (PM8)", bit 7 value changed from "0" to "1" 20.3.9 (2) (b), p.925 Figure 20-53 "Port Mode Register 9 (PM9)", bit 7 value changed from "0" to "1" 20.3.10 (2) (b), p.929 Figure 20-56 "Port Mode Register 10 (PM10)", bits 7 to 3 values changed from "0" to "1", register address changed 20.3.11 (2) (b), p.933 Figure 20-57 "Port Mode Control Register 10 (PMC10)", register address changed 20.3.11 (2) (c), p.934 Figure 23-3 "Example of Recommended Emulator Connection of V850E/PH2", Cautions, voltage changed from 5 V to 3.3 V 23.2.1 (3), p.974 Table 25-1 "Absolute Maximum Ratings", VSS1 added, operating temperature conditions changed 25.1, p.997 25.2.3 "Oscillator characteristics", Remark, R1 changed to R 25.2.3, p.999 Table 25-5 "DC Characteristics", changed, Notes 1 and 2 added 25.3, p.1000 Table 25-6 "External Asynchronous Memory Access Read Timing", values changed, Remark 6 added 25.4.1, p.1002 Figure 25-4 "External Asynchronous Memory Access Read Timing", changed 25.4.1, p.1003 Table 25-7 "External Asynchronous Memory Access Write Timing", parameters and values changed, Remark 6 added 25.4.2, p.1004 Figure 25-5 "External Asynchronous Memory Access Write Timing", changed 25.4.2, p.1005 Table 25-8 "Reset Timing", RESET high level width deleted 25.4.3, p.1006 Figure 25-6 "Reset Timing", changed 25.4.3, p.1006 Table 25-15 "CSI3 Characteristics (Master Mode)", minimum value changed 25.5.2 (2), p.1014 EE3 Table 25-17 "A/D Converter Characteristics" changed 25.5.3, p.1020 Section 25.6 "Flash Programming Characteristics" added 25.6, p.1021 Figure 26-2 "256-Pin Plastic BGA (Fine Pitch) (21 x 21)", added 26, p.1024 Figure 10-44 "Basic Operation Flow in External Trigger Pulse Output Mode", 10.10.3, p. 396 changed 10.10.4 (1) <4> "One-shot pulse operation flow", changed 10.10.4, p. 398 10.10.4 (2) (b) "Input pins", TTRGR1 changed 10.10.4, p. 399 Figure 10-46 "Basic Operation Flow in One-Shot Pulse Mode", changed 10.10.4, p. 400 Figure 10-47 "Basic Operation Timing in One-Shot Pulse Mode", changed, 10.10.4, p. 401 Note 2 added 1050 11.6.3 "External trigger pulse output mode", Caution changed 11.6.3, p. 495 11.6.4 "One-shot pulse mode", Caution changed 11.6.4, p. 498 Figure 16-2 "CSIBn Receive Data Register (CBnRX, CBnRXL)", Notes changed 16.2 (1), p. 645 User's Manual U16580EE3V1UD00 Appendix B Revision History (5/5) Edition No. EE3 Major items revised Revised Sections Figure 16-4 "CSIBn Control Register 0 (CBnCTL0) (1/2)", changed 16.3 (1), p. 647 Figure 17-2" Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2)", Note added 17.3 (1), p. 678 Figure 17-3 "Clocked Serial Interface Clock Select Register 3n (CSIC3n) (1/3)", Note added 17.3 (2), p. 680 Figure 17-4 "Receive Data Buffer Register 3n (SIRB3n, SIRB3nL, SIRB3nH)", Note added 17.3 (3), p. 683 Figure 17-5 "Chip Select CSI Buffer Register 3n (SFCS3n, SFCS3nL)", Note added 17.3 (4), p. 684 Figure 17-6 "Transmit Data CSI Buffer Register 3n (SFDB3n, SFDB3nL, SFDB3nH)", Note added 17.3 (5), p. 685 Figure 17-7 "CSIBUF Status Register 3n (SFA3n)(1/3)", Note added 17.3 (6), p. 686 Figure 17-8 "Transfer Data Length Select Register 3n (CSIL3n)", Note added 17.3 (7), p. 689 Figure 17-9 "Transfer Data Number Specification Register 3n (SFN3n)", Note added 17.3 (8), p. 690 18 "AFCAN Controller", introduction changed 18, p. 737 Figure 24-2 "Flash Memory Mapping of PD70F3447", values changed 24.2, p. 965 User's Manual U16580EE3V1UD00 1051 1052 User's Manual U16580EE3V1UD00