JFET Input Operational
Amplifiers
These low cost JFET input operational amplifiers combine two
state–of–the–art analog technologies on a single monolithic integrated
circuit. Each internally compensated operational amplifier has well matched
high voltage JFET input devices for low input offset voltage. The BIFET
technology provides wide bandwidths and fast slew rates with low input bias
currents, input offset currents, and supply currents.
The ON Semiconductor BIFET family offers single, dual and quad
operational amplifiers which are pin–compatible with the industry standard
MC1741, MC1458, and the MC3403/LM324 bipolar devices. The MC34001/
34002/34004 series are specified from 0°to +70°C.
•Input Offset Voltage Options of 5.0 mV and 10 mV Maximum
•Low Input Bias Current: 40 pA
•Low Input Offset Current: 10 pA
•Wide Gain Bandwidth: 4.0 MHz
•High Slew Rate: 13 V/µs
•Low Supply Current: 1.4 mA per Amplifier
•High Input Impedance: 1012 Ω
•High Common Mode and Supply Voltage Rejection Ratios: 100 dB
•Industry Standard Pinouts
ORDERING INFORMATION
Op Amp
Function Device Operating
Temperature Range Package
Single
MC34001BD, D
T=0°to+ 70°C
SO–8
Single MC34001BP, P TA = 0° to+ 70°CPlastic DIP
Dual
MC34002BD, D
T 0°to +70°C
SO–8
Dual MC34002BP, P TA = 0° to +70°CPlastic DIP
Quad MC34004BP, P TA = 0° to +70°CPlastic DIP
ON Semiconductor
Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 2 1Publication Order Number:
MC34001/D
MC34001, B
MC34002, B
MC34004, B
JFET INPUT
OPERATIONAL AMPLIFIERS
NC
VCC
Output
Offset Null
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
MC34001 (Top View)
PIN CONNECTIONS
MC34002 (Top View)
Offset Null
Noninv. Input
VEE
Inv. Input
VEE
Inputs A
Inputs B
Output B
Output A VCC
1
2
3
4
8
7
6
5
+
-
-
+
+
1
2
3
4
8
7
6
5
1
81
8
P SUFFIX
PLASTIC PACKAGE
CASE 646
PIN CONNECTIONS
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
MC34004 (Top View)
4
23
1
-
1
2
3
4
5
6
78
9
10
11
12
13
14
+
-
+
+
-
+
-
14
1
MC34001, B MC34002, B MC34004, B
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC, VEE ±18 V
Differential Input Voltage (Note 1) VID ±30 V
Input Voltage Range VIDR ±16 V
Open Short Circuit Duration tSC Continuous
Operating Ambient Temperature Range TA 0 to +70 °C
Operating Junction Temperature TJ150 °C
Storage Temperature Range Tstg –65 to +150 °C
NOTES: 1.Unless otherwise specified, the absolute maximum negative input voltage is equal to the
negative power supply.
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k)
MC3400XB
MC3400X
VIO —
—3.0
5.0 5.0
10
mV
Average Temperature Coefficient of Input Offset Voltage
RS ≤ 10 k, TA = Tlow to Thigh (Note 2) ∆VIO/∆T — 10 — µV/°C
Input Offset Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIO —
—25
25 100
100
pA
Input Bias Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIB —
—50
50 200
200
pA
Input Resistance ri— 1012 —Ω
Common Mode Input Voltage Range VICR ±11
—+15
–12 —
—V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k)
MC3400XB
MC3400X
AVOL 50
25 150
100 —
—
V/mV
Output Voltage Swing
(RL ≥ 10 k)
(RL ≥ 2.0 k)
VO±12
±10 ±14
±13 —
—
V
Common Mode Rejection Ratio (RS ≤ 10 k)
MC3400XB
MC3400X
CMRR 80
70 100
100 —
—
dB
Supply Voltage Rejection Ratio (RS ≤ 10 k) (Note 4)
MC3400XB
MC3400X
PSRR 80
70 100
100 —
—
dB
Supply Current (Each Amplifier)
MC3400XB
MC3400X
ID—
—1.4
1.4 2.5
2.7
mA
Slew Rate (AV = 1.0) SR — 13 — V/µs
Gain–Bandwidth Product GBW — 4.0 — MHz
Equivalent Input Noise Voltage
(RS = 100 Ω, f = 1000 Hz) en— 25 — nV/ Hz√
Equivalent Input Noise Current (f = 1000 Hz) in— 0.01 — pA/ Hz√
NOTES: 2.Tlow =0°C for MC34001/34001B Thigh = +70°C for MC34001/34001B
0°C for MC34002 +70°C for MC34002
0°C for MC34004/34004B +70°C for MC34004/34004B
3.The input bias currents approximately double for every 10°C rise in junction temperature, TJ. Due to limited test time, the input bias currents are
correlated to junction temperature. Use of a heatsink is recommended if input bias current is to be kept to a minimum.
4.Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
MC34001, B MC34002, B MC34004, B
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ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh [Note 2].)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k)
MC3400XB
MC3400X
VIO —
——
—7.0
13
mV
Input Offset Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIO —
——
—4.0
4.0
nA
Input Bias Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIB —
——
—8.0
8.0
nA
Common Mode Input Voltage Range VICR ±11 — — V
Large Signal (VO = ±10 V, RL = 2.0 k)
MC3400XB
MC3400X
AVOL 25
15 —
——
—
V/mV
Output Voltage Swing
(R ≥ 10 k)
(R ≥ 2.0 k)
VO±12
±10 —
——
—
V
Common Mode Rejection Ratio (RS ≤ 10 k)
MC3400XB
MC3400X
CMRR 80
70 —
——
—
dB
Supply Voltage Rejection Ratio (RS ≤ 10 k) (Note 4)
MC3400XB
MC3400X
PSRR 80
70 —
——
—
dB
Supply Current (Each Amplifier)
MC3400XB
MC3400X
ID—
——
—2.8
3.0
mA
NOTES: 2.Tlow =0°C for MC34001/34001B Thigh = +70°C for MC34001/34001B
0°C for MC34002 +70°C for MC34002
0°C for MC34004/34004B +70°C for MC34004/34004B
3.The input bias currents approximately double for every 10°C rise in junction temperature, TJ. Due to limited test time, the input bias currents are
correlated to junction temperature. Use of a heatsink is recommended if input bias current is to be kept to a minimum.
4.Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
MC34001, B MC34002, B MC34004, B
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VCC/VEE = ±15 V
RL = 10 k
RL = 2.0 k
VCC/VEE = ±15 V
±5.0 V
±10 V
RL = 2.0 k
TA = 25°C
VO, OUTPUT VOLTAGE SWING (Vpp )
VO, OUTPUT VOLTAGE SWING (Vpp)V
O, OUTPUT VOLTAGE SWING (Vpp )
Figure 1. Input Bias Current
versus Temperature Figure 2. Output Voltage Swing
versus Frequency
Figure 3. Output Voltage Swing
versus Load Resistance Figure 4. Output Voltage Swing
versus Supply Voltage
Figure 5. Output Voltage Swing
versus Temperature Figure 6. Supply Current per Amplifier
versus Temperature
TA, AMBIENT TEMPERATURE (°C)
-75 -50 -25 0 25 50 75 100 125
VCC/VEE = ±15 V
100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
RL, LOAD RESISTANCE (kΩ)
0.1 0.2 0.4 0.7 1.0 2.0 10
4.0 7.0
VCC/VEE = ±15 V
TA = 25°C
VCC/VEE , SUPPLY VOLTAGE (V)
0 5.0 10 15 20
RL = 2.0 k
TA = 25°C
TA, AMBIENT TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
VCC/VEE = ±15 V
I, SUPPLY DRAIN CURRENT (mA)
D
100
10
1.0
0.1
0.01
30
25
20
15
10
5.0
0
30
20
10
5.0
0
40
30
20
10
0
35
30
25
20
15
10
5.0
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
40
35
,VOOUTPUT VOLTAGE SWING (V pp)
IIB, INPUT BIAS CURRENT (nA)
MC34001, B MC34002, B MC34004, B
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Figure 7. Large–Signal Voltage Gain and
Phase Shift versus Frequency Figure 8. Large–Signal Voltage Gain
versus Temperature
Figure 9. Normalized Slew Rate
versus Temperature Figure 10. Equivalent Input Noise Voltage
versus Frequency
Figure 11. Total Harmonic Distortion
versus Frequency
f, FREQUENCY (Hz)
PHASE SHIFT (DEGREES)
1.0 10 100 1.0 k 10 k 100 k 1.0 M 1.0 M 10 M
AVOL
Gain
Phase Shift
VCC/VEE = ±15 V
RL = 2.0 k
TA = 25°C
A, VOLTAGE GAIN (V/mV)
VOL
VCC/VEE = ±15 V
VO = ±10 V
RL = 2.0 k
TA, AMBIENT TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
NORMALIZED SLEW RATE
-50 -25 0 25 50 75 100 125
f, FREQUENCY (kHz)
e
0.01 0.05 0.1 0.5 1.0 5.0 10 50 100
n
VCC/VEE = ±15 V
AV = 10
RS = 100 Ω
TA = 25°C
VCC/VEE = ±15 Vdc
AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
f, FREQUENCY (kHz)
THD, TOTAL HARMONIC DISTORTION (%)
0.1 0.5 1.0 5.0 10 50 100
nV/ Hz )√
, OPEN-LOOP GAIN
, EQUIVALENT INPUT NOISE VOLTAGE (
106
105
104
103
101
102
1
1000
100
10
1.0
1.15
1.10
1.05
1.00
0.95
0.90
0.85
60
50
40
30
20
10
0
1.0
0.5
0.1
0.05
0.01
0.005
0.001
0°
45°
90°
135°
180°
MC34001, B MC34002, B MC34004, B
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Figure 12. Output Current to Voltage Transformation
for a D–to–A Converter
Representative Circuit Schematic
(Each Amplifier)
-
+
Inputs
Q3 Q4 Q5 Q2
Q1
VCC
Q6
J1 J2
Q17
Q20
Q23
24
J3
2.0 k
Q14
Q15
10 pF
Q19
Q21 Q22 Q24
Q9 Q8 Q7 Q25
Q12
Q10
Q13
Q11
Q16
Q18
1.5 k
VEE
Bias Circuitry
Common to All
Amplifiers
Offset
Null
(MC34001 only)
Output
1.5 k
VCC
R1
Vref
R2 VCC = 15 V
VO
1
-
+
MC34001
VEE RO
15 pF
D-to-A
A1
A2
A3
A4
A5
A6
A7
A8LSB
C
VEE = -15 V
MSB
Settling time to within 1/2 LSB is approximately 4.0 µs
from the time all bits are switched (C = 68 pF).
The value of C may be selected to minimize overshoot
and ringing.
Theoretical VO
VO = Vref
R1 (RO)A1 A2 A3 A4 A5 A6 A7 A8
2 4 8 16 32 64 128 256
++++ ++ +
Io
MC34001, B MC34002, B MC34004, B
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7
Figure 13. Positive Peak Detector
Figure 14. Long Interval RC Timer Figure 15. Isolating Large Capacitive Loads
Figure 16. Wide BW, Low Noise,
Low Drift Amplifier
-10 V
10 V
C2
R2
R1
C1 3
4
VEE
Vin
VCC
6
2
7
fmax 240 kHz
Power BW: fmax = Sr
2π Vp 240 kHz
Parasitic input capacitance (C1 3.0 pF plus any additional layout capacitance)
interacts with feedback elements and creates undesirable high-frequency pole.
To compensate add C2 such that: R2C2 R1C1.
8
0.5
0.02
CL
=
R2 5.1 k VO
VCC
R1 5.1 k 27
6
4
3
MC34001
VEE
RL 5.1 k CL 0.5 µF
CC
R3 10
+2.0 V
0
∆VO IOV/µs = 0.04 V/µs (with CL shown)
∆t
-
+
Overshoot 10%
ts = 10 µs
When driving large CL, the VO slew rate is determined by CL
and IO(max):
=
-2.0 V
IO
8VCC
D1
2
3
-
+
6
5
-
+7
Reset
Vin
4VEE
1/2
MC34002
1N914 1 µF
*
Reset
Network
or Relay
*Polycarbonate capacitor
D1 = Hi-speed, low-reverse leakage diode
VO
MC34001
VR
Run
R4
R1 V1 R3 27+15 V
MC34001
6
R6
-15 V
Clear C*
R5
3
-
+4
*Polycarbonate or
Polystyrene Capacitor
Time (t) = R4 Cn (VR/VR-VI), R3 = R4, R5 = 0.1 R6
If R1 = R2: t = 0.693 R4C
Design Example: 100 Second Timer
VR = 10 V C = l.0 µF R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k R1 = R2 = 1.0 k
R2
20 pF
1/2
MC34002
MC34001, B MC34002, B MC34004, B
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8
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
OUTLINE DIMENSIONS
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040

SEATING
PLANE
1
4
58
A0.25 MCB SS
0.25 MBM
h
C
X 45
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.18 0.25
D4.80 5.00
E
1.27 BSCe
3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
0.25 0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
MC34001, B MC34002, B MC34004, B
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P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
OUTLINE DIMENSIONS
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
17
14 8
B
A
F
HG D K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L0.300 BSC 7.62 BSC
M0 10 0 10
N0.015 0.039 0.39 1.01

MC34001, B MC34002, B MC34004, B
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NOTES
MC34001, B MC34002, B MC34004, B
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NOTES
MC34001, B MC34002, B MC34004, B
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12
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