TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Correlated Double Sampling (CDS), AGC
and High Speed 10-Bit ADC in a Single
Package
D
5-V Analog Power Supply and 3.3-V Digital
Power Supply
D
Power Down Mode
D
56-Pin TSSOP (DGG) Package with
Multichip Module Assembly for Isolation
CDS/AGC
D
AGC Gain Range of 5 dB to 39 dB
D
Black Level Clamp Circuit
D
Direct Connection to ADC Input
D
Voltage Reference for ADC
Analog-to-Digital Converter
D
10-Bit Resolution
D
Maximum Conversion Rate...20 MSPS
(MIN)
D
Differential Nonlinearity...0.75 LSB (TYP)
D
Analog Input Voltage Range of 2 Vp-p
D
3.3 V CMOS Digital Interface
Applications
D
PC Camera
D
Digital Camera
D
Camcorder
D
CCD Scanner
description
The TLC976 is a multichip module (MCM) subsystem designed for interfacing Charge-Coupled Device (CCD)
in camcorder and digital camera systems. The TLC976 includes correlated double sampler (CDS), automatic
gain control (AGC), black level clamp circuit, 10 bit, 20 MSPS analog-to-digital converter (ADC), and internal
reference voltage generator for ADC.
The CDS/AGC can be connected directly to the ADC input or a separate signal can be connected directly to
the ADC input. A power-down mode is provided.
Assembled using the MCM process, the TLC976 provides isolation between the noisy digital domain and the
noise sensitive analog signals. The CDS/PGA, black level clamps are on one die and the ADC is on a separate
die. The separate dies significantly reduce the substrate noise to the analog section.
The TLC976 comes in a 56-pin TSSOP package with 0,50 mm pin pitch. This is about 25% smaller than using
two separate 32-pin quad flat packs (QFP).
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
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9
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14
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16
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20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SHV
GND1
BLK-PULSE
OFFSET
VCC3
DRIVE-OUT
GND3
CDS-STBY
VRB-OUT
VRT-OUT
A-SUB
D-SUB
DVSS
D0
D1
D2
D3
D4
DVSS
DVDD
D5
D6
D7
D8
D9
RESET
DVSS
AVDD
SHR
VCC1
CLP2
DATA-IN
PIN
AGCGAIN
OBCLP
AGCCLP
SH-PULSE
GND2
VCC2
A-SUB
DVDD
AVSS
AVSS
VIN
D-SUB
AVSS
VRB-IN
VRB-IN
VRT-IN
VRT-IN
AVSS
AVDD
AVDD
AD-STBY
OE
CLK
DGG PACKAGE
(TOP VIEW)
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
SHR
SH-PULSE
PIN
AGC
SH SH
SH
CLP1
CLP2
SHLPF
AGCCLP
BLK
VRB
VRT
Auto
Calibration
Circuit
DRV
CLK
Upper
Sampling
Comparators
+
–
S&H
DAC
Upper
Data
Latch
Upper
Data
Latch
Lower
Data
Latch
Lower
Sampling
Comparators
Lower
Data
Latch
Reference
Voltage
Clock
Generator
DATA-IN
CLP2
OFFSET
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SHV AGCGAIN AGCCLP OBCLP
BLK-PULSE
VRB-OUT
VRT-OUT
CDS-STBY
DRIVE-OUT
RESET
VIN
VRB-IN
VRT-IN
AD-STBY
OE
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AD-STBY 31 I ADC standby mode
L level in operation H level in standby mode
AGCCLP 49 I AGC clamp capacitor (connect 0.1 µF to GND)
AGCGAIN 51 I AGC gain control
A-SUB 11, 45 Analog GND
AVDD 28, 32, 33 ADC analog power supply
AVSS 34, 39, 42,
43 Analog GND for ADC
BLK-PULSE 3 I DRIVE-OUT terminal is clamped to 1.66 V internally when BLK-PULSE = L.
CDS-STBY 8 I CDS/AGC standby mode control
L level in operation H level in standby mode
CLK 29 I CLK input for ADC
CLP2 54 I CCD signal clamp control input
D0–D9 14–18,
21–25 ODigital data output, D0 (pin 14): LSB, D9 (pin 25): MSB
DATA-IN 53 I CCD signal input
DRIVE-OUT 6 O CDS/AGC output
D-SUB 12, 40 Analog GND
DVDD 20, 44 ADC digital power supply
DVSS 13, 19, 27 Digital GND for ADC
GND1 2 I CDS/AGC analog GND
GND2 47 CDS/AGC analog GND
GND3 7 GND for CDS output circuit
OBCLP 50 I Control input for clamping optical black level after AGC
OE 30 I ADC output enable
L level in operation H level in Hi-Z
OFFSET 4 I CDS/AGC output offset control:
DC voltage at OFFSET pin DRIVE-OUT offset
0 V –450 mV
0.5 V –280 mV
3 V 550 mV
PIN 52 I CCD signal input
RESET 26 I Reset for calibration circuit. Restart of startup calibration.
SHV 1 I CCD signal level sample clock input
SH-PULSE 48 I Sample and hold pulse input
SHR 56 I CCD reset level sample clock input
VCC1 55 CDS/AGC analog power supply
VCC2 46 CDS/AGC analog power supply
VCC3 5 CDS/AGC analog power supply
VIN 41 I ADC analog signal input
VRB-OUT 9 O ADC bottom reference voltage output (1.5 V typ)
VRB-IN 37, 38 I Connect to VRB-OUT
VRT-OUT 10 O ADC top reference voltage output (3.5 V typ)
VRT-IN 35, 36 I Connect to VRT-OUT
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Analog supply voltage, VCC1, VCC2, VCC3, AVDD (see Note 1) –0.4 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . .
Digital supply voltage, DVDD (see Note 1) –0.4 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, VI –0.4 V to AVCC1, 2,3 + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Note 2) 1344 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltages are with respect to GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 10.75 mW/°C.
recommended operating conditions
MIN NOM MAX UNIT
Analog supply voltage, VCC1, VCC2, VCC3, AVDD 4.75 5 5.25 V
ADC digital output supply voltage, DVDD 3 3.3 3.6 V
Difference, AGND to DGND –100 100 mV
High-level input voltage 2 V
Low-level input voltage 0.8 V
ADC analog input voltage full scale range 2 V
ADC CLK
p
ulse width
High level 25
ns
ADC
CLK
p
u
lse
w
idth
Low level 25
ns
Operating temperature 0 70 °C
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25°C (unless
otherwise noted)
total device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CDS/AGC supply current AGCGAIN = 0 V,
STBY = 0 V VRT = VRB = Open, 30 38 mA
ADC su
pp
ly current
Digital supply
NTSC ram
p
in
p
ut
3 6
mA
ADC
s
u
ppl
y
c
u
rrent
Analog supply
NTSC
ramp
inp
u
t
32 35
mA
CDS/AGC standby current CDS-STBY = High 5.6 11 mA
ADC standby current AD-STBY = HIGH, CDS STBY = HIGH,
(VIN = VRT-IN = VRB-IN = Hi-Z) 0.5 1 mA
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25°C (unless
otherwise noted) (continued)
CDS input/AGC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal clamp voltage 2.7 V
In
p
ut current for SHR SHV CLP2
High input VIN = 3 V 1 A
Inp
u
t
c
u
rrent
for
SHR
,
SHV
,
CLP2
Low input VIN = 0 V –1 µA
AGC gain
Minimum AGCGAIN = 0 V 5 7
dB
AGC
gain
Maximum AGCGAIN = 3 V 34 37 39
dB
High-level input current, OBCLP, BLK pulse 1 µA
Low-level input current, OBCLP, BLK pulse –1 µA
CDS input clock frequency 20 MHz
driver output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
p
High OFFSET = 3 V 0.55 0.65 V
u
u
v
Low OFFSET = 0 V –0.35 –0.45 V
Internal black level 1.36 1.66 1.96 V
Nominal signal voltage at DRIVE-OUT 2 Vp-p
reference voltage
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRT output voltage
300 ΩAVDD = VCC1 3 = 4 75 V
3.47 3.50 3.53 V
VRB output voltage
300
Ω
,
AVDD
=
VCC1
–
3
=
4
.
75
V
1.45 1.50 1.55 V
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25°C (unless
otherwise noted) (continued)
A/D converter
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Integral non-linearity Fs = 20 MSPS, VIN = 1.8 V – 3.8 V ±1.5 ±2.5 LSB
Differential non-linearity ±0.75 ±1.25 LSB
Analog input capacitance 10 pF
Reference voltage output current 6.5 mA
Reference voltage output impedance (VRT IN – VRB IN) 300 Ω
Zero scale offset error 20 mV
Full scale offset error 20 mV
High-level input current DVDD = MAX, VIH = DVDD 10 µA
Low-level input current DVDD = MAX, VIL = 0 V 10 µA
High-level output current OE = GND,
VOH = DVDD – 0.5 V DVDD = MIN, 3 mA
Low-level output current OE = GND,
VOL = 0.4 V DVDD = MIN, 5 mA
High-level output voltage DVDD = 3 V – 5.25 V, IOH = 2 mA VDD–
0.7V V
Low-level output voltage DVDD = 3 V – 5.25 V, IOL = 1 mA 0.8 V
High-level output leakage current OE = DVDD,
VOH = DVDD DVDD = MAX, 1µA
Low-level output leakage current OE = DVDD,
VOL = 0 V DVDD = MIN, 1µA
Automatic starting calibration voltage
DVDD–DGND 2.5
V
A
u
tomatic
starting
calibration
v
oltage
VRT–VRB 1
V
A/D converter operating characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sampling rate VIN = 1.8 V – 3.8 V, Fin = 1 kHz ramp 0.5 20 MSPS
Analog input bandwidth (–3 dB) 10 MHz
Data output, propagation delay CL = 20 pF 15 ns
Differential gain
NTSC 40 IRE mod ram
p
FS = 14 3 MSPS
1%
Differential phase
NTSC
40
IRE
mod
ramp
,
FS
=
14
.
3
MSPS
0.3 Degree
Sampling delay time 5 ns
Signal to noise ratio Fin = 1 MHz 55 dB
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
25
20
00 0.3 0.6 0.9 1.2 1.5 1.8
AGCGAIN – dB
30
40
AGCGAIN – V
AGCGAIN
vs
VOLTAGE
45
2.1 2.4 2.7 3
35
15
5
10
Figure 1. AGC Characteristics
0.1
–0.1
–0.3
–0.5 0 0.5 1 1.5
DRIVE OUT Offset Voltage
0.2
0.5
Control Voltage at OFFSET Pin (V)
OUTPUT OFFSET VOLTAGE
vs
OFFSET CONTROL VOLTAGE
0.6
2 2.5 3
0.4
0.3
0
–0.2
–0.4
Figure 2. OFFSET IN Terminal Input/Output Characteristics
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL OPERATION
CCD Input
10 µs
(typ)
2 µs
(typ)
CCD Reset Feedthrough
CCD Reset Level
CCD Signal Level
Optical Black
Pixel Period Dummy Black/Blanking Period Signal Period
SHR Input
SHV Input
CLP2 Input
(Internal)
AGC Output
SH-Pulse
(Input)
OBCLP Input
(Internal) BLK
BLK-PULSE
(Input)
DRIVE-OUT
(Output)
Optical Black Level Black Level
1.66 V
1.66 V
1.66 V
Figure 3. CCD Input Mode Timing Diagram
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
GND1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VCC3
GND3
A-SUB
D-SUB
DVSS
DVSS
DVDD
DVSS
AVDD
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC1
GND2
VCC2
A-SUB
DVDD
AVSS
AVSS
D-SUB
AVSS
AVSS
AVDD
AVDD
AVDD
AGND
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DGND
DVDD
NOTE A: A-SUB and D-SUB should be connected to Analog GND.
Figure 4. Typical Connection Diagram
Table 1. Standby, Output Enable
PIN PIN NAME FUNCTION OPERATION STAND-BY OR DISABLE
8 CDS-STBY Standby mode for CDS/AGC L H
31 AD-STBY Standby mode for AD converter L H
30 OE AD output L H
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
NOTE A: The 0.1 µF capacitors are necessary when you need to protect the noise.
SHR
SH-PULSE
PIN
AGC
SH SH
SH
CLP1
CLP2
SHLPF
AGCCLP
BLK
VRB
VRT
Auto
Calibration
Circuit
DRV
CLK
Upper
Sampling
Comparators
+
–
S&H
DAC
Upper
Data
Latch
Upper
Data
Latch
Lower
Data
Latch
Lower
Sampling
Comparators
Lower
Data
Latch
Reference
Voltage
Clock
Generator
DATA-IN
CLP2
OFFSET-IN
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SHV AGCGAIN AGCCLP
OBCLP
BLK-PULSE
VRB-OUT
VRT-OUT
CDS-STBY
DRIVE-OUT
RESET
VIN
VRB-IN
VRT-IN
AD-STBY
OE
(see Note A)
(see
Note A)
CCD-IN
0.1 µF
1 µF
1 µF
Figure 5. Typical Application
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
CDS/AGC signal processor
The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled
and held during both the reset reference interval and the video signal interval. By subtracting two resulting
voltage levels, the CDS removes low frequency noise from the output of the CCD sensor. Two sample/hold
control pulses (SHR and SHV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLC976. The AC coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLP2 input. The bias at the input to the TLC976 is set
to 2.7 V at VCC = 4.75 V. Normally, the CLP2 is applied at the sensor’s line rate.
The signal is sent to AGC after the CDS function is complete. The AGC gain can be adjusted from 5 dB to 39
dB by applying variable dc voltage from 0 V to 3 V at the AGCGAIN terminal.
A low-pass filter is installed at the AGC output to improve signal-to-noise ratio. After its output settles, it is
sampled and held by the SH-PULSE input for digitization. The SH-PULSE should synchronize with the ADC
clock.
The basic black level reference is established by clamping the AGC output to 1.66 V internally by the OBCLP
input during the optical black pixel period. A capacitor of 0.1 µF should be connected to the AGCCLP pin.
To prevent the black level from falling below the basic black level (1.66 V) during the blanking period, the AGC
output level is kept at 1.66 V by the BLK PULSE input. It is recommended that the BLK PULSE be kept low during
the entire blanking period.
The DRV block drives the ADC and adjusts the signal offset at the DRIVE OUT output. The offset can be
adjusted from –450 mV to 550 mV by applying control voltage on the OFFSET pin.
The VRT (3.5 V) and VRB (1.5 V) outputs provide voltage references for the ADC. They should be connected
to the VRT-IN and VRB-IN input pins externally.
analog-to-digital converter (ADC)
The A/DC in the TLC976 performs high-speed analog-to-digital conversion with 10-bit resolution using
semi-flash technique. The latency of the data output valid is 2.5 clocks.
Table 2. ADC Output Code
INPUT VOLTAGE
STEPS
DIGITAL OUTPUT CODE
INPUT
VOLTAGE
STEPS
MSB LSB
VRT
•
•
•
•
•
•
•
•
•
•
VRB
0
•
•
•
•
511
512
•
•
•
•
1023
1111111111
•
•
•
•
1000000000
0111111111
•
•
•
•
0000000000
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
twl
twh
tpd
CLOCK
INPUT SIGNAL
DATA OUTPUT N–3
NN+1 N+2 N+3 N+4
N–2 N–1 N N+1
Figure 6. ADC Operation Sequence
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
ADC internal calibration
start-up calibration at power up
After power is turned on, the start-up calibration starts under the following conditions:
1. The voltage between VRT and VRB is over 1 V when the voltage between AVDD and A VSS is over 2.5 V.
2. The voltage between DVDD and DVSS is over 2.5 V.
3. The RESET terminal (pin 26) is high.
4. The AD-STBY terminal (pin 31) is low.
The calibration sequence starts after condition 2 is met (see Figure 7). The following equation calculates the
time required for the start-up calibration after the above conditions are met.
Start-up calibration time = main clock pulse period × 16 × 16384
For example, if the main clock frequency is 15 MHz, the time required for startup calibration is 17.5 ms.
5 V
2.5 V 1 V
Reset = HIGH, AD-STBY = LOW
AVDD
VRT
DVDD
VRB
CALIBRATION START
Figure 7. Start-Up Calibration
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
start-up calibration using RESET terminal
If start-up characteristics are not stable, the start-up calibration can be performed using the AD-STBY terminal
(pin 31) or the RESET terminal (pin 26). Start-up calibration can be initiated properly by connecting RC
components to the RESET pin as shown in Figure 8. The RC components delay the start-up until the supply
voltage stablizes.
26
RESET
AVDD
AVSS
R
C
MAVDD
VRT
VRB
RESET
(t)
Figure 8. Start-Up Calibration Using RESET Terminal
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PIN SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: B. All linear dimensions are in millimeters.
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold protrusion not to exceed 0,15.
E. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC976CDGG OBSOLETE TSSOP DGG 56 TBD Call TI Call TI
TLC976CDGGR OBSOLETE TSSOP DGG 56 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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