TL/F/6037
MM54C922/MM74C922 16-Key Encoder, MM54C923/MM74C923 20-Key Encoder
July 1993
MM54C922/MM74C922 16-Key Encoder
MM54C923/MM74C923 20-Key Encoder
General Description
These CMOS key encoders provide all the necessary logic
to fully encode an array of SPST switches. The keyboard
scan can be implemented by either an external clock or
external capacitor. These encoders also have on-chip pull-
up devices which permit switches with up to 50 kXon resist-
ance to be used. No diodes in the switch array are needed
to eliminate ghost switches. The internal debounce circuit
needs only a single external capacitor and can be defeated
by omitting the capacitor. A Data Available output goes to a
high level when a valid keyboard entry has been made. The
Data Available output returns to a low level when the en-
tered key is released, even if another key is depressed. The
Data Available will return high to indicate acceptance of the
new key after a normal debounce period; this two-key roll-
over is provided between any two switches.
An internal register remembers the last key pressed even
after the key is released. The TRI-STATEÉoutputs provide
for easy expansion and bus operation and are LPTTL com-
patible.
Features
Y50 kXmaximum switch on resistance
YOn or off chip clock
YOn-chip row pull-up devices
Y2 key roll-over
YKeybounce elimination with single capacitor
YLast key register at outputs
YTRI-STATE outpust LPTTL compatible
YWide supply range 3V to 15V
YLow power consumption
Connection Diagrams
Pin Assignment for
Dual-In-Line Package
TL/F/6037–1
Top View
Order Number MM54C922 or
MM74C922
Pin Assignment
for SOIC
TL/F/6037–14
Top View
Order Number MM74C922
Pin Assignment for
DIP and SOIC Package
TL/F/6037–2
Top View
Order Number MM54C923 or
MM74C923
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin VCC b0.3V to VCC a0.3V
Operating Temperature Range
MM54C922, MM54C923 b55§Ctoa
125§C
MM74C922, MM74C923 b40§Ctoa
85§C
Storage Temperature Range b65§Ctoa
150§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating VCC Range 3V to 15V
VCC 18V
Lead Temperature
(Soldering, 10 seconds) 260§C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
VTaPositive-Going Threshold Voltage VCC e5V, IIN t0.7 mA 3.0 3.6 4.3 V
at Osc and KBM Inputs VCC e10V, IIN t1.4 mA 6.0 6.8 8.6 V
VCC e15V, IIN t2.1 mA 9.0 10 12.9 V
VTbNegative-Going Threshold Voltage VCC e5V, IIN t0.7 mA 0.7 1.4 2.0 V
at Osc and KBM Inputs VCC e10V, IIN t1.4 mA 1.4 3.2 4.0 V
VCC e15V, IIN t2.1 mA 2.1 5 6.0 V
VIN(1) Logical ‘‘1’’ Input Voltage, VCC e5V 3.5 4.5 V
Except Osc and KBM Inputs VCC e10V 8.0 9 V
VCC e15V 12.5 13.5 V
VIN(0) Logical ‘‘0’’ Input Voltage, VCC e5V 0.5 1.5 V
Except Osc and KBM Inputs VCC e10V 1 2 V
VCC e15V 1.5 2.5 V
Irp Row Pull-Up Current at Y1, Y2, VCC e5V, VIN e0.1 VCC b2b5mA
Y3, Y4 and Y5 Inputs VCC e10V b10 b20 mA
VCC e15V b22 b45 mA
VOUT(1) Logical ‘‘1’’ Output Voltage VCC e5V, IOeb
10 mA 4.5 V
VCC e10V, IOeb
10 mA9 V
V
CC e15V, IOeb
10 mA 13.5 V
VOUT(0) Logical ‘‘0’’ Output Voltage VCC e5V, IOe10 mA 0.5 V
VCC e10V, IOe10 mA1V
V
CC e15V, IOe10 mA 1.5 V
Ron Column ‘‘ON’’ Resistance at VCC e5V, VOe0.5V 500 1400 X
X1, X2, X3 and X4 Outputs VCC e10V, VOe1V 300 700 X
VCC e15V, VOe1.5V 200 500 X
ICC Supply Current VCC e5V 0.55 1.1 mA
Osc at 0V, (one Y low) VCC e10V 1.1 1.9 mA
VCC e15V 1.7 2.6 mA
IIN(1) Logical ‘‘1’’ Input Current VCC e15V, VIN e15V 0.005 1.0 mA
at Output Enable
IIN(0) Logical ‘‘0’’ Input Current VCC e15V, VIN e0V b1.0 b0.005 mA
at Output Enable
CMOS/LPTTL INTERFACE
VIN(1) Logical ‘‘1’’ Input Voltage, 54C, VCC e4.5V VCC b1.5 V
Except Osc and KBM Inputs 74C, VCC e4.75V VCC b1.5 V
VIN(0) Logical ‘‘0’’ Input Voltage, 54C, VCC e4.5V 0.8 V
Except Osc and KBM Inputs 74C, VCC e4.75V 0.8 V
VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e4.5V 2.4 V
IOeb
360 mA
74C, VCC e4.75V 2.4 V
IOeb
360 mA
VOUT(0) Logical ‘‘0’’ Output Voltage 54C, VCC e4.5V 0.4 V
IOeb
360 mA
74C, VCC e4.75V 0.4 V
IOeb
360 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise specified (Continued)
Symbol Parameter Conditions Min Typ Max Units
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE Output Source Current VCC e5V, VOUT e0V, b1.75 b3.3 mA
(P-Channel) TAe25§C
ISOURCE Output Source Current VCC e10V, VOUT e0V, b8b15 mA
(P-Channel) TAe25§C
ISINK Output Sink Current VCC e5V, VOUT eVCC,1.75 3.6 mA
(N-Channel) TAe25§C
ISINK Output Sink Current VCC e10V, VOUT eVCC,816 mA
(N-Channel) TAe25§C
AC Electrical Characteristics*TAe25§C, CLe50 pF, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
tpd0,t
pd1 Propagation Delay Time to CLe50 pF
(Figure 1)
Logical ‘‘0’’ or Logical ‘‘1’’ VCC e5V 60 150 ns
from D.A. VCC e10V 35 80 ns
VCC e15V 25 60 ns
t0H,t
1H Propagation Delay Time from RLe10k, CLe10 pF
(Figure 2)
Logical ‘‘0’’ or Logical ‘‘1’’ VCC e5V, RLe10k 80 200 ns
into High Impedance State VCC e10V, CLe10 pF 65 150 ns
VCC e15V 50 110 ns
tH0,t
H1 Propagation Delay Time from RLe10k, CLe50 pF
(Figure 2)
High Impedance State to a VCC e5V, RLe10k 100 250 ns
Logical ‘‘0’’ or Logical ‘‘1’’ VCC e10V, CLe50 pF 55 125 ns
VCC e15V 40 90 ns
CIN Input Capacitance Any Input (Note 2) 5 7.5 pF
COUT TRI-STATE Output Capacitance Any Output (Note 2) 10 pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Switching Time Waveforms
TL/F/6037–3
T1 &T2 &RC, T3 &0.7 RC, where R &10k and C is external capacitor at KBM input.
FIGURE 1
TL/F/6037–4
FIGURE 2
3
Block Diagram
TL/F/6037–5
Truth Table
Switch 012345678910111213141516171819
Position Y1,X1 Y1,X2 Y1,X3 Y1,X4 Y2,X1 Y2,X2 Y2,X3 Y2,X4 Y3,X1 Y3,X2 Y3,X3 Y3,X4 Y4,X1 Y4,X2 Y4,X3 Y4,X4 Y5*,X1 Y5*,X2 Y5*,X3 Y5*,X4
D
AA0101010101010101 0 1 0 1
TB0011001100110011 0 0 1 1
AC0000111100001111 0 0 0 0
OD0000000011111111 0 0 0 0
UE*0000000000000000 1 1 1 1
T
*Omit for MM54C922/MM74C922
4
Typical Performance Characteristics
Typical Irp vs VIN at
Any Y Input
TL/F/6037–6
Typical Ron vs VOUT at
Any X Output
TL/F/6037–7
Typical FSCAN vs COSC
TL/F/6037–8
Typical Debounce Period
vs CKBM
TL/F/6037–9
Typical Applications
Synchronous Handshake (MM74C922)
TL/F/6037–10
Synchronous Data Entry Onto Bus (MM74C922)
TL/F/6037–11
Outputs are enabled when valid entry is made and
go into TRI-STATE when key is released.
Note 3: The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz.
5
Typical Applications (Continued)
Asynchronous Data Entry Onto Bus (MM74C922)
TL/F/6037–12
Outputs are in TRI-STATE until key is pressed, then data is placed on bus.
When key is released, outputs return to TRI-STATE.
Expansion to 32 Key Encoder (MM74C922)
TL/F/6037–13
Theory of Operation
The MM74C922/MM74C923 Keyboard Encoders imple-
ment all the logic necessary to interface a 16 or 20 SPST
key switch matrix to a digital system. The encoder will con-
vert a key switch closer to a 4(MM74C922) or
5(MM74C923) bit nibble. The designer can control both the
keyboard scan rate and the key debounce period by altering
the oscillator capacitor, COSE, and the key bounce mask
capacitor, CMSK. Thus, the MM74C922/MM74C923’s per-
formance can be optimized for many keyboards.
The keyboard encoders connect to a switch matrix that is 4
rows by 4 columns (MM74C922) or 5 rows by 4 columns
(MM74C923). When no keys are depressed, the row inputs
are pulled high by internal pull-ups and the column outputs
sequentially output a logic ‘‘0’’. These outputs are open
drain and are therefore low for 25% of the time and other-
wise off. The column scan rate is controlled by the oscillator
input, which consists of a Schmitt trigger oscillator, a 2-bit
counter, and a 2– 4-bit decoder.
When a key is depressed, key 0, for example, nothing will
happen when the X1 input is off, since Y1 will remain high.
When the X1 column is scanned, X1 goes low and Y1 will go
low. This disables the counter and keeps X1 low. Y1 going
low also initiates the key bounce circuit timing and locks out
the other Y inputs. The key code to be output is a combina-
tion of the frozen counter value and the decoded Y inputs.
Once the key bounce circuit times out, the data is latched,
and the Data Available (DAV) output goes high.
If, during the key closure the switch bounces, Y1 input will
go high again, restarting the scan and resetting the key
bounce circuitry. The key may bounce several times, but as
soon as the switch stays low for a debounce period, the
closure is assumed valid and the data is latched.
A key may also bounce when it is released. To ensure that
the encoder does not recognize this bounce as another key
closure, the debounce circuit must time out before another
closure is recognized.
The two-key roll-over feature can be illustrated by assuming
a key is depressed, and then a second key is depressed.
Since all scanning has stopped, and all other Y inputs are
disabled, the second key is not recognized until the first key
is lifted and the key bounce circuitry has reset.
The output latches feed TRI-STATE, which is enabled when
the Output Enable (OE) input is taken low.
6
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C922J or MM74C922J
NS Package Number J18A
Ceramic Dual-In-Line Package (J)
Order Number MM54C923J or MM74C923J
NS Package Number J20A
7
Physical Dimensions inches (millimeters) (Continued)
Plastic Small Outline I.C. Package (M)
Order Number MM74C922M or MM74C923M
NS Package Number M20B
8
Physical Dimensions inches (millimeters) (Continued)
Plastic Dual-In-Line Package (N)
Order Number MM54C922N or MM74C922N
NS Package Number N18A
9
MM54C922/MM74C922 16-Key Encoder, MM54C923/MM74C923 20-Key Encoder
Physical Dimensions inches (millimeters) (Continued)
Plastic Dual-In-Line Package (N)
Order Number MM54C923N or MM74C923N
NS Package Number N20A
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