MM54C922/MM74C922 16-Key Encoder MM54C923/MM74C923 20-Key Encoder General Description These CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan can be implemented by either an external clock or external capacitor. These encoders also have on-chip pullup devices which permit switches with up to 50 kX on resistance to be used. No diodes in the switch array are needed to eliminate ghost switches. The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor. A Data Available output goes to a high level when a valid keyboard entry has been made. The Data Available output returns to a low level when the entered key is released, even if another key is depressed. The Data Available will return high to indicate acceptance of the new key after a normal debounce period; this two-key rollover is provided between any two switches. An internal register remembers the last key pressed even after the key is released. The TRI-STATEE outputs provide for easy expansion and bus operation and are LPTTL compatible. Features Y Y Y Y Y Y Y Y Y 50 kX maximum switch on resistance On or off chip clock On-chip row pull-up devices 2 key roll-over Keybounce elimination with single capacitor Last key register at outputs TRI-STATE outpust LPTTL compatible Wide supply range Low power consumption 3V to 15V Connection Diagrams Pin Assignment for SOIC Pin Assignment for Dual-In-Line Package Pin Assignment for DIP and SOIC Package TL/F/6037 - 14 Top View TL/F/6037-1 Order Number MM74C922 Top View TL/F/6037 - 2 Order Number MM54C922 or MM74C922 Top View Order Number MM54C923 or MM74C923 TRI-STATEE is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/6037 RRD-B30M105/Printed in U. S. A. MM54C922/MM74C922 16-Key Encoder, MM54C923/MM74C923 20-Key Encoder July 1993 Absolute Maximum Ratings (Note 1) Voltage at Any Pin VCC b 0.3V to VCC a 0.3V Operating Temperature Range MM54C922, MM54C923 MM74C922, MM74C923 b 65 C to a 150 C Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 3V to 15V 18V VCC Lead Temperature (Soldering, 10 seconds) 260 C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units VT a Positive-Going Threshold Voltage at Osc and KBM Inputs VCC e 5V, IIN t 0.7 mA VCC e 10V, IIN t 1.4 mA VCC e 15V, IIN t 2.1 mA 3.0 6.0 9.0 3.6 6.8 10 4.3 8.6 12.9 V V V VTb Negative-Going Threshold Voltage at Osc and KBM Inputs VCC e 5V, IIN t 0.7 mA VCC e 10V, IIN t 1.4 mA VCC e 15V, IIN t 2.1 mA 0.7 1.4 2.1 1.4 3.2 5 2.0 4.0 6.0 V V V VIN(1) Logical ``1'' Input Voltage, Except Osc and KBM Inputs VCC e 5V VCC e 10V VCC e 15V 3.5 8.0 12.5 4.5 9 13.5 VIN(0) Logical ``0'' Input Voltage, Except Osc and KBM Inputs VCC e 5V VCC e 10V VCC e 15V Irp Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs VCC e 5V, VIN e 0.1 VCC VCC e 10V VCC e 15V VOUT(1) Logical ``1'' Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VCC e 15V, IO e b10 mA VOUT(0) Logical ``0'' Output Voltage VCC e 5V, IO e 10 mA VCC e 10V, IO e 10 mA VCC e 15V, IO e 10 mA Ron Column ``ON'' Resistance at X1, X2, X3 and X4 Outputs VCC e 5V, VO e 0.5V VCC e 10V, VO e 1V VCC e 15V, VO e 1.5V ICC Supply Current Osc at 0V, (one Y low) IIN(1) IIN(0) CMOS TO CMOS V V V 0.5 1 1.5 1.5 2 2.5 V V V b2 b 10 b 22 b5 b 20 b 45 mA mA mA 4.5 9 13.5 V V V 0.5 1 1.5 V V V 500 300 200 1400 700 500 X X X VCC e 5V VCC e 10V VCC e 15V 0.55 1.1 1.7 1.1 1.9 2.6 mA mA mA Logical ``1'' Input Current at Output Enable VCC e 15V, VIN e 15V 0.005 1.0 mA Logical ``0'' Input Current at Output Enable VCC e 15V, VIN e 0V b 1.0 b 0.005 mA CMOS/LPTTL INTERFACE VIN(1) Logical ``1'' Input Voltage, Except Osc and KBM Inputs 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ``0'' Input Voltage, Except Osc and KBM Inputs 54C, VCC e 4.5V 74C, VCC e 4.75V VOUT(1) Logical ``1'' Output Voltage 54C, VCC e 4.5V IO e b360 mA 74C, VCC e 4.75V IO e b360 mA VOUT(0) Logical ``0'' Output Voltage 54C, VCC e 4.5V IO e b360 mA 74C, VCC e 4.75V IO e b360 mA VCC b 1.5 VCC b 1.5 V V 0.8 0.8 V V 2.4 V 2.4 V 0.4 V 0.4 V Note 1: ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits. The table of ``Electrical Characteristics'' provides conditions for actual device operation. 2 DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified (Continued) Symbol Parameter Conditions Min Typ Max Units OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current (P-Channel) VCC e 5V, VOUT e 0V, TA e 25 C ISOURCE Output Source Current (P-Channel) ISINK ISINK b 1.75 b 3.3 mA VCC e 10V, VOUT e 0V, TA e 25 C b8 b 15 mA Output Sink Current (N-Channel) VCC e 5V, VOUT e VCC, TA e 25 C 1.75 3.6 mA Output Sink Current (N-Channel) VCC e 10V, VOUT e VCC, TA e 25 C 8 16 mA AC Electrical Characteristics* TA e 25 C, CL e 50 pF, unless otherwise noted Symbol Typ Max Units Propagation Delay Time to Logical ``0'' or Logical ``1'' from D.A. CL e 50 pF (Figure 1) VCC e 5V VCC e 10V VCC e 15V 60 35 25 150 80 60 ns ns ns Propagation Delay Time from Logical ``0'' or Logical ``1'' into High Impedance State RL e 10k, CL e 10 pF (Figure 2) VCC e 5V, RL e 10k VCC e 10V, CL e 10 pF VCC e 15V 80 65 50 200 150 110 ns ns ns Propagation Delay Time from High Impedance State to a Logical ``0'' or Logical ``1'' RL e 10k, CL e 50 pF (Figure 2) VCC e 5V, RL e 10k VCC e 10V, CL e 50 pF VCC e 15V 100 55 40 250 125 90 ns ns ns CIN Input Capacitance Any Input (Note 2) 5 7.5 pF COUT TRI-STATE Output Capacitance Any Output (Note 2) 10 tpd0, tpd1 t0H, t1H tH0, tH1 Parameter Conditions Min pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits. The table of ``Electrical Characteristics'' provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Switching Time Waveforms TL/F/6037 - 4 TL/F/6037 - 3 T1 & T2 & RC, T3 & 0.7 RC, where R & 10k and C is external capacitor at KBM input. FIGURE 1 3 FIGURE 2 Block Diagram TL/F/6037 - 5 Truth Table Switch Position D A T A O U T A B C D E* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Y1,X1 Y1,X2 Y1,X3 Y1,X4 Y2,X1 Y2,X2 Y2,X3 Y2,X4 Y3,X1 Y3,X2 Y3,X3 Y3,X4 Y4,X1 Y4,X2 Y4,X3 Y4,X4 Y5*,X1 Y5*,X2 Y5*,X3 Y5*,X4 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 *Omit for MM54C922/MM74C922 4 0 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 0 1 Typical Performance Characteristics Typical Irp vs VIN at Any Y Input Typical Ron vs VOUT at Any X Output TL/F/6037 - 6 TL/F/6037 - 7 Typical Debounce Period vs CKBM Typical FSCAN vs COSC TL/F/6037 - 9 TL/F/6037 - 8 Typical Applications Synchronous Handshake (MM74C922) Synchronous Data Entry Onto Bus (MM74C922) TL/F/6037 - 10 TL/F/6037 - 11 Outputs are enabled when valid entry is made and go into TRI-STATE when key is released. Note 3: The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz. 5 Typical Applications (Continued) Asynchronous Data Entry Onto Bus (MM74C922) TL/F/6037 - 12 Outputs are in TRI-STATE until key is pressed, then data is placed on bus. When key is released, outputs return to TRI-STATE. Expansion to 32 Key Encoder (MM74C922) TL/F/6037 - 13 Theory of Operation low also initiates the key bounce circuit timing and locks out the other Y inputs. The key code to be output is a combination of the frozen counter value and the decoded Y inputs. Once the key bounce circuit times out, the data is latched, and the Data Available (DAV) output goes high. If, during the key closure the switch bounces, Y1 input will go high again, restarting the scan and resetting the key bounce circuitry. The key may bounce several times, but as soon as the switch stays low for a debounce period, the closure is assumed valid and the data is latched. A key may also bounce when it is released. To ensure that the encoder does not recognize this bounce as another key closure, the debounce circuit must time out before another closure is recognized. The two-key roll-over feature can be illustrated by assuming a key is depressed, and then a second key is depressed. Since all scanning has stopped, and all other Y inputs are disabled, the second key is not recognized until the first key is lifted and the key bounce circuitry has reset. The output latches feed TRI-STATE, which is enabled when the Output Enable (OE) input is taken low. The MM74C922/MM74C923 Keyboard Encoders implement all the logic necessary to interface a 16 or 20 SPST key switch matrix to a digital system. The encoder will convert a key switch closer to a 4(MM74C922) or 5(MM74C923) bit nibble. The designer can control both the keyboard scan rate and the key debounce period by altering the oscillator capacitor, COSE, and the key bounce mask capacitor, CMSK. Thus, the MM74C922/MM74C923's performance can be optimized for many keyboards. The keyboard encoders connect to a switch matrix that is 4 rows by 4 columns (MM74C922) or 5 rows by 4 columns (MM74C923). When no keys are depressed, the row inputs are pulled high by internal pull-ups and the column outputs sequentially output a logic ``0''. These outputs are open drain and are therefore low for 25% of the time and otherwise off. The column scan rate is controlled by the oscillator input, which consists of a Schmitt trigger oscillator, a 2-bit counter, and a 2 - 4-bit decoder. When a key is depressed, key 0, for example, nothing will happen when the X1 input is off, since Y1 will remain high. When the X1 column is scanned, X1 goes low and Y1 will go low. This disables the counter and keeps X1 low. Y1 going 6 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C922J or MM74C922J NS Package Number J18A Ceramic Dual-In-Line Package (J) Order Number MM54C923J or MM74C923J NS Package Number J20A 7 Physical Dimensions inches (millimeters) (Continued) Plastic Small Outline I.C. Package (M) Order Number MM74C922M or MM74C923M NS Package Number M20B 8 Physical Dimensions inches (millimeters) (Continued) Plastic Dual-In-Line Package (N) Order Number MM54C922N or MM74C922N NS Package Number N18A 9 MM54C922/MM74C922 16-Key Encoder, MM54C923/MM74C923 20-Key Encoder Physical Dimensions inches (millimeters) (Continued) Plastic Dual-In-Line Package (N) Order Number MM54C923N or MM74C923N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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