PRELIMINARY INFORMATION MK3771-17 VCXO and HDTV Set-Top Clock Source Description Features The MK3771-17 is a low cost, low jitter, high performance VCXO and clock synthesizer designed for set-top boxes and HDTV receivers. The on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by 100 ppm. Using ICS's patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 13.5 MHz crystal input to produce multiple output clocks including selectable BCLK, a selectable audio clock, two communications clocks, a 13.5 MHz clock, and three 27 MHz clocks. All clocks are frequency locked to the 27.00 MHz output (and to each other) with zero ppm error, so any output can be used as the VCXO output. * Packaged in 28 pin SSOP (QSOP) * HDTV frequencies of 74.25 and 74.175824 MHz * On-chip patented VCXO with pull range of 200ppm (minimum) * VCXO tuning voltage of 0 to 3.3 V * Supports Ethernet with 20 and 25 MHz clocks * Modem clocks of 11.0592 and 24.576 MHz option * Audio clocks support 32 kHz, 44.1 kHz, 48 kHz and 96 kHz sampling rates * Zero ppm synthesis error in all clocks (all exactly track 27MHz VCXO) * Uses an inexpensive 13.5 MHz crystal * Full CMOS output swings with 12 mA output drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * 3.3 V 5% operating supply Block Diagram 3 Output Buffer Audio Clock Output Buffer BCLK CS Output Buffer CCLK1 VIN Output Buffer CCLK2 Output Buffers 108 MHz or 27 MHz Output Buffer Output Buffer Output Buffer 54 MHz or 27 MHz AS2:0 BS1, BS0 X1 13.5 MHz pullable crystal X2 VS PLL Clock Synthesis Circuitry 2 Voltage Controlled Crystal Oscillator x8 PLL Divide Logic 27 MHz 13.5 MHz or 27 MHz 1 Revision 12289 Printed 1/10/0 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com MDS3771-17A PRELIMINARY INFORMATION MK3771-17 VCXO and HDTV Set-Top Clock Source Pin Assignment BS0 X2 X1 VDD VDD VIN VDD VDD CS GND GND BCLK VS ACLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Audio Clock (MHz) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AS2 AS1 AS0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 AS1 AS0 VCLK2 VCLK1 GND VCLK4 VDD AS2 GND GND VCLK3 CCLK1 BS1 CCLK2 ACLK 8.192 11.2896 12.288 16.9344 16.384 22.5792 18.432 24.576 VCXO Clocks (MHz) VS 0 M 1 VCLK1 27 27 27 VCLK2 27 54 27 VCLK3 27 13.5 27 VCLK4 108 108 27 B and C Clocks (MHz) BS1 BS0 CS 0 0 0 0 0 1 0 1 0 0 1 1 M 0 0 M 0 1 M 1 0 M 1 1 1 0 0 1 0 M 1 0 1 1 1 0 1 1 M 1 1 1 BCLK 74.175 74.175 74.25 74.25 5.06 5.06 10.12 10.12 48 48 48 14.318 14.318 14.318 CCLK1 20 11.0592 20 11.0592 20 11.0592 20 11.0592 20 7.3728 11.0592 20 7.3728 11.0592 CCLK2 25 24.576 25 24.576 25 24.576 25 24.576 25 24 24.576 25 28.636 24.576 0 = connect directly to GND M = leave unconnected (floating) 1 = connect directly to VDDIO X = don't care Pin Descriptions Number 1 2 3 4, 5, 7, 8, 22 6 9 10, 11,19,20,24 12 13 14 15 16 17 18 21 23 25 26 27 28 Name BS0 X2 X1 VDD VIN CS GND BCLK VS ACLK CCLK2 BS1 CCLK1 VCLK3 AS2 VCLK4 VCLK1 VCLK2 AS0 AS1 Type I XO XI P VI TI P O TI O O TI O O I O O O I I Description B Clock Select 0. Selects BCLK frequency. See table above. Internal pull-up. Crystal connection. Connect to a pullable 13.5 MHz crystal. Crystal connection. Connect to a pullable 13.5 MHz crystal. Connect to +3.3V. Analog control voltage for VCXO. Pulls outputs 100 ppm by varying from 0 to 3.3V. Communications Clock Select. Selects CCLK 1 and 2 per table above. Internal pull-up. Connect to ground. B Clock output. Determined by status of BS1, BS0. VCXO Clock Select. Selects frequencies on VCLK1-VCLK4 per table above. Audio Clock output. Determined by status of AS2:0 per table above. Communications Clock Output 2. Determined by status of CS per table above. B Clock Select 1. Selects BCLK frequency. See table above. Communications Clock output 1. Determined by status of CS per table above. VCXO Clock output 3. Can be either 27 or 13.5 MHz per table above. Audio Clock Select pin 2. Selects Audio clock on pin 14 per table above. Internal pull-up. VCXO Clock output 4. Can be either 27 or 108 MHz per table above. VCXO Clock output pin 1. Always 27 MHz. VCXO Clock output pin 2. Can be either 27 or 54 MHz per table above. Audio Clock Select pin 0. Selects Audio clock on pin 14. See table above. Internal pull-up. Audio Clock Select pin 1. Selects Audio clock on pin 14. See table above. Internal pull-up. Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections 2 Revision 12289 Printed 1/10/0 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com MDS3771-17A PRELIMINARY INFORMATION MK3771-17 VCXO and HDTV Set-Top Clock Source Electrical Specifications Parameter Conditions Minimum Typical Maximum Units 7 VDD+0.5 70 260 150 V V C C C 3.45 V V V V V V V V mA mA pF ppm V ABSOLUTE MAXIMUM RATINGS (note 1) Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Referenced to GND Referenced to GND -0.5 0 Max of 10 seconds -65 DC CHARACTERISTICS (VDD = 3.3V unless noted) Operating Voltage, VDD Input High Voltage, VIH, except TI pins Input Low Voltage, VIL, except TI pins Input High Voltage, VIH, all TI pins Input Low Voltage, VIL, all TI pins Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Short Circuit Current Input Capacitance Frequency synthesis error VIN, VCXO control voltage 3.15 2 3.30 0.8 VDD-0.5 0.5 IOH=-12mA IOL=12mA IOH=-8mA No Load, note 2 Each output 2.4 0.4 VDD-0.4 28 50 7 All clocks 0 3.3 0 AC CHARACTERISTICS (VDD = 3.3V unless noted) Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter, short term 27 MHz output pullability, note 3 Notes: 13.500000 0.8 to 2.0V 2.0 to 0.8V At VDD/2 0V VIN 3.3 V 1.5 1.5 60 40 100 300 140 MHz ns ns % ps ppm 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With all clocks at highest MHz. 3. With a pullable crystal that conforms to ICS' specifications External Components The MK3771-17 requires a minimum number of external components for proper operation. Use a low inductance ground plane, connect all GNDs to this. Connect 0.01F decoupling caps on pins 4, 5, 7, 8 and 22 directly to the ground plane, as close to the MK3771-17 as possible. A series termination resistor of 33 may be used for each clock output. The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a parallel mode, pullable, with load capacitance of 14 pF. See page 4 for crystal specifications. Please follow Application Note MAN05 for pullable crystal layout. 3 Revision 12289 Printed 1/10/0 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com MDS3771-17A PRELIMINARY INFORMATION MK3771-17 VCXO and HDTV Set-Top Clock Source Pullable Crystal Specifications: Frequency Correlation (load) Capacitance C0/C1 ESR Operating Temperature Initial Accuracy Temperature plus Aging Stability 13.500000 MHz 14 pF 240 max 35 max 0 to 70 C 20 ppm 50 ppm Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.) 28 pin SSOP E1 Symbol A A1 b c D e E E1 L E D A1 c e b Inches Min Max 0.053 0.069 0.004 0.010 0.008 0.012 0.007 0.010 0.386 0.394 .025 BSC 0.228 0.244 0.150 0.157 0.016 0.050 Millimeters Min Max 1.35 1.75 0.102 0.254 0.203 0.305 0.190 0.254 9.804 10.008 0.635 BSC 5.791 6.198 3.810 3.988 0.406 1.270 A L Ordering Information Part/Order Number MK3771-17R MK3771-17RTR Marking MK3771-17R MK3771-17R Shipping packaging tubes tape and reel Package Temperature 28 pin SSOP (QSOP) 0-70 C 28 pin SSOP (QSOP) 0-70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 4 Revision 12289 Printed 1/10/0 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel * www.icst.com MDS3771-17A