Philips
Semiconductors
PCA9540B
2-channel I2C multiplexer
2004 Sep 29
INTEGRATED CIRCUITS
Product data sheet
Supersedes data of 2004 Apr 13
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2
2004 Sep 29
FEATURES
•1-of-2 bi-directional translating multiplexer
•I2C interface logic; compatible with SMBus standards
•Channel selection via I2C-bus
•Power up with all multiplexer channels deselected
•Low RdsON switches
•Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
•No glitch on power-up
•Supports hot insertion
•Low stand-by current
•Operating power supply voltage range of 2.3 V to 5.5 V
•5 V tolerant Inputs
•0 to 400 kHz clock frequency
•ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V per JESD22-C101
•Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
•Packages Offered: SO8, TSSOP8
DESCRIPTION
The PCA9540B is a 1-of-2 bi-directional translating multiplexer,
controlled via the I2C-bus. The SCL/SDA upstream pair fans out to
two SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register .
A power-on reset function puts the registers in their default state and
initializes the I2C state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9540B. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors can pull the bus up to the desired voltage
level for this channel. All I/O pins are 5 V tolerant.
The PCA9540B has replaced the PCA9540 and all designs must
migrate to the PCA9540B. PCA9540B samples can be requested
from www.philipslogic.com/products/I2Cmuxes/.
PIN CONFIGURATION
1
2
3
45
6
7
8SCL
SDA
VDD
SD0
SC1
SD1
SC0
VSS
SW00491
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1 SCL Serial clock line
2 SDA Serial data line
3 VDD Supply voltage
4 SD0 Serial data 0
5 SC0 Serial clock 0
6 VSS Supply ground
7 SD1 Serial data 1
8 SC1 Serial clock 1
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
8-Pin Plastic SO –40 °C to +85 °C PCA9540BD PA9540B SOT96-1
8-Pin Plastic TSSOP –40 °C to +85 °C PCA9540BDP 9540B SOT505-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 3
BLOCK DIAGRAM
SW02211
SC0
SC1
SD0
SD1
VSS
SCL
VDD
SDA
Input
Filter
PCA9540B
Power-on
Reset
I2C-Bus
Control
SWITCH CONTROL LOGIC
Figure 2. Block diagram
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 4
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9540B
is shown in Figure 3.
0 0
0 0
SW00713
111 R/W
FIXED
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9540B which will be
stored in the Control Register. If multiple bytes are received by the
PCA9540B, it will save the last byte received. This register can be
written and read via the I2C bus.
X B2 B1 B0
CHANNEL SELECTION BITS
X
SW00839
X
(READ/WRITE)
6 5 4 2 1 0 7 3
X X
ENABLE BIT
Figure 4. Control register
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9540B
has been addressed. The 2 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, the channel will become active after a stop condition has
been placed on the I2C bus. This ensures that all SCx/SDx lines will
be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
D7 D6 D5 D4 D3 B2 B1 B0 COMMAND
X X X X X 0 X X No channel selected
X X X X X 1 0 0 Channel 0 enabled
X X X X X 1 0 1 Channel 1 enabled
X X X X X 1 1 X No channel selected
0 0 0 0 0 0 0 0 No channel selected;
power-up default state
POWER-ON RESET
When power is applied to VDD, an internal Power-On Reset holds
the PCA9540B in a reset condition until VDD has reached VPOR. At
this point, the reset condition is released and the PCA9540B
registers and I2C state machine are initialized to their default states,
all zeroes causing all the channels to be deselected. Thereafter,
VDD must be lowered below 0.2 V to reset the device.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9540B are constructed such
that the VDD voltage can be used to limit the maximum voltage that
will be passed from one I2C bus to another.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Vpass vs. VDD
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vpass
VDD
MINIMUM
TYPICAL
MAXIMUM
SW00820
2.0
Figure 5. Vpass voltage
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9540B to act as a voltage translator, the Vpass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then Vpass should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that Vpass (max.) will be at 2.7 V when the
PCA9540B supply voltage is 3.5 V or lower so the PCA9540B
supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see Figure
12).
More Information can be found in Application Note AN262
PCA954X
family of I
2
C/SMBus multiplexers and switches.
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 5
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 6).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 6. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
System configuration
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 8).
SDA
SCL
SW00365
S P
SDA
SCL
START condition STOP condition
Figure 7. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I2C
MULTIPLEXER
SLAVE
Figure 8. System configuration
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 6
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
12 89
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 9. Acknowledgement on the I2C-bus
SDA S0A A11 1 0 00 0
SLAVE ADDRESS
start condition R/W acknowledge
from slave acknowledge
from slave
B0
CONTROL REGISTER
P
SW00800
B1B2XXXXX
Figure 10. WRITE control register
SDA S1A NA
11100 0 0
start condition R/W acknowledge
from slave
CONTROL REGISTER
P
stop condition
last byte
SW00499
SLAVE ADDRESS
no acknowledge
from master
B0B1B2XXXXX
Figure 11. READ control register
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 7
TYPICAL APPLICATION
PCA9540B
V = 2.7 – 5.5 V
SD0
SC0
V = 2.7 – 5.5 V
SD1
SC1
VSS
SDA
SCL
VDD = 3.3 V
VDD = 2.7 – 5.5 V
I2C/SMBus MASTER
SW02212
SDA
SCL CHANNEL 0
CHANNEL 1
Figure 12. Typical application
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 8
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
VDD DC supply voltage –0.5 to +7.0 V
VIDC input voltage –0.5 to +7.0 V
IIDC input current ±20 mA
IODC output current ±25 mA
IDD Supply current ±100 mA
ISS Supply current ±100 mA
Ptot total power dissipation 400 mW
Tstg Storage temperature range –60 to +150 °C
Tamb Operating ambient temperature –40 to +85 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
DC CHARACTERISTICS
VDD = 2.3 to 3.6 V ; V SS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified. (See page 9 for VDD = 3.6 to 5.5 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
Supply
VDD Supply voltage 2.3 — 3.6 V
IDD Supply current Operating mode; VDD = 3.6 V ;
no load; VI = VDD or VSS;
fSCL = 100 kHz — 20 50 µA
Istb Standby current Standby mode; VDD = 3.6 V ;
no load; VI = VDD or VSS; fSLC = 0 kHz — 0.1 1 µA
VPOR Power-on reset voltage (Note 1) no load; VI = VDD or VSS — 1.6 2.1 V
Input SCL; input/output SDA
VIL LOW-level input voltage –0.5 — 0.3VDD V
VIH HIGH-level input voltage 0.7VDD — 6 V
IO
LOW level out
p
ut current
VOL = 0.4 V 3 — — mA
I
OL
LOW
-
le
v
el
o
u
tp
u
t
c
u
rrent
VOL = 0.6 V 6 — — mA
ILLeakage current VI = VDD or VSS –1 — +1 µA
CiInput capacitance VI = VSS — 7 8 pF
Pass Gate
RO
Switch resistance
VCC = 3.0 to 3.6 V, VO = 0.4 V, IO = 15 mA 511 31
Ω
R
ON
S
w
itch
resistance
VCC = 2.3 to 2.7 V, VO = 0.4 V, IO = 10 mA 7 16 55
Ω
Vswin = VDD = 3.3 V; Iswout = –100 µA — 1.9 —
V
Switch out
p
ut voltage
Vswin = VDD = 3.0 to 3.6 V; Iswout = –100 µA 1.6 — 2.8
V
V
Pass
S
w
itch
o
u
tp
u
t
v
oltage
Vswin = VDD = 2.5 V; Iswout = –100 µA — 1.5 —
V
Vswin = VDD = 2.3 to 2.7 V; Iswout = –100 µA 1.1 — 2.0
ILLeakage current VI = VDD or VSS –1 — +1 µA
Cio Input/output capacitance VI = VSS — 2.5 5 pF
NOTE:
1. VDD must be lowered to 0.2 V in order to reset part.
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 9
DC CHARACTERISTICS
VDD = 3.6 to 5.5 V ; V SS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified. (See page 8 for VDD = 2.3 to 3.6 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
Supply
VDD Supply voltage 3.6 — 5.5 V
IDD Supply current Operating mode; VDD = 5.5 V ;
no load; VI = VDD or VSS;
fSCL = 100 kHz — 65 100 µA
Istb Standby current Standby mode; VDD = 5.5 V ;
no load; VI = VDD or VSS — 0.3 1 µA
VPOR1Power-on reset voltage no load; VI = VDD or VSS — 1.6 2.1 V
Input SCL; input/output SDA
VIL LOW-level input voltage –0.5 —0.3 VDD V
VIH HIGH-level input voltage 0.7 VDD — 6 V
IO
LOW level out
p
ut current
VOL = 0.4 V 3 — — mA
I
OL
LOW
-
le
v
el
o
u
tp
u
t
c
u
rrent
VOL = 0.6 V 6 — — µA
IIL LOW-level input current VI = VSS –1 — 1 mA
IIH HIGH-level input current VI = VDD –1 — 1 µA
CiInput capacitance VI = VSS — 6 8 pF
Pass Gate
RON Switch resistance VCC = 4.5 to 5.5 V, VO = 0.4 V, IO = 15 mA 4 9 24 Ω
V
Switch out
p
ut voltage
Vswin = VDD = 5.0 V; Iswout = –100 µA — 3.6 — V
V
Pass
S
w
itch
o
u
tp
u
t
v
oltage
Vswin = VDD = 4.5 to 5.5 V; Iswout = –100 µA 2.6 — 4.5 V
ILLeakage current VI = VDD or VSS –1 — +1 µA
Cio Input/output capacitance VI = VSS — 2.5 5 pF
NOTE:
1. VDD must be lowered to 0.2 V in order to reset part.
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 10
AC CHARACTERISTICS
SYMBOL PARAMETER STANDARD-MODE
I2C-BUS FAST-MODE
I2C-BUS UNIT
MIN MAX MIN MAX
tpd Propagation delay from SDA to SDn or SCL to SC n— 0.31— 0.31ns
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF Bus free time between a STOP and START condition 4.7 — 1.3 — µs
tHD;STA Hold time (repeated) ST AR T condition
After this period, the first clock pulse is generated 4.0 — 0.6 — µs
tLOW LOW period of the SCL clock 4.7 — 1.3 — µs
tHIGH HIGH period of the SCL clock 4.0 — 0.6 — µs
tSU;STA Set-up time for a repeated ST ART condition 4.7 — 0.6 — µs
tSU;STO Set-up time for ST OP condition 4.0 — 0.6 — µs
tHD;DAT Data hold time 023.45 020.9 µs
tSU;DAT Data set-up time 250 — 100 — ns
tRRise time of both SDA and SCL signals — 1000 20 + 0.1Cb3300 ns
tFFall time of both SDA and SCL signals — 300 20 + 0.1Cb3300 µs
CbCapacitive load for each bus line — 400 — 400 µs
tSP Pulse width of spikes which must be suppressed
by the input filter — 50 — 50 ns
tVD:DATL Data valid (HL)4— 1 — 1 µs
tVD:DATH Data valid (LH)4— 0.6 — 0.6 µs
tVD:ACK Data valid Acknowledge — 1 — 1 µs
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical RON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
4. Measurements taken with 1 kΩ pull-up resistor and 50 pF load.
tSP
tBUF
tHD;STA
PP S
tLOW tR
tHD;DAT
tF
tHIGH tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
SU00645
Figure 13. Definition of timing on the I2C-bus
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 11
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 12
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 13
REVISION HISTORY
Rev Date Description
_2 20040929 Product data sheet (9397 750 13731). Supersedes data of 2004 Apr 13 (9397 750 12918).
Modifications:
•Section “Control Register Definition” on page 4: add “No channel selected; power-up default state” row to
bottom of Table 1.
•Section “Power-on Reset” on page 4 re-written.
•AC characterists table on page 10: Add Note 4 and references to it at parameters tVD;DATL and tVD;DATH.
_1 20040413 Product data (9397 750 12918).
Philips Semiconductors Product data sheet
PCA9540B2-channel I2C multiplexer
2004 Sep 29 14
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Date of release: 09-04
Document order number: 9397 750 13731
Philips
Semiconductors
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III
