FIELD PROGRAMMABLE The FPSLICTM (Field Programmable System Level Integrated Circuit) family of devices incorporates up to 40,000 gates of AT40K FPGA, 36K bytes of SRAM, the 30 MIPS 8-bit AVR(R) RISC microcontroller core and fixed peripherals on a monolithic device. For the first time all the components of a typical system are available in a high-performance field-programmable device. * A monolithic device featuring: - 10K, 20K, or 40K gate FPGA - 30 MIPS microcontroller performance - Ultra-low power consumption - In-system reconfigurable * Completely integrated design tools including: - FPGA Integrated Development System - AVR Studio - Synthesis - Simulation - Co-verification * FPSLIC supports: - 10K to 40K system-level logic gates - Eight global clocks - Up to 304 programmable PCI-compliant I/O pins * Atmel's SRAM-based AT40K FPGA eight-sided logic cell architecture performs complex DSP functions without impacting bus resources * Discrete FreeRAMTM 10 ns dual-port SRAM blocks are located at the corners of each 4 x 4 cell FPGA sector. Locating these SRAM blocks throughout the array puts memory where it's needed, and supports high-performance FIFO designs * Atmel's AVR 8-bit RISC microcontroller architecture enables throughput in excess of 30 million instructions per second * 8-bit hardware multiplication accelerator enables AVR microcontroller to perform complex DSP operations quickly and efficiently * 32K byte dynamic allocation program memory - a 16K x 16 (32K x 8) block of 15 ns SRAM for program instruction storage. If not all 32K is required, program memory may be partitioned during design development into 4K x 8 blocks to provide additional data memory storage * 4K byte (4K x 8) data memory (may be increased by adding partitions from program memory) SYSTEM LEVEL INTEGRATED CIRCUIT FPSLIC FIELD PROGRAMMABLE SYSTEM LEVEL INTEGRATED CIRCUIT Atmel has solved the software problems of system integration, debug and testing, by providing a complete system development productivity environment. Co-verification(1) tools allow for concurrent software and hardware development and debug. Design problems are identified earlier in the design process allowing them to be fixed quickly, minimizing their impact on project schedules. CONVENTIONAL TIMELINE: H W/ SW D EVEL O PM EN T W I T H O U T C O - VER I F I C A T I O N HARDWARE DESIGN HARDWARE DEBUG SOFTWARE DESIGN SOFTWARE CODING PRODUCT FINISHED SOFTWARE DEBUG TIME-TO-MARKET FPSLIC TIMELINE: H W / SW D EVEL O PM EN T U SI N G C O - VER I F I C A T I O N HARDWARE DESIGN PROTOTYPE BUILD HARDWARE DEBUG SOFTWARE DESIGN SOFTWARE CODING PRODUCT FINISHED SOFTWARE DEBUG By combining industry-standard development tools and tried and tested design methodology the System DesignerTM software is a system architects dream. We have taken mature tools and combined them with standard third-party design entry and verification tools to provide the ideal environment for rapid, bug free development and "what if" analysis. Make trade-offs between software and hardware implementations of an algorithm. Save power by running complex DSP functions in FPGA instead of software. Reconfigure FPGA on-the-fly from the microcontroller to update your latest encryption algorithm. Create your product with the interfaces and peripheral on it needed to make your designs fly. System Designer TM CO-VERIFICATION HDL Entry HDLPlanner AVR StudioTM Code Entry Functional Co-Verification Waveform Viewer Debugger Technology Mapping Place & Route Bitstream Back-Annotated Co-Verification Waveform Viewer FPSLIC P RO GRAM M I N G UT I L I T I E S Atmel U.K., Ltd. Coliseum Business Centre Riverside Way, Camberley Surrey GU15 3YL, England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East, Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan TIME-TO-MARKET HDL Synthesis 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe PROTOTYPE BUILD FPGA IDS Corporate Headquarters AVR Programming Code Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 e-mail literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Note: 1. Co-verification provided by Mentor Graphics. Terms and product names in this document may be trademarks of others. 1482A-10/99/7.5M