NXP Semiconductors User Guide Document Number: MPC5748GLCEVBUG Rev. 1, 08/2016 MPC5748G Low Cost EVB User Guide (MPC5748G-LCEVB) (c) 2016 NXP B.V. Table of Contents 1. Introduction ........................................................................................................................................................................ 3 2. LCEVB Features ................................................................................................................................................................... 3 2.1. Differences to the Customer EVB ............................................................................................................................... 4 3. Configuration Overview ...................................................................................................................................................... 6 4. Initial Setup ......................................................................................................................................................................... 7 4.1. Power Supply Configuration ....................................................................................................................................... 7 4.1.1. Power Input Connector ..................................................................................................................................... 7 4.1.2. Power Switch ..................................................................................................................................................... 7 4.1.3. Power Status LED ............................................................................................................................................... 8 4.1.4. MCU and Peripheral Voltage Configuration ...................................................................................................... 8 4.2. Reset Control (SW3) ................................................................................................................................................... 8 4.2.1. 4.3. MCU Clock Configuration ......................................................................................................................................... 10 4.4. Debug Connector (P1) .............................................................................................................................................. 10 4.4.1. 5. 6. Reset LEDs ......................................................................................................................................................... 9 Debug Connector Pinout ................................................................................................................................. 10 Communications & Memory Interfaces: ........................................................................................................................... 11 5.1. CAN Interfaces (P2, P3) ............................................................................................................................................ 11 5.2. LIN Interfaces (P6, P7) .............................................................................................................................................. 12 5.3. USB RS232 Serial Interface (P11).............................................................................................................................. 12 5.4. USB HOST Interface (P4)........................................................................................................................................... 12 5.5. Ethernet Interface (P5) ............................................................................................................................................. 13 5.6. FlexRay (P8, P9, P10) ................................................................................................................................................ 13 User Interface (I/O) ........................................................................................................................................................... 14 6.1. GPIO Matrix .............................................................................................................................................................. 14 6.2. User Switches (SW4, SW5) ....................................................................................................................................... 15 6.3. Hex Encoded Switch (SW1) ...................................................................................................................................... 15 6.4. User LED's (DS1, DS2, DS3, DS4) ............................................................................................................................... 16 6.5. ADC Input Potentiometer (RVAR, RV1) .................................................................................................................... 16 7. MCU Port Pin LCEVB Functions ......................................................................................................................................... 17 8. Appendix ........................................................................................................................................................................... 18 9. Revision History ................................................................................................................................................................. 34 MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 2 NXP Semiconductors 1. Introduction This user guide details the setup and configuration of the NXP MPC5748G Low Cost Evaluation Board (hereafter referred to as the LCEVB). The LCEVB is intended to provide a mechanism for easy evaluation of the MPC5748G family of microcontrollers, and to facilitate basic hardware and software development. Note that the LCEVB has a limited feature set compared to the main MPC574xG customer EVB and is intended for evaluation purposes. Customers moving to serious development activities are recommended to purchase the fully functional customer EVB which also has device specific daughter cards. The LCEVB is intended for bench / laboratory use and has been designed using normal temperature specified components (+70 C). This product contains components that may be damaged by electrostatic discharge. Observe precautions for handling electrostatic sensitive devices when using the LCEVB. The user guide is intended to be read alongside the respective MCU documentation available at www.nxp.com and includes: Reference Manuals Product Data Sheets Application notes Device Errata 2. LCEVB Features The LCEVB provides the following key features: Single 5 V DC external power supply input with on-board 3.3 V regulator. Power is supplied via a 2.1 mm barrel style power jack. Simple jumper less configuration (enhanced configuration is possible via 0 Ohm Resistors and optional jumpers if required). Master power switch and regulator status LED. USB Serial interface. 2 x High Speed CAN transceiver routed to 3-way headers. 2 x LIN interfaces routed to 3-way headers. Main clock supplied from on board crystal. User reset switch with reset status LED's. Ethernet PHY and RJ45 socket (configured for MII mode). USB Type A Host interface. 2 x FlexRay interfaces with standard 2-pin connectors. 14-pin JTAG connector. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 3 NXP Semiconductors 4 user LED's wired to MCU ports. 2 user pushbutton switches wired to MCU ports. Hexadecimal encoded switch wired to 4 MCU ports. Simple potentiometer connected to analogue input channel. 2.1. Differences to the Customer EVB Note that the GPIO pins used for peripherals on the LCEVB are the same as those used on the customer EVB. This ensures maximum code compatibility between the 2 boards, making it easy to migrate from one board to the other Table 1. Customer EVB vs LCEVB features Feature Customer EVB LCEVB MCU Support Custom MCU Daughter cards for Soldered 176QFP MPC5748G multiple devices (socketed) Power Supply External 12 V External 5 V (Caution) On Board Regulators (and LED's) 5 V, 3.3 V, 1.25 V (combination of 3.3 V Switching Regulator Linear and /or Switching regulators) Master Power Switch Yes Yes Reset Control Reset button with MCU and External Reset button with MCU and External Reset LED's Reset LED's USB FTDI Serial Interface Yes Yes CAN Physical Interfaces 2 (routed to 0.1" headers) 2 (routed to 0.1" headers) LIN Physical Interfaces 2 (routed to Molex headers) 2 (routed to 0.1" headers) FlexRay Physical Interfaces 2 (routed to 0.1" headers) 2 (routed to 0.1" headers) Ethernet Physical Interface 1 (MII and RMII Support) 1 (MII only mode) USB Physical Interface 2 (USB Host and OTG) 1 (USB Host) MLB Daughter card Connector Yes No SAI Audio / TWRPI Connectors Yes No SDHC Connector Full Size SDHC Socket No Fast External Osc (FXOSC) Daughter card Crystal * and 40 MHz Crystal SMA input connector Slow External Osc (SXOSC) Daughter card Crystal * 32.768 KHz Crystal CLKOUT signals available Yes (GPIO Matrix) Yes (Standalone pads) User LEDS 4 4 User Pushbutton Switches 4 2 Hex Encoded Switch Yes Yes Test Potentiometer for ADC Yes Yes GPIO Matrix All Available Pins not otherwise used Selection of Pins available from 5 for peripherals GPIO Ports Debug 14 Pin JTAG and 50 pin Nexus 14 Pin JTAG Configuration Highly configurable via jumper shunts Fixed (limited configuration via 0 ohm resistors) * Daughter card crystals are typically 40 MHz for FXOSC and 32.768 KHz for SXOSC but may vary between daughter cards. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 4 NXP Semiconductors LCEVB Features The figure below shows the customer EVB (left) next to the LCEVB (right). Figure 1. Customer and LCEVB side by side MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 3. Configuration Overview Out of the box, there is no configuration required for the LCEVB to function. Unlike the customer EVB, the LCEVB is primarily designed for a single mode of operation with no requirement for user configuration. If you wish to have a more flexible configuration the recommendation is that the fully configurable customer EVB is purchased. There are however some jumper footprints and zero ohm resistors populated in positions that would normally have jumper headers fitted (for example on the MCU power supply lines and tracking to the peripheral interfaces). If required these can be de-soldered to modify functionality. Any such modification is done at the full risk of the user and no support or warranty repairs will be provided for a board that has been modified. Modifications should only be attempted by appropriately trained personnel using the correct equipment and Personal Protective Apparel The diagram below gives an overview of the functional blocks of the LCEVB Figure 2. EVB Functional Blocks MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 6 NXP Semiconductors Initial Setup 4. Initial Setup This section details the power, reset, clocks, and debug configuration which is the minimum configuration needed in order to power ON the LCEVB. 4.1. Power Supply Configuration The Power supply section is located in the bottom left corner of the LCEVB The LCEVB requires an external power supply voltage of 5 V DC, minimum 1 A. There is a single 3.3 V switching regulator on the LCEVB providing MCU and peripheral power. CAUTION Connecting a power supply with a voltage greater than 5 V will result in irrecoverable board damage. Check the power supply voltage before connecting the plug to the LCEVB. 4.1.1. Power Input Connector Power is supplied to the LCEVB via a 2.1 mm connector from the wall-plug mains adapter as shown below. Note - if a replacement or alternative adapter is used, care must be taken to ensure the 2.1 mm plug uses the correct polarization as shown below: Figure 3. 2.1 mm Power Connector 4.1.2. Power Switch Slide switch SW2 can be used to isolate the power supply input from the EVB voltage regulators if required. Moving the slide switch to the right (away from the power connector) will turn the EVB ON. Moving the slide switch to the left (towards the power connector) will turn the EVB OFF. MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 7 4.1.3. Power Status LED When power is applied to the LCEVB, two green LED's adjacent to the regulator and power connector show the presence of the supply voltages as follows: LED DS5 - Indicates that the 5.0 V supply voltage is present LED DS6 - Indicates that the 3.3 V switching regulator is functioning If no LED's are illuminated when power is supplied to the LCEVB and the power switch is in the "ON" position, the power adapter may be faulty or there may be a fault with the LCEVB. If only one LED is illuminated there may be a short in that power supply rail - check there is nothing shorting on the EVB. If you continue to have problems, contact NXP for support. CAUTION In the event of a short on the regulator output (in which case one of the LED's would be off or dimly illuminated), the regulator and/or the shorted component will likely be hot. 4.1.4. MCU and Peripheral Voltage Configuration The following MCU supply rails are connected to the 3.3 V switching regulator: VDD_HV_ADC0 VDD_HV_ADC1 VDD_HV_ADC1_REF VDD_HV_A VDD_HV_B VDD_HV_FLA External Ballast Transistor Supply Similarly all of the peripheral interfaces (or the I/O power in the peripheral interface) are supplied from 3.3 V as is the reset circuitry and the voltage sense wire on the JTAG connector. 4.2. Reset Control (SW3) The reset circuitry is located in the bottom left quarter of the LCEVB next to the power switch The MCU has a single bi-directional open drain Reset pin. Rather than connect multiple devices to the reset pin directly, a reset-in and reset-out buffering scheme has been implemented on the LCEVB as shown in Figure 4. The reset "in" from the reset switch (SW3) and the debug connectors are logically OR'd together using an AND gate and then connected to the buffer to provide an open-drain output. The "reset-out" circuitry provides a buffered reset signal that can be used to drive any circuitry requiring a reset control from the MCU. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 8 NXP Semiconductors Initial Setup This scheme is not required if it is guaranteed that anything driving the reset pin has an open drain drive and that there is no significant output load on the MCU reset pin. Figure 4. EVB Reset Control 4.2.1. Reset LEDs As can be seen above, there are two reset LED's that can be used to identify the source / cause of a reset: RED LED DS8 (titled "MCU") will illuminate if: The MCU issues a reset (in this condition ONLY this LED will be illuminated and LED DS1 will be off) There is a target reset (i.e. from the reset switch or from the debugger in which case LED DS1 will be ON) YELLOW LED DS7 (titled "EXT") will illuminate when an external hardware device issues a reset to the MCU: The reset switch is pressed There is a reset being driven from one of the debug connectors LED DS7 (Yellow) OFF OFF LED DS8 (Red) OFF ON ON OFF ON ON Table 2. Reset LED Decoding Description No Reset being issued from MCU or external logic MCU has issued a reset External reset issued from switch or debug BUT not being issued to MCU (check R137 has not been removed) External reset issued from reset switch or debug and has been issued to MCU. MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 9 4.3. MCU Clock Configuration There is an external 40MHz crystal connected to the MCU Fast External Oscillator (FXOSC) pins EXTAL and XTAL. There is also a 32.768 crystal connected to the MCU Slow External Oscillator (SXOSC) pins OSC32K_EXTAL and OSC32K_XTAL. This can be used for accurate time keeping. There are 2 pads PG6 and PG7 (located just below the MCU) on the LCEVB to facilitate measurement of the CLKOUT1 and CLKOUT0 signals. Note - there is no external clock input on the LCEVB The JTAG debug connectors is located in the top left corner of the LCEVB 4.4. Debug Connector (P1) The LCEVB has a single 14-pin keyed JTAG connector for connection to an external debugger. Before attaching or removing the debug cable from the LCEVB remove power from the EVB to prevent damage to the LCEVB or debug hardware. 4.4.1. Debug Connector Pinout The following tables list the pinout for the JTAG connector used on the LCEVB Table 3. 14-Pin JTAG Debug Connector Pinout Pin No Function Connection Pin No Function Connection 1 TDI PC0 2 GND GND 3 TDO PC1 4 GND GND 5 TCLK PH9 6 GND GND 7 EVTI PL8 8 N/C --- 9 RESET JTAG - RSTx 10 TMS PH10 11 VREF PER_HVA 12 GND GND 13 RDY --- 14 JCOMP 10k Pulldown TDI, TDO and TMS have 10K pullup resistors on the LCEVB. TCLK has a 10K pulldown (R147) to facilitate STANDBY exit without any additional code (at the sacrifice of slightly higher STANDBY current), however this can be changed to a pullup if required by removing R147 and fitting the resistor on R56. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 10 NXP Semiconductors Communications & Memory Interfaces: Table 4. JTAG Pins Pull State (from MPC5748G Reference Manual) TERMINAL TYPE POWERUP pad state RESET pad status DEFAULY pad status RESET Strong pull-down Strong pull-down Weak pull-up PORST Weak pull-down Weak pull-up Weak pull-up GPIO High impedance High impedance High impedance ANALOG High impedance High impedance High impedance EOUT0, EOUT1 High impedance High impedance High impedance TCK High impedance Weak pull-up Weak pull-up TMS High impedance Weak pull-up Weak pull-up TDI High impedance Weak pull-up Weak pull-up TDO High impedance High impedance High impedance 5. Communications & Memory Interfaces: This section details the communication interface and storage peripherals that are implemented on the LCEVB. The CAN circuitry is located on the top right edge of the LCEVB 5.1. CAN Interfaces (P2, P3) The LCEVB incorporates two identical CAN interface circuits connected to MCU CAN0 and CAN1 using MC33901 transceivers. Both transceivers are configured for high speed operation by pulling pin 8 to GND via a 4.7 kOhm resistor. There are test points to allow the Select pin to be driven high if desired. The MC33901 is pin compatible with other CAN transceivers supporting full CAN FD data rates. For flexibility, the CAN transceiver I/O is connected to a 0.1" header (P2 for CAN0 / P3 for CAN1) rather than using non-standard DB9 connectors. The pinout of these headers is shown below. 1 H L GND Figure 5. CAN Physical Interface Connectors MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 11 The LIN Physical interface circuits are located on the right edge of the LCEVB 5.2. LIN Interfaces (P6, P7) The LCEVB incorporates two LIN transceiver circuits connected to MCU LIN0 and LIN1, using an NXP MC33662 transceiver. The MPC5748G LIN0 supports both master and slave modes whereas LIN1 only supports master mode. On the LCEVB, the LIN0 transceiver is configured as slave mode by default. Master mode operation is possible by either populating a zero ohm resistor (R143) or buy fitting a jumper header (J2) - see the schematics for details. The LIN0 transceiver is hard wired for master mode. To save on board space and cost, both LIN transceivers are connected to 0.1" pitch 3x1 headers as shown below rather than the usual LIN Molex header. 1 GND Vsup LIN Figure 6. LIN Physical Interface Connector Note that in order for the LIN transceiver to function, external 12v must be supplied via pin 2 of the connector 5.3. USB RS232 Serial Interface (P11) The USB RS232 interface is on the left hand edge of the board (USB Type B The LCEVB incorporates a USB RS232 serial interface providing RS232 connectivity via a direct USB connection between the PC and the EVB. The circuit contains an FTDI FT2232D USB to Serial interface which should automatically install the drivers for two additional COM ports on your PC. Note that only one of these ports is used so you will need to try both (usually the higher numbered COM port is the active one). For more information on the USB drivers and general fault finding, consult the FTDI website at http://www.ftdichip.com/ The MCU LIN2 signals are routed to the FTDI transceiver (UART TX and RX). No handshaking signals are implemented and no board configuration is required. 5.4. USB HOST Interface (P4) The USB Host interface is on the top left corner of the LCEVB on the left The LCEVB includes a Type A (Host) USB interface, routed to a USB type A female connector. The USB circuit contains a USB83340 transceiver with a MIC2026-1YM USB power switch. There is no hardware user configuration required to use the USB circuit. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 12 NXP Semiconductors Communications & Memory Interfaces: 5.5. Ethernet Interface (P5) The Ethernet interface is mid-way along the top edge of the LCEVB The EVB incorporates a single DP83848c Ethernet transceiver with the circuitry configured for MII mode. The transceiver is connected to a pulse J1011F21PNL RJ45 connector which includes a built-in isolation transformer. There is no hardware configuration needed. If you require RMII mode or access to both Ethernet ports on the MPC5748G, please purchase the MPC5748G customer EVB and appropriate daughter cards. Note that the MCU Ethernet signals are all in the VDD_HV_B domain. The Ethernet PHY will only function with 3.3 V I/O so if you have made any modifications to the EVB power domain configuration (via the zero ohm resistors), you need to ensure the VDD_HV_B domain is at 3.3 V before attempting to use the Ethernet module. If VDD_HV_B is set to 5 V, the signals routed to the Ethernet PHY (see the EVB schematics) must be left as tristate to prevent damage to the transceiver. 5.6. FlexRay (P8, P9, P10) The FlexRay interfaces are midway down the left hand edge of the LCEVB The LCEVB incorporates two FlexRay TJA1080TS/N interfaces connected to MCU FlexRay channels A and B and routed to two Molex 1.25 mm pitch Pico Blade shrouded headers (standard on many NXP EVB's). There is no hardware configuration required to use FlexRay. Note that the LCEVB is supplied with a 40 MHz crystal by default. If FlexRay is configured to use the external clock source, then the crystal should be left at 40 MHz MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 13 6. User Interface (I/O) This section details the user I/O available on the LCEVB and includes the GPIO matrix, switches, LED's and the ADC variable resistor. The GPIO matrix is on the right hand edge of the LCEVB 6.1. GPIO Matrix A sub-set of available GPIO pins (available pins being those not already routed to LCEVB peripherals) are available at the GPIO matrix as detailed below. The matrix provides an easy to follow, intuitive, space saving grid of 0.1" header through-hole pads. Users can solder wires, fit headers or simply insert a scope probe into the respective pad. To use the matrix, simply read the port letter from the top or bottom row of text then the pad number from the columns on the left or right of the matrix. For example, the 1st pad available on Port B is PB5 as outlined below. Figure 7. GPIO Matrix If a pad is populated in the matrix, it means this is available for exclusive use as GPIO. The exception to this are the port pins detailed below which are also shared with switches or user LED's (shaded red in the matrix diagram above). PD0, PD1, PD2, PD3 - HEX Encoder Switch PA1, PA2 - User pushbutton Switches If you require access to all of the available GPIO pads, the customer EVB and daughter card provides this additional functionality. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 14 NXP Semiconductors User Interface (I/O) The user pushbutton switches are in the bottom right corner of the LCEVB 6.2. User Switches (SW4, SW5) There are two active high (pulled low, driven to 3.3 V) pushbutton switches on the LCEVB connected directly to MCU GPIO ports. No configuration is required to use the switches. SW4 is connected to port PA1 (which is also the NMI pin) and SW5 is connected to port PA2 NOTE The MCU ports used on the user pushbutton switches are also routed to the GPIO matrix. The hex encoder switch is located to the left of the GPIO Matrix 6.3. Hex Encoded Switch (SW1) There is a single hex encoded 16 position rotary switch on the LCEVB. This outputs a binary encoded hex value (active high) on four MCU ports (Port D[0..3]). Table 5. Hex Encoder Switch (SW2) HEX_SW4 HEX_SW3 HEX_SW2 HEX_SW1 (PD3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (PD2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 (PD1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 (PD0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Position 0 1 2 3 4 5 6 7 8 9 A B C D E F Note that POSN 0 will ensure that no voltage is applied to the pads. This allows the pads to be used as normal GPIO (with 10K pulldown) and accessed at the respective pads on the GPIO matrix area. MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 15 6.4. User LED's (DS1, DS2, DS3, DS4) The user LED's are above the user switches in the lower right corner There are four active low user LED's, DS1 to DS4, connected directly to 4 MCU ports (PG[2..5]) as shown below. No configuration is required to use the LED's. Table 6. Use LED's (DS1, DS2, DS3 and DS4) User LED MCU Pin DS1 PG2 DS2 PG3 DS3 PG4 DS4 PG5 6.5. ADC Input Potentiometer (RVAR, RV1) The ADC Pot is above the hex switch to the left of the GPIO matrix There is a small variable resistor RV1 on the LCEVB which routes a voltage between 0v and 3.3 V to MCU pin PB4. This is useful for quick ADC testing. Test point RVAR can be used to probe the voltage with a voltmeter. Note that this circuit provides a very rough way to evaluate the ADC. There is a small current limiting series resistor network to limit the injection current to around 4.4 mA. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 16 NXP Semiconductors MCU Port Pin LCEVB Functions 7. MCU Port Pin LCEVB Functions The table below shows what each MCU pin is used for on the LCEVB. No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port A GPIO GPIO 2 GPIO 2 Ethernet GPIO GPIO GPIO Ethernet Ethernet Ethernet Ethernet Ethernet GPIO GPIO GPIO GPIO Port B CAN0 CAN0 LIN0 LIN0 ADC Pot GPIO GPIO GPIO EXTAL32 XTAL32 SAI Audio GPIO GPIO GPIO GPIO GPIO No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port I GPIO GPIO GPIO GPIO USB1 USB1 GPIO USB1 GPIO Port J ----------- 2 3 4 Table 7. LCEVB 176QFP Port Pin Functions Port C Port D Port E Port F GPIO 3 JTAG --GPIO JTAG GPIO 3 --GPIO USB1 GPIO 3 FlexRay A GPIO USB1 GPIO 3 FlexRay A GPIO FlexRay B GPIO FlexRay B GPIO FlexRay A GPIO FlexRay B GPIO LIN1 GPIO --GPIO LIN1 GPIO --GPIO RS232 GPIO --GPIO RS232 GPIO --GPIO CAN1 GPIO --GPIO CAN1 --GPIO FlexRay GPIO Ethernet GPIO FlexRay GPIO Ethernet GPIO FlexRay GPIO USB1 Ethernet FlexRay GPIO USB1 Ethernet Port G Ethernet Ethernet GPIO 4, GPIO 4 GPIO 4 GPIO 4 GPIO GPIO ----USB1 USB1 Ethernet Ethernet USB1 USB1 Port H Ethernet Ethernet Ethernet ------------JTAG JTAG USB1 USB1 ------- Key: --- Pin not bonded out on 176QFP package Pin not accessible on LCEVB Ethernet GPIO GPIO GPIO GPIO Shared with user switches Shared with Hex Encoder Switch Shared with user LED's MPC5748G Low Cost EVB User Guide, User Guide, Rev. 1, 08/2016 NXP Semiconductors 17 8. Appendix The MPC5748G LCEVB schematics, Rev B are shown below. MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 18 NXP Semiconductors 5 4 2 3 1 MPC5748G Low Cost Evaluation Board (MPC5748G-LCEVB) Revision Information Table Of Contents: D Power - Main input and 3.3V regulator Power - MCU Power Power - MCU Decoupling Reset and JTAG Clocks MCU GPIO 1 MCU GPIO 2 Comms1 - CAN and LIN Comms 2 - FTDI RS232 Interface Comms 3 - USB Host Interface (device footprints only) Comms 4 - Ethernet (MII Mode) Comms 5 - FlexRay User - Switches, LED's and Potentiometer User - GPIO Pin Matrix C Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Rev Date Designer Comments x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 A AX1 14 Apr 2015 08 May 2015 18 May 2015 19 May 2015 26 May 2015 27 May 2015 29 May 2015 31 May 2015 01 Jun 2015 01 Jun 2015 11 Jun 2015 29 Sep 2015 Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Andrew MacDonald Alasdair Robertson AX2 AX3 AX4 AX5 B 26 Oct 2015 29 Oct 2015 09 Dec 2015 20 Jan 2016 12 Feb 2016 Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Alasdair Robertson Start of capture, Working version (256BGA) Changed to 176 QFP Package and changed periperhal Matrix Changes required for initial placement Tidy Up, Replaced some "hard to source" components Renumber and Back Annoted from Layout Correction to GND on 3v3 Regulator circuit Correction to CAN Test points Few refdes changes after layout tweaks Correction to user LED Refdes after re-number DNP Jumpers. 0 Ohm resistors added accross LIN jumpers Prototype Manufacture Release Prodn Build changes (LIN0 default to Slave, LIN1 Master only) PN Changed to MPC5748G-LCEVB Change to JTAG Pulls to meet latest RM Spec Changed RV1 current limit resistor. SW4 / SW5 refdes swap Pull DOWN on TCLK to mitigate against STANDBY exit issue. Updated NXP Logos Updated NXP Logos D C Caution: These schematics are provided for reference purposes only. As such,NXP does not make any warranty, implied or otherwise, as to the suitability of circuit design or component selection (type or value) used in these schematics for hardware design using the NXP Calypso family of Microprocessors. Customers using any part of these schematics as a basis for hardware design, do so at their own risk and NXP does not assume any liability for such a hardware design. B B 3 Different test points used in design: TPVx - Through Hole Pad small TPHx - Through Hile Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx) TPX - Surface Mount Wire Loop Notes: - All components and board processes are to be ROHS compliant All small capacitors are 0402 unless otherwise stated All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603 All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated All jumpers are denoted Jx. Jumpers are 2mm pitch 2 Pin jumpers generally have the "source" on pin 1. Automotive Microcontroller Applications East Kilbride, Scotland - Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2. NXP General Business Use - All switches are denoted SWx A This document contains information proprietary to NXP and shall not be used for engineering design, - All test points (SMT wire loop style) are denoted TPx procurement or manufacture in whole or in part Designer: Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes. MPC5748G-LCEVB Page Title: A. Robertson User notes are given throughtout the schematics. Specific PCB LAYOUT notes are detailed in ITALICS Approved: A. Robertson 4 3 2 Freescale AISG Applications, East Kilbride Drawing Title: A. Robertson Drawn by: 5 A without the express written permission of NXP Semiconductors. - Test point Vias (just through hole pads) are denoted TPVx Index and Title Page Size B Document Number Date: Friday, February 12, 2016 SCH-27897 Rev B PDF: SPF-27897 Sheet 1 1of 15 5 4 3 2 1 Power Input and Linear Voltage Regulators Power Supply Input P12 Jumpers can be fitted to (Power Switch) 3 2 5 2.1mm Barrel D Power Control SW2 1 4 facilitate power measurements 5V0_SR Main Power In 5V-IN C 1 2 3 D4 B340A DNP 2 MCU_3V3 5v0 R142 560 3 MCU_5V0 3 5V0_SR J4 DS5 DNP 1 C MCU_3V3 HDR 1X2 R48 0 A GND C21 10UF 10V J3 1 (SR = Swithing Reg) 1 C26 0.1UF D 3V3_SR Connector 2 MCU_5V0 A HDR 1X2 R49 0 LED GREEN GND 5V0_SR 3V3_SR 3.3v Switching Regulator 5V0_SR PER_HVA R47 0 R45 DNP 0 R46 0 R44 DNP 0 U10 8 PER_HVB VIN PG EN SW 1 3 C22 10UF 10V 2 9 6 7 MODE VOS GND FB R138 1 L3 178K 3V3_SR 2 1.0uH 1 C 5 4 C23 22UF 10V EP R43 270 3v3 TPS62082 C DS6 C A LED GREEN GND 1 Inoput Voltage 5V, Output 3.3V at 700mA. Ripple 1.4mV, Approx 90% efficient B B Test and reference points GND15 GND16 1 1 1 1 1 GND1 GND2 GND3 GND4 GND Test Points, GND Test Points, Top Side underside of board GND Automotive Microcontroller Applications East Kilbride, Scotland NXP General Business Use A A Drawing Title: MPC5748G-LCEVB Page Title: Power Input and Linear Voltage Regulators 5 4 3 2 Size B Document Number Date: Friday, February 12, 2016 SCH-27897 Rev B PDF: SPF-27897 Sheet 1 2of 15 5 4 3 Calypso MCU Power Connections D 2 1 Power Supply Contraints: - If VDD_HV_A is driven from 3.3V, VDD_HV_FLA must also be supplied from 3.3V - If VDD_HV_A is driven from 5V, the VDD_HV_FLA pin must be disconnected from 3.3V Default Configuration: - ALL MCU supply voltages are set to 3.3V (ADC0, ADC1, VDD_HV_A, VDD_HV_B, VDD_HV_C, VBallast) - VDD_HV_FLA = External 3.3V supplied (jumper - Don't attempt to over drive an analogue pad to 5V when the digital VDD_HV_x supply is set to 3.3V. This will trigger the ESD protectrion on that pad. For example if VDD_HV_A is set to 3.3V and the analogue supplies are set to 5V, you cannot drive 5V fitted) The analogue pins can only be driven to the same voltage as the VDD_HV_x domain they are situated in (i.e. max 3.3V) so makes sense for the analogue supply and reference to be 3.3V D 9 0 into a pad in the VDD_HV_A domain MCU_3V3 2 MCU_3V3 MCU_5V0 R98 0 R112 0 R124 0 R103 0 R99 0 R111 0 R114 0 DNP DNP DNP DNP HVB CAP HVA CAP 1 ADC1REF CAP C A P 8 9 A D C 0 AD C1 CA P R139 0 supply control E_CAP C A P C_CAP L V D E C C 4 Q50 MJD31CT4 B_CAP 1 R102 0 Individual MCU 3 0 DNP R122 0 LV CAP R97 5v0 C R101 0 R100 0 C A P 3v3 H V F L A 2 MCU_5V0 Package 2of3 Flash 30 VDD LP DEC 110 152 VDD LV 31VDDLV54VDDLV 110VDDLV152 31 54 VRC CTRL VDD HV FLA VDD HV B 124 Calypso 6M 176QFP Analogue 32 27 124 VDD HV A 6VDDH VA59V DDHVA 85VDD HVA15 1 6 59 85 151 HV ADC1 REF V D D VDD HV ADC0 U20B B 98 VDD HV ADC1 99 TPH2 B 1.25v Core & External Ballast Power Pins dissipation & GND 177 26 109 EP VSS LV 109 VSS HV VPP VSS HV 150 7 28 55 57 86 123 150 97 VSS HV ADC0 VSS HV ADC1 VSS HV 7VSSH V28VS SHV55 VSSHV 57VSS HV86V SSH V1 23 Central Pad for heat PPC5748GSK0MKU6 R123 0 Automotive Microcontroller 1 GND GND GND TPH3 GND GND Applications East Kilbride, Scotland A Drawing Title: - The scheme shown has the analogue and digital grounds connected to the same plane - This results in better ADC performance than using an analogue grond plane with single entry point (or ferrite) to digital ground plane. 5 4 A NXP General Business Use Notes on signal Grounds: 3 MPC5748G-LCEVB Page Title: Calypso MCU Power 2 Size B Document Number Date: Friday, February 12, 2016 SCH-27899 Rev B PDF: SPF-27899 Sheet 1 3 of 15 5 4 3 2 1 Calypso MCU Decoupling and bulk storage ADC Flash ADC0_CAP ADC1_CAP ADC1REF_CAP Capacitor Types: 4700pF - Ceramic X7R, 50V 10% 0402 0.1uF - Ceramic X7R, 16V 10% 0402 (Kemet C0402C104K4RAC) HVFLA_CAP D C94 C93 C97 C96 C95 C118 1uF 0.1UF 1uF 0.1UF 1uF 2.2UF GND GND GND 0.68uF - Ceramic X7R, 16V 1uF - Ceramic X7R, 10V 2.2uF - Ceramic X7R, 10V D 10% 0805 (Murata GCM219R71C684KA37) 10% 0603 Low ESR (Taiyo Yuden LMK107B7105KA-T) 10% 0603 Low ESR (Taiyo Yuden LMK107B7225KA-TR) GND Place small Caps as close as possible to MCU pins VDD_HVA VDD_HVB HVA_CAP HVB_CAP C112 2.2UF C C109 0.1UF C120 0.1UF C92 0.1UF C100 0.1UF C99 C 0.1UF GND GND One 0.1uF cap per VDD_HV_x pin. Place as close as possible to pin VDD_LV Ballast Transistor LP Internal Reg Cap LV_CAP B_CAP B C110 0.68uF C111 0.68uF C27 0.68uF (low (low (low ESR) ESR) ESR) C108 0.1UF C116 0.1UF C98 0.1UF C113 0.1UF E_CAP C_CAP C119 4700pF VDD_LV (1.25V) Decoupling. Place one of the 0.1uF caps close to each VDD_LV GND pin. Place the 0.68uF caps on each side of the package such that there is LVDEC_CAP C122 2.2UF C117 1uF B GND GND no cap on the side with the ballast transistor (For regulator stability the total capacitance should be around 2.2uF). Place close to transistor Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: MPC5748G-LCEVB Page Title: Calypso MCU Decoupling Size B Date: 5 4 3 2 Document Number Rev SCH-27899 PDF: SPF-27899 Friday, February 12, 2016 Sheet 1 4 B of 15 5 4 3 2 1 Reset and External Clock In Reset is in the VDD_HVA domain. Reset Input / Output PER_HVA PORST Connect an external LVI to pad when supplying external 1.25V so that PORST is asserted until exterbal 1.25V supply is at PER_HVA 3V3_SR D threshold and stable C25 R140 270 (0603 R37 10.0K D TPH1 C24 (0603 0.1UF 50V) 1 PORSTx PORSTx 7 MCU-RSTx 5,7 R134 10.0K 1 JTAG-RSTx U12A VCC 5 JTAG-RSTx RST-SWITCHx 7 2 TARGET GND RESET LED U11 SYSTEM-RSTx 3 MR GND SN74LVC2G08DCT 4 Reset Switch (1.65 to 5.5v operation) 1 SW3 4 VCC RESET GND 1 2 B3WN-6002 GND line to/from MCU R137 0 2 RST-INx MCU-RSTx Tri-State Buffered RESET signal to reset the MCU Buffered RESET-out Active reset drive (high / low) for any periperhals that need to ADM6315-26D2ARTZR7 (2.5 to 5v operation) GND R136 10.0K Bi Directional reset RST C Reset from Debugger DS7 YELLOW LED GND 8 R135 10.0K 1 A 0.1UF 50V) be reset when MCU is in reset C C121 0.1UF (0603 TPV5 C 3V3_SR 50V) R141 270 Note: The Reset pad on Calypso is in the VDD_HV_A domain which can be run from either 3.3V or 5V GND DS8 A C LED RED (MCU RESET) (selected by the VDD_HV_A and PER_HVA jumpers) To maintian brightness on the LED's irrespective of the voltage setting, the LED's are U12B powered from constant 3.3V, grounded via the reset line. 5 3 RST-OUTx RST-OUTx 6 12 SN74LVC2G08DCT JTAG Standard 14-pin Connector PER_HVA B B R58 10.0K R57 10.0K R56 10.0K R52 10.0K ONCE Connector DNP P1 7 7 7 PC0 PC1 PC0 PC1 PH9 PH9 TDI TDO TCLK EVTI DBUG-RSTx 5 JTAG-RSTx JTAG-RSTx (buffered R55 0 reset TO MCU) 5,7 MCU-RSTx MCU-RSTx (bidirectional MCU reset) R147 R54 0 DNP (TDI) (TDO) (TCLK) (EVTI) (RESET) (VREF) 1 3 5 7 9 11 2 4 6 8 10 12 (RDY) 13 14 CON_2X7 10.0K (GND) (GND) (GND) (N/C) (TMS) (GND) PH10 JCOMP Note TCLK needs to be pulled down to allow exit from STANDBY in some corner cases R53 10.0K Optional Config Automotive Microcontroller Applications East Kilbride, Scotland NXP General Business Use GND GND A 7 PH10 PH10 Drawing Title: Page Title: Size B Date: 5 A TMS 4 3 2 MPC5748G-LCEVB Reset Circuitry & External Clock In Document Number Rev SCH-27897 PDF: SPF-27897 Friday, February 12, 2016 Sheet 1 5 B of 15 5 4 3 2 1 Clocks D D Oscillators 7 PB9 C18 PB9 R42 1.0M DNP 7 PB8 12PF (EXTAL32) 32.768KHZ FC-255 32.7680K-A3 (Load Capacitance 7pF) 1 2 PB8 Y3 C20 12PF (XTAL32) GND C C19 7 MCU-EXTAL R41 1.0M DNP Y2 40.0MHZ MCU-XTAL 12PF 2 1 MCU-XTAL NX8045GB-40.000M-STD-CSJ-1 XTAL (Optimised for Automotive, 8pF Load capacitance) C17 7 C 12PF MCU-EXTAL GND B B Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: Page Title: Size B Date: 5 4 3 2 MPC5748G-LCEVB Clocks Document Number Rev SCH-27899 PDF: SPF-27899 Friday, February 12, 2016 Sheet 1 6 B of 15 5 4 3 2 1 Calypso GPIO 1 of 2 U20A (GPIO) (SW1 & GPIO**) (SW2 & GPIO) (MII_RXCLK) (GPIO) (GPIO) (GPIO) (MII_RXD2) (RMII_RXD1) (RMII_RXD0) (MII_COL) (RMII_RXER) (GPIO) (GPIO) (GPIO) (GPIO) PA0 PB0 PB7 (CAN0_TX) (CAN0_RX) (LIN0_TX) (LIN0_RX) (ADC_POT) (GPIO) (GPIO) (GPIO) (XTAL32) 6 PB8 (EXTAL32) PB9 6 PB9 (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) PB10 PB11 PB12 PB13 PB14 PB15 15 (WKPU2 / NMI0) (WKPU3) 14,15 14,15 12 D Key to text colours: Purple - Comms Physical Interfaces Orange - Other Peripherals and I/O Blue - Debug (JTAG & Nexus) Black - Clock, Reset and Control RED - I/O Matrix and other functions (eg LED) Green - I/O Matrix (dedicated) 15 15 15 12 12 12 12 12 15 PA 12..15 has SPI PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 15 PA14 15 PA15 9 9 PB0 PB1 9 PB2 9 PB3 14 PB4 15 PB5 15 PB6 15 15 PB10 PB11 PB12 15 PB13 15 PB14 15 5 PC1 PC2 (USB1_DIR) 11 PC3 PC0 13 9 9 10 PC4 PC6 PC7 PC8 10 PC9 PC5 9 PC10 9 PC11 13 PC12 13 PC13 13 13 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PC14 PC1 PC2 149 145 PC3 144 (FR_B_TX_EN) (FR_A_TX) (LIN1_TX) PC4 PC5 PC6 (LIN1_RX) PC7 (RS232_TX) PC8 (RS232_RX) PC9 (CAN1_TX) (CAN1_RX) (FR_DBG0) (FR_DBG1) (FR_DBG2) (FR_DBG3) PC10 PC11 PC12 PC13 PC14 PC15 PD2 (HEX4 & GPIO) PD3 14,15 PD3 (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) PD4 PD5 PD6 PD7 PD8 PD9 PD10 15 15 PD4 PD5 15 PD6 PD7 PD8 PD9 159 158 44 PD12 15 PD13 15 PD14 PE0 PE2 PA3 Package 1of3 GPIO Pins1 PE3 PA4 PA5 PD0 PD1 PD2 PA11 PE11 PA12 PE12 PA13 PE13 PA14 PE14 PA15 PE15 PF0 PF1 PB2 PF2 PB3 PF3 PB4 PF4 PB5 PF5 PB6 PF6 PB7 PF7 PB8 PF8 PB9 PF9 PB10 PF10 PB11 PF11 PB12 PF12 PB13 PF13 PB14 PF14 PD15 5 5 MCU-RSTx PORSTx MCU-RSTx 6 6 MCU-XTAL MCU-EXTAL MCU-XTAL MCU-EXTAL PORSTx 29 153 PF0 64 65 66 67 68 69 70 42 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) 41 PF9 (GPIO) 46 47 43 49 126 125 PF10 PF11 PF12 PF13 PF14 PF15 (GPIO) (GPIO) (GPIO) (GPIO) (RMII_MDIO) (RMII_RXDV) PG1 121 16 PG1 PG2 PG2 15 PG3 (LED2 & GPIO) PG3 PG0 PG4 PG6 PG7 PG8 PC5 PG5 14 13 38 PG4 PG5 PG6 (LED3 & GPIO) (LED4 & GPIO) (CLKOUT1 GPIO) 37 PG7 (CLKOUT0 GPIO) PG10 PG11 PG12 PG13 PG14 PG15 (USB1_D4) (USB1_D5) (MII_TXD2) (MII_TXD3) (USB1_D0) (USB1_D1) PE2 13 PE3 13 PE4 13 PE5 13 PE12 12 PE13 12 PE14 11 PE15 11 PF0 PF1 15 15 PF2 15 PF3 15 PF4 15 PF5 15 PF6 15 PF7 15 PF8 15 PF9 15 D C PF10 15 PF11 15 PF12 15 PF13 15 PF14 12 PF15 12 PG0 12 PG1 12 PG2 14 (eMIOS E1UC_11_H) PG3 14 (eMIOS E1UC_12_H) PG4 14 (eMIOS E1UC_13_H) PG5 14 (eMIOS E1UC_14_H) PG9 PC10 PG10 PC11 PG11 PC12 PG12 PC13 PG13 PC14 PG14 138 139 116 115 134 135 1 PG15 PD2 PH2 PG6 1 34 33 PC9 117 PH0 118 119 PH1 PH2 (RMII_TXD1) (RMII_TXD0) (RMII_TXEN) 120 PG7 PG10 11 PG11 11 PG12 12 PG13 12 PG14 11 PG15 11 PH0 12 PH1 12 PH2 12 PH9 5 PH10 5 PH11 11 PH12 11 B PH3 PD4 PD5 PH4 PH5 PD6 PH6 PD7 PH7 PD8 PH8 PD9 PH9 PH10 PH11 PD12 PH12 PD13 PH13 PD14 PH14 PD15 15 63 PC3 PH1 100 102 104 106 (MII_CRS) (MII_RXD3) (USB1_D2) (USB1_D3) PC2 PH0 81 82 83 84 87 94 95 PE12 PE13 PE14 PE15 PC1 PC0 PD1 80 (FR_A_TX_EN) (FR_A_RX) (FR_B_TX) (FR_B_RX) (RMII_MDC) (RMII_TXCLK) (LED1 & GPIO) 77 PD0 78 79 PE2 PE3 PE4 PE5 122 PG0 2 36 35 173 174 3 4 20 156 157 160 161 167 168 21 22 23 25 133 127 136 137 PF15 PD3 PD12 PD13 PD14 PD15 PE4 PE6 PE7 PE8 PE9 PE10 PD10 (GPIO) (GPIO) (GPIO) (GPIO) PE1 PE5 PA6 PA7 PA8 PA9 PA10 PC4 PC6 45 PC7 PC8 175 PD10 15 Calypso 176QFP PC15 PD1 PD0 15 60 62 96 101 103 105 107 154 14,15 14,15 15 176 1 88 91 92 93 61 18 PA0 PA2 PA1 39 PB0 40 PB1 PC15 14,15 15 19 17 114 51 146 147 128 129 130 131 132 53 52 50 48 PC0 (HEX1 & GPIO) (HEX2 & GPIO) (HEX3 & GPIO) 15 24 PB15 11 13 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PB15 (TDI) (TDO) (USB1_CLK) 5 PD has ADC0 and ADC1 PA4 PA13 15 B PA3 15 15 C PA0 PA2 PA1 162 163 164 165 166 155 148 140 141 9 10 8 PH9 PH10 PH11 PH12 (TCK) (TMS) (USB1_D6) (USB1_D7) PH15 RESET PORST Automoti ve Microcontr oller A 56 XTAL 58 EXTAL Applications A East Kilbride, Scotland NXP General Business Use Drawing Title: PPC5748GSK0MKU6 Page Title: Size B Date: 5 4 3 2 MPC5748G-LCEVB Calypso GPIO 1of2 Document Number Rev SCH-27899 PDF: SPF-27899 Friday, February 12, 2016 Sheet 1 7 B of 15 5 4 3 Calypso GPIO 2 of 2 D Key to text colours: Purple - Comms Physical Interfaces Orange - Other Peripherals and I/O Blue - Debug (JTAG & Nexus) Black - Clock, Reset and Control RED - I/O Matrix and other functions (eg LED) Green - I/O Matrix (dedicated) 2 1 U20C 15 15 15 15 11 11 15 PI0 PI1 PI2 PI3 PI4 PI5 PI6 11 15 PI7 PI8 12 15 15 15 15 PI11 PI12 PI13 PI14 PI15 (GPIO) (GPIO) (GPIO) (GPIO) (USB1_STP) (USB1_NXT) (GPIO) (USB1_RST) (ENET_RST) (GPIO) (GPIO) (GPIO) (GPIO) PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 172 PI0 171 PI1 170 PI2 169 PI3 143 PI4 142 PI5 11 PI6 D 12 PI7 PI8 108 PI11 111 PI11 PI12 PI13 PI14 PI15 Calypso 176QFP Package 3of3 GPIO Pins2 PI8 112 PI12 113 PI13 76 PI14 75 PI15 74 73 72 71 5 PJ0 PJ1 PJ2 PJ3 PJ4 C C B B Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: Page Title: PPC5748GSK0MKU6 Size B Date: 5 4 3 2 MPC5748G-LCEVB Calypso GPIO 2of2 Document Number Rev SCH-27899 PDF: SPF-27899 Friday, February 12, 2016 Sheet 1 8 B of 15 5 4 3 2 1 CAN & LIN Physical CAN0 Physical Interface VDD 5V0_SR PER_HVA - 5.0V input supply for CAN transceiver (4.5 to 5.5V) VI/O - determines the signal level on MCU TX and RX pins and can range from 2.8 to 5.5V C60 0.1UF C59 2.2UF 10V (0603 50V) STB - High for Standby mode, pulled low for normal mode. (CAN0_TX) R64 0 CAN0_TX 1 (CAN0_RX) R63 0 CAN0_RX 4 R51 4.70K CAN0-S TXD RXD 8 STB CAN termination resistor footprint. Place on underside of PCB GND VIO PB0 PB1 VD D PB0 PB1 U1 R1 CANH GN D 7 7 (0603 50V) 5 3 D GND C53 0.1UF C52 2.2UF 10V CANL 7 CAN0-CANH 6 CAN0-CANL D 120 DNP P2 1 2 3 HDR_1X3 TPV16 All CAN and LIN signals are 2 GND MC33901WEF GND in power domain VDD_HV_A. GND All interfaces will work at CAN1 Physical Interface 3.3V or 5.0V (PER_HVA) VDD 5V0_SR - 5.0V input supply for CAN transceiver (4.5 to 5.5V) C58 C57 2.2UF 10V VI/O - determines the signal level on MCU TX and RX pins and can range from 2.8 to 5.5V C PER_HVA (0603 50V) 5 U2 (CAN1_TX) R62 0 CAN1_TX 1 (CAN1_RX) R59 0 CAN1_RX 4 R50 4.70K CAN1-S TXD 8 C GND VIO PC10 PC11 RXD CANH STB CANL GN D PC10 PC11 VD D GND 7 7 footprint. Place on underside of PCB 50V) 3 STB - High for Standby mode, pulled low for normal mode. CAN termination resistor C51 C50 2.2UF0.1UF 10V (0603 0.1UF R2 7 CAN1-CANH 6 CAN1-CANL 120 DNP P3 1 2 3 HDR_1X3 TPV15 2 GND MC33901WEF GND GND Master Mode Pullup Enable R143 Configired as SLAVE by default (Lin0 Supports Master and Slave) PER_HVA B 7 7 PB3 PB2 PB3 PB2 (LIN0_RX) (LIN0_TX) R74 R75 0 0 LIN0-RX (Enable) (Wake) LIN0-TX GND DNP J2 0 DNP 1 U6 1 INH 2 RXD VSUP 3 EN WAKE LIN 4 TXD GND MC33662BLEF 8 7 6 5 HDR 1X2 GND (LEF = 20K Baud) C70 0.1UF D50 2 A C D51 A GF1A C69 2.2UF 10V (0603 50V) EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A GF1A C R18 2.0K R17 2.0K VSUP2 HDR_1X3 P7 1 LIN0 Physical Interface Battery Reverse polarity & Pulse Protection Total current through resistors (LIN Bus at GND) = 12mA (0.144W) 3 pin GND Each resistor spec = 0.1W (0.2W total) WAKE = GND ensures no spurious wakeups B 1 2 3 LIN0-VSUP LIN0-LIN header MC33662LEF LIN transceiver is newer version of 33661 offering: (NOT Molex) - Full LIN compliance (33661 no longer compliant) - Improved ESD protection on LIN pin up to 15KV - Improved ESD on Wake and VSUP Pins - Other EMC and performance improvements GND See freescale.com for more details LIN1 Physical Interface Master Mode Pullup Enable Configired as MASTER by default PER_HVA 7 7 A PC7 PC6 PC7 PC6 (LIN1_RX) (LIN1_TX) R60 R61 0 0 (TXD_0) LIN1-RX (Enable) (Wake) LIN1-TX GND R144 U3 1 2 RXD 3 EN WAKE 4 TXD INH VSUP LIN GND MC33662BLEF (LEF = 20K Baud) D52 A 0 8 7 6 C D53 5 GF1A C A GF1A 2.0K R7 2.0K VSUP1 HDR_1X3 P6 0.1UF Battery through resistors 2.2UF Reverse (LIN Bus at GND) 10V polarity & C55 (0603 50V) Pulse Protection EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A WAKE = GND ensures no spurious wakeups 4 GND 3 pin header (NOT Molex) = 12mA (0.144W) Each resistor spec = 0.1W (0.2W total) 3 East Kilbride, Scotland A Drawing Title: GND 5 Automotive Microcontroller Applications 1 2 3 LIN1-VSUP LIN1-LIN Total current C56 GND R6 1 (Lin1 only supports Master mode) 2 NXP General Business Use MPC5748G-LCEVB Page Title: CAN and LIN Size B Document Number Date: Friday, February 12, 2016 SCH-27897 Rev B PDF: SPF-27897 Sheet 1 9 of 15 5 4 3 2 1 USB RS232 (serial) Interface FTDI USB <-> Serial Interface - Self Powered mode. No power is taken from USB - Device efaults to Dual serial (RS232) mode i.e. RS232 on both A and B - Configurable I/O voltage on CHA / CHB via VDDIOA/B 5V0_SR PER_HVA D1 D2 D4 D3 4 R119 C101 C115 0.1UF 50V) 470 0.1UF 0.1UF (0603 (0603 50V) 50V) 3V3OUT 3 2 4 1 -D 3 +D 4 1 S1 G V R38 27 USB_N USB_P USB_RN USB_RP 7 R35 27 R34 1.5K C107 C106 R39 4.70K 47PF 47PF DNP DNP 5 4 USBDP RSTOUT# RESET# 5V0_SR GND CLK_XTIN_6M 43 1 XTIN CLK_XTOUT_6M 44 XTOUT R 3 6 X1 6 MHZ R127 2 10.0K 3 GND GND 48 1 EECS 2 EESK EEDATA GND GND1GND2GND3GND 4 TEST AGND 47 24 ADBUS0 23 ADBUS1 22 ADBUS2 21 ADBUS3 20 ADBUS4 19 ADBUS5 17 ADBUS6 16 ADBUS7 15 ACBUS0 13 ACBUS1 12 ACBUS2 11 ACBUS3 10 SI/WUA 40 BDBUS0 39 BDBUS1 38 BDBUS2 37 BDBUS3 36 BDBUS4 35 BDBUS5 BDBUS6 33 BDBUS7 32 BCBUS0 BCBUS1 BCBUS2 BCBUS3 SI/WUB R118 10.0K PWREN# 182534 B 45 9 C103 0.1UF C104 0.1UF (0603 (0603 50V) 50V) GND GND 14 3 1 42 3 USBDM 1.0 M USB_TYPE_B 8 VCCIOA 6 VCC2 GND S2 2 AVCC VCC1 U9 46 C114 0.033UF GND P11 C102 2.2UF 10V C105 (0603 VCCIOB D3 BGX50A 3 2 C D 5V0_SR 1 D All Signals are in power domain VDD_HV_A. FTDI interface will work at 3.3V or 5.0V (PER_HVA) FT2232D 30 29 28 27 26 FTDI Pin 40 (TXD) is Output from FTDI Device, connect to MCU RXD FTDI Pin 39 (RXD) is Input to FTDI device, connect to MCU TXD Send Immediate / Wakeup Disabled for CHA PER_HVA R126 10.0K FTDI_TXD FTDI_RXD R116 R115 0 0 C (MCU_LIN2RX) PC9 PC9 7 (MCU_LIN2TX) PC8 PC8 7 Send Immediate / Wakeup Disabled for CHB PER_HVA 5V0_SR R125 10.0K 41 R117 10.0K DNP Disable Receiver when B in USB suspend mode GND Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: MPC5748G-LCEVB Page Title: USB RS232 Interface Size B Date: 5 4 3 2 Document Number Rev SCH-27897 Friday, February 12, 2016 PDF: SPF-27897 Sheet 1 10 B of 15 5 4 3 2 1 USB (Type A Host and Type AB OTG) 3V3_SR USB Signals General Layout Note. Recommendation is to keep all tracks between MCU and USB PHI less than 3" See additional SMSC Layout guidelines PDF to the right 5V0_SR are in power C6 10UF interface (0603 50V) GND PG14 (USB1_DO) PG15 (USB1_D1) 7 7 7 7 7 7 PE15 PG10 PG11 PH11 PH12 (USB1_D2) (USB1_D3) (USB1_D4) (USB1_D5) (USB1_D6) (USB1_D7) must be left 7 8 PC3 PI4 PC3 PI4 as tri-state 7 PC2 pullups. 8 PI7 set to 5V, USB MCU pads with no 8 PE14 PI5 3 4 5 6 7 9 10 13 30 USB1_CLK PI7 (USB1_RST Active Low) R3 10.0K C64 2 C 3V3_SR 1 33PF R70 GND C63 R71 10 A_XO A_XI (Layout Note: Route DP and DM with (Select 60MHz CLKOUT with 24MHz XTAL) VBUS DM 19 DP 18 23 ID RESET 25 26 XO REFCLK/XI 16 15 SPK_R SPK_L Crystals are FOXSDLF/240F-20 (20pF Load Capacitance) 1.0M USB_TYPE_A_FEMALE P4 90 Ohm Differential Pair. Keep tracks as short as possible) USB_A_EN VDD1V8_28 28 30 USB_A_VBUS R73 (20K for HOST) 20K C54 100UF (1/10W 0603) C67 1.0UF L50 26OHM 2 1 (16V (16V (0402 TANT) TANT) 50v) + + USB_A_DM USB_A_DP (ID=GND for HOST mode) C68 1000pF USB_A_VDD3.3 GND GND C66 C1 1000pF D+ G + S2 USB_A_5V A1 USB_A_DM A2 USB_A_DP A3 C78 A4 R81 1000pf 100 (1210 2KV) 10UF (35V TANT) GND (50V USB_A_VDD1.8 0402) VDD1V8_30 RBIAS D- S1 1 CLKOUT 27 D GND REFSEL0 8 11 REFSEL1 14 REFSEL2 VDD3V3_20 20 33PF Y50 24MHZ USB Host, Type A (Available on all packages) 3V3_SR 22 NXT R65 Adobe Acrobat Document V 2 PC2 10UF CPEN 17 DATA6 DATA7 31 DIR 29 STP (USB1_DIR) (USB1_STP) (USB1_NXT) PI5 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 PAD GND VDD_HVA is 7 33 signals must be 3.3V. If (0603 50V) U50 PG14 PG15 PE14 PE15 PG10 PG11 PH11 PH12 7 C2 21 The USB only supports 3.3V operation. All I/O 0.1UF (Layout Note: Place Series Termination resistor close to USB IC) 32 VDD_HV_A D C3 0.1UF C5 VDDIO VB AT 5V domain GND GND GND 24 C 12 NC USB83340 R72 8.06K 1% GND GND C4 1uF C65 1uF (10V 0603 low ESR) (10V 0603 low ESR) GND Layout Note: Place caps & resistor as close to device as possible 5V0_SR C76 0.1UF C77 10UF USB_A_EN 1 4 (0603 50V) 7 6 B GND USB Power Switch U5 ENA ENB IN FLGA FLGB OUTA GND OUTB MIC2026-1YM 2 FLG_A TPV12 3 FLG_B TPV13 8USB_A_PWR 5 B GND Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: Page Title: Size B Date: 5 4 3 2 MPC5748G-LCEVB USB Type A / Type AB Document Number Rev SCH-27897 Friday, February 12, 2016 PDF: SPF-27897 Sheet 1 11of B 15 5 4 3 2 1 Ethernet (Configured for MII Mode) All Ethernet Signals are in power 3V3_SR L51 3V3_SR 120OHM 1 2 Layout Note - Place Caps and Resistors close to PHI Ethernet MCU pads must be left as R12 10UF PG1 PG1 7 7 7 7 7 7 7 7 7 PE13 PA7 PA8 PA9 PF15 PA11 PA10 PE12 PA3 PE13 PA7 PA8 PA9 PF15 PA11 PA10 PE12 PA3 7 7 PG0 PF14 PG0 PF14 R104 R105 R106 R107 R108 50 50 50 50 50 R32 R31 R30 R29 R28 R24 R26 R27 R25 R22 R109 50 50 50 50 50 50 50 50 50 50 50 MCU Output PHI Output Resistors Next Place Next to to MCU on PHI daughtercard Series Termination Resistors: 50 Ohms as per TI spec. Place resistors as close to driving source as possible. Termination recommended for ALL MII signals (+MII) (+MII) (RMII) (RMII) (RMII) TXD3 TXD2 TXD1 TXD0 TXEN (RMII) TXCLK (+MII) (+MII) (RMII) (RMII) (RMII) (RMII) (+MII) (RMII) RXD3 RXD2 RXD1 RXD0 RXDV RXER COL CRS RXCLK (RMII) (RMII) MDC (+MII) (MDIO) 6 5 4 3 2 1 GND B RST-OUTx RST-OUTx 8 PI11 PI11 R82 25MHZ_OUT 25 TXD3_SNIMODE TXD2 TXD1 TXD0 TXEN TXCLK dp83848c TDP TDN 14 RDP 13 RDP RDN RDN 46 45 44 43 39 41 42 40 38 TPV17 TDP 17 TDN 16 RXD3_PHYAD3 RXD2_PHYAD2 RXD1_PHYAD1 LEDACTCOL_ANEN RXD0_PHYAD1 LEDLINK_AN0 RXDV_MIIMODE LEDSPEED_AN1 RXER_MDIXEN COL_PHYAD0 PFBOUT CRS/CRS_DV/LED_CFG RXCLK PFBIN1 PFBIN2 31 MDC 30 MDIO 28 26 27 LED_Y LED_G 23 PFBOUT R84 10.0K Pulse J1011F21PNL (Includes built in transformer) 3V3_SR (0603 50V) 1% 1 2 3 4 5 GND 6 7 3V3_SR R15 49.9 1% 8 P5 RJ45-8 TD+ TDGND1 CG1 CT_3 GND_4 GND_5 CT_6 CG2 GND2 RD+ RDC C11 0.1UF C8 0.1UF GND C7 0.1UF (0603 (0603 (0603 50V) 50V) 50V) R16 49.9 1% 18 37 R4 R5 270 GND GND 270 3V3_SR 3V3_SR GND 29 RESET 7 PWRDN_INT RBIAS 24 50 GND Place Caps close to connector RBIAS R10 4.87K C72 0.1UF C74 0.1UF C75 (0603 (0603 10UF Layout Note: Place 0.1uF cap close to each pin. 10uF TANT as close to pin 23 as possible as shown in diagram below (0603 taken from TI device specificaiton 50V) (TANT) 50V) PFBIN2 PFBOUT 50V) R83 0 DNP 3V3_SR C10 0.1UF R14 49.9 GND 5 3V3_SR 10/100 single phy RSVD 1RSVD 2RSVD3R SVD4R SVD 5 C PG13 PG12 PH0 PH1 PH2 R13 49.9 1% G C G A U8 34 X1 33 X2 89101 112 7 PG13 PG12 PH0 PH1 PH2 CLKIN_X1 X2 IOVDD33 1IOVDD332 7 7 7 7 7 1 C14 (RMII) (+MII) AVDD33 0 AGN D1 AGND 2 R23 5% RSVDPU1RSVDPU2 GND 33PF GND (0603 50V) 2.2K 5% 1112 Y1 25MHZ (0603 50V) D Y A Y C (0603 50V) 3248 2 33PF 2.2K (Bulk Storage) 2 2 (MII Clock) C15 R11 C79 0.1UF 9 1 0 C71 C81 0.1UF 2021 with no pullups. DGNDIOGND 1IOGND2 tri-state C73 0.1UF 1915363547 D domain VDD_HV_B The Ethernet interface only supports 3.3V operation. All I/O signals must be 3.3V. If VDD_HVA is set to 5V, Reset Control: - Reset from MCU Reset Out (will reset with MCU) - Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in reset while reset config data can be driven onto pins to change mode etc. PFBIN1 C80 0.1UF + B GND Boot Configuration (using PHY internal Pulls) - Auto Negotiation Enable (All speeds / duplex supported) (AN_EN, AN0 and AN1 all Internal PullUP) - Operating Mode (MII) (SNI_Mode Internal PullDown, MII_Mode control via PF15) - LED Configuraiton (Mode1) (LED_CFG Internal PullUp) - MDIX Enable (Auto MDIX Enabled) (MDIX_EN Internal PullUP) R110 PF15 2.2K 5% (MII_MODE) GND Configured for MII Mode MDIO Pullup 3V3_SR R113 1.5K PF14 Automotive Microcontroller Applications East Kilbride, Scotland NXP General Business Use - Physical Address (set to 0b00001) (PHYAD[0] Internal PullUp, PHYAD[1..4] Internal PullDown) A Layout Note: Drawing Title: MII Mode resistor and the MDIP ullup resistor should be placed as close as possible to the PF15 / PF14 tracks to reduce the effect of a stub on the transmission line. Page Title: A MPC5748G-LCEVB Ethernet Size B Date: 5 4 3 2 Document Number Rev SCH-27897 Friday, February 12, 2016 PDF: SPF-27897 Sheet 1 12 B of 15 5 4 3 2 1 FlexRAY Physical Interface All Signals are in D Decoupling Caps for BOTH IC's. Place next to power pins. Note on VBAT: - Operational range is 6.5v to 60V power domain VDD_HV_A. - Undervoltage detection is max 4.5v FlexRAY debug FlexRAY interface will work at 3.3V or 5.0V PC12 PC14 PC12 PC14 PC15 PC13 PC15 PC13 (FR_DBG0) (FR_DBG2) 2 (FR_DBG1) 4 (FR_DBG3) 1 3 D C89 C88 10UF PER_HVA 5V0_SR 10UF R21 0 0 0 0 GND 11 10 PER_HVA BGE: Bus Guardian Enable. Pull high to enable transmitter R88 R87 R121 R91 STBN: Standby Input. Pull High for non standby mode C 10.0K 10.0K 10.0K 10.0K EN: Enable Input. PUll high to FRA-BGE FRA-STBN FRA-EN 5 6 8 9 3 FRA-WAKE 15 enable TRXD0 TRXD1 TXD TXEN BGE STBN EN WAKE 16 GND C84 0.1UF C83 0.1UF C82 0.1UF (0603 50V) (0603 50V) (0603 50V) (0603 50V) FRB2 VBUF VCC VIO GND 1 INH2 2 INH1 18 BP 17 BM 7 RXD 13 ERRN 12 RXEN FRA-INH2 FRA-INH1 FRA-BP R33 47.0 1% TPV9 TPV7 1 L2 2 FRA-DATA-A C16 10PF C91 4700PF P10 (0603) 1 2 (50V 0805) FRA-BM FRA-ERRN FRA-RXEN 4 3 FRA-DATA-B DLW43SH R19 47.0 1% TPV1 TPV4 C12 GND 10PF Crimped lead - 279-9522 Receptacle housing - 279-9156 C (0603) TJA1080TS/N Bus voltage +/- 12V (VBAT = 12v) Components spec'd for 12V operation FlexRAY A GND FRBATB FRB1 PER_HVA 5V0_SR FlexRAY B (FR_B_TX) 7 PE4 PE4 7 PC4 PC4 (FR_B_TX_EN) 7 PE5 PE5 (FR_B_RX) R85 0 FRB-JTXD R79 0 FRB-JTXEN R78 0 FRB-JRXD U4 0 4 19 20 14 R9 VIOVCCVBUF B 10UF C85 0.1UF 4192014 U7 FRA-JTXD FRA-JTXEN FRA-JRXD VBAT R120 R90 R89 VIOVCCVBUF (FR_A_TX) (FR_A_TX_EN) (FR_A_RX) C86 10UF GND PC5 PE2 PE3 GND 11 10 TRXD0 VBAT PC5 PE2 PE3 C87 FRBATA VBAT 7 7 7 PER_HVA resistor and connecting pad to 12v DNP 7 7 5V0_SR applying Vbat and I/O voltages. If necessary, 12V can be externally supplied by removing the P9 7 7 FRBATB should be to battery with 60uS delay between connector (PER_HVA) FRBATA On EVB this is supplied from 5v, In theory this INH2 TRXD1 PER_HVA 5 6 TXD 10.0K 10.0K 10.0K 10.0K FRB-BGE FRB-STBN FRB-EN 8 BP TXEN BM 9 FRB-INH2 FRB-INH1 RXD EN WAKE 16 GND ERRN RXEN 13 12 R20 47.0 1% TPV8 TPV6 FRB-BP 1 FRB-BM 4 L1 2 FRB-DATA-A R8 47.0 1% FRB-ERRN TPV2 FRB-RXEN C13 10PF C90 4700PF B (0603) (50V 0805) 3 FRB-DATA-B DLW43SH 7 3 STBN FRB-WAKE 15 18 17 BGE GND R77 R76 R86 R80 1 2 INH1 TPV3 P8 1 2 C9 10PF GND Crimped lead - 279-9522 Receptacle housing - 279-9156 (0603) TJA1080TS/N Bus voltage +/- 12V (VBAT = 12v) Components spec'd for 12V operation GND MODE Normal Rec Only Go to Sleep Sleep STBN 1 1 0 0 EN 1 0 1 0 Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: Page Title: Size B Date: 5 4 3 2 MPC5748G-LCEVB FlexRAY Physical Interface Document Number Rev SCH-27897 Friday, February 12, 2016 PDF: SPF-27897 Sheet 1 13 B of 15 5 4 3 2 1 User Peripheralls (Led's, Switches and ADC Pot) Switches are hard wired to 3.3V rather than 5V so it's not possible to drive 5V into a 3.3V pad (which would cause damage) Similarly, the LED's are active low with 3.3v supply so can be safely coupled to pads on either 3.3V or 5V domains The ADC input is limited to 3.3V, again to prevent driving 5V into a 3.3V pad which would cause damage User LED's (Active Low) PG[2..5] share eMIOS1 UC[11..14] with PWM C DS1 functionality A DS2 PG2 PG3 PG4 PG2 PG3 PG4 (USR_LED1) (USR_LED2) 7 PG5 PG5 (USR_LED4) C R129 270 R133 270 3V3_SR 3 RV1 2K A 1 RVAR (USR_LED3) DS3 C 270 R130 270 GND A DS4 C R131 Current limit resistors to ensure injection spec of 5mA is not exceeded 1 7 7 7 D ADC Input Pot and Test Point 3V3_SR 2 D A R40 1.5K PB4 PB4 (ADC1_P[0]) 7 R146 1.5K LED's are SMD (1206) Yellow Note that LED2 and LED4 (PG3 and PG5) can be controlled in LPU_RUN mode (and also have pad keepers in LPU_STANDBY) Hex Encoded Switch (Active High) C C 3V3_SR SW1 R92 C 100 A 9 8 B C D E F 0 1 7 6543 2 1 2 (HEX_SW1) (HEX_SW2) 4 8 DRS4016 PD0 PD1 PD0 7,15 PD1 7,15 (HEX_SW3) PD2 PD2 7,15 (HEX_SW4) PD3 PD3 7,15 R93 R94 R95 R96 10.0K 10.0K 10.0K 10.0K GND User Pushbutton Switches (Active High) B 3V3_SR Note - PA1 is B also the NMI pin! SW4 1 2 (PB_SW1) (eMIOS H / X) PA1 PA1 7,15 1 2 (PB_SW2) (eMIOS G / X) PA2 PA2 7,15 R132 R128 10.0K 10.0K SW5 OMRON B3WN-6002 Pushbutton Switch GND Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: Page Title: Size B Date: 5 4 3 2 MPC5748G-LCEVB User Peripherals Document Number Rev SCH-27897 Friday, February 12, 2016 PDF: SPF-27897 Sheet 1 14 B of 15 5 4 GPIO Pin Matrix B PA0 PA1 PA2 PA4 PA5 PA6 PA12 PA13 PA14 PA15 7 PA4 7 7 7 7 7 7 PA5 PA6 PA12 PA13 PA14 PA15 7 7 7 7 7 7 7 7 7 PB5 PB6 PB7 PB10 PB11 PB12 PB13 PB14 PB15 PB5 PB6 PB7 PB10 PB11 PB12 PB13 PB14 PB15 PD0 PD1 PD2 PD3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD12 PD13 PD14 PD15 7,14 7,14 7,14 7,14 7 PD4 7 7 7 7 7 7 7 7 7 7 PD5 PD6 PD7 PD8 PD9 PD10 PD12 PD13 PD14 PD15 7 7 7 7 7 7 7 7 7 7 7 7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 7 7 8 8 8 8 PF12 PF13 PI0 PI1 PI2 PI3 8 PI6 8 8 8 PI8 PI12 PI13 8 PI14 8 PI15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PI0 PI1 PI2 PI3 PI6 PI8 PI12 PI13 PI14 PORTA PORTB PORTD 1 PA0 IOM1 1 PA1 IOM2 PA2 1 IOM3 1 PA4 IOM4 1 PA5 IOM19 1 PA6 IOM20 PA12 IOM36 PA13 IOM37 PA14 IOM38 PA15 IOM55 1 PB5 IOM21 1 PB6 IOM22 PB7 1 IOM23 PB10 IOM39 PB11 IOM40 PB12 IOM41 PB13 IOM42 PB14 IOM43 PB15 IOM56 1 1 1 1 TPH4 GND PortF 1 PD0 IOM5 1 PD1 IOM6 PD2 1 IOM7 1 PD3 IOM8 1 PD4 IOM9 1 PD5 IOM24 1 PD6 IOM25 PD7 1 IOM26 1 PD8 IOM27 PD9 1 IOM28 PD10 1 IOM44 1 PF0 IOM10 PF1 IOM11 PF2 IOM12 PF3 IOM13 PF4 IOM14 PF5 IOM29 PF6 IOM30 PF7 IOM31 PF8 IOM32 PF9 IOM33 PF10 IOM48 PF11 IOM49 PF12 IOM50 PF13 IOM51 1 1 PD12 1 IOM45 PD13 1 IOM46 PD14 1 IOM47 PD15 1 IOM57 1 1 1 TPH5 PortI 1 PI0 IOM15 PI1 IOM16 PI2 IOM17 PI3 IOM18 1 1 1 D 1 1 1 1 1 1 1 1 PI6 IOM34 1 1 1 PI8 IOM35 1 1 1 1 PI12 IOM52 PI13 IOM53 PI14 IOM54 PI15 IOM58 1 TPH6 C 1 1 1 1 TPH7 TPH8 1 PA2 1 1 C PA0 PA1 1 PD[0..3] shared with Hex Switch 7,14 1 user switches D 7 7,14 2 All pads are DNP (Do Not Populate) 0.1" pitch headers placed on a 0.1" grid 1 PA[1,2] shared with 3 5 GND Pads (one at bottom of each colum) B Layout Notes: Pads must be placed in a 5 (W) x 16(H) matrix pattern, 2.54 mm pitch - one column for each port - 16 tall (1 row for each port number from 0 to 15). - GND pad at bottom of each colum - After production, pads should be through hole (not solder filled) PI15 Automotive Microcontroller Applications East Kilbride, Scotland A A NXP General Business Use Drawing Title: MPC5748G-LCEVB Page Title: GPIO Pin Matrix Size B Date: 5 4 3 2 1 Document Number Rev SCH-27897 Friday, February 12, 2016 PDF: SPF-27897 Sheet 15 B of 15 9. Revision History Date Substantial changes March 2016 Initial release August 2016 Rev. 1: Updated Schematics and Board Pictures MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016 34 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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