PIC16F5X Data Sheet Flash-Based, 8-Bit CMOS Microcontroller Series (c) 2007 Microchip Technology Inc. DS41213D Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41213D-page ii (c) 2007 Microchip Technology Inc. PIC16F5X Flash-Based, 8-Bit CMOS Microcontroller Series High-Performance RISC CPU: Low-Power Features: * Only 33 single-word instructions to learn * All instructions are single cycle except for program branches which are two-cycle * Two-level deep hardware stack * Direct, Indirect and Relative Addressing modes for data and instructions * Operating speed: - DC - 20 MHz clock speed - DC - 200 ns instruction cycle time * On-chip Flash program memory: - 512 x 12 on PIC16F54 - 2048 x 12 on PIC16F57 - 2048 x 12 on PIC16F59 * General Purpose Registers (SRAM): - 25 x 8 on PIC16F54 - 72 x 8 on PIC16F57 - 134 x 8 on PIC16F59 * Operating Current: - 170 A @ 2V, 4 MHz, typical - 15 A @ 2V, 32 kHz, typical * Standby Current: - 500 nA @ 2V, typical Special Microcontroller Features: * Power-on Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable Code Protection * Power-Saving Sleep mode * In-Circuit Serial ProgrammingTM (ICSPTM) * Selectable oscillator options: - RC: Low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - LP: Power-saving, low-frequency crystal * Packages: - 18-pin PDIP and SOIC for PIC16F54 - 20-pin SSOP for PIC16F54 - 28-pin PDIP, SOIC and SSOP for PIC16F57 - 40-pin PDIP for PIC16F59 - 44-pin TQFP for PIC16F59 Program Memory Peripheral Features: * 12/20/32 I/O pins: - Individual direction control - High current source/sink * 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler CMOS Technology: * Wide operating voltage range: - Industrial: 2.0V to 5.5V - Extended: 2.0V to 5.5V * Wide temperature range: - Industrial: -40C to 85C - Extended: -40C to 125C * High-endurance Flash: - 100K write/erase cycles - > 40-year retention Data Memory Device I/O Flash (words) SRAM (bytes) Timers 8-bit PIC16F54 512 25 12 1 PIC16F57 2048 72 20 1 PIC16F59 2048 134 32 1 (c) 2007 Microchip Technology Inc. DS41213D-page 1 PIC16F5X Pin Diagrams PDIP, SOIC 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 T0CKI *1 28 MCLR/VPP VDD 2 27 OSC1/CLKIN N/C 3 26 VSS 4 25 OSC2/CLKOUT RC7 N/C 5 24 RC6 RA0 6 23 RA1 7 RA2 8 21 RC5 RC4 RC3 RA3 9 20 RC2 RB0 10 19 RC1 RB1 11 18 RC0 RB2 12 17 RB7/ICSPDAT RB3 13 16 RB6/ICSPCLK RB4 14 15 RB5 PIC16F57 *1 2 3 4 5 6 7 8 9 RA2 RA3 T0CKI MCLR/VPP VSS RB0 RB1 RB2 RB3 PIC16F54 PDIP, SOIC 22 SSOP SSOP 20 19 18 17 16 15 14 13 12 11 PIC16F54 *1 2 3 4 5 6 7 8 9 10 RA2 RA3 T0CKI MCLR/VPP VSS VSS RB0 RB1 RB2 RB3 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 *1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16F57 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7/ICSPDAT RB6/ICSPCLK RB5 T0CKI 39 RE7 3 38 RA3 4 37 RE6 RE5 GND 5 36 RE4 RB0 6 35 RB1 7 34 VDD OSC1/CLKIN RB2 8 33 RB3 9 32 RB4 10 11 12 RB7/ICSPDAT 13 28 MCLR/VPP 14 27 VDD 15 26 RC0 16 25 GND RC1 17 24 RD0 RC2 18 23 RC7 RC3 19 22 RC6 RC4 20 21 RC5 PIC16F59 RB5 RB6/ICSPCLK GND GND RB0 OSC2/CLKOUT RB1 RD7 RB2 RB3 RD6 RB4 RD5 RB5 RB6/ICSPCLK RD4 RB7/ICSPDAT RD3 MCLR/VPP RD2 RD1 31 30 29 44 43 42 41 40 39 38 37 36 35 34 40 2 1 2 3 4 5 6 7 8 9 10 11 PIC16F59 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 *1 RA1 RA2 OSC1/CLKIN OSC2/CLKOUT RD7 RD6 RD5 RD4 RD3 RD2 RD1 GND GND VDD VDD RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RA0 RA3 RA2 RA1 RA0 T0CKI RE7 RE6 RE5 RE4 VDD VDD TQFP PDIP, 0.600" DS41213D-page 2 VSS T0CKI VDD VDD RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 VSS (c) 2007 Microchip Technology Inc. PIC16F5X Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 Architectural Overview ................................................................................................................................................................. 7 3.0 Memory Organization ................................................................................................................................................................. 13 4.0 Oscillator Configurations ............................................................................................................................................................ 21 5.0 Reset .......................................................................................................................................................................................... 23 6.0 I/O Ports ..................................................................................................................................................................................... 29 7.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 33 8.0 Special Features of the CPU...................................................................................................................................................... 37 9.0 Instruction Set Summary ............................................................................................................................................................ 41 10.0 Development Support................................................................................................................................................................. 53 11.0 Electrical Specifications for PIC16F54/57 .................................................................................................................................. 57 11.0 Electrical Specifications for PIC16F59 (continued) .................................................................................................................... 58 12.0 Packaging Information................................................................................................................................................................ 69 The Microchip Web Site ....................................................................................................................................................................... 83 Customer Change Notification Service ................................................................................................................................................ 83 Customer Support ................................................................................................................................................................................ 83 Reader Response ................................................................................................................................................................................ 84 Product Identification System .............................................................................................................................................................. 85 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2007 Microchip Technology Inc. DS41213D-page 3 PIC16F5X NOTES: DS41213D-page 4 (c) 2007 Microchip Technology Inc. PIC16F5X 1.0 GENERAL DESCRIPTION 1.1 The PIC16F5X from Microchip Technology is a family of low-cost, high-performance, 8-bit, fully static, Flashbased CMOS microcontrollers. It employs a RISC architecture with only 33 single-word/single-cycle instructions. All instructions are single cycle except for program branches which take two cycles. The PIC16F5X delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easyto-remember instruction set reduces development time significantly. The PIC16F5X products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Powersaving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. Applications The PIC16F5X series fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The Flash technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, lowpower, high performance, ease of use and I/O flexibility make the PIC16F5X series very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of "glue" logic in larger systems, co-processor applications). The PIC16F5X products are supported by a full-featured macro assembler, a software simulator, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM(R) PC and compatible machines. TABLE 1-1: PIC16F5X FAMILY OF DEVICES Features Maximum Operation Frequency Flash Program Memory (x12 words) RAM Data Memory (bytes) Timer Module(s) PIC16F54 PIC16F57 PIC16F59 20 MHz 20 MHz 20 MHz 512 2K 2K 25 72 134 TMR0 TMR0 TMR0 I/O Pins 12 20 32 Number of Instructions 33 33 33 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC; 28-pin SSOP 40-pin DIP, 44-pin TQFP Packages Note: All PIC(R) Family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability. (c) 2007 Microchip Technology Inc. DS41213D-page 5 PIC16F5X NOTES: DS41213D-page 6 (c) 2007 Microchip Technology Inc. PIC16F5X 2.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F5X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F5X uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide, making it possible to have all singleword instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle except for program branches. The PIC16F54 addresses 512 x 12 of program memory, the PIC16F57 and PIC16F59 addresses 2048 x 12 of program memory. All program memory is internal. The PIC16F5X can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the program counter, are mapped in the data memory. The PIC16F5X has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any Addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16F5X simple, yet efficient. In addition, the learning curve is reduced significantly. (c) 2007 Microchip Technology Inc. The PIC16F5X device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS Register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 2-1 with the corresponding device pins described in Table 2-1 (for PIC16F54), Table 2-2 (for PIC16F57) and Table 2-3 (for PIC16F59). DS41213D-page 7 PIC16F5X FIGURE 2-1: Flash 512 X 12 (F54) 2048 X 12(F57) 2048 x 12(F59) PIC16F5X SERIES BLOCK DIAGRAM 9-11 9-11 T0CKI Pin Stack 1 Stack 2 OSC1 OSC2 MCLR Configuration Word "Disable" "Osc Select" PC Watchdog Timer 12 2 "CodeProtect" Oscillator/ Timing & Control Instruction Register 9 CLKOUT WDT/TMR0 Prescaler WDT Time-out 12 8 "Sleep" Instruction Decoder 6 "Option" Option Reg. Direct Address Direct RAM Address From W 5 5-7 8 Literals STATUS TMR0 General Purpose Register File (SRAM) 25, 72 or 134 Bytes SFR 8 W Data Bus ALU 8 From W 4 TRISA From W 4 From W 8 8 TRISB PORTA PORTB 4 8 "TRIS 6" "TRIS 5" RA<3:0> 8 4 PORTC 8 "TRIS 7" RC<7:0> PIC16F57/59 only PORTE 8 8 TRISD PORTD 8 4 "TRIS 9" RE<7:4> PIC16F59 only DS41213D-page 8 TRISC From W From W TRISE RB<7:0> 8 8 "TRIS 8" RD<7:0> PIC16F59 only (c) 2007 Microchip Technology Inc. PIC16F5X TABLE 2-1: PIC16F54 PINOUT DESCRIPTION Function Input Type Output Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS Bidirectional I/O pin Name RB7/ICSPDAT Description ICSPCLK ST -- RB7 TTL CMOS Bidirectional I/O pin Serial Programming Clock Serial Programming I/O ICSPDAT ST CMOS T0CKI T0CKI ST -- Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP MCLR ST -- Active-low Reset to device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. VPP HV -- Programming voltage input OSC1/CLKIN OSC2/CLKOUT VDD VSS Legend: I O ST OSC1 XTAL -- Oscillator crystal input CLKIN ST -- External clock source input OSC2 -- XTAL CLKOUT -- CMOS VDD Power -- VSS Power -- = input = output = Schmitt Trigger input (c) 2007 Microchip Technology Inc. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin can output CLKOUT, which has 1/4 the frequency of OSC1. Positive supply for logic and I/O pins Ground reference for logic and I/O pins I/O = input/output -- = Not Used TTL = TTL input CMOS = CMOS output XTAL = Crystal input/output HV = High Voltage DS41213D-page 9 PIC16F5X TABLE 2-2: PIC16F57 PINOUT DESCRIPTION Function Input Type Output Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS Bidirectional I/O pin Name RB7/ICSPDAT Description ICSPCLK ST -- RB7 TTL CMOS Bidirectional I/O pin Serial programming clock ICSPDAT ST CMOS Serial programming I/O RC0 RC0 TTL CMOS Bidirectional I/O pin RC1 RC1 TTL CMOS Bidirectional I/O pin RC2 RC2 TTL CMOS Bidirectional I/O pin RC3 RC3 TTL CMOS Bidirectional I/O pin RC4 RC4 TTL CMOS Bidirectional I/O pin RC5 RC5 TTL CMOS Bidirectional I/O pin RC6 RC6 TTL CMOS Bidirectional I/O pin Bidirectional I/O pin RC7 RC7 TTL CMOS T0CKI T0CKI ST -- Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP MCLR ST -- Active-low Reset to device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. VPP HV -- Programming voltage input OSC1/CLKIN OSC1 XTAL -- Oscillator crystal input CLKIN ST -- External clock source input OSC2 -- XTAL Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT -- CMOS In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1. VDD VDD Power -- VSS VSS Power -- Ground reference for logic and I/O pins N/C N/C -- -- Unused, do not connect OSC2/CLKOUT Legend: I = input O = output ST = Schmitt Trigger input DS41213D-page 10 Positive supply for logic and I/O pins I/O = input/output -- = Not Used TTL = TTL input CMOS = CMOS output XTAL = Crystal input/output HV = High Voltage (c) 2007 Microchip Technology Inc. PIC16F5X TABLE 2-3: PIC16F59 PINOUT DESCRIPTION Function Input Type Output Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS ICSPCLK ST -- Name RB7/ICSPDAT Description Bidirectional I/O pin Serial programming clock RB7 TTL CMOS Bidirectional I/O pin ICSPDAT ST CMOS Serial programming I/O RC0 RC0 TTL CMOS Bidirectional I/O pin RC1 RC1 TTL CMOS Bidirectional I/O pin RC2 RC2 TTL CMOS Bidirectional I/O pin RC3 RC3 TTL CMOS Bidirectional I/O pin RC4 RC4 TTL CMOS Bidirectional I/O pin RC5 RC5 TTL CMOS Bidirectional I/O pin RC6 RC6 TTL CMOS Bidirectional I/O pin RC7 RC7 TTL CMOS Bidirectional I/O pin RD0 RD0 TTL CMOS Bidirectional I/O pin RD1 RD1 TTL CMOS Bidirectional I/O pin RD2 RD2 TTL CMOS Bidirectional I/O pin RD3 RD3 TTL CMOS Bidirectional I/O pin RD4 RD4 TTL CMOS Bidirectional I/O pin RD5 RD5 TTL CMOS Bidirectional I/O pin RD6 RD6 TTL CMOS Bidirectional I/O pin RD7 RD7 TTL CMOS Bidirectional I/O pin RE4 RE4 TTL CMOS Bidirectional I/O pin RE5 RE5 TTL CMOS Bidirectional I/O pin RE6 RE6 TTL CMOS Bidirectional I/O pin RE7 RE7 TTL CMOS T0CKI T0CKI ST -- Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP MCLR ST -- Active-low Reset to device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. VPP HV -- Programming voltage input OSC1/CLKIN OSC1 XTAL -- Oscillator crystal input CLKIN ST -- OSC2 -- XTAL Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT -- CMOS In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1. OSC2/CLKOUT Bidirectional I/O pin External clock source input VDD VDD Power -- Positive supply for logic and I/O pins VSS VSS Power -- Ground reference for logic and I/O pins Legend: I = input O = output ST = Schmitt Trigger input (c) 2007 Microchip Technology Inc. I/O = input/output -- = Not Used TTL = TTL input CMOS XTAL HV = CMOS output = Crystal input/output = High Voltage DS41213D-page 11 PIC16F5X 2.1 Clocking Scheme/Instruction Cycle 2.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the Program Counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 2-1). The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 2-2 and Example 2-1. A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the instruction register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 2-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC PC OSC2/CLKOUT (RC mode) EXAMPLE 2-1: PC + 1 Fetch INST (PC) Execute INST (PC - 1) PC + 2 Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) INSTRUCTION PIPELINE FLOW 1. MOVLW H'55' 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. DS41213D-page 12 (c) 2007 Microchip Technology Inc. PIC16F5X 3.0 MEMORY ORGANIZATION PIC16F5X memory is organized into program memory and data memory. For the PIC16F57 and PIC16F59, which have more than 512 words of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS register bits. For the PIC16F57 and PIC16F59, which have a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR). A NOP at the Reset vector location will cause a restart at location 000h. The Reset vector for the PIC16F54 is at 1FFh. The Reset vector for the PIC16F57 and PIC16F59 is at 7FFh. See Section 3.5 "Program Counter" for additional information using CALL and GOTO instructions. FIGURE 3-1: 11 CALL, RETLW Stack Level 1 Stack Level 2 000h On-chip Program Memory (Page 0) Program Memory Organization The PIC16F54 has a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 3-1). The PIC16F57 and PIC16F59 have an 11-bit Program Counter capable of addressing a 2K x 12 program memory space (Figure 3-2). Accessing a location above the physically implemented address will cause a wraparound. PIC16F57/PIC16F59 PROGRAM MEMORY MAP AND STACK PC<10:0> 0FFh 100h 1FFh 200h User Memory Space 3.1 FIGURE 3-2: On-chip Program Memory (Page 1) 2FFh 300h 3FFh 400h On-chip Program Memory (Page 2) 4FFh 500h 5FFh 600h On-chip Program Memory (Page 3) 6FFh 700h Reset Vector 7FFh PIC16F54 PROGRAM MEMORY MAP AND STACK PC<8:0> 9 CALL, RETLW Stack Level 1 Stack Level 2 User Memory Space 000h On-chip Program Memory 0FFh 100h Reset Vector 1FFh (c) 2007 Microchip Technology Inc. DS41213D-page 13 PIC16F5X 3.2 3.2.1 Data Memory Organization Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). GENERAL PURPOSE REGISTER FILE The register file is accessed either directly or indirectly through the File Select Register (FSR). The FSR register is described in Section 3.7 "Indirect Data Addressing; INDF and FSR Registers". The Special Function Registers include the TMR0 register, the Program Counter (PC), the STATUS register, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Purpose Registers are used to control the I/O port configuration and prescaler options. FIGURE 3-3: File Address The General Purpose Registers are used for data and control information under command of the instructions. For the PIC16F54, the register file is composed of 7 Special Function Registers and 25 General Purpose Registers (Figure 3-3). For the PIC16F57, the register file is composed of 8 Special Function Registers, 8 General Purpose Registers and 64 additional General Purpose Registers that may be addressed using a banking scheme (Figure 3-4). 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h General Purpose Registers For the PIC16F59, the register file is composed of 10 Special Function Registers, 6 General Purpose Registers and 128 additional General Purpose Registers that may be addressed using a banking scheme (Figure 3-5). FIGURE 3-4: PIC16F54 REGISTER FILE MAP 1Fh Note 1: Not a physical register. See Section 3.7 "Indirect Data Addressing; INDF and FSR Registers". PIC16F57 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h General Purpose Registers 0Fh 10h 20h 2Fh 4Fh 6Fh 30h 50h 70h Note 1: DS41213D-page 14 General Purpose Registers 3Fh Bank 0 60h Addresses map back to addresses in Bank 0. General Purpose Registers 1Fh 40h General Purpose Registers 5Fh Bank 1 General Purpose Registers 7Fh Bank 2 Bank 3 Not a physical register. See Section 3.7 "Indirect Data Addressing; INDF and FSR Registers". (c) 2007 Microchip Technology Inc. PIC16F5X FIGURE 3-5: PIC16F59 REGISTER FILE MAP FSR<7:5> 000 001 010 011 100 101 110 111 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h PORTD 09h PORTE 20h 40h 60h 80h A0h C0h E0h Addresses map back to addresses in Bank 0. 0Ah 0Fh General Purpose Registers 10h General Purpose Registers 1Fh Bank 0 Note 1: 2Fh 4Fh 6Fh 8Fh AFh CFh EFh 30h General Purpose Registers 3Fh 50h General Purpose Registers 5Fh 70h General Purpose Registers 7Fh 90h General Purpose Registers 9Fh B0h General Purpose Registers BFh D0h General Purpose Registers DFh F0h General Purpose Registers FFh Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 1 Not a physical register. (c) 2007 Microchip Technology Inc. DS41213D-page 15 PIC16F5X 3.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFR) are registers used by the CPU and peripheral functions to control the operation of the device (Table 3-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 3-1: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Details on Page N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC, TRISD, TRISE) 1111 1111 29 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 18 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20 01h TMR0 Timer0 Module Register xxxx xxxx 34 02h PCL(1) Low order 8 bits of PC 1111 1111 19 03h STATUS 0001 1xxx 17 04h FSR(3) Indirect data memory Address Pointer 111x xxxx 20 04h FSR(4) Indirect data memory Address Pointer 1xxx xxxx 20 04h (5) FSR Indirect data memory Address Pointer xxxx xxxx 20 05h PORTA(6) ---- xxxx 29 PA2 -- PA1 -- PA0 -- TO -- PD RA3 Z RA2 DC RA1 C RA0 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 29 07h PORTC(2) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 29 08h PORTD(7) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 29 09h PORTE(6), (7) RE7 RE6 RE5 RE4 -- -- -- -- xxxx ---- 29 Legend: Shaded cells = unimplemented or unused, - = unimplemented, read as `0' (if applicable), x = unknown, u = unchanged Note 1: The upper byte of the Program Counter is not directly accessible. See Section 3.5 "Program Counter" for an explanation of how to access these bits. 2: File address 07h is a General Purpose Register on the PIC16F54. 3: PIC16F54 only. 4: PIC16F57 only. 5: PIC16F59 only. 6: Unimplemented bits are read as `0's. 7: File address 08h and 09h are General Purpose Registers on the PIC16F54 and PIC16F57. DS41213D-page 16 (c) 2007 Microchip Technology Inc. PIC16F5X 3.3 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bits for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF, MOVWF and SWAPF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 9.0 "Instruction Set Summary". STATUS REGISTER (ADDRESS: 03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x PA2 PA1 PA0 TO PD Z DC C bit 7 bit 0 bit 7 PA2: Reserved, do not use Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5 PA<1:0>: Program Page Preselect bits (PIC16F57/PIC16F59) 00 = Page 0 (000h-1FFh) 01 = Page 1 (200h-3FFh) 10 = Page 2 (400h-5FFh) 11 = Page 3 (600h-7FFh) Each page is 512 words. Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended. This may affect upward compatibility with future products. bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry to the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow to the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared (c) 2007 Microchip Technology Inc. x = Bit is unknown DS41213D-page 17 PIC16F5X 3.4 Option Register The Option register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the Option register. A Reset sets the Option<5:0> bits. REGISTER 3-2: OPTION REGISTER U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1 -- -- T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler rate select bits Bit Value Timer0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Legend: DS41213D-page 18 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown (c) 2007 Microchip Technology Inc. PIC16F5X 3.5 FIGURE 3-7: Program Counter As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. LOADING OF PC BRANCH INSTRUCTIONS - PIC16F57 AND PIC16F59 GOTO Instruction 10 9 8 7 PCL For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 3-6 and Figure 3-7). Instruction Word 2 For the PIC16F57 and PIC16F59, a page number must be supplied as well. Bit 5 and bit 6 of the STATUS register provide page information to bit 9 and bit 10 of the PC (Figure 3-6 and Figure 3-7). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 3-6 and Figure 3-7). 0 Status CALL or Modify PCL Instruction 10 FIGURE 3-6: LOADING OF PC BRANCH INSTRUCTIONS - PIC16F54 GOTO Instruction 8 7 0 PCL PC CALL or Modify PCL Instruction PC Reset to '0' 7 Instruction Word 0 PCL Instruction Word 2 Reset to `0' PA<1:0> 7 0 Status 3.5.1 PAGING CONSIDERATIONS PIC16F57 AND PIC16F59 If the PC is pointing to the last address of a selected memory page, when it increments, it will cause the program to continue in the next higher page. However, the page preselect bits in the STATUS register will not be updated. Therefore, the next GOTO, CALL or MODIFY PCL instruction will send the program to the page specified by the page preselect bits (PA0 or PA<1:0>). For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address xxh on page 0 (assuming that PA<1:0> are clear). 3.5.2 0 PCL 8 7 To prevent this, the page preselect bits must be updated under program control. Instruction Word 8 9 PC For the PIC16F57 and PIC16F59, a page number again must be supplied. Bit 5 and bit 6 of the STATUS register provide page information to bit 9 and bit 10 of the PC (Figure 3-6 and Figure 3-7). Because PC<8> is cleared in the CALL instruction or any modified PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). PA<1:0> 7 Instructions where the PCL is the destination or modify PCL instructions, include MOVWF PCL, ADDWF PCL, and BSF PCL,5. Note: 0 PC EFFECTS OF RESET The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the Reset vector). The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is preselected. Therefore, upon a Reset, a GOTO instruction at the Reset vector location will automatically cause the program to jump to page 0. (c) 2007 Microchip Technology Inc. DS41213D-page 19 PIC16F5X 3.6 Stack The PIC16F54 device has a 9-bit wide, two-level hardware PUSH/POP stack. The PIC16F57 and PIC16F59 devices have an 11-bit wide, two-level hardware PUSH/POP stack. A CALL instruction will PUSH the current value of stack 1 into stack 2 and then PUSH the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL's are executed, only the most recent two return addresses are stored. A RETLW instruction will POP the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW's are executed, the stack will be filled with the address previously stored in level 2. Note: The W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. For the RETLW instruction, the PC is loaded with the Top-of-Stack (TOS) contents. All of the devices covered in this data sheet have a two-level stack. The stack has the same bit width as the device PC, therefore, paging is not an issue when returning from a subroutine. 3.7 Indirect Data Addressing; INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR Register (FSR is a pointer). This is indirect addressing. EXAMPLE 3-1: INDIRECT ADDRESSING * * * * Register file 08 contains the value 10h Register file 09 contains the value 0Ah Load the value 08 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 09h) * A read of the INDF register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 3-2. EXAMPLE 3-2: NEXT MOVLW MOVWF CLRF INCF BTFSC GOTO HOW TO CLEAR RAM USING INDIRECT ADDRESSING H'10' FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF Register ;inc pointer ;all done? ;NO, clear next CONTINUE : ;YES, continue The FSR is either a 5-bit (PIC16F54), 7-bit (PIC16F57) or 8-bit (PIC16F59) wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC16F54: This does not use banking. FSR<7:5> bits are unimplemented and read as `1's. PIC16F57: FSR<7> bit is unimplemented and read as `1'. FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3). PIC16F59: FSR<7:5> are the bank select bits and are used to select the bank to be addressed (000 = Bank 0, 001 = Bank 1, 010 = Bank 2, 011 = Bank 3, 100 = Bank 4, 101 = Bank 5, 110 = Bank 6, 111 = Bank 7). Note: DS41213D-page 20 A CLRF FSR instruction may not result in an FSR value of 00h if there are unimplemented bits present in the FSR. (c) 2007 Microchip Technology Inc. PIC16F5X 4.0 OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types TABLE 4-1: Osc Type The PIC16F5X devices can be operated in four different oscillator modes. The user can program two Configuration bits (FOSC1:FOSC0) to select one of these four modes: * * * * LP: XT: HS: RC: Low-power Crystal Crystal/Resonator High-speed Crystal/Resonator Resistor/Capacitor 4.2 Crystal Oscillator/Ceramic Resonators In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 4-1). The PIC16F5X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency outside of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 4-2). FIGURE 4-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) C1(1) OSC1 PIC16F5X Sleep XTAL RF(3) OSC2 To internal logic RS(2) CAPACITOR SELECTION FOR CERAMIC RESONATORS Resonator Freq. Cap. Range C1 Cap. Range C2 XT 455 kHz 68-100 pF 68-100 pF 2.0 MHz 15-33 pF 15-33 pF 4.0 MHz 10-22 pF 10-22 pF HS 8.0 MHz 10-22 pF 10-22 pF 16.0 MHz 10 pF 10 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. TABLE 4-2: Osc Type CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq. Cap.Range C1 Cap. Range C2 LP 32 kHz(1) 15 pF 15 pF XT 100 kHz 200 kHz 455 kHz 1 MHz 2 MHz 4 MHz 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15 pF 15 pF 200-300 pF 100-200 pF 15-100 pF 15-30 pF 15 pF 15 pF HS 4 MHz 8 MHz 20 MHz 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specifications. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Note 1: C2(1) Note 1: 2: 3: See Capacitor Selection tables for recommended values of C1 and C2. A series resistor (RS) may be required. RF varies with the Oscillator mode chosen (approx. value = 10 M). FIGURE 4-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from ext. system OSC1 Open OSC2 PIC16F5X (c) 2007 Microchip Technology Inc. Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. 2: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required. DS41213D-page 21 PIC16F5X 4.3 External Crystal Oscillator Circuit FIGURE 4-4: Either a pre-packaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Pre-packaged oscillators provide a wide operating range and better stability. A well designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance or one with series resonance. Figure 4-3 shows an implementation example of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180 phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. FIGURE 4-3: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE) +5V To Other Devices 10k 74AS04 4.7k PIC16F5X CLKIN 74AS04 Open OSC2 10k XTAL To Other Devices 330 K 330 K 74AS04 74AS04 74AS04 PIC16F5X CLKIN 0.1 F Open XTAL 4.4 OSC2 RC Oscillator For applications where precise timing is not a requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is dependent upon a number of variables. The RC oscillator frequency is a function of: * Supply voltage * Resistor (REXT) and capacitor (CEXT) values * Operating temperature. The oscillator frequency will vary from unit to unit due to normal process parameter variation. The difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to account for the tolerance of the external R and C components. Figure 4-5 shows how the R/C combination is connected. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin and can be used for test purposes or to synchronize other logic. 10k 20 pF EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE) 20 pF FIGURE 4-5: RC OSCILLATOR MODE VDD Figure 4-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverters perform a 360 phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region. REXT OSC1 N CEXT Internal clock PIC16F5X VSS OSC2/CLKOUT FOSC/4 DS41213D-page 22 (c) 2007 Microchip Technology Inc. PIC16F5X 5.0 RESET The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different Reset conditions (Table 5-1). These bits may be used to determine the nature of the Reset. The PIC16F5X devices may be reset in one of the following ways: * * * * * Power-on Reset (POR) MCLR Reset (normal operation) MCLR Wake-up Reset (from Sleep) WDT Reset (normal operation) WDT Wake-up Reset (from Sleep) Table 5-3 lists a full description of Reset states of all registers. Figure 5-1 shows a simplified block diagram of the on-chip Reset circuit. Table 5-1 shows these Reset conditions for the PCL and STATUS registers. Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on Power-on Reset (POR), MCLR or WDT Reset. A MCLR or WDT wake-up from Sleep also results in a device Reset and not a continuation of operation before Sleep. TABLE 5-1: STATUS BITS AND THEIR SIGNIFICANCE Condition TO PD Power-on Reset 1 1 MCLR Reset (normal operation) u u MCLR Wake-up (from Sleep) 1 0 WDT Reset (normal operation) 0 1 WDT Wake-up (from Sleep) 0 0 Legend: u = unchanged, x = unknown, -- = unimplemented read as `0'. TABLE 5-2: Address 03h SUMMARY OF REGISTERS ASSOCIATED WITH RESET Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STATUS PA2 PA1 PA0 TO PD Z DC C Value on POR Value on MCLR and WDT Reset 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, q = see Table 5-1 for possible values. (c) 2007 Microchip Technology Inc. DS41213D-page 23 PIC16F5X TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS Register Address Power-on Reset MCLR or WDT Reset W N/A xxxx xxxx uuuu uuuu TRIS N/A 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000q quuu (1) FSR 04h 111x xxxx 111u uuuu FSR(2) 04h 1xxx xxxx 1uuu uuuu FSR(3) 04h xxxx xxxx uuuu uuuu PORTA 05h ---- xxxx ---- uuuu PORTB 06h xxxx xxxx uuuu uuuu PORTC(4) 07h xxxx xxxx uuuu uuuu PORTD(5) 08h xxxx xxxx uuuu uuuu PORTE(5) 09h xxxx ---- uuuu ---- Legend: u = unchanged, x = unknown, - = unimplemented, read as `0', q = see tables in Table 5-1 for possible values. Note 1: PIC16F54 only. 2: PIC16F57 only. 3: PIC16F59 only. 4: General purpose register file on PIC16F54. 5: General purpose register file on PIC16F54 and PIC16F57. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD POR MCLR/VPP MCLR Filter S R WDT Module Q Chip Reset DRT Reset DS41213D-page 24 (c) 2007 Microchip Technology Inc. PIC16F5X 5.1 Power-on Reset (POR) The PIC16F5X family of devices incorporate on-chip Power-on Reset (POR) circuitry which provides an internal chip Reset for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 5-1. The Power-on Reset circuit and the Device Reset Timer (Section 5.2) circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the Reset latch and thus end the onchip Reset signal. A power-up example where MCLR is not tied to VDD is shown in Figure 5-3. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. In Figure 5-4, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together). The VDD is stable before the start-up timer times out and there is no problem in getting a proper Reset. However, Figure 5-5 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses a high on the MCLR/VPP pin and the MCLR/VPP pin (and VDD) actually reach their full value is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not ensured to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 5-2). FIGURE 5-2: VDD EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD D R R1 MCLR C PIC16F5X * External Power-on Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. * R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specification. * R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Note 1: When the device starts normal operation (exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. 2: The POR is disabled when the device is in Sleep. For more information on the PIC16F5X POR, see Application Note AN522, "Power-Up Considerations" at www.microchip.com. (c) 2007 Microchip Technology Inc. DS41213D-page 25 PIC16F5X FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME FIGURE 5-4: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME FIGURE 5-5: V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note : When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min. DS41213D-page 26 (c) 2007 Microchip Technology Inc. PIC16F5X 5.2 Device Reset Timer (DRT) FIGURE 5-7: The Device Reset Timer (DRT) provides an 18 ms nominal time-out on Reset regardless of the oscillator mode used. The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the chosen oscillator to stabilize. Oscillator circuits, based on crystals or ceramic resonators, require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a Reset condition for approximately 18 ms after the voltage on the MCLR/VPP pin has reached a logic high (VIH) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. The device Reset time delay will vary from chip-to-chip due to VDD, temperature and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16F5X from Sleep mode automatically. 5.3 EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 MCLR R2 40k This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD * FIGURE 5-8: Reset on Brown-Out A Brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a Brown-out. To reset PIC16F5X devices when a Brown-out occurs, external Brown-out protection circuits may be built, as shown in Figure 5-6, Figure 5-7 and Figure 5-8. PIC16F5X R1 R1 + R2 = 0.7V EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 VDD VDD Bypass Capacitor VDD MCP809 VSS RST MCLR PIC16F5X FIGURE 5-6: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD VDD 33k 10k Q1 40k This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both "active-high and active-low" Reset pins. There are 7 different trip point selections to accommodate 5V and 3V systems. MCLR PIC16F5X This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). (c) 2007 Microchip Technology Inc. DS41213D-page 27 PIC16F5X NOTES: DS41213D-page 28 (c) 2007 Microchip Technology Inc. PIC16F5X 6.0 I/O PORTS As with any other register, the I/O registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB, W) always read the I/O pins independent of the pin's Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance), since the I/O control registers (TRISA, TRISB, TRISC, TRISD and TRISE) are all set. 6.1 6.6 The output driver control registers are loaded with the contents of the W register by executing the TRIS f instruction. A `1' from a TRIS register bit puts the corresponding output driver in a High-Impedance (Input) mode. A `0' puts the contents of the output data latch on the selected pins, enabling the output buffer. Note: PORTA PORTA is a 4-bit I/O register. Only the low order 4 bits are used (PORTA<3:0>). The high order 4 bits (PORTA<7:4>) are unimplemented and read as `0's. 6.2 PORTB TRIS Registers A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. The TRIS registers are "write-only" and are set (output drivers disabled) upon Reset. PORTB is an 8-bit I/O register (PORTB<7:0>). 6.7 6.3 The equivalent circuit for an I/O port pin is shown in Figure 6-1. All ports may be used for both input and output operation. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB, TRISC, TRISD and TRISE) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output. PORTC PORTC is an 8-bit I/O register (PORTC<7:0>) for the PIC16F57 and PIC16F59. PORTC is a General Purpose Register for the PIC16F54. 6.4 PORTD PORTD is an 8-bit I/O register (PORTD<7:0>) for the PIC16F59. PORTD is a General Purpose Register for the PIC16F54 and PIC16F57. 6.5 I/O Interfacing FIGURE 6-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN PORTE PORTE is an 4-bit I/O register for the PIC16F59. Only the high order 4 bits are used (PORTE<7:4>). The low order 4 bits (PORTE<3:0>) are unimplemented and read as `0's. Data Bus D WR Port Q Data Latch CK VDD Q P PORTE is a General Purpose Register for the PIC16F54 and PIC16F57. W Reg I/O pin N D Q TRIS Latch TRIS `f' VDD CK VSS VSS Q Reset Q D E RD Port (c) 2007 Microchip Technology Inc. DS41213D-page 29 PIC16F5X TABLE 6-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on MCLR and WDT Reset N/A TRIS 05h PORTA I/O Control Registers (TRISA, TRISB, TRISC, TRISD and TRISE) 1111 1111 1111 1111 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h PORTC(1) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 08h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 09h PORTE(2) RE7 RE6 RE5 RE4 -- -- -- -- xxxx ---- uuuu ---- -- -- -- -- RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu Legend: Shaded cells = unimplemented, read as `0', - = unimplemented, read as `0', x = unknown, u = unchanged Note 1: File address 07h is a General Purpose Register on the PIC16F54. 2: File address 08h and 09h are General Purpose Registers on the PIC16F54 and PIC16F57. DS41213D-page 30 (c) 2007 Microchip Technology Inc. PIC16F5X 6.8 6.8.1 EXAMPLE 6-1: I/O Programming Considerations BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit 5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit 5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit `0'), and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit `0' is switched into Output mode later on, the content of the data latch may now be unknown. ;Initial PORT Settings ;PORTB<7:4> Inputs ;PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; --------------------BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp MOVLW H'3F' ; TRIS PORTB ;10pp pppp 10pp pppp ; ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High). 6.8.2 Example 6-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (see Figure 6-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. FIGURE 6-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched MOVWF PORTB PC + 1 MOVF PORTB,W PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. RB<7:0> Instruction executed Port pin written here Port pin sampled here MOVWF PORTB (Write to PORTB) MOVF PORTB,W (Read PORTB) Fetch INST (PC) Execute INST (PC - 1) Fetch INST (PC + 1) Execute INST (PC) (c) 2007 Microchip Technology Inc. NOP Fetch INST (PC + 2) Execute INST (PC + 1) Fetch INST (PC + 3) Execute INST (PC + 2) DS41213D-page 31 PIC16F5X NOTES: DS41213D-page 32 (c) 2007 Microchip Technology Inc. PIC16F5X 7.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.1 "Using Timer0 with an External Clock". The Timer0 module has the following features: * 8-bit Timer/Counter register, TMR0 - Readable and writable * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock Note: Figure 7-1 is a simplified block diagram of the Timer0 module. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 7.2 "Prescaler" details the operation of the prescaler. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 7-1: The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. A summary of registers associated with the Timer0 module is found in Table 7-1. TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 PSout 8 1 1 T0CKI pin Programmable Prescaler(2) 0 T0SE(1) Sync with Internal Clocks TMR0 Reg PSout (2 cycle delay) Sync 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: 2: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section 3.4 "Option Register". The prescaler is shared with the Watchdog Timer (Figure 7-5). FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER PC (Program Counter) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Timer0 PC - 1 T0 PC T0 + 1 Instruction Executed (c) 2007 Microchip Technology Inc. PC + 1 PC + 2 PC + 3 T0 + 2 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 PC + 4 NT0 Read TMR0 reads NT0 PC + 5 NT0 + 1 PC + 6 NT0 + 2 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 DS41213D-page 33 PIC16F5X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2 PC (Program Counter) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Timer0 PC - 1 PC T0 PC + 1 PC + 3 T0 + 1 Write TMR0 executed TABLE 7-1: PC + 4 PC + 5 Read TMR0 reads NT0 Read TMR0 reads NT0 PC + 6 NT0 + 1 NT0 Instruction Execute Address PC + 2 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 REGISTERS ASSOCIATED WITH TIMER0 Name 01h TMR0 N/A OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PS2 PS1 PS0 Timer0 - 8-bit real-time clock/counter -- -- T0CS T0SE PSA Value on Power-on Reset Value on MCLR and WDT Reset xxxx xxxx uuuu uuuu --11 1111 --11 1111 Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged. DS41213D-page 34 (c) 2007 Microchip Technology Inc. PIC16F5X 7.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock is the Timer0 input. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-4). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. FIGURE 7-4: 7.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-4 shows the delay from the external clock edge to the timer incrementing. TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Prescaler Output(1) Q1 Q2 Q3 Q4 Small pulse misses sampling (3) External Clock/Prescaler Output After Sampling (2) Increment Timer0 (Q4) Timer0 Note 1: 2: 3: 7.2 T0 T0 + 1 T0 + 2 External clock if no prescaler selected; prescaler output otherwise. The arrows indicate the points in time where sampling occurs. Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC (duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4TOSC max. Prescaler An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 8.2.1 "WDT Period"). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. (c) 2007 Microchip Technology Inc. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all `0's. DS41213D-page 35 PIC16F5X 7.2.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. EXAMPLE 7-2: CLRWDT EXAMPLE 7-1: CLRWDT CLRF MOVLW OPTION CLRWDT MOVLW OPTION CHANGING PRESCALER (TIMER0WDT) MOVLW ;Clear WDT TMR0 ;Clear TMR0 & ;Prescaler B'00xx1111' ;Last 3 instructions ;in this example ;are required only if ;desired ;PS<2:0> are 000 or 001 B'00xx1xxx' ;Set Prescaler to ;desired WDT rate FIGURE 7-5: CHANGING PRESCALER (WDTTIMER0) ;Clear WDT and ;prescaler B'xxxx0xxx' ;Select TMR0, new ;prescale value and ;clock source OPTION BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = FOSC/4) Data Bus 0 T0CKI pin 1 8 M U X 1 M U X 0 T0SE(1) T0CS(1) 0 Watchdog Timer 1 M U X Sync 2 Cycles TMR0 reg PSA(1) 8-bit Prescaler 8 PS<2:0>(1) 8-to-1 MUX PSA(1) 1 0 WDT Enable bit MUX PSA(1) WDT Time-Out Note 1: DS41213D-page 36 T0CS, T0SE, PSA PS<2:0> are bits in the Option register. (c) 2007 Microchip Technology Inc. PIC16F5X 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC16F5X family of microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection. These features are: * * * * * * * * * Oscillator Selection Reset Power-on Reset Device Reset Timer Watchdog Timer (WDT) Sleep Code protection User ID locations In-Circuit Serial ProgrammingTM (ICSPTM) The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through external Reset or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of Configuration bits are used to select various options. 8.1 Configuration Bits Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type; one bit is the Watchdog Timer enable bit; one bit is for code protection for the PIC16F5X devices (Register 8-1). The PIC16F5X family has a Watchdog Timer which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external Reset circuitry. REGISTER 8-1: -- -- CONFIGURATION WORD FOR PIC16F5X -- -- -- -- -- -- CP WDTE FOSC1 FOSC0 bit 11 bit 0 bit 11-4: Unimplemented: Read as `1' bit 3: CP: Code Protection bit. 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator Note 1: Refer to the PIC16F54, PIC16F57 and PIC16F59 Programming Specifications to determine how to access the Configuration Word. These documents can be found on the Microchip web site at www.microchip.com. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = bit is set `0' = bit is cleared (c) 2007 Microchip Technology Inc. x = bit is unknown DS41213D-page 37 PIC16F5X 8.2 8.2.2 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or Wake-up Reset generates a device Reset. The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out and generating a device Reset. The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT Wake-up Reset. FIGURE 8-1: The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset (Section 3.3 "STATUS Register"). WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source The WDT can be permanently disabled by programming the Configuration bit WDTE as a `0' (Section 8.1 "Configuration Bits"). Refer to the PIC16F54 and PIC16F57 Programming Specifications to determine how to access the Configuration Word. These documents can be found on the Microchip web site at www.microchip.com. 8.2.1 WDT PROGRAMMING CONSIDERATIONS Watchdog Timer 0 M 1 U PSA(1) 8-to-1 MUX WDTE PS<2:0>(1) To TMR0 WDT PERIOD An 8-bit counter is available as a prescaler for the Timer0 module (Section 7.2 "Prescaler"), or as a postscaler for the Watchdog Timer (WDT), respectively. For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note: Prescaler X 0 1 PSA(1) MUX WDT Time-out The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio (Section 3.4 "Option Register"). The WDT has a nominal time-out period of 18 ms (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the Option register. Thus time-out, a period of a nominal 2.3 seconds, can be realized. These periods vary with temperature, VDD and part-to-part process variations (see Device Characterization). Under worst case conditions (VDD = Min., Temperature = Max., WDT prescaler = 1:128), it may take several seconds before a WDT time-out occurs. TABLE 8-1: Address N/A SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Name OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- T0CS T0SE PSA PS2 PS1 PS0 Value on Power-on Reset Value on MCLR and WDT Reset --11 1111 --11 1111 Legend: Shaded cells not used by Watchdog Timer, - = unimplemented, read as `0', u = unchanged DS41213D-page 38 (c) 2007 Microchip Technology Inc. PIC16F5X 8.3 Power-Down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 8.3.1 SLEEP The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance). It should be noted that a Reset generated by a WDT time-out does not drive the MCLR/VPP pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the MCLR/VPP pin must be at a logic high level (MCLR = VIH). 8.3.2 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. An external Reset input on MCLR/VPP pin. A Watchdog Timer time-out Reset (if WDT was enabled). Both of these events cause a device Reset. The TO and PD bits can be used to determine the cause of device Reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. 8.4 Program Verification/Code Protection If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. Once code protection is enabled, all program memory locations above 0x3F read all `0's. Program memory locations 0x00-0x3F are always unprotected. The user ID locations and the Configuration Word read out in an unprotected fashion. It is possible to program the user ID locations and the Configuration Word after code protect is enabled. (c) 2007 Microchip Technology Inc. 8.5 User ID Locations Four memory locations are designated as user ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify. Use only the lower 4 bits of the user ID locations and always program the upper 8 bits as `1's. Note: 8.6 Microchip will assign a unique pattern number for QTP and SQTP requests. This pattern number will be unique and traceable to the submitted code. In-Circuit Serial ProgrammingTM (ICSPTM) The PIC16F5X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. Thus, the most recent firmware or custom firmware can be programmed. The device is placed into a Program/Verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the respective Programming Specifications: "PIC16F54 Memory Programming Specification" (DS41207), "PIC16F57 Memory Programming Specification" (DS41208), and "PIC16F59 Memory Programming Specification" (DS41243). A typical In-Circuit Serial Programming connection is shown in Figure 8-1. DS41213D-page 39 PIC16F5X FIGURE 8-1: TYPICAL IN-CIRCUIT SERIAL PROGRAMMINGTM CONNECTION External Connector Signals To Normal Connections PIC16F5X +5V VDD 0V VSS VPP MCLR/VPP CLK RB6/ICSPCLK Data I/O RB7/ICSPDAT VDD To Normal Connections DS41213D-page 40 (c) 2007 Microchip Technology Inc. PIC16F5X 9.0 INSTRUCTION SET SUMMARY Each PIC16F5X instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16F5X instruction set summary in Table 9-2 groups the instructions into byteoriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator is used to specify which one of the 32 file registers in that bank is to be used by the instruction. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time would be 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time would be 2 s. Figure 9-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: The destination designator specifies where the result of the operation is to be placed. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in the file register specified in the instruction. where `h' signifies a hexadecimal digit. For bit-oriented instructions, `b' represents a bit field designator which selects the number of the bit affected by the operation, while `f' represents the number of the file in which the bit is located. Byte-oriented file register operations 0xhhh FIGURE 9-1: 11 TABLE 9-1: OPCODE FIELD DESCRIPTIONS Field f W b k x d label TOS PC WDT TO Description Register file address (0x00 to 0x1F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d = 1 (store result in file register `f') Default is d = 1 Label name Top-of-Stack Program Counter Watchdog Timer Counter 6 OPCODE For literal and control operations, `k' represents an 8- or 9-bit constant or literal value. GENERAL FORMAT FOR INSTRUCTIONS 5 d 4 0 f (FILE #) d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 8 7 5 4 b (BIT #) 0 f (FILE #) b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 8 7 OPCODE 0 k (literal) k = 8-bit immediate value Literal and control operations - GOTO instruction 11 9 8 OPCODE 0 k (literal) k = 9-bit immediate value Time-out bit PD dest Power-down bit Destination, either the W register or the specified register file location [ ] Options ( ) Contents Assigned to < > Register bit field In the set of italics User defined term (c) 2007 Microchip Technology Inc. DS41213D-page 41 PIC16F5X TABLE 9-2: Mnemonic, Operands INSTRUCTION SET SUMMARY 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected ADDWF 0001 11df ffff C,DC,Z 1, 2, 4 f, d Add W and f 1 ANDWF 0001 01df ffff f, d AND W with f 1 Z 2, 4 CLRF 0000 011f ffff f Clear f 1 Z 4 CLRW 0000 0100 0000 -- Clear W 1 Z COMF 0010 01df ffff f, d Complement f 1 Z DECF 0000 11df ffff f, d Decrement f 1 Z 2, 4 DECFSZ 0010 11df ffff f, d Decrement f, Skip if 0 1(2) None 2, 4 1 INCF 0010 10df ffff f, d Increment f Z 2, 4 1(2) INCFSZ 0011 11df ffff f, d Increment f, Skip if 0 None 2, 4 1 IORWF 0001 00df ffff f, d Inclusive OR W with f Z 2, 4 1 MOVF 0010 00df ffff f, d Move f Z 2, 4 1 MOVWF 0000 001f ffff f Move W to f None 1, 4 1 NOP 0000 0000 0000 -- No Operation None 1 RLF 0011 01df ffff f, d Rotate left f through Carry C 2, 4 1 RRF 0011 00df ffff f, d Rotate right f through Carry C 2,4 1 SUBWF 0000 10df ffff C,DC,Z 1, 2, 4 f, d Subtract W from f 1 SWAPF 0011 10df ffff f, d Swap f None 2, 4 1 XORWF 0001 10df ffff f, d Exclusive OR W with f Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS 0100 bbbf ffff None 2, 4 1 Bit Clear f BCF f, b 0101 bbbf ffff None 2, 4 1 Bit Set f BSF f, b 0110 bbbf ffff None Bit Test f, Skip if Clear 1(2) BTFSC f, b 1(2) 0111 bbbf ffff None f, b Bit Test f, Skip if Set BTFSS LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL 1 k Subroutine Call 2 1001 kkkk kkkk None CLRWDT -- Clear Watchdog Timer 1 0000 0000 0100 TO, PD None GOTO k Unconditional branch 2 101k kkkk kkkk Z IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk None MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION -- Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk SLEEP -- Go into Standby mode 1 0000 0000 0011 TO, PD None 3 TRIS f Load TRIS register 1 0000 0000 0fff Z XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Note 1: The 9th bit of the program counter will be forced to a `0' by any instruction that writes to the PC except for GOTO (see Section 3.5 "Program Counter" for more on program counter). 2: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 3: The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the tri-state latches of PORTA, B or C, respectively. A `1' forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS41213D-page 42 (c) 2007 Microchip Technology Inc. PIC16F5X ADDWF Add W and f ANDWF Syntax: [ label ] ADDWF Syntax: [ label ] ANDWF Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (W) + (f) (dest) Operation: (W) .AND. (f) (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df f, d AND W with f ffff Encoding: 0001 01df f, d ffff Description: Add the contents of the W register and register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register 'f'. Description: The contents of the W register are AND'ed with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Words: 1 Words: 1 Cycles: 1 Example: ANDWF Cycles: 1 Example: ADDWF Before Instruction W = TEMP_REG = After Instruction W = TEMP_REG = TEMP_REG, 0 Before Instruction W = TEMP_REG = After Instruction W = TEMP_REG = 0x17 0xC2 0xD9 0xC2 ANDLW AND literal with W Syntax: [ label ] ANDLW Operands: 0 k 255 Operation: (W).AND. (k) (W) Status Affected: Z Encoding: Description: 1110 kkkk k kkkk The contents of the W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: ANDLW H'5F' Before Instruction W = 0xA3 After Instruction W = 0x03 (c) 2007 Microchip Technology Inc. TEMP_REG, 1 0x17 0xC2 0x17 0x02 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 31 0b7 Operation: 0 (f<b>) Status Affected: None Encoding: Description: 0100 bbbf f, b ffff Bit `b' in register `f' is cleared. Words: 1 Cycles: 1 Example: BCF Before Instruction FLAG_REG = After Instruction FLAG_REG = FLAG_REG, 7 0xC7 0x47 DS41213D-page 43 PIC16F5X BSF Bit Set f BTFSS Syntax: [ label ] BSF Syntax: [ label ] BTFSS f, b Operands: 0 f 31 0b7 Operands: 0 f 31 0b<7 Operation: 1 (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 f, b Bit Test f, Skip if Set bbbf Description: Bit `b' in register `f' is set. Words: 1 Cycles: 1 Example: BSF Encoding: ffff FLAG_REG, BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f, b Operands: 0 f 31 0b7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 0110 bbbf ffff Description: If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE * * * Before Instruction PC After Instruction if FLAG<1> PC if FLAG<1> PC DS41213D-page 44 bbbf ffff Description: If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. Words: 1 Cycles: 1(2) Example: HERE FALSE TRUE 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A 0111 Before Instruction PC After Instruction If FLAG<1> PC if FLAG<1> PC BTFSS FLAG,1 GOTO PROCESS_CODE * * * = address (HERE) = = = = 0, address (FALSE); 1, address (TRUE) = address (HERE) = = = = 0, address (TRUE); 1, address(FALSE) (c) 2007 Microchip Technology Inc. PIC16F5X CALL Subroutine Call CLRW Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 k 255 Operands: None Operation: (PC) + 1 TOS; k PC<7:0>; (Status<6:5>) PC<10:9>; 0 PC<8> Operation: 00h (W); 1Z Status Affected: Z Status Affected: Encoding: Description: None 1001 kkkk kkkk Subroutine call. First, return address (PC + 1) is pushed onto the stack. The eight-bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two-cycle instruction. Words: 1 Cycles: 2 Example: HERE CALL Encoding: Description: Clear W 0000 0100 0000 The W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example: CLRW Before Instruction W = 0x5A After Instruction W = 0x00 Z = 1 THERE Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 1) CLRF Clear f Syntax: [ label ] CLRF Operands: CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT 0 f 31 Operands: None Operation: 00h (f); 1Z Operation: Status Affected: Z 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD Status Affected: TO, PD Encoding: Description: 0000 011f f ffff The contents of register `f' are cleared and the Z bit is set. Words: 1 Cycles: 1 Example: CLRF Before Instruction FLAG_REG = After Instruction FLAG_REG = Z = Encoding: 0x00 1 0100 Words: 1 Cycles: 1 Example: CLRWDT Before Instruction WDT counter After Instruction WDT counter WDT prescaler TO PD (c) 2007 Microchip Technology Inc. 0000 The CLRWDT instruction resets the WDT. It also resets the prescaler if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. FLAG_REG 0x5A 0000 Description: = ? = = = = 0x00 0 1 1 DS41213D-page 45 PIC16F5X COMF Complement f DECFSZ Syntax: [ label ] COMF Syntax: [ label ] DECFSZ f, d Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) (dest) Operation: (f) - 1 d; Status Affected: Z Status Affected: None Encoding: 0010 01df f, d Decrement f, Skip if 0 ffff Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Words: 1 Cycles: 1 Example: COMF Before Instruction REG1 = After Instruction REG1 = W = Words: 1 Cycles: 1(2) 0x13 0xEC Example: HERE Syntax: [ label ] DECF f, d Operands: 0 f 31 d [0,1] Operation: (f) - 1 (dest) Status Affected: Z 11df ffff Description: Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Words: 1 Cycles: 1 Example: DECF Before Instruction CNT = Z = After Instruction CNT = Z = DS41213D-page 46 11df ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1'. the result is placed back in register `f'. If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 0x13 Decrement f 0000 0010 Description: REG1,0 DECF Encoding: Encoding: skip if result = 0 DECFSZ GOTO CONTINUE * * * Before Instruction PC = After Instruction CNT = if CNT = PC = if CNT PC = CNT, 1 LOOP address(HERE) CNT - 1; 0, address (CONTINUE); 0, address (HERE+1) CNT, 1 0x01 0 0x00 1 (c) 2007 Microchip Technology Inc. PIC16F5X GOTO Unconditional Branch INCFSZ Syntax: [ label ] Syntax: [ label ] Operands: 0 k 511 Operands: Operation: k PC<8:0>; STATUS<6:5> PC<10:9> 0 f 31 d [0,1] Operation: (f) + 1 (dest), skip if result = 0 None Status Affected: None Status Affected: Encoding: Description: GOTO k 101k kkkk kkkk GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a twocycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE) INCF Increment f Syntax: [ label ] Operands: 0 f 31 d [0,1] Operation: (f) + 1 (dest) Status Affected: Z Encoding: INCF f, d 0010 10df ffff Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Words: 1 Cycles: 1 Example: INCF Before Instruction CNT = Z = After Instruction CNT = Z = CNT, Encoding: Increment f, Skip if 0 0011 INCFSZ f, d 11df ffff Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. Words: 1 Cycles: 1(2) Example: HERE INCFSZ GOTO CONTINUE * * * Before Instruction PC = After Instruction CNT = if CNT = PC = if CNT PC = CNT, 1 LOOP address (HERE) CNT + 1; 0, address (CONTINUE); 0, address (HERE +1) 1 0xFF 0 0x00 1 (c) 2007 Microchip Technology Inc. DS41213D-page 47 PIC16F5X IORLW Inclusive OR literal with W MOVF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. (k) (W) 0 f 31 d [0,1] Status Affected: Z Operation: (f) (dest) Status Affected: Z Encoding: Description: 1101 IORLW k kkkk kkkk The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: IORLW 0x35 Before Instruction W = 0x9A After Instruction W = 0xBF Z = 0 Encoding: Move f 0010 MOVF f, d 00df Description: The contents of register `f' is moved to destination `d'. If `d' is `0', destination is the W register. If `d' is `1', the destination is file register `f'. `d' is `1' is useful to test a file register since Status flag Z is affected. Words: 1 Cycles: 1 Example: MOVF FSR, MOVLW Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 k 255 Operation: (W).OR. (f) (dest) k (W) Operation: Status Affected: None Status Affected: Z Encoding: Encoding: Description: 0001 00df Words: 1 Cycles: 1 Example: IORWF DS41213D-page 48 IORWF f, d ffff Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Before Instruction RESULT = W = After Instruction RESULT = W = Z = 0 After Instruction W = value in FSR register Inclusive OR W with f IORWF ffff Move Literal to W 1100 MOVLW k kkkk kkkk Description: The eight-bit literal `k' is loaded into the W register. Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A RESULT, 0 0x13 0x91 0x13 0x93 0 (c) 2007 Microchip Technology Inc. PIC16F5X MOVWF Move W to f Syntax: [ label ] Operands: 0 f 31 Operands: None Operation: (W) (f) Operation: (W) OPTION Status Affected: None Status Affected: None Encoding: 0000 MOVWF 001f f ffff Description: Move data from the W register to register `f'. Words: 1 Cycles: 1 Example: MOVWF Before Instruction TEMP_REG W After Instruction TEMP_REG W TEMP_REG = = 0xFF 0x4F = = 0x4F 0x4F OPTION Load OPTION Register Syntax: [ label ] Encoding: 0000 OPTION 0000 0010 Description: The content of the W register is loaded into the Option register. Words: 1 Cycles: 1 Example: OPTION Before Instruction W = After Instruction OPTION = 0x07 0x07 NOP No Operation RETLW Return with Literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: No operation Operation: Status Affected: None k (W); TOS PC Status Affected: None Encoding: 0000 NOP 0000 Description: No operation. Words: 1 Cycles: 1 Example: NOP 0000 Encoding: 1000 kkkk kkkk Description: The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: CALL TABLE;W contains ;table offset ;value. * ;W now has table * ;value. * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table TABLE Before Instruction W = After Instruction W = (c) 2007 Microchip Technology Inc. RETLW k 0x07 value of k8 DS41213D-page 49 PIC16F5X RLF Rotate Left f through Carry RRF Syntax: [ label ] RLF Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: 0011 f, d 01df ffff The contents of register `f' are rotated one bit to the left through the Carry Flag (STATUS<0>). If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C Encoding: Description: Rotate Right f through Carry 0011 1 Words: 1 Cycles: 1 Cycles: 1 Example: RLF Example: RRF 1110 0110 0 1110 0110 1100 1100 1 REG1,0 Before Instruction REG1 = C = After Instruction REG1 = W = C = 1110 0110 0 1110 0110 0111 0011 0 Sleep Go into Standby Mode Syntax: [ label ] Sleep Operands: None Operation: 00h WDT; 0 WDT prescaler; if assigned 1 TO; 0 PD Status Affected: TO, PD Encoding: DS41213D-page 50 ffff register 'f' C Words: Before Instruction REG1 = C = After Instruction REG1 = W = C = 00df The contents of register `f' are rotated one bit to the right through the Carry Flag (STATUS<0>). If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. register 'f' REG1,0 RRF f, d 0000 0000 0011 Description: Time-out Status bit (TO) is set. The power-down Status bit (PD) is cleared. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See section on Sleep for more details. Words: 1 Cycles: 1 Example: SLEEP (c) 2007 Microchip Technology Inc. PIC16F5X SUBWF Subtract W from f SWAPF Syntax: [ label ] SUBWF f, d Syntax: [ label ] SWAPF f, d Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) - (W) (dest) Operation: Status Affected: C, DC, Z (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) Status Affected: None Encoding: Description: 0000 10df ffff Subtract (2's complement method) the W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Encoding: Description: Swap Nibbles in f 0011 1 Cycles: 1 Words: 1 SUBWF Cycles: 1 Example: SWAPF REG1, 1 Before Instruction REG1 = 3 W = 2 C = ? After Instruction REG1 = 1 W = 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = 0xFF W = 2 C = 0 ; result is negative (c) 2007 Microchip Technology Inc. ffff The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W register. If `d' is `1', the result is placed in register `f'. Words: Example 1: 10df Before Instruction REG1 = After Instruction REG1 = W = REG1, 0 0xA5 0xA5 0x5A TRIS Load TRIS Register Syntax: [ label ] TRIS Operands: f = 5, 6, 7, 8 or 9 Operation: (W) TRIS register f Status Affected: None Encoding: Description: 0000 0000 f 0fff TRIS register `f' (f = 5, 6 or 7) is loaded with the contents of the W register. Words: 1 Cycles: 1 Example: TRIS PORTB Before Instruction W = 0xA5 After Instruction TRISB = 0xA5 DS41213D-page 51 PIC16F5X XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k (W) Status Affected: Z Encoding: 1111 kkkk kkkk Description: The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 f 31 d [0,1] Operation: (W) .XOR. (f) (dest) Status Affected: Z Encoding: Description: 0001 ffff Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Words: 1 Cycles: 1 Example: XORWF Before Instruction REG = W = After Instruction REG = W = DS41213D-page 52 10df f, d REG,1 0xAF 0xB5 0x1A 0xB5 (c) 2007 Microchip Technology Inc. PIC16F5X 10.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits 10.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2007 Microchip Technology Inc. DS41213D-page 53 PIC16F5X 10.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process 10.5 MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 10.6 10.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 10.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. MPLAB ASM30 Assembler, Linker and Librarian MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41213D-page 54 (c) 2007 Microchip Technology Inc. PIC16F5X 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 10.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). 10.9 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 10.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2007 Microchip Technology Inc. DS41213D-page 55 PIC16F5X 10.11 PICSTART Plus Development Programmer 10.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. 10.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS41213D-page 56 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits. (c) 2007 Microchip Technology Inc. PIC16F5X 11.0 ELECTRICAL SPECIFICATIONS FOR PIC16F54/57 Absolute Maximum Ratings() Ambient Temperature under bias ......................................................................................................... -40C to +125C Storage Temperature ........................................................................................................................... -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................ 0V to +6.5V Voltage on MCLR with respect to VSS(1) ................................................................................................... 0V to +13.5V Voltage on all other pins with respect to VSS ............................................................................... -0.6V to (VDD + 0.6V) Total power dissipation(2) .................................................................................................................................. 800 mW Max. current out of VSS pin ................................................................................................................................ 150 mA Max. current into VDD pin ................................................................................................................................... 100 mA Max. current into an input pin (T0CKI only)....................................................................................................... 500 A Input clamp current, IIK (VI < 0 or VI > VDD) ....................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................ 20 mA Max. output current sunk by any I/O pin .............................................................................................................. 25 mA Max. output current sourced by any I/O pin ......................................................................................................... 25 mA Max. output current sourced by a single I/O port (PORTA, B or C) ..................................................................... 50 mA Max. output current sunk by a single I/O port (PORTA, B or C)........................................................................... 50 mA Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. 2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (c) 2007 Microchip Technology Inc. DS41213D-page 57 PIC16F5X 11.0 ELECTRICAL SPECIFICATIONS FOR PIC16F59 (continued) Absolute Maximum Ratings() Ambient Temperature under bias .........................................................................................................-40C to +125C Storage Temperature............................................................................................................................-65C to +150C Voltage on VDD with respect to VSS ............................................................................................................ 0V to +6.5V Voltage on MCLR with respect to VSS(1) ................................................................................................... 0V to +13.5V Voltage on all other pins with respect to VSS................................................................................ -0.6V to (VDD + 0.6V) Total power dissipation(2) ..................................................................................................................................900 mW Max. current out of VSS pins...............................................................................................................................250 mA Max. current into VDD pins .................................................................................................................................200 mA Max. current into an input pin (T0CKI only).......................................................................................................500 A Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................20 mA Max. output current sunk by any I/O pin...............................................................................................................25 mA Max. output current sourced by any I/O pin .........................................................................................................25 mA Max. output current sourced by a single I/O port (PORTA, B, C, D or E)...........................................................100 mA Max. output current sunk by a single I/O port (PORTA, B, C, D or E)................................................................100 mA Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. 2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS41213D-page 58 (c) 2007 Microchip Technology Inc. PIC16F5X PIC16F5X VOLTAGE-FREQUENCY GRAPH, -40C TA +125C FIGURE 11-1: 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. (c) 2007 Microchip Technology Inc. DS41213D-page 59 PIC16F5X 11.1 DC Characteristics: PIC16F5X (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C for industrial Param Sym. No. Min. Typ Max. Units Characteristic/Device Conditions D001 VDD Supply Voltage 2.0 -- 5.5 V D002 VDR RAM Data Retention Voltage(1) -- 1.5* -- V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset -- Vss -- V See Section 5.1 "Power-on Reset (POR)" for details on Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset 0.05* -- -- D010 IDD -- 170 350 -- -- -- 0.4 1.7 15 1.0 5.0 22.5 -- -- 1.0 0.5 6.0 2.5 D020 IPD V/ms See Section 5.1 "Power-on Reset (POR)" for details on Power-on Reset Supply Current(2) A FOSC = 4 MHz, VDD = 2.0V, XT or RC mode(3) mA FOSC = 10 MHz, VDD = 3.0V, HS mode mA FOSC = 20 MHz, VDD = 5.0V, HS mode A FOSC = 32 kHz, VDD = 2.0V, LP mode, WDT disabled Power-down Current(2) A A VDD = 2.0V, WDT enabled VDD = 2.0V, WDT disabled * These parameters are characterized but not tested. Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature, also have an impact on the current consumption. a) The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. The Power-down Current in Sleep mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. DS41213D-page 60 (c) 2007 Microchip Technology Inc. PIC16F5X 11.2 DC Characteristics: PIC16F5X (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended DC CHARACTERISTICS Param Sym. No. D001 VDD Characteristic/Device Supply Voltage RAM Data Retention Voltage D002 VDR D003 VPOR VDD Start Voltage to ensure Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset D010 IDD D020 IPD (1) Min. Typ 2.0 -- Max. Units 5.5 Conditions V -- 1.5* -- V Device in Sleep mode -- VSS -- V See Section 5.1 "Power-on Reset (POR)" for details on Power-on Reset 0.05* -- -- -- 170 450 A -- -- -- 0.4 1.7 15 2.0 7.0 40 mA mA A -- -- 1.0 0.5 15.0 8.0 A A V/ms See Section 5.1 "Power-on Reset (POR)" for details on Power-on Reset Supply Current(2) FOSC = 4 MHz, VDD = 2.0V, XT or RC mode(3) FOSC = 10 MHz, VDD = 3.0V, HS mode FOSC = 20 MHz, VDD = 5.0V, HS mode FOSC = 32 kHz, VDD = 2.0V, LP mode, WDT disabled Power-down Current(2) VDD = 2.0V, WDT enabled VDD = 2.0V, WDT disabled * These parameters are characterized but not tested. Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature, also have an impact on the current consumption. a) The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. The Power-down Current in Sleep mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. (c) 2007 Microchip Technology Inc. DS41213D-page 61 PIC16F5X 11.3 DC Characteristics PIC16F5X DC CHARACTERISTICS Param Sym. No. VIL D030 Characteristic VIH Min. Typ Max. Units VSS VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- -- 0.8V 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD 0.3 0.3 V V V V V V V V 4.5V <VDD 5.5V VDD 4.5V -- -- -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V V V 4.5V < VDD 5.5V VDD 4.5V D060 VSS VPIN VDD, pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP modes VOL D080 D083 RC mode(3) HS mode XT mode LP mode Input Leakage Current(1, 2) I/O ports -- -- 1.0 A MCLR T0CKI OSC1 -- -- -- -- -- -- 5.0 5.0 5.0 A A A -- -- -- -- 0.6 0.6 V V IOL = 8.5 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -3.0 mA, VDD = 4.5V IOH = -1.3 mA, VDD = 4.5V Output Low Voltage I/O ports OSC2/CLKOUT (RC mode) VOH RC mode(3) HS mode XT mode LP mode Input High Voltage I/O ports 2.0 I/O ports 0.25 VDD + 0.8 0.85 VDD MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) 0.85 VDD OSC1 (Schmitt Trigger) 0.85 VDD 0.7 VDD OSC1 1.6 1.6 IIL Conditions Input Low Voltage I/O Ports I/O Ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 D040 D090 D092 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C for industrial -40C TA +125C for extended Output High Voltage(2) I/O ports(2) OSC2/CLKOUT (RC mode) * These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F5X be driven with external clock in RC mode. DS41213D-page 62 (c) 2007 Microchip Technology Inc. PIC16F5X 11.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 11-2: T Time mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer P R V Z Period Rise Valid High-impedance LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16F5X Pin Legend: CL CL = 50 pF for all pins and OSC2 for RC mode 0-15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS 11.5 Timing Diagrams and Specifications FIGURE 11-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT (c) 2007 Microchip Technology Inc. DS41213D-page 63 PIC16F5X TABLE 11-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40C TA +85C for industrial -40C TA +125C for extended Parameter No. Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period(1) Min. Typ Max. Units DC -- 4.0 MHz XT Osc mode DC -- 20 MHz HS Osc mode DC -- 200 kHz DC -- 4.0 MHz RC Osc mode 0.1 -- 4.0 MHz XT Osc mode 4.0 -- 20 MHz HS Osc mode 5.0 -- 200 kHz LP Osc mode 250 -- -- ns XT Osc mode 50 -- -- ns HS Osc mode -- -- s LP Osc mode 250 -- -- ns RC Osc mode 250 -- 10,000 ns XT Osc mode 50 -- 250 ns HS Osc mode 5.0 -- -- s LP Osc mode TCY Instruction Cycle Time(2) -- 4/FOSC -- -- 3 TosL, TosH Clock in (OSC1) Low or High Time 50* -- -- ns TosR, TosF Clock in (OSC1) Rise or Fall Time LP Osc mode 5.0 2 4 Conditions XT oscillator 20* -- -- ns HS oscillator 2.0* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 5* ns HS oscillator -- -- 50* ns LP oscillator * These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS41213D-page 64 (c) 2007 Microchip Technology Inc. PIC16F5X FIGURE 11-4: CLKOUT AND I/O TIMING - PIC16F5X Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 12 18 19 16 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: TABLE 11-2: Param No. Please refer to Figure 11-2 for load conditions. CLKOUT AND I/O TIMING REQUIREMENTS - PIC16F5X Sym. Characteristic Min. Typ Max. Units 15 30** ns 10 TosH2CKL OSC1 to CLKOUT(1) -- 11 TosH2CKH OSC1 to CLKOUT(1) -- 15 30** ns 12 TCKR CLKOUT rise time(1) -- 5.0 15** ns 13 TCKF CLKOUT fall time(1) -- 5.0 15** ns 14 TCKL2IOV CLKOUT to Port out valid(1) -- -- 40** ns CLKOUT(1) 15 TIOV2CKH Port in valid before 16 TCKH2IOI 17 TOSH2IOV OSC1 (Q1 cycle) to Port out valid(2) 18 TOSH2IOI 19 TIOV2OSH Port input valid to OSC1 (I/O in setup time) 20 TIOR 20 Port in hold after CLKOUT(1) 0.25 TCY+30* -- -- ns 0* -- -- ns -- -- 100* ns TBD -- -- ns TBD -- -- ns Port output rise time(2, 3) -- 10 25** ns TIOR Port output rise time(2, 4) -- 10 50** ns 21 TIOF Port output fall time(2, 3) -- 10 25** ns 21 TIOF Port output fall time(2, 4) -- 10 50** ns Legend: * ** Note 1: 2: 3: 4: OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD = To Be Determined. These parameters are characterized but not tested. These parameters are design targets and are not tested. No characterization data available at this time. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Please refer to Figure 11-2 for load conditions. PIC16F54/57 only. PIC16F59 only. (c) 2007 Microchip Technology Inc. DS41213D-page 65 PIC16F5X FIGURE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -- PIC16F5X VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: Please refer to Figure 11-2 for load conditions. TABLE 11-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER - PIC16F5X Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C for industrial -40C TA +125C for extended AC CHARACTERISTICS Param Sym. No. Characteristic Min. Typ Max. Units Conditions 2000* -- -- ns VDD = 5.0V 30 TMCL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (No Prescaler) 9.0* 9.0* 18* 18* 30* 40* ms VDD = 5.0V (industrial) VDD = 5.0V (extended) 32 TDRT Device Reset Timer Period 9.0* 9.0* 18* 18* 30* 40* ms VDD = 5.0V (industrial) VDD = 5.0V (extended) 34 TIOZ I/O high-impedance from MCLR Low 100* 300* 2000* ns * These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41213D-page 66 (c) 2007 Microchip Technology Inc. PIC16F5X FIGURE 11-6: TIMER0 CLOCK TIMINGS - PIC16F5X T0CKI 40 41 42 Note: Please refer to Figure 11-2 for load conditions. TABLE 11-4: TIMER0 CLOCK REQUIREMENTS - PIC16F5X Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C for industrial -40C TA +125C for extended AC CHARACTERISTICS Param No. 40 41 Sym. Min. Typ Max. Units Tt0H T0CKI High Pulse Width: No Prescaler 0.5 TCY + 20* -- -- ns With Prescaler 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Tt0L Characteristic T0CKI Low Pulse Width: No Prescaler With Prescaler 42 Tt0P T0CKI Period Conditions Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. DS41213D-page 67 PIC16F5X NOTES: DS41213D-page 68 (c) 2007 Microchip Technology Inc. PIC16F5X 12.0 PACKAGING INFORMATION 12.1 Package Marketing Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX PIC16F54 -I/P e3 YYWWNNN 0723CBA 18-Lead SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16F54 -E/SO e3 0718CDK YYWWNNN Example 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F54 -E/SS e3 0720CBP 28-Lead PDIP Example XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN >h Legend: XX...X Y YY WW NNN e3 * Note: * PIC16F57 -I/P e3 0723CBA >h Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. (c) 2007 Microchip Technology Inc. DS41213D-page 69 PIC16F5X Package Marking Information (Continued) 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead SPDIP (.300") XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN >h Example PIC16F57 -E/SO e3 0718CDK Example PIC16F57 -E/SS e3 0725CBK Example PIC16F57 -I/P e3 0717HAT >h 40-Lead PDIP (.600") XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN >h PIC16F59 -I/P e3 0712SAA >h 44-Lead TQFP M M XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F59 -04/PT e3 0711HAT DS41213D-page 70 (c) 2007 Microchip Technology Inc. PIC16F5X 18-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 18 Pitch e Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .300 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .880 .900 .920 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .014 b1 .045 .060 .070 b .014 .018 .022 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-007B (c) 2007 Microchip Technology Inc. DS41213D-page 71 PIC16F5X 18-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h h c A2 A A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 18 Pitch e Overall Height A - 1.27 BSC - Molded Package Thickness A2 2.05 - - Standoff A1 0.10 - 0.30 Overall Width E Molded Package Width E1 7.50 BSC Overall Length D 11.55 BSC 2.65 10.30 BSC Chamfer (optional) h 0.25 - 0.75 Foot Length L 0.40 - 1.27 Footprint L1 1.40 REF Foot Angle 0 - 8 Lead Thickness c 0.20 - 0.33 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5 - 15 Mold Draft Angle Bottom 5 - 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-051B DS41213D-page 72 (c) 2007 Microchip Technology Inc. PIC16F5X 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A2 A A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A - 0.65 BSC - 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 - - Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 6.90 7.20 7.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 - Foot Angle 0 4 0.25 8 Lead Width b 0.22 - 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B (c) 2007 Microchip Technology Inc. DS41213D-page 73 PIC16F5X 28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A - - .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .050 .070 b .014 .018 .022 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B DS41213D-page 74 (c) 2007 Microchip Technology Inc. PIC16F5X 28-Lead Plastic Dual In-Line (P) - 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 NOTE 1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A - - .250 Molded Package Thickness A2 .125 - .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .590 - .625 Molded Package Width E1 .485 - .580 Overall Length D 1.380 - 1.565 Tip to Seating Plane L .115 - .200 Lead Thickness c .008 - .015 b1 .030 - .070 b .014 - .022 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-079B (c) 2007 Microchip Technology Inc. DS41213D-page 75 PIC16F5X 28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h A2 A h c L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A - 1.27 BSC - Molded Package Thickness A2 2.05 - - Standoff A1 0.10 - 0.30 Overall Width E Molded Package Width E1 7.50 BSC Overall Length D 17.90 BSC 2.65 10.30 BSC Chamfer (optional) h 0.25 - 0.75 Foot Length L 0.40 - 1.27 Footprint L1 1.40 REF Foot Angle Top 0 - 8 Lead Thickness c 0.18 - 0.33 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5 - 15 Mold Draft Angle Bottom 5 - 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B DS41213D-page 76 (c) 2007 Microchip Technology Inc. PIC16F5X 28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c A2 A A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A - 0.65 BSC - 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 - - Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 9.90 10.20 10.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 - Foot Angle 0 4 0.25 8 Lead Width b 0.22 - 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-073B (c) 2007 Microchip Technology Inc. DS41213D-page 77 PIC16F5X 40-Lead Plastic Dual In-Line (P) - 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 40 Pitch e Top to Seating Plane A - - .250 Molded Package Thickness A2 .125 - .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .590 - .625 Molded Package Width E1 .485 - .580 Overall Length D 1.980 - 2.095 Tip to Seating Plane L .115 - .200 Lead Thickness c .008 - .015 b1 .030 - .070 b .014 - .023 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-016B DS41213D-page 78 (c) 2007 Microchip Technology Inc. PIC16F5X 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 A c L A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A - 0.80 BSC - Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 - 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.20 1.00 REF Foot Angle Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC 0 3.5 7 Lead Thickness c 0.09 - 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top 11 12 13 Mold Draft Angle Bottom 11 12 13 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B (c) 2007 Microchip Technology Inc. DS41213D-page 79 PIC16F5X APPENDIX A: DATA SHEET REVISION HISTORY Revision D (04/2007) Changed PICmicro to PIC; Replaced Dev. Tool Section; Updated Package Marking Information and replaced Package Drawings (Rev. AP) DS41213D-page 80 (c) 2007 Microchip Technology Inc. PIC16F5X A G Absolute Maximum Ratings PIC1654/57 ................................................................. 57 PIC1659 ...................................................................... 58 ADDWF ............................................................................... 43 ALU ....................................................................................... 7 ANDLW ............................................................................... 43 ANDWF ............................................................................... 43 Applications........................................................................... 5 Architectural Overview .......................................................... 7 Assembler MPASM Assembler..................................................... 54 GOTO ........................................................................... 19, 47 B Block Diagram On-Chip Reset Circuit ................................................. 24 PIC16F5X Series .......................................................... 8 Timer0......................................................................... 33 TMR0/WDT Prescaler................................................. 36 Watchdog Timer.......................................................... 38 Brown-Out Protection Circuit .............................................. 27 BSF ..................................................................................... 44 BTFSC ................................................................................ 44 BTFSS ................................................................................ 44 C C Compilers MPLAB C18 ................................................................ 54 MPLAB C30 ................................................................ 54 CALL ............................................................................. 19, 45 Carry (C) bit .................................................................... 7, 17 Clocking Scheme ................................................................ 12 CLRF................................................................................... 45 CLRW ................................................................................. 45 CLRWDT............................................................................. 45 Code Protection ............................................................ 37, 39 COMF ................................................................................. 46 Configuration Bits................................................................ 37 Customer Change Notification Service ............................... 83 Customer Notification Service............................................. 83 Customer Support ............................................................... 83 D DC Characteristics Commercial................................................................. 62 Extended..................................................................... 61 Industrial ............................................................... 60, 62 DECF .................................................................................. 46 DECFSZ.............................................................................. 46 Development Support ......................................................... 53 Device Reset Timer (DRT).................................................. 27 Digit Carry (DC) bit.......................................................... 7, 17 DRT..................................................................................... 27 E Electrical Specifications PIC16F54/57............................................................... 57 PIC16F59.................................................................... 58 Errata .................................................................................... 3 External Power-On Reset Circuit ........................................ 25 F FSR Register ...................................................................... 20 Value on Reset (PIC16F54)........................................ 24 Value on Reset (PIC16F57)........................................ 24 Value on Reset (PIC16F59)........................................ 24 (c) 2007 Microchip Technology Inc. H High-Performance RISC CPU .............................................. 1 I I/O Interfacing ..................................................................... 29 I/O Ports ............................................................................. 29 I/O Programming Considerations ....................................... 31 ID Locations.................................................................. 37, 39 INCF ................................................................................... 47 INCFSZ............................................................................... 47 INDF Register ..................................................................... 20 Value on Reset ........................................................... 24 Indirect Data Addressing .................................................... 20 Instruction Cycle ................................................................. 12 Instruction Flow/Pipelining .................................................. 12 Instruction Set Summary .................................................... 41 Internet Address ................................................................. 83 IORLW ................................................................................ 48 IORWF................................................................................ 48 L Loading of PC ..................................................................... 19 M MCLR Reset Register values on...................................................... 24 Memory Map PIC16F54 ................................................................... 13 PIC16F57/59 .............................................................. 13 Memory Organization ......................................................... 13 Microchip Internet Web Site................................................ 83 MOVF ................................................................................. 48 MOVLW .............................................................................. 48 MOVWF .............................................................................. 49 MPLAB ASM30 Assembler, Linker, Librarian ..................... 54 MPLAB ICD 2 In-Circuit Debugger ..................................... 55 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator...................................................... 55 MPLAB Integrated Development Environment Software.... 53 MPLAB PM3 Device Programmer ...................................... 55 MPLAB REAL ICE In-Circuit Emulator System .................. 55 MPLINK Object Linker/MPLIB Object Librarian .................. 54 N NOP .................................................................................... 49 O Option ................................................................................. 49 Option Register................................................................... 18 Value on Reset ........................................................... 24 Oscillator Configurations..................................................... 21 Oscillator Types HS............................................................................... 21 LP ............................................................................... 21 RC .............................................................................. 21 XT ............................................................................... 21 P PA0 bit ................................................................................ 17 PA1 bit ................................................................................ 17 Paging ................................................................................ 19 PC....................................................................................... 19 Value on Reset ........................................................... 24 DS41213D-page 81 PIC16F5X PD bit ............................................................................ 17, 23 PICSTART Plus Development Programmer ....................... 56 Pinout Description - PIC16F54.............................................. 9 Pinout Description - PIC16F57............................................ 10 Pinout Description - PIC16F59............................................ 11 PORTA................................................................................ 29 Value on Reset ........................................................... 24 PORTB................................................................................ 29 Value on Reset ........................................................... 24 PORTC................................................................................ 29 Value on Reset ........................................................... 24 PORTD Value on Reset ........................................................... 24 PORTE Value on Reset ........................................................... 24 Power-down Mode .............................................................. 39 Power-on Reset (POR) ....................................................... 25 Register values on ...................................................... 24 Prescaler ............................................................................. 35 Program Counter................................................................. 19 Program Memory Organization ........................................... 13 Program Verification/Code Protection................................. 39 Q Q cycles .............................................................................. 12 R RC Oscillator ....................................................................... 22 Reader Response ............................................................... 84 Read-Modify-Write .............................................................. 31 Register File Map PIC16F54 .................................................................... 14 PIC16F57 .................................................................... 14 PIC16F59 .................................................................... 15 Registers Special Function ......................................................... 16 Value on Reset ........................................................... 24 Reset................................................................................... 23 Reset on Brown-out ............................................................ 27 RETLW................................................................................ 49 RLF ..................................................................................... 50 RRF..................................................................................... 50 T Timer0 Switching Prescaler Assignment ................................ 36 Timer0 (TMR0) Module............................................... 33 TMR0 register - Value on Reset ................................. 24 TMR0 with External Clock .......................................... 35 Timing Diagrams and Specifications .................................................................................... 63 Timing Parameter Symbology and Load Conditions .................................................................................... 63 TO bit ............................................................................ 17, 23 TRIS.................................................................................... 51 TRIS Registers ................................................................... 29 Value on Reset ........................................................... 24 W W Register Value on Reset ........................................................... 24 Wake-up from Sleep ..................................................... 23, 39 Watchdog Timer (WDT)................................................ 37, 38 Period ......................................................................... 38 Programming Considerations ..................................... 38 Register Values on Reset ........................................... 24 WWW Address ................................................................... 83 WWW, On-Line Support ....................................................... 3 X XORLW............................................................................... 52 XORWF .............................................................................. 52 Z Zero (Z) bit ...................................................................... 7, 17 S Sleep ....................................................................... 37, 39, 50 Software Simulator (MPLAB SIM)....................................... 54 Special Features of the CPU............................................... 37 Special Function Registers ................................................. 16 Stack ................................................................................... 20 STATUS Register............................................................ 7, 17 Value on Reset ........................................................... 24 SUBWF ............................................................................... 51 SWAPF ............................................................................... 51 DS41213D-page 82 (c) 2007 Microchip Technology Inc. PIC16F5X THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2007 Microchip Technology Inc. DS41213D-page 83 PIC16F5X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F5X Y N Literature Number: DS41213D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41213D-page 84 (c) 2007 Microchip Technology Inc. PIC16F5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) c) Device PIC16F54 - VDD PIC16F54T(1) - VDD PIC16F57 - VDD PIC16F57T(1) - VDD range 2.0V to 5.5V range 2.0V to 5.5V range 2.0V to 5.5V range 2.0V to 5.5V Temperature Range I E = -40C to +85C = -40C to +125C Package SO SS P SP SOG SSG PG SPG = = = = = = = = Pattern d) e) PIC16F54-I/P = Industrial temp, PDIP package PIC16F54T-I/SSG = Industrial temp, SSOP package (Pb -free), tape and reel PIC16F57-E/SP6 = Extended temp, Skinny Plastic DIP package (Pb-free) PIC16F57T-E/SS = Extended temp, SSOP package, tape and reel PIC16F54-I/SOG = Industrial temp, SOIC package (Pb-free) (Industrial) (Extended) SOIC SSOP PDIP Skinny Plastic DIP (SPDIP)(2) SOIC (Pb-free) SOIC (Pb-free) SOIC (Pb-free) SOIC (Pb-free) Note 1: 2: T = in tape and reel SOIC and SSOP packages only. PIC16F57 only QTP, SQTP, Code or Special Requirements (blank otherwise) PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC16F59 - VDD range 2.0V to 5.5V PIC16F59T(1) - VDD range 2.0V to 5.5V Temperature Range I E = -40C to +85C = -40C to +125C Package P PT = = Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) PIC16F59-I/P = Industrial temp, PDIP package (Pb-free). PIC16F59T-I/PT = Industrial temp, TQFP package (Pb-free), tape and reel. (Industrial) (Extended) PDIP TQFP Note (c) 2007 Microchip Technology Inc. 1: T = in tape and reel TQFP packages only. DS41213D-page 85 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 12/08/06 DS41213D-page 86 (c) 2007 Microchip Technology Inc.