PRELIMINARY
Publicati on# 21505 Rev: CAmendment/+2
Issue Date: April 19 98
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 5.0 Volt-onl y Boot Sec tor Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 5.0 volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F400 device
■High performan c e
— Access times as fast as 55 ns
■Low power consumption (typical values at 5
MHz)
— 1 µA standby mode current
— 20 mA read current (byt e mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
sev en 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
sev en 32 Kw ord sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in prev iously locked sectors
■Top or bottom boot block configurations
available
■Embe dded Algorithms
— Embedded Erase algorithm automatically
preprogr ams and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
■Minimum 1,000,000 progr am/erase cycles per
sector guaranteed
■Package option
— 48-pin TSOP
— 44-pin SO
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
pow er-s upply Flash
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■Ready/ Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■Erase Suspend/Erase Resume
— Suspends an er ase operati on to read dat a from,
or progr am data to, a sector that is not being
erased, then res umes the erase operation
■Hardware reset pin (RESET#)
— Hardware method t o reset the device to reading
array data
2 Am29F400B
PRELIMINARY
GENERAL DESCRIPTION
The Am29F400B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 44-pin SO and 48-pin TSOP
packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) dat a appea rs on DQ7–
DQ0. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
A 12.0 V VPP is not required for write or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.35 µm
process technolog y, and off ers all the f eatures an d ben-
efits of the Am29F400, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 60, 70,
90, 120, and 150 ns, allo wing high speed microproces-
sors to operate without wait states. To eliminate bus
contention the device has separate chip enab le (CE#),
write enable (WE#) and output enable (OE#) controls.
The de vice requires only a single 5.0 volt power sup-
ply for both read and wr ite functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by obser ving the RY /BY#
pin, or by reading the DQ7 (Data# Polling) and
DQ6/DQ2 (toggle) status bits. After a program or
erase cyc le has been c ompleted, the device is ready to
read array data or accept another command.
The sector erase arch itecture all ows memory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True background eras e can thus be achie ved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitr y. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standb y mode.
Pow er c onsumption is g re atly r educe d in t his mode .
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effec tivenes s.
The device electri cally erases all bits wit hi n a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Am29F400B 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: S ee “AC Characterist ics ” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F400B
Speed Option VCC = 5.0 V ± 5% -55
VCC = 5.0 V ± 10% -60 -70 -90 -120 -150
Max access time, ns (tACC)55 60 70 90 120 150
Max CE# access time, ns (tCE)55 60 70 90 120 150
Max OE# access time, ns (tOE)30 30 30 35 50 55
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A17
21505C-1
4 Am29F400B
PRELIMINARY
CONNECTION DIAGRAMS
A1
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A1
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
21505C-2
48-Pin TSOP—Standard Pinout
48-Pin TSOP—Reverse Pinout
Am29F400B 5
PRELIMINARY
CONNECTION DIAGRAMS
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/outpu t, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = De vice ground
NC = Pin not connected internally
LOGIC SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
21505C-3
SO
21505C-4
18 16 or 8
DQ0–DQ15
(A-1)
A0–A17
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
6 Am29F400B
PRELIMINARY
ORDERING INFORMATION
Standard Pr o ducts
AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed
by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm a vailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUM BE R/ DES CR IP TIO N
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
CE-55Am29F400B T
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Co mm erc ial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sec tor
B = Bottom Sector
Valid Combinations
Am29F400BT-55,
Am29F400BB-55 E C, EI, FC, FI, SC, SI
Am29F400BT-60,
Am29F400BB-60
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
Am29F400BT-70,
Am29F400BB-70
Am29F400BT-90,
Am29F400BB-90
Am29F400BT-120,
Am29F400BB-120
Am29F400BT-150,
Am29F400BB-150
Am29F400B 7
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The regi st er is composed of l atches that store the
commands, along with the address and data infor ma-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels the y requ ire, and t he resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29F400B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 oper ate in t he b y te or word c onfigur a-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configur ation, DQ15–DQ0 are acti v e and c ontrol-
led by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configurat ion, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the pow er transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device add ress inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figur e 9 for t he t iming diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE # to V IH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more in-
for mation.
An erase oper at ion can er ase one sect or, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies . A “sector ad-
dress” consists of t he ad dress b its requ ired to uni quely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
Operation CE# OE# WE# RESET# A0–A17 DQ0–DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H H AIN DOUT DOUT High-Z
Write L H L H AIN DIN DIN High-Z
CMOS Sta ndby VCC ±
0.5 V XX V
CC ±
0.5 V X High-Z High-Z High-Z
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
(See Note) XXX V
ID AIN DIN DIN High-Z
8 Am29F400B
PRELIMINARY
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram oper ation, th e system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current co nsumption is g reat ly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.5 V.
(Note that this is a more restricted voltage range than
VIH.) The device enters the TTL standby mode when
CE# and RESET# pins are both held at VIH. The de vice
requires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is dr iven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the CMOS and TTL/NMOS-c ompatible DC Charac-
teristics tables, ICC3 represents the standby current
specification.
RESET#: Hardware Reset Pin
The RESET# pin p rovides a hard ware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS±0.5
V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is ass erted during a progr am or er ase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor R Y/BY# to determine whether
the reset operation is complete. If RESET# is ass erted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 10 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the de vice is
disabled. The output pins are plac ed in the h igh imped-
ance state.
Am29F400B 9
PRELIMINARY
Table 2. Am29F400BT Top Boot Bloc k Sector Address Table
Table 3. Am29F400BB Bottom Boot Block Sector Address Tab le
Note:
Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration” section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t ca re.
When all necessary bits ha ve been set as require d, the
programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Sector A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Ran g e (in hexade cim al )
(x8)
Address Ran g e (x16)
Address Range
SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA71110XX 32/16 70000h–77FFFh38000h–3BFFFh
SA8111100 8/4 78000h–79FFFh3C000h–3CFFFh
SA9111101 8/4 7A000h–7BFFFh3D000h–3DFFFh
SA1011111X 16/8 7C000h–7FFFFh3E000h–3FFFFh
Sector A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Ran g e (in hexade cim al )
(x8)
Address Ran g e (x16)
Address Range
SA000000X 16/8 00000h–03FFFh00000h–01FFFh
SA1000010 8/4 04000h–05FFFh02000h–02FFFh
SA2000011 8/4 06000h–07FFFh03000h–03FFFh
SA30001XX 32/16 08000h–0FFFFh04000h–07FFFh
SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh
10 Am29F400B
PRELIMINARY
Table 4. Am29F400B Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection f eature disab les both pro-
gram and erase o perations in any se ctor. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high v oltage (VID) on address pin A9 and OE#.
Details on this method are provided in a supplement,
publication nu mber 20185. Contact an AMD represent-
ative to obtain a copy of this document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sect ors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. Dur ing this mode, former ly protected
sectors can be progr ammed or er ased b y sele cting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 18 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
Description Mode CE# OE# WE#
A17
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL X 01h
Device ID:
Am29F400B
(Top Boot Block)
Word L L H XXV
ID XLXLH22h 23h
Byte L L H X 23h
Device ID:
Am29F400B
(Bottom Boot Block)
Word L L H XXV
ID XLXLH22h ABh
Byte L L H X ABh
Sector Protection V erification L L H SA X VID XLXHL X01h
(protected)
X00h
(unprotected)
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
21505C-5
Am29F400B 11
PRELIMINARY
spurious system level signals during VCC power-up and
pow er-down transitions, or from system noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
pow er-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or W E# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on po wer-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accept s an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a progr amming operation in the Erase
Suspend mode, th e system ma y once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The s ystem
must
issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” se ctio n , next.
See also “Requirements for Reading Arra y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 9 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternativ e to that shown in Table 4, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
12 Am29F400B
PRELIMINARY
number of times, without initiating another command
sequence.
A read cycle at address XX0 0h o r retriev es t he man u-
f acturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) retur ns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is un-
protected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by wr iting two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is
not
required to provide further controls or t im-
ings. The device automatically provides internally gen-
erated program pulses and ver ify the programmed cell
margin. Table 5 shows the address and data require-
ments f or the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be re initiated onc e the device has reset
to reading array data, to ensur e data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempt ing to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver, a succeeding read will show that the
data is still “0”. Only erase operations can con vert a “0”
to a “1”.
Note:
See Table 5 for program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase i s a six -bus-cycle operat ion. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by t he chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogr am prior to erase. The Embedded Erase algo-
rithm automatically preprogr ams and verifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Not e that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data , to ensure da ta integ rity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
21505C-6
Am29F400B 13
PRELIMINARY
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the “Er ase/Program Oper ations” tab les in “A C
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements f or the sector eras e command sequence.
The device does
not
require the system to preprogram
the memory prior to e rase. The Embedded Erase algo-
rithm automatically progr ams and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector er ase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence , and the nu mber of sec-
tors ma y be from one sector to a ll sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All oth er commands
are ignored. Note that a hardware reset during the
sector erase operation immediately term inates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
dev ice returns to reading arr a y dat a and addr esses are
no longer latched. The system can determine the sta-
tus of the e rase operat ion b y using DQ7, DQ6, DQ2, or
R Y/BY#. ( Refer to “Write Ope ration St atus” f or inf orma-
tion on these status bits.)
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the “ E ra se/Progr am Oper at ions” tab les in
the “AC Characteris tics” section for paramet ers , and to
Figure 14 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend co mmand allo ws the s yste m to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspe nd command during the
Sector Erase time-out immediately terminates the
time-out period an d sus pends t he er ase oper at ion. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during
a sector erase operation, the dev ice requires a maxi-
mum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately te rminates the time-out period and suspend s the
erase operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not select ed for er asure . (The devic e “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
14 Am29F400B
PRELIMINARY
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase oper ation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
21505C-7
Am29F400B 15
PRELIMINARY
Table 5. Am29F400B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read op eration.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
5. Address bits A17–A11 are don’t cares for unlock and
command cycles, unless PA or SA required.
6. No unlock or command cycles required when read ing array
data.
7. The Reset command is requ ired to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Sus pend command is valid on ly during a
sector erase operation.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Top Boot Block Word 4555 AA 2AA 55 555 90 X01 2223
Byte AAA 555 AAA X02 23
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 22AB
Byte AAA 555 AAA X02 AB
Sector Protect Verify
(Note 9)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Sus pend (Note 10) 1 XXX B0
Erase Resume (Note 11) 1 XXX 30
Cycles
Autoselect (Note 8)
16 Am29F400B
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and R Y/BY# . Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# P oll ing bit, DQ7, indi cates to the host sys-
tem whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of
the final WE# pulse in the program or erase com-
mand sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is activ e f or ap-
proximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous t o the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for appro ximately 100 µs , the n the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
following
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 15, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
21505C-8
Figure 4. Data# Polling Algorithm
Am29F400B 17
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open- drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Tab le 6 sho ws the output s f or RY/BY#. Figures 10, Fig-
ure 13 and Figure 14 shows RY/BY# for reset, pro-
gram, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or er ase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle . The system ma y use either OE# or CE#
to control the read cycles. When the operation is com-
plete, DQ6 stops toggling.
After an er ase command sequence is written, if all sec-
tors selected f or er asing are protected , DQ6 toggles f or
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Tab le 6 sho ws the out puts for Toggle Bit I on DQ6. Fig-
ure 5 shows the toggle bit algorithm. Figure 16 in the
“AC Char acteristics” section sho ws the t oggle bit timing
diagrams. Figure 17 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for eras-
ure. (The s ystem ma y use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot dis-
tinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode infor-
mation. Refer to Table 6 to compare outputs for DQ2
and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form , and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Figure 16 shows the toggle bit timing diagram. Figure
17 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store th e v alue of the t oggle bit
after the first read. After the second read, the system
would compare the new value of t he toggle bit with the
first. I f the toggle bit is not t oggling, the de vice has com-
pleted the prog ram or er ase operation. The system can
read array data on DQ7–DQ0 on the following read cy-
cle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading
array data.
18 Am29F400B
PRELIMINARY
The remaining scenario is that the system initially de-
termines that the toggle bit is togglin g and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successiv e read cycles , de-
termining the stat us as described in the previous par a-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it re turns to determine
the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system ma y re ad DQ3 to dete rmine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selec ted f or er asure , the e ntire t ime-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
s witch es f ro m “0 ” to “1 .” I f t he time be tw een a dditi onal
sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not
monitor DQ3. See also the “Sector Erase Command
Sequence” section.
After the sector erase command sequence is written,
the system should rea d th e stat us on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence , and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other tha n Er ase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the s ystem softw are should chec k the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the output s for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
21505C-9
Figure 5. Toggle Bit Algorith m
(Notes
1, 2)
(Note 1)
Am29F400B 19
PRELIMINARY
Table 6. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Operation DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
20 Am29F400B
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input o r I/O p ins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input v oltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may ov ershoot to +13.5 V for periods
up to 20 ns.
3. No more tha n one outpu t may be sh or ted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresse s above those liste d under “Absolut e Maximum Rat-
ings” may cause p erman ent dam age to th e device . This is a
stress rati ng on ly; fu nct iona l ope rat ion of the de vic e at the se
or any other conditions above those indicated in the opera-
tional s ections o f this dat a sheet is not im plied. Exp osure of
the device to absolute maximum rating conditions for extend-
ed periods may affect device reliability.
Figure 6. M aximum Negative Overshoot
Waveform
Figure 7. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V
VCC for ± 10% device s. . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
21505C-10
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
21505C-11
Am29F400B 21
PRELIMINARY
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.
Parameter Descript ion Test Condition s Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET# Input Load
Current VCC = VCC max;
A9, OE#, RESET# = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Note 1)
CE# = VIL, OE# = VIH, VCC = VCC max,
f
= 5 MHz, Byte Mode 19 40 mA
CE# = VIL, OE# = VIH, VCC = VCC max,
f
= 5 MHz, Word Mode 19 50 mA
ICC2 VCC Active Write Current
(Notes 2, 3) CE# = VIL, OE# = VIH, VCC = VCC max 36 60 mA
ICC3 VCC Standby Current CE#, RESET#, and OE# = VIH,
VCC = VCC max 0.4 1 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC
+0.5 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
VLKO Low VCC Lock-Out Volta ge 3.2 4.2 V
22 Am29F400B
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.
4. ICC3 = 20 µA max at extended temperature (>+85
°
C).
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET#
Input Load Current VCC = VCC max;
A9, OE#, RESET# = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Note 1)
CE# = VIL, OE# = VIH,
VCC = VCC max,
f
= 5 MHz, Byte Mode 20 40 mA
CE# = VIL, OE# = VIH,
VCC = VCC max,
f
= 5 MHz, Word Mode 28 50
ICC2 VCC Active Write Current
(Notes 2, 3) CE# = VIL, OE# = VIH,
VCC = VCC max 30 50 mA
ICC3 VCC Standby Current (Note 4) OE# = VIH, CE# and RESET# = VCC±0.5 V,
VCC = VCC max 0.3 5 µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x
VCC
VCC+
0.3 V
VID Voltage for Autoselect and
Temporary Sector Unpro tec t VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC min 0.85
VCC V
VOH2 IOH = –100 µA, VCC = VCC min VCC–
0.4
VLKO Low VCC Lock-Out Voltage 3.2 4.2 V
Am29F400B 23
PRELIMINARY
TEST CONDITIONS
Table 7. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
21505C-12
Figure 8. Test Setup
Note:
Diodes are IN3064 or equivalent.
Test Condition -55 All
others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels 1.5 0.8, 2.0 V
Output timing measurement
reference levels 1.5 0.8, 2.0 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
24 Am29F400B
PRELIMINARY
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
Parameter
Description
Speed Opt ion
JEDEC Std Test Setup -55 -60 -70 -90 -120 -150 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 55 60 70 90 120 150 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max55607090120150ns
t
ELQV tCE Chip Enable to Output Delay OE# = VIL Max55607090120150ns
t
GLQV tOE Output Enable to Output Delay Max 30 30 30 35 50 55 ns
tEHQZ tDF Chip Enable to Output High Z
(Note 1) Max152020203035ns
t
GHQZ tDF Output Enable to Output High Z
(Note 1) Max152020203035ns
t
OEH
Output Enable
Hold Time
(Note 1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tAXQX tOH
Output Hold Time From
Addresses, CE# or OE#,
Whichev er Occurs First (Note 1) Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
21505C-13
Figure 9. Read Operations Timings
Am29F400B 25
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note:
Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
21505C-14
Figure 10. RESET# Timings
26 Am29F400B
PRELIMINARY
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
-55 -60 -70 -90 -120 -150JEDEC Std. Description Unit
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 15 20 20 20 30 35 ns
tFHQV BYTE# Switching High to Output Active Min 55 60 70 90 120 150 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
tELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
tELFH
DQ0–DQ14 Data Outpu t
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFHQV
BYTE#
Switching
from byte
to word
mode
21505C-15
Figure 11. BYTE# Timings for Read Operations
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
21505C-16
Figure 12. BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
Am29F400B 27
PRELIMINARY
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
-55 -60 -70 -90 -120 -150JEDEC Std. Description Unit
tAVAV tWC Write Cycle Time (Note 1) Min 55 60 70 90 120 150 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 45 45 50 50 ns
tDVWH tDS Data Setup Time Min 25 30 30 45 50 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 30 35 35 45 50 50 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Programming Operation
(Note 2) Byte Typ 7 µs
Word Typ 12
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY#
Delay Min 30 30 30 35 50 55 ns
28 Am29F400B
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tGHWL
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
tRB
tBUSY
tCH
PA
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
21505C-17
Figure 13. Program Operati on Timi ng s
Am29F400B 29
PRELIMINARY
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tGHWL
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
21505C-18
Figure 14. Chip/Sector Erase Operation Timings
30 Am29F400B
PRELIMINARY
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note:
V A = V alid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21505C-19
Figure 15. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note:
V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21505C-20
Figure 16. Toggle Bit Timings (During Embedded Algorithms)
Am29F400B 31
PRELIMINARY
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std. Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
Note:
The syste m may use either CE# or OE# to tog gle DQ2 and DQ6. DQ2 tog gl es onl y wh en re ad at an addr es s wit hi n an
erase -s usp end ed se ct or.
21505C-21
Figure 17. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Pro gra m
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 5 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
0 or 5 V
21505C-22
Figure 18. Temporary Sector Unprotect Timing Diagram
32 Am29F400B
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
-55 -60 -70 -90 -120 -150JEDEC Std. Description Unit
tAVAV tWC Write Cycle Time (Note 1) Min 55 60 70 90 120 150 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 45 45 50 50 ns
tDVEH tDS Data Setup Time Min 25 30 30 45 50 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Outp ut En able Setup Tim e Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 30 35 35 45 50 50 ns
tEHEL tCPH CE# Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Programming Operation
(Note 2) Byte Typ 7 µs
Word Typ 12
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
Am29F400B 33
PRELIMINARY
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
21505C-23
Figure 19. Alternate CE# Controlled Write Operation Timings
34 Am29F400B
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -60), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 1.0 8 s Excludes 00h programming
prior to erasure
Chip Erase Time 11 s
Byte Programming Time 7 300 µs
Excludes system level
overhead (Note 5)
Word Programming Time 12 500 µs
Chip Programming Time
(Note 3)
Byte Mode 3.6 10.8 s
Word Mode 3.1 9.3 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE #, and RESE T#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
Am29F400B 35
PRELIMINARY
PH YS ICAL DIMENSIONS
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)
TSR048
48-Pin Reverse Thin Small Outline Package (measured in millimeters)
48
25
1
24
18.30
18.50
19.80
20.20
11.90
12.10
0.05
0.15
0.50 BSC
0.95
1.05
16-038-TS48-2
TS 048
DT95
8-8-96 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0.25MM (0.0098") BSC 0°
5°
0.08
0.20
48
25
1
24
18.30
18.50
19.80
20.20
11.90
12.10
SEATING PLANE
0.05
0.15
0.50 BSC
0.95
1.05
16-038-TS48
TSR048
DT95
8-8-96 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0.25MM (0.0098") BSC 0°
5°
0.08
0.20
Am29F400B 37
PRELIMINARY
REVISION SUMMARY
Revision B
Global
Added -55 and -60 speed options, deleted -65 speed
option. Changed data s heet designation f rom Advance
Information to Preliminary.
Connection Diagrams
Corrected pinouts on all pac kages: deleted A18.
Table 1, Device Bus Operations
Revised to indicate inputs for both CE# and RESET#
are required for standby mode.
Sector Protecti on/Unprotection
Corrected text to indicate that these functions can only
be implemented using programming equipment.
Program Command Sequence
Changed to indicate Data# Polling is active for 2 µs
after a program command sequence if the sector spec-
ified is protected.
Sector Erase Command Sequence and DQ3: Sector
Erase Timer
Corrected sector erase timeout to 50 µs.
Erase Suspend Command
Changed to indicate that the device suspends the
erase operation a maximum of 20 µs after the rising
edge of WE#.
DC Characteristics
Changed to indicate VID min and max values are 11.5
to 12.5 V, with a VCC test condition of 5.0 V. Revised ILIT
to 50 µA. Added ICC4 specification. Added typical
values to TTL/NMOS table. Revised CMOS typical
standb y c urrent (ICC3).
Figure 14: Chip/Sector Erase Operation Timings;
Figure 19: Alternate CE# Controlled Write
Opera tion TIming s
Corrected hexadecimal values in address and data
waveforms.
AC Characteristics, Erase/Program Operations
Corrected tAH specification for -90 speed option to 45
ns.
Erase and Programming Performa nce
Corrected word and chip programmi ng times .
Revision C
Global
For matted for consistency with other 5.0 volt-only data
sheets.
AC Characteristics
Changed tDF and TFLQZ to 15 ns for -55 speed option.
Revision C+1
Table 2, Top Boot Block Sector Address Table
Corrected the sector size for SA10 to 16 Kbytes/8
Kwords.
DC Characteristics—TTL/NMOS Compatible
Deleted Note 4.
Revision C+2
Distinctive Characteri stics
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
AC Characteristics
Word/Byte Configuration:
Changed tFHQV specification
for 55 ns device.
Erase/Program Operations:
Changed tWHWH1 word
mode specification to 12 µs. Corrected the notes refer-
ence for tWHWH1 and tWHWH2. These parameters are
100% tested. Corrected the note reference for tVCS.
This parameter is not 100% tested.
Changed tDS and tCP specifications for 55 ns devi ce.
Alternate CE# Controlled Erase/Program Operations:
Changed tWHWH1 word mode specification to 12 µs.
Corrected the not es ref erence for tWHWH1 and tWHWH2.
These parameters are 100% tested.
Changed tDS and tCP specifications for 55 ns devi ce.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Erase and Programming Performance
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
