N/C
N/C
TRIP
EN
PGOOD
N/C
VBST
N/C
LL
LL
LL
LL
LL
LL
LL
LL
VFB
RF
MODE
VDD
TPS53315
GND1
PGND
VREG
GND2
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
LL
LL
LL
LL
LL
VIN
VIN
VIN
1 2 3 4 5 6 7 8 9 10 11 12
20
19
18
17
16
15
14
13
32 31 30 29 28 27 26 25 24 23 22 21
33
34
35
36
37
38
39
40
EN
VOUT
VIN
3 V to 15 V
UDG-10199
VDD
4.5 V to 25 V
PGOODVREG
TPS53315
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SLUSAE6 –DECEMBER 2010
12-A Step-Down Regulator with Integrated Switcher
Check for Samples: TPS53315
1FEATURES APPLICATIONS
• Server and Desktop Computers
2• Conversion Input Voltage Range: 3 V to 15 V • Notebook Computers
• VDD Input Voltage Range: 4.5 V to 25 V • Telecommunication Equipments
• Output Voltage Range: 0.6 V to 5.5 V
• 5-V LDO Output DESCRIPTION
• Integrated Power MOSFETs with 12-A TPS53315 is a D-CAP™ mode, 12-A synchronous
Continuous Output Current switcher with integrated MOSFETs. It is designed for
• <10-mA Shut Down Current ease of use, low external component count, and
• Auto-Skip Eco-mode™ for Light-Load small package power systems.
Efficiency This device features single-rail input support, one
• D-CAP™ Mode with Fast Transient Response 19-mΩand one 7-mΩintegrated MOSFET, accurate
1%, 0.6 V Reference, and integrated boost switch. A
• Selectable Switching Frequency from 250 kHz sample of competitive features include: greater than
to 1 MHz with an External Resistor 96% maximum efficiency, 3 V to 15 V wide input
• Built-in 1%, 0.6-V Reference voltage range, very low external component count,
• 0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable D-CAP™ mode control for super fast transient,
Internal Voltage Servo Soft-Start selectable auto-skip and PWM operation, internal
soft-start control, adjustable frequency, and no need
• Pre-Charged Start-up Capability for compensation.
• Integrated Boost Switch The conversion input voltage ranges from 3 V to
• Adjustable Overcurrent Limit Via External 15 V, the supply voltage range is from 4.5 V to 25 V,
Resistor and the output voltage range is from 0.6 V to 5.5 V.
• Overvoltage/Undervoltage, UVLO and The TPS53315 is available in a 5 mm × 7 mm 40-pin,
Over-Temperature Protection QFN package and is specified from –40°C to 85°C.
• Support All Ceramic Output Capacitors
• Open Drain Power Good Indication
• 40-pin QFN Package with PowerPAD™
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Eco-mode, D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
ORDERING TRANSPORT MINIMUM
TAPACKAGE PINS ECO PLAN
NUMBER MEDIA QUANTITY
TPS53315RGFR 40 Tape and reel 3000
Plastic QFN Green (RoHS and
–40°C to 85°C (RGF) no Pb/Br)
TPS53315RGFT 40 Mini reel 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
VIN (main supply) –0.3 to 17
VDD –0.3 to 28
Input voltage range VBST –0.3 to 24 V
VBST(with respect to LL) –0.3 to 7
EN, TRIP, VFB, RF, MODE –0.3 to 7
DC –1 to 23
LL Pulse < 20 ns, E = 5 mJ –7
Output voltage range V
PGOOD, VREG –0.3 to 7
PGND –0.3 to 0.3
Source/Sink Current VBST 50 mA
Operating free-air temperature, TA–40 to 85 °C
Storage temperature range, Tstg –55 to 150 °C
Junction temperature range, TJ–40 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION TPS53315
THERMAL METRIC(1) UNITS
RGF(40 PINS)
qJA Junction-to-ambient thermal resistance 35.8
qJCtop Junction-to-case (top) thermal resistance 23.8
qJB Junction-to-board thermal resistance 10.1 °C/W
yJT Junction-to-top characterization parameter 0.4
yJB Junction-to-board characterization parameter 10.0
qJCbot Junction-to-case (bottom) thermal resistance 2.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLUSAE6 –DECEMBER 2010
RECOMMENDED OPERATING CONDITIONS VALUE UNIT
VIN (main supply) 3 to 15
VDD 4.5 to 25
Input voltage range VBST 4.5 to 21 V
VBST(with respect to LL) 4.5 to 6.5
EN, TRIP, VFB, RF, MODE –0.1 to 6.5
LL –0.8 to 15
Output voltage range V
PGOOD, VREG –0.1 to 6.5
Source/Sink Current VBST 50 mA
Junction temperature range, TJ–40 to 125 °C
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ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VDD = 12 V (Unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND SUPPLY CURRENT
VIN pin power conversion input
VVIN 3 15 V
voltage
VDD Supply input voltage 4.5 25 V
IVIN(leak) VIN pin leakage current VEN = 0 V 1 µA
VDD current, TA= 25°C, No Load, VEN = 5 V,
IVDD VDD supply current 420 590 µA
VVFB = 0.630 V
IVDDSDN VDD shutdown current VDD current, TA= 25°C, No Load, VEN = 0 V 10 µA
INTERNAL REFERENCE VOLTAGE
VFB voltage, CCM condition(1) 0.6000 V
TA= 25°C 0.597 0.600 0.603
VVFB VFB regulation voltage TA= 0°C to 85°C 0.5952 0.600 0.6048 V
TA= -40°C to 85°C 0.594 0.600 0.606
IVFB VFB input current VVFB = 0.630 V, TA= 25°C 0.002 0.2 µA
LDO OUTPUT
VVREG LDO output voltage 0 mA ≤IVREG ≤30 mA 4.77 5.0 5.35 V
IVREG LDO output current(1) Maximum current allowed from LDO 30 mA
VDO LDO drop out voltage VDD = 4.5 V, IVREG = 30 mA 295 mV
BOOT STRAP SWITCH
VFBST Forward voltage VVREG-VBST, IF= 10 mA, TA= 25°C 0.1 0.2 V
IVBSTLK VBST leakage current VVBST = 23 V, VLL = 17 V, TA= 25°C 0.01 1.5 µA
DUTY AND FREQUENCY CONTROL
tOFF(min) Minimum off time TA= 25°C 150 260 400 ns
VVIN = 17 V, VOUT = 0.6 V, RRF = 0 Ωto VREG,
tON(min) Minimum on time 35
TA= 25°C(1)
SOFTSTART
RMODE = 39 kΩ0.7
RMODE = 100 kΩ1.4
Internal SS time from VOUT = 0 to
tSS ms
VOUT = 95% RMODE = 200 kΩ2.8
RMODE = 470 kΩ5.6
POWERGOOD
PG in from lower 92.5% 96% 98.5%
VTHPG PG threshold PG in from higher 107.5% 110% 112.5%
PG hysteresis 2.5% 5% 7.8%
RPG PG transistor on-resistance 15 30 55 Ω
tPGDEL PG Delay after soft-start 0.8 1 1.2 ms
(1) Ensured by design. Not production tested.
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SLUSAE6 –DECEMBER 2010
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VDD = 12 V (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC THRESHOLD AND SETTING CONDITIONS
Enable 1.8 V
VEN EN voltage threshold Disable 0.6
IEN EN input current VEN = 5 V 1.0 µA
RRF = 0 Ωto GND, TA= 25°C(1) 200 250 300
RRF = 187 kΩto GND, TA= 25°C(1) 250 300 350
RRF = 619 kΩto GND, TA= 25°C(1) 350 400 450
RRF = Open, TA= 25°C(1) 450 500 550
fSW Switching frequency kHz
RRF = 866 kΩto VREG, TA= 25°C(1) 580 650 720
RRF = 309 kΩto VREG, TA= 25°C(1) 670 750 820
RRF = 124 kΩto VREG, TA= 25°C(1) 770 850 930
RRF = 0 Ωto VREG, TA= 25°C(1) 880 970 1070
PROTECTION: CURRENT SENSE
ITRIP TRIP source current VTRIP = 1 V, TA= 25°C 9.4 10.0 10.6 µA
TCITRIP TRIP current temperature coefficent On the basis of 25°C(2) 4700 ppm/°C
VTRIP Current limit threshold setting range VTRIP-GND voltage 0.2 1.2 V
VTRIP = 1.2 V 140 150 160
VOCL Current limit threshold VTRIP = 0.2 19 26 33 mV
VTRIP = 1.2 V –160 –150 –140
VOCLN Negative current limit threshold VTRIP = 0.2 V –33 –26 –19
Positive 3 15
VAZCADJ Auto zero cross adjustable range mV
Negative –15 –3
PROTECTION: UVP and OVP
VOVP OVP trip threshold OVP detect 115% 120% 125%
tOVPDEL OVP propagation delay time VFB delay with 50-mV overdrive 1 µs
VUVP Output UVP trip threshold time UVP detect 65% 70% 75%
tUVPDEL Output UVP propagation delay time 0.8 1 1.2 ms
tUVPEN Output UVP enable delay time from EN to UVP workable, RMODE = 39 kΩ2.0 2.6 3.2 ms
UVLO
Wake up 4.00 4.20 4.32
VUVVREG VREG UVLO threshold V
Hysteresis 0.25
THERMAL SHUTDOWN
Shutdown temperature(2) 145
TSDN Thermal shutdown threshold °C
Hysteresis(2) 10
(1) Not production tested. Test condition is VIN = 12 V, VOUT= 1.1 V, IOUT= 5 A using application circuit shown in Figure 33.
(2) Ensured by design. Not production tested.
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N/C
N/C
TRIP
EN
PGOOD
N\C
VBST
N/C
32 31 30 29 28 27 26 25 24 23 22 21
LL
LL
LL
LL
LL
LL
LL
LL
33
34
35
36
37
38
39
40
VFB
RF
MODE
VDD
1 2 3 4 5 6 7 8 9 10 11 12
20
19
18
17
16
15
14
13
TPS53315RGF
GND1
PGND
VREG
GND2
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
LL
LL
LL
LL
LL
VIN
VIN
VIN
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
PIN DESCRIPTION
PIN FUNCTIONS
PIN I/O/P(1) DESCRIPTION
NAME NO.
EN 36 I Enable pin.
GND1 1 G GND for controller
GND2 4 G GND for half-bridge
16
17
18
19
20
21
LL 22 B Output of converted power. Connect this pin to the output Inductor.
23
24
25
26
27
28 Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The soft-start
MODE 39 I time is detected and stored into internal register during start-up.
29
31
N/C No connection
33
34
(1) I=Input, O=Output, B=Bidirectional, P=Supply, G=Ground
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SLUSAE6 –DECEMBER 2010
PIN FUNCTIONS (continued)
PIN I/O/P(1) DESCRIPTION
NAME NO.
Open drain power good flag. Provides a 1-ms start up delay after the VFB pin voltage falls within
PGOOD 32 O specified limits. When the VFB pin voltage goes outside the specified limits, the PGOOD pin goes low
within 10 µs.
2
5
6
PGND 7 G Power GND
8
9
10 Switching frequency selection. Connect a resistance to GND or VREG to select switching frequency using
RF 38 I Table 2. The switching frequency is detected and stored during the startup.
OCL detection threshold setting pin. 10 µA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
TRIP 35 I space VOCL = VTRIP/8 ( VTRIP ≤1.2 V, VOCL ≤150 mV)
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL-node.
VBST 30 P Internally connected to the VREG pin via bootstrap MOSFET switch.
VDD 40 P Controller power supply input.
VFB 37 I Output feedback input. Connect this pin to VOUT through a resistor divider.
11
12
VIN 13 P Conversion power input.
14
15
VREG 3 P 5-V LDO output.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
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Sdn VREG
V5OK
LL
TPS53315
tON
One-
Shot
Control
Logic
+
+OCP
ZC
GND
LL
XCON
PGND
+
1.2 V/0.95 V
EN
UVP/OVP
Logic
+
THOK 145°C/135°C
+
4.2 V/3.95 V
VIN
VBST
Fault
VOUT
LL
PGND
RF
+
+
PWM
+OV
+20%
UV
+
0.6 V –30% Delay
SS
0.6 V
VFB
TRIP
Enable
+
+
Delay
0.6 V +10/15%
0.6 V –10/15%
PGOOD
Control Logic
On/Off time
Minimum On/Off
Light load
OVP/UVP
FCCM/Skip
UDG-10200
10 mA
VREG
+
SS
FCCM/
Skip
Decode
MODE
LDO VDD
EN
Ramp
Compensation
+
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
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0
100
200
300
400
500
600
700
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
VDD Supply Current (µA)
VEN = 5 V
VVDD = 12 V
VVFB = 0.63 V
No Load
0
1
2
3
4
5
6
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
VDD Shutdown Current (µA)
VEN = 0 V
VVDD = 12 V
No Load
0
20
40
60
80
100
120
140
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
OVP/UVP Trip Threshold (%)
OVP
UVP
6
7
8
9
10
11
12
13
14
15
16
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
TRIP Pin Current (µA)
VVDD = 12 V
1
10
100
1000
0.01 0.1 1 10 100
Output Current (µA)
Switching Frequency (kHz)
FCCM
Skip Mode
fSET = 300 kHz
VIN = 12 V
VOUT = 1.1 V
1
10
100
1000
0.01 0.1 1 10 100
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
fSET = 500 kHz
VIN = 12 V
VOUT = 1.1 V
TPS53315
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SLUSAE6 –DECEMBER 2010
TYPICAL CHARACTERISTICS
Figure 1. VDD Supply Current vs. Temperature Figure 2. VDD Shutdown Current vs. Temperature
Figure 3. OVP/UVP Trip Threshold vs. Temperature Figure 4. Trip Pin Current vs. Temperature
Figure 5. Frequency vs. Temperature (fSET = 300 kHz) Figure 6. Frequency vs. Temperature (fSET = 500 kHz)
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1
10
100
1000
0.01 0.1 1 10 100
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
fSET = 750 kHz
VIN = 12 V
VOUT = 1.1 V
1
10
100
1000
0.01 0.1 1 10 100
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
fSET = 1 MHz
VIN = 12 V
VOUT = 1.1 V
−200
0
200
400
600
800
1000
1200
0 1 2 3 4 5 6
Output Voltage (V)
Switching Frequency (kHz)
fSW = 300 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1 MHz IOUT =10 A
VIN = 12 V
1.080
1.085
1.090
1.095
1.100
1.105
1.110
1.115
1.120
0 2 4 6 8 10 12
Output Current (A)
Output Voltage (V)
Skip Mode
FCCM
1.090
1.092
1.094
1.096
1.098
1.100
1.102
1.104
1.106
1.108
1.110
5 6 7 8 9 10 11 12 13 14 15
Input Voltage (V)
Output Voltage (V)
FCCM, No Load
Skip Mode, No Load
FCCM and Skip Mode, IOUT = 10 A
fSW = 500 kHz
VIN = 12 V
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100
Output Current (A)
Efficiency (%)
Skip Mode, fSW = 500 kHz
FCCM, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCCM, fSW = 300 kHz
VIN = 12 V
VOUT = 1.1 V
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
Inductor Values
IN06155: 1 µH, 2.3 mΩ, HCB1175-501: 0.5 µH, 0.29 mΩ
Figure 7. Frequency vs. Temperature (fSET = 750 kHz) Figure 8. Frequency vs. Temperature (fSET = 1 MHz)
Figure 9. Switching Frequency vs. Output Voltage Figure 10. Output Voltage vs. Output Current
Figure 11. Output Voltage vs. Input Voltage Figure 12. Efficiency vs. Output Current, Inductor: IN06155
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78
90
94
74
70
82
86
0
Efficiency (%)
98
2 4 6 8 10 12
Output Current (A)
VIN = 12 V
FCCM
fSW = 300 kHz
1.0
1.1
1.2
1.5
1.8
3.3
5.0
VOUT (V)
78
90
94
74
70
82
86
0
Efficiency (%)
98
2 4 6 8 10 12
Output Current (A)
VIN = 12 V
Skip Mode
fSW = 300 kHz
1.0
1.1
1.2
1.5
1.8
3.3
5.0
VOUT (V)
78
90
94
74
70
82
86
0
Efficiency (%)
98
2 4 6 8 10 12
Output Current (A)
1.0
1.1
1.2
1.5
1.8
3.3
5.0
VOUT (V)
VIN = 12 V
FCCM
fSW = 500 kHz
78
90
94
74
70
82
86
0
Efficiency (%)
98
2 4 6 8 10 12
Output Current (A)
VOUT (V)
1.0
1.1
1.2
1.5
1.8
3.3
5.0
VIN = 12 V
Skip Mode
fSW = 500 kHz
78
90
94
74
70
82
86
0
Efficiency (%)
98
2 4 6 8 10 12
Output Current (A)
VIN = 5 V
FCCM
fSW = 500 kHz
VOUT (V)
1.0
1.1
1.2
1.5
1.8
3.3
78
90
94
74
70
82
86
0
Efficiency (%)
98
2 4 6 8 10 12
Output Current (A)
VIN = 5 V
Skip Mode
fSW = 500 kHz
VOUT (V)
1.0
1.1
1.2
1.5
1.8
3.3
TPS53315
www.ti.com
SLUSAE6 –DECEMBER 2010
TYPICAL CHARACTERISTICS
Inductor Values
IN06155: 1 µH, 2.3 mΩ, HCB1175-501: 0.5 µH, 0.29 mΩ
Figure 13. Efficiency vs Output Current, Figure 14. Efficiency vs Output Current,
Inductors: VOUT ≤1.8 V: HCB1175-501, VOUT ≥3.3 V: Inductors: VOUT ≤1.8 V: HCB1175-501, VOUT ≥3.3 V:
IN06155 IN06155
Figure 15. Efficiency vs Output Current, Figure 16. Efficiency vs Output Current,
Inductors: VOUT ≤1.8 V: HCB1175-501, VOUT ≥3.3 V: Inductors: VOUT ≤1.8 V: HCB1175-501, VOUT ≥3.3 V:
IN06155 IN06155
Figure 17. Efficiency vs Output Current, Figure 18. Efficiency vs Output Current,
Inductor: HCB1175-501 Inductor: HCB1175-501
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Time (1 ms/div)
FCCM
VIN = 12 V
IOUT= 10 A
EN (5 V/div)
VOUT (0.5 V/div)
VREG (5 V/div)
PGOOD (5 V/div)
Time (1 ms/div)
FCCM
VIN = 12 V
IOUT= 0 A
EN (5 V/div)
VOUT (0.5 V/div)
VREG (5 V/div)
PGOOD (5 V/div)
0.5 V pre-biased
EN (5 V/div)
VOUT (0.5 V/div)
VREG (5 V/div)
PGOOD (5 V/div)
FCCM
VIN = 12 V
IOUT= 10 A
Time (4 ms/div)
VIN (5 V/div)
VOUT (0.5 V/div)
VREG (5 V/div)
PGOOD (5 V/div)
FCCM
VEN = 5 V
IOUT= 10 A
VDD = VIN
Time (2 ms/div)
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
Figure 19. Start-Up Figure 20. Pre-Bias Start-Up
Figure 21. Turn-Off Figure 22. UVLO Start-Up
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FCCM
VIN = 12 V
IOUT = 0 A
LL (5 V/div)
VOUT (20 mV/div)
IL(2 A/div)
Time (2 µs/div)
Skip Mode
VIN = 12 V
IOUT= 0 A
Time (1 µs/div)
VOUT (20 mV/div)
IL(2 A/div)
LL (5 V/div)
Time (100 µs/div)
Skip Mode
VIN = 12 V
VOUT = 1.1 V
LL (5 V/div)
VOUT (20 mV/div)
IL(2 A/div)
Time (100 µs/div)
Skip Mode
VIN = 12 V
VOUT = 1.1 V LL (5 V/div)
VOUT (20 mV/div)
IL(2 A/div)
TPS53315
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SLUSAE6 –DECEMBER 2010
TYPICAL CHARACTERISTICS
Figure 23. 1.1-V Output FCCM Steady-State Operation Figure 24. 1.1-V Output Skip Mode Steady-State Operation
Figure 25. CCM to DCM Transition Figure 26. DCM to CCM Transition
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FCCM
VIN = 12 V
VOUT = 1.1 V
IOUT from 0 A to 5 A, 2.5A/µs
Time (2 µs/div)
VOUT (20 mV/div)
IOUT (5 A/div)
Skip Mode
VIN = 12 V
VOUT = 1.1 V
IOUT from 0 A to 5 A, 2.5A/µs
Time (100 µs/div)
VOUT (20 mV/div)
IOUT (5 A/div)
VIN = 12 V
IOUT from 10 A to 15 A
Time (10 ms/div)
VOUT (1 V/div)
IL(10 A/div)
LL (10 V/div)
PGOOD (5 V/div)
VIN = 12 V
IOUT = 10 A
Time (1 s/div)
VOUT (1 V/div)
EN (5 V/div)
PGOOD (5 V/div)
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
Figure 27. FCCM Load Transient Figure 28. Skip Mode Load Transient
Figure 29. Overcurrent Protection Figure 30. Over-temperature Protection
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TYPICAL CHARACTERISTICS
Figure 31, shows the thermal signature of the TPS53315 EVM, VIN = 12 V, VOUT = 1.1 V, IOUT= 12 A, fSW = 500 kHz at room
temperature with no airflow.
Figure 32 shows the thermal signature of the TPS53315 EVM, VIN = 12 V, VOUT = 3.3 V, IOUT= 12 A, fSW = 650 kHz at room
temperature with no airflow.
Figure 31. Thermal Signature of TPS53315 EVM, Figure 32. Thermal Signature of TPS53315 EVM,
fSW = 500 kHz fSW = 650 kHz
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS53315
N/C
N/C
TRIP
EN
PGOOD
N/C
VBST
N/C
LL
LL
LL
LL
LL
LL
LL
LL
VFB
RF
MODE
VDD
TPS53315
GND1
PGND
VREG
GND2
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
LL
LL
LL
LL
LL
VIN
VIN
VIN
1 2 3 4 5 6 7 8 9 10 11 12
20
19
18
17
16
15
14
13
32 31 30 29 28 27 26 25 24 23 22 21
33
34
35
36
37
38
39
40
L1
1mH
IN06155
COUT
100 mF
Ceramic
CIN
22 mF x 4
EN
VOUT
VIN
3 V to 15 V
UDG-10202
C3
1mF
C4
1mF
VDD
4.5 V to 25 V
R5
100 kW
R4
187 kW
R8
80.6 kW
R2
10 kW
PGOOD
VREG
PGOOD
R1
8.06 kW
R7
1.5 kW
C2 1 nF
C1
0.1 mF
COUT
100 mF
Ceramic
R12
0W
C5
0.1 mF
R9 0 W
R10 100 kW
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
APPLICATION INFORMATION
APPLICATION CIRCUIT DIAGRAM
Figure 33. Typical Application Circuit Diagram
Figure 34. Typical Application Circuit Diagram with Ceramic Output Capacitors
16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53315
TPS53315
www.ti.com
SLUSAE6 –DECEMBER 2010
General Description
The TPS53315 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage
point-of-load applications in computing and similar digital consumer applications. The device features proprietary
D-CAP™ mode control combined with an adaptive on-time architecture. This combination is ideal for building
modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to
5.5 V. The conversion input voltage range is from 3 V up to 15 V. The D-CAP™ mode uses the ESR of the
output capacitor(s) to sense the device current. One advantage of this control scheme is that it does not require
an external phase compensation network. This allows a simple design with a low external component count.
Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or
the VREG pin. Adaptive on-time control tracks the preset switching frequency over a wide input and output
voltage range while allowing the switching frequency to increase at the step-up of the load.
The TPS53315 has a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms.
Enable and Soft Start
When the EN pin voltage rises above the enable threshold voltage (typically 1.2 V), the controller enters its
start-up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The
controller then uses the first 250 ms to calibrate the switching frequency setting resistance attached to the RF pin
and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In
the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the
MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
Table 1. Soft-Start and MODE
SOFT-START TIME RMODE
MODE SELECTION ACTION (ms) (kΩ)
0.7 39
1.4 100
Auto Skip Pull down to GND 2.8 200
5.6 475
0.7 39
1.4 100
Forced CCM(1) Connect to PGOOD 2.8 200
5.6 475
(1) The device transitions into FCCM after the PGOOD pin goes high.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS53315
IN
ON
OUT
V
tV
æ ö
µ
ç ÷
è ø
VFB
VREF
PWM
tON tOFF
UDG-10208
VFB
Compensation
Ramp
PWM
tON tOFF
VREF
UDG-10209
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
Adaptive On-Time D-CAP™ Control
The TPS53315 does not have a dedicated oscillator to determine switching frequency. However, the device
operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time
one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage
and proportional to the output voltage .
This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 2. (Leaving the resistance open sets the
switching frequency to 500 kHz.)
Table 2. Resistor and Switching Frequency
SWITCHING FREQUENCY
RESISTOR (RRF) CONNECTIONS (kHz)
0Ωto GND 250
187 kΩto GND 300
619 kΩto GND 400
Open 500
866 kΩto VREG 600
309 kΩto VREG 750
124 kΩto VREG 850
0Ωto VREG 970
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When the signal values match, the
PWM comparator asserts a set signal to terminate the off-time (turn off the low-side MOSFET and turn on
high-side MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the
off-time is extended until the current level falls below the threshold.
Figure 35 and Figure 36 show two on-time control schemes.
Figure 35. On-Time Control Without Ramp Figure 36. On-Time Control With Ramp
Compensation Compensation
18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53315
R1
R2
Voltage
Divider
37
+
VFB
+
0.6 V
PWM Control
Logic
and
Divider
VIN
L
ESR
COUT
VC
RLOAD
IIND IOUT
UDG-10203
IC
Switching Modulator
Output
Capacitor
VOUT
TPS53315
LL
VIN
( )=´ ´ OUT
1
H s s ESR C
= £
p´ ´
SW
0
OUT
f
1
f2 ESR C 4
TPS53315
www.ti.com
SLUSAE6 –DECEMBER 2010
Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 37.
Figure 37. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on-cycle substantially
constant.
(1)
For the loop stability, the 0 dB frequency, ƒ0, defined in Equation 2 must be lower than ¼ of the switching
frequency.
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor
chemistry. For example, specialty polymer capacitors (SP-CAP) have COUT on the order of several 100 µF and
ESR in range of 10 mΩ. These makes ƒ0on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ0at more than 700 kHz, and need special care when used with this modulator. An
application circuit using ceramic capacitors is described in External Parts Selection section under All Ceramic
Output Capacitors.
Ramp Signal
The TPS53315 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. The feedback
voltage is compared with the reference information to keep the output voltage in regulation. By adding a small
ramp signal to the reference, the signal-to-noise ratio at the onset of a new switching cycle is improved.
Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start with –7 mV at
the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady state.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS53315
( ) ( )
- ´
= ´
´ ´
IN OUT OUT
OUT LL SW IN
V V V
1
I2 L f V
( ) ( ) ( )
= W ´ m
TRIP TRIP TRIP
V mV R k I A
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
Auto-Skip Eco-mode™ Light Load Operation
While the MODE pin is pulled low via RMODE, the TPS53315 automatically reduces the switching frequency at
light-load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is
maintained as it was in the continuous conduction mode so that it takes longer time to discharge the output
capacitor with smaller load current to the level of the reference voltage. The transition point to the light-load
operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated
as shown in Equation 3.
where
• ƒSW is the PWM switching frequency (3)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 3. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
Adaptive Zero Crossing
The TPS53315 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by postponed detection and minimizes diode conduction period caused by
premature detection. As a result, better light-load efficiency is delivered.
Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) during light-load conditions. In this mode, the switching frequency is maintained over the entire load range
which is suitable for applications needing tight control of the switching frequency at a cost of lower efficiency.
Power Good
The TPS53315 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of
the target value, internal comparators detect the powergood state and the powergood signal becomes high after
a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good
signal becomes low after two microsecond (2-ms) internal delay. The powergood output is an open drain output
and must be pulled up externally.
In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic
before the TPS53315 is powered up, it is recommended the PGOOD be pull to VREG (either directly or through
a resistor divider) because VREG remains low when the device is off.
Current Sense and Overcurrent Protection
TPS53315 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller maintains the OFF state during the period in that the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53315 supports
temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip
voltage setting resistor, RTRIP. The TRIP pin sources ITRIP current, which is 10 mA typically at room temperature,
and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 4.
(4)
20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53315
( ) ( )
( )
- ´
= + = + ´
´ ´
´ ´
IND(ripple) IN OUT OUT
TRIP TRIP
OCP
SW IN
DS(on) DS(on)
IV V V
V V 1
I2 2 L f V
8 R 8 R
TPS53315
www.ti.com
SLUSAE6 –DECEMBER 2010
The inductor current is monitored by the voltage between the GND pin and the SW pin so that the SW pin should
be connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700 ppm/°C temperature slope
to compensate the temperature dependency of the RDS(on). The GND pin is used as the positive current sensing
node. The GND pin should be connected to the proper current sensing device, (for example, the source terminal
of the low-side MOSFET.)
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 5.
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, therefore the
output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts down.
After a hiccup delay (16 ms with 0.7-ms sort-start), the controller restarts. If the overcurrent condition remains,
the procedure is repeated and the device enters hiccup mode.
During CCM, the negative current limit (NCL) protects the internal FET from carrying too much current. The NCL
detect threshold is set as the same absolute value as positive OCL but negative polarity. Note that the threshold
continues to represent the valley value of the inductor current.
Overvoltage and Undervoltage Protection
The TPS53315 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. When the
feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an
internal UVP delay counter begins counting. After 1 ms, TPS53315 latches OFF both high-side and low-side
MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7-ms soft-start). This function is
enabled 1.5 ms after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The
output voltage decreases. If the output voltage reaches the UV threshold, then both high-side MOSFET and
low-side MOSFET driver is OFF and the device restarts after a hiccup delay. If the OV condition remains, both
high-side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed.
UVLO Protection
The TPS53315 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than the
UVLO threshold voltage, the switch mode power supply shuts off. This is a non-latch protection.
Thermal Shutdown
TPS53315 includes a temperature monitoring feature. If the temperature exceeds the threshold value (typically
145°C), TPS53315 shuts off. When the temperature falls approximately 10°C below the threshold value, the
device turns on again. This is a non-latch protection.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS53315
( )
( )
()
( ) ( )
( )
()
- ´ - ´
= ´ = ´
´ ´
IN OUT OUT IN OUT OUT
max max
SW IN OUT SW IN(max)
IND ripple max max
V V V V V V
1 3
LI f V I f V
( ) ( )
( )
()
( )
- ´
= + ´
´ ´
IN OUT OUT
max
TRIP
IND peak SW IN
DS on max
V V V
V1
I8 R L f V
( )
( ) ( )
( )( ) ( )
´ ´ - ´ ´ ´
= = = W
´
OUT SW SW
IND ripple
V 10 mV (1 D) 10 mV L f L f
ESR 0.6 V I 0.6 V 60
( )´
- -
= ´
IND ripple
OUT
I ESR
V 0.6
2
R1 R2
0.6
TPS53315
SLUSAE6 –DECEMBER 2010
www.ti.com
External Parts Selection
The external components selection is a simple process using D-CAP™ Mode.
1. CHOOSE THE INDUCTOR
The inductance value should be determined to give the ripple current of approximately 1/4 to ½ of maximum
output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and
helps stable operation.
(6)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 7.
(7)
2. CHOOSE THE OUTPUT CAPACITOR(S)
When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability,
capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to
determine ESR.
where
• D is the duty factor
• tSW is the switching period
• the required output ripple slope is approximately 20 mV per tSW in terms of VVFB (8)
3. DETERMINE THE VALUE OF R1 AND R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is
connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is from 10kΩto 20kΩ. Determine R1 using Equation 9.
(9)
22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS53315
-
= ´
´
IN OUT
INJ _ SW
SW
V V D
VR7 C1 f
( ) ( )
= ´ + ´ ´
IND ripple
INJ _ OUT IND ripple OUT SW
I
V ESR I 8 C f
+
= + INJ _ SW INJ _ OUT
VFB
V V
V 0.6 2
-
= ´
OUT FB
FB
V V
R1 R2
V
TPS53315
www.ti.com
SLUSAE6 –DECEMBER 2010
External Parts Selection with All Ceramic Output Capacitors
When ceramic output capacitors are used, the stability criteria in Equation 2 cannot be satisfied. The ripple
injection approach as shown in Equation 10 is implemented to increase the ripple on the VFB pin and make the
system stable. C2 can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.
The increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the
VFB pin has two components, one coupled from SW node and the other coupled from VOUT and they can be
calculated using Equation 10 and Equation 11.
(10)
(11)
The DC value of VFB can be calculated by Equation 12:
(12)
And the resistor divider value can be determined by Equation 13:
(13)
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a layout work using the TPS53315.
• The power components (including input/output capacitors, inductor and TPS53315) should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
• Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
• Since the TPS53315 controls output voltage referring to voltage across the VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner
both bottom side resistor and GND pad of the device should be connected to the negative node of VOUT
capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component
side and avoid via(s) between these resistors and the device.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
• Connect the frequency setting resistor from RF pin to ground, or to the VREG pin, and make the connections
as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node.
• Connect the MODE setting resistor from MODE pin to ground, or to the PGOOD pin, and make the
connections as close as possible to the device. The trace from the MODE pin to the resistor and from the
resistor to ground should avoid coupling to a high-voltage switching node.
• The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS53315
PACKAGE OPTION ADDENDUM
www.ti.com 27-Dec-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS53315RGFR ACTIVE VQFN RGF 40 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS53315RGFT ACTIVE VQFN RGF 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53315RGFR VQFN RGF 40 3000 330.0 16.4 5.25 7.25 1.45 8.0 16.0 Q1
TPS53315RGFT VQFN RGF 40 250 180.0 16.4 5.25 7.25 1.45 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53315RGFR VQFN RGF 40 3000 367.0 367.0 38.0
TPS53315RGFT VQFN RGF 40 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Aug-2012
Pack Materials-Page 2
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