AVAILABLE
EVALUATION KIT AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX15024/MAX15025 single/dual, high-speed
MOSFET gate drivers are capable of operating at fre-
quencies up to 1MHz with large capacitive loads. The
MAX15024 includes internal source-and-sink output
transistors with independent outputs allowing for control
of the external MOSFET’s rise and fall time. The
MAX15024 is a single gate driver capable of sinking an
8A peak current and sourcing a 4A peak current. The
MAX15025 is a dual gate driver capable of sinking a 4A
peak current and sourcing a 2A peak current. An inte-
grated adjustable LDO voltage regulator provides gate-
drive amplitude control and optimization.
The MAX15024A and MAX15025A/C accept transistor-
to-transistor (TTL) input logic levels while the
MAX15024B and MAX15025B/D accept CMOS-input
logic levels. High sourcing/sinking peak currents, a low
propagation delay, and thermally enhanced packages
make the MAX15024/MAX15025 ideal for high-frequency
and high-power circuits. The MAX15024/MAX15025
operate from a 4.5V to 28V supply. A separate output dri-
ver supply input enhances flexibility and permits a soft-
start of the power MOSFETs used in synchronous
rectifiers.
The MAX15024/MAX15025 are available in 10-pin
TDFN packages and are specified over the -40°C to
+125°C automotive temperature range.
Applications
Synchronous Rectifier Drivers
Power-Supply Modules
Switching Power Supply
Features
o8A Peak Sink Current/4A Peak Source Current
(MAX15024)
o4A Peak Sink Current/2A Peak Source Current
(MAX15025)
oLow 16ns Propagation Delay
o4.5 V to 28V Supply Voltage Range
oOn-Board Adjustable LDO for Gate-Drive
Amplitude Control and Optimization
oSeparate Output Driver Supply
oIndependent Source and Sink Outputs (MAX15024)
oMatched Delays Between Inverting and
Noninverting Inputs (MAX15024)
oMatched Delays Between Channels (MAX15025)
oCMOS or TTL Logic-Level Inputs with Hysteresis
for Noise Immunity
o-40°C to +125°C Operating Temperature Range
oThermal-Shutdown Protection
o1.95W Thermally Enhanced TDFN Power Packages
oAEC-Q100 Qualified
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
10 87
REG
P_OUT
N_OUT
FB/SET
GND
IN+
MAX15024
9
DRVVCC
6
1
EP*
*EP = EXPOSED PAD.
3425
PGNDIN-
TDFN
TOP VIEW
Pin Configurations
Ordering Information
Note: All devices are specified over the -40°C to +125°C operating
temperature range.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V = denotes an automotive qualified part.
*
EP = Exposed pad. T = Tape and reel.
See the Selector Guide at the end of the data sheet.
Pin Configurations continued at end of data sheet. Block Diagrams appear at end of data sheet.
PART PIN-PACKAGE
TOP MARK
MAX15024AATB+T 10 TDFN-EP* ATX
MAX15024AATB/V+T
10 TDFN-EP* AWT
MAX15024BATB+T 10 TDFN-EP* ATY
MAX15025AATB+T 10 TDFN-EP* ATZ
MAX15025AATB/V+T
10 TDFN-EP* AYE
MAX15025BATB+T 10 TDFN-EP* AUA
MAX15025CATB+T 10 TDFN-EP* AUB
MAX15025DATB+T 10 TDFN-EP* AUC
MAX15024/MAX15025
19-1053; Rev 3; 4/11
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
ABSOLUTE MAXIMUM RATINGS
MAX15024 ELECTRICAL CHARACTERISTICS
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= TJ=
+ 25°C). (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND............................................................-0.3V to +30V
REG to GND..............-0.3V to the lower of +22V or (VCC + 0.3V)
DRV to PGND .........................................................-0.3V to +22V
IN_ ..........................................................................-0.3V to +22V
FB/SET to GND.........................................................-0.3V to +6V
P_OUT to DRV ........................................................-22V to +0.3V
N_OUT to PGND.....................................................-0.3V to +22V
OUT1, OUT2 to PGND ..............................-0.3V to (VDRV + 0.3V)
PGND to GND .......................................................-0.3V to +0.3V
P_OUT, N_OUT Continuous Source/Sink Current* .......... 200mA
OUT1, OUT2 Continuous Source/Sink Current*................200mA
Continuous Power Dissipation (TA= +70°C)
10-Pin TDFN, Single-Layer Board
(derate 18.5mW/°C above +70°C)...........................1481.5mW
10-Pin TDFN, Multilayer Board
(derate 24.4mW/°C above +70°C)...........................1951.2mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYSTEM SPECIFICATIONS
MAX15024B 6.5 28.0
VCC powered only, VREG =
VDRV decoupled with
minimum 1µF to GND MAX15024A 4.5 28.0
VCC = VREG = VDRV (MAX15024B) 6.5 18.0
Input Voltage Range VCC
VCC = VREG = VDRV (MAX15024A) 4.5 18.0
V
VDRV Turn-On Voltage VDRV_ON VCC = VREG = 10V, IN+ = VCC, IN- = GND 1.7 2.3 V
Quiescent Supply Current IN_ = VCC or GND 700 1350 µA
Quiescent Supply Current
Under UVLO Condition IN_ = VCC or GND 250 µA
Switching Supply Current Switching at 250kHz, CL = 0F 1.5 3.0 mA
VCC Undervoltage Lockout UVLO_ VCC VCC rising 3.0 3.4 3.8 V
VCC Undervoltage-Lockout
Hysteresis 300 mV
VCC rising 100
VCC Undervoltage Lockout to
Output Delay VCC falling 2 µs
REG REGULATOR (VCC = 12V, REG = VDRV, CL = 1μF, FB/SET = GND)
Output Voltage VREG 12V < VCC < 28V, 0 < ILOAD < 10mA 91011 V
VCC = 6.5V, ILOAD = 100mA 0.4 0.9
Dropout Voltage VR_DO VCC = 4.5V, ILOAD = 50mA 0.2 0.5
V
Load Regulation VCC = 12V, ILOAD = 0 to 100mA 1 %
Line Re
g
ulation 12V < V
CC
< 28V 10 mV
*
Continuous output current is limited by the power dissipation of the package.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
10 TDFN
Junction-to-Ambient Thermal Resistance (θJA)...............41°C/W
Junction-to-Case Thermal Resistance (θJC)......................9°C/W
MAX15024/MAX15025
2
Maxim Integrated
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DRIVER OUTPUT (SINK)
TA = +25°C 0.45 0.60
VCC = VREG = VDRV = 10V,
sinking 100mA TA = +125°C 0.625 0.850
TA = +25°C 0.50 0.65
Driver Output Resistance RON-N VCC = VREG = VDRV = 4.5V,
sinking 100mA
(MAX15024A) TA = +125°C 0.7 0.9
Ω
Peak Output Current IPK-N VN_OUT = 10V 8 A
Maximum Load Capacitance SOA condition: CL x VDRV2 ≤ 20µJ,
for VDRV = 10V 200 nF
Latchup Robustness 500 mA
DRIVER OUTPUT (SOURCE)
TA = +25°C 0.875 1.500
VCC = VREG = VDRV = 10V,
sourcing 100mA TA = +125°C 1.2 2.0
TA = +25°C 0.95 1.65
Driver Output Resistance RON-P VCC = VREG = VDRV = 4.5V,
sourcing 100mA
(MAX15024A) TA = +125°C 1.25 2.20
Ω
Peak Output Current IPK-P VP_OUT = 0V 4 A
Latchup Robustness 500 mA
LOGIC INPUTS
MAX15024A 2.0
Logic 1 Input Voltage VIH MAX15024B 4.25 V
MAX15024A 0.8
Logic 0 Input Voltage VIL MAX15024B 2 V
MAX15024A 0.4
Logic Input Hysteresis MAX15024B 1 V
Logic Input Current Leakage VIN = 18V or VGND -75 0.01 +75 µA
Input Capacitance 10 pF
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 10V, P_OUT AND N_OUT ARE CONNECTED TOGETHER
(see Figure 1)
CLOAD = 1nF 3
CLOAD = 5nF 12
Rise Time tR
CLOAD = 10nF 24
ns
CLOAD = 1nF 3
CLOAD = 5nF 8Fall Time tF
CLOAD = 10nF 16
ns
Turn-On Delay Time tD-ON CLOAD = 1nF (Note 3) 8 16 32 ns
Turn-Off Delay Time tD-OFF CLOAD = 1nF (Note 3) 8 16 32 ns
Mismatch Propagation Delays
from Inverting and Noninverting
Inputs to Output
CLOAD = 1nF (Note 3) -9 1 +9 ns
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= TJ=
+ 25°C). (Note 2)
MAX15024/MAX15025
Maxim Integrated
3
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= TJ=
+ 25°C). (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 4.5V (see Figure 1) (MAX15024A)
CLOAD = 1nF 3
CLOAD = 5nF 11
Rise Time tR
CLOAD = 10nF 22
ns
CLOAD = 1nF 2.5
CLOAD = 5nF 8
Fall Time tF
CLOAD = 10nF 16
ns
Turn-On Delay Time tD-ON CLOAD = 1nF 18 ns
Turn-Off Delay Time tD-OFF CLOAD = 1nF 18 ns
Mismatch Propagation Delays
from Inverting and Noninverting
Inputs to Output
CLOAD = 1nF 2 ns
Minimum Input Pulse Width that
Changes the Output tPW 15 ns
THERMAL CHARACTERISTICS
Thermal-Shutdown
Temperature Temperature rising +160 °C
Thermal-Shutdown
Temperature Hysteresis 15 °C
MAX15025 ELECTRICAL CHARACTERISTICS
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= TJ=
+25°C). (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYSTEM SPECIFICATIONS
MAX15025B/D 6.5 28
VCC powered only,
VREG = VDRV decoupled
with minimum 1µF
to GND MAX15025A/C 4.5 28
VCC = VREG = VDRV (MAX15025B/D) 6.5 18.0
Input Voltage Range VCC
VCC = VREG = VDRV (MAX15025A/C) 4.5 18.0
V
VDRV Turn-On Voltage VDRV_ON VCC = VREG = 10V, IN1 = VCC, IN2 = VCC
(M AX 15025A/B) or GN D for ( M AX 15025C /D ) 1.7 2.3 V
Quiescent Supply Current IN_ = VCC or GND 700 1350 µA
Quiescent Supply Current
Under UVLO Condition IN_ = VCC or GND 250 µA
Switching Supply Current Switching at 250kHz, CL = 0F 1.5 3.0 mA
VCC Undervoltage Lockout UVLO_ VCC VCC rising 3.0 3.4 3.8 V
MAX15024/MAX15025
4
Maxim Integrated
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= TJ=
+25°C). (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Undervoltage-Lockout
Hysteresis 300 mV
VCC rising 100
VCC Undervoltage Lockout to
Output Delay VCC falling 2 µs
REG REGULATOR (VCC = 12V, VREG = VDRV, CL = 1μF, FB/SET = GND)
Output Voltage VREG 12V < VCC < 28V, 0 < ILOAD < 10mA 9 10 11 V
VCC = 6.5V, ILOAD = 100mA 0.4 0.9
Dropout Voltage VR_DO VCC = 4.5V, ILOAD = 50mA 0.2 0.5 V
Load Regulation VCC = 12V, ILOAD = 0 to 100mA 1 %
Line Regulation 12V < VCC < 28V 10 mV
FB/SET Reference Voltage External resistive divider connected at
FB/SET 1.10 1.23 1.35 V
FB/SET Threshold VFB rising 220 mV
FB/SET Input Leakage Current VFB = 4.5V -125 +125 nA
DRIVER OUTPUT SINK
TA = +25°C 1.0 1.6
VCC = VREG = VDRV = 10V,
sinking 100mA TA = +125°C 1.25 2.10
TA = +25°C 1.10 1.65
Driver Output Resistance RON-N VCC = VREG = VDRV = 4.5V,
sinking 100mA
(MAX15025A/C) TA = +125°C 1.5 2.2
Ω
Peak Output Current IPK-N VOUT_ = 10V 4 A
Maximum Load Capacitance SOA condition: CL x VDRV2
≤ 20µJ,
for VDRV = 10V 100 nF
Latchup Robustness 500 mA
DRIVER OUTPUT SOURCE
TA = +25°C 1.75 2.50
VCC = VREG = VDRV = 10V,
sourcing 100mA TA = +125°C 2.25 3.50
TA = +25°C 1.85 2.60
Driver Output Resistance RON-P VCC = VREG = VDRV = 4.5V,
sourcing 100mA
(MAX15025A/C) TA = +125°C 2.50 3.75
Ω
Peak Output Current IPK-P VOUT_ = 0V 2 A
Latchup Robustness 500 mA
LOGIC INPUTS
MAX15025A/C 2.0
Logic 1 Input Voltage VIH MAX15025B/D 4.25 V
MAX15025A/C 0.8
Logic 0 Input Voltage VIL MAX15025B/D 2 V
MAX15025A/C 0.4
Logic Input Hysteresis MAX15025B/D 1 V
Logic Input Current Leakage VIN = 18V or VGND -75 +0.01 +75 µA
Input Capacitance 10 pF
MAX15024/MAX15025
Maxim Integrated
5
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at TA= TJ=
+25°C). (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 10V (see Figure 1)
CLOAD = 1nF 6
CLOAD = 5nF 24Rise Time tR
CLOAD = 10nF 48
ns
CLOAD = 1nF 5
CLOAD = 5nF 16
Fall Time tF
CLOAD = 10nF 32
ns
Turn-On Delay Time tD-ON CLOAD = 1nF (Note 3) 8 16 32 ns
Turn-Off Delay Time tD-OFF CLOAD = 1nF (Note 3) 8 16 32 ns
Mismatch Propagation Delays
Between 2 Channels CLOAD = 1nF (Note 3) -9 1 +9 ns
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 4.5V (see Figure 1) (MAX15025A/C)
CLOAD = 1nF 5
CLOAD = 5nF 20Rise Time tR
CLOAD = 10nF 42
ns
CLOAD = 1nF 4
CLOAD = 5nF 15
Fall Time tF
CLOAD = 10nF 30
ns
Turn-On Delay Time tD-ON CLOAD = 1nF 18 ns
Turn-Off Delay Time tD-OFF CLOAD = 1nF 18 ns
Mismatch Propagation Delays
Between 2 Channels CLOAD = 1nF 2 ns
Minimum Input Pulse Width that
Changes the Output tPW 15 ns
THERMAL CHARACTERISTICS
Thermal-Shutdown Temperature Temperature rising +160 °C
Thermal-Shutdown Temperature
Hysteresis 15 °C
Note 2: All devices are 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 3: Design guaranteed by bench characterization. Limits are not production tested.
MAX15024/MAX15025
6
Maxim Integrated
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
RISE TIME vs. SUPPLY VOLTAGE
(DUAL DRIVER WITH 5nF LOAD)
MAX15024/25 toc01
SUPPLY VOLTAGE (V)
RISE TIME (ns)
191817161514131211
10
20
30
40
0
10 20
TA = +125°CMAX15025
TA = +85°C
TA = +25°C
TA = -40°C
TA = 0°C
FALL TIME vs. SUPPLY VOLTAGE
(WITH 5nF LOAD)
MAX15024/25 toc02
SUPPLY VOLTAGE (V)
FALL TIME (ns)
18161412
15
20
25
30
10
10 20
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = 0°C
MAX15025
PROPAGATION DELAY TIME
vs. TEMPERATURE (1nF LOAD)
MAX15024/25 toc03
TEMPERATURE (°C)
PROPAGATION DELAY TIME (ns)
120100806040200-20-40
8
10
12
14
16
18
6
-60 140
RISING
FALLING
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(PROGRAMMED EXTERNALLY TO 5V)
MAX15024/25 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
18161412108642
500
1000
1500
2000
2500
0
020
1MHz
500kHz
75kHz
40kHz
100kHz
SUPPLY CURRENT
vs. LOAD CAPACITANCE
MAX15024/25 toc05
LOAD CAPACITANCE (nF)
SUPPLY CURRENT (mA)
8000600040002000
6
12
18
24
30
0
0 10,000
SWITCHING
250kHz
VCC = VREG = VDRV = 10V
NOT SWITCHING
SUPPLY CURRENT
vs. TEMPERATURE
MAX15024/25 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
80400
200
400
600
800
1000
1200
1400
1600
1800
0
-40 120
SWITCHING
250kHz
NOT SWITCHING
VCC = VREG = VDRV = 10V
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE (TTL)
MAX15024/25 toc07
SUPPLY VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
16128
0.5
1.0
1.5
2.0
2.5
3.0
0
420
RISING
FALLING
SUPPLY CURRENT
vs. LOGIC IN
MAX15024/25 toc08
INPUT VOLTAGE (V)
SUPPLY CURRENT (μA)
541 2 3
200
400
600
800
1000
1200
1400
1600
00
06
INPUT
HIGH TO LOW
INPUT
LOW TO HIGH
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(5nF RISING)
MAX15024/25 toc09
20ns/div
IN_
1V/div
OUT_
5V/div
MAX15025
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX15024/MAX15025
Maxim Integrated
7
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(5nF FALLING)
MAX15024/25 toc10
20ns/div
IN_
1V/div
OUT_
5V/div
MAX15025
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(10nF RISING)
MAX15024/25 toc11
20ns/div
IN_
1V/div
OUT_
5V/div
MAX15025
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(10nF FALLING)
MAX15024/25 toc12
20ns/div
IN_
1V/div
OUT_
5V/div
MAX15025
PROPAGATION DELAY MISMATCH
vs. TEMPERATURE
MAX15024/25 toc13
TEMPERATURE (°C)
PROPAGATION DELAY BETWEEN CHANNELS (ns)
80400
0.5
1.0
1.5
2.0
2.5
3.0
0
-40 120
LINE REGULATION OF VREG
(PROGRAMMED EXTERNALLY TO 5.04V)
MAX15024/25 toc14
SUPPLY VOLTAGE
VREG (V)
25201510
4.8
4.9
5.0
5.1
5.2
5.3
4.7
530
LOAD REGULATION OF VREG
MAX15024/25 toc15
LOAD CURRENT (mA)
VREG (V)
18016014012010080604020
9.5
10.0
10.5
11.0
9.0
0 200
FB/SET VOLTAGE
vs. TEMPERATURE
MAX15024/25 toc16
TEMPERATURE (°C)
FB/SET VOLTAGE (V)
10080604020
1.232
1.234
1.236
1.238
1.240
1.230
0120
FB/SET CURRENT
vs. TEMPERATURE
MAX15024/25 toc17
TEMPERATURE (°C)
FB/SET CURRENT (nA)
10080604020
5
10
15
20
0
0120
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX15024/MAX15025
8
Maxim Integrated
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Pin Description
PIN
MAX15024 MAX15025A
MAX15025B
MAX15025C
MAX15025D
NAME FUNCTION
1 1 1 FB/SET
LDO Regulator Output Set. Feedback for VREG adjustment (VFB > 200mV).
Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a
resistor ladder to set VREG.
22 2V
CC
Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of
1µF. Input of the internal housekeeping regulator and of the main REG
regulator.
3 3 3 GND Signal Ground
4 — — IN+ Driver Noninverting Logic Input. Connect to VCC when not used.
— 4 4 IN1 Driver 1 Noninverting Logic Input
5 — — IN- Driver Inverting Logic Input. Connect to GND when not used.
— 5 — IN2 Driver 2 Noninverting Logic Input
—— 5IN2 Driver 2 Inverting Logic Input
6 6 6 PGND Power Ground. Sink current return. Source of the internal pulldown
n-channel transistor.
7 — — N_OUT Sink Output. Open-drain n-channel output. N_OUT sinks current for power
MOSFET turn-off.
— 7 7 OUT2 Driver 2 Output
8 — — P_OUT Source Output. Pullup p-channel output (open drain). Sources current for
power MOSFET turn-on.
— 8 8 OUT1 Driver 1 Output
9 9 9 DRV
Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1µF
ceramic capacitor to PGND placed in close proximity to the device. DRV
can be powered independently from REG. Connect DRV, REG, and VCC
together when there is no need for special DRV supply sequencing and
the power-MOSFET gate voltage does not need to be regulated or limited.
10 10 10 REG
Voltage Regulator Output. Connect to DRV for driving the power MOSFET
with regulated VGS amplitude. Bypass with a low-ESR 1µF (minimum)
ceramic capacitor to GND placed in close proximity to the device to
ensure regulator stability.
—— —EP
Exposed Pad. Internally connected to GND. Connect to GND plane or
thermal pad and use multiple vias to a solid copper area on the bottom of
the PCB.
MAX15024/MAX15025
Maxim Integrated
9
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Detailed Description
The MAX15024 single gate driver’s internal source and
sink transistor outputs are brought out of the IC to inde-
pendent outputs allowing control of the external
MOSFET’s rise and fall time. The MAX15024 single
gate driver is capable of sinking an 8A peak current
and sourcing a 4A peak current. The MAX15025 dual
gate drivers are capable of sinking a 4A peak current
and sourcing a 2A peak current.
An integrated adjustable low-dropout linear voltage
regulator (LDO) provides gate drive amplitude control
and optimization. The single gate-driver propagation
delay time is minimized and matched between the
inverting and noninverting inputs. The dual gate-driver
propagation delay is matched between channels.
The MAX15024 has a dual input (IN+ and IN-), allows
the use of an inverting or noninverting input, and is
offered in TTL or CMOS-logic standards. The
MAX15025 is offered with configurations of inverting
and noninverting inputs with TTL or CMOS standards
(see the
Selector Guide
).
LDO Voltage Regulator Feedback Control
The MAX15024/MAX15025 include an internal LDO
designed to deliver a stable reference voltage for use
as a supply voltage for the internal MOSFET gate dri-
vers. Connect the LDO feedback FB/SET to GND to set
VREG to a stable 10V. Connect FB/SET to a resistor-
divider between VREG and GND to set VREG:
VREG = VFB/SET x (1 + R2 / R1) (see Figure 2)
VCC Undervoltage Lockout
When VCC is below the UVLO threshold, the internal n-
channel transistor is ON and the internal p-channel tran-
sistor is OFF, holding the output at GND independent of
the state of the inputs so that the external MOSFETs
remain OFF in the UVLO condition. The UVLO threshold is
3.5V (typ) with 200mV (typ) hysteresis to avoid chattering.
When the device is operated at very low temperatures
and below the UVLO threshold, the driver output could
go high impedance. In this case, it is recommended
adding a 10kΩresistor to PGND to discharge the gate
of the external MOSFET (see Figures 4 and 5).
Input Control
The MAX15024 features inverting and noninverting
input terminals. These inputs provide for flexibility of
design and use. Connect IN+ to VCC when using IN- as
an inverting input. Connect IN- to GND when using IN+
as a noninverting input.
Shoot-Through Protection
The MAX15024/MAX15025 provide protection that
avoids any cross-conduction between the internal p-
channel and n-channel devices. It also eliminates shoot-
through, thus reducing the quiescent supply current.
Exposed Pad (EP)
The MAX15024/MAX15025 include an exposed pad
allowing greater heat dissipation from the internal die to
the outside environment. Solder the exposed pad care-
fully to GND or thermal pad to enhance the thermal
performance.
Applications Information
Supply Bypassing, Device Grounding,
and Placement
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the
VDRV pin can approach 4A, while at the PGND pin, the
peak current can approach 8A. VDRV drops and
ground shifts are forms of negative feedback for invert-
ers and, if excessive, can cause multiple switching
when the inverting input is used and the input slew rate
is low. The device driving the input should be refer-
enced to the MAX15024/MAX15025 GND. Ground
shifts due to insufficient device grounding can disturb
other circuits sharing the same AC ground return path.
Any series inductance in the VDRV, OUT_, and/or PGND
paths can cause oscillations due to the very high di/dt
that results when the MAX15024/MAX15025 are
switched with any capacitive load. A 0.1µF or larger
value ceramic capacitor is recommended for bypass-
ing VDRV to GND and should be placed as close to the
pins as possible. When driving very large loads
(> 10nF) at minimum rise time, 10µF or more of parallel
storage capacitance is recommended. A ground plane
is highly recommended to minimize ground return resis-
tance and series inductance. Care should be taken to
place the MAX15024/MAX15025 as close as possible to
the external MOSFET being driven to further minimize
board inductance and AC path resistance.
MAX15024/MAX15025
10
Maxim Integrated
Power Dissipation
Power dissipation of the MAX15024/MAX15025 con-
sists of three components: the quiescent current,
capacitive charge and discharge of internal nodes, and
the output current (either capacitive or resistive load).
The sum of these components must be kept below the
maximum power-dissipation limit. The quiescent cur-
rent is 700µA typ. The current required to charge and
discharge the internal nodes is frequency dependent
(see the
Typical Operating Characteristics
). The
MAX15024/MAX15025 power dissipation when driving
a ground-referenced resistive load is:
P = D x RON(MAX) x ILOAD2
where D is the fraction of the period the MAX15024/
MAX15025s’ output pulls high, RON(MAX) is the maxi-
mum on-resistance of the device with the output high
(p-channel), and ILOAD is the output load current of the
MAX15024/MAX15025. For capacitive loads, the power
dissipation for each driver is:
P = CLOAD x VDRV2x FREQ
where CLOAD is the capacitive load, VDRV is the driver
supply voltage, and FREQ is the switching frequency.
Layout Information
The MAX15024/MAX15025 MOSFET drivers source and
sink large currents to create very fast rise and fall edges
at the gate of the switching MOSFET. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. The following
printed-circuit board (PCB) layout guidelines are recom-
mended when designing with the MAX15024/MAX15025:
• Place one or more 1µF decoupling ceramic capaci-
tor(s) from VDRV to PGND as close to the device as
possible. At least one storage capacitor of 10µF (min)
should be located on the PCB with a low resistance
path to the VCC pin of the MAX15024/MAX15025.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from MOSFET gate to
OUT_ of the MAX15024/MAX15025 to PGND of the
MAX15024/MAX15025, and to the source of the
MOSFET. When the gate of the MOSFET is being
pulled high, the active current loop is from the VDD
terminal of the VDRV terminal of decoupling capaci-
tor, to the VDRV of the MAX15024/MAX15025, to the
OUT_ of the MAX15024/MAX15025, to the MOSFET
gate, to the MOSFET source, and to the negative ter-
minal of the decoupling capacitor. Both charging
current loop and discharging current loop are impor-
tant. It is important to minimize the physical distance
and the impedance in these AC current paths.
• Keep the device as close as possible to the MOSFET.
• In the multilayer PCB, the inner layers should consist
of a GND plane containing the discharging and
charging current loops.
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
IN+
P_OUT AND
N_OUT CONNECTED
TOGETHER
OR OUT1/OUT2
VIL
VIH
tD-OFF tF
90%
10%
tD-ON tR
Figure 1. Timing Diagram
MAX15024/MAX15025
Maxim Integrated
11
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Typical Operating Circuits
MAX15024
REG
R2
R1
VCC
(UP TO 28V)
DRV
FB/SET P_OUT
N_OUT
PGND
GND
IN-
VCC
IN+
Figure 2. Use R1, R2 to program VREG < 18V, OR. Connect
FB/SET to GND for VREG = 10V (Connect EP to GND)
MAX15024
VCC
C1
VCC
(UP TO 18V)
REG
FB/SET P_OUT
DRV
VDRV < 18V
N_OUT
PGND
GND
IN-
IN+
Figure 3. Operation Using a Different Supply Rail for DRV
(Connect EP to GND)
MAX15024
VCC
VCC
(UP TO 18V)
REG
FB/SET P_OUT
DRV
N_OUT
PGND
GND
IN-
IN+
Figure 4. Operation Using a VCC = DRV = REG (Connect EP
to GND)
MAX15025
REG
R2
R1
VCC
(UP TO 28V)
DRV
FB/SET
OUT1
OUT2
PGND
GND
IN1
VCC
IN2
Figure 5. Use R1, R2 to program VREG < 18V, OR. Connect
FB/SET to GND for VREG = 10V (Connect EP to GND)
MAX15024/MAX15025
12
Maxim Integrated
LDO
PREDRIVER
PREDRIVER
IN_ LOGIC
LEVEL SHIFT-UP
IN_ LOGIC
LEVEL SHIFT-UP
UVLO
VCC
FB/SET
IN+
IN-
GND
REG
DRV
P_OUT
N_OUT
PGND
N
P
LDO
VCC
FB/SET
IN1
IN2
GND
REG
DRV
OUT1
OUT2
PGND
UVLO
PREDRIVER
PREDRIVER
PREDRIVER
PREDRIVER
IN_ LOGIC
LEVEL SHIFT-UP
IN_ LOGIC
LEVEL SHIFT-UP
IN_ LOGIC
LEVEL SHIFT-UP
IN_ LOGIC
LEVEL SHIFT-UP
MAX15025
MAX15024A
MAX15024B
P
P
N
N
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Block Diagrams
MAX15024/MAX15025
Maxim Integrated
13
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Selector Guide
PART NO. OF
CHANNELS
PEAK CURRENTS
(SINK/SOURCE) INPUTS LOGIC
LEVELS
TOP
MARK
MAX15024AATB+ 1 8A/4A Complementary TTL ATX
MAX15024AATB/V+ 1 8A/4A Complementary TTL AWT
MAX15024BATB+ 1 8A/4A Complementary CMOS ATY
MAX15025AATB+ 2 4A/2A Noninverting TTL ATZ
MAX15025AATB/V+ 2 4A/2A Noninverting TTL AYE
MAX15025BATB+ 2 4A/2A Noninverting CMOS AUA
MAX15025CATB+ 2 4A/2A Noninverting (1)/
Inverting (2) TTL AUB
MAX15025DATB+ 2 4A/2A Noninverting (1)/
Inverting (2) CMOS AUC
Note: All devices operate in a -40°C to +125°C temperature range and come in a 10-pin TDFN package.
EP
TOP VIEW
10 87
REG
OUT1
OUT2
FB/SET
GND
IN1
MAX15025A
MAX15025B
9
DRVVCC
6
13425
PGNDIN2
TDFN
EP
10 87
REG
OUT1
OUT2
FB/SET
GND
IN1
MAX15025C
MAX15025D
9
DRVVCC
6
13425
PGNDIN2
TDFN
Pin Configurations (continued)
MAX15024/MAX15025
14
Maxim Integrated
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN T1033+1 21-0137 90-0003
MAX15024/MAX15025
Maxim Integrated
15
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/07 Initial release —
1 3/08 Released MAX15024A/MAX15025B/C/D versions 1–6, 9, 13
2 4/10 Removed future product (MAX15024C/D, MAX15025E-H); minimum and
maximum specifications added to the EC table 1–6, 9, 10, 12–15
3 4/11 Added automotive part numbers to Ordering Information and Selector
Guide 1, 14
MAX15024/MAX15025
16 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2011 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
