1. General description
The 74HCU04 is high-speed Si-gate CMOS devices and is pin compatible with low power
Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74HCU04 is a general purpose hex inverter. Each of the six inverters is a single
stage.
2. Features and benefits
Balanced propagation delays
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +125 C
3. Ordering information
74HCU04
Hex inverter
Rev. 5 — 6 August 2012 Product data sheet
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74HCU04N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCU04D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCU04DB 40 C to +125 C SSOP14 plastic shrink small outlin e package; 14 leads; body width
5.3 mm SOT337-1
74HCU04PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCU04BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 2 of 18
NXP Semiconductors 74HCU04
Hex inverter
4. Functional diagram
5. Pinning information
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one
inverter)
mna342
1A 1Y
12
2A 2Y
34
3A 3Y
56
4A 4Y
98
5A 5Y
11 10
6A 6Y
13 12
112
mna343
314
516
918
11 110
13 112
mna045
AY
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It cannot be used
as a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
74HCU04
1A VCC
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND 4Y
001aal924
1
2
3
4
5
6
78
10
9
12
11
14
13
001aal925
VCC(1)
74HCU04
Transparent top view
3Y 4A
3A 5Y
2Y 5A
2A 6Y
1Y 6A
GND
4Y
1A
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 3 of 18
NXP Semiconductors 74HCU04
Hex inverter
5.1 Pin description
6. Functional description
7. Limiting values
Table 2. Pin description
Symbol Pin Description
1A 1 data input
1Y 2 data output
2A 3 data input
2Y 4 data output
3A 5 data input
3Y 6 data output
GND 7 ground (0 V)
4Y 8 data output
4A 9 data input
5Y 10 data output
5A 11 data input
6Y 12 data output
6A 13 data input
VCC 14 supply voltage
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level
Input Output
nA nY
LH
HL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -50 mA
IOoutput current 0.5 V < V O < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages - 500 mW
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Product data sheet Rev. 5 — 6 August 2012 4 of 18
NXP Semiconductors 74HCU04
Hex inverter
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
VIH HIGH-level
input voltage VCC = 2.0 V 1.7 1.4 - 1.7 - 1.7 - V
VCC = 3.0 V 3.6 2.6 - 3.6 - 3.6 - V
VCC = 5.5 V 4.8 3.4 - 4.8 - 4.8 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.6 0.3 - 0.3 - 0.3 V
VCC = 3.0 V - 1.9 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - 2.6 1.2 - 1.2 - 1.2 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO= 20 A; VCC = 2.0 V 1.8 2.0 - 1.8 - 1.8 - V
IO= 20 A; VCC = 4.5 V 4.0 4.5 - 4.0 - 4.0 - V
IO= 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO= 20 A; VCC = 6.0 V 5.5 6.0 - 5.5 - 5.5 - V
IO= 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 20 A; VCC = 2.0 V - 0 0.2 - 0.2 - 0.2 V
IO= 20 A; VCC = 4.5 V - 0 0.5 - 0.5 - 0.5 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 20 A; VCC = 6.0 V - 0 0.5 - 0.5 - 0.5 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 5 of 18
NXP Semiconductors 74HCU04
Hex inverter
10. Dynamic characteristics
[1] tpd is the same as tPHL, tPLH.
[2] tt is the same as tTHL, tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2 fo) = sum of outputs.
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --0.1 - 1.0 - 1.0 A
ICC supply current V I=V
CC or GND; IO=0A;
VCC =6.0V --2 - 20 - 20 A
CIinput
capacitance -3.5- - - - - pF
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 7.
Symbol Parameter Conditions 25 C 40 C to
+85 C40 C to
+125 CUnit
Typ Max Max Max
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 2.0 V; CL = 50 pF 19 70 90 105 ns
VCC = 4.5 V; CL = 50 pF 7 14 18 21 ns
VCC = 5.0 V; CL = 15 pF 5 - - - ns
VCC = 6.0 V; CL = 50 pF 6 12 15 18 ns
tttransition time see Figure 6 [2]
VCC = 2.0 V; CL = 50 pF 19 75 95 110 ns
VCC = 4.5 V; CL = 50 pF 7 15 19 22 ns
VCC = 6.0 V; CL = 50 pF 6 13 16 19 ns
CPD power dissipation
capacitance per inverter; VI=GNDtoV
CC [3] 10 - pF
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Product data sheet Rev. 5 — 6 August 2012 6 of 18
NXP Semiconductors 74HCU04
Hex inverter
11. Waveforms
12. Typical transfer characteristics
VM = 0.5 VCC; VI = GND to VCC. Definitions for test circuit:
CL = Load capacitance including jig and probe
capacitance.
RT = Termination resistance should be equal to output
impedance Zo of the pulse generator.
Fig 6. The input (nA) to output (nY) propagation
delay times Fig 7. Load circuit for switching times
mna722
t
PLH
t
PHL
V
M
V
M
90 %
10 %
V
M
V
M
nY output
nA input
V
I
GND
V
OH
V
OL
t
TLH
t
THL
V
CC
VIVO
mna034
DUT
CL
50 pF
RT
PULSE
GENERATOR
Tamb = 25 C. Tamb = 25 C.
Fig 8. VCC =2.0V; I
O=0 A Fig 9. V
CC = 4.5 V; IO=0 A
VI (V)
0 2.41.60.8
001aal928
0.8
1.6
2.4
(1)
(2)
VO
(V) ID
(mA)
0
0.4
0.8
1.2
0
VI (V)
0642
001aal927
2
4
6
(1)
(2)
VO
(V) ID
(mA)
0
8
16
24
0
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Product data sheet Rev. 5 — 6 August 2012 7 of 18
NXP Semiconductors 74HCU04
Hex inverter
Tamb = 25 C.
fi = 1 kHz at VO is constant
Fig 10. VCC =6.0V; I
O= 0 A Fig 11. Test set-up for measuring forward
transconductance
VI (V)
0642
001aal926
2
4
6(1)
(2)
VO
(V) ID
(mA)
0
20
40
60
0
gfs
Io
Vi
---------
=
Tamb = 25 C.
Fig 12. Typical forward transconductance as a function of the supply voltage
0246
40
30
10
0
20
mna355
VCC (V)
gfs
(mA/V)
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Product data sheet Rev. 5 — 6 August 2012 8 of 18
NXP Semiconductors 74HCU04
Hex inverter
13. Application information
Some applications are:
•Linear amplifier (see Figure 13)
•Crystal oscillator design (see Figure 14)
•Astable multivibrator (see Figure 15)
Remark: All values given are typical unless otherwise specified.
Maximum Vo(p-p) =V
CC 2.0 V centered at 0.5 VCC.
Gol = open loop gain
Gv= voltage gain
R1 3k,R21M
ZL>10k; Gol =20(typical)
VCC = 6.0 V
Typical unity gain bandwidth product is 5 MHz.
C1 = 47 pF (typical)
C2 = 33 pF (typical)
R1 = 1 M to 10 M (typical
R2 optimum value depends on the frequency and
required stability against changes in VCC or average
minimum ICC. ICC is typically 5 mA at VCC = 5 V and
fi=10MHz.
Fig 13. Used as a linear am plifier Fig 14. Crystal oscilla to r configurati on
U04
R1
R2
VCC
ZL
mna052
1 μF
mna053
U04
out
R2
R1
C1 C2
GvGol
1R1
R2
-------1G
ol
++
---------------------------------------
–=
Table 8. External components for resonator (f < 1 MHz)
All values given are typical and must be used as an initial set-up.
Frequency R1 R2 C1 C2
10 kHz to 15.9 kHz 22 M220 k56 pF 20 pF
16 kHz to 24.9 kHz 22 M220 k56 pF 10 pF
25 kHz to 54.9 kHz 22 M100 k56 pF 10 pF
55 kHz to 129.9 kHz 22 M100 k47 pF 5 pF
130 kHz to 199.9 kHz 22 M47 k47 pF 5 pF
200 kHz to 349.9 kHz 10 M47 k47 pF 5 pF
350 kHz to 600 kHz 10 M47 k47 pF 5 pF
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 9 of 18
NXP Semiconductors 74HCU04
Hex inverter
Table 9. Optimum value for R2
Frequency R2 Optimum for
3 kHz 2.0 kminimum required ICC
8.0 kminimum influence due to change in VCC
6 kHz 1.0 kminimum required ICC
4.7 kminimum influence by VCC
10 kHz 0.5 kminimum required ICC
2.0 kminimum influence by VCC
14 kHz 0.5 kminimum required ICC
1.0 kminimum influence by VCC
>14 kHz - replace R2 by C3 with a typical value of 35 pF
The average ICC (mA) is approximately
3.5 + 0.05 f(MHz) C (pF) at VCC = 5.0 V.
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
Tamb = 25 C.
Fig 15. Astable multivibrator Fig 16. Input capacitance as function of input voltage
001aah115
RSRC
U04 U04
VI (V)
08624
001aal930
40
20
60
80
0
input
capacitance
(pF)
(2)
(1)
(3)
(4) (5)
f1
T
---1
2.2RC
---------------
=
RS2R
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 10 of 18
NXP Semiconductors 74HCU04
Hex inverter
14. Package outline
Fig 17. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 11 of 18
NXP Semiconductors 74HCU04
Hex inverter
Fig 18. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
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Product data sheet Rev. 5 — 6 August 2012 12 of 18
NXP Semiconductors 74HCU04
Hex inverter
Fig 19. Package outline SOT337-1 (SSOP14)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
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Product data sheet Rev. 5 — 6 August 2012 13 of 18
NXP Semiconductors 74HCU04
Hex inverter
Fig 20. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
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Product data sheet Rev. 5 — 6 August 2012 14 of 18
NXP Semiconductors 74HCU04
Hex inverter
Fig 21. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
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Product data sheet Rev. 5 — 6 August 2012 15 of 18
NXP Semiconductors 74HCU04
Hex inverter
15. Abbreviations
16. Revision history
Table 10. Abbr eviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
LSTTL Low-power Schottky Transistor-Transistor Logic
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
CDM Charge Device Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HCU04 v.5 20120806 Product data sheet - 74HCU04 v. 4
Modifications: •Measurement points added to figure 6 (errata).
74HCU04 v.4 20111212 Product data sheet - 74HCU04 v.3
Modifications: •Legal pages updated.
74HCU04 v.3 20100916 Product data sheet - 74HCU04_CNV v.2
74HCU04_CNV v.2 19970826 Product specification - -
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Product data sheet Rev. 5 — 6 August 2012 16 of 18
NXP Semiconductors 74HCU04
Hex inverter
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HCU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 17 of 18
NXP Semiconductors 74HCU04
Hex inverter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting fr om customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HCU04
Hex inverter
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 August 2012
Document identifier: 74HCU04
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Typical transfer characteristics . . . . . . . . . . . . 6
13 Application information. . . . . . . . . . . . . . . . . . . 8
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
18 Contact information. . . . . . . . . . . . . . . . . . . . . 17
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18