74LVX3245QSC_NL - Fairchild Semiconductor

July 1993

Revised September 2003

74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74LVX3245

8-Bit Dual Supply Translating Transceiver with

3-STATE Outputs

General Description

The LVX3245 is a du al-supp ly, 8-bit tr ansl ating transcei ver

that is designed to interface between a 3V bus and a 5V

bus in a mixed 3V/5V supply environment. The Transmit/

Receive (T/R) input determines the direction of data flow.

Transmit (active-HIGH) enables data from A Ports to B

Ports; R eceive (ac tive-LOW ) enable s data fro m B Ports to

A Ports. The Output Enable input, when HIGH, disables

both A and B Ports by placing them in a high impedance

condition. The A Port interfaces with the 3V bus; the B Port

interfaces with the 5V bus.

The LVX3245 is suitable for mixed voltage applications

such as notebook computers using 3.3V CPU and 5V

peripheral components.

Features

■Bidirectional interface between 3V and 5V buses

■Inputs compatible with TTL level

■3V data flow at A Port and 5V data flow at B Port

■Outputs source/sink 24 mA

■Guaranteed simultaneous switching noise level and

dynamic thresh ol d per for man ce

■Implements proprietary EMI reduction circuitry

■Functionally compatible with the 74 series 245

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing suffix lette r “X” to the ordering co de.

Logic Symbol

Pin Descriptions

Connection Diagram

Order Number Package Number Package Description

74LVX3245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVX3245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

74LVX3245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

OE Output Enable Input

T/R Tr ansmit/Receive Input

A0–A7Side A Inputs or 3-STATE Outputs

B0–B7Side B Inputs or 3-STATE Outputs

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74LVX3245

Tr uth Table

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Immaterial

Logic Diagram

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

HXHIGH-Z State

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74LVX3245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: The “Absolute Maximum Ratings” are those val ues beyond w hich

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristi c s tables are not guar anteed at t he ab s olute maxi m um r atings.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: Unused Pi ns (inputs an d I/Os) mu st be held HIGH or LO W. T hey

may not float.

DC Electrical Characteristics

Supply Voltage (VCCA, VCCB)−0.5V to +7.0V

DC Input Voltage (VI) @ OE, T/R −0.5V to VCCA + 0.5V

DC Input/Output Voltage (VI/O)

@ An−0.5V to VCCA + 0.5 V

@ Bn−0.5V to VCCB + 0.5 V

DC Input Diode Current (IIN)

@ OE, T/R ±20 mA

DC Output Diode Current (IOK)±50 mA

DC Output Source or

Sink Curr en t (IO)±50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)±50 mA

and Max Current @ ICCA ±100 mA

@ ICCB ±2 00 mA

Storage Temperature Range (TSTG)−65°C to +150°C

DC Latch-Up Source or

Sink Curr en t ±300 mA

Supply Voltage

VCCA 2.7V to 3.6V

VCCB 4.5V to 5.5V

Input Voltage (VI) @ OE, T/R 0V to VCCA

Input/Output Voltage (VI/O)

@ An0V to VCCA

@ Bn0V to VCCB

Free Air Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆t/∆V) 8 ns/V

VIN from 30% to 70% of VCC

VCC @ 3.0V, 4.5V, 5.5V

Symbol Parameter VCCA VCCB TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

VIHA Minimum HIGH Level An, T/R, 3.6 5.0 2.0 2.0

Input Voltage OE 2.7 5.0 2.0 2.0 VOUT ≤ 0.1V or

VIHB Bn3.3 4.5 2.0 2.0 ≥ VCC − 0.1V

3.3 5.5 2.0 2.0

VILA Maximum LOW Level An, T/R, 3.6 5.0 0.8 0.8

Input Voltage OE 2.7 5.0 0.8 0.8 VOUT ≤ 0.1V or

VILB Bn3.3 4.5 0.8 0.8 ≥ VCC −0.1V

3.3 5.5 0.8 0.8

VOHA Minimum HIGH Level 3.0 4.5 2.99 2.9 2.9

IOUT = −100 µA

Output Voltage 3.0 4.5 2.65 2.35 2.25 IOH = −24 mA

2.7 4.5 2.5 2.3 2.2 IOH = −12 mA

2.7 4.5 2.3 2.1 2.0 IOH = −24 mA

VOHB 3.0 4.5 4.5 4.4 4.4 VIOUT = −100 µA

3.0 4.5 4.25 3.86 3.76 IOH = −24 mA

VOLA Maximum LOW Level 3.0 4.5 0.002 0.1 0.1

IOUT =100 µA

Output Voltage 3.0 4.5 0.21 0.36 0.44 IOL = 24 mA

2.7 4.5 0.11 0.36 0.44 IOL = 12 mA

2.7 4.5 0.22 0.42 0.5 IOL = 24 mA

VOLB 3.0 4.5 0.002 0.1 0.1 VIOUT = 100 µA

3.0 4.5 0.18 0.36 0.44 IOL = 24 mA

IIN Maximum Input

Leakage Current 3.6 5.5 ±0.1 ±1.0 µAV

I = VCCB, GND

@ OE, T/R

IOZA Maximum 3-STATE VI = VIL, VIH

Output Leakage 3.6 5.5 ±0.5 ±5.0 µAOE = VCCA

@ AnVO = VCCA, GND

IOZB Maximum 3-STATE VI = VIL, VIH

Output Leakage 3.6 5.5 ±0.5 ±5.0 µAOE = VCCA

@ BnVO = VCCB, GND

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74LVX3245

DC Electrical Characteristi cs (Continued)

Note 3: Worst case package.

Note 4: Max num ber of outputs defined as (n). D at a inputs ar e driven 0V t o VCC level; one output at GND .

Note 5: Max num ber of Dat a In puts (n) sw it c hing. (n−1) inputs switching 0V to VCC level. I nput-under-test s w it c hing:

VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.

AC Electrical Characteristi cs

Note 6: Voltage Range 3.3V is 3.3V ± 0.3V.

Note 7: Voltage Range 5.0V is 5.0V ± 0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specif ic ation applies to any out pu ts switching in the same directio n, eit her HIGH-t o-LOW (tOSHL) or LOW-to-HI GH (t OSLH). Parameter guaranteed by design.

Symbol Parameter VCCA VCCB TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Gu ar anteed Limits

∆ICC Maximum Bn3.6 5.5 1.0 1.35 1.5 mA VI = VCCB − 2.1V

ICCT/Input @ An, T/R,3.6 5.5 0.35 0.5 mA VI = VCCA −0.6V

ICCA Quiescent VCCA An = VCCA or GND

Supply Current 3.6 5.5 5 50 µAB

n = VCCB or GND,

OE = GND, T/R = GND

ICCB Quiescent VCCB An = VCCA or GND

Supply Current 3.6 5.5 8 80 µAB

n = VCCB or GND,

OE = GND, T/R = VCCA

VOLPA Quiet Output Maximum 3.3 5.0 0.8 V(Note 3) (Note 4)

VOLPB Dynamic VOL 3.3 5.0 1.5

VOLVA Quiet Output Minimum 3.3 5.0 −0.8 V(Note 3) (Note 4)

VOLVB Dynamic VOL 3.3 5.0 −1.2

VIHDA Minimum HIGH Level 3.3 5.0 2.0 V(Note 3) (Note 5)

VIHDB Dynamic Input Voltage 3.3 5.0 2.0

VILDA Maxi mum LOW Level 3.3 5.0 0.8 V(Note 3) (Note 5)

VILDB Dynamic Input Voltage 3.3 5.0 0.8

Symbol Parameters

TA = +25°CT

A = −40°C to +85°CT

A = −40°C to +85°C

Units

CL = 50 pF CL = 50 pF CL = 50 pF

VCCA = 3.3V (Note 6) VCCA = 3.3V (Note 6) VCCA = 2.7V

VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7)

Min Typ Max Min Max Min Max

tPHL Propagation Delay 1.0 5.4 8.0 1.0 8.5 1.0 9.0 ns

tPLH A to B 1.0 5.6 7.5 1.0 8.0 1.0 8.5

tPHL Propagation Delay 1.0 5.1 7.5 1.0 8.0 1.0 8.5 ns

tPLH B to A 1.0 5.7 7.5 1.0 8.0 1.0 8.5

tPZL Output Enable 1.0 4.8 8.0 1.0 8.5 1.0 9.0 ns

tPZH Time OE to B 1.0 6.3 8.5 1.0 9.0 1.0 9.5

tPZL Output Enable 1.0 6.3 8.5 1.0 9.0 1.0 9.5 ns

tPZH Time OE to A 1.0 6.8 9.0 1.0 9.5 1.0 10.0

tPHZ Output Disable 1.0 5.3 7.5 1.0 8.0 1.0 8.5 ns

tPLZ Time OE to B 1.0 4.2 7.0 1.0 7.5 1.0 8.0

tPHZ Output Disable 1.0 5.3 8.0 1.0 8.5 1.0 9.0 ns

tPLZ Time OE to A 1.0 3.7 6.5 1.0 7.0 1.0 7.5

tOSHL Output to Output

tOSLH Skew (Note 8) 1.0 1.5 1.5 1.5 ns

Data to Output

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74LVX3245

Capacitance

Note 9: CPD is measured at 10 MHz

8-Bit Dual Supply Translating Transceiver

The LVX3245 is a dual supply device capable of bidirec-

tional signal translation. This level shifting ability provides

an efficient interface between low voltage CPU local bus

with memo ry and a standar d bus defined by 5V I/O levels.

The device control inputs can be controlled by either the

low vol tage CPU an d core logi c or a bus arbitra tor w ith 5V

I/O levels.

Manufactured on a sub-micron CMOS process, the

LVX3245 is ideal for mixed voltage applications such as

notebook computers using 3.3V CPU’s and 5V peripheral

devices.

Power Up Considerations

To insure that the system does not experience unneces-

sary ICC curre n t dr aw, bus cont e nt io n, or os ci l l ati o ns du rin g

power up, the following guidelines should be adhered to

(refer to Table 1):

•Power up the control side of t he device first. This is the

VCCA.

•OE should ramp with or ahead of VCCA. This will help

guar d against bus cont ention.

•The Transmit/Receive control pin (T/R) should ramp with

VCCA, this will ensure that the A Port data pins are con-

figured as inpu ts. Wit h VCCA receiving powe r first, the A

I/O Port should be configured as inputs to help guard

against bus conten tion and oscilla ti on s.

•A side data inp uts sh ould be dr iven to a val id logic l eve l.

This will prevent excessive current draw.

The above steps will ensure that no bus contention or oscil-

lations, and therefore no excessive current draw occurs

during the power up cycli ng of these devices. These steps

will help prevent possible damage t o the t ranslator device s

and potential damage to other system components.

TABLE 1. Low Voltage Translator Power Up Sequencing Table

Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual

Supply CMOS Translating Transceivers.

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = Open

CI/O Input/Output 15 pF VCCA = 3.3V

Capacitance VCCB = 5.0V

CPD Power Dissipation A → B55

pF VCCB = 5.0V

Capacitance (Note 9) B → A40V

CCA = 3.3V

Device Type VCCA VCCB T/R OE A Side I/O B Side I/O Floatable Pin

Allowed

74LVX3245 3V 5V ramp ramp logic outputs No

(power up 1st) configurable with VCCA with VCCA 0V or VCCA

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74LVX3245

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M24B

24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Package Number MQA24

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74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC24

Fairchild does not assume an y responsibility for u se of any circuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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device or system, or to affect its safety or effectiveness.