This is information on a product in full production.
October 2018 DS12470 Rev 2 1/194
STM32L422xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
128KB Flash, 40KB SRAM, analog, AES, ext. SMPS
Datasheet - production data
Features
Ultra-low-power with FlexPowerControl
1.71 V to 3.6 V power supply
-40 °C to 85/125 °C temperature range
300 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
16 nA Shutdown mode (4 wakeup pins)
32 nA Standby mode (4 wakeup pins)
245 nA Standby mode with RTC
0.7 µA Stop 2 mode, 0.95 µA with RTC
79 µA/MHz run mode (LDO Mode)
–28 A/MHz run mode (@3.3 V SMPS
Mode)
Batch acquisition mode (BAM)
4 µs wakeup from Stop mode
Brown out reset (BOR)
Interconnect matrix
Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS and DSP instructions
Performance benchmark
1.25 DMIPS/MHz (Drystone 2.1)
273.55 CoreMark® (3.42 CoreMark/MHz @
80 MHz)
Energy benchmark
442 ULPMark-CP®
165 ULPMark-PP®
Clock Sources
4 to 48 MHz crystal oscillator
32 kHz crystal oscillator for RTC (LSE)
Internal 16 MHz factory-trimmed RC (±1%)
Internal low-power 32 kHz RC (±5%)
Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
Internal 48 MHz with clock recovery
PLL for system clock
Up to 52 fast I/Os, most 5 V-tolerant
RTC with HW calendar, alarms and calibration
Up to 12 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
10x timers: 1x 16-bit advanced motor-control,
1x 32-bit and 2x 16-bit general purpose, 1x 16-
bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
Memories
128 KB single bank Flash, proprietary code
readout protection
40 KB of SRAM including 8 KB with
hardware parity check
Quad SPI memory interface with XIP
capability
Rich analog peripherals (independent supply)
2x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
2x operational amplifiers with built-in PGA
1x ultra-low-power comparator
Accurate 2.5 V or 2.048 V reference
voltage buffered output
AES: 128/256-bit key encryption hardware
accelerator
12x communication interfaces
USB 2.0 full-speed crystal less solution
with LPM and BCD
–3x I2C FM+(1 Mbit/s), SMBus/PMBus
3x USARTs (ISO 7816, LIN, IrDA, modem)
1x LPUART (Stop 2 wake-up)
2x SPIs (and 1x Quad SPI)
IRTIM (Infrared interface)
LQFP32 (7x7) UFBGA64 (5x5) WLCSP36
UFQFPN32 (5x5)
UFQFPN48 (7x7)
LQFP64 (10x10)
LQFP48 (7x7)
www.st.com
STM32L422xx
2/194 DS12470 Rev 2
14-channel DMA controller
True random number generator
CRC calculation unit, 96-bit unique ID
Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
All packages are ECOPACK2® compliant
Table 1. Device summary
Reference Part numbers
STM32L422xx STM32L422CB, STM32L422KB, STM32L422RB, STM32L422TB
DS12470 Rev 2 3/194
STM32L422xx Contents
6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 19
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 36
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 36
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Contents STM32L422xx
4/194 DS12470 Rev 2
3.17 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.18 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.19 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.20 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 40
3.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.21.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.21.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 42
3.21.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.21.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 42
3.21.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.21.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.21.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.21.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.22 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 44
3.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.24 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.25 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.26 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.27 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.28 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.29 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.30 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.30.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.30.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DS12470 Rev 2 5/194
STM32L422xx Contents
6
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 80
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 80
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 138
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 139
6.3.19 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.20 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.24 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 158
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
7.2 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.5 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Contents STM32L422xx
6/194 DS12470 Rev 2
7.6 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.7 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 189
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DS12470 Rev 2 7/194
STM32L422xx List of tables
9
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32L422xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17
Table 4. STM32L422xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. STM32L422xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. STM32L422xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. STM32L422xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 15. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 16. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 17. STM32L422xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 71
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 24. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 25. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 86
Table 26. Current consumption in Run modes, code with data processing running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 28. Current consumption in Run modes, code with data processing running from Flash,
ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . 89
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 30. Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . 91
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 92
Table 32. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 33. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.00 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 34. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 35. Typical current consumption in Run modes, with different codes running from
List of tables STM32L422xx
8/194 DS12470 Rev 2
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . 94
Table 36. Typical current consumption in Run modes, with different codesrunning from
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V). . . . . . . . . 95
Table 37. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 38. Typical current consumption in Run, with different codesrunning from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . 96
Table 39. Typical current consumption in Run, with different codesrunning from
SRAM1 and power supplied by external SMPS (VDD12 = 1.00 V) . . . . . . . . . . . . . . . . . . 96
Table 40. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 97
Table 41. Current consumption in Sleep, Flash ON and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 42. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . . 98
Table 43. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 44. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 45. Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 46. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 47. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 48. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 49. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 50. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 51. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 52. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 53. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 54. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 55. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 56. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 57. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 58. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Table 59. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 60. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 61. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 62. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 63. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 64. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 65. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 66. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 67. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 68. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 69. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 70. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 71. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 72. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 73. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 74. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 75. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 76. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 77. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 78. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 79. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 80. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 81. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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9
Table 82. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 83. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 84. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 85. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 86. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 87. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 88. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 89. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 90. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 91. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 92. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 93. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 94. LQFP - 64 pins, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 95. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 96. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 170
Table 97. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 98. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 99. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 100. WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 101. UFQFPN - 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 102. LQFP - 32 pins, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 103. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 104. STM32L422xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 105. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
List of figures STM32L422xx
10/194 DS12470 Rev 2
List of figures
Figure 1. STM32L422xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5. STM32L422Vx, external SMPS device, LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 6. STM32L422Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 7. STM32L422Rx, external SMPS, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 8. STM32L422Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 9. STM32L422Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. STM32L422Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11. STM32L422Tx WLCSP36 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. STM32L422Kx LQFP32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13. STM32L422Kx UFQFPN32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14. STM32L422xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 15. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 16. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 17. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 18. Current consumption measurement scheme with and without external
SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 19. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 24. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 25. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 26. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 27. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 28. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 29. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 30. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 31. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 32. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 34. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 35. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 36. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 37. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 166
Figure 38. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 39. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 40. LQFP64, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . . 168
Figure 41. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 42. UFBGA64 – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 43. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 44. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . 172
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11
Figure 45. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 46. LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 47. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 48. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 49. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 50. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 51. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 52. WLCSP36 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 53. UFQFPN - 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 54. UFQFPN - 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 55. UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 56. LQFP - 32 pins, 7 x 7 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . 185
Figure 57. LQFP - 32 pins, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 58. LQFP32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Introduction STM32L422xx
12/194 DS12470 Rev 2
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L422xx microcontrollers.
This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx
reference manual (RM0394). The reference manual is available from the
STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12470 Rev 2 13/194
STM32L422xx Description
50
2 Description
The STM32L422xx devices are the ultra-low-power microcontrollers based on the high-
performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.
The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all
Arm® single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU) which enhances application
security.
The STM32L422xx devices embed high-speed memories (Flash memory up to 128
Kbyte,40 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages)
and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two
AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L422xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer two fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,
a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to
motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers.
In addition, up to 12 capacitive sensing channels are available.
They also feature standard and advanced communication interfaces.
Three I2Cs
Two SPIs
Three USARTs and one Low-Power UART.
One USB full-speed device crystal less
The STM32L422xx devices embed AES hardware accelerator.
The STM32L422xx operates in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using
internal LDO regulator and a 1.00 to 1.32V VDD12 power supply when using external SMPS
supply. A comprehensive set of power-saving modes allows the design of low-power
applications.
Some independent power supplies are supported: analog independent supply input for
ADC, OPAMP and comparator. A VBAT input allows to backup the RTC and backup
registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO
regulator when connected to an external SMPS.
The STM32L422xx family offers six packages from 32 to 64-pin packages.
Table 2. STM32L422xx family device features and peripheral counts
Peripheral STM32L422Rx STM32L422Cx STM32L422Tx STM32L422Kx
Flash memory 128KB
SRAM 40KB
Quad SPI Yes
Description STM32L422xx
14/194 DS12470 Rev 2
Timers
Advanced
control 1 (16-bit)
General
purpose
2 (16-bit)
1 (32-bit)
Basic 1 (16-bit)
Low -power 2 (16-bit)
SysTick timer 1
Watchdog
timers
(independent,
window)
2
Comm.
interfaces
SPI 2 1
I2C3 2
USART
LPUART
3
1
2
1
USB FS Yes
RTC Yes
Tamper pins 2 2 1
AES Yes
Random generator Yes
GPIOs(1)
Wakeup pins
52
4
38
3
30
2
26
2
Capacitive sensing
Number of channels 12 6 2
12-bit ADC
Number of channels
2
16
2
10
2
10
2
10
Internal voltage reference
buffer No
Analog comparator 1
Operational amplifiers 1
Max. CPU frequency 80 MHz
Operating voltage (VDD) 1.71 to 3.6 V
Operating voltage (VDD12) 1.00 to 1.32 V
Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 130 °C
Packages LQFP64
UFBGA64
LQFP48
UFQFPN48 WLCSP36 UFQFPN32
LQFP32
1. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies
hence reducing the number of available GPIO's by 2.
Table 2. STM32L422xx family device features and peripheral counts (continued)
Peripheral STM32L422Rx STM32L422Cx STM32L422Tx STM32L422Kx
DS12470 Rev 2 15/194
STM32L422xx Description
50
Figure 1. STM32L422xx block diagram
Note: AF: alternate function on I/O pins.
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Functional overview STM32L422xx
16/194 DS12470 Rev 2
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm® core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32L422xx family is compatible with all Arm® tools
and software.
Figure 1 shows the general block diagram of the STM32L422xx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS12470 Rev 2 17/194
STM32L422xx Functional overview
50
3.4 Embedded Flash memory
STM32L422xx devices feature up to 128Kbyte of embedded Flash memory available for
storing programs and data in single bank architecture.The Flash memory contains 64 pages
of 2 Kbyte
Flexible protections can be configured thanks to option bytes:
Readout protection (RDP) to protect the whole memory. Three levels are available:
Level 0: no readout protection
Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 2-Kbyte granularity.
Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)
allows to select if the PCROP area is erased or not when the RDP protection is
changed from Level 1 to Level 0.
Table 3. Access status versus readout protection level and execution modes
Area Protection
level
User execution Debug, boot from RAM or boot
from system memory (loader)
Read Write Erase Read Write Erase
Main
memory
1 Yes Yes Yes No No No
2 Yes Yes Yes N/A N/A N/A
System
memory
1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
Option
bytes
1 Yes Yes Yes Yes Yes Yes
2 Yes No No N/A N/A N/A
Backup
registers
1YesYesN/A
(1)
1. Erased when RDP change from Level 1 to Level 0.
No No N/A(1)
2 Yes Yes N/A N/A N/A N/A
SRAM2
1 Yes Yes Yes(1) No No No(1)
2 Yes Yes Yes N/A N/A N/A
Functional overview STM32L422xx
18/194 DS12470 Rev 2
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
single error detection and correction
double error detection.
The address of the ECC fail can be read in the ECC register
3.5 Embedded SRAM
STM32L422xx devices feature 40 Kbyte of embedded SRAM. This SRAM is split into two
blocks:
32 Kbyte mapped at address 0x2000 0000 (SRAM1)
8 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2000 8000, offering a contiguous address
space with the SRAM1 (8 Kbyte aliased by bit band)
This block is accessed through the ICode/DCode buses for maximum performance.
These 8 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
Three segments can be protected and defined thanks to the Firewall registers:
Code segment (located in Flash or SRAM1 if defined as executable protected
area)
Non-volatile data segment (located in Flash)
Volatile data segment (located in SRAM1)
The start address and the length of each segments are configurable:
Code segment: up to 1024 Kbyte with granularity of 256 bytes
Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes
Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
Volatile data segment can be shared or not with the non-protected code
Volatile data segment can be executed or not depending on the Firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
DS12470 Rev 2 19/194
STM32L422xx Functional overview
50
3.7 Boot modes
At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select
one of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
A Flash empty check mechanism is implemented to force the boot from system flash if the
first flash memory location is not programmed and if the boot selection is configured to boot
from main flash.
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI or USB FS in Device mode through DFU (device firmware upgrade).
3.8 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9 Power supply management
3.9.1 Power supply schemes
VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
VDD12 = 1.00 to 1.32 V: external power supply bypassing internal regulator when
connected to an external SMPS. It is provided externally through VDD12 pins and only
available on packages with the external SMPS supply option. VDD12 does not require
any external decoupling capacitance and cannot support any external load.
VDDA = 1.62 V (ADC/COMP) / 1.8 (OPAMP) to 3.6 V: external analog power supply for
ADC, OPAMP, Comparator. The VDDA voltage level is independent from the VDD
voltage.
VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage.
VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted
to VDD.
Functional overview STM32L422xx
20/194 DS12470 Rev 2
Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant.
Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with
VDDIO1 = VDD.
Figure 2. Power supply overview
During power-up and power-down phases, the following power sequence requirements
must be respected:
When VDD is below 1 V, other power supplies (VDDAVDDUSB) must remain below VDD +
300 mV.
When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power-down transient
phase.
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STM32L422xx Functional overview
50
Figure 3. Power-up/down sequence
1. VDDX refers to any power supply among VDDA, VDDUSB.
3.9.2 Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltage VDDA with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
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Functional overview STM32L422xx
22/194 DS12470 Rev 2
3.9.3 Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 8 Kbyte SRAM2 in Standby with SRAM2 retention.
Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L422xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
Range 1 with the CPU running at up to 80 MHz.
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
3.9.4 Low-power modes
The ultra-low-power STM32L422xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
STM32L422xx Functional overview
DS12470 Rev 2 23/194
Table 4. STM32L422xx modes overview
Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
Run
MR range 1
Yes O N(4) ON Any
All
N/A
91 µA/MHz
N/A
SMPS range 2 high 34 µA/MHz
MR range2
All except USB_FS, RNG
79 µA/MHz
SMPS range 2 low 28 µA/MHz
LPRun LPR Yes ON(4) ON
Any
except
PLL
All except USB_FS, RNG N/A 83 µA/MHz to Range 1: 4 µs
to Range 2: 64 µs
Sleep
MR range 1
No ON(4) ON(5) Any
All
Any interrupt or
event
21 µA/MHz
6 cycles
SMPS range 2 high 7.5 µA/MHz
MR range2
All except USB_FS, RNG
20 µA/MHz
SMPS range 2 low 7 µA/MHz
LPSleep LPR No ON(4) ON(5)
Any
except
PLL
All except USB_FS, RNG Any interrupt or
event 83 µA/MHz 6 cycles
Stop 0
MR Range 1
No OFF ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMP1, OPAMP1
USARTx (x=1...3)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMP1
USARTx (x=1...3)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
USB_FS(8)
105 µA 2.47 µs in SRAM
4.1 µs in Flash
MR Range 2
Functional overview STM32L422xx
24/194 DS12470 Rev 2
Stop 1 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMP1, OPAMP1
USARTx (x=1...3)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMP1
USARTx (x=1...3)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
USB_FS(8)
3.25 µA w/o RTC
3.65 µA w RTC
5.7 µs in SRAM
7 µs in Flash
Stop 2 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMP1
I2C3(7)
LPUART1(6)
LPTIMx (x = 1, 2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMP1
I2C3(7)
LPUART1(6)
LPTIMx (x = 1, 2)
710 nA w/o RTC
950 nA w RTC
5.8 µs in SRAM
8.3 µs in Flash
Table 4. STM32L422xx modes overview (continued)
Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
STM32L422xx Functional overview
DS12470 Rev 2 25/194
Standby
LPR
Power
ed Off Off
SRAM
2 ON
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-down
Reset pin
5 I/Os (WKUPx)(9)
BOR, RTC, IWDG
195 nA
16.1 µs
OFF
Power
ed
Off
105 nA
Shutdown OFF Power
ed Off Off
Power
ed
Off
LSE
RTC
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-
down(10)
Reset pin
5 I/Os (WKUPx)(9)
RTC
18 nA 256 µs
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. The SRAM1 and SRAM2 clocks can be gated on or off independently.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
Table 4. STM32L422xx modes overview (continued)
Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
Functional overview STM32L422xx
26/194 DS12470 Rev 2
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low-
power run mode.
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
DS12470 Rev 2 27/194
STM32L422xx Functional overview
50
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
Functional overview STM32L422xx
28/194 DS12470 Rev 2
Table 5. Functionalities depending on the working mode(1)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
CPU Y - Y - - --------
Flash memory (up to
128 KB) O(2) O(2) O(2) O(2) ---------
SRAM1 (32 KB) Y Y(3) YY
(3) Y-Y------
SRAM2 (8 KB) Y Y(3) YY
(3) Y-Y-O
(4) ----
Quad SPI O O O O - --------
Backup Registers Y Y Y Y Y -Y-Y-Y-Y
Brown-out reset
(BOR) YYYYYYYYYY- --
Programmable
Voltage Detector
(PVD)
OOOOO
OOO- ----
Peripheral Voltage
Monitor (PVMx;
x=1,3,4)
OOOOO
OOO- ----
DMA OOOO-
--------
High Speed Internal
(HSI16) OOOO
(5) -(5) ------
Oscillator RC48 O O - - - --------
High Speed External
(HSE) OOOO-
--------
Low Speed Internal
(LSI) OOOOO
-O-O----
Low Speed External
(LSE) OOOOO
-O-O-O-O
Multi-Speed Internal
(MSI) OOOO-
--------
Clock Security
System (CSS) OOOO-
--------
Clock Security
System on LSE OOOOO
OOOOO- --
RTC / Auto wakeup O O O O O OOOOOOOO
Number of RTC
Tamper pins 22222O2O2O2O2
USARTx (x=1,2,3) O O O O O(6) O(6) -------
DS12470 Rev 2 29/194
STM32L422xx Functional overview
50
Low-power UART
(LPUART) OOOOO
(6) O(6) O(6) O(6) -----
I2Cx (x=1,2) O O O O O(7) O(7) -------
I2C3 OOOOO
(7) O(7) O(7) O(7) -----
SPIx (x=1,2) O O O O - --------
ADCx (x=1,2) O O O O - --------
OPAMPx (x=1) O O O O O --------
COMP1 OOOOO
OOO- ----
Temperature sensor O O O O - --------
Timers (TIMx) O O O O - --------
Low-power timer 1
(LPTIM1) OOOOO
OOO- ----
Low-power timer 2
(LPTIM2) OOOOO
OOO- ----
Independent
watchdog (IWDG) OOOOO
OOOOO- --
Window watchdog
(WWDG) OOOO-
--------
SysTick timer O O O O - --------
Touch sensing
controller (TSC) OOOO-
--------
Random number
generator (RNG) O(8) O(8) -----------
CRC calculation unit O O O O - --------
GPIOs OOOOO
OOO(9)
4
pins
(10)
(11)
4
pins
(10)
-
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame
event.
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
Functional overview STM32L422xx
30/194 DS12470 Rev 2
3.9.5 Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.6 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present. The VBAT pin supplies the RTC with LSE and the backup registers. Two anti-
tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
3.10 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Table 6. STM32L422xx peripherals interconnect matrix
Interconnect source Interconnect
destination Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
TIMx
TIMx Timers synchronization or chaining Y Y Y Y - -
ADCx Conversion triggers Y Y Y Y - -
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -
DS12470 Rev 2 31/194
STM32L422xx Functional overview
50
TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - -
COMPx
TIM1
TIM2
Timer input channel, trigger, break from
analog signals comparison YYYY - -
LPTIMERx Low-power timer triggered by analog
signals comparison YYYYYY
ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -
RTC
TIM16 Timer input channel from RTC events Y Y Y Y - -
LPTIMERx Low-power timer triggered by RTC alarms
or tampers YYYYYY
All clocks sources (internal
and external)
TIM2
TIM15, 16
Clock source used as input channel for
RC measurement and trimming YYYY - -
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
PVD
TIM1
TIM15,16 Timer break Y Y Y Y - -
GPIO
TIMx External trigger Y Y Y Y - -
LPTIMERx External trigger Y Y Y Y Y Y
ADCx Conversion external trigger Y Y Y Y - -
Table 6. STM32L422xx peripherals interconnect matrix (continued)
Interconnect source Interconnect
destination Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
Functional overview STM32L422xx
32/194 DS12470 Rev 2
3.11 Clocks and startup
The clock controller (see Figure 4) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be
used to drive the USB or the RNG peripherals. This clock can be output on the MCO.
Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
Peripheral clock sources: Several peripherals (RNG, USARTs, I2Cs, LPTimers) have
their own independent clock whatever the system clock. PLL having three independent
outputs allowing the highest flexibility, can generate independent clocks for the RNG.
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
DS12470 Rev 2 33/194
STM32L422xx Functional overview
50
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
Clock-out capability:
MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSI, LSE) are available
down to Stop 1 low power state.
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
LSCO is not available in VBAT mode.
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 80 MHz.
Functional overview STM32L422xx
34/194 DS12470 Rev 2
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DS12470 Rev 2 35/194
STM32L422xx Functional overview
50
3.12 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13 Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, each dedicated to managing memory
access requests from one or more peripherals. Each has an arbiter for handling the priority
between DMA requests.
The DMA supports:
14 independently configurable channels (requests)
Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
Support for circular buffer management
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
Memory-to-memory transfer
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536.
Table 7. DMA implementation
DMA features DMA1 DMA2
Number of regular channels 7 7
Functional overview STM32L422xx
36/194 DS12470 Rev 2
3.14 Interrupts and events
3.14.1 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4.
The NVIC benefits are the following:
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 37 edge detector lines used to generate
interrupt/event requests and wake-up the system from Stop mode. Each external line can be
independently configured to select the trigger event (rising edge, falling edge, both) and can
be masked independently. A pending register maintains the status of the interrupt requests.
The internal lines are connected to peripherals with wakeup from Stop mode capability. The
EXTI can detect an external line with a pulse width shorter than the internal clock period. Up
to 52 GPIOs can be connected to the 16 external interrupt lines.
DS12470 Rev 2 37/194
STM32L422xx Functional overview
50
3.15 Analog to digital converter (ADC)
The device embeds 2 successive approximation analog-to-digital converter with the
following features:
12-bit native resolution, with built-in calibration
5.33 Msps maximum conversion rate with full resolution
Down to 18.75 ns sampling time
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
Up to 16 external channels, some of them shared between ADC1 and ADC2.
3 internal channels: internal reference voltage, temperature sensor, VBAT/3.
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
Single-ended and differential mode inputs
Low-power design
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
Dual clock domain architecture: ADC speed independent from CPU frequency
Highly versatile digital interface
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
Handles two ADC converters for dual mode operation (simultaneous or
interleaved sampling modes)
Each ADC supports multiple trigger inputs for synchronization with on-chip timers
and external signals
Results stored into 2 data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.15.1 Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
Functional overview STM32L422xx
38/194 DS12470 Rev 2
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.15.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
3.15.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be
higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally
connected to a bridge divider by 3. As a consequence, the converted digital value is one
third the VBAT voltage.
3.16 Comparators (COMP)
The STM32L422xx devices embed one rail-to-rail comparator with programmable reference
voltage (internal or external), hysteresis and speed (low speed for low-power) and with
selectable output polarity.
The reference voltage can be one of the following:
External I/O
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
Table 8. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75A8 - 0x1FFF 75A9
TS_CAL2
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75CA - 0x1FFF 75CB
Table 9. Internal voltage reference calibration values
Calibration value name Description Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
DS12470 Rev 2 39/194
STM32L422xx Functional overview
50
3.17 Operational amplifier (OPAMP)
The STM32L422xx embeds one operational amplifier with external or internal follower
routing and PGA capability.
The operational amplifier features:
Low input bias current
Low offset voltage
Low-power mode
Rail-to-rail input
3.18 Touch sensing controller (TSC)
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (glass,
plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
Proven and robust surface charge transfer acquisition principle
Supports up to 12 capacitive sensing channels
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
Spread spectrum feature to improve system robustness in noisy environments
Full hardware management of the charge transfer acquisition sequence
Programmable charge transfer frequency
Programmable sampling capacitor I/O pin
Programmable channel I/O pin
Programmable max count value to avoid long acquisition when a channel is faulty
Dedicated end of acquisition and max count error flags with interrupt capability
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.19 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
Functional overview STM32L422xx
40/194 DS12470 Rev 2
3.20 Advanced encryption standard hardware accelerator (AES)
The devices embed an AES hardware accelerator can be used to both encipher and
decipher data using AES algorithm.
The AES peripheral supports:
Encryption/Decryption using AES Rijndael Block Cipher algorithm
NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
32-bit registers)
Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois
Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher
Message Authentication Code mode (CMAC) supported.
Key scheduler
Key derivation for decryption
128-bit data block processing
128-bit, 256-bit key length
1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.
Register access supporting 32-bit data width only.
One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode.
Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data.
Suspend a message if another message with a higher priority needs to be processed
3.21 Timers and watchdogs
The STM32L422xx includes one advanced control timers, up to five general-purpose timers,
two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table
below compares the features of the advanced control, general purpose and basic timers.
Table 10. Timer feature comparison
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advanced
control TIM1 16-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 3
General-
purpose TIM2 32-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 No
General-
purpose TIM15 16-bit Up
Any integer
between 1
and 65536
Yes 2 1
DS12470 Rev 2 41/194
STM32L422xx Functional overview
50
3.21.1 Advanced-control timer (TIM1)
The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers. The 4 independent
channels can be used for:
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.21.2) using the same architecture, so the advanced-control timer can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
General-
purpose TIM16 16-bit Up
Any integer
between 1
and 65536
Yes 1 1
Basic TIM6 16-bit Up
Any integer
between 1
and 65536
Yes 0 No
Table 10. Timer feature comparison (continued)
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Functional overview STM32L422xx
42/194 DS12470 Rev 2
3.21.2 General-purpose timers (TIM2, TIM15, TIM16)
There are up to three synchronizable general-purpose timers embedded in the
STM32L422xx (see Table 10 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
TIM2
It is a full-featured general-purpose timers:
TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
This timers feature 4 independent channels for input capture/output compare, PWM or
one-pulse mode output. They can work with the other general-purpose timers via the
Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoder.
TIM15 and 16
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
TIM15 has 2 channels and 1 complementary channel
TIM16 has 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.21.3 Basic timer (TIM6)
The basic timer can be used as generic 16-bit timebase.
3.21.4 Low-power timer (LPTIM1 and LPTIM2)
The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
Both LPTIM1 and LPTIM2 are active in Stop 0, Stop 1 and Stop 2 modes.
This low-power timer supports the following features:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
Programmable digital glitch filter
Encoder mode (LPTIM1 only)
DS12470 Rev 2 43/194
STM32L422xx Functional overview
50
3.21.5 Infrared interface (IRTIM)
The STM32L422xx includes one infrared interface (IRTIM). It can be used with an infrared
LED to perform remote control functions. It uses TIM15 and TIM16 output channels to
generate output signal waveforms on IR_OUT pin.
3.21.6 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.21.7 System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.21.8 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
Functional overview STM32L422xx
44/194 DS12470 Rev 2
3.22 Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Two anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
DS12470 Rev 2 45/194
STM32L422xx Functional overview
50
3.23 Inter-integrated circuit interface (I2C)
The device embeds three I2C. Refer to Table 11: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
I2C-bus specification and user manual rev. 5 compatibility:
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Address resolution protocol (ARP) support
SMBus alert
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 4: Clock tree.
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features(1)
1. X: supported
I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X
Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup from Stop 1 mode on address match X X X
Wakeup from Stop 2 mode on address match - - X
Functional overview STM32L422xx
46/194 DS12470 Rev 2
3.24 Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32L422xx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
10Mbit/s.
USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and
SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake
up events from Stop mode are programmable and can be:
Start bit detection
Any received data frame
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 12. STM32L422xx USART/UART/LPUART features
USART modes/features(1)
1. X = supported.
USART1 USART2 USART3 LPUART1
Hardware flow control for modem X X X X
Continuous communication using DMA X X X X
Multiprocessor communication X X X X
Synchronous mode X X X -
Smartcard mode X X X -
Single-wire half-duplex communication X X X X
IrDA SIR ENDEC block X X X -
LIN mode X X X -
Dual clock domain X X X X
Wakeup from Stop 0 / Stop 1 modes X X X X
Wakeup from Stop 2 mode - - - X
Receiver timeout interrupt X X X -
Modbus communication X X X -
Auto baud rate detection X (4 modes) -
Driver Enable X X X X
LPUART/USART data length 7, 8 and 9 bits
DS12470 Rev 2 47/194
STM32L422xx Functional overview
50
3.25 Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
Start bit detection
Any received data frame
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
Functional overview STM32L422xx
48/194 DS12470 Rev 2
3.26 Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.27 Universal serial bus (USB)
The STM32L422xx devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.
It requires a precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in
automatic trimming mode. The synchronization for this oscillator can be taken from the USB
data stream itself (SOF signalization) which allows crystal less operation.
3.28 Clock recovery system (CRS)
The STM32L422xx devices embed a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from LSE oscillator, from an external signal on CRS_SYNC
pin or generated by user software. For faster lock-in during startup it is also possible to
combine automatic trimming with manual trimming action.
3.29 Quad SPI memory interface (QUADSPI)
The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
Indirect mode: all the operations are performed using the QUADSPI registers
Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad SPI flash memories are accessed simultaneously.
DS12470 Rev 2 49/194
STM32L422xx Functional overview
50
The Quad SPI interface supports:
Three functional modes: indirect, status-polling, and memory-mapped
Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
flash memories in parallel.
SDR and DDR support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Programmable masking for external flash flag management
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
Functional overview STM32L422xx
50/194 DS12470 Rev 2
3.30 Development support
3.30.1 Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.30.2 Embedded Trace Macrocell™
The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L422xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell™ operates with third party debugger software tools.
DS12470 Rev 2 51/194
STM32L422xx Pinouts and pin description
73
4 Pinouts and pin description
Figure 5. STM32L422Vx, external SMPS device, LQFP100 pinout(1)
1. The above figure shows the package top view.
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52/194 DS12470 Rev 2
Figure 6. STM32L422Rx LQFP64 pinout(1)
1. The above figure shows the package top view.
Figure 7. STM32L422Rx, external SMPS, LQFP64 pinout(1)
1. The above figure shows the package top view.
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DS12470 Rev 2 53/194
STM32L422xx Pinouts and pin description
73
Figure 8. STM32L422Rx UFBGA64 ballout(1)
1. The above figure shows the package top view.
Figure 9. STM32L422Cx LQFP48 pinout(1)
1. The above figure shows the package top view.
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Pinouts and pin description STM32L422xx
54/194 DS12470 Rev 2
Figure 10. STM32L422Cx UFQFPN48 pinout(1)
1. The above figure shows the package top view.
Figure 11. STM32L422Tx WLCSP36 ballout(1)
1. The above figure shows the package top view.
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DS12470 Rev 2 55/194
STM32L422xx Pinouts and pin description
73
Figure 12. STM32L422Kx LQFP32 pinout(1)
1. The above figure shows the package top view.
Figure 13. STM32L422Kx UFQFPN32 pinout(1)
1. The above figure shows the package top view.
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Pinouts and pin description STM32L422xx
56/194 DS12470 Rev 2
Table 13. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
_f (1) I/O, Fm+ capable
_u (2) I/O, with USB function supplied by VDDUSB
_a (3) I/O, with Analog switch function supplied by VDDA
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 14 are: FT_f, FT_fa.
2. The related I/O structures in Table 14 are: FT_u, FT_fu.
3. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a.
STM32L422xx Pinouts and pin description
DS12470 Rev 2 57/194
Table 14. STM32L422xx pin definitions
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
- - - 1 1 1 1 B2 VBAT S - - - -
- - - 2 2 2 2 A2 PC13 I/O FT - EVENTOUT RTC_TAMP1/RTC_TS/RTC
_OUT1/WKUP2
22B6333 3 A1
PC14-OSC32_IN
(PC14) I/O FT - EVENTOUT OSC32_IN
33C6444 4 B1
PC15-
OSC32_OUT
(PC15)
I/O FT - EVENTOUT OSC32_OUT
- - - 555 5 C1 PH0-OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN
- - - 666 6 D1
PH1-OSC_OUT
(PH1) I/O FT - EVENTOUT OSC_OUT
4 4 D6 7 7 7 7 E1 NRST I/O RST - - -
-----88E3 PC0 I/OFT_fa-
TRACECK, LPTIM1_IN1, I2C3_SCL,
LPUART1_RX, LPTIM2_IN1,
EVENTOUT
ADC12_IN1
-----99E2 PC1 I/OFT_fa-
TRACED0, LPTIM1_OUT, I2C3_SDA,
LPUART1_TX, EVENTOUT ADC12_IN2
-----1010F2 PC2 I/OFT_a- LPTIM1_IN2, SPI2_MISO,
EVENTOUT ADC12_IN3
-----1111G1 PC3 I/OFT_a- LPTIM1_ETR, SPI2_MOSI,
LPTIM2_ETR, EVENTOUT ADC12_IN4
- - - 8 8 12 12 F1 VSSA/VREF- S - - - -
--E6--- - - VREF+ S - - - -
Pinouts and pin description STM32L422xx
58/194 DS12470 Rev 2
- - F6 - - - - - VDDA S - - - -
5 5 - 9 9 13 13 H1 VDDA/VREF+ S - - - -
- - - 101014 14 G2 PA0 I/O FT_a -
TIM2_CH1, USART2_CTS,
COMP1_OUT, TIM2_ETR,
EVENTOUT
OPAMP1_VINP,
COMP1_INM, ADC1_IN5,
RTC_TAMP2/WKUP1
6 6 D5 - - - - - PA0-CK_IN I/O FT_a -
TIM2_CH1, USART2_CTS,
COMP1_OUT, TIM2_ETR,
EVENTOUT
OPAMP1_VINP,
COMP1_INM, ADC1_IN5,
RTC_TAMP2/WKUP1,
CK_IN
7 7 D4 11 11 15 15 H2 PA1 I/O FT_a -
TIM2_CH2, I2C1_SMBA, SPI1_SCK,
USART2_RTS_DE, TIM15_CH1N,
EVENTOUT
OPAMP1_VINM,
COMP1_INP, ADC1_IN6
8 8 E5 12 12 16 16 F3 PA2 I/O FT_a -
TIM2_CH3, USART2_TX,
LPUART1_TX, QUADSPI_BK1_NCS,
TIM15_CH1, EVENTOUT
ADC12_IN7, WKUP4/LSCO
9 9 F5 13 13 17 17 G3 PA3 I/O TT_a -
TIM2_CH4, USART2_RX,
LPUART1_RX, QUADSPI_CLK,
TIM15_CH2, EVENTOUT
OPAMP1_VOUT,
ADC12_IN8
-----1818C2 VSS S - - - -
-----1919D2 VDD S - - - -
10 10 F4 14 14 20 20 H3 PA4 I/O TT_a SPI1_NSS, USART2_CK,
LPTIM2_OUT, EVENTOUT COMP1_INM, ADC12_IN9
11 11 E4 15 15 21 21 F4 PA5 I/O TT_a TIM2_CH1, TIM2_ETR, SPI1_SCK,
LPTIM2_ETR, EVENTOUT COMP1_INM, ADC12_IN10
Table 14. STM32L422xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
STM32L422xx Pinouts and pin description
DS12470 Rev 2 59/194
12 12 D3 16 16 22 22 G4 PA6 I/O FT_a
TIM1_BKIN, SPI1_MISO,
COMP1_OUT, USART3_CTS,
LPUART1_CTS, QUADSPI_BK1_IO3,
TIM16_CH1, EVENTOUT
ADC12_IN11
13 13 E3 17 17 23 23 H4 PA7 I/O FT_fa TIM1_CH1N, I2C3_SCL, SPI1_MOSI,
QUADSPI_BK1_IO2, EVENTOUT ADC12_IN12
- - - - - 24 24 H5 PC4 I/O FT_a USART3_TX, EVENTOUT COMP1_INM, ADC12_IN13
- - - - - - 25 H6 PC5 I/O FT_a USART3_RX, EVENTOUT COMP1_INP, ADC12_IN14,
WKUP5
14 14 F3 18 18 25 26 F5 PB0 I/O FT_a
TRACED0, TIM1_CH2N, SPI1_NSS,
USART3_CK, QUADSPI_BK1_IO1,
COMP1_OUT, EVENTOUT
ADC12_IN15
15 15 D2 19 19 26 27 G5 PB1 I/O FT_a
TRACED1, TIM1_CH3N,
USART3_RTS_DE,
LPUART1_RTS_DE,
QUADSPI_BK1_IO0, LPTIM2_IN1,
EVENTOUT
COMP1_INM, ADC12_IN16
- - E2 20 20 27 28 G6 PB2 I/O FT_a LPTIM1_OUT, I2C3_SMBA,
EVENTOUT COMP1_INP, RTC_OUT2
- - F2 21 21 28 29 G7 PB10 I/O FT_f
TIM2_CH3, I2C2_SCL, SPI2_SCK,
USART3_TX, LPUART1_RX,
TSC_SYNC, QUADSPI_CLK,
COMP1_OUT, EVENTOUT
-
- - - 222229 30 H7 PB11 I/O FT_f
TIM2_CH4, I2C2_SDA, USART3_RX,
LPUART1_TX, QUADSPI_BK1_NCS,
EVENTOUT
-
-----30- - VDD12 S - - - -
Table 14. STM32L422xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
Pinouts and pin description STM32L422xx
60/194 DS12470 Rev 2
16 16 F1 23 23 31 31 D6 VSS S - - - -
17 17 E1 24 24 32 32 E6 VDD S - - - -
- - - 252533 33 H8 PB12 I/O FT -
TIM1_BKIN, I2C2_SMBA, SPI2_NSS,
USART3_CK, LPUART1_RTS_DE,
TSC_G1_IO1, TIM15_BKIN,
EVENTOUT
-
- - - 262634 34 G8 PB13 I/O FT_f -
TIM1_CH1N, I2C2_SCL, SPI2_SCK,
USART3_CTS, LPUART1_CTS,
TSC_G1_IO2, TIM15_CH1N,
EVENTOUT
-
- - - 272735 35 F8 PB14 I/O FT_f -
TIM1_CH2N, I2C2_SDA, SPI2_MISO,
USART3_RTS_DE, TSC_G1_IO3,
TIM15_CH1, EVENTOUT
-
- - - 282836 36 F7 PB15 I/O FT -
RTC_REFIN, TIM1_CH3N,
SPI2_MOSI, TSC_G1_IO4,
TIM15_CH2, EVENTOUT
-
- - - - - 37 37 F6 PC6 I/O FT - TSC_G4_IO1, EVENTOUT -
- - - - - 38 38 E7 PC7 I/O FT - TSC_G4_IO2, EVENTOUT -
- - - - - 39 39 E8 PC8 I/O FT - TSC_G4_IO3, EVENTOUT -
- - - - - 40 40 D8 PC9 I/O FT - TSC_G4_IO4, USB_NOE, EVENTOUT -
18 18 D1 29 29 41 41 D7 PA8 I/O FT - MCO, TIM1_CH1, USART1_CK,
LPTIM2_OUT, EVENTOUT -
19 19 C1 30 30 42 42 C7 PA9 I/O FT_f - TIM1_CH2, I2C1_SCL, USART1_TX,
TIM15_BKIN, EVENTOUT -
Table 14. STM32L422xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
STM32L422xx Pinouts and pin description
DS12470 Rev 2 61/194
20 20 C2 31 31 43 43 C6 PA10 I/O FT_f - TIM1_CH3, I2C1_SDA, USART1_RX,
USB_CRS_SYNC, EVENTOUT -
21 21 B1 32 32 44 44 C8 PA11 I/O FT_u -
TIM1_CH4, TIM1_BKIN2, SPI1_MISO,
COMP1_OUT, USART1_CTS,
USB_DM, TIM1_BKIN2_COMP1,
EVENTOUT
-
22 22 A1 33 33 45 45 B8 PA12 I/O FT_u -
TIM1_ETR, SPI1_MOSI,
USART1_RTS_DE, USB_DP,
EVENTOUT
-
23 23 B2 34 34 46 46 A8 PA13
(JTMS/SWDIO) I/O FT - JTMS/SWDIO, IR_OUT, USB_NOE,
EVENTOUT -
- - - 353547 47 D5 VSS S - - - -
- - - 36 36 48 48 E5 VDDUSB S - - - -
24 24 A2 37 37 49 49 A7 PA14
(JTCK/SWCLK) I/O FT - JTCK/SWCLK, LPTIM1_OUT,
I2C1_SMBA, EVENTOUT -
25 25 C3 38 38 50 50 A6 PA15 (JTDI) I/O FT -
JTDI, TIM2_CH1, TIM2_ETR,
USART2_RX, SPI1_NSS,
USART3_RTS_DE, TSC_G3_IO1,
EVENTOUT
-
-----5151B7 PC10 I/OFT- TRACED1, USART3_TX,
TSC_G3_IO2, EVENTOUT -
-----5252B6 PC11 I/OFT- USART3_RX, TSC_G3_IO3,
EVENTOUT -
-----5353C5 PC12 I/OFT- TRACED3, USART3_CK,
TSC_G3_IO4, EVENTOUT -
Table 14. STM32L422xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
Pinouts and pin description STM32L422xx
62/194 DS12470 Rev 2
------54B5 PD2 I/OFT- TRACED2, USART3_RTS_DE,
TSC_SYNC, EVENTOUT -
26 26 B3 39 39 54 55 A5
PB3
(JTDO/TRACES
WO)
I/O FT_a -
JTDO/TRACESWO, TIM2_CH2,
SPI1_SCK, USART1_RTS_DE,
EVENTOUT
-
27 27 A3 40 40 55 56 A4 PB4 (NJTRST) I/O FT_fa -
NJTRST, I2C3_SDA, SPI1_MISO,
USART1_CTS, TSC_G2_IO1,
EVENTOUT
-
28 28 C4 41 41 56 57 C4 PB5 I/O FT -
TRACED2, LPTIM1_IN1, I2C1_SMBA,
SPI1_MOSI, USART1_CK,
TSC_G2_IO2, TIM16_BKIN,
EVENTOUT
-
29 29 B4 42 42 57 58 D3 PB6 I/O FT_fa -
TRACED3, LPTIM1_ETR, I2C1_SCL,
USART1_TX, TSC_G2_IO3,
TIM16_CH1N, EVENTOUT
-
30 30 A4 43 43 58 59 C3 PB7 I/O FT_fa -
TRACECK, LPTIM1_IN2, I2C1_SDA,
USART1_RX, TSC_G2_IO4,
EVENTOUT
PVD_IN
31 31 C5 44 44 59 60 B4 PH3-BOOT0
(BOOT0) I/O FT - EVENTOUT -
- - B5 45 45 60 61 B3 PB8 I/O FT_f - I2C1_SCL, TIM16_CH1, EVENTOUT -
- - - 464661 62 A3 PB9 I/O FT_f - IR_OUT, I2C1_SDA, SPI2_NSS,
EVENTOUT -
-----62- - VDD12 S - - -
Table 14. STM32L422xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
STM32L422xx Pinouts and pin description
DS12470 Rev 2 63/194
32 32 A5 47 47 63 63 D4 VSS S - - -
1 1 A6 48 48 64 64 E4 VDD S - - -
Table 14. STM32L422xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP32
UFQFPN32
WLCSP36
LQFP48
UFQFPN48
LQFP64 SMPS
LQFP64
UFBGA64
Pinouts and pin description STM32L422xx
64/194 DS12470 Rev 2
Table 15. Alternate function AF0 to AF7(1)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF TIM1/TIM2/LPT
IM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1 USART1/USA
RT2/USART3
Port A
PA0-TIM2_CH1-----USART2_CTS
PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - USART2_RTS_
DE
PA2-TIM2_CH3-----USART2_TX
PA3-TIM2_CH4-----USART2_RX
PA4 - - - - - SPI1_NSS - USART2_CK
PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - -
PA6 - TIM1_BKIN - - SPI1_MISO COMP1_OUT USART3_CTS
PA7 - TIM1_CH1N - - I2C3_SCL SPI1_MOSI - -
PA8 MCO TIM1_CH1 - - - - USART1_CK
PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX
PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS
PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_
DE
PA13JTMS/SWDATIR_OUT------
PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA - - -
PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS - USART3_RTS_
DE
STM32L422xx Pinouts and pin description
DS12470 Rev 2 65/194
Port B
PB0 TRACED0 TIM1_CH2N - - - SPI1_NSS - USART3_CK
PB1TRACED1TIM1_CH3N-----
USART3_RTS_
DE
PB2 - LPTIM1_OUT - - I2C3_SMBA - - -
PB3 JTDO/TRACES
WO TIM2_CH2 - - - SPI1_SCK - USART1_RTS_
DE
PB4 NJTRST - - - I2C3_SDA SPI1_MISO - USART1_CTS
PB5 TRACED2 LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI - USART1_CK
PB6 TRACED3 LPTIM1_ETR - - I2C1_SCL - - USART1_TX
PB7 TRACECK LPTIM1_IN2 - - I2C1_SDA - - USART1_RX
PB8----I2C1_SCL---
PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK - USART3_TX
PB11 - TIM2_CH4 - - I2C2_SDA - USART3_RX
PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS - USART3_CK
PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK - USART3_CTS
PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO - USART3_RTS_
DE
PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - -
Table 15. Alternate function AF0 to AF7(1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF TIM1/TIM2/LPT
IM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1 USART1/USA
RT2/USART3
Pinouts and pin description STM32L422xx
66/194 DS12470 Rev 2
Port C
PC0 TRACECK LPTIM1_IN1 - - I2C3_SCL - - -
PC1 TRACED0 LPTIM1_OUT - - I2C3_SDA - - -
PC2 - LPTIM1_IN2 - - - SPI2_MISO - -
PC3 - LPTIM1_ETR - - - SPI2_MOSI - -
PC4-------USART3_TX
PC5-------USART3_RX
PC6--------
PC7--------
PC8--------
PC9--------
PC10TRACED1------USART3_TX
PC11-------USART3_RX
PC12TRACED3------USART3_CK
PC13--------
PC14--------
PC15--------
Port DPD2TRACED2------
USART3_RTS_
DE
Port H
PH0--------
PH1--------
PH3--------
1. Refer to Table 16 for AF8 to AF15.
Table 15. Alternate function AF0 to AF7(1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF TIM1/TIM2/LPT
IM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1 USART1/USA
RT2/USART3
STM32L422xx Pinouts and pin description
DS12470 Rev 2 67/194
Table 16. Alternate function AF8 to AF15(1)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
LPUART1 TSC CAN1
/QUADSPI -COMP1-
TIM2/TIM15/
TIM16/LPTIM2 EVENOUT
Port A
PA0 - - - - COMP1_OUT - TIM2_ETR EVENTOUT
PA1------TIM15_CH1NEVENTOUT
PA2 LPUART1_TX - QUADSPI_BK1
_NCS - - - TIM15_CH1 EVENTOUT
PA3 LPUART1_RX - QUADSPI_CLK - - - TIM15_CH2 EVENTOUT
PA4------LPTIM2_OUTEVENTOUT
PA5------LPTIM2_ETREVENTOUT
PA6 LPUART1_CTS - QUADSPI_BK1
_IO3 - - - TIM16_CH1 EVENTOUT
PA7 - - QUADSPI_BK1
_IO2 ----EVENTOUT
PA8------LPTIM2_OUTEVENTOUT
PA9------TIM15_BKINEVENTOUT
PA10 - - USB_CRS_SY
NC ----EVENTOUT
PA11 - - USB_DM - TIM1_BKIN2_C
OMP1 - - EVENTOUT
PA12--USB_DP----EVENTOUT
PA13--USB_NOE----EVENTOUT
PA14-------EVENTOUT
PA15-TSC_G3_IO1-----EVENTOUT
Pinouts and pin description STM32L422xx
68/194 DS12470 Rev 2
Port B
PB0--------
PB1 - - QUADSPI_BK1
_IO1 - COMP1_OUT - - EVENTOUT
PB2 LPUART1_RTS
_DE -QUADSPI_BK1
_IO0 - - - LPTIM2_IN1 EVENTOUT
PB3-------EVENTOUT
PB4-------EVENTOUT
PB5-TSC_G2_IO1-----EVENTOUT
PB6-TSC_G2_IO2----TIM16_BKINEVENTOUT
PB7-TSC_G2_IO3----TIM16_CH1NEVENTOUT
PB8-TSC_G2_IO4-----EVENTOUT
PB9------TIM16_CH1EVENTOUT
PB10-------EVENTOUT
PB11 LPUART1_RX TSC_SYNC QUADSPI_CLK - COMP1_OUT - - EVENTOUT
PB12 LPUART1_TX - QUADSPI_BK1
_NCS ----EVENTOUT
PB13 LPUART1_RTS
_DE TSC_G1_IO1----TIM15_BKINEVENTOUT
PB14LPUART1_CTSTSC_G1_IO2----TIM15_CH1NEVENTOUT
PB15-TSC_G1_IO3----TIM15_CH1EVENTOUT
Table 16. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
LPUART1 TSC CAN1
/QUADSPI -COMP1-
TIM2/TIM15/
TIM16/LPTIM2 EVENOUT
STM32L422xx Pinouts and pin description
DS12470 Rev 2 69/194
Port C
PC0-TSC_G1_IO4----TIM15_CH2EVENTOUT
PC1--------
PC2LPUART1_RX-----LPTIM2_IN1EVENTOUT
PC3LPUART1_TX------EVENTOUT
PC4-------EVENTOUT
PC5------LPTIM2_ETREVENTOUT
PC6------ EVENTOUT
PC7------ EVENTOUT
PC8-TSC_G4_IO1---- EVENTOUT
PC9-TSC_G4_IO2---- EVENTOUT
PC10-TSC_G4_IO3---- EVENTOUT
PC11 - TSC_G4_IO4 USB_NOE - - - - EVENTOUT
PC12 - TSC_G3_IO2 - - - - EVENTOUT
PC13 - TSC_G3_IO3 - - - - EVENTOUT
PC14 - TSC_G3_IO4 - - - - EVENTOUT
PC15-------EVENTOUT
Port DPD2-------EVENTOUT
Port H
PH0-------EVENTOUT
PH1--------
PH3-TSC_SYNC-----EVENTOUT
1. Refer to Table 15 for AF0 to AF7.
Table 16. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
LPUART1 TSC CAN1
/QUADSPI -COMP1-
TIM2/TIM15/
TIM16/LPTIM2 EVENOUT
Memory mapping STM32L422xx
70/194 DS12470 Rev 2
5 Memory mapping
Figure 14. STM32L422xx memory map
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DS12470 Rev 2 71/194
STM32L422xx Memory mapping
73
Table 17. STM32L422xx memory map and peripheral register boundary addresses(1)
Bus Boundary address Size(bytes) Peripheral
AHB2
0x5006 0800 - 0x5006 0BFF 1 KB RNG
0x5006 0000 - 0x5006 03FF 1 KB AES
0x5004 0400 - 0x5005 FFFF 126 KB Reserved
0x5004 0000 - 0x5004 03FF 1 KB ADC
0x5000 0000 - 0x5003 FFFF 16 KB Reserved
0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved
0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH
0x4800 1000 - 0x4800 1BFF 3 KB Reserved
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
-0x4002 4400 - 0x47FF FFFF ~127 MB Reserved
AHB1
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 1 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2400 - 0x4002 2FFF 3 KB Reserved
0x4002 2000 - 0x4002 23FF 1 KB FLASH registers
0x4002 1400 - 0x4002 1FFF 3 KB Reserved
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0800 - 0x4002 0FFF 2 KB Reserved
0x4002 0400 - 0x4002 07FF 1 KB DMA2
0x4002 0000 - 0x4002 03FF 1 KB DMA1
Memory mapping STM32L422xx
72/194 DS12470 Rev 2
APB2
0x4001 4800 - 0x4001 FFFF 46 KB Reserved
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2000 - 0x4001 2BFF 3 KB Reserved
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL
0x4001 0800- 0x4001 1BFF 5 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0200 - 0x4001 03FF 1 KB COMP
0x4001 0030 - 0x4001 01FF 1 KB Reserved
0x4001 0000 - 0x4001 002F 1 KB SYSCFG
APB1
0x4000 9800 - 0x4000 FFFF 26 KB Reserved
0x4000 9400 - 0x4000 97FF 1 KB LPTIM2
0x4000 8400 - 0x4000 93FF 4 KB Reserved
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP
0x4000 7400 - 0x4000 77FF 1 KB Reserved
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB USB SRAM
0x4000 6800 - 0x4000 6BFF 1 KB USB FS
0x4000 6400 - 0x4000 67FF 1 KB Reserved
0x4000 6000 - 0x4000 63FF 1 KB CRS
0x4000 5C00- 0x4000 5FFF 1 KB I2C3
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 4C00 - 0x4000 53FF 2 KB Reserved
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
0x4000 4000 - 0x4000 43FF 1 KB Reserved
Table 17. STM32L422xx memory map and peripheral register boundary addresses(1)
(continued)
Bus Boundary address Size(bytes) Peripheral
DS12470 Rev 2 73/194
STM32L422xx Memory mapping
73
APB1
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 1400 - 0x4000 27FF 5 KB Reserved
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0400- 0x4000 0FFF 3 KB Reserved
0x4000 0000 - 0x4000 03FF 1 KB TIM2
1. The gray color is used for reserved boundary addresses.
Table 17. STM32L422xx memory map and peripheral register boundary addresses(1)
(continued)
Bus Boundary address Size(bytes) Peripheral
Electrical characteristics STM32L422xx
74/194 DS12470 Rev 2
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 15.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 16.
Figure 15. Pin loading conditions Figure 16. Pin input voltage
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DS12470 Rev 2 75/194
STM32L422xx Electrical characteristics
165
6.1.6 Power supply scheme
Figure 17. Power supply scheme
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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Electrical characteristics STM32L422xx
76/194 DS12470 Rev 2
6.1.7 Current consumption measurement
Figure 18. Current consumption measurement scheme with and without external
SMPS power supply
The IDD_ALL parameters given in Table 25 to Table 47 represent the total MCU consumption
including the current supplying VDD, VDDA, VDDUSB and VBAT
.
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
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Table 18. Voltage characteristics(1)
Symbol Ratings Min Max Unit
VDDX - VSS
External main supply voltage (including
VDD, VDDA, VDDUSB, VBAT)-0.3 4.0 V
VDD12 - VSS External SMPS supply voltage -0.3 1.32 V
VIN(2)
Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDUSB)
+ 4.0(3)(4)
V
Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on any other pins VSS-0.3 4.0
DS12470 Rev 2 77/194
STM32L422xx Electrical characteristics
165
|VDDx|Variations between different VDDX power
pins of the same domain -50mV
|VSSx-VSS|Variations between all the different ground
pins(5) -50mV
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected
current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 18. Voltage characteristics(1) (continued)
Symbol Ratings Min Max Unit
Table 19. Current characteristics
Symbol Ratings Max Unit
IVDD Total current into sum of all VDD power lines (source)(1)(2) 140
mA
IVSS Total current out of sum of all VSS ground lines (sink)(1) 140
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
IIO(PIN)
Output current sunk by any I/O and control pin except FT_f 20
Output current sunk by any FT_f pin 20
Output current sourced by any I/O and control pin 20
IIO(PIN)
Total output current sunk by sum of all I/Os and control pins(3) 100
Total output current sourced by sum of all I/Os and control pins(3) 100
IINJ(PIN)(4)
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,
PA5 -5/+0(5)
Injected current on PA4, PA5 -5/0
|IINJ(PIN)|Total injected current (sum of all I/Os and control pins)(6) 25
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. Valid also for VDD12 on SMPS packages.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage
characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum |IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Electrical characteristics STM32L422xx
78/194 DS12470 Rev 2
Table 20. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
DS12470 Rev 2 79/194
STM32L422xx Electrical characteristics
165
6.3 Operating conditions
6.3.1 General operating conditions
Table 21. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 80
MHzfPCLK1 Internal APB1 clock frequency - 0 80
fPCLK2 Internal APB2 clock frequency - 0 80
VDD Standard operating voltage - 1.71
(1) 3.6 V
VDDA Analog supply voltage
ADC or COMP used 1.62
3.6 VOPAMP used 1.8
ADC, OPAMP, COMP not used 0
VDD12 Standard operating voltage
Full frequency range 1.08
1.32 V
Up to 26 MHz 1.00
VBAT Backup operating voltage - 1.55 3.6 V
VDDUSB USB supply voltage
USB used 3.0 3.6
V
USB not used 0 3.6
VIN I/O input voltage
TT_xx I/O -0.3 VDDIOx+0.3
V
All I/O except TT_xx -0.3
Min(Min(VDD, VDDA,
VDDUSB)+3.6 V,
5.5 V)(2)(3)
PD
Power dissipation at
TA = 85 °C for suffix 6
or
TA = 105 °C for suffix 7(4)
LQFP64 - 303
mW
UFBGA64 - 317
LQFP48 - 294
UFQFPN48 - 667
WLCSP36 235
LQFP32 294
UFQFPN32 541
PD
Power dissipation at
TA = 125 °C for suffix 3(4)
LQFP64 - 76
mW
UFBGA64 - 79
LQFP48 - 75
UFQFPN48 - 167
WLCSP36 - 59
LQFP32 - 75
UFQFPN32 - 135
Electrical characteristics STM32L422xx
80/194 DS12470 Rev 2
6.3.2 Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
6.3.3 Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature conditions summarized in Table 21: General operating conditions.
TA
Ambient temperature for the
suffix 6 version
Maximum power dissipation –40 85
°C
Low-power dissipation(5) –40 105
Ambient temperature for the
suffix 3 version
Maximum power dissipation –40 125
Low-power dissipation(5) –40 130
TJ Junction temperature range
Suffix 6 version –40 105
°C
Suffix 3 version –40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDUSB)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).
Table 21. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit
Table 22. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate
-
0
µs/V
VDD fall time rate 10
tVDDA
VDDA rise time rate
-
0
VDDA fall time rate 10
tVDDUSB
VDDUSB rise time rate
-
0
VDDUSB fall time rate 10
Table 23. Embedded reset and power control block characteristics
Symbol Parameter Conditions(1) Min Typ Max Unit
tRSTTEMPO(2) Reset temporization after
BOR0 is detected VDD rising - 250 400 s
VBOR0(2) Brown-out reset threshold 0
Rising edge 1.62 1.66 1.7
V
Falling edge 1.6 1.64 1.69
DS12470 Rev 2 81/194
STM32L422xx Electrical characteristics
165
VBOR1 Brown-out reset threshold 1
Rising edge 2.06 2.1 2.14
V
Falling edge 1.96 2 2.04
VBOR2 Brown-out reset threshold 2
Rising edge 2.26 2.31 2.35
V
Falling edge 2.16 2.20 2.24
VBOR3 Brown-out reset threshold 3
Rising edge 2.56 2.61 2.66
V
Falling edge 2.47 2.52 2.57
VBOR4 Brown-out reset threshold 4
Rising edge 2.85 2.90 2.95
V
Falling edge 2.76 2.81 2.86
VPVD0
Programmable voltage
detector threshold 0
Rising edge 2.1 2.15 2.19
V
Falling edge 2 2.05 2.1
VPVD1 PVD threshold 1
Rising edge 2.26 2.31 2.36
V
Falling edge 2.15 2.20 2.25
VPVD2 PVD threshold 2
Rising edge 2.41 2.46 2.51
V
Falling edge 2.31 2.36 2.41
VPVD3 PVD threshold 3
Rising edge 2.56 2.61 2.66
V
Falling edge 2.47 2.52 2.57
VPVD4 PVD threshold 4
Rising edge 2.69 2.74 2.79
V
Falling edge 2.59 2.64 2.69
VPVD5 PVD threshold 5
Rising edge 2.85 2.91 2.96
V
Falling edge 2.75 2.81 2.86
VPVD6 PVD threshold 6
Rising edge 2.92 2.98 3.04
V
Falling edge 2.84 2.90 2.96
Vhyst_BORH0 Hysteresis voltage of BORH0
Hysteresis in
continuous
mode
-20-
mV
Hysteresis in
other mode -30-
Vhyst_BOR_PVD
Hysteresis voltage of BORH
(except BORH0) and PVD --100-mV
IDD
(BOR_PVD)(2)
BOR(3) (except BOR0) and
PVD consumption from VDD
--1.11.6µA
BOR(3) (except BOR0) and
PVD consumption from VDD
with ENULP = 1
-
VPVM1
VDDUSB peripheral voltage
monitoring - 1.18 1.22 1.26 V
VPVM3
VDDA peripheral voltage
monitoring
Rising edge 1.61 1.65 1.69
V
Falling edge 1.6 1.64 1.68
Table 23. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
Electrical characteristics STM32L422xx
82/194 DS12470 Rev 2
VPVM4
VDDA peripheral voltage
monitoring
Rising edge 1.78 1.82 1.86
V
Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV
Vhyst_PVM4 PVM4 hysteresis - - 10 - mV
IDD (PVM1)
(2) PVM1 consumption from VDD --0.2-µA
IDD
(PVM3/PVM4)
(2)
PVM3 and PVM4
consumption from VDD
--2-µA
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
Table 23. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
DS12470 Rev 2 83/194
STM32L422xx Electrical characteristics
165
6.3.4 Embedded voltage reference
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +130 °C 1.182 1.212 1.232 V
tS_vrefint (1)
ADC sampling time when
reading the internal reference
voltage
-4
(2) --µs
tstart_vrefint
Start time of reference voltage
buffer when ADC is enable --812
(2) µs
IDD(VREFINTBUF)
VREFINT buffer consumption
from VDD when converted by
ADC
- - 12.5 20(2) µA
VREFINT
Internal reference voltage
spread over the temperature
range
VDD = 3 V - 5 7.5(2) mV
TCoeff Temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
-
24 25 26
%
VREFINT
VREFINT_DIV2 1/2 reference voltage 49 50 51
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
Electrical characteristics STM32L422xx
84/194 DS12470 Rev 2
Figure 19. VREFINT versus temperature
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DS12470 Rev 2 85/194
STM32L422xx Electrical characteristics
165
6.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 18: Current consumption
measurement scheme with and without external SMPS power supply.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0394 reference manual).
When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 25 to Table 48 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Electrical characteristics STM32L422xx
86/194 DS12470 Rev 2
Table 25. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
Range 2
26 MHz 2.05 2.10 2.10 2.20 2.35 2.20 2.25 2.30 2.40 2.60
mA
16 MHz 1.30 1.35 1.40 1.45 1.60 1.40 1.45 1.50 1.60 1.80
8 MHz 0.715 0.730 0.780 0.855 1.00 0.76 0.78 0.84 0.96 1.25
4 MHz 0.415 0.430 0.475 0.555 0.710 0.45 0.50 0.55 0.70 0.90
2 MHz 0.265 0.28 0.325 0.400 0.555 0.30 0.30 0.40 0.50 0.80
1 MHz 0.190 0.205 0.250 0.325 0.480 0.20 0.25 0.30 0.44 0.70
100 kHz 0.120 0.135 0.180 0.255 0.410 0.15 0.20 0.25 0.40 0.60
Range 1
80 MHz 7.30 7.35 7.40 7.55 7.70 7.75 7.80 7.80 7.90 8.10
72 MHz 6.60 6.65 6.70 6.80 7.00 7.00 7.00 7.10 7.20 7.40
64 MHz 5.90 5.90 6.00 6.10 6.30 6.25 6.30 6.35 6.40 6.65
48 MHz 4.40 4.40 4.50 4.60 4.80 4.70 4.75 4.80 4.90 5.10
32 MHz 3.00 3.00 3.05 3.15 3.35 3.20 3.25 3.30 3.40 3.60
24 MHz 2.30 2.30 2.35 2.45 2.65 2.40 2.40 2.50 2.60 2.90
16 MHz 1.55 1.60 1.65 1.75 1.90 1.70 1.75 1.80 1.90 2.20
IDD_ALL
(LPRun)
Supply
current in
Low-power
run mode
fHCLK = fMSI
all peripherals disable
2 MHz 190 205 255 335 505 235 230 315 455 725
µA
1 MHz 110 120 165 250 415 135 145 230 370 645
400 kHz 55.0 65.5 115 195 360 75.0 90.5 180 325 590
100 kHz 26.0 40.0 87.5 170 335 45.0 65.5 160 290 550
1. Guaranteed by characterization results, unless otherwise specified.
STM32L422xx Electrical characteristics
DS12470 Rev 2 87/194
Table 26. Current consumption in Run modes, code with data processing running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP
Unit
-f
HCLK 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL(Run) Supply current in Run
mode
fHCLK = fHSE up to 48MHz included, bypass mode
PLL ON above
48 MHz all peripherals disable
80 MHz 2.62 2.64 2.66 2.71 2.77
mA
72 MHz 2.37 2.39 2.41 2.44 2.52
64 MHz 2.12 2.12 2.16 2.19 2.26
48 MHz 1.58 1.58 1.62 1.65 1.73
32 MHz 1.08 1.08 1.10 1.13 1.20
24 MHz 0.83 0.83 0.84 0.88 0.95
16 MHz 0.56 0.58 0.59 0.63 0.68
8 MHz 0.26 0.26 0.28 0.31 0.36
4 MHz 0.15 0.15 0.17 0.20 0.26
2 MHz 9.53 0.10 0.12 0.14 0.20
1 MHz 0.07 0.07 0.09 0.12 0.17
100 kHz 0.01 0.01 0.03 0.06 0.12
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
Electrical characteristics STM32L422xx
88/194 DS12470 Rev 2
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
Range 2
26 MHz 2.40 2.45 2.50 2.55 2.75 2.60 2.65 2.70 2.80 3.00
mA
16 MHz 1.70 1.75 1.80 1.85 2.05 1.85 1.90 1.95 2.05 2.30
8 MHz 0.970 0.985 1.05 1.10 1.25 1.05 1.10 1.15 1.25 1.50
4 MHz 0.570 0.585 0.630 0.710 0.865 0.61 0.63 0.70 0.80 1.10
2 MHz 0.340 0.355 0.400 0.475 0.635 0.40 0.40 0.50 0.60 0.80
1 MHz 0.230 0.240 0.285 0.365 0.52 0.25 0.30 0.34 0.50 0.70
100 kHz 0.125 0.140 0.185 0.260 0.415 0.14 0.20 0.25 0.40 0.60
Range 1
80 MHz 7.65 7.70 7.85 8.00 8.20 8.20 8.30 8.40 8.50 8.80
72 MHz 6.95 6.95 7.05 7.15 7.35 7.40 7.45 7.50 7.60 7.80
64 MHz 6.90 6.95 7.05 7.20 7.40 7.40 7.45 7.50 7.60 7.80
48 MHz 5.85 5.90 6.00 6.15 6.35 6.30 6.35 6.50 6.65 6.90
32 MHz 4.20 4.20 4.30 4.45 4.65 4.50 4.55 4.70 4.80 5.10
24 MHz 3.15 3.20 3.25 3.35 3.55 3.40 3.40 3.50 3.60 3.90
16 MHz 2.25 2.30 2.35 2.50 2.65 2.50 2.50 2.60 2.70 3.00
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI
all peripherals disable
2 MHz 275 290 340 425 590 325 360 425 565 840
µA
1 MHz 155 165 210 295 460 185 195 275 420 690
400 kHz 69.0 83.0 130 215 280 90.5 108 195 340 600
100 kHz 32.0 45.5 92.0 175 340 48.0 69 155 300 570
1. Guaranteed by characterization results, unless otherwise specified.
STM32L422xx Electrical characteristics
DS12470 Rev 2 89/194
Table 28. Current consumption in Run modes, code with data processing running from Flash,
ART disable and power supplied by external SMPS (VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP Uni
t
-f
HCLK 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL(Run) Supply current in Run
mode
fHCLK = fHSE up to 48MHz included, bypass mode
PLL ON above 48 MHz all peripherals disable
80 MHz 2.75 2.77 2.82 2.88 2.95
mA
72 MHz 2.50 2.50 2.53 2.57 2.64
64 MHz 2.48 2.50 2.53 2.59 2.66
48 MHz 2.10 2.12 2.16 2.21 2.28
32 MHz 1.51 1.51 1.55 1.60 1.67
24 MHz 1.13 1.15 1.17 1.20 1.28
16 MHz 0.81 0.83 0.84 0.90 0.95
8 MHz 0.35 0.35 0.38 0.40 0.45
4 MHz 0.20 0.21 0.23 0.26 0.31
2 MHz 12.22 0.13 0.14 0.17 0.23
1 MHz 0.08 0.09 0.10 0.13 0.19
100 kHz 0.01 0.02 0.03 0.06 0.12
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
Electrical characteristics STM32L422xx
90/194 DS12470 Rev 2
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105
°C
125
°C 25 °C 55 °C 85 °C 105
°C
125
°C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
Range 2
26 MHz 2.00 2.05 2.10 2.15 2.35 2.20 2.20 2.25 2.35 2.55
mA
16 MHz 1.30 1.30 1.35 1.45 1.60 1.40 1.45 1.45 1.55 1.80
8 MHz 0.705 0.720 0.765 0.845 1.00 0.75 0.77 0.83 0.94 1.20
4 MHz 0.410 0.425 0.470 0.550 0.700 0.44 0.46 0.52 0.64 0.90
2 MHz 0.265 0.275 0.320 0.395 0.555 0.28 0.30 0.37 0.49 0.75
1 MHz 0.190 0.200 0.245 0.325 0.475 0.21 0.22 0.29 0.42 0.67
100 kHz 0.120 0.135 0.180 0.255 0.410 0.14 0.15 0.23 0.35 0.61
Range 1
80 MHz 7.15 7.20 7.25 7.45 7.55 7.65 7.65 7.75 7.75 8.00
72 MHz 6.45 6.50 6.55 6.75 6.85 6.90 6.95 7.00 7.05 7.25
64 MHz 5.75 5.80 5.85 6.05 6.15 6.15 6.20 6.25 6.30 6.50
48 MHz 4.20 4.35 4.40 4.50 7.70 4.65 4.65 4.70 4.80 5.00
32 MHz 2.95 2.95 3.00 3.10 3.30 3.15 3.15 3.20 3.30 3.55
24 MHz 2.25 2.25 2.30 2.40 2.60 2.40 2.40 2.50 2.60 2.85
16 MHz 1.55 1.55 1.60 1.70 1.85 1.65 1.70 1.75 1.85 2.10
IDD_ALL
(LPRun)
Supply
current in
low-power
run mode
fHCLK = fMSI
all peripherals disable
FLASH in power-down
2 MHz 180 190 240 320 485 215 225 300 450 720
µA
1 MHz 90.5 110 155 235 400 120 135 220 360 640
400 kHz 40.5 56.0 105 185 350 60.0 76.5 165 315 565
100 kHz 17.5 32.0 78.5 160 325 33.5 53.5 140 285 555
1. Guaranteed by characterization results, unless otherwise specified.
STM32L422xx Electrical characteristics
DS12470 Rev 2 91/194
Table 30. Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP
Unit
-f
HCLK 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL(Run) Supply current in Run mode
fHCLK = fHSE up to 48MHz included, bypass mode
PLL ON above
48 MHz all peripherals disable
80 MHz 2.57 2.59 2.61 2.68 2.71
mA
72 MHz 2.32 2.34 2.35 2.43 2.46
64 MHz 2.07 2.08 2.10 2.17 2.21
48 MHz 1.55 1.56 1.58 1.62 1.69
32 MHz 1.06 1.06 1.08 1.11 1.19
24 MHz 0.81 0.81 0.83 0.86 0.93
16 MHz 0.56 0.56 0.58 0.61 0.67
8 MHz 0.25 0.26 0.28 0.30 0.36
4 MHz 0.15 0.15 0.17 0.20 0.25
2 MHz 9.53 0.10 0.12 0.15 0.20
1 MHz 0.07 0.07 0.09 0.14 0.17
100 kHz 0.01 0.01 0.03 0.06 0.12
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
Electrical characteristics STM32L422xx
92/194 DS12470 Rev 2
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up
to 48 MHz
included, bypass
mode PLL ON
above 48 MHz
all peripherals
disable
Range 2
fHCLK = 26 MHz
Reduced code(1) 2.05
mA
79
µA/MHz
Coremark 2.30 88
Dhrystone 2.1 2.35 90
Fibonacci 2.25 87
While(1) 1.95 75
Range 1
fHCLK = 80 MHz
Reduced code(1) 7.30
mA
91
µA/MHz
Coremark 8.15 102
Dhrystone 2.1 8.35 104
Fibonacci 8.10 101
While(1) 7.20 90
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1) 190
µA
95
µA/MHz
Coremark 205 103
Dhrystone 2.1 220 110
Fibonacci 205 103
While(1) 225 113
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 32. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above
48 MHz
all peripherals
disable
fHCLK = 26 MHz
Reduced code(2) 0.88
mA
34
µA/MHz
Coremark 0.99 38
Dhrystone 2.1 1.01 39
Fibonacci 0.97 37
While(1) 0.84 32
fHCLK = 80 MHz
Reduced code(2) 3.15 39
Coremark 3.52 44
Dhrystone 2.1 3.60 45
Fibonacci 3.49 44
While(1) 3.11 39
DS12470 Rev 2 93/194
STM32L422xx Electrical characteristics
165
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 33. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.00 V)
Symbol Parameter
Conditions(1) TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above
48 MHz
all peripherals
disable
fHCLK = 26 MHz
Reduced code(2) 0.73
mA
28
µA/MHz
Coremark 0.82 32
Dhrystone 2.1 0.84 32
Fibonacci 0.80 31
While(1) 0.70 27
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Electrical characteristics STM32L422xx
94/194 DS12470 Rev 2
Table 34. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz
all peripherals
disable
Range 2
fHCLK = 26 MHz
Reduced code(1) 2.40
mA
92
µA/MHz
Coremark 2.15 83
Dhrystone 2.1 2.20 85
Fibonacci 2.05 79
While(1) 1.90 73
Range 1
fHCLK = 80 MHz
Reduced code(1) 7.65
mA
96
µA/MHz
Coremark 6.95 87
Dhrystone 2.1 7.00 88
Fibonacci 6.60 83
While(1) 6.85 86
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1) 275
µA
138
µA/MHz
Coremark 300 150
Dhrystone 2.1 315 158
Fibonacci 305 153
While(1) 385 193
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 35. Typical current consumption in Run modes, with different codes running from
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz
all peripherals
disable
fHCLK = 26 MHz
Reduced code(2) 1.04
mA
40
µA/MHz
Coremark 0.93 36
Dhrystone 2.1 0.95 37
Fibonacci 0.88 34
While(1) 0.82 32
fHCLK = 80 MHz
Reduced code(2) 3.30 41
Coremark 3.00 37
Dhrystone 2.1 3.02 38
Fibonacci 2.85 36
While(1) 2.95 37
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
DS12470 Rev 2 95/194
STM32L422xx Electrical characteristics
165
Table 36. Typical current consumption in Run modes, with different codesrunning from
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V)
Symbol Parameter
Conditions(1) TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz
all peripherals
fHCLK = 26 MHz
Reduced code(2) 0.86
mA
33
µA/MHz
Coremark 0.77 29
Dhrystone 2.1 0.78 30
Fibonacci 0.73 28
While(1) 0.68 26
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 37. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals
disable
Range 2
fHCLK = 26 MHz
Reduced code(1) 2.00
mA
77
µA/MHz
Coremark 2.00 77
Dhrystone 2.1 2.05 79
Fibonacci 2.00 77
While(1) 1.85 71
Range 1
fHCLK = 80 MHz
Reduced code(1) 7.15
mA
89
µA/MHz
Coremark 7.00 88
Dhrystone 2.1 7.15 89
Fibonacci 7.10 89
While(1) 6.60 83
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1) 180
µA
90
µA/MHz
Coremark 180 90
Dhrystone 2.1 185 93
Fibonacci 170 85
While(1) 170 85
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Electrical characteristics STM32L422xx
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Table 38. Typical current consumption in Run, with different codesrunning from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
fHCLK = 26 MHz
Reduced code(2) 0.86
mA
33
µA/MHz
Coremark 0.86 33
Dhrystone 2.1 0.88 34
Fibonacci 0.86 33
While(1) 0.80 31
fHCLK = 80 MHz
Reduced code(2) 3.08 39
Coremark 3.02 38
Dhrystone 2.1 3.08 39
Fibonacci 3.06 38
While(1) 2.85 36
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 39. Typical current consumption in Run, with different codesrunning from
SRAM1 and power supplied by external SMPS (VDD12 = 1.00 V)
Symbol Parameter
Conditions(1) TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
fHCLK = 26 MHz
Reduced code(2) 0.71
mA
27
µA/MHz
Coremark 0.71 27
Dhrystone 2.1 0.73 28
Fibonacci 0.71 27
While(1) 0.66 25
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
STM32L422xx Electrical characteristics
DS12470 Rev 2 97/194
Table 40. Current consumption in Sleep and Low-power sleep modes, Flash ON
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Sleep)
Supply
current in
sleep
mode,
fHCLK = fHSE up
to 48 MHz
included, bypass
mode
pll ON above
48 MHz all
peripherals
disable
Range 2
26 MHz 0.535 0.550 0.600 0.680 0.835 0.58 0.60 0.66 0.79 1.05
mA
16 MHz 0.375 0.390 0.435 0.515 0.670 0.41 0.43 0.50 0.62 0.88
8 MHz 0.245 0.260 0.305 0.385 0.540 0.27 0.29 0.36 0.49 0.74
4 MHz 0.180 0.195 0.240 0.315 0.470 0.20 0.22 0.29 0.42 0.67
2 MHz 0.150 0.160 0.205 0.285 0.435 0.17 0.18 0.25 0.38 0.63
1 MHz 0.130 0.145 0.190 0.265 0.420 0.15 0.16 0.24 0.36 0.62
100 kHz 0.115 0.130 0.175 0.250 0.405 0.13 0.15 0.22 0.35 0.60
Range 1
80 MHz 1.65 1.70 1.75 1.85 2.00 1.80 1.80 1.85 1.95 2.25
72 MHz 1.50 1.55 1.60 1.70 1.85 1.60 1.65 1.70 1.80 2.10
64 MHz 1.35 1.40 1.45 1.55 1.70 1.45 1.50 1.55 1.65 1.95
48 MHz 1.00 1.05 1.10 1.2 1.35 1.10 1.15 1.20 1.35 1.65
32 MHz 0.725 0.740 0.795 0.885 1.05 0.78 0.80 0.87 1.05 1.35
24 MHz 0.575 0.595 0.650 0.740 0.910 0.62 0.64 0.72 0.86 1.15
16 MHz 0.425 0.440 0.495 0.585 0.760 0.47 0.48 0.56 0.71 1.00
IDD_ALL
(LPSleep)
Supply
current in
low-power
sleep
mode
fHCLK = fMSI
all peripherals disable
2 MHz 52.5 66.5 115 195 360 71.0 91.5 175 315 600
µA
1 MHz 37.0 51.5 97.5 180 345 55.0 73.0 165 295 575
400 kHz 25.5 39.0 85.0 170 330 41.0 63.0 150 280 565
100 kHz 18.5 33.5 80.5 165 325 36.0 57.5 145 280 560
1. Guaranteed by characterization results, unless otherwise specified.
Electrical characteristics STM32L422xx
98/194 DS12470 Rev 2
Table 41. Current consumption in Sleep, Flash ON and power supplied by external SMPS
(VDD12 = 1.10 V)
Symbol Parameter
Conditions(1) TYP
Unit
-f
HCLK 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL(Sleep) Supply current in sleep mode,
fHCLK = fHSE up to 48 MHz included, bypass
mode
pll ON above
48 MHz all peripherals disable
80 MHz 0.59 0.61 0.63 0.67 0.72
mA
72 MHz 0.54 0.56 0.58 0.61 0.67
64 MHz 0.49 0.50 0.52 0.56 0.61
48 MHz 0.36 0.38 0.40 0.43 0.49
32 MHz 0.26 0.27 0.29 0.32 0.38
24 MHz 0.21 0.21 0.23 0.27 0.33
16 MHz 0.15 0.16 0.18 0.21 0.27
8 MHz 0.09 0.09 0.11 0.14 0.19
4 MHz 0.06 0.07 0.09 0.11 0.17
2 MHz 5.39 0.06 0.07 0.10 0.15
1 MHz 0.05 0.05 0.07 0.10 0.15
100 kHz 0.01 0.01 0.03 0.06 0.12
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
Table 42. Current consumption in Low-power sleep modes, Flash in power-down
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(LPSleep)
Supply current
in low-power
sleep mode
fHCLK = fMSI
all peripherals disable
2 MHz 50 60 105 185 350 63 83 170 300 585
µA
1 MHz 35 45 89.0 170 335 46 65 150 285 570
400 kHz 20 32 76.5 155 320 32 51 135 270 560
100 kHz 15 25 71.5 150 315 25 46 135 270 555
1. Guaranteed by characterization results, unless otherwise specified.
STM32L422xx Electrical characteristics
DS12470 Rev 2 99/194
Table 43. Current consumption in Stop 2 mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Stop 2)
Supply current in
Stop 2 mode,
RTC disabled
-
1.8 V 0.77 2.35 8.60 20.5 46.0 2.0 5.6 21.5 51.0 115
µA
2.4 V 0.78 2.35 8.75 21.0 47.0 2.1 5.8 22.0 52.5 120
3 V 0.79 2.40 9.00 21.5 49.0 2.1 5.9 22.5 54.0 125
3.6 V 0.84 2.55 9.40 22.5 51.5 2.3 6.1 23.0 56.0 130
ENULP = 1
1.8 V 0.72 2.35 9.35 21.0 46.5 - - - - -
2.4 V 0.74 2.35 9.65 22.0 48.0 - - - - -
3 V 0.75 2.65 10.0 22.5 50.0 - - - - -
3.6 V 0.79 2.90 10.5 24.0 52.5 - - - - -
IDD_ALL
(Stop 2 with
RTC)
Supply current in
Stop 2 mode,
RTC enabled
RTC clocked by LSI
1.8 V 1.05 2.70 9.00 21.0 46.0 2.5 6.2 22.0 51.5 120
µA
2.4 V 1.10 2.90 9.30 21.5 47.5 2.8 6.4 22.5 53.0 120
3 V 1.20 3.10 9.65 22.5 49.5 3.0 6.8 23.0 54.5 125
3.6 V 1.30 3.35 10.0 23.5 52.0 3.3 7.2 24.5 57.0 130
RTC clocked by LSI
ENULP = 1
LPCAL = 1
1.8 V 1.00 2.65 9.55 21.5 46.5 - - - - -
2.4 V 1.05 2.90 10.0 22.0 48.5 - - - - -
3 V 1.10 3.15 10.5 23.0 50.5 - - - - -
3.6 V 1.20 3.55 11.5 24.5 53.0 - - - - -
RTC clocked by LSI
ENULP = 1
LPCAL = 1
LSIPREDIV = 1
1.8 V 0.86 2.45 9.35 21.5 46.5 - - - - -
2.4 V 0.88 2.60 9.70 22.0 48.0 - - - - -
3 V 0.93 2.75 10.0 23.0 50.0 - - - - -
3.6 V 0.98 3.05 11.0 24.0 52.5 - - - - -
Electrical characteristics STM32L422xx
100/194 DS12470 Rev 2
IDD_ALL
(Stop 2 with
RTC)
Supply current in
Stop 2 mode,
RTC enabled
RTC clocked by LSE
bypassed at 32768 Hz
1.8 V 1.35 2.85 9.15 21.0 46.0 - - - - -
µA
2.4 V 1.60 3.15 9.60 22.0 48.0 - - - - -
3 V 2.00 3.85 11.0 24.0 51.5 - - - - -
3.6 V 3.90 6.60 15.0 29.5 58.5 - - - - -
RTC clocked by LSE
bypassed at 32768 Hz,
ENULP = 1,
LPCAL = 1
1.8 V 1.20 2.80 9.70 21.5 46.5 - - - - -
2.4 V 1.35 3.10 10.5 22.5 48.5 - - - - -
3 V 1.80 3.90 11.5 25.0 52.5 - - - - -
3.6 V 3.65 6.75 16.0 30.5 59.5 - - - - -
RTC clocked by LSE
quartz in low drive
mode
1.8 V 1.20 2.65 8.85 20.5 47.5 - - - - -
2.4 V 1.25 2.75 9.10 21.0 49.0 - - - - -
3 V 1.35 2.90 9.45 22.0 51.0 - - - - -
3.6 V 1.50 3.10 9.95 23.0 53.0 - - - - -
RTC clocked by LSE
quartz(2) in low drive
mode, ENULP = 1,
LPCAL = 1
1.8 V 1.00 2.55 9.50 21.0 48.0 - - - - -
2.4 V 1.10 2.75 9.90 22.0 49.5 - - - - -
3 V 1.15 3.00 10.5 23.0 52.0 - - - - -
3.6 V 1.25 3.25 11.0 25.0 54.5 - - - - -
IDD_ALL
(wakeup from
Stop2)
Supply current
during wakeup
from Stop 2
mode
Wakeup clock is
MSI = 48 MHz,
voltage Range 1.
See (3).
3 V 185 - - - - - - - - -
mA
Wakeup clock is
MSI = 4 MHz,
voltage Range 2.
See (3).
3 V 155 - - - - - - - - -
Wakeup clock is
HSI16 = 16 MHz,
voltage Range 1.
See (3).
3 V 152 - - - - - - - - -
1. Guaranteed by characterization results, unless otherwise specified.
Table 43. Current consumption in Stop 2 mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
STM32L422xx Electrical characteristics
DS12470 Rev 2 101/194
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Electrical characteristics STM32L422xx
102/194 DS12470 Rev 2
Table 44. Current consumption in Stop 1 mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
--V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Stop 1)
Supply current
in Stop 1
mode,
RTC disabled
-
1.8 V 3.95 13.0 47.5 110 230 7.40 24.5 87.0 190 395 µA
2.4 V 3.95 13.0 48.0 110 230 7.50 24.5 86.0 190 395
3 V 4.00 13.5 48.0 110 235 7.30 24.5 87.0 195 400
3.6 V 4.10 13.5 48.5 110 240 7.85 25.0 90.0 195 405
IDD_ALL
(Stop 1 with
RTC)
Supply current
in stop 1
mode,
RTC enabled
RTC clocked by LSI
1.8 V 4.40 13.5 48.0 110 230 8.05 24.5 86.5 190 395
µA
2.4 V 4.60 14.0 48.5 110 235 8.10 25.0 90.0 195 395
3 V 4.75 14.0 48.5 110 235 8.20 25.5 89.0 195 400
3.6 V 5.05 14.5 49.5 115 240 8.55 27.0 89.5 195 405
RTC clocked by LSE
bypassed at 32768 Hz
1.8 V 4.50 13.5 48.5 110 230 11.5 26.5 86.0 190 395
2.4 V 4.70 14.0 49.0 110 230 29.0 31.5 90.0 190 395
3 V 5.35 14.5 50.0 115 240 36.0 31.5 87.5 195 400
3.6 V 7.20 17.5 54.5 120 245 26.0 28.0 88.0 195 405
RTC clocked by LSE quartz(2)
in low drive mode
1.8 V 4.25 13.5 47.5 110 - - - - - -
2.4 V 4.35 13.5 48.0 110 - - - - - -
3 V 4.40 13.5 48.0 110 - - - - - -
3.6 V 4.50 14.0 49.0 125 - - - - - -
IDD_ALL
(wakeup
from Stop1)
Supply current
during
wakeup from
Stop 1
Wakeup clock MSI = 48 MHz,
voltage Range 1.
See (3).
3 V1.15--- ---- - -
mA
Wakeup clock MSI = 4 MHz,
voltage Range 2.
See (3).
3 V1.25--- ---- - -
Wakeup clock
HSI16 = 16 MHz,
voltage Range 1.
See (3).
3 V1.20--- ---- - -
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
STM32L422xx Electrical characteristics
DS12470 Rev 2 103/194
Table 45. Current consumption in Stop 0
Symbol Parameter
Conditions TYP MAX(1)
Unit
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Stop 0)
Supply current
in Stop 0 mode,
RTC disabled
1.8 V 110 125 165 240 380 130 145 215 340 585
µA
2.4 V 110 125 170 240 385 130 145 215 340 585
3 V 115 125 170 245 385 130 145 220 345 590
3.6 V 115 130 175 250 390 135 150 220 345 595
1. Guaranteed by characterization results, unless otherwise specified.
Electrical characteristics STM32L422xx
104/194 DS12470 Rev 2
Table 46. Current consumption in Standby mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Standby)
Supply current
in Standby
mode (backup
registers
retained),
RTC disabled
No independent watchdog
1.8 V 95 255 1150 3200 8350 115 405 2750 7150 19500
nA
2.4 V 105 290 1300 3600 9500 175 540 3250 8350 23000
3 V 120 354 1550 4350 11500 215 650 3750 9600 26000
3.6 V 150 410 1850 5050 13000 280 835 4450 11500 29500
No independent watchdog
ENULP = 1
1.8 V 32 225 1400 3850 9000 115 405 2750 7250 19500
2.4 V 46 315 1800 4500 10500 175 540 3250 8350 23000
3 V 66 430 2400 5450 12500 215 650 3750 9600 26000
3.6 V 115 570 3050 6350 14500 280 835 4450 11500 29500
With independent
watchdog
1.8 V 295 450 1300 3250 8250 - - - - -
2.4 V 350 530 1500 3750 9450 - - - - -
3 V 415 635 1800 4450 11500 - - - - -
3.6 V 505 775 2200 5350 13500 - - - - -
With independent
watchdog
ENULP = 1
1.8 V 230 415 1450 3900 8850 - - - - -
2.4 V 290 540 1950 4600 10550 - - - - -
3 V 365 710 2550 550 12500 - - - - -
3.6 V 460 915 3300 6600 14500 - - - - -
STM32L422xx Electrical characteristics
DS12470 Rev 2 105/194
IDD_ALL
(Standby
with RTC)
Supply current
in Standby
mode (backup
registers
retained),
RTC enabled
RTC clocked by LSI, no
independent watchdog
1.8 V 480 635 1500 3450 8400 560 900 3180 7500 19500
nA
2.4 V 615 800 1800 4050 9700 770 1200 3850 880 23000
3 V 775 995 2150 4850 11500 975 1450 4450 10500 26000
3.6 V 970 1250 2650 5850 14000 1250 1850 5300 12000 29500
RTC clocked by LSI, no
independent watchdog
ENULP = 1
1.8 V 330 515 1600 4000 9000 560 900 3180 7500 19500
2.4 V 435 690 2100 4750 10500 770 1200 3850 8800 23000
3 V 565 915 2750 5750 12500 975 1450 4450 10500 26000
3.6 V 725 1200 3600 6900 1500 1250 1850 5300 12000 29500
RTC clocked by LSI, with
independent watchdog
1.8 V 530 680 1550 3500 8450 - - - - -
2.4 V 675 855 1850 4100 9850 - - - - -
3 V 850 1050 2250 4900 11500 - - - - -
3.6 V 1050 1350 2750 4900 11500 - - - - -
RTC clocked by LSI, with
independent watchdog
ENULP = 1
1.8 V 370 560 1600 4050 9050 - - - - -
2.4 V 495 755 2150 4800 10500 - - - - -
3 V 645 985 2850 5800 12500 - - - - -
3.6 V 825 1300 3700 6950 15000 - - - - -
Table 46. Current consumption in Standby mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Electrical characteristics STM32L422xx
106/194 DS12470 Rev 2
IDD_ALL
(Standby
with RTC)
(cont.)
Supply current
in Standby
mode (backup
registers
retained),
RTC enabled
(cont.)
RTC clocked by LSE
bypassed at 32768 Hz
1.8 V 480 640 1500 3450 8100 - - - - -
nA
2.4 V 615 800 1800 4000 9300 - - - - -
3 V 775 995 2150 4800 11000 - - - - -
3.6 V 960 1250 2650 5800 13000 - - - - -
RTC clocked by LSE
bypassed at 32768 Hz
ENULP = 1
1.8 V 330 510 1600 4000 8800 - - - - -
2.4 V 435 695 2100 4750 10000 - - - - -
3 V 565 910 2750 5700 12000 - - - - -
3.6 V 730 1200 3600 6900 14500 - - - - -
RTC clocked by LSE
quartz (2) in low drive mode
1.8 V 415 575 1450 3400 - - - - - -
2.4 V 485 670 1650 3900 - - - - - -
3 V 550 800 1950 4600 - - - - - -
3.6 V 690 985 2400 - - - - - - -
RTC clocked by LSE
quartz (2) in low drive mode
ENULP = 1
1.8 V 245 450 1600 4000 - - - - - -
2.4 V 290 565 2050 4650 - - - - - -
3 V 355 705 2650 5500 - - - - - -
3.6 V 450 915 3400 - - - - - - -
IDD_ALL
(SRAM2)(3)
Supply current
to be added in
Standby mode
when SRAM2
is retained
-
1.8 V 195 490 1900 4800 12000 350 904 4247 10380 26047
nA
2.4 V 205 520 2050 5300 13000 431 1095 4756 11605 29157
3 V 220 565 2250 5900 15000 477 1211 5263 12861 32215
3.6 V 245 650 2600 6750 13500 556 1414 5956 14382 35821
IDD_ALL
(wakeup
from
Standby)
Supply current
during wakeup
from Standby
mode
Wakeup clock is
MSI = 4 MHz.
See (4).
3 V1.25---------mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby
+ RTC) + IDD_ALL(SRAM2).
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 46. Current consumption in Standby mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
STM32L422xx Electrical characteristics
DS12470 Rev 2 107/194
Table 47. Current consumption in Shutdown mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Shutdown)
Supply current
in Shutdown
mode
(backup
registers
retained) RTC
disabled
-
1.8 V 16 100 600 1850 5450 56 310 1200 3350 9550
nA
2.4 V 22 120 705 2150 6250 65 365 1350 3800 11000
3 V 31 155 870 2650 7700 97 600 1700 4750 12500
3.6 V 52 220 1150 3350 9350 95 440 1850 5050 14500
IDD_ALL
(Shutdown
with RTC)
Supply current
in Shutdown
mode
(backup
registers
retained) RTC
enabled
RTC clocked by LSE
bypassed at 32768 Hz
1.8 V 210 300 820 2050 5750 - - - - -
nA
2.4 V 315 445 1100 2650 6950 - - - - -
3 V 625 1000 2200 44000 10000 - - - - -
3.6 V 820 1650 3500 5600 14500 - - - - -
RTC clocked by LSE
bypassed at 32768 Hz
ENULP = 1
1.8 V 210 300 820 2050 5750 - - - - -
2.4 V 315 445 1100 2650 6950 - - - - -
3 V 625 1000 2200 44000 10000 - - - - -
3.6 V 820 1650 3500 5600 14500 - - - - -
RTC clocked by LSE
quartz (2) in low drive
mode
1.8 V 325 425 930 2200 - - - - - -
2.4 V 400 515 1100 2550 - - - - - -
3 V 475 630 1350 3100 - - - - - -
3.6 V 595 795 1750 - - - - - - -
RTC clocked by LSE
quartz (2) in low drive
mode ENULP = 1
1.8 V 230 325 830 2050 - - - - - -
2.4 V 270 380 975 2400 - - - - - -
3 V 320 455 1200 1950 - - - - - -
3.6 V 400 575 1500 - - - - - - -
IDD_ALL
(wakeup from
Shutdown)
Supply current
during wakeup
from Shutdown
mode
Wakeup clock is
MSI = 4 MHz.
See (3).
3 V 0.78 - - - - - - - - - mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Electrical characteristics STM32L422xx
108/194 DS12470 Rev 2
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 48. Current consumption in VBAT mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
BAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_VBAT
(VBAT)
Backup domain
supply current
RTC disabled
1.8 V 2 12 66 195 540 - - - - -
nA
2.4 V 3 14 73 215 600 - - - - -
3 V 5 16 92 265 730 - - - - -
3.6 V 6 30 161 460 1250 - - - - -
RTC enabled and
clocked by LSE
quartz(2)
1.8 V 300 455 460 990 1750 - - - - -
2.4 V 380 515 575 1050 1950 - - - - -
3 V 445 550 595 1200 2550 - - - - -
3.6 V 495 630 820 1500 2950 - - - - -
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
DS12470 Rev 2 109/194
STM32L422xx Electrical characteristics
165
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 69: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 49: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDDIOx fSW C××=
Electrical characteristics STM32L422xx
110/194 DS12470 Rev 2
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 49. The MCU is placed
under the following conditions:
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
when the peripheral is clocked on
when the peripheral is clocked off
Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 49. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 49. Peripheral current consumption
Peripheral Range 1 Range 2 Low-power run
and sleep Unit
AHB
Bus Matrix(1) 3.0 2.9 2.8
µA/MHz
ADC independent clock domain 0.4 0.2 0.1
ADC clock domain 2.2 1.8 1.8
CRC 0.5 0.3 0.2
DMA1 1.3 1.2 1.1
DMA2 1.3 1.2 1.1
FLASH 5.9 4.9 5.6
GPIOA(2) 1.6 1.5 1.3
GPIOB(2)) 1.5 1.4 1.3
GPIOC(2) 1.7 1.6 1.5
GPIOH(2) 0.6 0.5 0.6
QSPI 6.9 7.0 5.6
RNG independent clock domain 2.2 NA NA
RNG clock domain 0.5 NA NA
SRAM1 0.7 0.6 0.7
SRAM2 0.9 0.7 0.8
TSC 1.5 1.3 1.3
All AHB Peripherals 21.9 19.2 20.5
APB1
AHB to APB1 bridge(3) 0.8 0.6 0.8
RTCA 1.7 1.1 2.1
CRS 0.3 0.3 0.5
USB FS independent clock
domain 2.8 NA NA
USB FS clock domain 2.2 NA NA
DS12470 Rev 2 111/194
STM32L422xx Electrical characteristics
165
APB1
I2C1 independent clock domain 3.4 2.8 3.3
µA/MHz
I2C1 clock domain 1.0 0.9 0.9
I2C2 independent clock domain 3.4 2.8 3.3
I2C2 clock domain 1.0 0.9 0.9
I2C3 independent clock domain 2.8 2.3 2.4
I2C3 clock domain 0.9 0.4 0.7
LPUART1 independent clock
domain 1.8 1.6 1.7
LPUART1 clock domain 0.6 0.6 1.7
LPTIM1 independent clock
domain 2.8 2.3 2.7
LPTIM1 clock domain 0.8 0.4 0.7
LPTIM2 independent clock
domain 2.9 2.6 3.8
LPTIM2 clock domain 0.8 0.7 0.8
OPAMP 0.4 0.2 0.4
PWR 0.4 0.1 0.4
SPI2 1.7 1.5 1.5
SPI3 1.7 1.4 1.5
TIM2 6.2 5.0 5.8
TIM6 1.0 0.6 0.9
USART2 independent clock
domain 4.0 3.5 3.7
USART2 clock domain 1.3 0.8 1.1
USART3 independent clock
domain 4.2 3.4 4.1
USART3 clock domain 1.5 1.1 1.3
WWDG 0.5 0.5 0.5
All APB1 on 41.4 28.5 38.9
Table 49. Peripheral current consumption (continued)
Peripheral Range 1 Range 2 Low-power run
and sleep Unit
Electrical characteristics STM32L422xx
112/194 DS12470 Rev 2
The consumption for the peripherals when using SMPS can be found using STM32CubeMX
PCC tool.
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 50 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
APB2
AHB to APB2(4) 1.0 0.9 0.9
µA/MHz
FW 0.2 0.2 0.2
SPI1 1.7 1.6 1.7
SYSCFG/COMP 0.6 0.5 0.6
TIM1 8.1 6.4 7.6
TIM15 3.7 3.0 3.4
TIM16 2.6 2.1 2.5
USART1 independent clock
domain 4.1 4.1 4.4
USART1 clock domain 1.5 1.2 1.6
All APB2 on 19.2 16.1 17.8
ALL 82.5 63.8 77.2
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
Table 49. Peripheral current consumption (continued)
Peripheral Range 1 Range 2 Low-power run
and sleep Unit
Table 50. Low-power mode wakeup timings(1)
Symbol Parameter Conditions Typ Max Unit
tWUSLEEP
Wakeup time from Sleep
mode to Run mode -66
Nb of
CPU
cycles
tWULPSLEEP
Wakeup time from Low-
power sleep mode to Low-
power run mode
Wakeup in Flash with Flash in power-down
during low-power sleep mode (SLEEP_PD=1 in
FLASH_ACR) and with clock MSI = 2 MHz
68.3
DS12470 Rev 2 113/194
STM32L422xx Electrical characteristics
165
tWUSTOP0
Wake up time from Stop 0
mode to Run mode in
Flash
Range 1
Wakeup clock MSI = 48 MHz 3.8 5.7
µs
Wakeup clock HSI16 = 16 MHz 4.1 6.9
Range 2
Wakeup clock MSI = 24 MHz 4.07 6.2
Wakeup clock HSI16 = 16 MHz 4.1 6.8
Wakeup clock MSI = 4 MHz 8.45 11.8
Wake up time from Stop 0
mode to Run mode in
SRAM1
Range 1
Wakeup clock MSI = 48 MHz 1.5 2.9
Wakeup clock HSI16 = 16 MHz 2.4 2.76
Range 2
Wakeup clock MSI = 24 MHz 2.4 3.48
Wakeup clock HSI16 = 16 MHz 2.4 2.76
Wakeup clock MSI = 4 MHz 8.16 10.94
tWUSTOP1
Wake up time from Stop 1
mode to Run in Flash
Range 1
Wakeup clock MSI = 48 MHz 6.34 7.86
µs
Wakeup clock HSI16 = 16 MHz 6.84 8.23
Range 2
Wakeup clock MSI = 24 MHz 6.74 8.1
Wakeup clock HSI16 = 16 MHz 6.89 8.21
Wakeup clock MSI = 4 MHz 10.47 12.1
Wake up time from Stop 1
mode to Run mode in
SRAM1
Range 1
Wakeup clock MSI = 48 MHz 4.7 5.97
Wakeup clock HSI16 = 16 MHz 5.9 6.92
Range 2
Wakeup clock MSI = 24 MHz 5.4 6.51
Wakeup clock HSI16 = 16 MHz 5.9 6.92
Wakeup clock MSI = 4 MHz 11.1 12.2
Wake up time from Stop 1
mode to Low-power run
mode in Flash Regulator in
low-power
mode (LPR=1
in PWR_CR1)
Wakeup clock MSI = 2 MHz
16.4 17.73
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
17.3 18.82
Table 50. Low-power mode wakeup timings(1) (continued)
Symbol Parameter Conditions Typ Max Unit
Electrical characteristics STM32L422xx
114/194 DS12470 Rev 2
tWUSTOP2
Wake up time from Stop 2
mode to Run mode in
Flash
Range 1
Wakeup clock MSI = 48 MHz 8.02 9.24
µs
Wakeup clock HSI16 = 16 MHz 7.66 8.95
Range 2
Wakeup clock MSI = 24 MHz 8.5 9.54
Wakeup clock HSI16 = 16 MHz 7.75 8.95
Wakeup clock MSI = 4 MHz 12.06 13.16
Wake up time from Stop 2
mode to Run mode in
SRAM1
Range 1
Wakeup clock MSI = 48 MHz 5.45 6.79
Wakeup clock HSI16 = 16 MHz 6.9 7.98
Range 2
Wakeup clock MSI = 24 MHz 6.3 7.36
Wakeup clock HSI16 = 16 MHz 6.9 7.9
Wakeup clock MSI = 4 MHz 13.1 13.31
tWUSTBY
Wakeup time from Standby
mode to Run mode Range 1
Wakeup clock MSI = 8 MHz 12.2 18.35
µs
Wakeup clock MSI = 4 MHz 19.14 25.8
tWUSTBY
SRAM2
Wakeup time from Standby
with SRAM2 to Run mode Range 1
Wakeup clock MSI = 8 MHz 12.1 18.3
µs
Wakeup clock MSI = 4 MHz 19.2 25.87
tWUSHDN
Wakeup time from
Shutdown mode to Run
mode
Range 1 Wakeup clock MSI = 4 MHz 261.5 315.7 µs
1. Guaranteed by characterization results.
Table 50. Low-power mode wakeup timings(1) (continued)
Symbol Parameter Conditions Typ Max Unit
Table 51. Regulator modes transition times(1)
Symbol Parameter Conditions Typ Max Unit
tWULPRUN
Wakeup time from Low-power run mode to
Run mode(2) Code run with MSI 2 MHz 5 7
µs
tVOST
Regulator transition time from Range 2 to
Range 1 or Range 1 to Range 2(3) Code run with MSI 24 MHz 20 40
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
Table 52. Wakeup time using USART/LPUART(1)
Symbol Parameter Conditions Typ Max Unit
tWUUSART
tWULPUART
Wakeup time needed to calculate the
maximum USART/LPUART baudrate
allowing to wakeup up from stop mode
when USART/LPUART clock source is
HSI
Stop 0 mode - 1.7
µs
Stop 1 mode and Stop 2
mode -8.5
1. Guaranteed by design.
DS12470 Rev 2 115/194
STM32L422xx Electrical characteristics
165
6.3.7 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 20: High-speed external clock
source AC timing diagram.
Figure 20. High-speed external clock source AC timing diagram
Table 53. High-speed external user clock characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext User external clock source frequency
Voltage scaling
Range 1 -848
MHz
Voltage scaling
Range 2 -826
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx -V
DDIOx V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
Voltage scaling
Range 1 7- -
ns
Voltage scaling
Range 2 18 - -
1. Guaranteed by design.
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116/194 DS12470 Rev 2
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 21.
Figure 21. Low-speed external clock source AC timing diagram
Table 54. Low-speed external user clock characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User external clock source frequency - - 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx -V
DDIOx V
VLSEL OSC32_IN input pin low level voltage - VSS -0.3 V
DDIOx
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time - 250 - - ns
1. Guaranteed by design.
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DS12470 Rev 2 117/194
STM32L422xx Electrical characteristics
165
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 55. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 22). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Table 55. HSE oscillator characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions(2)
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 8 48 MHz
RFFeedback resistor - - 200 - k
IDD(HSE) HSE current consumption
During startup(3)
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
--5.5
mA
VDD = 3 V,
Rm = 30 ,
CL = 10 pF@8 MHz
-0.44-
VDD = 3 V,
Rm = 45 ,
CL = 10 pF@8 MHz
-0.45-
VDD = 3 V,
Rm = 30 ,
CL = 5 pF@48 MHz
-0.68-
VDD = 3 V,
Rm = 30 ,
CL = 10 pF@48 MHz
-0.94-
VDD = 3 V,
Rm = 30 ,
CL = 20 pF@48 MHz
-1.77-
Gm
Maximum critical crystal
transconductance Startup - - 1.5 mA/V
tSU(HSE)(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
Electrical characteristics STM32L422xx
118/194 DS12470 Rev 2
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 56. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Symbol Parameter Conditions(2) Min Typ Max Unit
IDD(LSE) LSE current consumption
LSEDRV[1:0] = 00
Low drive capability -250-
nA
LSEDRV[1:0] = 01
Medium low drive capability -315-
LSEDRV[1:0] = 10
Medium high drive capability -500-
LSEDRV[1:0] = 11
High drive capability -630-
Gmcritmax
Maximum critical crystal
gm
LSEDRV[1:0] = 00
Low drive capability --0.5
µA/V
LSEDRV[1:0] = 01
Medium low drive capability - - 0.75
LSEDRV[1:0] = 10
Medium high drive capability --1.7
LSEDRV[1:0] = 11
High drive capability --2.7
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
DS12470 Rev 2 119/194
STM32L422xx Electrical characteristics
165
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 23. Typical application with a 32.768 kHz crystal
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
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Electrical characteristics STM32L422xx
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6.3.8 Internal clock source characteristics
The parameters given in Table 57 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 57. HSI16 oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz
TRIM HSI16 user trimming step
Trimming code is not a
multiple of 64 0.2 0.3 0.4
%
Trimming code is a
multiple of 64 -4 -6 -8
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
Tem p(HSI16) HSI16 oscillator frequency
drift over temperature
TA= 0 to 85 °C -1 - 1 %
TA= -40 to 125 °C -2 - 1.5 %
VDD(HSI16) HSI16 oscillator frequency
drift over VDD
VDD=1.62 V to 3.6 V -0.1 - 0.05 %
tsu(HSI16)(2) HSI16 oscillator start-up
time --0.81.2s
tstab(HSI16)(2) HSI16 oscillator
stabilization time --35s
IDD(HSI16)(2) HSI16 oscillator power
consumption - - 155 190 A
1. Guaranteed by characterization results.
2. Guaranteed by design.
DS12470 Rev 2 121/194
STM32L422xx Electrical characteristics
165
Figure 24. HSI16 frequency versus temperature
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Electrical characteristics STM32L422xx
122/194 DS12470 Rev 2
Multi-speed internal (MSI) RC oscillator
Table 58. MSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fMSI
MSI frequency
after factory
calibration, done
at VDD=3 V and
TA=30 °C
MSI mode
Range 0 98.7 100 101.3
kHz
Range 1 197.4 200 202.6
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
MHz
Range 5 1.974 2 2.026
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31
Range 10 31.58 32 32.42
Range 11 47.38 48 48.62
PLL mode
XTAL=
32.768 kHz
Range 0 - 98.304 -
kHz
Range 1 - 196.608 -
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
MHz
Range 5 - 1.999 -
Range 6 - 3.998 -
Range 7 - 7.995 -
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
TEMP(MSI)(2)
MSI oscillator
frequency drift
over temperature
MSI mode
TA= -0 to 85 °C -3.5 - 3
%
TA= -40 to 125 °C -8 - 6
DS12470 Rev 2 123/194
STM32L422xx Electrical characteristics
165
VDD(MSI)(2)
MSI oscillator
frequency drift
over VDD
(reference is 3 V)
MSI mode
Range 0 to 3
VDD=1.62 V
to 3.6 V -1.2 -
0.5
%
VDD=2.4 V
to 3.6 V -0.5 -
Range 4 to 7
VDD=1.62 V
to 3.6 V -2.5 -
0.7
VDD=2.4 V
to 3.6 V -0.8 -
Range 8 to 11
VDD=1.62 V
to 3.6 V -5 -
1
VDD=2.4 V
to 3.6 V -1.6 -
FSAMPLING
(MSI)(2)(6)
Frequency
variation in
sampling mode(3)
MSI mode
TA= -40 to 85 °C - 1 2
%
TA= -40 to 125 °C - 2 4
P_USB
Jitter(MSI)(6)
Period jitter for
USB clock(4)
PLL mode
Range 11
for next
transition ---3.458
ns
for paired
transition ---3.916
MT_USB
Jitter(MSI)(6)
Medium term jitter
for USB clock(5)
PLL mode
Range 11
for next
transition ---2
ns
for paired
transition ---1
CC jitter(MSI)(6) RMS cycle-to-
cycle jitter PLL mode Range 11 - - 60 - ps
P jitter(MSI)(6) RMS Period jitter PLL mode Range 11 - - 50 - ps
tSU(MSI)(6) MSI oscillator
start-up time
Range 0 - - 10 20
us
Range 1 - - 5 10
Range 2 - - 4 8
Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
tSTAB(MSI)(6) MSI oscillator
stabilization time
PLL mode
Range 11
10 % of final
frequency - - 0.25 0.5
ms
5 % of final
frequency --0.51.25
1 % of final
frequency ---2.5
Table 58. MSI oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L422xx
124/194 DS12470 Rev 2
IDD(MSI)(6)
MSI oscillator
power
consumption
MSI and
PLL mode
Range 0 - - 0.6 1
µA
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
Range 5 - - 6.5 9
Range 6 - - 11 15
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI @48 MHz clock.
5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28
cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over
56 cycles.
6. Guaranteed by design.
Table 58. MSI oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DS12470 Rev 2 125/194
STM32L422xx Electrical characteristics
165
Figure 25. Typical current consumption versus MSI frequency
High-speed internal 48 MHz (HSI48) RC oscillator
Table 59. HSI48 oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSI48 HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz
TRIM HSI48 user trimming step - - 0.11(2) 0.18(2) %
USER TRIM
COVERAGE HSI48 user trimming coverage ±32 steps ±3(3) ±3.5(3) -%
DuCy(HSI48) Duty Cycle - 45(2) -55
(2) %
ACCHSI48_REL
Accuracy of the HSI48 oscillator
over temperature (factory
calibrated)
VDD = 3.0 V to 3.6 V,
TA = –15 to 85 °C --±3
(3)
%
VDD = 1.65 V to 3.6 V,
TA = –40 to 125 °C --±4.5
(3)
DVDD(HSI48) HSI48 oscillator frequency drift
with VDD
VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)
%
VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)
tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) s
IDD(HSI48) HSI48 oscillator power
consumption --340
(2) 380(2) A
Electrical characteristics STM32L422xx
126/194 DS12470 Rev 2
Figure 26. HSI48 frequency versus temperature
Low-speed internal (LSI) RC oscillator
NT jitter Next transition jitter
Accumulated jitter on 28 cycles(4) --+/-0.15
(2) -ns
PT jitter Paired transition jitter
Accumulated jitter on 56 cycles(4) --+/-0.25
(2) -ns
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
Table 59. HSI48 oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Table 60. LSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fLSI LSI Frequency
VDD = 3.0 V, TA = 30 °C 31.04 - 32.96
kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34
tSU(LSI)(2) LSI oscillator start-
up time --80130s
tSTAB(LSI)(2) LSI oscillator
stabilization time 5% of final frequency - 125 180 s
IDD(LSI)(2) LSI oscillator power
consumption --110180nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
DS12470 Rev 2 127/194
STM32L422xx Electrical characteristics
165
6.3.9 PLL characteristics
The parameters given in Table 61 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 21: General operating conditions.
Table 61. PLL characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN
PLL input clock(2) -4-16MHz
PLL input clock duty cycle - 45 - 55 %
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 1 3.0968 - 80
MHz
Voltage scaling Range 2 3.0968 - 26
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 1 12 - 80
MHz
Voltage scaling Range 2 12 - 26
fPLL_R_OUT PLL multiplier output clock R
Voltage scaling Range 1 12 - 80
MHz
Voltage scaling Range 2 12 - 26
fVCO_OUT PLL VCO output
Voltage scaling Range 1 96 - 344
MHz
Voltage scaling Range 2 96 - 128
tLOCK PLL lock time - - 15 40 s
Jitter
RMS cycle-to-cycle jitter
System clock 80 MHz
-40-
±ps
RMS period jitter - 30 -
IDD(PLL) PLL power consumption on
VDD(1)
VCO freq = 96 MHz - 200 260
AVCO freq = 192 MHz - 300 380
VCO freq = 344 MHz - 520 650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 2 PLLs.
Electrical characteristics STM32L422xx
128/194 DS12470 Rev 2
6.3.10 Flash memory characteristics
Table 62. Flash memory characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Typ Max Unit
tprog 64-bit programming time - 81.69 90.76 µs
tprog_row
one row (32 double
word) programming time
normal programming 2.61 2.90
ms
fast programming 1.91 2.12
tprog_page
one page (2 Kbyte)
programming time
normal programming 20.91 23.24
fast programming 15.29 16.98
tERASE Page (2 KB) erase time - 22.02 24.47
tprog_bank
one bank (512 Kbyte)
programming time
normal programming 5.35 5.95
s
fast programming 3.91 4.35
tME
Mass erase time
(one or two banks) - 22.13 24.59 ms
IDD
Average consumption
from VDD
Write mode 3.4 -
mA
Erase mode 3.4 -
Maximum current (peak)
Write mode 7 (for 2 s) -
Erase mode 7 (for 41 s) -
Table 63. Flash memory endurance and data retention
Symbol Parameter Conditions Min(1)
1. Guaranteed by characterization results.
Unit
NEND Endurance TA = –40 to +105 °C 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Yea rs
1 kcycle(2) at TA = 105 °C 15
1 kcycle(2) at TA = 125 °C 7
10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10
DS12470 Rev 2 129/194
STM32L422xx Electrical characteristics
165
6.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 64. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Table 64. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 80 MHz,
conforming to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 80 MHz,
conforming to IEC 61000-4-4
5A
Electrical characteristics STM32L422xx
130/194 DS12470 Rev 2
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
6.3.12 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 65. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fHSE/fHCLK]Unit
8 MHz/ 80 MHz
SEMI Peak level
VDD = 3.6 V, TA = 25 °C,
LQFP100 package
compliant with IEC
61967-2
0.1 MHz to 30 MHz 3
dBµV
30 MHz to 130 MHz 3
130 MHz to 1 GHz 4
1 GHz to 2 GHz 8
EMI Level 2.5 -
Table 66. ESD absolute maximum ratings
Symbol Ratings Conditions Package Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming
to ANSI/ESDA/JEDEC
JS-001
All 2 2000
V
VESD
Electrostatic discharge voltage
(charge device model)
TA = +25 °C,
conforming to
ANSI/ESDA/JEDEC-002
BGA64 C2a 500
All others C1 250
1. Guaranteed by characterization results.
DS12470 Rev 2 131/194
STM32L422xx Electrical characteristics
165
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 68.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 67. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II
Table 68. I/O current injection susceptibility(1)
1. Guaranteed by characterization results.
Symbol Description
Functional
susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on all pins except PA4, PA5 -5 N/A(2)
2. Injection is not possible.
mA
Injected current on PA4, PA5 pins -5 0
Electrical characteristics STM32L422xx
132/194 DS12470 Rev 2
6.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 69. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(1)
I/O input low level
voltage 1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx (2)
V
I/O input low level
voltage 1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06 (3)
I/O input low level
voltage 1.08 V<VDDIOx<1.62 V - - 0.43xVDDIOx-0.1 (3)
VIH(1)
I/O input high level
voltage 1.62 V<VDDIOx<3.6 V 0.7xVDDIOx (2) --
V
I/O input high level
voltage 1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26 (3) --
I/O input high level
voltage 1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05 (3) --
Vhys(3)
TT_xx, FT_xxx and
NRST I/O input
hysteresis
1.62 V<VDDIOx<3.6 V - 200 - mV
Ilkg(4)
FT_xx input leakage
current(3)(5)
VIN
Max(VDDXXX)(6)(7) --±100
nA
Max(VDDXXX) VIN
Max(VDDXXX)+1 V(6)(7) - - 650
Max(VDDXXX)+1 V <
VIN 5.5 V(6)(7) - - 200
FT_u and PC3 I/O
VIN
Max(VDDXXX)(6)(7) --±150
Max(VDDXXX) VIN
Max(VDDXXX)+1 V(6)(7) - - 2500(3)
Max(VDDXXX)+1 V <
VIN 5.5 V(6)(7) - - 250
TT_xx input leakage
current
VIN Max(VDDXXX)(6) --±150
Max(VDDXXX) VIN <
3.6 V(6) - - 2000(3)
RPU
Weak pull-up
equivalent resistor (8) VIN = VSS 25 40 55 k
RPD
Weak pull-down
equivalent resistor(8) VIN = VDDIOx 25 40 55 k
CIO I/O pin capacitance - - 5 - pF
DS12470 Rev 2 133/194
STM32L422xx Electrical characteristics
165
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 27 for standard I/Os, and in Figure 27 for
5 V tolerant I/Os.
Figure 27. I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
1. Refer to Figure 27: I/O input characteristics.
2. Tested in production.
3. Guaranteed by design.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITo t al _Il ea k_ m ax = 10 µA + [number of IOs where VIN is applied on the pad] Ilkg(Max).
5. All FT_xx GPIOs except FT_u and PC3 I/O.
6. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
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Electrical characteristics STM32L422xx
134/194 DS12470 Rev 2
IVDD (see Table 18: Voltage characteristics).
The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see
Table 18: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 28 and
Table 71, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 70. Output voltage characteristics(1)
Symbol Parameter Conditions Min Max Unit
VOL Output low level voltage for an I/O pin CMOS port(2)
|IIO| = 8 mA
VDDIOx 2.7 V
-0.4
V
VOH Output high level voltage for an I/O pin VDDIOx-0.4 -
VOL(3) Output low level voltage for an I/O pin TTL port(2)
|IIO| = 8 mA
VDDIOx 2.7 V
-0.4
VOH(3) Output high level voltage for an I/O pin 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA
VDDIOx 2.7 V
-1.3
VOH(3) Output high level voltage for an I/O pin VDDIOx-1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 4 mA
VDDIOx 1.62 V
-0.45
VOH(3) Output high level voltage for an I/O pin VDDIOx-0.45 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 2 mA
1.62 V VDDIOx 1.08 V
-0.35VDDIOx
VOH(3) Output high level voltage for an I/O pin 0.65VDDIOx -
VOLFM+
(3)
Output low level voltage for an FT I/O
pin in FM+ mode (FT I/O with "f"
option)
|IIO| = 20 mA
VDDIOx 2.7 V -0.4
|IIO| = 10 mA
VDDIOx 1.62 V -0.4
|IIO| = 2 mA
1.62 V VDDIOx 1.08 V -0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
DS12470 Rev 2 135/194
STM32L422xx Electrical characteristics
165
Table 71. I/O AC characteristics(1)(2)
Speed Symbol Parameter Conditions Min Max Unit
00
Fmax Maximum frequency
C=50 pF, 2.7 VVDDIOx3.6 V - 5
MHz
C=50 pF, 1.62 VVDDIOx2.7 V - 1
C=50 pF, 1.08 VVDDIOx1.62 V - 0.1
C=10 pF, 2.7 VVDDIOx3.6 V - 10
C=10 pF, 1.62 VVDDIOx2.7 V - 1.5
C=10 pF, 1.08 VVDDIOx1.62 V - 0.1
Tr/Tf Output rise and fall time
C=50 pF, 2.7 VVDDIOx3.6 V - 25
ns
C=50 pF, 1.62 VVDDIOx2.7 V - 52
C=50 pF, 1.08 VVDDIOx1.62 V - 140
C=10 pF, 2.7 VVDDIOx3.6 V - 17
C=10 pF, 1.62 VVDDIOx2.7 V - 37
C=10 pF, 1.08 VVDDIOx1.62 V - 110
01
Fmax Maximum frequency
C=50 pF, 2.7 VVDDIOx3.6 V - 25
MHz
C=50 pF, 1.62 VVDDIOx2.7 V - 10
C=50 pF, 1.08 VVDDIOx1.62 V - 1
C=10 pF, 2.7 VVDDIOx3.6 V - 50
C=10 pF, 1.62 VVDDIOx2.7 V - 15
C=10 pF, 1.08 VVDDIOx1.62 V - 1
Tr/Tf Output rise and fall time
C=50 pF, 2.7 VVDDIOx3.6 V - 9
ns
C=50 pF, 1.62 VVDDIOx2.7 V - 16
C=50 pF, 1.08 VVDDIOx1.62 V - 40
C=10 pF, 2.7 VVDDIOx3.6 V - 4.5
C=10 pF, 1.62 VVDDIOx2.7 V - 9
C=10 pF, 1.08 VVDDIOx1.62 V - 21
Electrical characteristics STM32L422xx
136/194 DS12470 Rev 2
10
Fmax Maximum frequency
C=50 pF, 2.7 VVDDIOx3.6 V - 50
MHz
C=50 pF, 1.62 VVDDIOx2.7 V - 25
C=50 pF, 1.08 VVDDIOx1.62 V - 5
C=10 pF, 2.7 VVDDIOx3.6 V - 100(3)
C=10 pF, 1.62 VVDDIOx2.7 V - 37.5
C=10 pF, 1.08 VVDDIOx1.62 V - 5
Tr/Tf Output rise and fall time
C=50 pF, 2.7 VVDDIOx3.6 V - 5.8
ns
C=50 pF, 1.62 VVDDIOx2.7 V - 11
C=50 pF, 1.08 VVDDIOx1.62 V - 28
C=10 pF, 2.7 VVDDIOx3.6 V - 2.5
C=10 pF, 1.62 VVDDIOx2.7 V - 5
C=10 pF, 1.08 VVDDIOx1.62 V - 12
11
Fmax Maximum frequency
C=30 pF, 2.7 VVDDIOx3.6 V - 120(3)
MHz
C=30 pF, 1.62 VVDDIOx2.7 V - 50
C=30 pF, 1.08 VVDDIOx1.62 V - 10
C=10 pF, 2.7 VVDDIOx3.6 V - 180(3)
C=10 pF, 1.62 VVDDIOx2.7 V - 75
C=10 pF, 1.08 VVDDIOx1.62 V - 10
Tr/Tf Output rise and fall time
C=30 pF, 2.7 VVDDIOx3.6 V - 3.3
nsC=30 pF, 1.62 VVDDIOx2.7 V - 6
C=30 pF, 1.08 VVDDIOx1.62 V - 16
Fm+
Fmax Maximum frequency
C=50 pF, 1.6 VVDDIOx3.6 V
-1MHz
Tf Output fall time(4) -5ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0394 reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
Table 71. I/O AC characteristics(1)(2) (continued)
Speed Symbol Parameter Conditions Min Max Unit
DS12470 Rev 2 137/194
STM32L422xx Electrical characteristics
165
Figure 28. I/O AC characteristics definition(1)
1. Refer to Table 71: I/O AC characteristics.
6.3.15 NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
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Table 72. NRST pin characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)
NRST input low level
voltage ---0.3VDDIOx
V
VIH(NRST)
NRST input high level
voltage -0.7VDDIOx --
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis --200-mV
RPU
Weak pull-up
equivalent resistor(2) VIN = VSS 25 40 55 k
VF(NRST) NRST input filtered
pulse ---70ns
VNF(NRST)
NRST input not filtered
pulse 1.71 V VDD 3.6 V 350 - - ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
Electrical characteristics STM32L422xx
138/194 DS12470 Rev 2
Figure 29. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 72: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.16 Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
6.3.17 Analog switches booster
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Table 73. EXTI Input Characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
PLEC Pulse length to event
controller -20--ns
Table 74. Analog switches booster characteristics(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 - 3.6 V
tSU(BOOST) Booster startup time - - 240 µs
IDD(BOOST)
Booster consumption for
1.62 V VDD 2.0 V --250
µA
Booster consumption for
2.0 V VDD 2.7 V --500
Booster consumption for
2.7 V VDD 3.6 V --900
DS12470 Rev 2 139/194
STM32L422xx Electrical characteristics
165
6.3.18 Analog-to-Digital converter characteristics
Unless otherwise specified, the parameters given in Table 75 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 21: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 75. ADC characteristics(1) (2)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.62 - 3.6 V
VREF+ Positive reference voltage
VDDA 2 V 2 - VDDA V
VDDA < 2 V VDDA V
VREF-
Negative reference
voltage -V
SSA V
fADC ADC clock frequency
Range 1 0.14 - 80
MHz
Range 2 0.14 - 26
fs
Sampling rate for FAST
channels
Resolution = 12 bits - - 5.33
Msps
Resolution = 10 bits - - 6.15
Resolution = 8 bits - - 7.27
Resolution = 6 bits - - 8.88
Sampling rate for SLOW
channels
Resolution = 12 bits - - 4.21
Resolution = 10 bits - - 4.71
Resolution = 8 bits - - 5.33
Resolution = 6 bits - - 6.15
fTRIG External trigger frequency
fADC = 80 MHz
Resolution = 12 bits - - 5.33 MHz
Resolution = 12 bits - - 15 1/fADC
VCMIN Input common mode Differential mode
(VREF++
VREF-)/2
- 0.18
(VREF++
VREF-)/2
(VREF++
VREF-)/2
+ 0.18
V
VAIN (3) Conversion voltage
range(2) -0-V
REF+ V
RAIN External input impedance - - - 50 k
CADC
Internal sample and hold
capacitor --5-pF
tSTAB Power-up time - 1 conversion
cycle
tCAL Calibration time
fADC = 80 MHz 1.45 µs
-1161/f
ADC
Electrical characteristics STM32L422xx
140/194 DS12470 Rev 2
The maximum value of RAIN can be found in Table 76: Maximum ADC RAIN.
tLATR
Trigger conversion
latency Regular and
injected channels without
conversion abort
CKMODE = 00 1.5 2 2.5
1/fADC
CKMODE = 01 - - 2.0
CKMODE = 10 - - 2.25
CKMODE = 11 - - 2.125
tLATRINJ
Trigger conversion
latency Injected channels
aborting a regular
conversion
CKMODE = 00 2.5 3 3.5
1/fADC
CKMODE = 01 - - 3.0
CKMODE = 10 - - 3.25
CKMODE = 11 - - 3.125
tsSampling time
fADC = 80 MHz 0.03125 - 8.00625 µs
- 2.5 - 640.5 1/fADC
tADCVREG_STUP
ADC voltage regulator
start-up time ---20
µs
tCONV
Total conversion time
(including sampling time)
fADC = 80 MHz
Resolution = 12 bits 0.1875 - 8.1625 µs
Resolution = 12 bits
ts + 12.5 cycles for
successive approximation
= 15 to 653
1/fADC
IDDA(ADC) ADC consumption from
the VDDA supply
fs = 5 Msps - 730 830
µAfs = 1 Msps - 160 220
fs = 10 ksps - 16 50
IDDV_S(ADC)
ADC consumption from
the VREF+ single ended
mode
fs = 5 Msps - 130 160
µAfs = 1 Msps - 30 40
fs = 10 ksps - 0.6 2
IDDV_D(ADC)
ADC consumption from
the VREF+ differential
mode
fs = 5 Msps - 260 310
µAfs = 1 Msps - 60 70
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
Table 75. ADC characteristics(1) (2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DS12470 Rev 2 141/194
STM32L422xx Electrical characteristics
165
Table 76. Maximum ADC RAIN(1)(2)
Resolution Sampling cycle
@80 MHz
Sampling time [ns]
@80 MHz
RAIN max ()
Fast channels(3) Slow channels(4)
12 bits
2.5 31.25 100 N/A
6.5 81.25 330 100
12.5 156.25 680 470
24.5 306.25 1500 1200
47.5 593.75 2200 1800
92.5 1156.25 4700 3900
247.5 3093.75 12000 10000
640.5 8006.75 39000 33000
10 bits
2.5 31.25 120 N/A
6.5 81.25 390 180
12.5 156.25 820 560
24.5 306.25 1500 1200
47.5 593.75 2200 1800
92.5 1156.25 5600 4700
247.5 3093.75 12000 10000
640.5 8006.75 47000 39000
8 bits
2.5 31.25 180 N/A
6.5 81.25 470 270
12.5 156.25 1000 680
24.5 306.25 1800 1500
47.5 593.75 2700 2200
92.5 1156.25 6800 5600
247.5 3093.75 15000 12000
640.5 8006.75 50000 50000
6 bits
2.5 31.25 220 N/A
6.5 81.25 560 330
12.5 156.25 1200 1000
24.5 306.25 2700 2200
47.5 593.75 3900 3300
92.5 1156.25 8200 6800
247.5 3093.75 18000 15000
640.5 8006.75 50000 50000
1. Guaranteed by design.
Electrical characteristics STM32L422xx
142/194 DS12470 Rev 2
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.
4. Slow channels are: all ADC inputs except the fast channels.
DS12470 Rev 2 143/194
STM32L422xx Electrical characteristics
165
Table 77. ADC accuracy - limited test conditions 1(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
Single
ended
Fast channel (max speed) - 4 5
LSB
Slow channel (max speed) - 4 5
Differential
Fast channel (max speed) - 3.5 4.5
Slow channel (max speed) - 3.5 4.5
EO Offset
error
Single
ended
Fast channel (max speed) - 1 2.5
Slow channel (max speed) - 1 2.5
Differential
Fast channel (max speed) - 1.5 2.5
Slow channel (max speed) - 1.5 2.5
EG Gain error
Single
ended
Fast channel (max speed) - 2.5 4.5
Slow channel (max speed) - 2.5 4.5
Differential
Fast channel (max speed) - 2.5 3.5
Slow channel (max speed) - 2.5 3.5
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1 1.5
Slow channel (max speed) - 1 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 1.5 2.5
Slow channel (max speed) - 1.5 2.5
Differential
Fast channel (max speed) - 1 2
Slow channel (max speed) - 1 2
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10.4 10.5 -
bits
Slow channel (max speed) 10.4 10.5 -
Differential
Fast channel (max speed) 10.8 10.9 -
Slow channel (max speed) 10.8 10.9 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 64.4 65 -
dB
Slow channel (max speed) 64.4 65 -
Differential
Fast channel (max speed) 66.8 67.4 -
Slow channel (max speed) 66.8 67.4 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 65 66 -
Slow channel (max speed) 65 66 -
Differential
Fast channel (max speed) 67 68 -
Slow channel (max speed) 67 68 -
Electrical characteristics STM32L422xx
144/194 DS12470 Rev 2
THD
To t a l
harmonic
distortion
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
Single
ended
Fast channel (max speed) - -74 -73
dB
Slow channel (max speed) - -74 -73
Differential
Fast channel (max speed) - -79 -76
Slow channel (max speed) - -79 -76
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 77. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
DS12470 Rev 2 145/194
STM32L422xx Electrical characteristics
165
Table 78. ADC accuracy - limited test conditions 2(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
2 V VDDA
Single
ended
Fast channel (max speed) - 4 6.5
LSB
Slow channel (max speed) - 4 6.5
Differential
Fast channel (max speed) - 3.5 5.5
Slow channel (max speed) - 3.5 5.5
EO Offset
error
Single
ended
Fast channel (max speed) - 1 4.5
Slow channel (max speed) - 1 5
Differential
Fast channel (max speed) - 1.5 3
Slow channel (max speed) - 1.5 3
EG Gain error
Single
ended
Fast channel (max speed) - 2.5 6
Slow channel (max speed) - 2.5 6
Differential
Fast channel (max speed) - 2.5 3.5
Slow channel (max speed) - 2.5 3.5
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1 1.5
Slow channel (max speed) - 1 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 1.5 3.5
Slow channel (max speed) - 1.5 3.5
Differential
Fast channel (max speed) - 1 3
Slow channel (max speed) - 1 2.5
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10 10.5 -
bits
Slow channel (max speed) 10 10.5 -
Differential
Fast channel (max speed) 10.7 10.9 -
Slow channel (max speed) 10.7 10.9 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 62 65 -
dB
Slow channel (max speed) 62 65 -
Differential
Fast channel (max speed) 66 67.4 -
Slow channel (max speed) 66 67.4 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 64 66 -
Slow channel (max speed) 64 66 -
Differential
Fast channel (max speed) 66.5 68 -
Slow channel (max speed) 66.5 68 -
Electrical characteristics STM32L422xx
146/194 DS12470 Rev 2
THD
To t a l
harmonic
distortion
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
2 V VDDA
Single
ended
Fast channel (max speed) - -74 -65
dB
Slow channel (max speed) - -74 -67
Differential
Fast channel (max speed) - -79 -70
Slow channel (max speed) - -79 -71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 78. ADC accuracy - limited test conditions 2(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
DS12470 Rev 2 147/194
STM32L422xx Electrical characteristics
165
Table 79. ADC accuracy - limited test conditions 3(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 1
Single
ended
Fast channel (max speed) - 5.5 7.5
LSB
Slow channel (max speed) - 4.5 6.5
Differential
Fast channel (max speed) - 4.5 7.5
Slow channel (max speed) - 4.5 5.5
EO Offset
error
Single
ended
Fast channel (max speed) - 2 5
Slow channel (max speed) - 2.5 5
Differential
Fast channel (max speed) - 2 3.5
Slow channel (max speed) - 2.5 3
EG Gain error
Single
ended
Fast channel (max speed) - 4.5 7
Slow channel (max speed) - 3.5 6
Differential
Fast channel (max speed) - 3.5 4
Slow channel (max speed) - 3.5 5
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1.2 1.5
Slow channel (max speed) - 1.2 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 3 3.5
Slow channel (max speed) - 2.5 3.5
Differential
Fast channel (max speed) - 2 2.5
Slow channel (max speed) - 2 2.5
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10 10.4 -
bits
Slow channel (max speed) 10 10.4 -
Differential
Fast channel (max speed) 10.6 10.7 -
Slow channel (max speed) 10.6 10.7 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 62 64 -
dB
Slow channel (max speed) 62 64 -
Differential
Fast channel (max speed) 65 66 -
Slow channel (max speed) 65 66 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 63 65 -
Slow channel (max speed) 63 65 -
Differential
Fast channel (max speed) 66 67 -
Slow channel (max speed) 66 67 -
Electrical characteristics STM32L422xx
148/194 DS12470 Rev 2
THD
To t a l
harmonic
distortion
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 1
Single
ended
Fast channel (max speed) - -69 -67
dB
Slow channel (max speed) - -71 -67
Differential
Fast channel (max speed) - -72 -71
Slow channel (max speed) - -72 -71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 79. ADC accuracy - limited test conditions 3(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
DS12470 Rev 2 149/194
STM32L422xx Electrical characteristics
165
Table 80. ADC accuracy - limited test conditions 4(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
26 MHz,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 2
Single
ended
Fast channel (max speed) - 5 5.4
LSB
Slow channel (max speed) - 4 5
Differential
Fast channel (max speed) - 4 5
Slow channel (max speed) - 3.5 4.5
EO Offset
error
Single
ended
Fast channel (max speed) - 2 4
Slow channel (max speed) - 2 4
Differential
Fast channel (max speed) - 2 3.5
Slow channel (max speed) - 2 3.5
EG Gain error
Single
ended
Fast channel (max speed) - 4 4.5
Slow channel (max speed) - 4 4.5
Differential
Fast channel (max speed) - 3 4
Slow channel (max speed) - 3 4
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1 1.5
Slow channel (max speed) - 1 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 2.5 3
Slow channel (max speed) - 2.5 3
Differential
Fast channel (max speed) - 2 2.5
Slow channel (max speed) - 2 2.5
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10.2 10.5 -
bits
Slow channel (max speed) 10.2 10.5 -
Differential
Fast channel (max speed) 10.6 10.7 -
Slow channel (max speed) 10.6 10.7 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 63 65 -
dB
Slow channel (max speed) 63 65 -
Differential
Fast channel (max speed) 65 66 -
Slow channel (max speed) 65 66 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 64 65 -
Slow channel (max speed) 64 65 -
Differential
Fast channel (max speed) 66 67 -
Slow channel (max speed) 66 67 -
Electrical characteristics STM32L422xx
150/194 DS12470 Rev 2
Figure 30. ADC accuracy characteristics
THD
To t a l
harmonic
distortion
ADC clock frequency
26 MHz,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 2
Single
ended
Fast channel (max speed) - -71 -69
dB
Slow channel (max speed) - -71 -69
Differential
Fast channel (max speed) - -73 -72
Slow channel (max speed) - -73 -72
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 80. ADC accuracy - limited test conditions 4(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
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STM32L422xx Electrical characteristics
165
Figure 31. Typical connection diagram using the ADC
1. Refer to Table 75: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 69: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 69: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 17: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
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Electrical characteristics STM32L422xx
152/194 DS12470 Rev 2
6.3.19 Comparator characteristics
Table 81. COMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.62 - 3.6
VVIN
Comparator input voltage
range -0-V
DDA
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
IDDA(SCALER) Scaler static consumption
from VDDA
BRG_EN=0 (bridge disable) - 200 300 nA
BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
tSTART
Comparator startup time to
reach propagation delay
specification
High-speed
mode
VDDA 2.7 V - - 5
µs
VDDA < 2.7 V - - 7
Medium mode
VDDA 2.7 V - - 15
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 40
tD(3) Propagation delay with
100 mV overdrive
High-speed
mode
VDDA 2.7 V - 55 80
ns
VDDA < 2.7 V - 65 100
Medium mode - 0.55 0.9
µs
Ultra-low-power mode - 4 7
Voffset Comparator offset error Full common
mode range --±5±20mV
Vhys Comparator hysteresis
No hysteresis - 0 -
mV
Low hysteresis - 8 -
Medium hysteresis - 15 -
High hysteresis - 27 -
DS12470 Rev 2 153/194
STM32L422xx Electrical characteristics
165
6.3.20 Operational amplifiers characteristics
IDDA(COMP) Comparator consumption
from VDDA
Ultra-low-
power mode
Static - 400 600
nA
With 50 kHz
±100 mV overdrive
square signal
-1200-
Medium mode
Static - 5 7
µA
With 50 kHz
±100 mV overdrive
square signal
-6-
High-speed
mode
Static - 70 100
With 50 kHz
±100 mV overdrive
square signal
-75-
Ibias
Comparator input bias
current ----
(4) nA
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 24: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 69: I/O static characteristics.
Table 81. COMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 82. OPAMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply
voltage(2) -1.8-3.6V
CMIR Common mode
input range -0-V
DDA V
VIOFFSET
Input offset
voltage
25 °C, No Load on output. - - ±1.5
mV
All voltage/Temp. - - ±3
VIOFFSET
Input offset
voltage drift
Normal mode - ±5 - V/°C
Low-power mode - ±10 -
TRIMOFFSETP
TRIMLPOFFSETP
Offset trim step
at low common
input voltage
(0.1 VDDA)
--0.81.1
mV
TRIMOFFSETN
TRIMLPOFFSETN
Offset trim step
at high common
input voltage
(0.9 VDDA)
--11.35
Electrical characteristics STM32L422xx
154/194 DS12470 Rev 2
ILOAD Drive current
Normal mode
VDDA 2 V
- - 500
µA
Low-power mode - - 100
ILOAD_PGA
Drive current in
PGA mode
Normal mode
VDDA 2 V
- - 450
Low-power mode - - 50
RLOAD
Resistive load
(connected to
VSSA or to
VDDA)
Normal mode
VDDA < 2 V
4--
k
Low-power mode 20 - -
RLOAD_PGA
Resistive load
in PGA mode
(connected to
VSSA or to
VDDA)
Normal mode
VDDA < 2 V
4.5 - -
Low-power mode 40 - -
CLOAD Capacitive load - - - 50 pF
CMRR Common mode
rejection ratio
Normal mode - -85 -
dB
Low-power mode - -90 -
PSRR Power supply
rejection ratio
Normal mode CLOAD 50 pf,
RLOAD 4 k DC 70 85 -
dB
Low-power mode CLOAD 50 pf,
RLOAD 20 k DC 72 90 -
GBW Gain Bandwidth
Product
Normal mode VDDA 2.4 V
(OPA_RANGE = 1)
550 1600 2200
kHz
Low-power mode 100 420 600
Normal mode VDDA < 2.4 V
(OPA_RANGE = 0)
250 700 950
Low-power mode 40 180 280
SR(3)
Slew rate
(from 10 and
90% of output
voltage)
Normal mode
VDDA 2.4 V
-700-
V/ms
Low-power mode - 180 -
Normal mode
VDDA < 2.4 V
-300-
Low-power mode - 80 -
AO Open loop gain
Normal mode 55 110 -
dB
Low-power mode 45 110 -
VOHSAT(3) High saturation
voltage
Normal mode
Iload = max or Rload =
min Input at VDDA.
VDDA -
100 --
mV
Low-power mode VDDA -
50 --
VOLSAT(3) Low saturation
voltage
Normal mode Iload = max or Rload =
min Input at 0.
- - 100
Low-power mode - - 50
mPhase margin
Normal mode - 74 -
°
Low-power mode - 66 -
Table 82. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DS12470 Rev 2 155/194
STM32L422xx Electrical characteristics
165
GM Gain margin
Normal mode - 13 -
dB
Low-power mode - 20 -
tWAKEUP
Wake up time
from OFF state.
Normal mode
CLOAD 50 pf,
RLOAD 4 k
follower
configuration
-510
µs
Low-power mode
CLOAD 50 pf,
RLOAD 20 k
follower
configuration
-1030
Ibias
OPAMP input
bias current General purpose input - - -(4) nA
PGA gain(3) Non inverting
gain value -
-2-
-
-4-
-8-
-16-
Rnetwork
R2/R1 internal
resistance
values in PGA
mode(5)
PGA Gain = 2 - 80/80 -
k/k
PGA Gain = 4 - 120/
40 -
PGA Gain = 8 - 140/
20 -
PGA Gain = 16 - 150/
10 -
Delta R
Resistance
variation (R1 or
R2)
--15-15%
PGA gain error PGA gain error - -1 - 1 %
PGA BW
PGA bandwidth
for different non
inverting gain
Gain = 2 - - GBW/
2-
MHz
Gain = 4 - - GBW/
4-
Gain = 8 - - GBW/
8-
Gain = 16 - - GBW/
16 -
Table 82. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L422xx
156/194 DS12470 Rev 2
6.3.21 Temperature sensor characteristics
en Voltage noise
density
Normal mode at 1 kHz, Output
loaded with 4 k-500-
nV/Hz
Low-power mode at 1 kHz, Output
loaded with 20 k-600-
Normal mode at 10 kHz, Output
loaded with 4 k-180-
Low-power mode at 10 kHz, Output
loaded with 20 k-290-
IDDA(OPAMP)(3)
OPAMP
consumption
from VDDA
Normal mode no Load, quiescent
mode
- 120 260
µA
Low-power mode - 45 100
1. Guaranteed by design, unless otherwise specified.
2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V
3. Guaranteed by characterization results.
4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 69: I/O static characteristics.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
Table 82. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 83. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1) VTS linearity with temperature - ±1 ±2 °C
Avg_Slope(2) Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) -815µs
tSTART(1) Start-up time when entering in continuous mode(4) -70120µs
tS_temp(1) ADC sampling time when reading the temperature 5 - - µs
IDD(TS)(1) Temperature sensor consumption from VDD, when
selected by ADC -4.77 µA
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 8:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
DS12470 Rev 2 157/194
STM32L422xx Electrical characteristics
165
6.3.22 VBAT monitoring characteristics
6.3.23 Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 84. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -39-k
QRatio on V
BAT measurement - 3 - -
Er(1)
1. Guaranteed by design.
Error on Q -10 - 10 %
tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs
Table 85. VBAT charging characteristics
Symbol Parameter Conditions Min Typ Max Unit
RBC
Battery
charging
resistor
VBRS = 0 - 5 -
k
VBRS = 1 - 1.5 -
Table 86. TIMx(1) characteristics
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
-1-t
TIMxCLK
fTIMxCLK = 80 MHz 12.5 - ns
fEXT
Timer external clock
frequency on CH1 to CH4
-0f
TIMxCLK/2 MHz
fTIMxCLK = 80 MHz 0 40 MHz
ResTIM Timer resolution
TIMx (except
TIM2) -16
bit
TIM2 - 32
tCOUNTER
16-bit counter clock
period
- 1 65536 tTIMxCLK
fTIMxCLK = 80 MHz 0.0125 819.2 µs
tMAX_COUNT
Maximum possible count
with 32-bit counter
- - 65536 × 65536 tTIMxCLK
fTIMxCLK = 80 MHz - 53.68 s
Electrical characteristics STM32L422xx
158/194 DS12470 Rev 2
6.3.24 Communication interfaces characteristics
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0394 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 87. IWDG min/max timeout period at 32 kHz (LSI)(1)
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF Unit
/4 0 0.125 512
ms
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
Table 88. WWDG min/max timeout value at 80 MHz (PCLK)
Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0512 3.2768
ms
2 1 0.1024 6.5536
4 2 0.2048 13.1072
8 3 0.4096 26.2144
DS12470 Rev 2 159/194
STM32L422xx Electrical characteristics
165
Table 89. I2C analog filter characteristics(1)
1. Guaranteed by design.
Symbol ParameterMinMaxUnit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
2. Spikes with widths below tAF(min) are filtered.
260(3)
3. Spikes with widths above tAF(max) are not filtered
ns
Electrical characteristics STM32L422xx
160/194 DS12470 Rev 2
SPI characteristics
Unless otherwise specified, the parameters given in Table 90 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 21: General operating conditions.
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 90. SPI characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode receiver/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
--
40
MHz
Master mode receiver/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
16
Master mode transmitter
1.71 < VDD < 3.6 V
Voltage Range 1
40
Slave mode receiver
1.71 < VDD < 3.6 V
Voltage Range 1
40
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
37(2)
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
20(2)
Voltage Range 2 13
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4TPCLK --ns
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2TPCLK --ns
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 ns
tsu(MI) Data input setup time
Master mode 4 - -
ns
tsu(SI) Slave mode 1.5 - -
th(MI) Data input hold time
Master mode 6.5 - -
ns
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 9 - 36 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
DS12470 Rev 2 161/194
STM32L422xx Electrical characteristics
165
Figure 32. SPI timing diagram - slave mode and CPHA = 0
tv(SO) Data output valid time
Slave mode 2.7 < VDD < 3.6 V
Voltage Range 1 - 12.5 13.5
ns
Slave mode 1.71 < VDD < 3.6 V
Voltage Range 1 -12.524
Slave mode 1.71 < VDD < 3.6 V
Voltage Range 2 -12.533
tv(MO) Master mode - 4.5 6
th(SO) Data output hold time
Slave mode 7 - -
ns
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
Table 90. SPI characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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162/194 DS12470 Rev 2
Figure 33. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 34. SPI timing diagram - master mode
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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STM32L422xx Electrical characteristics
165
Quad SPI characteristics
Unless otherwise specified, the parameters given in Table 91 and Table 92 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 21: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 15 or 20 pF
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 91. Quad SPI characteristics in SDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
FCK
1/t(CK)
Quad SPI clock frequency
1.71 < VDD< 3.6 V, CLOAD = 20 pF
Voltage Range 1 --40
MHz
1.71 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1 --48
2.7 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1 --60
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2 --26
tw(CKH) Quad SPI clock high and
low time fAHBCLK= 48 MHz, presc=0
t(CK)/2-2 - t(CK)/2
ns
tw(CKL) t(CK)/2 - t(CK)/2+2
ts(IN) Data input setup time
Voltage Range 1 2 - -
Voltage Range 2 3.5 - -
th(IN) Data input hold time
Voltage Range 1 5 - -
Voltage Range 2 6.5 - -
tv(OUT) Data output valid time
Voltage Range 1 - 1 5
Voltage Range 2 - 3 5
th(OUT) Data output hold time
Voltage Range 1 0 - -
Voltage Range 2 0 - -
1. Guaranteed by characterization results.
Electrical characteristics STM32L422xx
164/194 DS12470 Rev 2
Table 92. QUADSPI characteristics in DDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
FCK
1/t(CK)
Quad SPI clock
frequency
1.71 < VDD < 3.6 V, CLOAD = 20 pF
Voltage Range 1 --40
MHz
2 < VDD < 3.6 V, CLOAD = 20 pF
Voltage Range 1 --48
1.71 < VDD < 3.6 V, CLOAD = 15 pF
Voltage Range 1 --48
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2 --26
tw(CKH) Quad SPI clock high
and low time fAHBCLK = 48 MHz, presc=0
t(CK)/2-2 - t(CK)/2
ns
tw(CKL) t(CK)/2 - t(CK)/2+2
tsr(IN)
Data input setup time
on rising edge
Voltage Range 1 1
--
Voltage Range 2 3.5
tsf(IN)
Data input setup time
on falling edge
Voltage Range 1 1
--
Voltage Range 2 1.5
thr(IN)
Data input hold time
on rising edge
Voltage Range 1 6
--
Voltage Range 2 6.5
thf(IN)
Data input hold time
on falling edge
Voltage Range 1 5.5
--
Voltage Range 2 5.5
tvr(OUT)
Data output valid time
on rising edge
Voltage Range 1
-
55.5
Voltage Range 2 9.5 14
tvf(OUT)
Data output valid time
on falling edge
Voltage Range 1
-
58.5
Voltage Range 2 15 19
thr(OUT)
Data output hold time
on rising edge
Voltage Range 1 3.5 -
-
Voltage Range 2 8 -
thf(OUT)
Data output hold time
on falling edge
Voltage Range 1 3.5 -
-
Voltage Range 2 13 -
1. Guaranteed by characterization results.
DS12470 Rev 2 165/194
STM32L422xx Electrical characteristics
165
Figure 35. Quad SPI timing diagram - SDR mode
Figure 36. Quad SPI timing diagram - DDR mode
USB characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
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Table 93. USB electrical characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDUSB USB transceiver operating voltage 3.0(2) -3.6V
Tcrystal_less USB crystal less operation temperature -15 - 85 °C
RPUI Embedded USB_DP pull-up value during idle 900 1250 1600
RPUR
Embedded USB_DP pull-up value during
reception 1400 2300 3200
ZDRV(3) Output driver impedance(4) Driving high
and low 28 36 44
1. TA = -40 to 125 °C unless otherwise specified.
2. The STM32L422xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics
which are degraded in the 2.7-to-3.0 V voltage range.
3. Guaranteed by design.
4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
Package information STM32L422xx
166/194 DS12470 Rev 2
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 LQFP64 package information
Figure 37. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline
1. Drawing is not to scale.
Table 94. LQFP - 64 pins, 10 x 10 mm low-profile quad flat
package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
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DS12470 Rev 2 167/194
STM32L422xx Package information
191
Figure 38. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0°3.5°7° 0°3.5°7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 94. LQFP - 64 pins, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
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Package information STM32L422xx
168/194 DS12470 Rev 2
Device marking
The following figures gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 39. LQFP64 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Figure 40. LQFP64, external SMPS device, marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
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DS12470 Rev 2 169/194
STM32L422xx Package information
191
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
7.2 UFBGA64 package information
Figure 41. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package outline
1. Drawing is not to scale.
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Table 95. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 0.080 0.130 0.180 0.0031 0.0051 0.0071
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.170 0.280 0.330 0.0067 0.0110 0.0130
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.450 3.500 3.550 0.1358 0.1378 0.1398
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 3.450 3.500 3.550 0.1358 0.1378 0.1398
Package information STM32L422xx
170/194 DS12470 Rev 2
Figure 42. UFBGA64 – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package recommended footprint
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 95. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
Table 96. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch 0.5
Dpad 0.280 mm
Dsm 0.370 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
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DS12470 Rev 2 171/194
STM32L422xx Package information
191
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 43. UFBGA64 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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172/194 DS12470 Rev 2
7.3 LQFP48 package information
Figure 44. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package outline
1. Drawing is not to scale.
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DS12470 Rev 2 173/194
STM32L422xx Package information
191
Table 97. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
Package information STM32L422xx
174/194 DS12470 Rev 2
Figure 45. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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DS12470 Rev 2 175/194
STM32L422xx Package information
191
Figure 46. LQFP48 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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176/194 DS12470 Rev 2
7.4 UFQFPN48 package information
Figure 47. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
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DS12470 Rev 2 177/194
STM32L422xx Package information
191
Figure 48. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Table 98. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
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Package information STM32L422xx
178/194 DS12470 Rev 2
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 49. UFQFPN48 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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STM32L422xx Package information
191
7.5 WLCSP36 package information
Figure 50. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
package outline
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
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180/194 DS12470 Rev 2
Table 99. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A(2)
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
- - 0.59 - - 0.023
A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
A3(3)
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
- 0.025 - - 0.001 -
b 0.22 0.25 0.28 0.009 0.010 0.011
D 2.55 2.58 2.61 0.100 0.102 0.103
E 3.04 3.07 3.10 0.120 0.121 0.122
e - 0.40 - - 0.016 -
e1 - 2.00 - - 0.079 -
e2 - 2.00 - - 0.079 -
F(4)
4. Calculated dimensions are rounded to the 3rd decimal place
- 0.290 - - 0.0114 -
G(4) - 0.235 - - 0.0093 -
aaa - 0.10 - - 0.004 -
bbb - 0.10 - - 0.004 -
ccc - 0.10 - - 0.004 -
ddd - 0.05 - - 0.002 -
eee - 0.05 - - 0.002 -
DS12470 Rev 2 181/194
STM32L422xx Package information
191
Figure 51. WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus ball 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Table 100. WLCSP36 recommended PCB design rules
Dimension Recommended values
Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
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182/194 DS12470 Rev 2
Figure 52. WLCSP36 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
7.6 UFQFPN32 package information
Figure 53. UFQFPN - 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
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DS12470 Rev 2 183/194
STM32L422xx Package information
191
Figure 54. UFQFPN - 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Table 101. UFQFPN - 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 - - 0.050 - - 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
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184/194 DS12470 Rev 2
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 55. UFQFPN32 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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DS12470 Rev 2 185/194
STM32L422xx Package information
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7.7 LQFP32 package information
Figure 56. LQFP - 32 pins, 7 x 7 mm low-profile quad flat package outline
1. Drawing is not to scale.
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186/194 DS12470 Rev 2
Table 102. LQFP - 32 pins, 7 x 7 mm low-profile quad flat package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.100 - - 0.0039
DS12470 Rev 2 187/194
STM32L422xx Package information
191
Figure 57. LQFP - 32 pins, 7 x 7 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 58. LQFP32 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
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188/194 DS12470 Rev 2
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12470 Rev 2 189/194
STM32L422xx Package information
191
7.8 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
TA max is the maximum ambient temperature in °C,
JA is the package junction-to-ambient thermal resistance, in °C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the
maximum chip internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
7.8.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.8.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
Table 103. Package thermal characteristics
Symbol Parameter Value Unit
JA
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch 66
°C/W
Thermal resistance junction-ambient
UFBGA64 - 5 × 5 mm / 0.5 mm pitch 63
Thermal resistance junction-ambient
UFQFPN48 - 7 × 7 mm / 0.5 mm pitch 30
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch 68
Thermal resistance junction-ambient
WLCSP36 - 2.58 x 3.07 mm / 0.4 mm pitch 85
Thermal resistance junction-ambient
LQFP32 - 7 x 7 / 0.8 mm pitch 68
Thermal resistance junction-ambient
UFQFPN32- 5 × 5 mm / 0.5 mm pitch 37
Package information STM32L422xx
190/194 DS12470 Rev 2
As applications do not commonly use the STM32L422xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 72 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 103 TJmax is calculated as follows:
For LQFP64, 66 °C/W
TJmax = 72 °C + (66 °C/W × 447 mW) = 72 °C + 29.502 °C = 101.502 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see Part
numbering).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 37).
Suffix 6: TAmax = TJmax - (66°C/W × 447 mW) = 105-29.502 = 75.498 °C
Suffix 3: TAmax = TJmax - (46°C/W × 447 mW) = 130-29.502 = 100.498 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
DS12470 Rev 2 191/194
STM32L422xx Package information
191
Using the values obtained in Table 103 TJmax is calculated as follows:
For LQFP64, 66 °C/W
TJmax = 100 °C + (66 °C/W × 134 mW) = 100 °C + 8.844 °C = 108.844 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
Ordering information STM32L422xx
192/194 DS12470 Rev 2
8 Ordering information
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 104. STM32L422xx ordering information scheme
Example: STM32 L 422 C B T 6 P TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
422: STM32L422xx
Pin count
K = 32 pins
T = 36 pins
C = 48 pins
R = 64 pins
Flash memory size
B = 128 kB of Flash memory
8 = 64 KB of Flash memory
Package
T = LQFP ECOPACK®2
U = QFN ECOPACK®2
I = UFBGA ECOPACK®2
Y = CSP ECOPACK®2
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130 °C junction)
Option
Blank = Standard production with integrated LDO
P = Dedicated pinout supporting extenal SMPS
Packing
TR = tape and reel
xxx = programmed parts
DS12470 Rev 2 193/194
STM32L422xx Revision history
193
9 Revision history
Table 105. Document revision history
Date Revision Changes
02-Oct-2018 1 Initial release.
19-Oct-2018 2
Updated:
Features
Table 25: Current consumption in Run and Low-power
run modes, code with data processing running from
Flash, ART enable (Cache ON Prefetch OFF),
Table 27: Current consumption in Run and Low-power
run modes, code with data processing running from
Flash, ART disable, Table 29: Current consumption in
Run and Low-power run modes, code with data
processing running from SRAM1, Table 40: Current
consumption in Sleep and Low-power sleep modes,
Flash ON, Table 42: Current consumption in Low-
power sleep modes, Flash in power-down, Table 43:
Current consumption in Stop 2 mode, Table 48:
Current consumption in VBAT mode, Table 49:
Peripheral current consumption
STM32L422xx
194/194 DS12470 Rev 2
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