CD4060BMSFN3317 - Intersil Corporation

7-949

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

CD4060BMS

CMOS 14 Stage Ripple-Carry

Binary Counter/Divider and Oscillator

Pinout

Functional Diagram

Q12

Q13

Q14

VSS

VDD

RESET

øI

ø0

Q10

14 STAGE

RIPPLE

COUNTER

AND

OSCILLATOR

Q10

Q12

Q13

Q14

øI

ø0

VSS = 8

VDD = 16

Features

• High Voltage Type (20V Rating)

• Common Reset

• 12MHz Clock Rate at 15V

• Fully Static Operation

• Buffered Inputs and Outputs

• Schmitt Trigger Input Pulse Line

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Oscillator Features

• All Active Components on Chip

• RC or Crystal Oscillator Conﬁguration

• RC Oscillator Frequency of 690kHz Min. at 15V

Applications

• Control counters

• Timers

• Frequency Dividers

• Time Delay Circuits

Description

CD4060BMS consists of an oscillator section and 14 ripple

carry binary counter stages. The oscillator conﬁguration allows

design of either RC or crystal oscillator circuits. A RESET input

is provided which resets the counter to the all O’s state and dis-

ables the oscillator. A high level on the RESET line accom-

plishes the reset function. All counter stages are master slave

ﬂip-ﬂops. The state of the counter is advanced one step in

binary order on the negative transition of øI (and ø0). All inputs

and outputs are fully buffered. Schmitt trigger action on the

input pulse line permits unlimited input pulse rise and fall times.

The CD4060BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP H4W

Frit Seal DIP H1F

Ceramic Flatpack H6W

December 1992

File Number 3317

7-950

Speciﬁcations CD4060BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . . θja θjc

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW

For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

2 +125oC - 1000 µA

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

2 +125oC -1000 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

2 +125oC - 1000 nA

VDD = 18V 3 -55oC - 100 nA

Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV

Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V

Output Current (Sink)

(Excluding pins 9 & 10) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA

IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA

IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA

Output Current (Source)

(Excluding pins 9 & 10) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA

IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA

IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA

IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA

N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V

P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V

Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD/2 VOL <

VDD/2 V

VDD = 20V, VIN = VDD or GND 7 +25oC

VDD = 18V, VIN = VDD or GND 8A +125oC

VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

Input Voltage High

(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

Input Voltage Low

(Note 2) VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V

Input Voltage High

(Note 2) VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

3. For accuracy, voltage is measured differentially to VDD. Limit

is 0.050V max.

7-951

Speciﬁcations CD4060BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Propagation Delay

Input Pulse Operation

øI to Q4

TPHL1

TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 740 ns

10, 11 +125oC, -55oC - 999 ns

Propagation Delay

QN to QN + 1 TPHL2

TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

Propagation Delay

RESET TPHL3 VDD = 5V, VIN = VDD or GND 9 +25oC - 360 ns

10, 11 +125oC, -55oC - 486 ns

Transition Time TTHL

TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

Maximum Input Pulse

Frequency FØI VDD = 5V

VIN = VDD or GND 9 +25oC 3.5 - MHz

10, 11 +125oC, -55oC 2.59 - MHz

NOTES:

1. VDD = 5V, CL = 50pF, RL = 200K

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

+125oC - 150 µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 300 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 600 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC-50mV

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC-50mV

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC4.95 - V

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC9.95 - V

Output Current (Sink)

(Excluding pins 9 & 10) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink)

(Excluding pins 9 & 10) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink)

(Excluding pins 9 & 10) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current

(Source)

(Excluding pins 9 & 10)

IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current

(Source)

(Excluding pins 9 & 10)

IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current

(Source)

(Excluding pins 9 & 10)

IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

7-952

Speciﬁcations CD4060BMS

Output Current

(Source)

(Excluding pins 9 & 10)

IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V,

VOL < 1V 1, 2 +25oC, +125oC,

-55oC-3V

Input Voltage High VIH VDD = 10V, VOH > 9V,

VOL < 1V 1, 2 +25oC, +125oC,

-55oC+7 - V

Drive Current at Pin 9

Oscillator Design IOL VDD = 5V, VO = .4V 3 +25oC 0.16 - mA

VDD = 10V, VO = .5V 3 +25oC 0.42 - mA

VDD = 15V, VO = 1.5V 3 +25oC -1.0 - mA

Drive Current at Pin 9

Oscillator Design IOH VDD = 5V 1, 2, 3 +25oC - -.16 mA

VDD = 10V 1, 2, 3 +25oC - -.42 mA

VDD = 15V 1, 2, 3 +25oC - 1.0 mA

Propagation Delay

Input Pulse øI to Q4 TPHL1

TPLH1 VDD = 10V 1, 2, 3 +25oC - 300 ns

VDD = 15V 1, 2, 3 +25oC - 200 ns

Propagation Delay

QN to QN + 1 TPHL2

TPLH2 VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

Propagation Delay

RESET TPHL3 VDD = 10V 1, 2, 3 +25oC - 160 ns

VDD = 15V 1, 2, 3 +25oC - 100 ns

Transition Time TTHL

TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

Maximum Input Pulse

Frequency FØIVDD = 10V 1, 2, 3 +25oC 8 - MHz

VDD = 15V 1, 2, 3 +25oC 12 - MHz

Minimum RESET Pulse

Width TW VDD = 5V 1, 2, 3 +25oC - 120 ns

VDD = 10V 1, 2, 3 +25oC - 60 ns

VDD = 15V 1, 2, 3 +25oC - 40 ns

Minimum Input Pulse

Width

F = 100kHz

TW VDD = 5V 1, 2, 3 +25oC - 100 ns

VDD = 10V 1, 2, 3 +25oC - 40 ns

VDD = 15V 1, 2, 3 +25oC - 30 ns

RC Operation RX Max RX VDD = 5V, CX = 10µF 2, 3 +25oC - 20 MΩ

VDD = 10V, CX = 50µF 2, 3 +25oC - 20 MΩ

VDD = 15V, CX = 10µF 2, 3 +25oC - 10 MΩ

RC Operation CX Max CX VDD = 5V, RX = 500kΩ2, 3 +25oC - 1000 µF

VDD = 10V, RX = 300kΩ2, 3 +25oC-50µF

VDD = 15V, RX = 300kΩ2, 3 +25oC-50µF

Maximum Oscillator

Frequency (Note 4) RX = 5kΩ

CX = 15pF VDD = 10V 2, 3 +25oC 530 810 ns

VDD = 15V 2, 3 +25oC 690 940 ns

RC Operation Variation

of Frequency

(Unit-to-Unit)

CX = 200pF

RS = 560K

RX = 50k

VDD = 5V 2, 3 +25oC 18 25 kHz

VDD = 10V 2, 3 +25oC 20 26 kHz

VDD = 15V 2, 3 +25oC 21.1 27 kHz

Variation of Frequency

with Voltage Change

(Same Unit)

CX = 200pF

RS = 560K

RX = 50k

5V to 10V 2, 3 +25oC - 2 kHz

10V to 15V 2, 3 +25oC - 1 kHz

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

7-953

Speciﬁcations CD4060BMS

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. RC Oscillator applications are not recommended at supply voltages below 7V for RX < 50kΩ.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA

N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V

N Threshold Voltage

Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V

P Threshold Voltage

Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2 VOL <

VDD/2 V

VDD = 3V, VIN = VDD or GND

Propagation Delay Time TPHL

TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

+25oC

Limit

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA

Output Current (Sink) IOL5 ± 20% x Pre-Test Reading

Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP MIL-STD-883

METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Final Test 100% 5004 2, 3, 8A, 8B, 10, 11

Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

7-954

Speciﬁcations CD4060BMS

Logic Diagram

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS MIL-STD-883

METHOD

TEST READ AND RECORD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION OPEN GROUND VDD 9V ± -0.5V

OSCILLATOR

50kHz 25kHz

Static Burn-In 1 Note 1 1 - 7, 9, 10, 13 - 15 8, 11, 12 16

Static Burn-In 2 Note 1 1 - 7, 9, 10, 13 - 15 8 11, 12, 16

Dynamic Burn-In Note 1 - 8, 12 16 1 - 7, 9, 10, 13 - 15 11 -

Irradiation Note 2 1 - 7, 9, 10, 13 - 15 8 11, 12, 16

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer , 0 failures, VDD = 10V±

0.5V

TABLE 6. APPLICABLE SUBGROUPS (Continued)

CONFORMANCE GROUP MIL-STD-883

METHOD GROUP A SUBGROUPS READ AND RECORD

FF2-FF13

FF1 FF14

ø1 Q1

ø1 Q1 Q13ø2

ø2 Q13

Q14

ø14

Q14

RESET

ø 0

ø I

Q14

Q4 - Q10

Q12, Q13

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION

NETWORK

VDD

VSS

**R = HIGH DOMINATES (RESETS ALL STAGES)

***COUNTER ADVANCES ONE BINARY COUNT

ON EACH NEGATIVE - GOING TRANSITION

OF øI (AND øO)

***

DETAIL OF TYPICAL FLIP-FLOP STAGE

7-955

CD4060BMS

Typical Performance Curves

FIGURE 1. TYPICAL N-CHANNEL OUTPUT LOW SINK

CURRENT CHARACTERISTICS FIGURE 2. MINIMUM N-CHANNEL OUTPUT LOW (SINK)

CURRENT CHARACTERISTICS

FIGURE 3. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE)

CURRENT CHARACTERISTICS FIGURE 4. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE)

CURRENT CHARACTERISTICS

FIGURE 5. TYPICAL PROPAGATION DELAY TIME (QN TO

QN+1) AS A FUNCTION OF LOAD CAPACITANCE FIGURE 6. TYPICAL PROPAGATION DELAY TIME (Ø1 TO Q4

OUTPUT) AS A FUNCTION OF LOAD

CAPACITANCE

10V

AMBIENT TEMPERATURE (T A) = +25oC

GATE-TO-SOURCE VOLT AGE (VGS) = 15V

0 5 10 15

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

10V

AMBIENT TEMPERATURE (T A) = +25oC

GATE-TO-SOURCE VOLT AGE (VGS) = 15V

0 5 10 15

7.5

5.0

2.5

10.0

12.5

15.0

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

-10V

-15V

AMBIENT TEMPERATURE (T A) = +25oC

GATE-TO-SOURCE VOLT AGE (VGS) = -5V

-5

-10

-15

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

-20

-25

-30

0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

-10V

-15V

AMBIENT TEMPERATURE (T A) = +25oC0

-5

-10

-15

DRAIN-TO-SOURCE VOLT AGE (VDS) (V) 0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLT AGE (VGS) = -5V

AMBIENT TEMPERATURE (T A) = +25oC

SUPPLY VOL TAGE (VDD) = 5V

10V

15V

LOAD CAPACITANCE (CL) (pF)

020 40 60 80 100

100

150

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

AMBIENT TEMPERATURE (T A) = +25oC

SUPPLY VOL TAGE (VDD) = 5V

10V

15V

0LOAD CAPACITANCE (CL) (pF)

20 40 60 80 100

100

200

300

400

500

600

700

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

7-956

CD4060BMS

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACIT ANCE FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF INPUT FREQUENCY

Test Circuits

FIGURE 9. DYNAMIC POWER DISSIPATION TEST CIRCUIT FIGURE 10. TYPICAL RC CIRCUIT

Typical Performance Curves (Continued)

AMBIENT TEMPERATURE (T A) = +25oC

LOAD CAPACITANCE (CL) (pF)

0 40 60 80 10020

100

150

200

SUPPLY VOL TAGE (VDD) = 5V

10V

15V

TRANSITION TIME (tTHL, tTLH) (ns)

AMBIENT TEMPERATURE (T A) = +25oC

SUPPLY VOL TAGE (VDD) = 15V

10V

CL = 50pF

CL = 15pF

10V

110

102103104

2468

103

104

105

102

INPUT FREQUENCY (føI) (kHz)

DYNAMIC POWER DISSIPATION (PD) (µW)

2468 2468 2468 2468

0.1

LOAD CAPACITANCE

ID500µF

VDD

PULSE

GENERATOR

11 10 9

RS RX

NOTE:

RS IS 2RX TO 10RX

T = 2.2 RXCX

957

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

Intersil Corporation

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

EUROPE

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

ASIA

Intersil (Taiwan) Ltd.

Taiwan Limited

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

CD4060BMS

FIGURE 11. TYPICAL CRYSTAL CIRCUIT

Chip Dimensions and Pad Layout

Dimension in parenthesis are in millimeters

and are derived from the basic inch dimensions

as indicated. Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ−14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

Test Circuits (Continued)

11 9

RC RS

NOTE:

CXTAL = C1 + C2 + CSTRAY

RC = Broader frequency

response

RS = Current limiting