LTC6561 Four-Channel Multiplexed Transimpedance Amplifier with Output Multiplexing FEATURES DESCRIPTION 220MHz -3dB Bandwidth with 2pF Input Capacitance nn Single-Ended Output nn 74k Transimpedance Gain nn 4.8pA/Hz Input Current Noise Density at 200MHz (2pF) nn 64nA RMS Integrated Input Current Noise Over 200MHz (2pF) nn Linear Input Range 0A to 30A nn Overload Current > 400mA Peak nn Fast Overload Recovery 12ns, 1mA nn Fast Channel Switchover < 50ns nn Single 5V Supply nn 200mW Power Dissipation for 4 Channels nn 2V P-P Output Swing on 100 Load nn 4mm x 4mm, 24-Lead QFN Package nn Output MUX Combines Multiple 4-Channel Devices to Create 4, 8,12,16, 24, 32 Channel Solutions nn AEC-Q100 Qualified for Automotive Applications The LTC(R)6561 is a low-noise four-channel, transimpedance amplifier (TIA)with 220MHz bandwidth. The LTC6561 multi-channel transimpedance amplifier's low noise, high transimpedance, and low power dissipation are ideal for LIDAR receivers using Avalanche Photodiodes (APDs). The amplifier features 74k transimpedance gain and 30A linear input current range. Using an APD input circuit with a total capacitance of 2pF, the input current noise density is 4.5pA/Hz at 200MHz. With lower capacitance, noise and bandwidth improve further. Only a 5V single supply is needed and the device consumes only 200mW. Utilizing the internal 4-to-1 MUX along with the LTC6561's output MUX; multiple 4-channel LTC6561 devices can be combined to directly interface with 8, 12, 16 and 32-channel APD arrays. The LTC6561's fast overload recovery and fast channel switchover make it well suited for LIDAR receivers with multiple APDs. Its single-ended output can swing 2VP-P on a 100 load. While its low impedance op amp-style output can drive back-terminated 50 cables. APPLICATIONS The LTC6561 is packaged in a compact 4mm x 4mm 24-pin leadless QFN package with an exposed pad for thermal management and low inductance. nn nn nn LIDAR Receiver Industrial Imaging All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Typical Application with DC-Coupled Inputs Driving a Time-to-Digital Converter with Back-Terminated Cable MULTIPLE LTC6561's TIA OUT(2) VCC1,2 VCCO 47.5 WIRE-OR MUX LTC6561 OUT OUTPUT STAGE TIA 47.5 WITH SERIES 50, INTO 50 LOAD,RTEFF = 37k IN2 + -150V VREF2 - TIA 4:1 MUX 50 GAIN IN3 APD ARRAY VREF3 INPUT PULSE (20A/DIV) OUTTERM TIA IN4 VREF4 OUTPUT RESPONSE (0.5V/DIV) TIME-OF-FLIGHT DETECTOR IN1 VREF1 Pulse Response at the Edge of the Overload Region (40A) O_MUX(2) GND CHSEL1,0 O_MUX 5ns/DIV 6561 F01b 6561 TA01a Rev. C Document Feedback For more information www.analog.com 1 LTC6561 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) DNC OUTTERM GND GND OUT CHSEL1 TOP VIEW 24 23 22 21 20 19 VCCO 1 18 VCCO CHSEL0 2 17 O_MUX VCC1 3 VREF1 4 GND 5 IN1 6 16 VCC2 25 GND 15 VREF4 14 GND IN3 GND VREF3 9 10 11 12 VREF2 8 IN2 13 IN4 7 GND Total Supply Voltage (VCC1, VCC2, VCCO to GND).......5.5V Voltage (CHSEL0, CHSEL1, O_MUX).............. -0.3V to 5.5V Amplifier Reference Current (VREF1, VREF2, VREF3, VREF4)........................................................ 10mA Amplifier Reference Voltage (VREF1, VREF2, VREF3, VREF4)............................................. -0.3V to 3.5V Amplifier Input Current (IN1, IN2, IN3, IN4)..................400mA RMS 2A Transient (10ns) Amplifier Output Current (OUT, OUTTERM)......... +80mA Operating Temperature Range LTC6561I (Note 2)................................-40C to 85C LTC6561H (Note 3)............................. -40C to 125C Storage Temperature Range................... -65C to 150C Junction Temperature............................................ 150C UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 150C, JA = 47C/W, JC = 4.5C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6561IUF#PBF LTC6561IUF#TRPBF 6561 24-LEAD (4mm x 4mm) PLASTIC QFN -40C to 85C LTC6561HUF#PBF LTC6561HUF#TRPBF 6561 24-LEAD (4mm x 4mm) PLASTIC QFN -40C to 125C LTC6561HUF#WTRPBF 6561 24-LEAD (4mm x 4mm) PLASTIC QFN -40C to 125C AUTOMOTIVE PRODUCTS** LTC6561HUF#WPBF Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for thesemodels. AC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100. Output is AC-coupled. Output taken from OUT pin. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 220 UNITS BW -3dB Bandwidth 200mVP-P,OUT and CIN,TOT = 2pF RT Small Signal Transimpedance IIN < 2AP-P RIN Input Impedance f = 100kHz 236 ROUT Output Impedance f = 100kHz 3 l 63 47.7 74 MHz 85 101 k Rev. C 2 For more information www.analog.com LTC6561 AC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100. Output is AC-coupled. Output taken from OUT pin. SYMBOL PARAMETER In Input Current Noise Density CONDITIONS MIN TYP MAX UNITS f = 100MHz, CIN,TOT = 2pF 4.3 pA/Hz f = 200MHz, CIN,TOT = 2pF 4.8 pA/Hz f = 0.1MHz to 100MHz, CIN,TOT = 2pF 43 nARMS f = 0.1MHz to 200MHz, CIN,TOT = 2pF 64 nARMS Adjacent Channel to Channel Isolation f = 100MHz -45 dB Integrated Input Current Noise Non Adjacent Channel Isolation f = 100MHz -65 dB tRECOVER Overload Recovery Time Input Pulse = 1mA 12 ns tSWITCH Channel Switchover Time DC Coupled Input 50 ns tOMUX_SWITCH Output MUX Switchover Time DC Coupled Input 50 ns DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100. Output is AC-coupled. Output taken from OUT pin. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.43 1.25 0.78 0.70 1.55 0.93 1.64 1.76 1.38 1.53 V V V V 1.55 1.50 1.63 1.67 V V 12 -116 mV mV V V V V IN1,2,3,4 Pins and VREF1,2,3,4 Pins VIN Input Bias Voltage Active Channel Inactive Channel l l VREF Input Reference Voltage Active Channel Inactive Channel 1.43 1.34 Offset VIN - VREF Active Channel Inactive Channel -12 -741 Output Default Voltage O_MUX = 0V OUT Pin VOUT O_MUX = 3.3V, Standalone Device OVR OUTTERM IIN Current Range = 0 to -50A Output Voltage Range 1.10 0.60 l 0.83 0.79 0.32 0.28 1.47 1.67 0.88 0.92 1.22 0.98 1.90 l 2.58 2.80 VP-P VP-P 44 56 70.8 0.7 V l Internal Series Resistor for Optional Output CHSEL0, CHSEL1, O_MUX Pins with Internal Pull-Down Resistors VIL l VIH l 1.5 20.7 l 16.9 15.4 26.0 28.0 A A 37 34 47 l 57 62 A A IIL Pin Voltage = 0.7V IIH Pin Voltage = 1.5V CIN Input Capacitance RIN Input Resistance V 1.5 l 22 21 29 pF 35 37 k k Rev. C For more information www.analog.com 3 LTC6561 DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100. Output is AC-coupled. Output taken from OUT pin. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4.75 5 5.25 V Power Supply VS Operating Supply Range ICC1,2 Input Supply Current ICC0 Output Supply Current IS Total Supply Current (IS(VCC1,2) + IS(VCC0)) PSRR(VCC1,2) Input Power Supply Rejection Ratio PSRR(VCC0) Output Power Supply Rejection Ratio VCC1 and VCC2 Are Internally Tied Together 29.0 26.8 36.3 l 44.0 45.8 mA mA Both VCCO Pins Are Internally Tied Together 1.8 1.7 2.3 l 2.8 2.9 mA mA 30.8 28.5 38.6 l 46.8 48.7 mA mA 21 15 25 l dB dB 34 33 40 l dB dB VCC1,2 = 4.75V to 5.25V, VCC0 = 5V VCC0 = 4.75V to 5.25V, VCC1,2 = 5V Note 2: The LTC6561I is guaranteed to meet specified performance from -40C to 85C. Note 3: The LTC6561H is guaranteed to meet specified performance from -40C to 125C. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. TYPICAL PERFORMANCE CHARACTERISTICS ISUPPLY vs VSUPPLY Over Temperature VSUP = VCCI = VCCO 45.0 45 3.5 40 35.0 35 30.0 30 25.0 20.0 125C 85C 25C -40C 10.0 5.0 0 3.0 25 20 15 15.0 2 2.5 3 3.5 4 4.5 VSUPPLY (V) 5 5.5 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VCCI (V) 6561 G01 2.5 2.0 1.5 1.0 125C 85C 25C -40C 10 6 ICCO vs VCCO Over Temperature 4.0 40.0 ICCI (mA) ISUPPLY (mA) ICCI vs VCCI Over Temperature 50 ICCO (mA) 50.0 125C 85C 25C -40C 0.5 6 6561 G02 0 2 2.5 3 3.5 4 4.5 VCCO (V) 5 5.5 6 6561 G03 Rev. C 4 For more information www.analog.com LTC6561 TYPICAL PERFORMANCE CHARACTERISTICS 1.8 1.8 1.6 1.6 1.4 1.2 VREF vs Temperature 0 1.4 2.0 -2.0 -6.0 1.0 -40 -20 20 40 60 80 100 120 140 TEMPERATURE (C) VIN-VREF Offset vs Temperature 6.0 1.2 1.0 -40 -20 0 6561 G04 350 10.0 VIN-VREF OFFSET (mV) 2.0 VREF (V) VIN (V) VIN vs Temperature 2.0 -10.0 -40 -20 20 40 60 80 100 120 140 TEMPERATURE (C) 0 20 40 60 80 100 120 140 TEMPERATURE (C) 6561 G06 6561 G05 RT Transimpedance vs Temperature RIN vs Temperature 300 VIN vs IIN Over Temperature 100 2.00 80 1.80 60 1.60 150 VIN (V) 200 RT (k) RIN () 250 40 1.40 100 1.20 20 50 0 -40 -20 0 0 -40 -20 20 40 60 80 100 120 140 TEMPERATURE (C) 6561 G07 0 1.00 -40 -35 -30 -25 -20 -15 -10 IIN (A) 20 40 60 80 100 120 140 TEMPERATURE (C) 6561 G08 VOUT vs IIN Over Temperature -5 0 6561 G09 3dB Bandwidth vs Temperature Over CIN,TOT RT Transimpedance vs IIN Over Temperature 100 5.00 125C 85C 25C -40C 300 4.50 VOUT (V) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 125C 85C 25C -40C 0 -40 -35 -30 -25 -20 -15 -10 IIN (uA) -5 0 6561 G10 250 80 3DB BANDWIDTH (MHz) RT TRANSIMPEDANCE (k) 4.00 60 40 20 0 -40 -35 -30 -25 -20 -15 -10 IIN (A) 125C 85C 25C -40C -5 200 150 100 CIN,TOT = 0.5pF CIN,TOT = 2.2pF CIN,TOT = 4.0pF 50 0 6561 G11 0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 6561 G12 Rev. C For more information www.analog.com 5 LTC6561 TYPICAL PERFORMANCE CHARACTERISTICS 125C 85C 25C -40C 14 12 10 8 6 4 2 0 0.1 1 10 FREQUENCY (MHz) 100 500 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 Integrated Input-Referred Noise vs Bandwidth Over Temperature CIN,TOT = 0.5pF INTEGRATED STARTING FROM 100kHz CIN,TOT = 0.5pF 125C 85C 25C -40C 0 50 100 150 200 FREQUENCY (MHz) 250 16 125C 85C 25C -40C 14 12 10 8 6 4 2 0 0.1 1 10 FREQUENCY (MHz) 100 6561 G16 6 4 2 0 0.1 500 -30 -40 -50 -60 -70 PSRR VCCI PSRR VCCO 800 1200 1600 FREQUENCY (MHz) 2000 6561 G19 10 FREQUENCY (MHz) 100 140 130 INTEGRATED STARTING FROM 100kHz = 4.0pF C 120 IN,TOT 110 100 90 80 70 60 50 40 125C 30 85C 20 25C 10 -40C 0 0 50 100 150 200 250 300 FREQUENCY (MHz) O_MUX Isolation vs Frequency Over Temperature 100 50 40 30 20 125C 85C 25C -40C 10 0 0 200 400 600 FREQUENCY (MHz) 800 500 6561 G18 MAGNITUDE ISOLATION (dB) -20 1 Integrated Input-Referred Noise vs Bandwidth Over Temperature CIN,TOT = 4.0pF ANY SELECTED CHANNEL TO ANY UNSELECTED CHANNEL 60 MAGNITUDE ISOLATION (dB) POWER SUPPLY REJECTION RATIO (dB) 70 400 8 Ch to Ch Isolation vs Frequency Over Temperature PSRR Out to VCCI, VCCO 1 10 6561 G17 -10 -90 12 6561 G15 INTEGRATED INPUT REFERRED NOISE (nARMS) 140 130 INTEGRATED STARTING FROM 100kHz = 2.0pF C 120 IN,TOT 110 100 90 80 70 60 50 40 125C 30 85C 20 25C 10 -40C 0 0 50 100 150 200 250 300 FREQUENCY (MHz) 125C 85C 25C -40C 14 Input-Referred Noise Density with CIN,TOT = 4.0pF INPUT-REFERRED NOISE DENSITY (pA/Hz) INTEGRATED INPUT REFERRED NOISE (nARMS) Integrated Input-Referred Noise vs Bandwidth Over Temperature CIN,TOT = 2.0pF -80 300 16 Input-Referred Noise Density with CIN,TOT = 2.0pF 6561 G14 6561 G13 0 INPUT-REFERRED NOISE DENSITY (pA/Hz) INPUT-REFERRED NOISE DENSITY (pA/Hz) 16 INTEGRATED INPUT REFERRED NOISE (nARMS) Input-Referred Noise Density with CIN,TOT = 0.5pF 1000 6561 G20 ANY INPUT TO OUTPUT WHEN O_MUX = HI 80 60 40 125C 85C 25C -40C 20 0 0 200 400 600 FREQUENCY (MHz) 800 1000 6561 G21 Rev. C 6 For more information www.analog.com LTC6561 TYPICAL PERFORMANCE CHARACTERISTICS S21(Gain) vs Frequency Over Temperature 30 0 CIN,TOT = 0.5pF S22 vs Frequency Over Temperature 7 CIN,TOT = 0.5pF 0 -10 -20 125C 85C 25C -40C -30 0 200 400 600 FREQUENCY (MHz) 800 -10 -20 -30 -40 1000 125C 85C 25C -40C 0 200 400 600 FREQUENCY (MHz) 800 MAGNITUDE K (UNITLESS) MAGNITUDE S21 (dB) MAGNITUDE S21 (dB) 10 0 CIN,TOT = 2pF 1000 Unconditionally UNCONDITIONALLY Stable STABLE POTENTIALLY Potentially UNSTABLE unstable 0 200 0 -10 -20 125C 85C 25C -40C 0 200 400 600 FREQUENCY (MHz) 800 7 CIN,TOT = 2pF -10 -20 -30 -40 1000 125C 85C 25C -40C 0 200 400 600 FREQUENCY (MHz) 800 5 4 3 2 UNCONDITIONALLY STABLE 1 0 1000 POTENTIALLY UNSTABLE 0 200 0 7 CIN,TOT = 4pF 125C 85C 25C -40C -30 0 200 400 600 FREQUENCY (MHz) 800 1000 -10 -20 -30 -40 125C 85C 25C -40C 0 200 400 600 FREQUENCY (MHz) 800 1000 6561 G29 6561 G28 MAGNITUDE K (UNITLESS) MAGNITUDE S21 (dB) -20 1000 CIN,TOT = 4pF 125C 85C 25C -40C 6 -10 800 Stability Factor K vs Frequency Over Temperature 20 0 400 600 FREQUENCY (MHz) 6561 G27 S22 vs Frequency Over Temperature CIN,TOT = 4pF 1000 CIN,TOT = 2pF 125C 85C 25C -40C 6561 G26 S21(Gain) vs Frequency Over Temperature 10 800 Stability Factor K vs Frequency Over Temperature 6561 G25 30 400 600 FREQUENCY (MHz) 6561 G24 MAGNITUDE K (UNITLESS) MAGNITUDE S21 (dB) MAGNITUDE S21 (dB) 2 6 -30 MAGNITUDE S21 (dB) 3 0 S22 vs Frequency Over Temperature S21(Gain) vs Frequency Over Temperature 10 -40 4 1 20 -40 5 6561 G23 6561 G22 30 CIN,TOT = 0.5pF 125C 85C 25C -40C 6 20 -40 Stability Factor K vs Frequency Over Temperature 5 4 3 2 UNCONDITIONALLY STABLE 1 0 POTENTIALLY UNSTABLE 0 200 400 600 FREQUENCY (MHz) 800 1000 6561 G30 Rev. C For more information www.analog.com 7 LTC6561 Pulse Response Linear Range (20A) Pulse Response Linear Range (2.5A) OUTPUT RESPONSE 0.05V/DIV INPUT PULSE 1A/DIV OUTPUT RESPONSE 0.5V/DIV WITH SERIES 50, INTO 50 LOAD,RTEFF = 37k INPUT PULSE 10A/DIV 6561 G31 5ns/DIV 5ns/DIV INPUT PULSE 20A/DIV OUTPUT RESPONSE 0.5V/DIV WITH SERIES 50, INTO 50 LOAD,RTEFF = 37k INPUT PULSE 0.5mA/DIV 6561 G33 5ns/DIV OPTICAL PULSE-INJECTED 30ns AFTER CHSEL WITH SERIES 50, INTO 50 LOAD,RTEFF = 37k 5ns/DIV Channel Select Switching Time DC Coupled Input CHSEL UNSELECT->SELECT 6561 G32 Pulse Response Overload Region (1mA) Pulse Response Overload Region (40A) OUTPUT RESPONSE 0.5V/DIV WITH SERIES 50, INTO 50 LOAD,RTEFF = 37k 6561 G34 O_MUX Switching Time DCCoupled Input O_MUX DISABLED->ENABLED O_MUX OUTPUT GLITCH SWITCHING GLITCH OUTPUT 1V/DIV OUTPUT 0.5V/DIV READY IN LESS THAN 30ns 50ns/DIV SETTLED IN LESS THAN 25ns 6561 G35 5ns/DIV 6561 G36 Rev. C 8 For more information www.analog.com LTC6561 O_MUX and Channel Switching Time for ACCoupled Input 1E6 Channel Switching Glitch ACCoupled Input, 10pF 1.25 RC = 12k * INPUT CAP 1000 100 0.75 CHANNEL SELECT GLITCH 0.50 0.25 MIN. MEASURED SWITCHING TIME RC MODELED 10 100 1000 1E4 INPUT CAPACITOR VALUE (pF) 1E5 0 0 100 200 300 TIME (ns) 400 0.4 0.6 0.8 1 1.2 INPUT CURRENT (mA) 1.4 PULSE STRETCHING (nS) 125C 85C 25C -40C CURVE FIT 0.2 INPUT COUPLING CAP = 100pF 0 400 800 1200 TIME (ns) 1.6 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USING FULL WIDTH = HALF MAX. TO DETERMINE OUTPUT PULSE WIDTH y = 8.0x + 2.0 CIN = 2.0pF 125C 85C 25C -40C CURVE FIT 0 0.2 0.4 0.6 0.8 1 1.2 INPUT CURRENT (mA) 1.4 Pulse Width vs ADP Current Optical Measurement USING FULL WIDTH = HALF MAX. TO DETERMINE OUTPUT PULSE WIDTH y = 10.5x + 2.0 CIN = 4.0pF 125C 85C 25C -40C CURVE FIT 0.2 0.4 0.6 0.8 1 1.2 INPUT CURRENT (mA) 1.6 6561 G41 Pulse Stretching CIN=4.0pF, Using FWHM 0 2000 6561 G39 6561 G40 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1600 Pulse Stretching CIN=2.0pF, Using FWHM USING FULL WIDTH = HALF MAX. TO DETERMINE OUTPUT PULSE WIDTH y = 5.1x + 2.0 CIN = 0.5pF 0 0 500 Pulse Stretching CIN=0.5pF, Using FWHM 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHANNEL SELECT GLITCH 0.50 6561 G39 6561 G37 PULSE STRETCHING (nS) 1 0.75 0.25 INPUT COUPLING CAP = 10pF 1.4 PULSE WIDTH (nS) 10 CHSEL OUT 1.00 AMPLITUDE (V) AMPLITUDE (V) 1E4 1 1.25 CHSEL OUT 1.00 PULSE STRETCHING (nS) SWITCHING TIME (ns) 1E5 Channel Switching Glitch ACCoupled Input, 100pF 1.6 6561 G42 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 APD CAP APPROXIMATELY 4pF 0 2 4 6 APD CURRENT (mA) 8 10 6561 G43 Rev. C For more information www.analog.com 9 LTC6561 PIN FUNCTIONS VCCO (Pins 1, 18): Positive Power Supply for the output stage. Typically 5V. VCCO can be tied to VCC1 or VCC2 for single supply operation. Bypass capacitors of 1000pF and 0.1F should be placed as close as possible between VCCO and ground. Both VCCO pins are internally tied together. CHSEL0 (Pin 2): LSB for Channel Selection. CMOS input. The CHSEL0 pin has a 29k internal pull-down resistor. Default value is 0V. VCC1, VCC2 (Pins 3, 16): Positive Power Supply. Typically 5V. Bypass capacitors of 1000pF and 0.1F should be placed as close as possible between VCC1,2 and ground. VCC1 (Pin 3) and VCC2 (Pin 16) are internally tied together. VREF1, VREF2, VREF3, VREF4 (Pins 4, 9, 10, 15): Reference Voltage Pins for Transimpedance Amplifier for Channels 1, 2, 3, and 4 Respectively. This pin sets the input voltage for each transimpedance amplifier. The VREF pin has a Thevenin equivalent resistance of approximately 1.4k and can be overdriven by an external voltage. If no voltage is applied to VREF, it will float to a default voltage of approximately 1.55V on a 5V supply. Each VREF pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.1F. The bypass cap should be located close to its VREF pin. GND(Pins 5,8,11,14,21,22,Exposed Pad Pin 25): Negative Power Supply. Normally tied to ground. All GND pins and the exposed pad must be tied to the same voltage. The exposed pad (pin 25) should have multiple via holes to underlying ground plane for low inductance and good heat transfer. IN1, IN2, IN3, IN4 (Pin 6, 7, 12, 13): Input Pin for Transimpedance Amplifier for Channels 1, 2, 3, and 4 respectively. This pin is internally biased to 1.55V. See the Applications section for specific recommendations. O_MUX(Pin 17): Output MUX is a digital input controlling the output multiplexing function. The pin is functional when multiple LTC6561s are combined at the output. When O_MUX is low, the output is enabled. When O_ MUX is high, all 4 inputs are decoupled from the output. Its default value is 0V. This MUX pin is ineffective effect unless a 2nd LTC6561 is DC-coupled at the output. See Applications section on how to use O_MUX to expand the channel count with multiple LTC6561s. The O_MUX pin has a 29k internal pull-down resistor. DNC(Pin 19): No Connection. Do not connect. OUTTERM (Pin 20): TIA Output with an Internal Series 50 Resistor. OUT (Pin 23): TIA Output without an internal series 50 CHSEL1 (Pins 24): MSB for Channel Selection. CMOS input. The CHSEL1 pin has a 29k internal pull-down resistor. Default value is 0V. Rev. C 10 For more information www.analog.com LTC6561 BLOCK DIAGRAM VCCO VCC1,2 IN1 TIA VREF1 IN2 TIA VREF2 IN3 4:1 MUX TIA OUT OUTPUT STAGE VREF3 47.5 GAIN IN4 OUTTERM TIA VREF4 GND CHSEL0,1 O_MUX 6561 BD Rev. C For more information www.analog.com 11 LTC6561 OPERATION The LTC6561 is a four channel transimpedance amplifier (TIA) with an integrated 4-to-1 multiplexer. Each of the transimpedance amplifiers converts an input current to an output voltage. The integrated multiplexer simplifies the system design while saving space and power. In addition, the Output Multiplexer capability (O_MUX) allows multiple 4-channel LTC6561 devices to be combined. 8, 12, 16 or 32 input channels are easily multiplexed into a single output. In typical LIDAR applications, the LTC6561 amplifies the output current of an APD. APD are biased near breakdown to achieve high current gain Under intense optical illumination they can conduct large currents, often in excess of 1A. The LTC6561 survives and quickly recovers from large overload currents of this magnitude. During recover, any TIA is blinded from subsequent pulses. The LTC6561 recovers from 1mA saturation events in less than 12ns without phase reversal, minimizing this form of data loss. As the level of input current exceeds the linear range, the output pulse width will widen. However, the recovery time remains in the 10's of ns. See Figure7b and Figure8a plots of pulse stretching versus input current. TIA Internally the LTC6561 consists of multiple stages. The first stage is a transimpedance amplifier. A second voltage gain stage leads to a final output buffer that can drive a 2VP-P swing on a 100 load. To increase the LIDAR's spatial resolution many APDs are deployed, often in an array. To achieve maximum bandwidth each APD pixel must have a dedicated TIA as increasing CIN will reduce bandwidth. The LTC6561 multiplexing capability allows compact multichannel designs without external multiplexers. The use of multiple LTC6561's works well with an APD array to minimize trace capacitance and solution size. Channel Selection CHSEL1 CHSEL0 O_MUX ACTIVE CHANNEL 0 0 0 1 0 1 0 2 1 0 0 3 1 1 0 4 X X 1 High Z VCC1,2 VCCO LTC6561 IN1 VREF1 APD ARRAY -150V OUT 47.5 OUTPUT STAGE TIA IN2 + VREF2 - IN3 VREF3 TIME-OF-FLIGHT DETECTOR 50 TIA 4:1 MUX 47.5 GAIN OUTTERM TIA IN4 VREF4 GND CHSEL0,1 O_MUX 6561 F01 Figure1. Typical Application with DC-Coupled Inputs Driving a TDC with Back-Terminated Cable Rev. C 12 For more information www.analog.com LTC6561 APPLICATIONS INFORMATION MULTIPLE LTC6561's OUT(2) VCC1,2 VCCO TIA 47.5 WIRE-OR MUX LTC6561 TIME-OF-FLIGHT DETECTOR IN1 VREF1 OUT OUTPUT STAGE TIA 47.5 IN2 + -150V VREF2 - TIA 4:1 MUX 50 GAIN IN3 APD ARRAY VREF3 OUTTERM TIA IN4 VREF4 O_MUX(2) GND CHSEL1,0 O_MUX 6561 F02 Figure2. Typical Application with Multiplexed Output PCB Layout The LTC6561 has separate supply pins for input (VCC1,2) and output (VCCO). VCC1 (Pin 3) and VCC2 (Pin 16) are internally tied together. VCC0 pins (Pins 1 and 18) are internally tied together as well. Duplicate supply pins are provided to ease layout. One set of supply pins should be bypassed with 1000pF and 0.1F capacitors to ground. For best operation, the output and input supplies should be set to the same voltage. At each VREF pin the LTC6561 has small internal bypass capacitors connected between pin and ground to ensure low input noise. For the lowest possible input noise, the VREF pin at each TIA should be bypassed with a high quality 1000pF ceramic capacitor to ground. This bypass cap should be located physically close to each VREF pin and far from input pins to avoid unintentional coupling to the output. Output Considerations The LTC6561's output stage is a low impedance driver. When using the OUT pin, a series 47.5 resistor must be added to match to 50 transmission lines and equipment. If the OUTTERM pin is utilized, the 47.5 resistor is internal and no external component is needed. Only one of the outputs should be utilized at a time. At the single ended output, the resting voltage is approximately 1.0V. Loaded with 100 or higher load, the output can swing to 3V. This is equivalent to a 2VP-P swing. If loaded with 50, only a 1VP-P swing is possible since half of the voltage is dropped across the series output resistor. The output must be terminated with a low impedance load <400. If the output is measured directly into a high impedance oscilloscope, the output falling edge will be distorted as the LTC6561 has limited ability to sink current. When monitoring the output, be sure to set the oscilloscope's input termination to 50. Input Considerations AC- or DC-Coupling Input coupling the APD to the TIA is a critical design aspect with many trade-offs to consider. The DC coupled input is the simplest, requiring minimal components to directly couple the APD to the TIA. In the DC case switching times are fast <50nS and saturation recovery times are minimized. However, DC coupling allows APD dark current, and ambient light components to leak through. These DC components can diminish the TIA's dynamic range. DC current cancellation can be used to restore the TIA's dynamic range by injecting current at the TIA input to offset the APD's DC current component. Care must be taken at the TIA's input as current injection can also inject noise. The AC coupled input case will block all DC inputs, preserving the TIA's full dynamic range. See Figure3. Rev. C For more information www.analog.com 13 LTC6561 APPLICATIONS INFORMATION MULTIPLE LTC6561s 1nF TIA 50 WIRE-OR MUX OUT(2) VCC1,2 VCCO LTC6561 TIME-OF-FLIGHT DETECTOR IN1 10k 10k 10k 10k 1nF VREF1 50 OUT OUTPUT STAGE TIA IN2 + 150V 1nF - VREF2 TIA 4:1 MUX 50 GAIN IN3 APD ARRAY 1nF VREF3 OUTTERM TIA IN4 VREF4 O_MUX(2) GND CHSEL1,0 O_MUX 6561 F03 Figure3. Typical Application with Multiplexed Output When using a positively biased APD, the input must be AC coupled off of the APD's anode. 1.25 0.75 CHANNEL SELECT GLITCH 0.50 0.25 1E6 INPUT COUPLING CAP = 10pF RC = 12k * INPUT CAP 0 1E5 0 100 1E4 200 300 TIME (ns) 500 6561 F05 1000 1.25 CHSEL OUT 100 1.00 10 1 400 Figure5. Switching Glitch 10pF MIN. MEASURED SWITCHING TIME RC MODELED 1 10 100 1000 1E4 INPUT CAPACITOR VALUE (pF) 1E5 6561 F04 AMPLITUDE (V) SWITCHING TIME (ns) CHSEL OUT 1.00 AMPLITUDE (V) However, switching times will be affected depending on the choice of AC coupling capacitor. When a channel is switched from inactive to active using either the CHSEL or O_MUX control, a glitch will appear at the output. (See Figure5 and Figure6) The TIA will not be ready for a desired input pulse until the glitch has settled. The glitch settling time is dependent upon the AC coupling capacitor value. The value of the AC coupling cap must be carefully considered. A plot of switching times vs. coupling capacitor is shown in Figure4. Figure4. AC Switching Times To maximize dynamic range, the LTC6561's input is limited to negative current pulses (current flowing out of the LTC6561). When using a negatively biased APD, the TIA input can be AC or DC coupled to the APD cathode. 0.75 CHANNEL SELECT GLITCH 0.50 0.25 0 INPUT COUPLING CAP = 100pF 0 400 800 1200 TIME (ns) 1600 2000 6561 F06 Figure6. Switching Glitch 100pF Rev. C 14 For more information www.analog.com LTC6561 APPLICATIONS INFORMATION Coupling the APD to the TIA is critical, direct DC coupling or AC coupling, using a small AC coupling capacitor from 10pF to 100pF is recommended. Channel Selection There are four TIA inputs to the LTC6561. The active channel is selected using the two channel selection bits CHSEL0 and CHSEL1. When a channel is selected, its DC input voltage is approximately 1.5V; when deselected its input voltage drops to 0.9V. A reselected channel will not be active until its AC-coupling cap is recharged to 1.5V, leading to slow switching times. With a large AC-coupling cap, switching time can stretch into the S range. When DC- coupled, the LTC6561 will switch channels in less than 50nS. Inactive channels have more than 45dB of isolation to the active channel to prevent cross-talk. It is critical to route adjacent channel input lines with ground isolation between them to minimize channel to channel coupling. Output MUXing The Output MUX (O_MUX) requires at least one additional LTC6561 devices to operate in a master/slave relationship. To MUX multiple LTC6561's they need to share a DC connection at their outputs. One LTC6561 output must be selected at all times by asserting its O_MUX pin low. To disable the rest of the outputs, drive the other O_MUX pins high. The chosen LTC6561 effectively commands the others. It is recommended to DC couple the outputs after the series 40-50 resistor as this will limit reflection from unselected outputs. At least one LTC6561 output must be selected at all times. In its default mode O_MUX is low, so the LTC6561 output is enabled. Obviously, if there is only one LTC6561, then setting the O_MUX pin high will not MUX anything, however the output will be isolated from all the inputs. Input Capacitance As with most TIAs, bandwidth and rise time of the output pulse are a strong function of the input capacitance. To receive narrow pulses, a low capacitance APD sensor is recommended. As well, trace capacitance and parasitic pad capacitance should be minimized at the input. All LTC6561 plots reference CIN,TOT which is the total input capacitance including APD sensor, trace routing and parasitics. The LTC6561's MUX capability allows short input coupling to individual APDs and a more compact solution size for APD arrays. Internal protection circuitry at each TIA input can protect the LTC6561 even under strong overdrive conditions. Most application circuits will not need external protection diodes which add to the total input capacitance and slow the rise time. Output rise time can be estimated from the amplifier bandwidth using the following relationship: RISETIME = 0.35 BW APD Biasing Proper APD biasing is key to producing a high fidelity output and protecting both the APD and TIA. As suggested earlier a negatively biased APD provides the lowest input capacitance and allows the APD to be DC coupled to the TIA. To keep the optical gain stable the APD bias should be temperature compensated. Quenching resistors in series are required to limit the maximum current, thereby protecting the APD and TIA from damage. An example of a typical APD bias network is shown in Figure9. Starting at the Negative bias input, two physically large 10kW resistors can dissipate the maximum pulse power. They are decoupled with a 1nF capacitor. Moving towards the APD, a second smaller quenching resistor 50 is decoupled by two 0.047F capacitors. This smaller quenching resistor acts to dampen ringing especially under high slew rates due to large optical inputs pulses. All capacitors must be rated for high voltage as APD bias voltages can run above 200V. Dramatically Improving the LTC6561's Dynamic Range While the LTC6561's 30A of linear input range is quite respectable, it is possible to dramatically improve the range over which input current can be accurately measured. The measurement range can be increased from 30A to at least 3mA, a 100x improvement in current measurement range! As the input current exceeds the linear range, the output pulse amplitude saturates. Once Rev. C For more information www.analog.com 15 LTC6561 APPLICATIONS INFORMATION This behavior is demonstrated using the FT2563 evaluation board. This evaluation board uses a series 2k resistor to convert a voltage pulse to a current pulse as it is difficult to obtain a fast current pulse generator. The input is terminated in 50 so that current pulses of known quantity are generated at the TIA input using a voltage source. Sweeping the TIA pulse input current from 2.8A to 3mA, we see that as the current surpasses the 30A saturation point, the output pulse width increases (Figure7b). C1 0.1F R1 2k IN J1 25V R2 100 captured by an ADC. A plot of pulse stretching vs input current with CIN=0.5pF is shown in Figure8a. Figure8b shows pulse stretching with 4pF on input capacitance. current range in. PULSE STRETCHING (nS) in saturation, the pulse width widens in a predictable manner. Pulse stretching is a function of input capacitance, but fortunately insensitive to temperature. R3 100 0603 TIA 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USING FULL WIDTH = HALF MAX. TO DETERMINE OUTPUT PULSE WIDTH y = 5.1x + 2.0 CIN = 0.5pF 125C 85C 25C -40C CURVE FIT 0 0.2 C2 OPT 0.4 0.6 0.8 1 1.2 INPUT CURRENT (mA) 1.4 1.6 6561 F08a Figure8a. Pulse Stretching CIN = 0.5pF, Using FWHM 6561 F03a PULSE STRETCHING (nS) Figure7a. 79A 3mA 1mA 155A 29A 14A 2.8A PULSE AMPLITUDE (200mV/DIV) WITH SERIES 50, INTO 50 LOAD 10ns/DIV 6561 G03b 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USING FULL WIDTH = HALF MAX. TO DETERMINE OUTPUT PULSE WIDTH y = 10.5x + 2.0 CIN = 4.0pF 125C 85C 25C -40C CURVE FIT 0 0.2 0.4 0.6 0.8 1 1.2 INPUT CURRENT (mA) 1.4 1.6 6561 F08b Figure7b. Output Pulse Over Input Current Figure8b. Pulse Stretching CIN = 4pF, Using FWHM When we plot the pulse stretching (output response width - input pulse width), we see that the stretching is linearly proportional to the input current. Below, the saturation point of 30A the pulse stretching falls to zero. Here we have used the simple FWHM (full width half max) criteria to establish the pulse width. The pulse width is taken at half of the maximum swing, usually around 0.45V. A more sophisticated algorithm could be used to gain greater accuracy assuming the pulse shape is accurately The same pulse stretching has been demonstrated using optical excitation. Independently measuring the current generated during an optical pulse impinging on an APD is quite difficult. The parasitics of any measuring device will impair the actual pulse input. Refer to Figure9. Using a balun across series resistor R48 feeding the APD, we can get an independent determination of APD current to the TIA for moderate laser input powers. Again, when this APD current is plotted versus pulse stretching, we find a nearly linear relationship under moderate illumination. Rev. C 16 For more information www.analog.com LTC6561 APPLICATIONS INFORMATION Pulse Width vs APD Current Optical Measurement 8 7 6 1 8 5 7 4 6 3 GR 2 5 4 3 2 R48 50 1204 R47 10k 1206 C45 0.047F 1206 300V C70 0.047F 1206 300V R75 10k 1206 C46 1nF 1206 E8 E11 HOLE FOR -300V HOLE FOR GND PULSE WIDTH (nS) U3 APD-ARRAY 6561 F05a 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 2000 4000 6000 8000 APD CURRENT (A) 10000 6561 F05b Figure9. Typical APD Bias Circuit 1.2 5W 1.0 PULSE AMPLITUDE (V) Using a calibrated laser source, we find that pulse stretching continues even at extremely high laser power levels of 50 Watts! At high illumination levels, the relationship no longer appears perfectly linear, but the potential to measure these high power levels is possible. Of course, with any system, a calibration of optical input power to pulse stretching should be done as the optical gain is a strong function of the APD reverse bias, temperature and the choice of APD. 50W 0.8 0.6 507W 0.4 5mW 0.2 5W 0.0 0 1 2 TIME (sec) 3 4 6561 F06 Figure10. Pulse Width vs Input Hi Power Optical Rev. C For more information www.analog.com 17 LTC6561 APPLICATIONS INFORMATION DC2849 4-Channel Demonstration Circuit for Optical Evaluation DC2849 Front Side 5 DC2849 Back Side 4 3 2 1 VCC0 VCC 3 VCC R17 1k 2 GND E4 Z1 CLL4734A 5.6V 2 C2 1uF 0603 1 VCC EXT C3 1uF 0603 VCC0_SEL JP1 APD1 C4 10uF 0805 E2 GND 0.1uF C6 1000pF R1 OPT 10 11 0.1uF C9 1000pF 1 VCCO 3 5 2 VCC1 CHSELO GND CHSEL1 0 OUT VREF2 GND VREF3 GND NC C11 OPT 24 R5 23 47.5 1 OUT J3 21 R6 20 OPT C16 OPT 19 1 OUTTERM J4 C18 OPT C DNI VCC0 1000pF VCC C14 0.1uF 22 C19 R9 OPT VCC 3 0 DNI 18 O_MUX VCC2 17 16 15 GND IN4 14 13 0 VREF4 OUTTERM IN3 CHSEL1 R3 OPT 0.1uF C21 APD4 D 1 2 25 C20 1000pF R8 DNI J2 LTC6561-UF GND GND 12 R7 CHSEL0 J1 1 C7 VCC0 8 9 C15 1000pF 4 IN2 VREF1 IN1 7 GND 6 0 C 1 CHSEL1 JP3 U1 C13 1000pF APD3 R18 1k 0 R4 0 VCC C5 C10 1000pF APD2 1 2 JP2 VCC E3 R2 VCC0 1 C1 10uF 0805 1 3 D 3 E1 1 VCC CHSEL0 R19 1k JP4 O_MUX DIS EN 1 C23 1000pF 2 1 C24 0.1uF O_MUX J5 DNI B B PCA ADDITIONAL PARTS A MP1 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) MP2 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) MP3 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) MP4 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) LB1 PCB1 STNCL1 LABEL PCB, DC2849A NOTE: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTORS ARE IN OHMS, 0402 ALL CAPACITORS ARE IN MICROFARADS, 0402 REV0x TOOL, STENCIL, 700-DC2849A CUSTOMER NOTICE REV0x ANALOG DEVISES HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT ANALOG DEVICES APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO ANALOG DEVICES 5 4 3 ANALOG DEVICES APPROVALS PCB DES. AK APP ENG. NOE Q. AHEAD OF WHAT'S POSSIBLE A www.analog.com TM TITLE: DEMO CIRCUIT SCHEMATIC, IC NO. OPTICAL LIDAR RECEIVER 4 CHANNEL LTC6561 SKU NO. DC2849A SIZE: N/A 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 PCA BOM: 700-DC2849A_REV02 PCA ASS'Y: 705-DC2849A_REV02 SCALE = NONE 2 SCHEMATIC NO. AND REVISION: 710-DC2849A_REV 02 SHEET DATE: 1 OF 2 1 Rev. C 18 For more information www.analog.com LTC6561 APPLICATIONS INFORMATION DC2808 4-Channel Demonstration Circuit for Electrical Evaluation INPUT 1 INPUT 2 INPUT 4 +5V GND LOW-NOISE SUPPLY INPUT 4 5 4 E2 VCC E3 0.1uF C11 1000pF 11 1 IN4 J4 R17 100 R18 100 14 13 C22 1000pF C23 0.1uF C30 0.1uF 0603 CHSEL1 1 0 1 VCCO NC 18 IN3 O_MUX OUTTERM 25 R9 C16 0.1uF OPT R19 23 1 22 OUT J7 OPT R23 21 20 C 19 R10 OPT R21 OPT R20 OPT 1 OUTTERM J8 R22 OPT DNI 0.1uF C10 1000pF VCC VCC 25V C24 OPT 47.5 24 VCC0 C7 C21 OPT R15 2k 3 GND 25V R14 100 R28 1k 2 JP3 O_MIX 1 R13 100 2 GND VREF3 C29 0.1uF 0603 VCC1 5 OUT VREF2 GND 12 GND CHSEL1 GND IN4 C19 0.1uF 10 VCC2 C17 1000pF J3 0 VCC0 8 9 C 4 IN2 CHSELO 7 17 C14 0.1uF C15 1000pF IN3 VCC 1 LTC6561-UF 25V C12 OPT R11 2k D CHSEL0 U1 C28 0.1uF 0603 R8 100 1 R27 1k 2 JP2 VREF1 2k VCC 3 C8 C9 OPT R5 R7 100 1000pF VREF4 J2 25V R4 100 1 IN2 0.1uF C6 C27 0.1uF 0603 R3 100 C5 16 J1 GND 15 R1 2k 1 IN1 VCC0 1 C4 10uF 0805 3 C3 1uF 0603 1 1 VCC0_SEL VCC EXT 6 E4 Z1 CLL4734A 5.6V 2 C2 1uF 0603 IN1 GND C1 10uF 0805 1 1 JP1 GND D 3 E1 2 GND VCC 3 VCC0 2 VCC C25 1000pF R29 1k 2 DIS EN JP4 3 C26 0.1uF B B PCA ADDITIONAL PARTS A <Variant Name> CUSTOMER NOTICE MP1 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) MP2 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) MP3 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) MP4 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm) NOTE: UNLESS OTHERWISE SPECIFIED LABEL TOOL, STENCIL, 700-DC2808A 1. ALL RESISTORS ARE IN OHMS, 0402 ALL CAPACITORS ARE IN MICROFARADS, 0402 LB1 STNCL1 PCB1 PCB, DC2808A REV03 REV03 SKU NO. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 5 4 3 ANALOG DEVICES APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A PCB DES. AK CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO APP ENG. NOE Q. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED IC NO. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR LTC6561 TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. DC2808A SIZE: N/A AHEAD OF WHAT'S POSSIBLE A www.analog.com TM TITLE: DEMO CIRCUIT SCHEMATIC, RECEIVER TIA 4:1 PCA BOM: 700-DC2808A_REV03 PCA ASS'Y: 705-DC2808A_REV03 SCALE = NONE 2 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 SCHEMATIC NO. AND REVISION: 710-DC2808A_REV03 SHEET DATE: 1 OF 1 1 Rev. C For more information www.analog.com 19 LTC6561 APPLICATIONS INFORMATION FT2724 16-Channel Demonstration Circuit for Optical or Electrical Evaluation FT2724 Front Side 5 FT2724 Back Side 4 3 J3 C15 C16 NC NC NC 24 22 25 GND CHSEL1 OUT 21 23 GND GND 20 NC OUTTERM R2 1k CS2 R3 1k CS3 R4 1k CS4 R5 1k CS5 R6 1k CS6 R7 1k CS7 R8 1k OS0 R9 1k OS1 R10 1k OS2 R11 1k OS3 R12 1k IN2 7 GND VREF3 VREF2 8 9 CS1 5 6 GND 8 1000pF 6 APD13 14 APD15 13 R28 R27 R26 R25 0 0 0 0 12 TSW-112-07-L-D 0.1uF OUT CN8 0.1uF X4 VCC E1 13 0402 14 5 15 16 OS1 17 18 IN4 GND VREF4 7 VREF1 LTC6561IUF-1 VCC2 VCC1 O_MUX CHSEL0 VCCO 19 GND IN2 IN1 GND U4 VCCO 6 5 VCC 4 3 CS2 2 1 C2 1000pF GND GND E2 VCC B CHSEL1 SHUTDOWN NC R16 10K 8 VCC 4 9 TMP35 +VS 2 4 6 8 10 12 14 16 18 20 22 24 4 3 1 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 18 5 TMP35 SOT-23-5 OS2 15 GND VOUT 1k J2 24 17 APD11 NC GND 3 16 16 19 20 21 GND 22 GND 24 25 VCCO 2 R1 C3 OUT O_MUX VCCO OUTTERM CHSEL0 13 15 APD9 NC VCC2 U6 1 14 APD7 17 23 IN3 10 11 GND VREF3 9 VREF2 8 7 IN2 GND 12 VREF4 LTC6561IUF-1 VCC1 OUT 1 C5 1000pF VREF1 CHSEL1 2 IN4 GND U2 23 3 VCC 4 CS0 4 C13 C14 D C1 5 C11 C12 APD5 18 3 C10 APD3 19 2 C9 20 6 C8 APD1 7 C7 E3 CS4 19 C6 10 IN3 C5 11 12 C3 C4 3 C 21 8 R29 0 C2 CS0 2 22 12 R32 R31 R30 0 0 0 8 7 6 CN2 0.1uF X4 11 C1 IN3 1 2 3 4 APD16 10 G/RING NC 10 APD8 6 C/ANOD VREF2 5 APD14 9 GND R20 R17 R18 R19 0 0 0 0 VREF3 4 APD6 U5 16AA0.4-9-SMD 1 CN7 0.1uF X4 GND 3 APD4 APD12 8 IN1 IN1 GND APD2 APD10 7 4 GND IN4 22 2 5 C8 0.047uF 500V 1206 VREF1 GND 21 1 5 C6 0.047uF 500V 1206 1 2 3 4 R21 R22 R23 R24 0 0 0 0 6 13 1 IN3 R15 100 1206 C VCC VREF4 14 R14 10k 1206 CN1 0.1uF X4 B 15 C7 1000pF 500V 1206 R13 10k 1206 VCC1 LTC6561IUF-1 11 13 12 GND 11 10 15 14 CHSEL0 U3 VCC2 VCC VCCO O_MUX 16 8 7 8 7 5 VREF3 IN4 VREF2 GND IN1 16 VCCO 17 GND VREF4 GND 18 OS0 OUTTERM VREF1 -300V NC6-P108-02 OS3 20 VCC2 17 7 NC 21 19 24 20 GND GND OUTTERM O_MUX LTC6561IUF-1 18 1 CS1 GND 2 VCCO U1 VCC1 IN2 6 CHSEL0 9 5 VCCO 6 4 C4 1000pF 22 25 3 OUT GND 2 GND 1 CHSEL1 VCC CS6 23 1 2 CS7 D 2 CS5 CS3 CUSTOMER NOTICE A NOTE: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTORS ARE IN OHMS, 0402 ALL CAPACITORS ARE IN MICROFARADS, 0402 AK GREG F. AHEAD OF WHAT'S POSSIBLE 4 3 N/A SCALE = NONE 2 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 A www.analog.com TM TITLE: SCHEMATIC SIZE ADI CONFIDENTIAL - FOR CUSTOMER USE ONLY THIS CIRCUIT IS PROPRIETARY TO ANALOG DEVICES AND SUPPLIED FOR USE WITH ANALOG DEVICES PARTS. 5 ANALOG DEVICES APPROVALS ANALOG DEVICES HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER - SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT ANALOG DEVICES APPLICATIONS ENGINEERING FOR ASSISTANCE. DATE: IC NO. RECEIVER TIA PLUS 16 CH. LTC6561IUF FT2724A REV. 4 Thursday, February 01, 2018 SHEET 1 OF 1 1 Rev. C 20 For more information www.analog.com LTC6561 APPLICATIONS INFORMATION LB2800 16:4 Channel Demonstration Circuit for Optical Evaluation LB2800 Front Side LB2800 Back Side R17 OPT 0201 R18 OPT 0201 R19 OPT 0201 R20 OPT 0201 APD2 3 APD4 4 APD6 5 APD8 6 APD10 7 APD12 8 APD14 9 APD16 10 R21 OPT 0201 11 R22 OPT 0201 R23 OPT 0201 NC C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 NC NC NC 24 22 25 GND CHSEL1 OUT 21 23 1k 4 C1 CS0 R1 1k 5 1000pF CS1 R2 1k OS0 R9 1k CS2 R3 1k CS3 R4 1k OS1 R10 1k CS4 R5 1k CS5 R6 1k OS2 R11 1k CS6 R7 1k CS7 R8 1k OS3 R12 1k SD1 R35 1k SD2 R36 1k IN2 6 7 GND VREF2 8 1k R33 5 9 6 R34 SD4 21 APD1 20 APD3 19 APD5 18 APD7 17 APD9 16 APD11 15 APD13 14 APD15 4 3 CN7 1.0uF X4 22 1 G/RING GND 20 19 8 2 U5 16AA0.4-9-SMD C/ANOD GND SHDN IN1 VREF3 GND SD3 CS0 3 VREF1 IN4 C8 0.047uF 500V 1206 R38 OPT 2 VCC1 GND IN3 C6 0.047uF 500V 1206 OUTTERM VREF4 13 IN3 1 1 2 3 15 OUT3 1 VCCO LTC6561IUF-1 1 0.1uF 1 J1 VCC CHSEL0 U3 VCC2 14 R15 100 1206 CN1 1.0uF X4 4 16 R14 10k 1206 13 O_MUX GND 14 VCCO 17 10 15 OS0 11 16 18 C7 1000pF 500V 1206 R13 10k 1206 12 GND 11 10 OS3 8 8 7 5 VREF3 IN4 VREF2 GND IN1 17 CS1 12 VREF4 GND C -300V 7 VCC2 LTC6561IUF-1 VREF1 GND 2 TERMINAL BLOCK HV-CON-282836-2 18 2 C3 SD3 1 SHDN 21 19 20 GND 24 22 GND OUTTERM VCCO U1 VCC1 IN2 6 R37 OPT O_MUX 7 5 1000pF CHSEL0 9 4 C4 VCCO 6 3 23 25 2 OUT GND 1 CS6 CHSEL1 VCC D 3 J5 CS7 GND J2 4 SD1 2 5 C25 0.1uF 1 OUT1 FT2724 with Switch Board R25 OPT 0201 R26 OPT 0201 R27 OPT 0201 R28 OPT 0201 D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 TSW-16-07-L-D J6 C R29 OPT 0201 13 R30 OPT 0201 12 R31 OPT 0201 R32 OPT 0201 4 3 6 5 8 9 7 IN2 GND VREF2 VREF3 10 CHSEL0 VCCO R40 OPT OPT 5 2 CS2 1 C2 1000pF 1 OUT4 J3 CUSTOMER NOTICE ANALOG DEVICES APPROVALS AK NOE Q. AHEAD OF WHAT'S POSSIBLE ADI CONFIDENTIAL - FOR CUSTOMER USE ONLY THIS CIRCUIT IS PROPRIETARY TO ANALOG DEVICES AND SUPPLIED FOR USE WITH ANALOG DEVICES PARTS. 4 3 N/A SCALE = NONE 2 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 A www.analog.com TM TITLE: SCHEMATIC SIZE 1. ALL RESISTORS ARE IN OHMS, 0402 ALL CAPACITORS ARE IN MICROFARADS, 0402 B GND VCC 4 ANALOG DEVICES HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER - SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT ANALOG DEVICES APPLICATIONS ENGINEERING FOR ASSISTANCE. NOTE: UNLESS OTHERWISE SPECIFIED E4 GND 3 CS3 C27 0.1uF SD4 E2 VCC 6 GND VCCO 19 SD2 R39 5 O_MUX SHDN 18 E1 C29 1uF 16V 0402 25 17 CHSEL1 OS1 VCC1 OUT OS2 18 GND 17 IN1 VREF1 LTC6561IUF-1 VCC2 C28 10uF 16V 1206 GND U4 VREF4 24 16 GND 23 16 IN4 22 15 GND 14 15 OUTTERM 13 GND 0402 5 21 GND SOT-23-5 14 7 8 NC R16 10k 11 +VS 4 SHDN OUTTERM CS5 C26 0.1uF J4 A SHUTDOWN 20 11 12 IN3 GND VREF3 8 9 10 GND VCCO 13 TMP35 19 20 24 GND 25 1 VCC2 O_MUX VCCO C5 1000pF OUT2 IN4 CHSEL0 21 1 GND IN2 2 3 VREF4 LTC6561IUF-1 VCC1 2 GND U2 VREF1 GND CS4 GND OUT 3 IN1 CHSEL1 4 22 5 VCC 23 6 VREF2 7 B VOUT 12 U6 1 IN3 VCC VCC CN8 1.0uF X4 TMP35 E3 8 7 6 5 CN2 1.0uF X4 2 1 1 2 3 4 R24 OPT 0201 DATE: IC NO. RECEIVER TIA 16:4 LTC6561IUF LB2800A REV. 2 Friday, February 16, 2018 SHEET 1 OF 1 1 Rev. C For more information www.analog.com 21 LTC6561 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm x 4mm) (Reference LTC DWG # 05-08-1697 Rev B) 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 0.75 0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 0.10 1 2 2.45 0.10 (4-SIDES) (UF24) QFN 0105 REV B 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. C 22 For more information www.analog.com LTC6561 REVISION HISTORY REV DATE DESCRIPTION A 09/18 Edited Description PAGE NUMBER Edited Absolute Maximum Ratings 2 B 11/18 Added H-Grade option (-40C to 125C) All C 11/19 Added W-Grade (Automotive) option All 1 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. moreby information www.analog.com 23 LTC6561 TYPICAL APPLICATION Typical Application with Multiplexed Output MULTIPLE LTC6561's VCC1,2 VCCO TIA 47.5 WIRE-OR MUX OUT(2) LTC6561 TIME-OF-FLIGHT DETECTOR IN1 VREF1 OUT OUTPUT STAGE TIA 47.5 IN2 + -150V VREF2 - TIA 4:1 MUX 47.5 GAIN IN3 APD ARRAY VREF3 OUTTERM TIA IN4 VREF4 O_MUX(2) GND CHSEL1,0 O_MUX 6561 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC6560 Single Channel 220MHz 74k TIA Single Channel Version of the LTC6561 LTC6268 500MHz Ultra Low Bias Current FET Input Op Amp GBW = 500MHz, -3dB BW = 350MHz, Ib = 3FA LTC6268-10 4GHz Ultra Low Bias Current FET Input Op Amp De-Comped Version of the LTC6268, GBW = 4GHz LTC6244 Dual 50MHz, Low Noise, Rail-to-Rail CMOS Op Amp GBW = 50MHz, Ib = 1pA LTC6240/LTC6241/ Single/Dual/Quad 18MHz, Low Noise, Rail-to-Rail Output LTC6242 CMOS Op Amps GBW = 18MHz, Ib = 0.2pA, 0.1Hz-10Hz, Noise 550nVP-P LTC6409 10GHz Bandwidth, 1.1nV/Hz Differential Amplifier/ADC Driver GBW = 10GHz, en = 1.1nV/Hz ADA4939-1 Ultralow Distortion Differential ADC Driver Slew Rate: 6800V/s AD9694 Quad 14-Bit, 500Msps, 1.2V/2.5V ADC JESD204B AD9695-625 14-Bit, 1300Msps/625Msps, JESD204B, Dual ADC JESD204B HMCAD1511 High Speed Multi-Mode 8-Bit GSPS A/D Converter Serial LVDS Rev. C 24 D16964-0-11/19(B) For more information www.analog.com www.analog.com (c) ANALOG DEVICES, INC. 2018-2019