LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 LF156QML JFET Input Operational Amplifiers Check for Samples: LF156QML FEATURES COMMON FEATURES * * * * * * * 1 2 Advantages - Replace Expensive Hybrid and Module FET Op Amps - Rugged JFETs Allow Blow-Out Free Handling Compared with MOSFET Input Devices - Excellent for Low Noise Applications Using Either High or Low Source Impedance--Very Low 1/f Corner - Offset Adjust Does Not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers - New Output Stage Allows Use of Large Capacitive Loads (5,000 pF) Without Stability Problems - Internal Compensation and Large Differential Input Voltage Capability APPLICATIONS * * * * * * * Precision High Speed Integrators Fast D/A and A/D Converters High Impedance Buffers Wideband, Low Noise, Low Drift Amplifiers Logarithmic Amplifiers Photocell Amplifiers Sample and Hold Circuits Low Input Bias Current: 30pA Low Input Offset Current: 3pA High Input Impedance: 1012 Low Input Noise Current: 0.01 pA / Hz High Common-Mode Rejection Ratio: 100 dB Large DC Voltage Gain: 106 dB UNCOMMON FEATURES * * * * Extremely Fast Settling - Time to 0.01% 1.5s Fast Slew Rate 12V/s Wide Gain Bandwidth 5MHz Low Input Noise Voltage 12 nV / Hz DESCRIPTION This is the first monolithic JFET input operational amplifier to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FETTM Technology). This amplifier features low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The device is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Connection Diagrams Figure 1. Top View TO-99 Package (LMC) See Package Number LMC 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2013, Texas Instruments Incorporated LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Simplified Schematic *3pF in LF357 series. Detailed Schematic *C = 3pF in LF357 series. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage 22V Differential Input Voltage 40V Input Voltage Range (2) 20V Output Short Circuit Duration Continuous TJmax 150C Power Dissipation at TA = 25C (3) (4) Still Air 560 mW 500 LF/Min Air Flow 1200 mW Still Air JA Thermal Resistance 162C/W 400 LF/Min Air Flow 89C/W JC 32C/W -65C TA +150C Storage Temperature Range Lead Temperature (Soldering 10 sec.) 300C ESD tolerance (5) 1200V (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condition for which the device is functional, but do not ensure specific performance limits . For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax(maximum junction temperature), JA(package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PD=(TJmax-TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. Maximum power dissipation (PDmax)is defined by the package characteristics. Operating the part near the PDmax may cause the part to operate outside specified limits. Human body model, 100pF discharged through 1.5K. Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description Temp ( C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 3 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com LF156 Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = 5V, VCM = 0V, RS = 50 Symbol VIO Parameter Conditions Notes Max Unit -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -0.02 0.02 nA 1 -20 20 nA 2, 3 VCC = 20V -0.1 0.1 nA 1 -10 50 nA 2, 3 VCC = 20V, VCM = -16V -0.1 0.1 nA 1 -10 50 nA 2, 3 -0.1 3.5 nA 1 -10 60 nA 2, 3 -0.1 0.1 nA 1 -10 50 nA 2, 3 -0.1 0.1 nA 1 -10 50 nA 2, 3 -0.1 3.5 nA 1 -10 60 Input Offset Voltage VCC = 20V IIO Input Offset Current +IIB Input Bias Current VCC = 20V VCC = 20V, VCM = 16V -I IB Input Bias Current Subgroups Min VCC = 20V VCC = 20V, VCM = -16V VCC = 20V, VCM = 16V nA 2, 3 +PSRR Power Supply Rejection Ratio +VCC = 20V to 10V, -VCC = -20V 85 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio -VCC = -20V to -10V, +VCC = 20V 85 dB 1, 2, 3 CMRR Common Mode Rejection Ratio VCM = 11V 85 ICC Power Supply Current +IOS Short Circuit Current -IOS Short Circuit Current VCM Common Mode Voltage Range +VOP Output Voltage Swing VO = 0V VO = 0V See RL = 10K RL = 2K -VOP Output Voltage Swing Large Signal Voltage Gain RL = 2K, VO = 0 to 10V RL = 2K, VO = 0 to -10V (1) 4 See (1) 1, 2, 3 mA 1 14 mA 2, 3 -45 -15 mA 1 -35 -10 mA 2 -65 -15 mA 3 15 45 mA 1 10 35 mA 2 15 65 mA 3 -11 11 V 1, 2, 3 12 V 4, 5, 6 10 V 4, 5, 6 -12 V 4, 5, 6 -10 V 4, 5, 6 50 V/mV 4 25 V/mV 5, 6 50 V/mV 4 25 V/mV 5, 6 RL = 10K RL = 2K AVS (1) dB 7.0 See (1) Parameter specified by CMRR test. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 LF156 Electrical Characteristics AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = 5V, VCM = 0V, RS = 50 Symbol Parameter Conditions Notes Min Max Unit Subgroups +SR Slew Rate AV = 1, RLOAD = 2K, CL = 100pfd, VI = -5V to +5V 7.5 V/S 7 -SR Slew Rate AV = 1, RL = 2K, CL = 100pF, VI = +5V to -5V 7.5 V/S 7 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 5 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Typical DC Performance Characteristics 6 Input Bias Current Input Bias Current Figure 2. Figure 3. Input Bias Current Voltage Swing Figure 4. Figure 5. Supply Current Supply Current Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 Typical DC Performance Characteristics (continued) Negative Current Limit Positive Current Limit Figure 8. Figure 9. Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Figure 10. Figure 11. Open Loop Voltage Gain Output Voltage Swing Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 7 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Typical AC Performance Characteristics 8 Gain Bandwidth Normalized Slew Rate Figure 14. Figure 15. Output Impedance Output Impedance Figure 16. Figure 17. LF156 Small Signal Pulse Response, AV = +1 LF156 Large Signal Puls Response, AV = +1 Figure . Figure 18. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 Typical AC Performance Characteristics (continued) Inverter Settling Time Open Loop Frequency Response Figure 19. Figure 20. Bode Plot Common-Mode Rejection Ratio Figure . Figure 21. Power Supply Rejection Ratio Undistorted Output Voltage Swing Figure 22. Figure 23. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 9 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Typical AC Performance Characteristics (continued) 10 Equivalent Input Noise Voltage Equivalent Input Noise Voltage (Expanded Scale) Figure 24. Figure 25. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 APPLICATION HINTS These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pickup" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Typical Circuit Connections Figure 26. VOS Adjustment * * * * VOS is adjusted with a 25k potentiometer The potentiometer wiper is connected to V+ For potentiometers with temperature coefficient of 100 ppm/C or less the additional drift with adjust is 0.5V/C/mV of adjustment Typical overall drift: 5V/C (0.5V/C/mV of adj.) Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 11 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Figure 27. Driving Capacitive Loads * LF156 R = 5k Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) 0.01F. Overshoot 20% Settling time (ts) 5s Typical Applications Figure 28. Settling Time Test Circuit * * * Settling time is tested with the LF156 connected as unity gain inverter. FET used to isolate the probe capacitance Output = 10V step Figure 29. Large Signal Inverter Output, VOUT (from Settling Time Circuit) LF356 12 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 Figure 30. Low Drift Adjustable Voltage Reference * * * * VOUT/T = 0.002%/C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Figure 31. Fast Logarithmic Converter * * * * * Dynamic range: 100A Ii 1mA (5 decades), |VO| = 1V/decade Transient response: 3s for Ii = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/C Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 13 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Figure 32. Precision Current Monitor * * VO = 5 R1/R2 (V/mA of IS) R1, R2, R3: 0.1% resistors Figure 33. 8-Bit D/A Converter with Symmetrical Offset Binary Operation * * R1, R2 should be matched within 0.05% Full-scale response time: 3s EO B1 B2 B3 B4 B5 B6 B7 B8 Comments +9.920 1 1 1 1 1 1 1 1 Positive Full-Scale +0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale -0.040 0 1 1 1 1 1 1 1 (-) Zero-Scale -9.920 0 0 0 0 0 0 0 0 Negative Full-Scale Figure 34. Wide BW Low Noise, Low Drift Amplifier * 14 Parasitic input capacitance C1 3pF interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 R1 C1. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 Figure 35. Boosting the LF156 with a Current Amplifier * IOUT(MAX)150mA (will drive RL 100) * * No additional phase shift added by the current amplifier Figure 36. 3 Decades VCO R1, R4 matched. Linearity 0.1% over 2 decades. Figure 37. Isolating Large Capacitive Loads * * * Overshoot 6% ts 10s When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX): Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 15 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Figure 38. Low Drift Peak Detector * * * * By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf. Leakage of circuit is essentially Ib plus capacitor leakage of Cp. Diode D3 clamps VOUT (A1) to VIN-VD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 1/2RfCD2 where CD2 is the shunt capacitance of D2. Figure 39. High Impedance, Low Drift Instrumentation Amplifier * * 16 System VOS adjusted via A2 VOS adjust Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML LF156QML www.ti.com SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 Figure 40. Fast Sample and Hold * * Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time TA, estimated by: (1) * * * LF156 develops full Sr output capability for VIN 1V Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2 Figure 41. High Accuracy Sample and Hold * * * * * By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. - No VOS adjust required for A2. TA can be estimated by same considerations as previously but, because of the added - propagation delay in the feedback loop (A2) the overshoot is not negligible. Overall system slower than fast sample and hold R1, CC: additional compensation Use LF156 for - Fast settling time - Low VOS Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML 17 LF156QML SNOSAN9A - MARCH 2006 - REVISED MARCH 2013 www.ti.com Figure 42. High Q Notch Filter * * * * 2R1 = R = 10M - 2C = C1 = 300pF Capacitors should be matched to obtain high Q fNOTCH = 120 Hz, notch = -55 dB, Q > 100 Use LF155 for - Low IB - Low supply current Revision History 18 Date Released Revision 03/10/06 A New Released, Corporate format. Electrical Section Delete Drift Value table. 03/25/13 A All Section Originator Changes R. Malone New Release, Corporate format 1 MDS data sheet converted into a Corp. data sheet format. Following MDS data sheet will be Archived MNLF156-X, Rev. 2A0. Delete Drift Value table from Electrical Section. Reson: Referenced product is 883 only. - Submit Documentation Feedback Changed layout of National Data Sheet to TI format. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LF156QML PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) LF156H/883 ACTIVE Package Type Package Pins Package Drawing Qty TO-99 LMC 8 20 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (C) Top-Side Markings (3) Call TI Call TI (4) -55 to 125 LF156H/883 Q ACO LF156H/883 Q >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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