GDDR5 SGRAM
EDW2032BBBG – 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks
Features
• VDD = VDDQ = 1.6V/1.5V ±3% and 1.35V ±3%
• Data rate: 5.0 Gb/s, 6.0 Gb/s, 7.0 Gb/s (MAX)
• 16 internal banks
• Four bank groups for tCCDL = 3 tCK
• 8n-bit prefetch architecture: 256-bit per array read
or write access for x32; 128-bit for x16
• Burst length (BL): 8 only
• Programmable CAS latency: 6–22
• Programmable WRITE latency: 3–7
• Programmable CRC READ latency: 1–3
• Programmable CRC WRITE latency: 8–14
• Programmable EDC hold pattern for CDR
• Precharge: Auto option for each burst access
• Auto refresh and self refresh modes
• Refresh cycles: 16,384 cycles/32ms
• Interface: Pseudo open drain (POD-15) compatible
outputs: 40Ω pull-down, 60Ω pull-up
• On-die termination (ODT): 60Ω or 120Ω (NOM)
• ODT and output driver strength auto calibration
with external resistor ZQ pin: 120Ω
• Programmable termination and driver strength off-
sets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address/command in-
puts
• TC = 0°C to +95°C
• x32/x16 mode configuration set at power-up with
EDC pin
• Single-ended interface for data, address, and com-
mand
• Quarter data rate differential clock inputs CK_t,
CK_c for address and commands
• Two half data rate differential clock inputs, WCK_t
and WCK_c, each associated with two data bytes
(DQ, DBI_n, EDC)
• DDR data (WCK) and addressing (CK)
• SDR command (CK)
• Write data mask function via address bus (single/
double byte mask)
• Data bus inversion (DBI) and address bus inversion
(ABI)
• Input/output PLL on/off mode
• Duty cycle corrector (DCC) for data clock (WCK)
• Address training: Address input monitoring via DQ
pins
• WCK2CK clock training: Phase information via EDC
pins
• Data read and write training via read FIFO (FIFO
depth = 6)
• Read FIFO pattern preloaded by LDFF command
• Direct write data load to read FIFO by WRTR com-
mand
• Consecutive read of read FIFO by RDTR command
• Read/write data transmission integrity secured by
cyclic redundancy check (CRC-8)
• Read/write EDC on/off mode
• Low power modes
• RDQS mode on EDC pin
• On-die temperature sensor with readout
• Automatic temperature sensor controlled self
refresh rate
• Digital RAS lockout
• Vendor ID, FIFO depth and density info fields for
identification
• Mirror function with MF pin
• Boundary scan function with SEN pin
Options1Marking
• Organization
– Density 20
– 64 Meg x 32 (words x bits) 32
• FBGA package
– 170-ball (12mm x 14mm) BG
• Package environment code
– Lead- and halogen-free
(RoHS-compliant)
-F
• Package media
– Dry pack (tray) -D
– Reel -R
• Timing – Cycle time
– 5.0 Gb/s, 4.0 Gb/s -50
– 6.0 Gb/s, 5.0 Gb/s -6A
– 7.0 Gb/s, 5.5 Gb/s -7A
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C) None
• Revision B
Note: 1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2Gb: x16, x32 GDDR5 SGRAM
Features
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 1: Addressing
Parameter 128 Meg x 16 64 Meg x 32
Configuration 8 Meg x 16 x 16 banks 4 Meg x 32 x 16 banks
Refresh count 16K/32ms 16K/32ms
Refresh period 1.9µs 1.9µs
Row addressing A[12:0] A[12:0]
Bank addressing BA[3:0] BA[3:0]
Column addressing A[6:0] A[5:0]
Auto precharge A8 A8
Page size 2KB 2KB
Figure 1: Part Numbering
Elpida Memory
Type
D = Packaged device
Product Family
W = GDDR5 SGRAM
Density/Bank
20 = 2Gb/16-bank
Organization
32 = x32
Power Supply, Interface
B = VDD = 1.6V/1.5V
E D W 20 32 B B BG - 7A - -F D
Packing Media
D = Dry pack (tray)
R = Reel
Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free
Speed
-50 = 5.0 Gb/s
-6A = 6.0 Gb/s
-7A = 7.0 Gb/s
Package
BG = 170-ball FBGA, 12mm x 14mm
Revision
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s web site:
http://www.micron.com.
2Gb: x16, x32 GDDR5 SGRAM
Features
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Ball Assignments and Descriptions
Figure 2: 170-Ball FBGA – MF = 0 (Top View)
1
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
MF
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
2
DQ1
DQ3
EDC0
DBI0_n
DQ5
DQ7
VDDQ
VSSQ
RESET_n
VSSQ
VDDQ
DQ31
DQ29
DBI3_n
EDC3
DQ27
DQ25
3
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
RAS_n
VDDQ
CKE_n
VDDQ
CAS_n
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
4
DQ0
DQ2
VSSQ
WCK01_t
DQ4
DQ6
VDD
A10, A0
ABI_n
A8, A7
VDD
DQ30
DQ28
WCK23_t
VSSQ
DQ26
DQ24
6 7 8 9 10
VREFD
VSS
VDD
VSS
VDDQ
VSSQ
VSS
BA3, A3
SEN
BA1, A5
VSS
VSSQ
VDDQ
VSS
VDD
VSS
VREFD
11
DQ8
DQ10
VSSQ
VDD
DQ12
DQ14
VDD
BA0, A2
CK_c
BA2, A4
VDD
DQ22
DQ20
VDD
VSSQ
DQ18
DQ16
12
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
CS_n
VDDQ
CK_t
VDDQ
WE_n
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
13
DQ9
DQ11
EDC1
DBI1_n
DQ13
DQ15
VDDQ
VSSQ
ZQ
VSSQ
VDDQ
DQ23
DQ21
DBI2_n
EDC2
DQ19
DQ17
14
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREFC
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
5
NC
VSS
VDD
WCK01_c
VDDQ
VSSQ
VSS
A9, A1
A12, RFU
A11, A6
VSS
VSSQ
VDDQ
WCK23_c
VDD
VSS
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
(Top view)
GroundSupplyGDDR5AddressesData
Note: 1. Balls shown with a heavy, solid outline are off in x16 mode.
2Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Figure 3: 170-Ball FBGA – MF = 1 (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
(Top view)
GroundSupplyGDDR5AddressesData
1
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
MF
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
2
DQ25
DQ27
EDC3
DBI3_n
DQ29
DQ31
VDDQ
VSSQ
RESET_n
VSSQ
VDDQ
DQ7
DQ5
DBI0_n
EDC0
DQ3
DQ1
3
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS_n
VDDQ
CKE_n
VDDQ
RAS_n
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
4
DQ24
DQ26
VSSQ
WCK23_t
DQ28
DQ30
VDD
A8, A7
ABI_n
A10, A0
VDD
DQ6
DQ4
WCK01_t
VSSQ
DQ2
DQ0
6 7 8 9 10
VREFD
VSS
VDD
VSS
VDDQ
VSSQ
VSS
BA1, A5
SEN
BA3, A3
VSS
VSSQ
VDDQ
VSS
VDD
VSS
VREFD
11
DQ16
DQ18
VSSQ
VDD
DQ20
DQ22
VDD
BA2, A4
CK_c
BA0, A2
VDD
DQ14
DQ12
VDD
VSSQ
DQ10
DQ8
12
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
WE_n
VDDQ
CK_t
VDDQ
CS_n
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
13
DQ17
DQ19
EDC2
DBI2_n
DQ21
DQ23
VDDQ
VSSQ
ZQ
VSSQ
VDDQ
DQ15
DQ13
DBI1_n
EDC1
DQ11
DQ9
14
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREFC
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
5
NC
VSS
VDD
WCK23_c
VDDQ
VSSQ
VSS
A11, A6
A12, RFU
A9, A1
VSS
VSSQ
VDDQ
WCK01_c
VDD
VSS
NC
Note: 1. Balls shown with a heavy, solid outline are off in x16 mode.
2Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Table 2: 170-Ball FBGA Ball Descriptions
Symbol Type Description
A[12:0] Input Address inputs: Provide the row address for ACTIVE commands. A[5:0] (A6) provide
the column address and A8 defines the auto precharge bit for READ/WRITE com-
mands, to select one location out of the memory array in the respective bank. A8
sampled during a PRECHARGE command determines whether the PRECHARGE ap-
plies to one bank (A8 LOW, bank selected by BA[3:0]) or all banks (A8 HIGH). The ad-
dress inputs also provide the op-code during a MODE REGISTER SET command and
the data bits during LDFF commands. A[12:8] are sampled with the rising edge of
CK_t and A[7:0] are sampled with the rising edge of CK_c.
ABI_n Input Address bus inversion: Reduces the power requirements on address pins by limit-
ing the number of address lines driving LOW to 5. ABI_n is enabled by the corre-
sponding ABI mode register bit.
BA[3:0] Input Bank address inputs: Define the bank to which an ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[3:0] define which mode register is loaded
during the MODE REGISTER SET command. BA[3:0] are sampled with the rising edge
of CK_t.
CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on
the rising edge of CK_t. Address inputs are latched on the rising edge of CK_t and
the rising edge of CK_c. All latencies are referenced to CK_t. CK_t and CK_c are ex-
ternally terminated.
WCK01_t, WCK01_c/
WCK23_t, WCK23_c
Input Data Clocks: WCK_t and WCK_c are differential clocks used for write data capture
and read data output. WCK01_t and WCK01_c are associated with DQ[15:0], DBI0_n,
DBI1_n, EDC0, and EDC1. WCK23_t and WCK23_c are associated with DQ[31:16],
DBI2_n, DBI3_n, EDC2, and EDC3. WCK clocks operate at nominally twice the CK
clock frequency.
CKE_n Input Clock enable: CKE_n enables (registered LOW) and disables (registered HIGH) inter-
nal circuitry and clocks on the SGRAM. The specific circuitry that is enabled/disabled
is dependent upon the device configuration and operating mode. Taking CKE_n
HIGH provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or active power-down (row active in any bank). CKE_n is synchronous for pow-
er-down entry and exit and for self refresh entry. CKE_n must be maintained LOW
throughout read and write accesses. Input buffers (excluding CKE_n) are disabled
during SELF REFRESH operation. The value of CKE_n latched at power-up with RE-
SET_n going HIGH determines the termination value of the address and command
inputs.
CS_n Input Chip select: CS_n enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS_n is registered HIGH, but in-
ternal command execution continues. CS_n is considered part of the command code.
MF Input Mirror function: VDDQ CMOS input. Must be tied to VDDQ or VSS.
RAS_n, CAS_n, WE_n Input Command inputs: RAS_n, CAS_n, and WE_n (along with CS_n) define the com-
mand being entered.
RESET_n Input Reset: RESET_n is an active LOW CMOS input referenced to VSS. A full chip reset may
be performed at any time by pulling RESET_n LOW. With RESET_n LOW all ODTs are
disabled.
SEN Input Scan enable: VDDQ CMOS input. Must be tied to VSS when not in use.
2Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Table 2: 170-Ball FBGA Ball Descriptions (Continued)
Symbol Type Description
DQ[31:0] I/O Data input/output: Bidirectional 32-bit data bus.
DBI[3:0]_n I/O Data bus inversion: Reduces the DC power consumption and supply noise induced
jitter on data pins. DBI0_n is associated with DQ[7:0], DBI1_n with DQ[15:8], DBI2_n
with DQ[23:16], and DBI3_n with DQ[31:24].
EDC[3:0] Output Error detection code: The calculated CRC data is transmitted on these pins. In ad-
dition, these pins drive a hold pattern when idle and can be used as an RDQS func-
tion. EDC0 is associated with DQ[7:0], EDC1 with DQ[15:8], EDC2 with DQ[23:16], and
EDC3 with DQ[31:24].
VDD Supply Power supply: 1.6V/1.5V ±3% and 1.35V ±3%.
VDDQ Supply DQ power supply: 1.6V/1.5V ±3% and 1.35V ±3%. Isolated on the device for im-
proved noise immunity.
VREFC Supply Reference voltage for control and address: VREFC must be
maintained at all times (including self refresh) for proper device operation.
VREFD Supply Reference voltage for data: VREFD must be maintained at all times (including self
refresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an
external 120Ω resistor (ZQ), which is tied to VSSQ.
NC – No connect: These balls should be left unconnected (the ball has no connection to
the SGRAM or to other balls).
2Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Package Dimensions
Figure 4: 170-Ball FBGA (BG)
A
0.2 S 1.1 ±0.1
0.35 ±0.05
S
12.0 ±0.1
Ball A1 ID
Ball A1 ID
14.0 ± 0.1
170- 0.45 ±0.05
B
0.15 MS
12.8
A B
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2.0
10.4
0.8
0.8
0.2 S B
0.2 S A
0.12 S
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
2Gb: x16, x32 GDDR5 SGRAM
Package Dimensions
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
