Document Number: 91207 www.vishay.com
S11-0446-Rev. C, 14-Mar-11 1
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
Power MOSFET
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptable Power Supply
• High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Full Bridge Converters
• Power Factor Correction Boost
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 4.87 mH, Rg = 25 , IAS = 22 A (see fig. 12).
c. ISD 22 A, dI/dt 190 A/µs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
PRODUCT SUMMARY
VDS (V) 500
RDS(on) ()V
GS = 10 V 0.23
Qg (Max.) (nC) 120
Qgs (nC) 32
Qgd (nC) 52
Configuration Single
N-Channel MOSFET
G
D
S
TO-247AC
G
D
S
Available
RoHS*
COMPLIANT
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free IRFP22N50APbF
SiHFP22N50A-E3
SnPb IRFP22N50A
SiHFP22N50A
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500 V
Gate-Source Voltage VGS ± 30
Continuous Drain Current VGS at 10 V TC = 25 °C ID
22
A
TC = 100 °C 14
Pulsed Drain CurrentaIDM 88
Linear Derating Factor 2.2 W/°C
Single Pulse Avalanche EnergybEAS 1180 mJ
Repetitive Avalanche CurrentaIAR 22 A
Repetitive Avalanche EnergyaEAR 28 mJ
Maximum Power Dissipation TC = 25 °C PD277 W
Peak Diode Recovery dV/dtcdV/dt 4.8 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91207
2S11-0446-Rev. C, 14-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 µs; duty cycle 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -40
°C/WCase-to-Sink, Flat, Greased Surface RthCS 0.24 -
Maximum Junction-to-Case (Drain) RthJC -0.45
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.55 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 30 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 500 V, VGS = 0 V - - 25 µA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 13 Ab--0.23
Forward Transconductance gfs VDS = 50 V, ID = 13 Ab12 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
- 3450 -
pF
Output Capacitance Coss - 513 -
Reverse Transfer Capacitance Crss -27-
Output Capacitance Coss VGS = 0 V
VDS = 1.0 V, f = 1.0 MHz 4935
VDS = 400 V, f = 1.0 MHz 137
Effective Output Capacitance Coss eff. VDS = 0 V to 400 Vc264
Total Gate Charge Qg
VGS = 10 V ID = 22 A, VDS = 400 V,
see fig. 6 and 13b
- - 120
nC Gate-Source Charge Qgs --32
Gate-Drain Charge Qgd --52
Turn-On Delay Time td(on)
VDD = 250 V, ID = 22 A,
RG = 4.3 , RD = 11, see fig. 10b
-26-
ns
Rise Time tr -94-
Turn-Off Delay Time td(off) -47-
Fall Time tf -47-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS
MOSFET symbol
showing the
integral reverse
p - n junction diode
--22
A
Pulsed Diode Forward CurrentaISM --88
Body Diode Voltage VSD TJ = 25 °C, IS = 22A, VGS = 0 Vb--1.5V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 22 A, dI/dt = 100 A/µsb- 570 850 ns
Body Diode Reverse Recovery Charge Qrr -6.19.2µC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
S
D
G
Document Number: 91207 www.vishay.com
S11-0446-Rev. C, 14-Mar-11 3
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
www.vishay.com Document Number: 91207
4S11-0446-Rev. C, 14-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91207 www.vishay.com
S11-0446-Rev. C, 14-Mar-11 5
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
V
DS
V
DD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
R
G
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-V
DD
A
10 V
Vary tp to obtain
required IAS
IAS
VDS
VDD
VDS
tp
www.vishay.com Document Number: 91207
6S11-0446-Rev. C, 14-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current
Fig. 13b - Gate Charge Test Circuit
QGS QGD
QG
V
G
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91207 www.vishay.com
S11-0446-Rev. C, 14-Mar-11 7
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
IRFP22N50A, SiHFP22N50A
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91207.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Package Information
www.vishay.com Vishay Siliconix
Revision: 24-Sep-12 1Document Number: 91360
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TO-247AC (High Voltage)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -
b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144
c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224
D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC
ECN: X12-0167-Rev. B, 24-Sep-12
DWG: 5971
0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
123
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP (Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
CC
View B
(b1, b3, b5) Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
5
5
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Revision: 12-Mar-12 1Document Number: 91000
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