QuickLogic Military FPGA Introduction - QuickLogic

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Device Highlights

Flexible Programmable Logic

•0.25 µ, 5 layer metal CMOS process

•2.5 V Vcc, 2.5/3.3 V drive capable I/O

•Up to 4032 logic cells

•Up to 583,000 max system gates

•Up to 347 I/O

Embedded Dual Port SRAM

•Up to thirty-six 2,304-bit dual port SRAM

blocks

•Up to 82,900 RAM bits

•RAM/ROM/FIFO Wizard for automatic

configuration

•Configurable and cascadable

Applications

•Signal processing operators

•Signal processing functions

•Networking/communications for VoIP

•Speech/voice processing

•Channel coding

Programmable I/O

•High performance: <3.2 ns Tco

•Programmable slew rate control

•Programmable I/O standards:

•LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

•Eight independent I/O banks

•Three register configurations: input,

output and output enable

Advanced Clock Network

•Nine global clock networks

•One dedicated

•Eight programmable

•Sixteen I/O (high-drive) networks

•Twenty quad-net networks: five per quadrant

Figure 1: Eclipse Block Diagram

Embedded RAM BlocksPLL PLL

Fabric

Embedded RAM BlocksPLL PLL

Combining Performance, Density, and Embedded RAM

Eclipse Family Data Sheet

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Eclipse Family Data Sheet Rev C

QuickWorks Design Software

The turnkey QuickWorks package provides the most complete ESP and FPGA software solution from design

entry to logic synthesis, to place and route to simulation. The packages provide a solution for designers who

use third party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic and other third-party tools for

design entry, synthesis, or simulation.

Process Data

Eclipse is fabricated on a 0.25 µm five-layer metal CMOS process. The core voltage is 2.5 V VCC supply

and 3.3 V tolerant I/O with the addition of 3.3 V VCCIO. Eclipse is available in commercial, industrial, and

military temperature grades.

Programmable Logic Architectural Overview

The Eclipse logic cell structure is presented in Figure 2. This architectural feature addresses current register-

intensive designs.

Table 1: Eclipse Product Family Members

QL6250 QL6325 QL6500 QL6600

Max Gates 248,160 320,640 488,064 583,008

Logic Array 40x24 48x32 64x48 72x56

Logic Cells 960 1,536 3,072 4,032

Max Flip-Flops 2,670 4,002 7,185 9,105

Max I/O 250 310 347 347

RAM Modules 20 24 32 36

RAM bits 46,100 55,300 73,700 82,900

Packages

PQFP 208 208 - -

PBGA (1.27 mm) - - 516 516

FPBGA (1.0 mm) 484 484 484 484

LFBGA (0.8 mm) 280 280 280 280

Table 2: Max I/O per Device /Package Combination

Device 208 PQFP 280 FPBGA 484 PBGA 516 PBGA

QL6250 99 163 250 -

QL6325 99 163 310 -

QL6500 - 163 327 347

QL6600 - 163 327 347

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Eclipse Family Data Sheet Rev C

The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the

NZ output or directly from a dedicated input.

NOTE:

The input "PP" is not an "input" in the classical sense. It can only be tied high or low using default

links only and is used to select which path "NZ" or "PS" is used as an input to the register. All other

inputs can be connected not only to "tiehi" and "tielo" but to multiple routing channels as well.

The complete logic cell consists of 2 6-input AND gates, 4 two-input AND gates, 7 two-to-one multiplexers

and 2 D flip-flop with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register

control lines) and fits a wide range of functions with up to 17 simultaneous inputs. It has 6 outputs;

4 combinatorial and 2 registered. The high logic capacity and fan-in of the logic cell accommodate many

user functions with a single level of logic delay while other architectures require two or more levels of delay.

Figure 2: Eclipse LogicCell

Table 3: Performance Standards

Function Description Slowest Speed Grade Fastest Speed Grade

Multiplexer 16:1 5 ns 2.8 ns

Parity Tree 24 6 ns 3.4 ns

36 6 ns 3.4 ns

Counter 16 bit 250 MHz 450 MHz

32 bit 250 MHz 450 MHz

FIFO

128 x 32 155 MHz 280 MHz

256 x 16 155 MHz 280 MHz

128 x 64 155 MHz 280 MHz

Clock to Out 4.5 ns 2.5 ns

System clock 200 MHz 400 MHz

Q2Z

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Eclipse Family Data Sheet Rev C

RAM Modules

The Eclipse Family includes multiple dual-port 2,304-bit RAM modules for implementing RAM, ROM and

FIFO functions. Each module is user-configurable into four different block organizations. Modules can also

be cascaded horizontally to increase their effective width or vertically to increase their effective depth as

shown in Figure 3. The RAM can also be configured as a modified Harvard Architecture, similar to those

found in DSPs.

Figure 3: 2,304-bit Eclipse RAM Module

The number of RAM modules varies from 20 to 36 blocks within the Eclipse family, for a total of

46.1 to 82.9 K bits of RAM. Using two "mode" pins, designers can configure each module into 128 x 18

(Mode 0), 256 x 9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily

cascadable to increase their effective width and/or depth. See Figure 4.

Figure 4: Cascaded RAM Modules

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word

lengths of up to 18 bits and address spaces of up to 1024 words. Depending on the mode selected, however,

some higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE)

acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable

for asynchronous READ operation (ASYNCRD input high).

MODE[1:0]

WA[9:0]

WD[17:0]

WCLK

2,304-bit Module

SYNCRD

RA[9:0]

RD[17:0]

RCLK

WDATA

RDATA

WADDR

WDATA

RADDR

RAM

Module

(2,304 bits)

RAM

Module

(2,304 bits)

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Eclipse Family Data Sheet Rev C

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 512 words. In this case address signals higher

than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data

outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT

signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

I/O Cell Structure

Eclipse features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-

directional I/O pins and input-only pins. All I/O pins are 2.5 V and 3.3 V tolerant and comply with the

specific I/O standard selected. All dedicated input pins are 2.5 V tolerant and comply with the LVCMOS2

standard.For single ended I/O standards, VCCIO specifies the input tolerance and the output drive. For

voltage referenced I/O standards (e.g., SSTL), the voltage supplied to the INREF pins in each bank specifies

the input switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V

compliance. Eclipse can also support the LVDS and LVPECL I/O standards with the use of external resistors

(see Table 4).

As designs become more complex and requirements more stringent, several application-specific I/O

standards have emerged for specific applications. I/O standards for processors, memories, and a variety of

bus applications have become commonplace and a requirement for many systems. In addition, I/O timing

has become a greater issue with specific requirements for setup, hold, clock to out, and switching times.

Eclipse has addressed these new system requirements and now includes a completely new I/O cell which

consists of programmable I/Os as well as a new cell structure consisting of three registers—Input, Output,

and Output Enable (OE).

Eclipse offers banks of programmable I/Os that address many of the bus standards that are popular today.

As shown in Figure 5 each bi-directional I/O pin is associated with an I/O cell which features an input

to-one output multiplexers.

Table 4: I/O Standards and Applications

I/O Standard INREF Reference

Voltag e Output Voltage Application

LVTTL n/a 3.3 General Purpose

LVCMOS2 n/a 2.5 General Purpose

PCI n/a 3.3 PCI Bus Applications

GTL+ 1.0 n/a Backplane

SSTL3 1.5 3.3 SDRAM

SSTL2 1.25 2.5 SDRAM

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Eclipse Family Data Sheet Rev C

Figure 5: Eclipse I/O Cell

The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As

shown in Figure 5, each bi-directional I/O pin is associated with an I/O cell which features an input register,

an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one

multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either VCC

or GND.

For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to

the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to

the array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing

data to be captured with fast set-up times without consuming internal logic cell resources. The comparator

and multiplexor in the input path allows for native support of I/O standards with reference points offset from

traditional ground.

For output functions, I/O pins can receive combinatorial or registered data from the logic array. For

combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For

registered output operation, the array logic drives the D input of the output cell register which in turn drives

the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be

driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register

does not need to drive the routing the length of the output path is also reduced.

The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O

pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic

cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the

global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow

PAD

OUTPUT ENABLE

OUTPUT

INPUT

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Eclipse Family Data Sheet Rev C

for the output cell. For combinatorial control operation data is routed from the logic array through a

multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all

I/O cells within the same bank.

For registered control operation, the array logic drives the D input of the OE cell register which in turn drives

the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered

signal to be driven to the three-state control.

When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register

to be used for registered feedback into the logic array.

I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular

routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/Os. The

CLK and RESET signals share common lines, while the clock enables for each register can be independently

controlled. I/O interface support is programmable on a per bank basis. Figure 6 illustrates the I/O bank

configurations.

Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply

inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to

which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and

INREF can be shared within the same bank (e.g., PCI and LVTTL).

Figure 6: Multiple I/O Banks

Embedded RAM BlocksPLL PLL

Fabric

Embedded RAM BlocksPLL PLL

VCCIO 0 INREF 0 VCCIO 1 INREF 1

VCCIO 2

INREF 2

VCCIO 3

INREF 3

INREF 4VCCIO 4

INREF 5

VCCIO 5

INREF 6

VCCIO 6

INREF 7

VCCIO 7

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Eclipse Family Data Sheet Rev C

Programmable Slew Rate

Each I/O has programmable slew rate capability. The rate is programmable to one of two slew rates either

fast or slow. The slower rate can be used to reduce ground bounce noise.

Programmable Weak Pull-Down

Programmable weak-pull down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the

need for external pull down resistor for used I/O. The spec for pull-down current is maximum of 150 µA

under worst case condition.

Figure 7: Programmable I/O Weak Pull-Down

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Eclipse Family Data Sheet Rev C

Clock Networks

Global Clocks

There are eight global clock networks in the Eclipse device family. Global clocks can drive logic cell, I/O,

and RAM blocks in the device. Five global clocks have access to a Quad Net (local clock network) connection

with a programmable connection to the register inputs. Global clock pins are 2.5 V, LVCMOS2, compliant.

Figure 8: Global Clock Methodology

Quad-Net Network

There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net

is local to a quadrant. Before driving the columns clock buffers, the quad-net is driven by the output of a mux

which selects between the CLK input and an internally generated clock source (see Figure 9).

Quad Net

CLK Pin

Global Clock Net

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Eclipse Family Data Sheet Rev C

Figure 9: Global Clock Structure Schematic

Dedicated Clock

There is one dedicated clock each device of the Eclipse Family (QL6250, QL6325, QL6500, and QL6600).

This clock connects to the clock input of the LogicCell and I/O registers, and RAM blocks through a

hardwired connection and is multiplexed with the programmable clock input. The dedicated clock provides

a fast global network with low skew. Users have the ability to select either the dedicated clock or the

programmable clock (Figure 10). The dedicated clock is 2.5 V, LVCMOS2, compliant.

Figure 10: Dedicated Clock Circuitry within Logic Cell

NOTE:

For more information on the clocking capabilities of Eclipse FPGAs, refer to the QuickLogic

Application Note 68 at http://www.quicklogic.com/images/appnote68.pdf.

I/O Control and Local Hi-Drives

Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK and EN inputs

of I/Os in that bank. These input only pins also serve as high drive inputs to a quadrant. As an I/O control

or high drive, these buffers can be driven by the internal logic. I/O control pins, called IOCTRL in the pin

tables, are 2.5 V, LVCMOS2, compliant.

tPGCK tBGCK

Internally generated clock, or

clock from general routing network

Global Clock

(CLK) Input

Global Clock Network

Global Clock Buffer

Programmable Clock or

General Routing

Dedicated Clock CLK

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Eclipse Family Data Sheet Rev C

Phase Locked Loops (PLLs)

Instead of requiring extra components, designers simply need to instantiate one of the pre-configured

models described in this section and listed in Table 5. The QuickLogic built-in PLLs support a wider range

of frequencies than many other PLLs. Also, QuickLogic PLLs can be cascaded to support different ranges

of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock

frequency. Most importantly, they achieve a very short clock-to-out time—generally less than 3 ns. This low

clock-to-out time is achieved by the PLL subtracting the clock tree delay through the feedback path,

effectively making the clock tree delay zero.

Figure 11 illustrates a typical QuickLogic ESP PLL.

Figure 11: PLL Block

Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal

can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself.

Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the

local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that

a phase detector (the crossed circle in Figure 11) can compare the two signals. If the phases of the external

and local signals are not within the tolerance required, the phase detector sends a signal through the charge

pump and loop filter (Figure 11). The charge pump generates an error voltage to bring the VCO back into

alignment and the loop filter removes any high frequency noise before the error voltage enters the VCO.

This new VCO signal enters the clock tree to drive the chip circuitry.

Fout represents the clock signal that emerges from the output pad (the output signal PLLPAD_OUT is

explained in Table 6). This clock signal is meaningful only when the PLL is configured for external use;

otherwise, it remains in high Z state, as shown in the post-simulation waveform.

Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL presented in

Figure 11 controls the clock tree in the fourth Quadrant of the FPGA. As previously mentioned, QuickLogic

PLLs compensate for the additional delay created by the clock tree itself by subtracting the clock tree delay

through the feedback path.

vco

Filter

FIN

FOUT

1st Quadrant

2nd Quadrant

3rd Quadrant

4th Quadrant

Clock

Tree

Frequency Divide

Frequency Multiply

PLL Bypass

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Eclipse Family Data Sheet Rev C

For more specific information on the Phase Locked Loops, please refer to Application Note 58 at

http://www.quicklogic.com/images/appnote58.pdf

PLL Modes of Operation

QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output

frequency. Table 5 indicates the features of each mode.

Table 5: PLL Mode Frequencies

PLL Model Output Frequency Input Frequency Rangea

a. The input frequency can range from 165 MHz to 300 MHz, while output frequency ranges from 25 MHz to 250 MHz.

When you add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output

frequencies.

Output Frequency Range

PLL_HFb

b. HF stands for high frequency and LF stands for low frequency.

Same as input frequency 66 MHz–150 MHz 66 MHz–150 MHz

PLL_LF Same as input frequency 25 MHz–133 MHz 25 MHz–133 MHz

PLL_MULT2HF 2 × input frequency 50 MHz–125 MHz 100 MHz–250 MHz

PLL_MULT2LF 2 × input frequency 16 MHz–50 MHz 32 MHz–100 MHz

PLL_DIV2HF 1/2 × input frequency 100 MHz–250 MHz 50 MHz–125 MHz

PLL_DIV2LF 1/2 × input frequency 50 MHz–100 MHz 25 MHz–50 MHz

PLL_MULT4 4 × input frequency 16 MHz–40 MHz 64 MHz–160 MHz

PLL_DIV4 1/4 × input frequency 100 MHz–300 MHz 25 MHz–75 MHz

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Eclipse Family Data Sheet Rev C

PLL Signals

Table 6 summarizes the key signals in QuickLogic PLLs.

NOTE:

For PLL AC specifications, contact the factory.

Programmable Logic Routing

Eclipse devices are delivered with six types of routing resources as follows: short (sometimes called

segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires

span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the

length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires

supply VCC and GND (Logic ‘1’ and Logic ‘0’) to each column of logic cells.

Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are

typically used to implement intermediate length or medium fan-out nets.

Express lines run the length of the programmable logic uninterrupted. Each of these lines has a higher

capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the

length of the device. The resistance is lower because the express wires do not require the use of "pass" links.

Express wires provide higher performance for long routes or high fan-out nets.

Distributed networks are described in the clock/control section. These wires span the programmable logic

and are driven by "column clock" buffers. All clock network pin buffers (Dedicated and Global) are hard wired

to individual sets of column clock buffers.

Table 6: PLL Signals

Signal Name Description

PLLCLK_INa

a. Because PLLCLK_IN and PLL_RESET signals have INPAD, and PLLPAD_OUT has OUTPAD, you do not have to add addi-

tional pads to your design.

Input clock signal

PLL_RESET Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0.

This signal must be asserted and then released in order for the LOCK_DETECT to work.

ONn_OFFCHIP

PLL output This signal selects whether the PLL will drive the internal clock network or be used off-chip.

This is a static signal, not a dynamic signal.

Tied to GND = outgoing signal drives internal gates.

Tied to VCC = outgoing signal used off-chip.

CLKNET_OUT Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that

this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT).

PLLCLK_OUT Out from PLL to internal gates This signal can drive the internal gates after going through the PLL.

For this to work, ONn_OFFCHIP must be tied to GND.

PLLPAD_OUT Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must be

tied to VCC.

LOCK_DETECT

Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after 10

clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon

release of the RESET signal.

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Eclipse Family Data Sheet Rev C

Global POR (Power-On Reset)

The Eclipse family of devices features a global power-on reset. This reset is hardwired to all registers and

resets them to Logic ‘0’ upon power-up of the device. In QuickLogic devices, the asynchronous Reset input

to flip-flops has priority over the Set input. Therefore, the Global POR resets all flip-flops during power-up.

If you want to set the flip-flops to Logic ‘1’, you must assert the “Set” signal after the Global POR signal has

been deasserted.

Figure 12: Power-On Reset

Joint Test Access Group (JTAG) Information

Figure 13: JTAG Block Diagram

VCC

Power-on

Reset

QXXXXXXX 0

TCK

TMS

TRSTB

RDI TDO

Instruction Decode

Control Logic

TAp Controller

State Machine

(16 States)

Instruction Register

Boundary-Scan Register

(Data Register)

Mux

Bypass

Mux

Internal

User Defined Data Register

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Eclipse Family Data Sheet Rev C

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one

problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE

standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture.

The JTAG boundary scan test methodology allows complete observation and control of the boundary pins

of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert

with the Instruction Register (IR), which allow users to run three required tests along with several user-defined

tests.

JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem

tests for fuller verification of higher level system elements.

The 1149.1 standard requires the following three tests:

•Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device

into an external boundary test mode, selecting the boundary scan register to be connected between the

TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test

patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis.

•Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while

selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the

boundary scan register can be accessed via a data scan operation, allowing users to sample the functional

data entering and leaving the device.

•Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the

data passes through the bypass register. The Bypass instruction allows users to test a device without

passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing

serial data to be transferred through a device without affecting the operation of the device.

JTAG BSDL Support

•BSDL-Boundary Scan Description Language

•Machine-readable data for test equipment to generate testing vectors and software

•BSDL files available for all device/package combinations from QuickLogic

•Extensive industry support available and Automatic Test-vector Generation (ATG)

Security Fuses

There are two security links: one to disable reading logic from the array, and the second to disable JTAG

access to the device. Programming these optional links completely disables access to the device from the

outside world and provides an extra level of design security not possible in SRAM-based FPGAs. The option

to program these fuses is selectable via QuickWorks in the Tools/Options/Device Programming window in

SpDE.

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Eclipse Family Data Sheet Rev C

Flexibility Fuse

The flexibility link enables Power-Up loading of the Embedded RAM blocks. If the link is programmed, the

Power Up Loading state machine is activated during power-up of the device. The state machine

communicates with an external EPROM via the JTAG pins to download memory contents into the on-chip

RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they

normally would. The option to program this bit is selectable via QuickWorks in the Tools/Options/Device

Programming window in SpDE. For more information on Power-Up Loading refer to QuickLogic

Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf.

Packaging

Eclipse product is offered in the following packages. All packages support commercial, industrial, and

military temperature ranges.

Table 7: Packaging Options

208 280 484 516

Package Style PQFP FPBGA PBGA PBGA

Pitch 0.8mm 1.0mm 1.27mm

Ordering Code PQ208 PT280 PS484 PB516

QL6250 X X X

QL6325 X X X

QL6500 X X X

QL6600 X X X

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Eclipse Family Data Sheet Rev C

Ordering Information

Contact Information

Telephone: (408) 990 4000 (US)

(416) 497 8884 (Canada)

+(44) 1932 57 9011 (Rest of Europe)

+(49) 89 930 86 170 (Germany & Benelux)

+(8621) 2890 3029 (Asia)

+(81) 45 470 5525 (Japan)

E-mail: info@quicklogic.com

Support: support@quicklogic.com

Web site: http://www.quicklogic.com/

QL 6250 - 7 PQ208 C

QuickLogic Device

Eclipse Device

Part Number

6250, 6325, 6500, and 6600

Speed Grade

4 = Quick

5 = Fast

6 = Faster

7 = Fastest

Operating Range

C = Commercial

I = Industrial

M = Military

Package Lead Count

PQ208 = 208-pin PQFP

PT280 = 280-ball LFBGA (0.8 mm)

PS484 = 484-ball FPBGA (1.0 mm)

PB516 = 516-ball PBGA (1.27 mm)

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Eclipse Family Data Sheet Rev C

Revision History

The information contained in this product brief, and the accompanying software programs are protected by

make periodic modifications of this product without obligation to notify any person or entity of such revision.

Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written

consent of an authorized representative of QuickLogic is prohibited.

QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are trademarks of

QuickLogic Corporation.

Verilog is a registered trademark of Cadence Design Systems, Inc.

Table 8: Revision History

Revision Date Comments

A Jan 2002 First release.

B April 2003 Brian Faith and Kathleen Murchek

C May 2003 Brian Faith and Kathleen Murchek