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Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Rev.1.07 Mar 19, 2009 Page 1 of 60
REJ03B0140-0107
DESCRIPTION
The 7545 Group is the 8-bit microcomputer based on the 740
family core technology.
The 7545 Group has an 8-bit timer , power -on reset circuit and the
voltage drop detection circuit. Also, Function set ROM is
equipped.
FEATURES
• Basic machine-language instructions .................................. 71
• The minimum instruction execution time .................... 2.00 µs
(at 4 MHz oscillation frequency for the shortest instruction)
• Memory size ROM .............. .............. .. .......... 4K to 60K bytes
RAM............................................ 256, 512 bytes
• Programmable I/O ports ...................................................... 25
• Key-on wakeup input .................................................. 8 inputs
• LED output port................. .............. ............. ............. ............. 8
• Interrupts.................................................... 7 sources, 7 vectors
• Timers ..................... ......................... ........................ .... 8-bit × 3
• Carrier wave generating circuit .......1 cha nnel (8-bit timer × 2)
• Clock generating circuit .......................... ............. .B uilt-in type
(connect to external ceramic resonator or quartz-crystal
oscillator)
• Watchdog tim er ...................... ............. .............. ........16-bit × 1
• Power-on reset circuit............................................Built-in type
• Voltage drop detection circuit................................Built-in type
• Power source voltage
XIN oscillation frequency at ceramic/quartz-crystal oscillation
At 4 MHz............................. ............. 1.8 to 3.6 V
• Power dissipation ......... ............. .............. ...................... 1.8mW
• Operating temperature range.................................−20 to 85 °C
APPLICATION
Remote control transmit.
Fig. 1 Pin configuration (PLQP0032GB-A type)
Package type: PLQP0032GB-A (32P6U-A)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
87
65
34
VCC
CNVSS
P25(LED5)P03/KEY3
P00/KEY0
P02/KEY2
P01/KEY1
P04/KEY4
P37
P36
P35
M37545Gx-XXXGP
M37545GxGP
P26(LED6)
P27(LED7)
P42/CARR
VDDR
RESET
12
P23(LED3)
P24(LED4)
P22(LED2)
P21(LED1)/INT1
P20(LED0)/INT0
P07/KEY7
P06/KEY6
P05/KEY5
XOUT
XIN
VSS
P30
P31
P32
P33
P34
24 23 22 21 20 19 18 17
PIN CONFIGURATION (TOP VIEW)
7545 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0140-0107
Rev.1.07
Mar 19, 2009
Rev.1.07 Mar 19, 2009 Page 2 of 60
REJ03B0140-0107
7545 Group
Fig. 2 Pin configuration (PLSP0032JB-A type)
Fig. 3 Pin configuration (42S1M type)
P21(LED1)/INT132
M37545GxKP
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED6)
P27(LED7)
P42/CARR
RESET
VCC
XIN
XOUT
VSS
P30
P20(LED0)/INT0
P07/KEY7
P06/KEY6
P05/KEY5
P04/KEY4
P03/KEY3
P02/KEY2
P01/KEY1
P37
P00/KEY0
P35
P34
P33
P32
P31
P36
CNVSS
VDDR
Package type: PLSP0032JB-A
PIN CONFIGURATION (TOP VIEW)
Package type: 42S1M
P22(LED2)42
M37545RLSS
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
P23(LED3)
P24(LED4)
NC
P25(LED5)
P26(LED6)
P27(LED7)
P40(LED8)
P42/CARR
NC
NC
VDDR
RESET
P41(LED9)
P21(LED1)/INT1
P20(LED0)/INT0
P07/KEY7
P06/KEY6
P05/KEY5
P04/KEY4
P03/KEY3
P02/KEY2
P01/KEY1
P00/KEY0
P36
NC
P35
P34
P33
P37
26
25
24
23
22
17
18
19
20
21
CNVSS
VCC
XIN
XOUT
VSS
P32
P31
P30
P11
P10
PIN CONFIGURATION (TOP VIEW)
Rev.1.07 Mar 19, 2009 Page 3 of 60
REJ03B0140-0107
7545 Group
Table 1 Performance overview (1)
Parameter Function
Number of basic instructions 71
Instruction execution time 2.00 µs (Minimum instruction)
Memory sizes ROM M37545G1 4096 bytes × 8 bits
M37545G2 8192 bytes × 8 bits
M37545G4 16384 bytes × 8 bits
M37545G6 24576 bytes × 8 bits
M37545G8 32768 bytes × 8 bits
M37545GC 49152 bytes × 8 bits
M37545GF 61440 bytes × 8 bits
RAM M37545G1/G2 RAM1: 240 bytes × 8 bits, RAM2: 16 bytes × 8 bits
M37545G4/G6/G8/GC/GF RAM1: 384 bytes × 8 bits, RAM2: 128 bytes × 8 bits
I/O port P00−P07I/O • 1-bit × 8
• CMOS compatible input level
• CMOS 3-state output structure
• Whether the pull-up function/key-on wakeup function is to be used or not
can be determined by program.
P10, P11 I/O (RLSS-only pin) • 1-bit × 2
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
P20−P27I/O • 1-bit × 8
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
• P2 can output a large current for driving LED.
•P2
0 and P21 are also used as INT0 and INT1, respectively.
P30−P37I/O • 1-bit × 8
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
P40, P41I/O (RLSS-only pin) • 1-bit × 2
• CMOS compatible input level
• CMOS 3-state output structure
P42I/O • 1-bit × 1
• CMOS compatible input level
• CMOS 3-state output structure
• Carrier wave output pin for remote-control transmitter
Timer Timer 1 8-bit timer with timer 1 latch
Count source is Prescaler output.
Timer 2 8-bit timer with timer 2 primary latch and timer 2 secondary latch
Count source can be selected from f(X
IN
)/16, f(X
IN
)/8, f(X
IN
)/2 or f(X
IN
)/1.
Timer 3 8-bit timer with timer 3 latch
Count source can be selected from f(X
IN
)/16, f(X
IN
)/8 or f(X
IN
)/2 or carrier wave output.
Carrier wave generating circuit Remote-control waveform is generated by using timer 2 and timer 3.
455 kHz carrier wave generating mode is available.
Watchdog timer 16-bit × 1
Power-on reset circuit Built-in
Voltage drop detection circuit (Not available for RLSS) Typ. 1.75 V (Ta=25 °C)
Interrupt Source 7 sources (External × 3, Timer × 3, Software)
Function set
ROM area Function set ROM Function set ROM is assigned to address FFDA16.
Enable/disable of watchdog timer and STP instruction can be selected.
Valid/invalid of voltage drop detection circuit can be selected.
ROM code protect ROM code protect is assigned to address FFDB16.
Read/write the built-in QzROM by serial programmer is disabled by setting
“00” to ROM code protect.
Device structure CMOS silicon gate
Package 32-pin plastic molded LQFP (PLQP0032GB-A)
32-pin plastic molded SSOP (PLSP0032JB-A)
Operating temperature range −20 to 85 °C
Power source
voltage f(XIN) = 4 MHz 1.8 to 3.6 V
Rev.1.07 Mar 19, 2009 Page 4 of 60
REJ03B0140-0107
7545 Group
Table 2 Performance overview (2)
Parameter Function
Power dissipation At CPU active Typ. 0.6 mA (f(X
IN
)=4 MHz, Vcc=3.0 V, output transistors “off” )
At WIT instruction executed Typ. 0.3 mA (f(X
IN
)=4 MHz, Vcc=3.0 V, output transistors “off” , in WIT state,
function except timer 1 disabled)
At STP instruction executed Typ. 0.1 µA (Ta = 25 °C, VCC ≥ VDDR ≥ VCC−0.6 V, output transistors “off”, in
STP state, all oscillation stopped)
During reset by voltage drop
detection circuit Typ. 0.1 µA (Ta = 25 °C, VDDR = 1.1 V, 1.8 V ≥ VCC ≥ 0V)
Rev.1.07 Mar 19, 2009 Page 5 of 60
REJ03B0140-0107
7545 Group
Fig. 4 Functional block diagram (PLQP0032GB-A package)
P2(8)
13129
323028
P0(8)
2726252423222120
R A MR O M
A
X
Y
S
PC
L
PC
H
PS
C P U
V
SS
11
V
CC
8
0
P3(8)
32
0
P4(1)
4
Timer 1(8)
Reset
Reset
Reset
I/O port P3I/O port P0
FUNCTIONAL BLOCK DIAGRAM
(Package: PLQP0032GB-A)
Watchdog timer
Carrier wave
generating
circuit
Prescaler 1 (8)
Voltage drop
detection circuit
Power-on reset circuit
I/O port P2
I/O port P4
171513
161412
1918
INT
0
INT
1
Key-on wakeup
Prescaler 2 (8)
Prescaler 3 (8)
V
DDR
5
Clock output
X
OUT
10
9
Clock input
X
IN
Clock generating circuit
RESET
6
Reset I/O
7
CNV
SS
Rev.1.07 Mar 19, 2009 Page 6 of 60
REJ03B0140-0107
7545 Group
Fig. 5 Functional block diagram (PLSP0032JB-A package)
P2(8)
531
4232
P0(8)
3130292827262523
R A MR O M
A
X
Y
S
PC
L
PC
H
PS
C P U
V
SS
15
V
CC
12
0
P3(8)
76
0
P4(1)
8
Timer 1(8)
Reset
Reset
Reset
I/O port P3I/O port P0
FUNCTIONAL BLOCK DIAGRAM
(Package: PLSP0032JB-A)
Watchdog timer
Carrier wave
generating
circuit
Prescaler 1 (8)
Voltage drop
detection circuit
Power-on reset circuit
I/O port P2
I/O port P4
211917
201816
2422
INT
0
INT
1
Key-on wakeup
Prescaler 2 (8)
Prescaler 3 (8)
V
DDR
10
Clock output
X
OUT
14
13
Clock input
X
IN
Clock generating circuit
RESET
9
Reset I/O
11
CNV
SS
Rev.1.07 Mar 19, 2009 Page 7 of 60
REJ03B0140-0107
7545 Group
PIN DESCRIPTION
Table 3 Pin description
Pin Name Function Function expect a port function
VCC, VSS Power source • Apply voltage of 1.8 to 3.6V to VCC, and 0 V to VSS.
VDDR Power source • P ower source pin only for RAM2. When this pin is used, connect an approximately 0.1 µF
bypass capacitor across the VSS line and the VDDR line. When not used, connect it to VSS.
CNVSS CNVSS • Chip operating mode control pin, which is always connected to Vss.
RESET Reset I/O • An N-channel open-drain I/O pin for a system reset. This pin has a pull-up transistor. When the
watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the
system to be reset, the RESET pin outputs "L" level.
XIN Clock input • Input and output pins for main clock generating circuit
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins.
XOUT Clock output
P00/KEY0−
P07/KEY7I/O port P0 • 8-bit I/O port.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Whether the pull-up function/key-on wakeup function
is to be used or not can be determined by program.
• Key-input (key-on wake up interrupt
input) pins
P10, P11I/O port P1 • 2-bit I/O port having almost the same function as P0.
• CMOS compatible input level
• The output structure can be switched to N-channel
open-drain or CMOS by software.
Note: RLSS-only pins
P20(LED0)/INT0
P21(LED1)/INT1
P22(LED2)−
P27(LED7)
I/O port P2 • 8-bit I/O port having almost the same function as P0.
• CMOS compatible input level
• The output structure can be switched to N-channel
open-drain or CMOS by software.
• P 2 can output a large current for driving LED.
• I nterrupt input pins
P30−P37I/O port P3 • 8-bit I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
P40(LED8),
P41(LED9)I/O port P4 • 2-bit I/O port having almost the same function as P0.
• CMOS compatible input level
• CMOS 3-state output structure
Note: RLSS-only pins
P42/CARR • 1-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• Carrier wave output pin for remote-
control transmit
Rev.1.07 Mar 19, 2009 Page 8 of 60
REJ03B0140-0107
7545 Group
GROUP EXPANSION
We are planning to expand the 7545 group as follow:
Memory Type
Support for QzROM version and emulator MCU.
Memory Size
• ROM size ... ............. ......................... ............ 4 K to 60 K bytes
• RAM size .......................................................... 256, 512 bytes
Packages
• PLQP0032GB-A ...0.8 mm-pitch 32-pin plastic molded LQFP
• PLSP0032JB-A ... 0.65 mm-pitch 32-pin plastic molded SSOP
• 42S1M ...........................42-pin shrink ceramic PIGGY BACK
Fig. 6 Memory expansion plan
Currently supported products are listed below.
256 512
32K
24K
16K
0
M37545G8
RAM size
(bytes)
ROM size
(bytes)
M37545G6
M37545G4
8K
60K
48K
4K
M37545G2
M37545G1
M37545GF
M37545GC
Table 4 List of supported products
Part number ROM size (bytes)
ROM size for User ( ) RAM size
(bytes) Package Remarks
M37545G1KP 4096 (3966) 256 PLSP0032JB-A QzROM version (blank)
M37545G2KP 8192 (8062) PLSP0032JB-A QzROM version (blank)
M37545G4-XXXGP 16384
(16254)
512
PLQP0032GB-A QzROM version
M37545G4GP QzROM version (blank)
M37545G4KP PLSP0032JB-A QzROM version (blank)
M37545G6-XXXGP 24576
(24446) PLQP0032GB-A QzROM version
M37545G6GP QzROM version (blank)
M37545G6KP PLSP0032JB-A QzROM version (blank)
M37545G8-XXXGP 32768
(32638) PLQP0032GB-A QzROM version
M37545G8GP QzROM version (blank)
M37545G8KP PLSP0032JB-A QzROM version (blank)
M37545GC-XXXGP 49152
(49022) PLQP0032GB-A QzROM version
M37545GCGP QzROM version (blank)
M37545GF-XXXGP 61440
(61310) PLQP0032GB-A QzROM version
M37545GFGP QzROM version (blank)
M37545RLSS 42S1M Emulator MCU
Rev.1.07 Mar 19, 2009 Page 9 of 60
REJ03B0140-0107
7545 Group
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S
MANUAL for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
This instruction cannot be used while CPU operates by an on-
chip oscillator.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index register X (X), Index register Y (Y)]
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is
added to the contents of register X or register Y and specifies the
real address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
[Stack pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack
address are determined by the Stack Page Selection Bit. If the
Stack Page Selection Bit is “0”, then the RAM in the zero page is
used as the stack area. If the S tac k Page Sel ectio n Bit is “1”, the n
RAM in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some
microcompu ter types have no Stack Page Select ion Bit and the
upper eight bits of the stack address are fixed. The operations of
pushing register contents onto the stack and popping them from
the stack are shown in Figure 8.
[Program counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 7 740 Family CPU register structure
b7 b0
X
b7 b0
S
b7 b0
Y
b7 b0
PCL
Processor Status Register (PS)
Carry Flag
b7 b0
b7 b0
A
b15 PCH
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Program Counter
Stack Pointer
Index Register Y
Index Register X
Accumulator
CZIDBTVN
Rev.1.07 Mar 19, 2009 Page 10 of 60
REJ03B0140-0107
7545 Group
Fig. 8 Register push and pop at interrupt generation and subrouti ne call
Execute JSR
On-going Routine
M (S) (PCH)
M (S) (PCL)
Execute RTS
(PCL) M (S)
(S) (S + 1)
(S) (S + 1)
(PCH) M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack M (S) (PS)
Execute RTI
(PS) M (S)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S) (PCH)
(S) (S - 1)
M (S) (PCL)
(PCL) M (S)
(PCH) M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
(S) (S - 1)
(S) (S - 1)
(S) (S + 1)
(S) (S + 1)
(S) (S + 1)
(S) (S - 1)
(S) (S - 1)
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack Pop instruction from stack
Accumulator PHA PLA
Processor status register PHP PLP
Rev.1.07 Mar 19, 2009 Page 11 of 60
REJ03B0140-0107
7545 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an
arithmetic operation. Branch operations can be performed by
testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or
the Negative (N) flag. In decimal mode, the Z, V, N flags are not
valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate
instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK i nstruction. Interrupts are disabled
when the I flag is “1”.
When an interrupt occurs, thi s flag is aut omati cally set to “1”
to prevent other interrupts f rom interfering until the current
interrupt is serviced.
Bit 3: Decimal mode flag (D)
The D flag de termines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it
is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can be used for decimal
arithmetic.
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”. The saved processor status is the only place where the
break flag is ever set.
Bit 5: Index X mode flag (T)
When the T flag is “0” , arithmetic operations are performed
between accumulator and m emory. When the T flag is “ 1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to -
128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instructi on is store d
in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithm etic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory locati on operated on by the
BIT instruction is stored in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction SEC −SEI SED −SET −−
Clear instruction CLC −CLI CLD −CLT CLV −
Rev.1.07 Mar 19, 2009 Page 12 of 60
REJ03B0140-0107
7545 Group
[CPU mode register (CPUM)]
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
For this product, the clock speed of CPU is always f(XIN)/4.
Fig. 9 Structure of CPU mode register
Processor mode bits (Note)
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1 Not available
b7 b0
Note : The bit can be rewritten only once after releasing reset.
After rewriting, it is disabled to write any data to this bit.
However, by reset the bit is initialized and can be rewritten, again.
It is not disabled to write any data to this bit for emulator MCU M37545RLSS.
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Stack page selection bit
0 : 0 page
1 : 1 page
Clock division ratio selection bits
b7 b6
0 0 : Not available
0 1 : Not available
1 0 : f(f) = f(XIN)/4
1 1 : Not available
Not used (returns 0 when read)
Rev.1.07 Mar 19, 2009 Page 13 of 60
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7545 Group
MEMORY
Specia l Func ti on Register (SFR) Area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts. RAM consists of RAM1 and RAM2. The
power source for RAM1 is supplied from VCC pin. The power
source for RAM2 is supplied from VDDR pin.
Note: When the VDDR pin is used, connect an approximately 0.1
µF bypass capacitor across the VSS line and the VDDR line.
When not used, connect it to VSS.
ROM
The first 128 bytes and the last 2 bytes of ROM ar e reserved for
device testing and the rest is a user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function
registers (SFR) are allocated to this are a.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Specia l Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be used
to specify memory addresses in the special page area. Access to
this area with only 2 bytes is possible in the special page
addressing mode.
Function Set ROM Area
[Renesas shipment te st area]
Figure 10 shows the Assignment of Function set ROM area.
The random data are set to the Renesas shipment test areas
(addresses FFD416 to address FFD916).
Do not rewrite the data of these areas.
When the checksum is included in the user program, avoid
assigning it to these are as.
[Function set ROM data] FSROM
Function set ROM data (address FFDA16) is used to set modes of
peripheral functions. By setting this area, the operation mode of
each peripheral function are set after system is released from
reset.
Refer to the descriptions of peripheral functions for the details of
operation of peripheral functions.
• Watchdog timer
• Low voltage detection circuit
This mode setting of peripheral functions cannot be changed by
program after system is released from reset.
ROM Code Protect Address (address FFDB16)
Address FFDB16, which is the reserved ROM area of QzROM, is
the ROM code protect address. “0016” is written into this a ddress
when selecting the prote ct bit write by using a serial programmer
or selecting protect enabled for writing shipment by Renesas
Technology corp.. When “0016” is set to the ROM code protect
address, the protect function is enabled, so that reading or writing
from/to QzROM is disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected
by selecting the protect bit write at ROM writing with a serial
programmer.
As for the QzROM product shipped after writing, “00 16” (protect
enabled) or “FF16” (protect disabled) is writte n into the ROM
code protect address when Renesas Technology corp. performs
writing.
The writing of “0016” or “FF16” can be selected as the ROM
option setup (referred to as “Mask option setup” in MM) when
ordering.
<Notes>
1. Because the contents of RAM are indefinite at reset, set ini-
tial values before using.
2. Do not access to the reserved area.
3. Random data is written into the Renesas shipment test area
and the reserved ROM area. Do no t rewrite the data in these
areas. Data of these area may be changed without notice.
Accordingly, do not includ e these areas into programs such
as checksum of all ROM areas.
4. The QzROM values in function set ROM data set the oper-
ating modes of the var ious peripheral functions after an
MCU reset is released. Do not fail to set the value for the
selected function. Bits designated with a fixed value of 1 or
0 must be set to the designated value.
5. Emulator MCU: As for M37545RLSS, set “010000XX2” to
Function set ROM data (address FFDA16). Also, set “FF16”
to ROM code protect (address FFDB16).
Rev.1.07 Mar 19, 2009 Page 14 of 60
REJ03B0140-0107
7545 Group
Fig. 10 Memory map diagram
000016
004016
044016
FF0016
FFDC16
FFFE16
FFFF16
XXXX16
YYYY16
ZZZZ16
RAM1
ROM
16384 C00016 C08016
240 012F16
FFD416
WWWW16
16 01CF16 RAM2
24576 A00016 A08016
32768 800016 808016
Function set ROM area
Address
FFD416
FFD516
FFD616
Renesas shipment test area
Reserved ROM area
Reserved ROM area
FFD716
FFD816
FFD916
Reserved ROM area
Reserved ROM area
Reserved ROM area
FFDA16
FFDB16
Function set ROM data
ROM code protect
RAM 2 area
RAM capacit y
(bytes) address
XXXX16
RAM 1 area
RAM capacit y
(bytes) address
WWWW16
ROM area
ROM capacity
(bytes) address
YYYY16 address
ZZZZ16
Reserved area
SFR area
Disable
Interrupt vector area
Reserved ROM area
(128 bytes)
Reserved ROM area
Function set ROM area
384 01BF16
128 023F16
49152 400016 408016
61440 100016 108016
4096 F00016 F08016
8192 E00016 E08016
01C016
ROM
Rev.1.07 Mar 19, 2009 Page 15 of 60
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7545 Group
Fig. 11 Memory map of special function regist er (SFR)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Pull-up control regist er (PULL)
Key-on wakeup pin selection regist er (KEYSEL)
Port output mode s ele c tio n regi st er (PM OD)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer count source set register (TCSS)
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer 1,2,3 control register (TC123)
Timer 2 primary (T2P)
Reserved
Reserved
Reserved
MISRG
Watchdog timer co nt rol regi s ter (W DTCON)
Interrupt edge sele c ti on regi s ter (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Carrier wave control register (CARCNT)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note : Do not access to the SFR area including nothing.
Port P4 (P4)
Port P4 direction register (P4D)
Key-on wakeup edge selection register (KEYEDGE)
Reserved
Reserved
Timer 2 secondary (T2S)
Timer 3 (T3)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev.1.07 Mar 19, 2009 Page 16 of 60
REJ03B0140-0107
7545 Group
Fig. 12 Structure of Function set ROM area
b7 Function set ROM data
(FSROM: address FFDA16)
b0
Watchdog timer disable bit
0: Watchdog timer enabled
1: Watchdog timer disabled
STP instruction function selection bit
0: Inte rnal reset occurs at the STP
instruction execution
1: System enters into the stop mode
at the STP instruction execution
MCU pa ck ag e set bit
0: GP package version
1: KP package version
Set 0 to this bit.
Voltage drop detection circuit valid bit
0: Voltage drop detection circuit invalid
1: Voltage drop detection circuit valid
Set 0 to this bit.
Setting the number of pins
0: set 0 to this bit in G P or K P
package version
1: set 1 to this bit in the emulator
MCU
Set 0 to this bit.
Rev.1.07 Mar 19, 2009 Page 17 of 60
REJ03B0140-0107
7545 Group
I/O PORTS
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register
corresponds to one pin, and each pin can be set to be input or
output.
When “1” is set to the bit corresponding to a pin, this pin
becomes an output port. When “0” is set to the bit, the pin
becomes an input port.
When data is read from a pin set to output, not the value of the
pin itself but the value of port latch is read. Pins set to input are
floating, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to
and the pin remains floating.
[Pull-up control register] Pull
By setting the pull-up control register (address 001616), port P0
can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-
up control.
[Port output mode selectio n re g is te r] PMO D
By setting the port output mode selection register (address
001716), CMOS output or N-channel open-drain can be selected
for ports P1, P2, P3 by program.
Fig. 13 Structure of pull-up control register
Fig. 14 Structure of port output mode select ion register
Port P04
Port P01
Port P00
0: Pull-up transistor off
1: Pull-up transistor on
b7 b0
Port P02
Port P03
Port P05
Port P06
Port P07
Pull-up control register
(PULL: address 001616, initial value: 0016)
Table 7 I/O port function table
Pin Name
Input/Output
I/O format Non-port function Related SFRs
Diagram No.
P00−P07Port P0 I/O individual
bits • CMOS compatible input
level
• CMOS 3-state output
Key input interrupt Pull-up control register
Key-on wakeup pin selection register
Key-on wakeup edge selection regis-
ter
(1)
P10−P11Port P1 •CMOS compatible input
level
•CMOS 3-state output or
N-channel open drain
RLSS-only pin Port output mode selection register (2)
P20/INT0
P21/INT1Port P2 External interrupt input Interrupt edge selection register
Port output mode selection register (3)
P22−P27Port output mode selection register (2)
P30−P37Port P3 Port output mode selection register (2)
P40, P41Port P4 • CMOS compatible input
level
• CMOS 3-state output
RLSS-only pin (4)
P42/CARR Carrier wave output for
remote-control transmitter Carrier wave control register (5)
Port P34−P37
Port P20−P23
Port P10−P11
0: CMOS output
1: N-channel open-drain
b7 b0
Port P24−P27
Port P30−P33
Disable (returns “0” when read)
Port output mode selection register
(PMOD: address 001716, initial value: 00 16)
Rev.1.07 Mar 19, 2009 Page 18 of 60
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7545 Group
Fig. 15 Block diagram of ports (1)
(5) Por t P42
(4) Ports P40, P41
(1) Ports P00-P07
Pull-up control
To key input interrupt
generating circuit
(2) Ports P10-P11, P22-P27, P30-P37
Key-on wakeup pin selection
(3) Ports P20, P21
Port output mode switch
To INT0, INT1 interrupt circuit
Port output mode switch
Direction
register
Data bus Port latch
Carrier wave output
Carrier wave output valid bit
Direction
register
Port latch
Direction
register
Port latch
Data bus Data bus
Direction
register
Port latch
Data bus
Direction
register
Port latch
Data bus
Rev.1.07 Mar 19, 2009 Page 19 of 60
REJ03B0140-0107
7545 Group
Termination of Unused Pins
1. Termination of common pins
I/O ports: Select an input port or an output port and follow
each processing method.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply
current may increase .
Especially, when expecting low consumption
current (at STP or WIT instruction execution etc.),
pull-up or pull-down input ports to prevent
through current (built-in resistor can be used).
We recommend processing unused pins through a
resistor which can secure IOH(avg) or IOL(avg).
Table 8 Termination of unused pins
Pin Termination 1 (recommend) Termination 2 (recommend)
P00/KEY0−P07/KEY7I/O port When selecting key-on wakeup function, perform termination of input port.
P10−P11(RLSS-only pin) When selecting N-channel open-drain for output structure, open.
P20 (LED0)/INT0When selecting N-channel open-drain for output structure, connect to VSS
through a resistor. Or set its port latch to “0” and open.
P21 (LED1)/INT1When selecting N-channel open-drain for output structure, connect to VSS
through a resistor. Or set its port latch to “0” and open.
P22 (LED2)−P27 (LED7) When selecting N-channel open-drain for output structure, open.
P30−P37When selecting N-channel open-drain for output structure, open.
P40 (LED8) (RLSS-only pin) −
P41 (LED9) (RLSS-only pin) −
P42/CARR When selecting CARR output function, perform termination of output port.
VDDR Connect to VSS.−
Rev.1.07 Mar 19, 2009 Page 20 of 60
REJ03B0140-0107
7545 Group
Interrupts
The 7545 group interrupts are vector interrupts with a fixed
priority scheme, and generated by 7 sources 3 external, 3
internal, and 1 software.
The interrupt sources, vector addresses(1), and interrupt priority
are shown in Table 9.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 16 shows an interrupt control diagram.
An interrupt requests is accepted when all of the following
conditions are satisfied:
• Interrupt disable flag.. .. .............. .............. “0”
• Interrupt request bit.. .. ................ .............. “1”
• Interrupt enable bit... .......................... ......“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
NOTES:
1. Vector addressed contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Table 9 Interrupt vector address and priority
Interrupt source
Priority
Vector addresses(1) Interrupt request generating conditions Remarks
High-
order Low-
order
Reset (2) 1FFFD16 FFFC16 At reset input Non-maskable
Key-on wakeup 2 FFFB16 FFFA16 AND operation of input logic level of port P0 (input)
External interrupt
INT03 FFF916 FFF816 At detection of either rising or falling edge of INT0
input
External interrupt
(active edge select able)
INT14 FFF716 FFF616 At detection of either rising or falling edge of INT1
input
External interrupt
(active edge select able)
Timer 2 5 FFF516 FFF416 At timer 2 underflow
Timer 3 6 FFF316 FFF216 At timer 3 underflow
Timer 1 7 FFF116 FFF016 At timer 1 underflow STP release timer underflow
BRK instruction 8 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt
Rev.1.07 Mar 19, 2009 Page 21 of 60
REJ03B0140-0107
7545 Group
Fig. 16 Interrupt control diagram
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the S ET instruction and set to “0” with th e CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushe d onto the stack while the
interrupt disable flag remains set to “0”. Subsequently, this flag
is automatically set to “1” and multipl e interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status regist er are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remains “1 ” until the reque st
is accepted. When the request is accepted, this bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt en able bit is set to “ 1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
• Interrupt Edge Selection
The valid edge of external interrupt INT0 and INT1 can be
selected by the interrupt edge selection register(address003A16),
respectively.
• Key-on W a ke up Pin Selection
By setting the key-on wakeup pin selection register (address
001816), the valid or invalid of key-on wakeup for each pin can
be selected.
• Key-on Wakeup Edge Selection
By setting the key-on wakeup edge selection register (address
001916), the trigger edge of key-on wakeup for each pin can be
selected.
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Rev.1.07 Mar 19, 2009 Page 22 of 60
REJ03B0140-0107
7545 Group
Fig. 17 Structure of interrupt-related registers
b7 Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Timer 2 interrupt request bit
Key-on wakeup interrupt request bit
Timer 1 interrupt request bi t
Timer 3 interrupt request bi t
INT1 interrupt request bit
INT0 interrupt request bit
Disable (returns “0” when read)
(Do not write “1” to these bits)
b0
b7 b0 Interrupt edge selection register
INT0 interrupt edge selection bit
(INTEDGE : address 003A16, initial value : 0016)
Disable (returns “0” when read)
1 : Rising edge active
0 : Falling edge active
INT1 interrupt edge selection bit
1 : Rising edge active
0 : Falling edge active
Port P04
Port P01
Port P00
0: Key-on wakeup invalid
1: Key-on wakeup valid
b7 b0
Port P02
Port P03
Port P05
Port P06
Port P07
Key-on wakeup pin selection register
(KEYSEL: address 001816, initial value: 0016)
b7 b0
Port P04
Port P01
Port P00
0: Falling edge
1: Rising edge
Port P02
Port P03
Port P05
Port P06
Port P07
Key-on wakeup edge selection register
(KEYEDGE: address 001916, initial value: 0016)
Timer 2 interrupt enable b it
b7 Interrupt control regist er 1
(ICON1 : address 003E16, init ial value : 0016)
Key-on wakeup int errupt enable bit
Timer 1 interrupt enable bit
Timer 3 interrupt enable bit
INT1 interrupt enable bit
INT0 interrupt enable bit
Disable (returns “0” when read)
(Do not write “1” to these bits)
b0
Rev.1.07 Mar 19, 2009 Page 23 of 60
REJ03B0140-0107
7545 Group
• Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source
(external interrupt signal input, timer underflow, etc.) and
the corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance
conditions (interrupt request bit, interrupt enable bit, and
interrupt disable flag) and interrupt priority levels for
accepting interrupt requests. When two or more interrup t
requests are generated simultaneously, the highest priority
interrupt is accepted. The value of interrupt request bi t for
an unaccepted interrupt remains the same and acceptance is
determined at th e next in terrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted in te rrupt request is processed.
Figure 18 shows the time up to execution in the interrupt
processing routine, and Figure 19 shows the interrupt sequence.
Figure 20 shows the timing of interrupt request generation,
interrupt request bit, and interrupt reques t acceptance.
• Interrupt Handling Execution
When interrupt handling is executed, the following operations
are performed automatically.
(1) Once the currently executing instruction is completed, an
interrupt request is accept ed.
(2) The contents of the program counters and the processor
status register at this point are pushed onto the stack area in
order from 1 to 3.
1. High-order bits of program counter (PCH)
2. Low-order bits of program counter (PCL)
3. Processor status register (PS)
(3) Concurrently with the push operation, the jump address of
the corresponding interrupt (the start address of the interrupt
processing routine) is transferred from the interrupt vector to
the program counter.
(4) The interrupt request bit for the corresponding interrupt is
set to “0”. Also, the interrupt disable flag is se t to “1” and
multiple interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the
registers pushed onto the stack area are popped off in the
order from 3 to 1. Then, the routine that was before running
interrupt processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each
interrupt to execute the interrupt processing routine.
Fig. 18 Time up to execution in interrupt routine
7 cycles
Interrupt request
generated Interrupt request
acceptance Interrupt routine
starts
Interrupt sequence
*
0 to 16 cycles
7 to 23 cycles
* When executing DIV instruction
Main routine Stack push and
Vector fetch Interrupt handling
routine
Rev.1.07 Mar 19, 2009 Page 24 of 60
REJ03B0140-0107
7545 Group
Fig. 19 Interrupt seq uence
Fig. 20 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
<Notes>
When setting the followings, the interrupt request bit may be set
to “1” .
<When setting the external interrupt active edge>
•INT
0 interrupt edge selection bit (bit 0 of Interrupt edge
selection register (address 3A16))
•INT
1 interrupt edge selection bit (bit 1 of Interrupt edge
selection register)
• Key-on wakeup edge selection register (address 1916)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
φ
SYNC
RD
WR
Push onto stack
Vector fetch
Address bus
Data bus
Execute interrupt
routine
PC S,SPS S-1,SPS S-2,SPS BLBHAL,AH
Not used PCHPCLPS ALAH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
SPS : “0016” or “0116”
([SPS] is a page selected by the stack page selection bit of CPU mod e register.)
T1
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
IR1T2
SYNC
IR2T3
12
Internal clock φ
Instruction cycle Push onto stack
Vector fetch Instruction cycle
Rev.1.07 Mar 19, 2009 Page 25 of 60
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7545 Group
Key Input Interru pt (Key-on Wake-Up)
A key-on wake-up interrupt request is generated by applying the
level set by KEYEDGE to any pin of port P0 that has been set to
input mode and KEYSEL has been valid. In other words, it is
generated when the AND of input level goes from “1” to “0” or
from “0” to “1”.
An example of using a key input interrupt is shown in Figure 21,
where an interrupt request is generated by pressing one of the
keys provided as an active-low key matrix which uses ports P00
to P03 as input ports.
Fig. 21 Connection example when using key input interru pt and port P0 block diagram
Port PXx
“L” level output
PULL register
bit 7 = “0”
Port P07
latch
Port P07
Direction regist er = "1”
***
P07 output
Key input interrupt request
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS output buffer
PULL register
bit 6 = "0”
Port P06
latch
Port P06
Direction regist er = "1”
***
P06 output
PULL register
bit 5 = "0”
Port P05
latch
Port P05
Direction regist er = "1”
***
P05 output
PULL register
bit 4 = "0”
Port P04
latch
Port P04
Direction regist er = "1”
***
P04 output
PULL register
bit 3 = "1”
Port P03
latch
Port P03
Direction regist er = "0”
***
P03 input
PULL register
bit 2 = "1”
Port P02
latch
Port P02
Direction regist er = "0”
***
P02 input
PULL register
bit 1 = "1”
Port P01
latch
Port P01
Direction regist er = "0”
***
P01 input
PULL register
bit 0 = "1”
Port P00
latch
Port P00
Direction regist er = "0”
***
P00 input
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Port P00 key-on wa keup
selection register
Bit 0
Port P01 key-on wa keup
selection register
Bit 1
Port P02 key-on wa keup
selection register
Bit 2
Port P03 key-on wa keup
selection register
Bit 3
Port P04 key-on wa keup
selection register
Bit 4
Port P05 key-on wa keup
selection register
Bit 5
Port P06 key-on wa keup
selection register
Bit 6
Port P07 key-on wa keup
selection register
Bit 7
Rev.1.07 Mar 19, 2009 Page 26 of 60
REJ03B0140-0107
7545 Group
Timers
The 7545 Group has 3 timers: timer 1, timer 2 and timer 3.
The division ratio of every timer and prescaler is 1/(n+1)
provided that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”,
an underflow occurs at the next count pulse, and the
corresponding timer latch is reloaded into the timer. When a
timer underflows, the interrupt request bit corresponding to each
timer is set to “1”.
1. Timer 1
T imer 1 is an 8-bit timer and counts the prescaler 1 output.
When Timer 1 underflows, the timer 1 interrupt request bit is set
to “1”.
Prescaler 1 is an 8-bit prescaler and counts the clock which is
f(XIN) divided by 16.
Prescaler 1 and T imer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when
Timer 1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is
written to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading fro m Prescaler 1 (PRE1) and Timer 1 (T1) is
executed, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the clock which is f(XIN) divided by 16. Each
time the count clock is input, the contents of Prescaler 1 is
decremented by 1. When the contents of Prescaler 1 reach
“0016”, an underflow occurs at the n ext count clock, and the
prescaler 1 latch is reloaded into Prescaler 1 and count continues.
The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
Timer 1 counts the underflow signal of Prescaler 1. The contents
of Timer 1 is decremented by 1 each time the count clock is
input.
When the contents of Timer 1 reach “0016”, an underflow occurs
at the next count clock, and the ti mer 1 latch is reloaded into
Timer 1 and count contin ues. The division ratio of Timer 1 is
1/(m+1) provided that the value of Timer 1 is m.
T imer 1 is stopped by setting “1” to the timer 1 count stop bit.
2. Timer 2
Timer 2 is an 8-bit timer and counts the clock selected by the
timer 2 count source selection bit. When Timer 2 underflows, the
timer 2 interrupt request bit is set to “1”.
Timer 2 has two timer latches (primary latch and secondary
latch) to retain the reloa d value .
The value written to timer 2 primary (T2P) while timer 2 is
stopped is transferred to the timer 2 primary latch and the
counter.
The value written to timer 2 secondary (T2S) while timer 2 is
stopped is transferred only to timer 2 secondary latch.
After the count of timer 2 starts, the values written to timer 2
primary (T2P) and timer 2 secondary (T2S) are transferred only
to each latch. The values are not transferred to the counter at
write.
When each timer underflows, the values of timer 2 primary latch
and the timer 2 secondary latch are alternately transferred to the
counter. (Since a count value of a timer is retained, the written
value becomes the count value of the timer after the next
underflow.)
When timer 2 primary (T2P) is read, the count value of the timer
is read. When timer 2 secondary (T2S) is read, a set value of
timer 2 secondary is read. (Read the time r 2 primary to read the
count value even during the count period of timer 2 secondary.)
When the timer 2 primary is read, the count value of timer 2 is
read since the count value of the timer 2 is retained until writing
to timer 2 primary (T2P) is performed after timer 2 is stopped.
Timer 2 always operates in the timer mode.
Timer 2 counts the clock selected by the timer 2 count source
selection bit. The contents of Timer 2 is decremented by 1 each
time the count clock is input. When the contents of Timer 2 reach
“0016”, an underflow occurs at the next count clock, and the
timer 2 pr imary latch or t imer 2 secondary lat ch is alternate ly
reloaded into Timer 2 and count continues.
Rev.1.07 Mar 19, 2009 Page 27 of 60
REJ03B0140-0107
7545 Group
3. Timer 3
Timer 3 is an 8-bit timer and counts the clock selected by the
timer 3 count source selection bit. When Timer 3 underflows, the
timer 3 interrupt request bit is set to “1”.
Timer 3 has a timer latch to retain the reload value.
The value written to timer 3 (T3) while timer 3 is stopped is
transferred to the timer latch and the counter.
After the count of timer 3 (T3) starts, the value written to timer 3
is transferred only to the timer 3 latch. The value is not
transferred to the counter at write.
When timer underflows, the value of timer 3 latch is transferred
to the counter. (Since a count value of a timer is retained, the
written value becomes the count value of the timer after the next
underflow.)
When timer 3 (T3) is read, the count value of the timer is read.
When the timer 3 is read, the count value of timer 3 is read since
the count value of the timer 3 is retained until writing to timer 3
(T3) is performed after timer 3 is stopped.
Timer 3 always operates in the timer mode.
Timer 3 counts the clock selected by the timer 3 count source
selection bit. The contents of Timer 3 is decremented by 1 each
time the count clock is input.
The division ratio of Timer 3 is 1/(n+1) provided that the value
of Timer 3 is n.
T imer 3 is stopped by setting “1” to the timer 3 count stop bit.
Timer 2 and timer 3 are also used for the control timer of the
carrier wave control circuit.
Fig. 22 Structure of timer count source set regist er
Fig. 23 Timer 1, 2, 3 control register
b7 b0 Timer count source set register
(TCSS : address 002A16, initial value: 0016)
Timer 2 count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN)/8
1 1 : f(XIN)/1
Disable (return “0” when read)
Timer 3 count source selection bits
b3 b2
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN)/8
1 1 : Carrier wave output (CARRY)
b7 Timer 1, 2, 3 control register
(TC123 : address 002B16, initial value: 0616)
Timer 1 count stop bit
0: Count start
1: Count stop
Timer 2 count stop bit
0: Count start
1: Count stop
Timer 3 count stop bit
0: Count start
1: Count stop
Disable (return “0” when read)
b0
Rev.1.07 Mar 19, 2009 Page 28 of 60
REJ03B0140-0107
7545 Group
.
Fig. 24 Block diagram of timer 1, timer 2, timer 3 and carrier wave generating circuit
1/16
1/2
1/8
1/1
Timer 2 secondary latch (8)
Timer 2(8)
Wave expansion function
Reload control
circuit
Reload control
circuit
Timer 2 primary latch (8)
Timer 2 interrupt reque
st
Timer 3 interrupt reques
t
Timer 3 count value reload bit
P42/CARR
"00"
"0"
"1"
"0"
"0"
"1"
"01"
"10"
"11"
Timer 1(8)
Prescaler 1 (8)
Timer 3 latch (8)
Carrier wave output valid bit
Software carrier wave output bit
Carrier wave output level bit
Timer 3(8)
Timer 1 latch (8)Prescaler 1 latch (8)
Timer 1 interrupt reque
st
f(XIN)/16
T
imer 2 count source selection bits
1/16
1/2
1/8
"00"
"01"
"10"
"11"
Timer 3 count source selection bits
Toggle flip flop
Toggle flip flop Timer 2 count value reload bit
T
R
Q
T
R
Q
Carrier wave "H" interval expansion bit
Trigger stop
Carrier wave output trigger bit
Data bus
Data bus
Data bus
"1"
"0"
Carrier wave auto-output control bit
"1"
Rev.1.07 Mar 19, 2009 Page 29 of 60
REJ03B0140-0107
7545 Group
4. Carrier wave generating circuit
The carrier wave generating circuit is used to generate the control
wave of the remote control by using timer 2 and timer 3 (Figure
26).
In order to use the carrier wave generating function by timer 2,
set “1” to the carrier wave output valid bit (bit 1 of the carrier
wave control register (address 2716)).
Carrier wave “H” duration is set to the timer 2 primary, and
carrier wave “L” duration is set to the ti mer 2 secondary. Timer 2
counts a primary latch and a secondary latch alternately, and
controls carrier wave “H” duration and the “L” duration (Figure
27).
The “H” duration of the carrier waveform can be expanded for a
half clock of timer 2 count source by setting “1” to the carrier
wave “H” duration bit (bit 0) (Figure 28).
Therefore, the frequency of the carrier wave can be set by the
resolution of 1/2 of the timer 2 count source.
For example, the carrier wave of the resolu tion of 125 ns (max.)
can be generated at f(XIN) = 4 MHz when f(XIN)/1 is selected for
the timer 2 count source.
In order to initialize the carrier waveform, write in the timer 2
primary after stopping the count of timer 2, and then, start the
count of timer 2. The output of the carrier waveform is started
from a primary period.
Output/stop of the carrier waveform can be controlled by
software or timer 3 (Figure 31 and Figure 32). The output o f the
carrier wave is started from the P42/CARR pin when “1” is set to
the software carrier wave output bit (bit 2), and the output of the
carrier wave is stopped when “0” is written.
The auto-output of the carrier wave using timer 3 can be
performed by setting “1” to the carrier wave auto-output control
bit (bit 3) (Figure 29). Each time timer 3 underflow occurs, the
trigger signal which is used to turn the output of the carrier wave
on/off is generated.
The trigger from timer 3 becomes valid by setting “1” to the
carrier wave output trigger bit (b it 4), and the output/stop of the
carrier wave from the P42/CARR pin is repeated each time timer
3 underflows. Timer 3 count continues without stopping though
the output/stop state of the carri er wave at that ti me is maintaine d
when “0” is written to the carrier wave auto-output control bit
(bit 3) while the output of the carrier wave by timer 3 is
controlled.
In order to initialize output/stop control of the carrier waveform,
write in the timer 3 after stopping the count of timer 3, and then,
start the count of time r 3. The output of the carrier waveform is
started from “waveform output valid period”.
5. 455 kHz carrier wave generatin g mo de
The 455 kHz carrier wave generating mode is used to generate
artificially the 455 kHz carrier wave by auto-control of the
setting value of the timer, or the waveform expansion mode.
If “1” (valid) is set to the 455 kHz carrier wave generating mode
bit (bit 5), the values of the timer latch and the carrier wave “H”
duration expansion bit (bit 0) are automatically set.
Then, the nine waveforms of 2.250 µs wavelength and the seven
waveforms of 2.125 µs wavelength are generated periodically as
shown in Figure 30.
The carrier wave of 455.516 kHz can be pseudo generated since
the average wavelength for one period becomes 2.195 µs.
In order to use 455 kHz carrier wave generating mode, use the 4
MHz oscillator and select f(XIN)/1 for the timer 2 count source.
Fig. 25 Carrier wave control register
b7 b0 Carrier wave control register
(CARCNT : address 002716, initial value: 0016)
Carrier wave “H” duration expansion bit
0: “H” duration expansion function invalid
1: “H” duration expansion function valid
Disable (return “0” when read)
Carrier wave output valid bit
0: Carrier wave generating function invalid
1: Carrier wave generating function valid
Software carrier wave output bit
0: Output invalid
1: Output valid
Carrier wave auto-output control bit
0: Auto-control by timer 3 invalid
1: Auto-control by timer 3 valid
Carrier wave output trigger bit
0: Carrier wave output trigger invalid
1: Carrier wave output trigger valid
455 kHz carrier wave generating mode bit
0: 455 kHz carrier wave generating mode
invalid
1: 455 kHz carrier wave generating mode
valid
Carrier wave output level bit
0: Positive waveform
1: Inverted waveform
Rev.1.07 Mar 19, 2009 Page 30 of 60
REJ03B0140-0107
7545 Group
Fig. 26 Operating waveform diagram of carrier wave generating circuit
Fig. 27 Control waveform diagram of carrier wave by timer 2
Fig. 28 Waveform diagram of carrier wave in “H” duration expansion mode
04
Carrier waveform control by timer 2
Timer 2 count source
Timer 2 interrupt
Timer 2 count value
Carrier waveform
Primary
Timer 3 count source
(carrier wave output
selected)
Timer 3 interrupt
Timer 3 count value
Carrier waveform
Count period
Secondary Secondary SecondaryPrimary Primary Primary
03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01
04 03 02 01 00
05 04 03 02 01 0005 04 03 02 01 0005 04 03 02 01 0005 04 03 02 01 0005 04 03 02 01 0005 05
P42/CARR pin output
The timing adjustment of the output waveform causes the gap between the timer count value and the output waveform,
and the output waveform changes in the reload cycle after the timer underflow.
Moreover, the timer interrupt occurs at the change point of the output waveform.
(The timing of the interrupt occurrence is behind a half cycle of the count source, compared with timer 1. )
Note:
Carrier waveform control by timer 3
The timing adjustment of the output waveform causes the gap between the timer count value and the output waveform,
and the output waveform changes in the reload cycle after the timer underflow.
Moreover, the timer interrupt occurs at the change point of the output waveform.
(The timing of the interrupt occurrence is behind a half cycle of the count source, compared with timer 1. )
Note:
04 03 02 01 00 05 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 0
1
T
imer 2 count value
Writing to timer 2 secondary
in this duration
Writing to timer 2 primary
in this duration
Count value of primary side is changed
Count value of secondary side is changed
Primary Secondary Secondary SecondaryPrimary Primary Primary
Timer 2 count source
Timer 2 interrupt
Carrier waveform
03 02 01 00 04 03 02 01 00 03 02 01 04
00 03 02 01 00
T
imer 2 count source
T
imer 2 interrupt
T
imer 2 count value
C
arrier waveform
Primary Secondary Primary
Expansion duration for half-clock
Carrier wave “H” duration expansion = invalid Carrier wave “H” duration expansion = valid
Secondary
Rev.1.07 Mar 19, 2009 Page 31 of 60
REJ03B0140-0107
7545 Group
Fig. 29 Control wave form diagram of CARR output by timer 3
Fig. 30 Waveform diagram in 455 kHz carrier wave gene rating mode
06 05 04 03 02 01 00 02 01 00 03
03 01 00 03 0202 0001 02 01 0003 02 01 00 03
03 01 00 03 02
02 00
01 02 0
1
03
P42/CARR pin output
Timer 3 count source
(carrier wave output selected)
Timer 3 interrupt
Timer 3 count value
Count period
Generating carrier waveform
or not is controlled by setting
carrier waveform output trigger bit.
C
arrier waveform output trigger bit
Writing to timer 3
in this duration Count value of next period
is changed
Successive carrier waveform
is not generated in this duration.
2.250 µs X 9 waveforms + 2.125 µs X 7 waveforms
2.125 µs waveform duration (7 waveforms)
35.125 µs (16 waveforms), Average waveform = 2.195 µs (Frequency = 455.516 kHz)
Waveform period in 455 kHz carrier waveform generating mode
Waveform length: 2.250 µs-waveform Waveform length: 2.125 µs-waveform
2.250 µs
5-clock 4-clock
2.125 µs
4.5-clock 4-clock
C
arrier waveform
Timer 2 count source
Carrier waveform
Timer 2 count source
Carrier waveform
Rev.1.07 Mar 19, 2009 Page 32 of 60
REJ03B0140-0107
7545 Group
Fig. 31 Setting of carrier wave aut o-cont rol by timer 3
Carrier waveform
(Timer 2 output)
Timer 3 count value
Timer 3 underflow
Carrier wave output trigger bit
P4
2
/CARR pin output
Output valid Output valid
Waveform output timing of remote-control waveform by carrier waveform output trigger bit
03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 0004 04 04 04 04 04 04
0XX0000X
b7 b0
12
11
0000011X
b7 b0
10
0XX0101X
b7 b0
9
000011XX
b7 b0
6
0000000X
b7 b0
7
0XXX101X
b7 b0
8
0000011X
b7 b0
1
0000XXXX
b7 b0
2
0XXX101X
b7 b0
3
XXXXXXXX
b7 b0
XXXXXXXX
b7 b0
4
XXXXXXXX
b7 b0
5
Output invalid Trigger invalid
(Successive output invalid duration) Trigger invalid (Successive output valid duration)
Start (initial state after reset)
Timer 1, 2, 3 control register TC123 (2B16)
Set “1” to bit 1 and bit 2 to stop counting of timer 2 and timer 3.
Timer count source set register TCSS (2A16)
X: Set it to “0” or “1” arbitrary.
Select carrier waveform output for timer 3 count source by bit 2 and bit 3.
Timer 1, 2, 3 control register TC123 (2B16)
Set “0” to bit 1 and bit 2 to start counting of timer 2 and timer 3.
Carrier wave control register, CARCNT (2716)
During waveform output of remote-control, whether to output waveform or not
can be controlled by “bit 4: carrier waveform output trigger bit”.
(Refer to Figure below.)
Carrier wave control register, CARCNT (2716)
When waveform output is stopped, set “0” to
“bit 4: Carrier waveform output trigger bit”
while carrier waveform output is set to be invalid.
Timer 1, 2, 3 control register TC123 (2B16)
Set “1” to bit 1 and bit 2 to stop counting of timer 2 and timer 3.
When the carrier wave output circuit operation is started again,
execute the setting from the processing No.2.
Carrier wave control register, CARCNT (2716)
In order to change the carrier wave control from the auto-control by timer 3
to software carrier wave output, initialize the carrier wave circuit
by setting “0” to “bit 1: carrier wave output valid bit”.
Timer count source set register TCSS (2A16)
Set timer 2 count source to bit 0 and bit 1. Also, in order to initialize
carrier waveform circuit, be sure to select f(XIN)/16, f(XIN)/2 or f(XIN)/8
for timer 3 count source.
Do not select carrier waveform output (b3b2=112) for timer 3 count source.
Carrier wave control register, CARCNT (2716)
Set carrier wave control register.
bit 0: Set whether to expand waveform.
bit 1: Select “1: Carrier waveform generating function is valid”
bit 2: Select “0: Software output is invalid”
bit 3: Select “1: auto-control by timer 3 is valid.
bit 4: Select whether carrier waveform output trigger is valid or invalid.
bit 5: Select whether 455 kHz carrier wave generating mode is valid or invalid.
bit 6: Set output level of waveform.
bit 7: Set this bit to “0”.
Timer 2 secondary T2S (2D16)
Timer 2 primary T2P (2C16)
Set carrier wave “H”, “L” duration to timer 2 primary and timer 2 secondary,
respectively.(when 455 kHz carrier waveform generating mode is used,
this setting is not necessary.)
Timer 3 T3 (2E16)
Set valid period/invalid period of carrier waveform output to timer 3.
Waveform output of remote-control
Rev.1.07 Mar 19, 2009 Page 33 of 60
REJ03B0140-0107
7545 Group
Fig. 32 Setting of carrier wave control by software
0 XX 0 0X1 X
b7 b0
0 0 0 0 0 X1X
b7 b0
1
0 0 0 0 XX XX
b7 b0
2
XXXXXXXX
b7 b0
XXXXXXXX
b7 b0
4
0 XX 0 0 0 1X
b7 b0
3
0 0 0 0 0 X0X
b7 b0
5
6
9
0 XX 0 001 X
b7 b0
7
0 0 0 0 0 X1X
b7 b0
8
0 XX 0000X
b7 b0
10
P4
2
/CARR pin output
Carrier waveform
(Timer 2 output)
S
oftware carrier wave output bit
Waveform output timing of remote-control waveform by software carrier waveform output bit
Set “1” to bit 1 to stop counting of timer 2.
Timer 1, 2, 3 control register TC123 (2B16)
Set “0” to bit 1 to start counting of timer 2.
Carrier wave control register, CARCNT (2716)
Timer 1, 2, 3 control register TC123 (2B16)
Set “1” to bit 1 to stop counting of timer 2.
Carrier wave control register, CARCNT (2716)
Carrier wave control register, CARCNT (2716)
Timer count source set register TCSS (2A16)
Set timer 2 count source to bit 0 and bit 1. Also, in order to initialize
carrier waveform circuit, be sure to select f(XIN)/16, f(XIN)/2 or f(XIN)/8
for timer 3 count source.
Do not select carrier waveform output (b3b2=112) for timer 3 count source.
Carrier wave control register, CARCNT (2716)
Timer 2 secondary T2S (2D16)
Timer 2 primary T2P (2C16)
Set carrier wave “H”, “L” duration to timer 2 primary and timer 2 secondary, respectively.
(when 455 kHz carrier waveform generating mode is used,
this setting is not necessary.)
Waveform output of remote-control
Start (initial state after reset)
Timer 1, 2, 3 control register TC123 (2B16)
Generating waveform or not can be controlled by
bit 2: Software carrier waveform output bit
In order to stop carrier waveform,
set bit 2: Software carrier waveform output bit to “0: Output invalid”.
X: Set it to “0” or “1” arbitrary
.
When the carrier wave output circuit operation is started again,
execute the setting from the processing No.4 .
In order to change the carrier wave control from the auto-control by timer 3
to software carrier wave output, initialize the carrier wave circuit
by setting “0” to “bit 1: carrier wave output valid bit”.
Set carrier wave control register.
bit 0: Set whether to expand waveform.
bit 1: Select “1: Carrier waveform generating function is valid”
bit 2: Select “0: Software output is invalid”
bit 3: Select “0: auto-control by timer 3 is invalid.
bit 4: Select “0: carrier waveform output trigger is invalid”
bit 5: Select whether 455 kHz carrier waveform generating mode is valid or invalid.
bit 6: Set output level of waveform.
bit 7: Set this bit to “0”.
Rev.1.07 Mar 19, 2009 Page 34 of 60
REJ03B0140-0107
7545 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a
runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
1. Standard operation of watchdog timer
The watchdog timer is valid by setting “0” to bit 0 of the
Function set ROM data (address FFDA16) of the built-in
QzROM.
When an internal clock is supplied after waiting the oscillation
stabilizing time by timer 1 aft er system is release d from reset, the
watchdog timer starts operation. When the watchdog timer H
underflows, an internal reset occurs. Accordingly, it is
programmed that the watchdog timer control register (address
003916) can be set before an underflow occurs.
When the watchdog timer control register (address 003916) is
read, the values of the high-order 6-bit of the watchdog timer H
and watchdog timer H count source selection bit are read.
2. Initial value of watchdog timer
By a reset or writing to the watchdog timer control register
(address 003916), the watchdog timer H is set to “FF16” and the
watchdog timer L is set to “FF16”.
3. Operation of watchdog timer H count source
selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit
is “0”, the count source becomes a watchdog timer L underflow
signal. The detection time is 262.144 ms at f(XIN) = 4 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 1024 µs at f(XIN) = 4 MHz.
This bit is cleared to “0” afte r res et.
4. STP instruction function sele ction bit
The function of the STP instruction can be selected by the bit 1 in
FSROM. This bit cannot be used for rewriting by executing the
STP instruction.
• When this bit is set to “0”, internal reset occurs by executing
the STP instruction.
• When this bit is set to “1”, stop mode is entered by executing
the STP instruction.
<Notes on W atchdog Timer>
1. The watchdog timer is operating during the wait mode.
Write data to the watchdog timer control register to prevent
timer underflow.
2. The watchdog timer stops during the stop mode. However,
the watchdog timer is running during the oscillation stabi-
lizing time after the STP instruction is released. In order to
avoid the underflow of the watchdog timer, the watchdog
timer H count source selection bit (bit 7 of watchdog timer
control register (address 003916)) must be set to “0” just
before executing the STP instruction.
Fig. 33 Structure of watchdog timer control register
b7 b0
Watchdog timer H (read only for high-order 6-bit)
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Watchdog timer control register
(WDTCON: address 003916, initial value: 3F16)
Disable (returns “0” when read)
Rev.1.07 Mar 19, 2009 Page 35 of 60
REJ03B0140-0107
7545 Group
Fig. 34 Timing diagram at reset
Fig. 35 Block diagram of watchdog timer and reset circuit
f
(XIN)
f(XIN) 16384 pulses
R
ESET
I
nternal reset signal
C
PU clock φ
? ? ?FFFCFFFD?
? ? ? ADL ADH?
ADH, ADL
S
YNC
D
ata
A
ddress
Write "FF
16
" to
the watchdog timer
control register
X
IN
Watchdog timer H count source selection bit
"0"
"1"
Watchdog timer H(8)
Reset circuit
Watchdog timer L(8)
Voltage drop detection circuit
Power-on reset circuit
Internal reset
1/16
STP instruction function selection bit
STP instruction
RESET
Write "FF
16
" to
the watchdog timer
control register
Count start
(Watchdog timer disable bit
(bit 0 of FSROM)
Rev.1.07 Mar 19, 2009 Page 36 of 60
REJ03B0140-0107
7545 Group
Power-on Reset Circuit
Reset can be automatically performed at power on (power-on
reset) by the built-in power-on reset circuit.
In order to use the power-on reset circuit effectively, the time for
the supply voltage to rise fr om 0 V to 1.8 V must be set to 1 ms
or less.
Voltage Drop Detection Circuit
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply
voltage drops below a set value (Typ.1.75 V). When the STP
instruction is executed, the voltage drop detection circuit is
stopped, so that the power dissipation is reduced.
The operation of the voltage drop detection circuit is disabled by
setting “0” to bit 4 of the Function set ROM data (address
FFDA16) of the built-in QzROM.
Note: The emulator MCU “M37545 RLSS” is not equipped with
the voltage drop detection circuit.
RESETOUT Output
RESETOUT function is used to output “L” level from RESET
pin when system reset occurs by the power-on reset, the voltage
drop detection circuit or the watchdog timer. Also, the built-in
pull-up transistor is connected to the RESET pin. Fig. 36 Operation wave form diagram of power-on reset
circuit
Fig. 37 Operation waveform diagram of voltage drop detection circuit
<Note on Voltage Drop Detection Circuit>
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and
regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added to
the power supply pin, the following case may cause program
failure;
supply voltage does not fall below to VDET, and its voltage re-
goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VDET and re-goes up after that.
Fig. 38 VCC and VDET
VCC (Note)
1ms or less
Power-on Reset released
Internal reset signal
Reset
state
N
ote: Keep the value of supply voltage to the minimum valu
e
or more of the recommended operating conditions.
Po
circuit output
wer-on reset
V
cc
I
nternal reset signal
R
eset voltage (Typ:1.75V)
Microcomputer starts operation
after f(XIN) clock is counted 16384 times.
Note: The voltage drop detection circuit does not have
the hysteresis characteristics in the detected voltag
e.
Vcc
VDET
Reset
Normal operation
No reset
Program failure may occur.
Recommended
o
perating condition
min. value
Vcc
VDET
Recommended
o
perating condition
min. value
Rev.1.07 Mar 19, 2009 Page 37 of 60
REJ03B0140-0107
7545 Group
MISRG
The 7545 Group has two power source supply pins. One is the
VCC pin, and the other is the VDDR pin only for RAM2. A
potential difference between VCC and VDDR may cause some
failures in reading from RAM2 or writing to RAM2.
Accordingly, if there is a pot ential difference between VCC and
VDDR at power-on, confirm the bit 1 (RAM2 status flag) of
MISRG (address 003816) before reading from RAM2 or writ ing
to RAM2.
Fig. 39 Structure of MISRG
Fig. 40 Internal status of microcomputer at reset
b7 b0
RAM2 status flag
0: RW disabled
1: RW enabled
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0316” in timer1, and “FF16”
in prescaler 1 automatically
1: Not set automatically
Reserved bits
(Do not write “1” to these bits)
MISRG(address 003816, initial value: 0X16)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)(
17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
000116
000316
000516
000716
000916
001616
001716
001816
001916
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
003816
003916
003A16
003B16
003C16
003E16
(PS)
(PCH)
(PCL)
0016
00
0016
0016
0016
0016
0016
FF16
0316
0016
0616
FF16
FF16
000000 0
00111111
10000000
0016
0016
X1
0016
0016
000
FF16
00000000
Register contents
Address
Port P0 direct ion register (P0D)
Port P1 direct ion register (P1D)
Port P2 direct ion register (P2D)
Port P3 direct ion register (P3D)
Port P4 direct ion register (P4D)
Pull-up control regis ter (PULL)
Port output mode switch register (PMOD)
Key-on wakeup pin selection register (KEYSEL)
Key-on wakeup edge selection register (KEYEDGE)
Carrier wave control register (CARCNT)
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer count source set reg ist er (TCSS)
Timer 1, 2, 3 control register (TC123)
Timer 2 primary (T2P)
Timer 2 secondary (T2 S)
Timer 3 (T3)
MISRG
Watchdog timer contr ol register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Processor status regis ter
Program counte r Contents of address FFFD16
Contents of address FFFC16
XXXX XX
X
XXXXXX
X
XXXX
X : Undefined
The content of other registers and RAM are undefined when the microcomputer is reset.
The initial values must be surely set before you use it.
Rev.1.07 Mar 19, 2009 Page 38 of 60
REJ03B0140-0107
7545 Group
CLOCK GENERATING CIRCUIT
An oscillation circuit can be formed by connecting a resonator
between XIN and XOUT.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
No external resistor is needed between XIN and XOUT since a
feed-back resistor exists on-chip. (An external feed-back resistor
may be needed depending on conditions.)
<Ceramic resonator/quartz-crystal oscillator>
When the ceramic resonator/quartz-crystal oscillator is used for
the main clock, connect the ceramic resonator/quartz-crystal
oscillator and the external circuit to pins XIN and XOUT at the
shortest dist ance. A feedb ack r esistor is built in between pins XIN
and XOUT. (An external feed-back resistor may be needed
depending on conditions.)
Oscillation Control
1. Stop mode
When the STP instruction is executed, the internal clock φ sto ps
at an “H” level and the XIN oscillator stops. At this time, timer 1
is set to “0316” and prescaler 1 is set to “FF16”when the
oscillation stabilization time set bit after release of the STP
instruction is “0”. On the other hand, timer 1 and prescaler 1 are
not set when the above bit is “1”. Accordingly, set the wait time
fit for the oscillation stabilization time of the oscillator to be
used. When an external interrupt is accepted, oscillation is
restarted but the internal clock φ remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock φ
is supplied. This is because when a ce ramic resonator is used,
some time is required until a sta rt of o sc ill ation.
In the stop mode, the voltage drop detection circu it is stopped, so
that the power dissipation is reduced.
2. Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock
restarts if a reset occurs or when an interrupt is accepted. Since
the oscillator does not stop, normal operation can be started
immediately after the clock is restarted. To ensure that an
interrupt will be accepted to release the STP or WIT state, the
corresponding interrupt enable bit must be set to “1” before the
STP or WIT instructi on is exe cuted.
Fig. 41 Externa l cir cui t of ceramic resonator/quartz-cryst al
oscillator
Fig. 42 Structure of CPU mode register
XIN XOUT
CIN COUT
Rd
M37545
Note: Insert a damping resistor if required.
The resistance will vary depending on the oscillator and the
oscillation drive capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer’s data sheet specifies
that a feedback resistor be added external to the chip
though a feedback resistor exists on-chip, insert a feedback
resistor between XIN and XOUT following the instruction.
Processor mode bits (Note)
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1 Not available
b7 b0
Note : The bit can be rewritten only once after releasing reset.
After rew riting, it is d is ab led to w rite a n y da ta to this bit.
However, by reset the bit is initialized and can be rewritten, again.
It is not disab led to w rite a ny d at a to this bit fo r emulator MCU M37545RLSS.
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Stack page selection bit
0 : 0 page
1 : 1 page
Clock division ratio selection bits
b7 b6
0 0 : Not av a ilable
0 1 : Not av a ilable
1 0 : f(f) = f(X IN)/4
1 1 : Not av a ilable
Not u s ed (returns 0 when read)
Rev.1.07 Mar 19, 2009 Page 39 of 60
REJ03B0140-0107
7545 Group
Fig. 43 Block diagram of system clock generating circuit (for ceramic resonator)
S
R
QS
R
Q
1/2
XIN
R
S
Q
Interrupt request
Interrupt disable flag I
Reset
STP instruction
Timing φ
(Internal clock)
Prescaler 1 Timer 1
Rf
STP inst ructio n
WIT
instruction
1/2 1/4
Reset
Although a feed-back resistor exists on-chip, an external feed-back resistor
may be needed depending on conditions.
Note:
XOUT
Rev.1.07 Mar 19, 2009 Page 40 of 60
REJ03B0140-0107
7545 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be
rewritten while the microcomputer is mounted on-board by u sing
a serial programmer which is applicable for this microcomputer.
Table 10 lists the pin description (QzROM writing mode) and
Figure 44 and Figure 45 show the pin connections.
Refer to Figure 46 and Figure 47 for examples of a connection
with a serial programmer.
Contact the manufacturer of you r serial programmer for seria l
programmer. Refer to the user’s manual of your serial
programmer for details on how to use it.
Table 10 Pin description (QzROM writing mode)
Pin Name I/O Function
VCC, VSS, VDDR Power source Input • Apply 1.8 to 3.6 V to VCC, and 0 V to VSS and VDDR.
RESET Reset input Input • Reset input pin for active “L”. Reset occurs when RESET pin is hold at
an “L”level for 16 cycles or more of XIN.
XIN Clock input Input • Set the same termination as the single-chip mode.
XOUT Clock output Output
P00−P05
P21−P27
P30−P37
P42
I/O port I/O • Input “H” or “L” level signal or leave the pin open.
CNVSS VPP input Input • QzROM programmable power source pin.
P07ESDA input/output I/O • Serial data I/O pin.
P20ESCLK input Input • Serial clock input pin.
P06ESPGMB input Input • R ead/program pulse input pin.
Rev.1.07 Mar 19, 2009 Page 41 of 60
REJ03B0140-0107
7545 Group
Fig. 44 Pin connection diagram (M37545Gx-XXXGP)
Fig. 45 Pin connection dia gram (M37545GxKP)
Package type: PLQP0032GB-A (32P6U-A)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
87
65
34
VCC
CNVSS
P25(LED5)P03/KEY3
P00/KEY0
P02/KEY2
P01/KEY1
P04/KEY4
P37
P36
P35
M37545Gx-XXXGP
M37545GxGP
P26(LED6)
P27(LED7)
P42/CARR
VDDR
RESET
12
P23(LED3)
P24(LED4)
P22(LED2)
P21(LED1)/INT1
P20(LED0)/INT0
P07/KEY7
P06/KEY6
P05/KEY5
XOUT
XIN
VSS
P30
P31
P32
P33
P34
24 23 22 21 20 19 18 17
ESCLK
ESPGMB ESDA
: Connec t t o os c ill at io n ci rcu it
: QzROM pin
*
*
VCC
VPP
RESET
VSS
Package type: PLSP0032JB-A
P21(LED1)/INT132
M37545GxKP
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED6)
P27(LED7)
P42/CARR
RESET
VCC
XIN
XOUT
VSS
P30
P20(LED0)/INT0
P07/KEY7
P06/KEY6
P05/KEY5
P04/KEY4
P03/KEY3
P02/KEY2
P01/KEY1
P37
P00/KEY0
P35
P34
P33
P32
P31
P36
CNVSS
VDDR
ESDA ESCLK
ESPGMB
VCC
VPP
VSS
*
: Connect to oscillat ion circuit
: QzROM pin
*
RESET
Rev.1.07 Mar 19, 2009 Page 42 of 60
REJ03B0140-0107
7545 Group
Fig. 46 When using E8 programmer, connection example
7545 Group
Set the same termination as the
single-chip mode.
Vcc
CNVSS
P07 (ESDA)
P20 (ESCLK)
P06 (ESPGMB)
RESET
Vss
XIN XOUT
4.7 kΩ
4.7 kΩ
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
13
11
9
7
5
3
1
14
12
10
8
6
4
2
RESET
circuit
Vcc
*1: Open-collector buffer
*1
Rev.1.07 Mar 19, 2009 Page 43 of 60
REJ03B0140-0107
7545 Group
Fig. 47 When using programmer of Suisei Electronics Syst em Co., LTD, connection example
7545 Group
T_VDD
T_VPP
T_RXD
T_SCLK
T_PGM/OE/MD
T_RESET
GND
RESET circuit
Set the same termination as the
single-chip mode.
Vcc
CNVSS
P07 (ESDA)
P20 (ESCLK)
P06 (ESPGMB)
RESET
Vss
XIN XOUT
4.7 kΩ
4.7 kΩ
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
T_TXD
T_BUSY N.C.
Rev.1.07 Mar 19, 2009 Page 44 of 60
REJ03B0140-0107
7545 Group
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”.
After reset, initialize flags which affect program execution. In
particular, it is essential to initialize the T flag and the D flag
because of their effect on calculations. Initialize these flags at
beginning of the program.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the de cima l mode fl ag
D to “1”, then execute the ADC instruction o r SBC instruction.
In this case, execute SEC instruction, CLC instruction or CLD
instruction after executing one instruction before the ADC
instruction or SBC instruction.
• In the decimal mode, the values of the N (negative), V
(overflow) and Z (zero) flags are invalid.
Ports
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory
operation instruction when the T flag is “1”, addressing mode
using direction register values as qualifiers, and bit test
instructions such as BBC and BBS.
It is also imposs ible t o use bit operation instru ctions such as CLB
and SEB and read/modify/wri te instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA
instruction, etc.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying
the frequency of the internal clock φ by the number of cycles
mentioned in the machine-language instruction table.
The frequency of the internal clock φ is 4 times the XIN cycle.
CPU Mode Re gis ter
The processor mode bits can be rewritten only once after
releasing reset. However, after rewriting it is disable to write any
value to the bit. (Emulator MCU is excluded.)
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin). Besides, connect
the capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a
ceramic capacitor of 0.01 µF to 0.1 µF is recommended.
Rev.1.07 Mar 19, 2009 Page 45 of 60
REJ03B0140-0107
7545 Group
NOTES ON USE
Countermeasures Against Noise
1. Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring
length short.
<Reason>
The wiring length depends on a microcomput er package. Use of
a small package, for example QFP and not DIP, makes the total
wiring length short to reduce influence of noise.
Fig. 48 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20 mm).
<Reason>
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is
completely initialized. This may cause a program runaway.
Fig. 49 Wiring for the RESET pin
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
• Make the length of wiring (within 20 mm) across the
grounding lead of a capacitor which is connected to an
oscillator and the VSS pin of a microcomputer as short as
possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be
deformed. This may cause a program failure or program
runaway. Also, if a potential difference is caused by the noise
between the VSS level of a microcomputer and the VSS level of
an oscillator, the correct clock will not be input in the
microcomputer.
Fig. 50 Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect CNVSS pin to a GND pattern at the shortest distance.
The GND patter n is required to be as cl ose as possible to the
GND supplied to VSS.
In order to improve the noise reduction, to connect a 5 kΩ
resistor serially to the CNVSS pin - GND line may be valid.
As well as the above-mentioned, in this case, connect to a GND
pattern at the shortest distance. The GND pattern is required to
be as close as possible to the GND supplied to VSS.
<Reason>
The CNVSS pin of the QzROM is the power source input pin for
the built-in QzROM. When programming in the built-in
QzROM, the impedance of the CNVSS pin is low to allo w the
electric current for writing flow into the QzROM. Because of
this, noise can enter easily. If noise enters the CNVSS pin,
abnormal instruction codes or data are read from the built-in
QzROM, which may cause a program runaway.
Fig. 51 Wiring for the VPP pin of the QzROM
DIP
SDIP SOP
QFP
RESET
Reset
circuit
Noise
VSSVSS
Reset
circuit
VSS
RESET
VSS
N.G.
O.K.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
N.G. O.K.
About 5kΩ
VSS
The shortest
The shortest
CNVSS
(Note)
(Note)
Note: This indicates pin.
Rev.1.07 Mar 19, 2009 Page 46 of 60
REJ03B0140-0107
7545 Group
2. Connection of bypass capacitor
(1) Connection of bypass capacitor across VSS line
and VCC line
Connect an approximately 0.1 µF bypass capacitor across the
VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
Fig. 52 Bypass capacitor across the VSS line and the VCC
line
(2) Connection of bypass capacitor across VSS line
and VDDR line
Connect an approximately 0.1 µF bypass capacitor across the
VSS line and the VDDR line as follows:
• Connect a bypass capacitor across the VSS pin and the VDDR
pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VDDR
pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VDDR line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VDDR pin.
Fig. 53 Bypass cap acitor across the VSS line and the VDDR
line
VSS
VCC
VSS
VCC
N.G. O.K.
VSS
VDDR
VSS
VDDR
N.G. O.K.
Rev.1.07 Mar 19, 2009 Page 47 of 60
REJ03B0140-0107
7545 Group
3. Oscillator concerns
So that the product obtains the stabilized operation cloc k on the
user system and its condition, contact the resonator manufacturer
and select the resonator and oscillation circuit constants.
Be careful especially when range of voltage and temperature is
wide.
Take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
(1) Keeping oscillator away from large current signal
lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the
tolerance of current value flows.
<Reason>
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise
occurs because of mutual inductance.
(2) Installing oscillator away from signal lines where
potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
<Reason>
Signal lines where potential levels change frequently (such as the
CARR pin signal line) may affect o ther lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
Fig. 54 Wiring for a large current signal line/Writing of
signal lines where potential levels change
frequently
(3) Oscilla to r protection using VSS pattern
As for a two-sided p rinted circui t board, print a VSS pattern on
the underside (soldering side) of the position (on the component
side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the
shortest possible wiring. Besides, separate this VSS pattern from
other VSS patterns.
Fig. 55 VSS pattern on the underside of an oscillator
XIN
XOUT
VSS
M
Mutual inductance
Large
current
GND
XIN
XOUT
VSS
CARR
Do not cross
N.G.
1. Keeping oscillator away from large current signal lines
2. Installing oscillator away from signal lines where potential
levels change frequently
Microcomputer
XIN
XOUT
VSS
An example of VSS patterns on the
underside of a printed circuit board
Oscillator w iring
pattern example
Separate the V SS line for oscillation from other VSS lines
Rev.1.07 Mar 19, 2009 Page 48 of 60
REJ03B0140-0107
7545 Group
4. Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port, since the output data may reverse
because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers
at fixed periods.
Fig. 56 Setup for I/O ports
5. Providing of watchd og timer function by software
If a microcomputer runs away because of noise or others, it can
be detected by a software watchdog timer and the microcomputer
can be reset to normal operation. This is equal to or more
effective than program runaway detection by a hardware
watchdog timer.
The following shows an example of a watchdog timer provided
by software.
In the following example, to reset a microcomputer to normal
operation, the main routine detects errors of the interrupt
processing routine and the interrupt processing routine detects
errors of the main routine.
This example assumes that interrupt processing is repeated
multiple times in a single mai n ro utine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at
each execution of the main routine. The initial value N should
satisfy the following condition:
N+1 ≥ (Counts of interrupt processing executed in each main
routine)
As the main routine execution cycle may change because of an
interrupt processing or others, the initial value N should have a
margin.
• Watches the operation of the interrupt processing routine by
comparing the SWDT contents with counts of interrupt
processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and
determines to branch to the program initialization routine for
recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt
processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to
branch to the program initialization routine for recovery
processing in the following case:
If the SWDT contents are not initialized to the initial value N
but continued to decrement and if they reach 0 or less.
Fig. 57 Watchdog timer by software
Direction register
Port latch
Data bus
I/O port pins
Noise
Noise
N.G.
O.K.
Main routine
(SWDT)← N
CLI
Main processing
(SWDT)
Interrupt processing
routine errors
N
Interrupt processing routine
(SWDT) ← (SWDT)1
Interrupt processing
(SWDT)
Main routine
errors
>0
≤0RTI
Return
=N?
≤0?
≠N
Rev.1.07 Mar 19, 2009 Page 49 of 60
REJ03B0140-0107
7545 Group
Notes on QzRO M
1. Note on Product shipped in blank
As for the product s hipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur.
Moreover, please note the contact of cables and foreign bodies
on a socket, etc. because a writing environment may cause some
writing errors.
2. Precautions Regarding Overvoltage
Make sure that voltage exceeding the VCC pin voltage is not
applied to other pins. In particular, ensure that the state indicated
by bold lines in Figure below does not occur for pin CNVSS (VPP
power source pin for QzROM) during power-on or power-off.
Otherwise the contents of QzROM could be rewritten.
Fig. 58 Timing Diagram (bold-lined periods are applicable)
3. QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .mask) which is made by the
mask file converter MM.
Be sure to set the ROM option (“MASK option” written in the
mask file converter) setup when making the mask file by using
the mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “0016” and “FF16” can not be accepted.
•Set “FF
16” to the ROM code protect address in ROM data
regardless of the presence or absence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
4. Data Required for QzROM Writing Orders
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, re fer to the “Renesas Tec hnology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
VCC pin voltage
CNVSS pin voltage
“L” input
(1) Input voltage to other MCU pins rises before Vcc pin voltage.
(2) Input voltage to other MCU pins falls after Vcc pin voltage.
Note: The internal circuitry is unstable when Vcc is below the minimum voltage
specification of 1.8 V (shaded portion), so particular care should be
exercised regarding overvoltage.
1.8V 1.8V
~
~
~
~
Rev.1.07 Mar 19, 2009 Page 50 of 60
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ELECTRICAL CHARACTERISTICS (QzROM version)
Absolute Maximum Ratings
Table 11 Absolute maximum ratings
Symbol Parameter Conditions Ratings Unit
VCC Power source voltage VCC, VDDR All voltages are
based on VSS.
When an input
voltage is measured,
output transistors are
cut off.
−0.3 to 5.0 V
VIInput voltage
P00−P07, P10−P11, P20−P27, P30−P37, P40−P42
−0.3 to VCC + 0.3 V
VIInput voltage RESET, XIN −0.3 to VCC + 0.3 V
VIInput voltage CNVSS −0.3 to VCC + 0.3 V
VOOutput voltage
P00−P07, P10−P11, P20−P27, P30−P37, P40−P42, XOUT, RESET −0.3 to VCC + 0.3 V
PdPower dissipation Ta = 25°C 200 mW
Topr Operating temperature −−20 to 85 °C
Tstg Storage temperature −−40 to 125 °C
Rev.1.07 Mar 19, 2009 Page 51 of 60
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Recommended Op erating Conditions
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2. The peak output current is the peak current flowing in each port.
3. The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
4. When the oscillation frequency has a duty cycle of 50 %.
Table 12 Recommended operating condi tions (1) (VCC = 1.8 to 3.6 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
VCC Power source voltage (At 4MHz) 1.8 3.0 3.6 V
VSS Power source voltage 0V
VIH “H” input voltage P00−P07, P10−P11, P20−P27, P30−P37, P40−P420.7VCC VCC V
VIH “H” input voltage RESET, XIN 0.8VCC VCC V
VIL “L” input voltage P00−P07, P10−P11, P20−P27, P30−P37, P40−P4200.3VCC V
VIL “L” input voltage RESET, CNVSS 00.2VCC V
VIL “L” input voltage XIN 0 0.16VCC V
ΣIOH(peak) “H” total peak output current (1)
P00−P07, P10−P11, P20−P27, P30−P37, P40−P42
−80 mA
ΣIOL(peak) “L” total peak output current (1)
P00−P07, P10−P11, P30−P37
80 mA
ΣIOL(peak) “L” total peak output current (1)
P20−P27, P40−P42
80 mA
ΣIOH(avg) “H” total average output current (1)
P00−P07, P10−P11, P20−P27, P30−P37, P40−P42
−40 mA
ΣIOL(avg) “L” total average output current (1)
P00−P07, P10−P11, P30−P37
40 mA
ΣIOL(avg) “L” total average output current (1)
P20−P27, P40−P42
40 mA
IOH(peak) “H” peak output current (2)
P00−P07, P10−P11, P20−P27, P30−P37, P40−P41
VCC = 3.0 V −4mA
IOH(peak) “H” peak output current (2)
P42
VCC = 3.0 V −20 mA
IOL(peak) “L” peak output current (2)
P00−P07, P10−P11, P30−P37
VCC = 3.0 V 4 mA
IOL(peak) “L” peak output current (2)
P20−P27, P40−P42
VCC = 3.0 V 24 mA
IOH(avg) “H” average output current (3)
P00−P07, P10−P11, P20−P27, P30−P37, P40−P41
VCC = 3.0 V −2mA
IOH(avg) “H” average output current (3)
P42
VCC = 3.0 V −10 mA
IOL(avg) “L” average output current (3)
P00−P07, P10−P11, P30−P37
VCC = 3.0 V 2 mA
IOL(avg) “L” average output current (3)
P20−P27, P40−P42
VCC = 3.0 V 12 mA
f(XIN)Internal clock oscillation frequency (4)
at ceramic oscillation or external clock input VCC = 1.8 to 3.6 V 4 MHz
VDET Detection voltage of voltage drop detection circuit Ta = −20 to 85 °C 1.65 1.75 1.85 V
Ta = 0 to 50 °C 1.70 1.75 1.80 V
TDET Low-voltage detection time of voltage drop detection circuit When detected
voltage passes
detection voltage at
±50V/S
0.2 1.2 ms
TPON Power-on reset circuit valid supply voltage rising time VCC = 0 to 1.8 V 1 ms
Rev.1.07 Mar 19, 2009 Page 52 of 60
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Electrical Characteristics
NOTES:
1. In this case, CMOS output is selected by the port output mode selection register.
2. It is available only when operating key-on wake up.
Table 13 Electrical characteristics (1) (VCC = 1.8 to 3.6 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
VOH “H” output voltage
P00−P07, P10−P11, P20−P27, P30−P37 (1)
P40−P41
IOH = −2.0 mA
VCC = 3.0 V 2.1 V
VOH “H” output voltage
P42IOH = −10 mA
VCC = 3.0 V 1.0 V
VOL “L” output voltage
P00−P07, P10−P11, P30−P37IOL = 2 mA
VCC = 3.0 V 0.9 V
VOL “L” output voltage
P20−P27, P40−P42IOL = 12 mA
VCC = 3.0 V 1.5 V
VT+−VT- Hysteresis
INT0, INT1, P00−P07 (2) VCC = 3.0 V 0.3 V
VT+−VT- Hysteresis
RESET VCC = 3.0 V 0.45 V
IIH “H” input current
P00−P07, P10−P11, P20−P27, P30−P37, P40−P42VI = VCC
(Pin floating. Pull up
transistors “off”)
5.0 µA
IIH “H” input current
RESET VI = VCC 5.0 µA
IIL “L” input current
P00−P07, P10−P11, P20−P27, P30−P37, P40−P42VI = VSS
(Pin floating. Pull up
transistors “off”)
−5.0 µA
RFB Feed-back resistor value between XIN-XOUT VCC = 3.0 V, VI = 3.0 V 700 3200 kΩ
RPH Pull-up resistor value
P00−P07VCC = 3.0 V, VI = 0 V 50 120 250 kΩ
RPH Pull-up resistor value
RESET VCC = 3.0 V, VI = 0 V 25 60 130 kΩ
RPL Pull-down resistor value
RESET VCC = 3.0 V, VI = 3.0 V 7.0 kΩ
VRAM1 RAM1 hold voltage (VCC) When clock stopped 1.1 3.6 V
VRAM2 RAM2 hold voltage (VDDR) When clock stopped and
reset by voltage drop
detection
1.1 V
Rev.1.07 Mar 19, 2009 Page 53 of 60
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Electrical Characteristics (continued)
Timing Requirements
Switching Characteristics
NOTE:
1. Pin XOUT is excluded
Table 14 Electrical characteristics (2) (VCC = 1.8 to 3.6 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
ICC Power source
current VCC = 3.0 V, f(XIN) = 4 MHz
Output transistors “off”0.6 1.2 mA
VCC = 3.0 V, f(XIN) = 4 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
0.3 0.6 mA
All oscillation stopped (in STP state)
Output transistors “off”
VCC ≥ VDDR ≥ VCC − 0.6 V
Ta = 25°C0.11.0µA
Ta = 85°C 10.0 µA
IDDR During reset by voltage drop detection circuit
VDDR = 1.1 V, 1.8 V ≥ VCC ≥ 0 V Ta = 25°C0.11.0µA
Ta = 85°C 10.0 µA
Table 15 Timing Requirements (VCC = 1.8 to 3.6 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
tw(RESET)Reset input “L” pulse width 2µs
tC(XIN) External clock input cycle time 250 ns
tWH(XIN)External clock input “H” pulse width 100 ns
tWL(XIN)External clock input “L” pulse width 100 ns
tWH(INT0)INT0, INT1, input “H” pulse width 460 ns
tWL(INT0)INT0, INT1, input “L” pulse width 460 ns
Table 16 Switching Charac teristics (VCC = 1.8 to 3.6 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
tr(CMOS) CMOS output rising time (1) 25 100 ns
tf(CMOS) CMOS output falling time (1) 25 100 ns
Rev.1.07 Mar 19, 2009 Page 55 of 60
REJ03B0140-0107
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PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas
Technology website.
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
*3
F
32
25
24 17
16
9
81
*1
*2
x
b
p
e
H
E
E
D
H
D
Z
D
Z
E
Detail F
L
1
L
A
c
A
2
A
1
Previous CodeJEITA Package Code RENESAS Code
PLQP0032GB-A 32P6U-A
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
1.0
0.125
0.35
0.7
0.7
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9
D
7.17.06.9
E
1.4
A
2
9.29.08.8
9.29.08.8
1.7
A
0.20.1
0
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
b
1
c
1
bp
c
JEITA Package Code
P-LSSOP32-5.6x11-0.65
RENESAS Code
PLSP0032JB-A
Previous Code
32P2X-B
MASS [Typ.]
0.18 g
Rev.1.07 Mar 19, 2009 Page 56 of 60
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APPENDIX
NOTES ON PROGRAMMING
Processor Status Register
1. Initializing of processor status register
Flags which affect program execution must be initialized after a
reset.
In particular, it is essential to initialize the T and D flags becaus e
they have an important effect on calculations. Initialize these
flags at beginning of the program.
<Reason>
After a re set, the c ont ents of the proc esso r sta tus re gist er (PS) are
undefined except for the I flag which is “1”.
Fig 1. Initialization of processor status register
2. How to reference the processor status register
To reference the contents of the processor status register (PS) ,
execute the PHP ins tructio n once the n read the co nten ts of (S+1).
If necessary, execute the PLP instruction to return the PS to its
original status.
Fig 2. Stack memory contents after PHP instruction
execution
Decimal Calculations
1. Execution of dec imal calculations
The ADC and SBC are the only instructions which will yield
proper decimal notation, set the decimal mode flag (D) to “1”
with the SED instruction. After executing the ADC or SBC
instruction, execute another instruction before executing the
SEC, CLC, or CLD instruction.
Fig 3. Instructions for decimal calculations
2. Notes on status flag in decimal mode
When decimal mode is selected, th e values of thre e of the flag s in
the status register (the N, V, and Z flags) are invalid aft er a ADC
or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result
of the calculation, or is cleared to “0” if a borrow is generated.
To dete rmine whether a ca lculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check
for a borrow, the C flag must be initialized to “1” before each
calculation.
3. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
4. Multiplication and division instructions
(1) The index X mode (T) and the decimal mode (D) flags do
not affect the MUL and DIV instruction.
(2) The execution of these instructions does not change the
contents of the processor status register.
Initializing of flags
Main program
Reset
(S)
(S)+1 Stored PS
ADC or SBC instruction
NOP instruction
Set D flag to 1
SEC, CLC, or CLD instruction
Rev.1.07 Mar 19, 2009 Page 57 of 60
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5. Read-modify-write instruction
Do not execute a read-modify-write instruction to the read
invalid address (SFR).
The read-modify-write instruction operates in the following
sequence: read one-byte of data from memory, modify the data,
write the data back to original memory. The following
instructions are classified as the read-modify-write instructions
in the 740 Family.
(1) Bit managem ent in structions: CLB, SEB
(2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF
(3) Add and subtract instructions: DEC, INC
(4) Logical operation instructions (1’s complement): COM
Add and subtract/log ical operation instructions (ADC, SBC,
AND, EOR, and ORA) when T flag = “1” operate in the way as
the read-modify-write instruction. Do not execute the read
invalid SFR.
<Reason>
When the read-modify-write instruction is executed to read
invalid SFR, the instruction may cause the following
consequence: the instruction reads unspe cif ied dat a fro m th e area
due to the read invalid condition. Then the instruction modifies
this unspecified data and writes the data to the area. The result
will be random data written to the area or some unexpected
event.
NOTES ON PERIPHERAL FUNCTIONS
Notes on I/O Ports
1. Pull-up control register
When using each port which built in pull-up resistor as an output
port, the pull-up control bit of corresponding port becomes
invalid, and pull-up resistor is not connected.
<Reason>
Pull-up control is effective only when each direction register is
set to the input mode.
2. Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input
levels of an input port and an I/O port “undefined”.
Pull-up (connect the port to Vcc) or pull-do wn (connect the por t
to Vss) these ports through a resistor.
When determining a re sistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current
values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing
out to external.
<Reason>
The output transistor becomes the OFF state, which causes the
ports to be the high-impedance state. Note that the level becomes
“undefined” depending on external circuits.
Accordingly, the potent ial which is input to the input buffer in a
microcomputer is unstable in the state that input levels of an
input port and an I/O port are “undefined”. This may cause
power source current.
*1 stand-by state : the stop mode by executing the STP
instruction
3. Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit
managing instruction*1, the value of the unspecified bit may be
changed.
<Reason>
I/O ports are set to input or output mode in bit units. Reading
from a port register or writing to it involves the following
operations.
• Port in input mode
Read: Read the pin level.
Write: Write to the port latch.
• Port in output mode
Read: Read the port latch or read the output from the
peripheral function (specifications differ depending on the
port).
Write: Write to the port latch. (The port latch value is output
from the pin.)
Since bit managing instructions*1 are read-modify-write
instructions,*2 using such an instruction on a port register causes
a read and writ e to be performed simultaneously on the bits other
than the one specified by the instruction.
When an unspecified bit is in input mode, its pin level is read and
that value is written to the port latch. If the previous value of the
port latch differs from the pin level, the port latch value is
changed.
If an unspecified bit is in output mode, the port latch is generally
read. However, for some ports the peripheral functi on output is
read, and the value is writte n to the port latch. In this case, if the
previous value of the port latch differs from the peripheral
function output, the port latch value is changed.
*1 Bit managing instructions: SEB and CLB instructions
*2 Read-modify-write instructions: Instructions that read
memory in byte units, modify the value, and then write the
result to the same location in memory in byte units
4. Direction register
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory
operation instruction when the T flag is “1”, addressing mode
using direction register values as qualifiers, and bit test
instructions such as BBC and BBS.
It is also impossib le to us e bit operation instru ctions such as CLB
and SEB and read-modify-write instructions of direction
registers for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA
instruction, etc.
Rev.1.07 Mar 19, 2009 Page 58 of 60
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Termination of Unused Pins
1. Termi nate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to VCC
or VSS through each resistor of 1 kΩ to 10 kΩ. The port which
can select a built-in pull-up resistor can also use the built-in pull-
up resistor.
When using the I/O ports as the output mode, open them at “L”
or “H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched
over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source
current may increase in the input mode. With regard to an
effects on the system, thoroughly perform system evaluation
on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
2. Termination remarks
(1) I/O ports setting as input mode
(1) Do not open in the input mode.
<Reason>
• The power source current may increase depending on the first-
stage circuit.
• An effect due to noise may be easily produced as compared
with proper termination (1) shown on the above “1. Te rminate
unused pins”.
(2) Do not connect to VCC or VSS directly.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may
occur.
(3) Do not connect multiple ports in a lump to VCC or VSS
through a resistor.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may occur
between ports.
Notes on Interrupts
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous
with the following case, take the sequence shown in Figure 4.
• When switching external interrupt active edge
• When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
Fig 4. Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the
corresponding interrupt may be set to “1”.
• When switching external interrupt active edge
INT0 interrupt edge selection bit (bit 0 of Interrupt edge
selection register (address 3A16))
INT1 interrupt edge selection bit (bit 1 of Interrupt edge
selection register)
Key-on wakeup edge selection register (address 1916)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an
interrupt request bit immediately after this bit is set to “0”, take
the following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an
interrupt request bit is cleared to “0”, the value of the interrupt
request bit before being cleared to “0” is read.
Fig 5. Sequence of check of interrupt request bit
Set the interrupt edge selection bit, active edge switch bit,
or the interrupt source selection bit.
NOP (One or more instructions)
Set the corresponding interrupt request bit to 0
(no interrupt request issued).
Set the corresponding interrupt enable bit to 0 (disabled).
Set the corresponding interrupt enable bit to 1 (enabled).
Set the interrupt request bit to 0 (no interrupt issued)
NOP (One or more instructions)
Execute the BBC or BBS instruction
Rev.1.07 Mar 19, 2009 Page 59 of 60
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Notes on Timers
1. When n (0 to 255) is written to a timer latch, the frequency
division ratio is 1/(n+1).
2. Timer count source
Stop timer 2, timer 3 counting to change its count source.
3. Timer 1, timer 2, timer 3 count start timing and count time
when operation starts
Time to first underflow is different from time among next
underflow by the timing to start the timer and count source
operations after count starts.
4. Timer 2, timer 3, carrier wave generating circuit
The timing adjustment of the output waveform causes the
gap between the timer count value and the output
waveform, and the output waveform changes in the reload
cycle after the timer underflow.
Moreover, the timer interrupt occurs at the change point of
the output waveform.
(The timing of the interrupt occurrence is behind a half
cycle of the count source, compared with timer 1.)
Notes on Watchdog Timer
1. The watchdog timer is operating during the wait mode.
Write data to the watchdog timer control register to prevent
timer underflow.
2. The watchdog timer stops during the stop mode. However,
the watchdog timer is running during the oscillation stabi-
lizing time after the STP instruction is released. In order to
avoid the underflow of the watchdog timer, the watchdog
timer H count source selection bit (bit 7 of watchdog timer
control register (address 3916)) must be set to “0” just
before executing the STP instruction.
Notes on RESET Pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a
ceramic capacitor or others across the RESET pin and the Vss
pin.
And use a 1000 pF or more capacitor for high frequency use.
When connecting the capacitor, note the following:
• Make the length of the wiring which is connected to a
capacitor as short as possible.
• Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer
failure.
Notes on Power-on Reset Circuit
Reset occurs by the power-on reset circuit under the following
conditions;
• when the power source voltage rises from 0 V to 1.8 V within
1 ms.
Also, note that reset may not occur under the following
conditions;
• when the power source voltage rises from the voltage higher
than 0 V.
• when it takes longer than 1 ms that the power source voltage
rises from 0 V to 1.8 V.
Note on Voltage Drop Detection Circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and
regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added to
the power supply pin, the following case may cause program
failure;
supply voltage does not fall below to VDET, and its voltage re-
goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VDET and re-goes up after that.
Fig 6. VCC and VDET
Notes on Clock Generati ng Circuit
(1) CPU mode register
Processor mode bits (bits 1 and 0) of CPU mode register (address
3B16) is used to control operation modes of the microcomputer.
In order to prevent the dead-lock by erroneously writing (ex.
program run-away), these bits can be rewritten only once after
releasing reset.
After rewriting, it is disabled to write any data to the bit. (The
emulator MCU “M37545RLSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB, etc.)
are executed to bits 2, 6, 7, bits 1 and 0 are locked.
(2) Ceramic resonator
When the ceramic resonator/quartz-crystal oscillation is used for
the main clock, connect the ceramic resonator and the external
circuit to pins XIN and XOUT at the shortest distance. A feedback
resistor is built-in.
Vcc
VDET
Reset
Normal operation
No reset
Program failure may occur.
Recommended
o
perating condition
min. value
Vcc
VDET
Recommended
o
perating condition
min. value
Rev.1.07 Mar 19, 2009 Page 60 of 60
REJ03B0140-0107
7545 Group
Notes on Oscilla t io n Control
1. Stop mode
(1) When the stop mode is used, set “1” (STP instruction
enabled) to the ST P instruction function selection bit (bit 1
of Function set ROM data (address FFDA16)).
(2) The oscillation stabilizing time after release of STP
instruction can be selected from “set automatica lly”/“ not se t
automatically” by the oscill ati on stabil izing t ime set bi t afte r
release of the STP instruction (bit 0 of MISRG (address
3816)). When “0” is set to this bit, “0316” is set to timer 1
and “FF16” is set to prescaler 1 automatically at the
execution of the STP instruction. When “1” is set to this bit,
set the wait time to timer 1 and prescaler 1 according to the
oscillation stabilizing time of the oscillation. Also, when
timer 1 is used, set values again to timer 1 a nd prescaler 1
after system is returned from the stop mode.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the s upply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin, VDDR pin) and GND pin (VSS pin). Besides,
connect the capacitor to as close as possible. For bypass
capacitor which should not be located too far from the pins to be
connected, a ceramic capacitor of 0.1 µF is recommended.
Handling of CNVSS Pin
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it ha s the multiplexed function
to be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, make the length of wiring
between the CNVSS pin and the VSS pin the shortest possible.
Notes on QzRO M
1. Note on Product shipped in blank
As for the product s hipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur.
Moreover, please not e the contact of cables and foreign bodies
on a socket, etc. because a writing environment may cause some
writing errors.
2. Precautions Regarding Overvoltage
Make sure that voltage exceeding the VCC pin voltage is not
applied to other pins. In particular, ensure that the state indicated
by bold lines in Figure below does not occur for pin CNVSS (VPP
power source pin for QzROM) during power-on or power-off.
Otherwise the contents of QzROM could be rewritten.
Fig 7. Timing Diagram (bold-lined periods are ap plicable)
3. QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask fi le (extension: .mask) which is made by the
mask file converter MM.
Be sure to set the ROM option (“MASK option” written in the
mask file converter) setup when making the mask file by using
the mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “0016” and “FF16” can not be accepted.
•Set “FF
16” to the ROM code protect address in ROM data
regardless of the presence or a bsence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
4. Data Required for QzROM Writing Orders
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
VCC pin voltage
CNVSS pin voltage
“L” input
(1) Input voltage to other MCU pins rises before Vcc pin voltage.
(2) Input voltage to other MCU pins falls after Vcc pin voltage.
Note: The internal circuitry is unstable when Vcc is below the minimum voltage
specification of 1.8 V (shaded portion), so particular care should be
exercised regarding overvoltage.
1.8V 1.8V
~
~
~
~
(1/2)
REVISION HISTORY 7545 Group Datasheet
Rev. Date Description
Page Summary
1.00 Feb . 07 , 20 0 5 −First edition issued
1.01 May. 10, 2005 20 Fig.22 : Carrier wave auto-control bit; “1” and “0” added.
26 Standard operation of watchdog timer and Operation of STP instruction disable bit:
address FFFA16 → address FFDA16
Note on Watchdog Timer 2: ... set to “1” just before ... → ... set to “0” just before ...
28 Voltage Drop Detection Circuit: add ress FFFA16 → address FFDA16
33 S tate transition deleted
36 Fig. 51 partly revised
40 Table 9: RPL; V → kΩ
42 Fig. 55: CNTR0 → INT0
47 Notes on Wa tchdog timer: ... set to “1” just before ... → ... set to “0” just before ...
Notes on Clock Genera tin g C irc uit 1: bits 2 to 4 to 7 → bits 2, 6, 7
1.02 Jul. 20, 2005 All pages ROM option → Function set ROM
3 Table 1: added.
11 ROM Code Protect Address (address FFDB16) added.
16 Termination of unused pins added.
35 [ROM option data] ROMOP → [Function set ROM] FSR OM
Fig. 42, 43: partly revised.
37 (4) Wiring to CNVSS pin → (4) Wiring to VPP pin
51 DATA REQUIRED FOR QzROM WRITING ORDERS, Notes On QzROM Writing
Orders,
Notes On ROM Code Protect added.
1.03 Oct. 21, 2005 −STP instruction disable bit → STP instruction function selection bit
29 “Operation of STP instruction function selection bit” revised.
30 Fig.33 Block diagram of watchdog timer and reset circuit
“Count start (W atchdog timer disable bit (bit 0 of FSROM))” added.
35 Function set ROM : Description revised.
Fig.42: Reserved → Renesas shipment test area
“When the checksum is included in the user program, avoid assigning it to
these areas.” added to Note.
Fig.43: Bit 0, bit 1 and bit 4 of FSROM revised.
1.04 May. 17, 2006 −“PRELIMINARY” eliminated.
1.05 May. 18, 2006 6 Fig.4 “Under development” eliminated.
1.06 Feb. 29, 2008 1 Revised by additional new products (memory size)
2 Fig. 2 is added
3 Revised by additional new products (memory size and package)
6 Fig. 5 is added
8 Revised by additional new products (memory size, package, Fig. 6, and Tabl e 4)
12 Fig. 9 is revised
13 Function set ROM Area and Notes (2) - (5) added
Clock circuit is deleted from [Function set ROM data] FSROM
Notes on use deleted
14 Fig. 10 is revised
16 Fig.12 added
20 to 24 Interrupts is revised whole
(2/2)
REVISION HISTORY 7545 Group Datasheet
1.06 Feb. 29, 2008 34 Initial value of watchdog timer: Description added
Operation of STP instruction function selection bit deleted
STP instruction function selection bit added
35 Fig. 35 is revised
38 Fig. 42 is revised
40 Function set ROM is moved to Memory (page 13)
40 to 44 QzROM Writing Mode is added
45 Notes on Hardware is added
46 (4) Wiring to VPP pin: “VPP” → “CNVSS”
Fig.52 is revised
52 Symbol of Feed-back resistor value between XIN-XOUT is revised
55 PLSP0032JB-A package is added.
56 Fig.2, 4, and BRK instruction deleted
57 Modifyi ng output data with bit managing instruction i s revised
59 Notes on Watchdog Timer: 3. is added
60 Notes on Oscillation Control is revised (“0” → “1”)
Precautions Regarding Overvoltage is added
1.07 Mar 19, 2009 8 Fig.6 “Under development” deleted
Table 4 M37545GCKP and M37545GFKP deleted
41 Fig. 44 and Fig.45 RESET→RESET
44 “Processor Status Register” revised
49 “Notes on QzROM” added
56 “1. Initializing of processor status register” revised / Figure title of F ig.3 revised
60 “Notes On QzROM Writing Orders” is revised
“Precautions Regarding Overvoltage” revised:
CNVSS power source pin for QzROM→VPP power source pin for QzROM
Rev. Date Description
Page Summary
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Notes:
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please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
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Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
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9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
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rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
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