1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
Y
B
Z
A
GND2
DW PACKAGE
GND2
NC
R
RE
D
D1
DE
GND1
D2
VCC1
VCC2
DE 7
D8
R5
6
RE
Y
Z
B
A
14
11
12
13
NGALVANIC ISOLATI O
D1
2OSC
1
D2
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
Isolated 3.3V RS-485 Transceiver With Integrated Transformer Driver
Check for Samples: ISO35T
1FEATURES
•3000VRMS / 4242VPK Isolation
•Bus-Pin ESD Protection
–16 kV HBM Between Bus-Pins and GND2
–6 kV HBM Between Bus-Pins and GND1
•1/8 Unit Load –Up to 256 Nodes on a Bus
•Designed for RS-485 and RS-422 Applications
•Signaling Rates up to 1 Mbps
•Thermal Shutdown Protection FUNCTION DIAGRAM
•Typical Efficiency >60% (ILOAD = 100 mA)
- see SLUU470
•Low Driver Bus Capacitance 16 pF (Typ)
•50 kV/µs Typical Transient Immunity
•UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
Approvals Pending
•Fail-safe Receiver for Bus Open, Short, Idle
•Logic Inputs are 5-V Tolerant
APPLICATIONS
•Isolated RS-485/RS-422 Interfaces
•Factory Automation
•Motor/Motion Control
•HVAC and Building Automation Networks
•Networked Security Stations
DESCRIPTION
The ISO35T is an isolated differential line transceiver with integrated oscillator outputs that provide the primary
voltage for an isolation transformer. The device is a full-duplex differential line transceiver for RS-485 and
RS-422 applications that can easily be configured for half-duplex operation by connecting pin 11 to pin 14, and
pin 12 to pin 13.
These devices are ideal for long transmission lines since the ground loop is broken to allow for a much larger
common-mode voltage range. The symmetrical isolation barrier of the device is tested to provide 4242VPK of
isolation per VDE for 60s between the bus-line transceiver and the logic-level interface.
Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can
cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and
duration. The ISO35T can significantly reduce the risk of data corruption and damage to expensive control
circuits.
The ISO35T is specified for use from –40°C to 85°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
C2
1
2
3
4
5
6
7
8
D1
D2
VCC1
GND1
R
RE
DE
D
VCC2
A
B
GND2
Z
Y
C3
16
14
13
12
11
15
9, 10
OUT
NC
C6
IN
EN
GND
5
1
LDO
1
3
2
C5C4
D1
D2
8
7
6
5
4
3
2
1
C1
X-FMR
ISO35T
Isolated Supply to
other Components
RS-485 Bus
Interface
Control
Circuitry
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
Typical Application Circuit (For details see sluu470)
PIN DESCRIPTIONS
NAME PIN # FUNCTION
D1 1 Transformer Driver Terminal 1, Open Drain Output
D2 2 Transformer Driver Terminal 2, Open Drain Output
GND1 3 Logic-side Ground
VCC1 4 Logic-side Power Supply
R 5 Receiver Output
RE 6 Receiver Enable Input. This pin has complementary logic.
DE 7 Driver Enable Input
D 8 Driver Input
GND2 9, 15 Bus-side Ground. Both pins are internally connected.
NC 10 No Connect. This pin is not connected to any internal circuitry.
Y 11 Non-inverting Driver Output
Z 12 Inverting Driver Output
B 13 Inverting Receiver Input
A 14 Non-inverting Receiver Input
VCC2 16 Bus-side Power Supply
2Copyright ©2010–2011, Texas Instruments Incorporated
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
vertical spacer
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
VCC1,VCC2 Input supply voltage(2) –0.3 to 6 V
VA,VB,VY,VZVoltage at any bus I/O terminal (A, B, Y, Z) –9 to 14 V
VD1,VD2 Voltage at D1, D2 14 V
V(TRANS) Voltage input, transient pulse through 100Ω, see Figure 12 (A,B,Y,Z) –50 to +50 V
VIVoltage input at any D, DE or RE terminal –0.5 to 7 V
IOReceiver output current ±10 mA
ID1,ID2 Transformer Driver Output Current 450 mA
Bus pins and GND1 ±6 kV
JEDEC Standard 22, Test Method
Human Body Model Bus pins and GND2 ±16 kV
A114-C.01
Electrostatic All pins ±4 kV
ESD discharge Charged Device Model JEDEC Standard 22, Test Method ±1.5 kV
C101 All pins
Machine Model ANSI/ESDS5.2-1996 ±200 V
TJMaximum junction temperature 170 °C
TSTG Storage temperature -65 to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
VCC1,VCC2 Supply Voltage 3.0 3.3 3.6 V
VIor VIC Voltage at any bus terminal (separately or common-mode) –7 12 V
VIH High-level input voltage 2 VCC
D, DE, RE V
VIL Low-level input voltage 0 0.8
VID Differential input voltage A with respect to B –12 12 V
RLDifferential load resistance 54 60 Ω
Driver –60 60
IOOutput Current mA
Receiver –8 8
TAAmbient temperature -40 85 °C
TJOperating junction temperature –40 150 °C
1 / tUI Signaling Rate 1 Mbps
SUPPLY CURRENT &COMMON MODE TRANSIENT IMMUNITY
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1(1) Logic-side quiescent supply DE &RE = 0V or VCC1 (Driver and Receiver Enabled or 4.5 8 mA
current Disabled), D = 0 V or VCC1, No load
ICC2(1) Bus-side quiescent supply RE = 0 V or VCC1, DE = 0 V (driver disabled), No load 7.5 13 mA
current RE = 0 V or VCC1, DE = VCC1 (driver enabled), D = 0 V or VCC1, 9 16
No Load
CMTI Common-mode transient See Figure 13 25 50 kV/µs
immunity
(1) ICC1 and ICC2 are measured when device is connected to external power supplies, VCC1 &VCC2. In this case, D1 &D2 are open and
disconnected from external transformer.
Copyright ©2010–2011, Texas Instruments Incorporated 3
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
RS-485 DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO= 0 mA (No Load) 2.5 VCC2
RL= 54 Ω(RS-485), See Figure 1 1.5 2
|VOD| Differential output voltage magnitude V
RL= 100 Ω(RS-422)(1), See Figure 1 2 2.3
Vtest =–7 V to +12 V, See Figure 2 1.5
Change in magnitude of the differential output
Δ|VOD| See Figure 1 and Figure 2 –0.2 0 0.2 V
voltage
VOC(SS) Steady-state common-mode output voltage 1 2.6 3 V
Figure 3
Change in steady-state common-mode output
ΔVOC(SS) –0.1 0.1 V
voltage
VOC(pp) Peak-to-peak common-mode output voltage See Figure 3 0.25 V
IIInput current, D &DE VIat 0 V or VCC1 –10 10 µA
VYor VZ= 12V,
VCC = 0 V or 3 V, 90
DE = 0 V Other input
IOZ High-impedance state output current µA
at 0 V
VYor VZ=–7 V,
VCC = 0 V or 3 V, –10
DE = 0 V
IOS(P)(2) Peak short-circuit output current 300 mA
VYor VZ=–7 V to +12 V, Other input
See Figure 4 at 0 V
IOS(SS)(2) Steady-state short-circuit output current -250 250 mA
VI= 0.4 sin (4E6πt) + 0.5V,
C(OD) Differential output capacitance 16 pF
DE at 0 V
(1) VCC2 = 3.3 V ±5%
(2) This device has thermal shutdown and output current-limiting features to protect in short-circuit fault condition.
RS-485 DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay See Figure 5 205 340
tsk(p) Pulse skew (|tPHL –tPLH|) 1.5 ns
trDifferential output signal rise time 120 185 300
tfDifferential output signal fall time 120 180 300
tPHZ Propagation delay, high-level-to-high-impedance output See Figure 6 205
tPZH Propagation delay, high-impedance-to-high-level output 530 ns
tPLZ Propagation delay, low-level to high-impedance output See Figure 7 330
tPZL Propagation delay, high-impedance-to-low-level output 530
RS-485 RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT(+) Positive-going input threshold voltage IO= -8 mA –20 mV
VIT(–)Negative-going input threshold voltage IO= 8 mA –200
Vhys Hysteresis voltage (VIT+ –VIT–) 50 mV
VID = +200 mV, IO= -8
VOH High-level output voltage 2.4
mA
See Figure 8 V
VID =–200 mV, IO= 8
VOL Low-level output voltage 0.4
mA
IO(Z) High-impedance state output current VO= 0 or VCC1, RE = VCC1 –1 1 µA
4Copyright ©2010–2011, Texas Instruments Incorporated
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
RS-485 RECEIVER ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VAor VB= 12 V 50 100
VAor VB= 12 V, VCC2 = 0 60 100
V
IA, IBBus input current Other input at 0 V µA
VAor VB=–7 V –100 –40
VAor VB= -7 V, VCC2 = 0 –100 –30
V
IIH High-level input current, RE VIH = 2. V –10 10 µA
IIL Low-level input current, RE VIL = 0.8 V –10 10
RID Differential input resistance Measured between A &B 96 kΩ
CID Differential input capacitance VI= 0.4 sin (4E6πt) + 0.5V, DE at 0 V 2 pF
RS-485 RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH,Propagation delay 85 115
tPHL
tsk(p) Pulse skew (|tPHL –tPLH|) 13
See Figure 9 ns
trOutput signal rise time 1 4
tfOutput signal fall time 1 4
tPHZ, Propagation delay, high-level to high-impedance output See Figure 10,13 25
tPZH Propagation delay, high-impedance to high-level output DE at 0 V ns
tPLZ Propagation delay, low-level to high-impedance output See Figure 11,13 25
tPZL Propagation delay, high-impedance to low-level output DE at 0 V
TRANSFORMER DRIVER CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOSC Oscillator frequency VCC1 = 3.3V ±10%, D1 and D2 connected to Transformer 300 400 550 kHz
RON Switch on resistance D1 and D2 connected to 50Ωpull-up resistors 1 2.5 Ω
tr_D D1, D2 output rise time VCC1 = 3.3V ±10%, see Figure 14, D1 and D2 connected to 70 ns
50-Ωpull-up resistors.
tf_D D1, D2 output fall time VCC1 = 3.3V ±10%, see Figure 14, D1 and D2 connected to 80 ns
50-Ωpull-up resistors.
fSt Startup frequency VCC1 = 2.4 V, D1 and D2 connected to Transformer 350 kHz
tBBM Break before make time delay VCC1 = 3.3V ±10%, see Figure 14, D1 &D2 connected to 140 ns
50-Ωpull-up resistors.
Copyright ©2010–2011, Texas Instruments Incorporated 5
375
375
60
.+
-
D
DE
Y
Z
W
W
W
VCC2
0 or 3 V
GND2
VOD V =
-7 V to 12 V
TEST
0 or
II
VI
D
DE
Y
Z
VZVY
VOD
IY
IZ
GND2GND1
VCC1
VCC1
GND2GND1
RL
VOC
ZVZ
VY
Y
VOC(SS)
OC(p-p)
V
Generator: PRR= 100 kHz, 50 % duty
cycle, t r< 6ns , t f< 6 ns, ZO= 50W
Input
Input
II
VI
D
DE
Y
ZVOD
27
±1%
W
VCC1
GND1 GND2
GND2
GND1
IY
IZ
VZVYVOC
27
±1%
W
_
+
VOS
DE
D
GND1 GND2
Y
Z
IOS
IOS
300
250
time
Output Current - mA
RL=54 L= 50pF
50
D
Y
Z
DE
VI
Input
Generator
±20%
±1%
W
W
Generator: PRR = 100 kHz, 50 % duty cycle,
tr< 6ns , t f< 6 ns, ZO= 50W
includes fixture and
instrumentation capacitance
C
L
C
VCC1
GND1
VOD 50%
3 V
tf
tr
tpLH
10%
90%
VI
90%
10%
50%
50 %50 %
VOD
VOD(H)
VOD(L)
tpHL
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD Test and Current Definitions Figure 2. Driver VOD With Common-Mode Loading
Test Circuit
Figure 3. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
Figure 4. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
6Copyright ©2010–2011, Texas Instruments Incorporated
CL= 50 pF
Input
Generator 50
S1 RL= 110
VCC2
D
Y
Z
DE
VI
±20 %
±1%
VO
W
W
GND1 GND2
CL includes fixture and
instrumentation
capacitance
Generator: PRR=50 kHz, 50% duty cycle,
r< 6ns, t f< 6ns, Z
O= 50W
t
50%
3 V
VOL
tpZL
10%
0 V
VO
VI
50%
50%
tpLZ
D S1
3 V Y
0 V Z
VCC2
V
ID
IO
A
B
R
IB
IA
VIC
VA
VB
V
B
V
A+
2
VO
Input
Generator
1.5 V
CL includes fixture and
instrumentation capacitance
A
B
R
±20%
VO
VI
RE
50W
CL= 15 pF
Generator : PRR=100 kHz, 50% duty cycle,
r< 6 ns, t f< 6 ns, ZO= 50 W
t
50% 50%
3 V
VOH
VOL
tf
tr
tpLH
10%
90%
50% 50%
0 V
VO
VI
tpHL
GND2 GND1
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
Figure 8. Receiver Voltage and Current Definitions
Figure 9. Receiver Switching Test Circuit and Waveforms
Copyright ©2010–2011, Texas Instruments Incorporated 7
VCC
Input
Generator 50
R
A
B
CL includesfixture
andinstrumentation
capacitance
RE
VI
VO
W
CL= 15 pF±20 %
S1
W
1k ±1%
1.5 V
0 V
Generator: PRR=100 kHz, 50% duty cycle,
r<6ns, tf<6ns, ZO= 50 W
t
50%
VOH
tpZH
50%
3 V
0 V
90%
VI
VO
0 V
50%
»
tpHZ
VCC
Input
Generator 50
R
A
B
CL includes fixture
and instrumentation
capacitance
RE
VI
VO
W
CL= 15 pF±20 %
S1
W
1k ±1%
0 V
1.5 V
Generator : PRR =100 kHz , 50 % duty cycle ,
r
< 6ns , t f< 6ns, ZO= 50 W
t
50%
3 V
0 V
VI
VCC
VOL
tpLZ
VO
50%
50%
10%
tpZL
B
A
R
100 W
±1%
+
–
Pulse Generator
15 ms duration
1% Duty Cycle
t , t 100 ns
r f £
Z
Y
D
100 W
±1%
+
–
DE
0 V or 3 V
0 V or 3 V
RE
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 10. Receiver Enable Test Circuit and Waveforms, Data Output High
Figure 11. Receiver Enable Test Circuit and Waveforms, Data Output Low
Figure 12. Transient Over-Voltage Test Circuit
8Copyright ©2010–2011, Texas Instruments Incorporated
VOD
D
R
DE
VCC 1
1 kW
RE
54 W
VCC 2
GND 1
VTEST
GND 2
CL= 15 pF
(includes probe and
jig capacitance)
C = 0.1 F 1%
m±
A
B
GND 1
C = 0.1 F
m
±1%
S 1
2.0 V
0.8 V 1.5 V or 0 V
0 V or 1.5 V
Z
Y
54 W
VOH OL
or V
D1
D2
tBBM
90%
10%
10%
90%
tr_D tf_D
tf_D tr_D
tBBM
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 13. Common-Mode Transient Immunity Test Circuit
Figure 14. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs
Copyright ©2010–2011, Texas Instruments Incorporated 9
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
DEVICE INFORMATION
Table 1. Driver Function Table(1)
INPUT ENABLE OUTPUTS
(D) (DE) Y Z
H H H L
L H L H
X L hi-Z hi-Z
X OPEN hi-Z hi-Z
OPEN H H L
(1) H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off)
Table 2. Receiver Function Table(1)
DIFFERENTIAL INPUT ENABLE OUTPUT
VID = (VA–VB) (RE) (R)
–0.02 V ≤VID L H
–0.2 V <VID –0.02 V L ?
VID ≤ –0.2 V L L
X H hi-Z
X OPEN hi-Z
Open circuit L H
Short Circuit L H
Idle (terminated) bus L H
(1) H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off), ? = Indeterminate
10 Copyright ©2010–2011, Texas Instruments Incorporated
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
IEC INSULATION AND SAFETY RELATED SPECIFICATIONS FOR 16-DW PACKAGE
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance(1)) Shortest terminal to terminal distance through air 8.3 mm
L(I02) Minimum external tracking (Creepage(1)) Shortest terminal to terminal distance across the 8.1 mm
package surface
CTI Tracking resistance(Comparative Tracking DIN IEC 60112 / VDE 0303 Part 1 400 V
Index)
Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm
RIO Isolation resistance Input to output, VIO = 500 V, all pins on each >1012 Ω
side of the barrier tied together creating a
two-terminal device
CIO Barrier capacitance Input to output VIO = 0.4 sin (2πft), f = 1 MHz 2 pF
CIInput capacitance to ground VI= VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques
shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications
IEC 60664-1 RATINGS TABLE
PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Rated mains voltage ≤150 VRMS I-IV
Installation classification Rated mains voltage ≤300 VRMS I-III
Rated mains voltage ≤400 VRMS I-II
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIORM Maximum working insulation voltage 566 Vpeak
VPR Input to output test voltage Method b1, VPR = VIORM ×1.875, 1062 Vpeak
100% Production test with t = 1 s,
Partial discharge <5 pC
Method a, After environmental tests subgroup 1, 906
VPR = VIORM ×1.6, t = 10 s,
Partial discharge <5pC
After Input/Output Safety Test Subgroup 2/3, 680
VPR = VIORM x 1.2, t = 10 s,
Partial discharge <5 pC
VIOTM Transient overvoltage t = 60 s (Qualification) 4242 Vpeak
t = 1 s (100% Production)
VIOSM Maximum surge voltage Tested per IEC 60065 (Qualification Test) 4242 Vpeak
RSInsulation resistance VIO = 500 V at TS>109Ω
Pollution degree 2
(1) Climatic Classification 40/125/21
Copyright ©2010–2011, Texas Instruments Incorporated 11
0
100
200
300
400
500
600
0 50 100 150 200
T - Case Temperature - °C
C
Safety Limiting Current - mA
V = V = 3.6 V
CC1 CC2
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
REGULATORY INFORMATION
VDE UL
Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2) Recognized under 1577 Component Recognition Program
Basic Insulation Single / Basic Isolation Voltage, 2500 VRMS(1)
Maximum Transient Overvoltage, 4242 VPK
Maximum Surge Voltage, 4242 VPK
Maximum Working Voltage, 566 VPK
File Number: 40016131 (Approval Pending) File Number: E181974 (Approval Pending)
(1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply. Without current limiting, sufficient power is
dissipated to overheat the die; and, damage the isolation barrier—potentially leading to secondary system
failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISSafety input, output, or supply current θJA = 80.5°C/W, VI= 3.6V, TJ= 170°C, TA= 25°C 500 mA
DW-16
TSMaximum case temperature 150 °C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed on the High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
Figure 15. DW-16 θJC Thermal Derating Curve per IEC 60747-5-2
12 Copyright ©2010–2011, Texas Instruments Incorporated
16V
Input
B Input
16V
VCC 2
36 kW
36 kW
180 k
16V
Input
A Input
36 k
16V
W
W
36 kW
VCC 2
180 kW
16V
Output
Y and Z Outputs
16V
VCC 2
4
6 .5
W
W
VCC 1
R Output
output
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
THERMAL INFORMATION ISO35T
THERMAL METRIC(1) DW UNITS
16 PINS
θJA Junction-to-ambient thermal resistance 80.5
θJC(TOP) Junction-to-case(top) thermal resistance 43.8
θJB Junction-to-board thermal resistance 49.7 °C/W
ψJT Junction-to-top characterization parameter 13.8
ψJB Junction-to-board characterization parameter 41.4
θJC(BOTTOM) Junction-to-case(bottom) thermal resistance n/a
PD(2) VCC1 = VCC2 = 3.6V, TJ= 150°C, RL= 54Ω, CL= 50pF (Driver), CL= 15pF (Receiver), 373 mW
Input a 0.5 MHz 50% duty cycle square wave to Driver and Receiver
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) PD= Maximum device power dissipation
EQUIVALENT CIRCUIT SCHEMATICS
Copyright ©2010–2011, Texas Instruments Incorporated 13
W
VCC 1
1 M
VCC 1
VCC 1
500 W
W1 M
VCC 1
500 W
DE Input
VCC 1
inputinput
D, InputRE
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
14 Copyright ©2010–2011, Texas Instruments Incorporated
Data Rate - Kbps
I - Supply Current - mA
CC
0
10
20
30
40
50
60
0 200 400 600 800 1000
ICC1
ICC2
V = V = 3.3 V,
Driver: R = 54 , C = 50 pF,
Receiver: C = 15 pF
T = 25°C
PRBS Data 2 - 1
CC1 CC2
L L
L
A
W
16
Data Rate - Kbps
ICC1
ICC2
I - Supply Current - mA
CC
0
5
10
15
20
25
0 200 400 600 800 1000
V = V = 3.3 V,
No Load
T = 25°C
PRBS Data 2 - 1
CC1 CC2
A
16
195
200
205
210
215
220
225
230
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
Driver Propagation Delay - ns
tPHL
tPLH
V = V = 3.3 V,
R = 54 ,
C = 50 pF,
CC1 CC2
L
L
W
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
tPHL
tPLH
V = V = 3.3 V,
C = 15 pF
CC1 CC2
L
70
80
90
100
Receiver Propagation Delay - ns
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS
SUPPLY CURRENT SUPPLY CURRENT
vs vs
DATA RATE WITH NO LOAD DATA RATE WITH LOAD
Figure 16. Figure 17.
DRIVER PROPAGATION DELAY RECEIVER PROPAGATION DELAY
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 18. Figure 19.
Copyright ©2010–2011, Texas Instruments Incorporated 15
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
185
190
195
200
205
210
215
220
Driver Rise, Fall Time - ns
V = V = 3.3 V,
R = 54 ,
C = 50 pF
CC1 CC2
L
L
W
tr
tf
600
700
800
900
1000
1100
1200
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
V = V = 3.3 V,
C = 15 pF
CC1 CC2
L
tr
tf
Receiver Rise, Fall Time - ps
0
0.5
1
1.5
2
2.5
3
3.5
0 10 20 30 40 50 60 70
I - Load Current - mA
L
V - Differential Output Voltage - V
OD
T = 25°C
A
V = 3.6 V
CC2
V = 3 V
CC2
V = 3.3 V
CC2
100 W
50 W
0
20
40
60
80
100
120
140
0 1 2 3 4
V - Output Voltage - V
O
5
I - Output Current - mA
O
T = 25 C
A
o
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DRIVER RISE, FALL TIME RECEIVER RISE, FALL TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 20. Figure 21.
DIFFERENTIAL OUTPUT VOLTAGE RECEIVER LOW-LEVEL OUTPUT CURRENT
vs vs
LOAD CURRENT LOW-LEVEL OUTPUT VOLTAGE
Figure 22. Figure 23.
16 Copyright ©2010–2011, Texas Instruments Incorporated
-60
-40
-20
20
40
0
60
-7 -4 -1 2 5 8 11 14
V = 3.3 V
CC
T = 25°C
A
I - Bus Input Current
I- Am
V - Bus Input Voltage - V
I
0
-20
-40
-60
-80
-100
-120
0 1 2 3 4
V - Output Voltage - V
O
I - Output Current - mA
O
T = 25 C
A
o
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS (continued)
RECEIVER HIGH-LEVEL OUTPUT CURRENT BUS INPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE INPUT VOLTAGE
Figure 24. Figure 25.
Copyright ©2010–2011, Texas Instruments Incorporated 17
ISO
GND2 N
ISO IN
Z
v = v
Z + Z
´
9
GN D2 ISO
9 4
N ISO IN
v R 10
= =
v R + R 10 + 6 10
1
16
GND2 ISO
ISO
N
ISO IN IN
1
v C 1 1
= = = = 0.94
1 1 C
v+ 1 +
1 +
C C C
VN
RIN
CIN
RISO
CISO
SystemGround (GND1)
BusReturn(GND2)
16 V
A,B, Y, orZ
ISO35T
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
www.ti.com
APPLICATION INFORMATION
REFERENCE DESIGN
ISO35T Reference design (sluu470) and miniature evaluation boards are available to provide a complete isolated
data and power solution.
TRANSIENT VOLTAGES
Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation and the transient ratings of ISO35T are sufficient for all but the most severe
installations. However, some equipment manufacturers use their ESD generators to test transient susceptibility of
their equipment and can easily exceed insulation ratings. ESD generators simulate static discharges that may
occur during device or equipment handling with low-energy but very high voltage transients.
Figure 26 models the ISO35T bus IO connected to a noise generator. CIN and RIN is the device and any other
stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and
resistance between GND1 and GND2 of ISO35T plus those of any other insulation (transformer, etc.), and we
assume stray inductance negligible. From this model, the voltage at the isolated bus return is
and will always be less than 16 V from VN.
If ISO35T is tested as a stand-alone device, RIN=6×104Ω, CIN= 16 ×10-12 F, RISO= 109Ωand CISO= 10-12 F.
.
Note from Figure 26 that the resistor ratio determines .
the voltage ratio at low frequency and it is the inverse .
capacitance ratio at high frequency. In the
stand-alone case and for low frequency,
.
or essentially all noise appears across the barrier.
At very high frequency,
and 94% of VNappears across the barrier. As long as
RISO is greater than RIN and CISO is less than CIN,
most of transient noise appears across the isolation
barrier, as it should. Figure 26. Noise Model
We recommend the reader not test equipment
transient susceptibility with ESD generators or
consider product claims of ESD ratings above the
barrier transient ratings of an isolated interface. ESD
is best managed through recessing or covering
connector pins in a conductive connector shell and
installer training.
18 Copyright ©2010–2011, Texas Instruments Incorporated
ISO35T
www.ti.com
SLLSE26C –NOVEMBER 2010–REVISED AUGUST 2011
REVISION HISTORY
Changes from Original (November 2010) to Revision A Page
•Changed the data sheet From: Product Preview To: Production data ................................................................................. 1
Changes from Revision A (March 2011) to Revision B Page
•Changed pin 16 From: VCC1 To: VCC2 in the DW Package drawing ..................................................................................... 1
Changes from Revision B (June 2011) to Revision C Page
•Deleted MIN and MAX values from the tr_D, tf_D, and tBBM specifications in theTransformer Driver Chara table. ................ 5
•Changed conditions statement from 1.9V to 2.4V; and changed TYP value from 230 to 350 for fSt specification in
Transformer Driver Characteristics table. ............................................................................................................................. 5
•Added "D1 and D2 connected to 50-Ωpull-up resistors"to conditions statement for tr_D, tf_D, and tBBM specifications
in theTransformer Driver Chara table. .................................................................................................................................. 5
Copyright ©2010–2011, Texas Instruments Incorporated 19
PACKAGE OPTION ADDENDUM
www.ti.com 31-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO35TDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO35TDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO35TDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO35TDWR SOIC DW 16 2000 533.4 186.0 36.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Aug-2012
Pack Materials-Page 2
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