30052857
PRE-BIASED STARTUP CAPABILITY
The LM2854 is in a pre-biased state when the device starts
up with an output voltage greater than zero. This often occurs
in many multi-rail applications such as when powering an FP-
GA, ASIC, or DSP. The output can be pre-biased in these
applications through parasitic conduction paths from one sup-
ply rail to another. Even though the LM2854 is a synchronous
converter, it will not pull the output low when a pre-bias con-
dition exists. The LM2854 will not sink current during start up
until the soft-start voltage exceeds the voltage on the FB pin.
Since the device can not sink current it protects the load from
damage that might otherwise occur if current is conducted
through the parasitic paths of the load.
FEEDBACK VOLTAGE ACCURACY
The FB pin is connected to the inverting input of the voltage
loop error amplifier and during closed loop operation its ref-
erence voltage is 0.8V. The FB voltage is accurate to within
-1.25% / +1.0% over temperature. Additionally, the LM2854
contains error nulling circuitry to substantially eliminate the
feedback voltage over temperature drift as well as the long
term aging effects of the internal amplifiers. In addition, the 1/
f noise of the bandgap amplifier and reference are dramati-
cally reduced. The manifestation of this circuit action is that
the duty cycle will have two slightly different but distinct op-
erating points, each evident every other switching cycle. The
oscilloscope plot shown previously of the SW pin with infinite
persistence set shows this behavior. No discernible effect is
evident on the output due to LC filter attenuation. For further
information, a National Semiconductor white paper is avail-
able on this topic.
POSITIVE CURRENT LIMIT
The LM2854 employs lossless cycle-by-cycle high-side cur-
rent limit circuitry to limit the peak current through the high-
side FET. The peak current limit threshold, denoted ICL, is
nominally set at 6A internally. When a current greater than
ICL is sensed through the PFET, its on-time is immediately
terminated and the NFET is activated. The NFET stays on for
the entire next four switching cycles (effectively four PFET
pulses are skipped). During these skipped pulses, the voltage
on the soft-start pin is reduced by discharging the soft-start
capacitor by a current sink on the soft-start pin of nominally 6
µA or 14 µA for the 500 kHz or 1 MHz options, respectively.
Subsequent over-current events will drain more and more
charge from the soft-start capacitor, effectively decreasing
the reference voltage as the output droops due to the pulse
skipping. Reactivation of the soft-start circuitry ensures that
when the over-current situation is removed, the part will re-
sume normal operation smoothly.
NEGATIVE CURRENT LIMIT
The LM2854 implements negative current limit detection cir-
cuitry to prevent large negative current in the inductor. When
the negative current sensed in the low-side NFET is below
approximately -0.4A, the present switching cycle is immedi-
ately terminated and both FETs are turned off. When both
FETs are off, the negative inductor current originally flowing
in the low-side NFET and into the SW pin commutates to the
high-side PFET’s body diode and ramps back to zero. At this
point, the SW pin becomes a high impedance node and ring-
ing can be observed on the SW node as the stored energy in
the inductor is dissipated while resonating with the parasitic
nodal capacitance.
OVER-TEMPERATURE PROTECTION
When the LM2854 senses a junction temperature greater
than 165°C, both switching FETs are turned off and the part
enters a sleep state. Upon sensing a junction temperature
below 155°C, the part will re-initiate the soft-start sequence
and begin switching once again. This feature is provided to
prevent catastrophic failure due to excessive thermal dissi-
pation.
LOOP COMPENSATION
The LM2854 preserves flexibility by integrating the control
components around the error amplifier while utilizing three
small external compensation components from VOUT to FB.
An integrated type II (two pole, one zero) voltage-mode com-
pensation network is featured. To ensure stability, an external
resistor and small value capacitor can be added across the
upper feedback resistor as a pole-zero pair to complete a type
III (three pole, two zero) compensation network. For correct
selection of these components, see the design section of this
datasheet.
Design Guidelines
INPUT FILTER CAPACITOR
Fast switching currents place a large strain on the input supply
to a buck regulator. A capacitor placed close to the PVIN and
PGND pins of the LM2854 helps to supply the instantaneous
charge required when the regulator demands a pulse of cur-
rent every switching cycle. In fact, the input capacitor con-
ducts a square-wave current of peak-to-peak amplitude equal
to IOUT. With this high AC current present in the input capac-
itor, the RMS current rating becomes an important parameter.
The necessary RMS current rating of the input capacitor to a
buck regulator can be estimated by
where the PWM duty cycle, D, is given by
Neglecting capacitor ESR, the resultant input capacitor AC
ripple voltage is a triangular waveform with peak-to-peak am-
plitude specified as follows
The maximum input capacitor ripple voltage and RMS current
occur at 50% duty cycle. A 22 µF or 47 µF high quality di-
electric (X5R, X7R) ceramic capacitor with adequate voltage
rating is typically sufficient as an input capacitor to the
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LM2854