Reference Manual - Microchip Technology



1997 Microchip Technology Inc. December 1997 /DS33023A

PICmicro™

Mid-Range MCU Family

Reference Manual

December 1997 /DS33023A



1997 Microchip Technology Inc.

Internationally Recognized Quality

System Certiﬁcations

Microchip’ s Quality System embodies the requirements

of ISO9001:1994. Our Microchip Chandler and Tempe

Design and Manuf acturing facilities ha v e been certiﬁed

to ISO 9001. The Microchip Kaohsiung Test facility, and

primary Assembly houses have been certiﬁed to ISO

9002. ISO certiﬁcation plans are in-process for an esti-

mated certiﬁcation grant by year-end 1997. In addition,

Microchip has received numerous customer certiﬁca-

tions, including a Delco issued certiﬁcate of compliance

to AEC-A100/QS9000.

Microchip received ISO 9001 Quality System certiﬁca-

tion for its worldwide headquar ters, design, and wafer

fabrication facilities in January, 1997. Our ﬁeld-pro-

grammab le PICmicro™ 8-bit MCUs , Serial EEPROMs ,

related specialty memory products and development

systems conform to the stringent quality standards of

the International Standard Organization (ISO).

Incorporated, USA. Information contained in this publication

regarding device applications and the like is intended through

suggestion only and may be superseded by updates. No rep-

resentation or warranty is given and no liability is assumed by

Microchip Technology Incorporated with respect to the accu-

racy or use of such infor mation, or infringement of patents or

other intellectual property rights arising from such use or oth-

erwise. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any intellectual property rights.

The Microchip logo and name are registered trademarks of

Microchip Technology Inc. in the U.S.A. and other countries.

the property of their respective companies. No licenses are

conveyed, implicitly or otherwise, under any intellectual prop-

erty rights.”

Trademarks

The Microchip name, logo, PIC, K

, PICMASTER,

PICSTART, PRO MATE, and SEEVAL are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

MPLAB, PICmicro, ICSP and In-Circuit Serial Programming

are trademarks of Microchip Technology Incorporated.

Serialized Quick-Tur n Production is a Service Mar k of Micro-

chip Technology Incorporated.

All other trademarks mentioned herein are property of their

respective companies.

 
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PAGE
 
SECTION 1. INTRODUCTION  1-1
 
Introduction .......................................................................................................................................................1-2
Manual Objective ..............................................................................................................................................1-3
Device Structure ...............................................................................................................................................1-4
Development Support .......................................................................................................................................1-6
Device Varieties  ...............................................................................................................................................1-7
Style and Symbol Conventions  ......................................................................................................................1-12
Related Documents ........................................................................................................................................1-14
Related Application Notes ..............................................................................................................................1-17
Revision History  .............................................................................................................................................1-18
 
SECTION 2. OSCILLATOR  2-1
 
Introduction .......................................................................................................................................................2-2
Oscillator Configurations ..................................................................................................................................2-2
Crystal Oscillators / Ceramic Resonators .........................................................................................................2-4
External RC Oscillator ....................................................................................................................................2-12
Internal 4 MHz RC Oscillator ..........................................................................................................................2-13
Effects of Sleep Mode on the On-chip Oscillator ............................................................................................2-17
Effects of Device Reset on the On-chip Oscillator  .........................................................................................2-17
Design Tips  ....................................................................................................................................................2-18
Related Application Notes ..............................................................................................................................2-19
Revision History  .............................................................................................................................................2-20
 
SECTION 3. RESET  3-1
 
Introduction .......................................................................................................................................................3-2
Power-on Reset (POR), Power-up Timer (PWRT), 
 Oscillator Start-up Timer (OST), Brown-out Reset (BOR), and Parity Error Reset (PER) ..............................3-4
Registers and Status Bit Values .....................................................................................................................3-10
Design Tips  ....................................................................................................................................................3-16
Related Application Notes ..............................................................................................................................3-17
Revision History  .............................................................................................................................................3-18
 
SECTION 4. ARCHITECTURE  4-1
 
Introduction .......................................................................................................................................................4-2
Clocking Scheme/Instruction Cycle ..................................................................................................................4-5
Instruction Flow/Pipelining ................................................................................................................................4-6
I/O Descriptions ................................................................................................................................................4-7
Design Tips  ....................................................................................................................................................4-12
Related Application Notes ..............................................................................................................................4-13
Revision History  .............................................................................................................................................4-14
 
Table of Contents

 
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PAGE
 
SECTION 5. CPU AND ALU  5-1
 
Introduction .......................................................................................................................................................5-2
General Instruction Format ...............................................................................................................................5-4
Central Processing Unit (CPU) .........................................................................................................................5-4
Instruction Clock ...............................................................................................................................................5-4
Arithmetic Logical Unit (ALU) ...........................................................................................................................5-5
STATUS Register .............................................................................................................................................5-6
OPTION_REG Register  ...................................................................................................................................5-8
PCON Register .................................................................................................................................................5-9
Design Tips  ....................................................................................................................................................5-10
Related Application Notes ..............................................................................................................................5-11
Revision History  .............................................................................................................................................5-12
 
SECTION 6. MEMORY ORGANIZATION  6-1
 
Introduction .......................................................................................................................................................6-2
Program Memory Organization ........................................................................................................................6-2
Data Memory Organization  ..............................................................................................................................6-8
Initialization .....................................................................................................................................................6-14
Design Tips  ....................................................................................................................................................6-16
Related Application Notes ..............................................................................................................................6-17
Revision History  .............................................................................................................................................6-18
 
SECTION 7. DATA EEPROM  7-1
 
Introduction .......................................................................................................................................................7-2
Control Register  ...............................................................................................................................................7-3
EEADR ............................................................................................................................................................. 7-4
EECON1 and EECON2 Registers ....................................................................................................................7-4
Reading the EEPROM Data Memory ...............................................................................................................7-5
Writing to the EEPROM Data Memory .............................................................................................................7-5
Write Verify .......................................................................................................................................................7-6
Protection Against Spurious Writes ..................................................................................................................7-7
Data EEPROM Operation During Code Protected Configuration  ....................................................................7-7
Initialization .......................................................................................................................................................7-7
Design Tips  ......................................................................................................................................................7-8
Related Application Notes ................................................................................................................................7-9
Revision History  .............................................................................................................................................7-10
 
SECTION 8. INTERRUPTS  8-1
 
Introduction .......................................................................................................................................................8-2
Control Registers ..............................................................................................................................................8-5
Interrupt Latency  ............................................................................................................................................8-10
INT and External Interrupts ............................................................................................................................8-10
Context Saving During Interrupts ...................................................................................................................8-11
Initialization .....................................................................................................................................................8-14
Design Tips  ....................................................................................................................................................8-16
Related Application Notes ..............................................................................................................................8-17
Revision History  .............................................................................................................................................8-18
 
Table of Contents

 
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PAGE
 
SECTION 9. I/O PORTS  9-1
 
Introduction .......................................................................................................................................................9-2
PORTA and the TRISA Register ......................................................................................................................9-4
PORTB and the TRISB Register ......................................................................................................................9-6
PORTC and the TRISC Register ......................................................................................................................9-8
PORTD and the TRISD Register ......................................................................................................................9-9
PORTE and the TRISE Register ....................................................................................................................9-10
PORTF and the TRISF Register  ....................................................................................................................9-11
PORTG and the TRISG Register ...................................................................................................................9-12
GPIO and the TRISGP Register .....................................................................................................................9-13
I/O Programming Considerations ...................................................................................................................9-14
Initialization .....................................................................................................................................................9-16
Design Tips  ....................................................................................................................................................9-17
Related Application Notes ..............................................................................................................................9-19
Revision History  .............................................................................................................................................9-20
 
SECTION 10. PARALLEL SLAVE PORT  10-1
 
Introduction .....................................................................................................................................................10-2
Control Register  .............................................................................................................................................10-3
Operation ........................................................................................................................................................10-4
Operation in Sleep Mode ................................................................................................................................10-5
Effect of a Reset .............................................................................................................................................10-5
PSP Waveforms .............................................................................................................................................10-5
Design Tips  ....................................................................................................................................................10-6
Related Application Notes ..............................................................................................................................10-7
Revision History  .............................................................................................................................................10-8
 
Table of Contents

 
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PAGE
 
SECTION 11. TIMER0  11-1
 
Introduction .....................................................................................................................................................11-2
Control Register  .............................................................................................................................................11-3
Operation ........................................................................................................................................................11-4
TMR0 Interrupt ...............................................................................................................................................11-5
Using Timer0 with an External Clock  .............................................................................................................11-6
TMR0 Prescaler  .............................................................................................................................................11-7
Design Tips  ..................................................................................................................................................11-10
Related Application Notes ............................................................................................................................11-11
Revision History  ...........................................................................................................................................11-12
 
SECTION 12. TIMER1  12-1
 
Introduction .....................................................................................................................................................12-2
Control Register  .............................................................................................................................................12-3
Timer1 Operation in Timer Mode  ...................................................................................................................12-4
Timer1 Operation in Synchronized Counter Mode .........................................................................................12-4
Timer1 Operation in Asynchronous Counter Mode ........................................................................................12-5
Timer1 Oscillator ............................................................................................................................................12-7
Sleep Operation  .............................................................................................................................................12-9
Resetting Timer1 Using a CCP Trigger Output ..............................................................................................12-9
Resetting of Timer1 Register Pair (TMR1H:TMR1L) ......................................................................................12-9
Timer1 Prescaler ............................................................................................................................................12-9
Initialization ...................................................................................................................................................12-10
Design Tips  ..................................................................................................................................................12-12
Related Application Notes ............................................................................................................................12-13
Revision History  ...........................................................................................................................................12-14
 
SECTION 13. TIMER2  13-1
 
Introduction .....................................................................................................................................................13-2
Control Register  .............................................................................................................................................13-3
Timer Clock Source ........................................................................................................................................13-4
Timer (TMR2) and Period (PR2) Registers ....................................................................................................13-4
TMR2 Match Output .......................................................................................................................................13-4
Clearing the Timer2 Prescaler and Postscaler ...............................................................................................13-4
Sleep Operation  .............................................................................................................................................13-4
Initialization .....................................................................................................................................................13-5
Design Tips  ....................................................................................................................................................13-6
Related Application Notes ..............................................................................................................................13-7
Revision History  .............................................................................................................................................13-8
 
SECTION 14. COMPARE/CAPTURE/PWM (CCP)  14-1
 
Introduction .....................................................................................................................................................14-2
Control Register  .............................................................................................................................................14-3
Capture Mode .................................................................................................................................................14-4
Compare Mode ...............................................................................................................................................14-6
PWM Mode .....................................................................................................................................................14-8
Initialization ...................................................................................................................................................14-12
Design Tips  ..................................................................................................................................................14-15
Related Application Notes ............................................................................................................................14-17
Revision History  ...........................................................................................................................................14-18
 
Table of Contents

 
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PAGE
 
SECTION 15. SYNCHRONOUS SERIAL PORT (SSP)  15-1
 
Introduction .....................................................................................................................................................15-2
Control Registers ............................................................................................................................................15-3
SPI Mode ........................................................................................................................................................15-6
SSP I
 
2
 
C Operation .......................................................................................................................................15-16
Initialization ...................................................................................................................................................15-26
Design Tips  ..................................................................................................................................................15-28
Related Application Notes ............................................................................................................................15-29
Revision History  ...........................................................................................................................................15-30
 
SECTION 16. BASIC SYCHRONOUS SERIAL PORT (BSSP)  16-1
 
Introduction .....................................................................................................................................................16-2
Control Registers ............................................................................................................................................16-3
SPI Mode ........................................................................................................................................................16-6
SSP I
 
2
 
C Operation .......................................................................................................................................16-15
Initialization ...................................................................................................................................................16-23
Design Tips  ..................................................................................................................................................16-24
Related Application Notes ............................................................................................................................16-25
Revision History  ...........................................................................................................................................16-26
 
SECTION 17. MASTER SYNCHRONOUS SERIAL PORT (MSSP)  17-1
 
Introduction .....................................................................................................................................................17-2
Control Register  .............................................................................................................................................17-4
SPI Mode ........................................................................................................................................................17-9
SSP I
 
2
 
C™ Operation ....................................................................................................................................17-18
Connection Considerations for I
 
2
 
C Bus ........................................................................................................17-56
Initialization ...................................................................................................................................................17-57
Design Tips  ..................................................................................................................................................17-58
Related Application Notes ............................................................................................................................17-59
Revision History  ...........................................................................................................................................17-60
 
SECTION 18. USART  18-1
 
Introduction .....................................................................................................................................................18-2
Control Registers ............................................................................................................................................18-3
USART Baud Rate Generator (BRG) .............................................................................................................18-5
USART Asynchronous Mode  .........................................................................................................................18-8
USART Synchronous Master Mode .............................................................................................................18-15
USART Synchronous Slave Mode ...............................................................................................................18-19
Initialization ...................................................................................................................................................18-21
Design Tips  ..................................................................................................................................................18-22
Related Application Notes ............................................................................................................................18-23
Revision History  ...........................................................................................................................................18-24
 
Table of Contents

 
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PAGE
 
SECTION 19. VOLTAGE REFERENCE  19-1
 
Introduction .....................................................................................................................................................19-2
Control Register  .............................................................................................................................................19-3
Configuring the Voltage Reference ................................................................................................................19-4
Voltage Reference Accuracy/Error .................................................................................................................19-5
Operation During Sleep ..................................................................................................................................19-5
Effects of a Reset ...........................................................................................................................................19-5
Connection Considerations ............................................................................................................................19-6
Initialization .....................................................................................................................................................19-7
Design Tips  ....................................................................................................................................................19-8
Related Application Notes ..............................................................................................................................19-9
Revision History  ...........................................................................................................................................19-10
 
SECTION 20. COMPARATOR  20-1
 
Introduction .....................................................................................................................................................20-2
Control Register  .............................................................................................................................................20-3
Comparator Configuration ..............................................................................................................................20-4
Comparator Operation ....................................................................................................................................20-6
Comparator Reference ...................................................................................................................................20-6
Comparator Response Time ..........................................................................................................................20-8
Comparator Outputs .......................................................................................................................................20-8
Comparator Interrupts ....................................................................................................................................20-9
Comparator Operation During SLEEP  ...........................................................................................................20-9
Effects of a RESET  ........................................................................................................................................20-9
Analog Input Connection Considerations .....................................................................................................20-10
Initialization ...................................................................................................................................................20-11
Design Tips  ..................................................................................................................................................20-12
Related Application Notes ............................................................................................................................20-13
Revision History  ...........................................................................................................................................20-14
 
SECTION 21. 8-BIT A/D CONVERTER  21-1
 
Introduction .....................................................................................................................................................21-2
Control Registers ............................................................................................................................................21-3
Operation ........................................................................................................................................................21-5
A/D Acquisition Requirements ........................................................................................................................21-6
Selecting the A/D Conversion Clock  ..............................................................................................................21-8
Configuring Analog Port Pins .........................................................................................................................21-9
A/D Conversions  ..........................................................................................................................................21-10
A/D Operation During Sleep .........................................................................................................................21-12
A/D Accuracy/Error .......................................................................................................................................21-13
Effects of a RESET  ......................................................................................................................................21-13
Use of the CCP Trigger ................................................................................................................................21-14
Connection Considerations ..........................................................................................................................21-14
Transfer Function .........................................................................................................................................21-14
Initialization ...................................................................................................................................................21-15
Design Tips  ..................................................................................................................................................21-16
Related Application Notes ............................................................................................................................21-17
Revision History  ...........................................................................................................................................21-18
 
Table of Contents

 
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PAGE
 
SECTION 22. BASIC 8-BIT A/D CONVERTER  22-1
 
Introduction .....................................................................................................................................................22-2
Control Registers ............................................................................................................................................22-3
A/D Acquisition Requirements ........................................................................................................................22-6
Selecting the A/D Conversion Clock  ..............................................................................................................22-8
Configuring Analog Port Pins .......................................................................................................................22-10
A/D Conversions  ..........................................................................................................................................22-11
A/D Operation During Sleep .........................................................................................................................22-14
A/D Accuracy/Error .......................................................................................................................................22-15
Effects of a RESET  ......................................................................................................................................22-16
Connection Considerations ..........................................................................................................................22-16
Transfer Function .........................................................................................................................................22-16
Initialization ...................................................................................................................................................22-17
Design Tips  ..................................................................................................................................................22-18
Related Application Notes ............................................................................................................................22-19
Revision History  ...........................................................................................................................................22-20
 
SECTION 23. 10-BIT A/D CONVERTER  23-1
 
Introduction .....................................................................................................................................................23-2
Control Register  .............................................................................................................................................23-3
Operation ........................................................................................................................................................23-5
A/D Acquisition Requirements ........................................................................................................................23-6
Selecting the A/D Conversion Clock  ..............................................................................................................23-8
Configuring Analog Port Pins .........................................................................................................................23-9
A/D Conversions  ..........................................................................................................................................23-10
Operation During Sleep ................................................................................................................................23-14
Effects of a Reset .........................................................................................................................................23-14
A/D Accuracy/Error .......................................................................................................................................23-15
Connection Considerations ..........................................................................................................................23-16
Transfer Function .........................................................................................................................................23-16
Initialization ...................................................................................................................................................23-17
Design Tips  ..................................................................................................................................................23-18
Related Application Notes ............................................................................................................................23-19
Revision History  ...........................................................................................................................................23-20
 
SECTION 24. SLOPE A/D  24-1
 
Introduction .....................................................................................................................................................24-2
Control Registers ............................................................................................................................................24-3
Conversion Process .......................................................................................................................................24-6
Other Analog Modules ..................................................................................................................................24-12
Calibration Parameters .................................................................................................................................24-13
Design Tips  ..................................................................................................................................................24-14
Related Application Notes ............................................................................................................................24-15
Revision History  ...........................................................................................................................................24-16
 
Table of Contents

 
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PAGE
 
SECTION 25. LCD  25-1
 
Introduction .....................................................................................................................................................25-2
Control Register  .............................................................................................................................................25-3
LCD Timing  ....................................................................................................................................................25-6
LCD Interrupts ..............................................................................................................................................25-12
Pixel Control .................................................................................................................................................25-13
Voltage Generation  ......................................................................................................................................25-15
Operation During Sleep ................................................................................................................................25-16
Effects of a Reset .........................................................................................................................................25-17
Configuring the LCD Module ........................................................................................................................25-17
Discrimination Ratio  .....................................................................................................................................25-18
LCD Voltage Generation ..............................................................................................................................25-20
Contrast ........................................................................................................................................................25-22
LCD Glass ....................................................................................................................................................25-22
Initialization ...................................................................................................................................................25-23
Design Tips  ..................................................................................................................................................25-24
Related Application Notes ............................................................................................................................25-25
Revision History  ...........................................................................................................................................25-26
 
SECTION 26. WATCHDOG TIMER AND SLEEP MODE  26-1
 
Introduction .....................................................................................................................................................26-2
Control Register  .............................................................................................................................................26-3
Watchdog Timer (WDT) Operation .................................................................................................................26-4
SLEEP (Power-Down) Mode ..........................................................................................................................26-7
Initialization .....................................................................................................................................................26-9
Design Tips  ..................................................................................................................................................26-10
Related Application Notes ............................................................................................................................26-11
Revision History  ...........................................................................................................................................26-12
 
SECTION 27. DEVICE CONFIGURATION BITS  27-1
 
Introduction .....................................................................................................................................................27-2
Configuration Word Bits  .................................................................................................................................27-4
Program Verification/Code Protection ............................................................................................................27-8
ID Locations  ...................................................................................................................................................27-9
Design Tips  ..................................................................................................................................................27-10
Related Application Notes ............................................................................................................................27-11
Revision History  ...........................................................................................................................................27-12
 
SECTION 28. IN-CIRCUIT SERIAL PROGRAMMING™  28-1
 
Introduction .....................................................................................................................................................28-2
Entering In-Circuit Serial Programming Mode ................................................................................................28-3
Application Circuit ...........................................................................................................................................28-4
Programmer ...................................................................................................................................................28-6
Programming Environment .............................................................................................................................28-6
Other Benefits  ................................................................................................................................................28-7
Field Programming of PICmicro OTP MCUs ..................................................................................................28-8
Field Programming of FLASH PICmicros .....................................................................................................28-10
Design Tips  ..................................................................................................................................................28-12
Related Application Notes ............................................................................................................................28-13
Revision History  ...........................................................................................................................................28-14
 
Table of Contents

 
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PAGE
 
SECTION 29. INSTRUCTION SET  29-1
 
Introduction .....................................................................................................................................................29-2
Instruction Formats .........................................................................................................................................29-4
Special Function Registers as Source/Destination  ........................................................................................29-6
Q Cycle Activity ..............................................................................................................................................29-7
Instruction Descriptions ..................................................................................................................................29-8
Design Tips  ..................................................................................................................................................29-45
Related Application Notes ............................................................................................................................29-47
Revision History  ...........................................................................................................................................29-48
 
SECTION 30. ELECTRICAL SPECIFICATIONS  30-1
 
Introduction .....................................................................................................................................................30-2
Absolute Maximums .......................................................................................................................................30-3
Device Selection Table ...................................................................................................................................30-4
Device Voltage Specifications ........................................................................................................................30-5
Device Current Specifications ........................................................................................................................30-6
Input Threshold Levels ...................................................................................................................................30-9
I/O Current Specifications  ............................................................................................................................30-10
Output Drive Levels ......................................................................................................................................30-11
I/O Capacitive Loading .................................................................................................................................30-12
Data EEPROM / Flash  .................................................................................................................................30-13
LCD ..............................................................................................................................................................30-14
Comparators and Voltage Reference ...........................................................................................................30-15
Timing Parameter Symbology ......................................................................................................................30-16
Example External Clock Timing Waveforms and Requirements ..................................................................30-17
Example Power-up and Reset Timing Waveforms and Requirements ........................................................30-19
Example Timer0 and Timer1 Timing Waveforms and Requirements ...........................................................30-20
Example CCP Timing Waveforms and Requirements  .................................................................................30-21
Example Parallel Slave Port (PSP) Timing Waveforms and Requirements .................................................30-22
Example SSP and Master SSP SPI Mode Timing Waveforms and Requirements ......................................30-23
Example SSP I
 
2
 
C Mode Timing Waveforms and Requirements ..................................................................30-27
Example Master SSP I
 
2
 
C Mode Timing Waveforms and Requirements ......................................................30-30
Example USART/SCI Timing Waveforms and Requirements ......................................................................30-32
Example 8-bit A/D Timing Waveforms and Requirements ...........................................................................30-34
Example 10-bit A/D Timing Waveforms and Requirements .........................................................................30-36
Example Slope A/D Timing Waveforms and Requirements .........................................................................30-38
Example LCD Timing Waveforms and Requirements ..................................................................................30-40
Related Application Notes ............................................................................................................................30-41
Revision History  ...........................................................................................................................................30-42
 
SECTION 31. DEVICE CHARACTERISTICS  31-1
 
Introduction .....................................................................................................................................................31-2
Characterization vs. Electrical Specification ...................................................................................................31-2
DC and AC Characteristics Graphs and Tables .............................................................................................31-2
Revision History  ...........................................................................................................................................31-22
 
Table of Contents

 
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SECTION 32. DEVELOPMENT TOOLS  32-1
 
Introduction .....................................................................................................................................................32-2
The Integrated Development Environment (IDE) ...........................................................................................32-3
MPLAB Software Language Support  .............................................................................................................32-6
MPLAB-SIM Simulator Software ....................................................................................................................32-8
MPLAB Emulator Hardware Support ..............................................................................................................32-9
MPLAB Programmer Support .......................................................................................................................32-10
Supplemental Tools ......................................................................................................................................32-11
Development Boards ....................................................................................................................................32-12
Development Tools for Other Microchip Products ........................................................................................32-14
Related Application Notes ............................................................................................................................32-15
Revision History  ...........................................................................................................................................32-16
 
SECTION 33. CODE DEVELOPMENT  33-1
 
Revision History  .............................................................................................................................................33-2
 
SECTION 34. APPENDIX  34-1
 
I
 
2
 
C
 

 
 Overview  ...............................................................................................................................................34-2
List of LCD Glass Manufacturers ................................................................................................................. 34-11
Device Enhancement ...................................................................................................................................34-13
Revision History ........................................................................................................................................... 34-19
 
SECTION 35. GLOSSARY  35-1
 
Revision History  ...........................................................................................................................................35-14
 
Table of Contents

 

 
 1997 Microchip Technology Inc.   DS31001A page 1-1
 
Introduction
 
1
 
M
 
Section 1. Introduction
 
HIGHLIGHTS
 
This section of the manual contains the following major topics:
1.1 Introduction....................................................................................................................1-2
1.2 Manual Objective ...........................................................................................................1-3
1.3 Device Structure ............................................................................................................1-4
1.4 Development Support....................................................................................................1-6
1.5 De vice V arieties..............................................................................................................1-7
1.6 Style and Symbol Conventions....................................................................................1-12
1.7 Related Documents .....................................................................................................1-14
1.8 Related Application Notes............................................................................................1-17
1.9 Revision History...........................................................................................................1-18

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-2



1997 Microchip Technology Inc.

1.1 Introduction

Microchip is the Embedded Control Solutions Company



. The company’s focus is on products

that meet the needs of the embedded control market. We are a leading supplier of:

• 8-bit General Purpose Microcontrollers (PICmicro™ MCUs)

• Speciality and standard non-volatile memory devices

• Security devices (K

OQ®

)

• Application speciﬁc standard products

Please request a Microchip Product Line Card f or a listing of all the interesting products that we

hav e to off er. This literature can be obtained from your local sales ofﬁce , or downloaded from the

Microchip web site (www.microchip.com).

In the past, 8-bit MCU users were ﬁx ed on the traditional MCU model for production, a R OM device

was required. Microchip has been the leader in changing this perception by showing that OTP

de vices can give a better lifetime product cost compared to ROM versions .

Microchip has a strength is in EPROM technology. That made it the memory technology of choice

for the PICmicro MCU’s program memory. Microchip has minimized the cost difference between

EPROM and ROM memory technology, and therefore Microchip can pass these beneﬁts onto our

customers. This is not true f or other MCU vendors, and is seen in the price diff erence between their

EPROM and ROM versions .

The growth of Microchip’s 8-bit MCU market share is a testament to the PICmicro MCUs ability to

meet the needs of many. This growth has made the PICmicro architecture one of the top three

architectures av ailab le in the gener al market today. This g rowth w as fueled b y the Microchip vision

of the beneﬁts of a low cost OTP solution. Some of the beneﬁts for the customer include:

• Quick time to market

• Allows code changes to product, during production run

• No Non-Recurring Engineering (NRE) charges f or Mask Revisions

• Ability to easily serialize the product

• Ability to store calibration data, without additional hardware

• Better able to maximize PICmicro MCU inventory

• Less risk, since the same device is used f or development as well as for production.

Microchip’ s PICmicro 8-bit MCUs off er a price/performance ratio that allows them to be considered

for any traditional 8-bit MCU application as well as some traditional 4-bit applications (Base-Line

f amily), dedicated logic replacement and lo w-end DSP applications (High-End family). These fea-

tures and price-performance mix make PICmicro MCUs an attractive solution for most applications.

 1997 Microchip Technology Inc. DS31001A-page 1-3

Section 1. Introduction

Introduction

1.2 Manual Objective

PICmicro devices are grouped by the size of their Instruction Word. The three current PICmicro

families are:

1. Base-Line: 12-bit Instruction Word length

2. Mid-Range: 14-bit Instruction Word length

3. High-End: 16-bit Instruction Word length

This manual focuses on the Mid-Range devices, which are also referred to as the PIC16CXXX

MCU family.

The operation of the PIC16CXXX MCU f amily architecture and peripheral modules is explained,

but does not co ver the speciﬁcs of each de vice. Theref ore, it is not intended to replace the de vice

data sheets, but complement them. In other words, this guide supplies the general details and

operation of the PICmicro architecture and peripheral modules, while the data sheet s give spe-

ciﬁc details such as device memory mapping.

Initialization e xamples are given throughout this man ual. These examples sometimes need to be

written as device speciﬁc as opposed to family generic, though they are valid for most other

devices. Some modiﬁcations may be required f or devices with v ariations in register ﬁle mappings.

Note: The ﬁrst few Mid-Range devices have minor device variations when compared to

this general description. We have tried to descr ibe these variations throughout this

manual. Please refer to the speciﬁc device data sheet for complete infor mation on

the device.

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-4  1997 Microchip Technology Inc.

1.3 Device Structure

Each part of a device can be placed into one of three groups:

1. Core

2. Peripherals

3. Special Features

1.3.1 The Core

The core pertains to the basic features that are required to make the device operate. These

include:

1. Device Oscillator Revision “DS31002A”

2. Reset logic Revision “DS31003A”

3. CPU (Central Processing Unit) operation Revision “DS31005A”

4. ALU (Arithmetic Logical Unit) operation Revision “DS31005A”

5. Device memory map organization Revision “DS31006A”

6. Interrupt operation Revision “DS31008A”

7. Instruction set Revision “DS31029A”

1.3.2 Peripherals

P eripherals are the features that add a diff erentiation from a microprocessor . These ease in inter-

facing to the external world (such as general purpose I/O, LCD drivers, A/D inputs, and PWM

outputs), and internal tasks such as keeping different time bases (such as timers). The peripher-

als that are discussed are:

1. General purpose I/O Revision “DS31009A”

2. Timer0 Re vision “DS31011A”

3. Timer1 Re vision “DS31012A”

4. Timer2 Re vision “DS31013A”

5. Capture, Compare, and PWM (CCP) Revision “DS31014A”

6. Synchronous Serial Port (SSP) Revision “DS31015A”

7. Basic Synchronous Serial Port (SSP) Revision “DS31016A”

8. Master Synchronous Serial Port (MSSP) Revision “DS31017A”

9. USART (SCI) Revision “DS31018A”

10. Voltage References Revision “DS31019A”

11. Comparators Re vision “DS31020A”

12. 8-bit Analog to Digital (A/D) Revision “DS31021A”

13. Basic 8-bit Analog to Digital (A/D) Revision “DS31022A”

14. 10-bit Analog to Digital (A/D) Revision “DS31023A”

15. Slope Analog to Digital (A/D) w/ Thermister Revision “DS31024A”

16. Liquid Crystal Display (LCD) Drivers Revision “DS31025A”

17. Parallel Slave Port (PSP) Revision “DS31010A”

 1997 Microchip Technology Inc. DS31001A-page 1-5

Section 1. Introduction

Introduction

1.3.3 Special Features

Special features are the unique features that help to do one or more of the following things:

• Decrease system cost

• Increase system reliability

• Increase design ﬂexibility

The Mid-Range PICmicro MCUs off er sev eral f eatures that help achiev e these goals. The special

features discussed are:

1. Device Conﬁguration bits Revision “DS31027A”

2. On-chip Power-on Reset (POR) Revision “DS31003A”

3. Brown-out Reset (BOR) logic Revision “DS31003A”

4. W atchdog Timer Re vision “DS31026A”

5. Low power mode (Sleep) Revision “DS31026A”

6. Internal RC device oscillator Revision “DS31002A”

7. In-Circuit Serial Programming™ (ICSP™) Revision “DS31028A”

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-6  1997 Microchip Technology Inc.

1.4 Development Support

Microchip offers a wide range of development tools that allow users to efﬁciently develop and

debug application code . Microchip’ s de v elopment tools can be brok en down into four categories:

1. Code generation

2. Software debug

3. Device programmer

4. Product evaluation boards

All tools developed by Microchip operate under the MPLAB™ Integrated Development Environ-

ment (IDE), while some third party tools may not. The code generation tools include:

• MPASM

• MPLAB-C

• MP-DriveWay™

These software de v elopment programs include de vice header ﬁles . Each header ﬁle deﬁnes the

the header ﬁles eases code migration, and reduces the tediousness of memorizing a register’s

address or a bit’s position in a register.

Tools which ease in debugging software are:

• PICMASTER® In-Circuit Emulator

• ICEPIC In-Circuit Emulator

• MPLAB-SIM Software Simulator

After generating and deb ugging the application software, the de vice will need to be programmed.

Microchip offers two levels of programmers:

1. PICSTART Plus programmer

2. PROMATE II programmer

Demonstration boards allow the developer of software code to evaluate the capability and suit-

ability of the device to the application. The demo boards offered are:

• PICDEM-1

• PICDEM-2

• PICDEM-3

• PICDEM-14A

A full description of each of Microchip’s development tools is discussed in the “Development

Tools” section. As new tools are developed, product briefs and user guides may be obtained

from the Microchip web site (www.microchip.com) or from your local Microchip Sales Ofﬁce.

Code de velopment recommendations and techniques are provided in the “Code De velopment”

section.

Microchip offers other reference tools to speed the development cycle. These include:

• Application Notes

• Reference Designs

• Microchip web site

• Microchip BBS

• Local Sales Ofﬁces with Field Application Support

• Corporate Support Line

Additional avenues of assistance can be found in many Web User Groups including the MIT

reﬂector PIClist. The Microchip web site lists other sites that may be useful references.

Note: Microchip strongly recommends that the supplied header ﬁles be used in the source

code of your program. This eases code migration as well as increases the quality

and depth of the technical support that Microchip can offer.

 1997 Microchip Technology Inc. DS31001A-page 1-7

Section 1. Introduction

Introduction

1.5 Device Varieties

Once the functional requirements of the device are speciﬁed, some other decisions need to be

made. These include:

• Memory technology

• Operating voltage

• Operating temperature range

• Operating frequency

• Packaging

Microchip has a large number of options and option combinations, one of which should fulﬁll y our

requirements.

1.5.1 Memory Varieties

Memor y technology has no effect on the logical operation of a device. Due to the different pro-

cessing steps required, some electrical characteristics may v ary between devices with the same

f eature set/pinout but with diff erent memory technologies. An e xample is the electrical character-

istic VIL (Input Low Voltage), which may ha ve some diff erence between a typical EPROM device

and a typical ROM device.

Each device has a variety of frequency ranges and packaging options available. Depending on

application and production requirements, the proper device options can be identiﬁed using the

inf ormation in the Product Selection System section at the end of each data sheet. When placing

orders, please use the “Product Identiﬁcation System” at the back of the data sheet to specify the

correct part number.

When discussing the functionality of the device, the memor y technology and the voltage range

do not matter. Microchip offers three program memory types. The memor y type is designated in

the part number by the ﬁrst letter(s) after the family afﬁliation designators.

1. C, as in PIC16CXXX. These devices have EPROM type memory.

2. CR, as in PIC16CRXXX. These devices have ROM type memory.

3. F, as in PIC16FXXX. These devices have Flash type memory.

1.5.1.1 EPROM

Microchip f ocuses on Erasable Programmab le Read Only Memory (EPROM) technology to giv e

the customers ﬂexibility throughout their entire design cycle. With this technology Microchip

offers various packaging options as well as services.

1.5.1.2 Read Only Memory (ROM) Devices

Microchip offers a masked Read Only Memory (ROM) version of several of the highest volume

parts, thus giving customers a lower cost option for high volume, mature products.

ROM devices do not allow serialization information in the program memory space.

For information on submitting ROM code, please contact your local Microchip sales ofﬁce.

1.5.1.3 Flash Memory Devices

These devices are electr ically erasable, and can therefore be offered in a low cost plastic pack-

age. Being electrically erasable, these devices can be both erased and reprogrammed without

removal from the circuit. A device will have the same speciﬁcations whether it is used for proto-

type development, pilot programs, or production.

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-8  1997 Microchip Technology Inc.

1.5.2 Operating Voltage Range Options

All Mid-Range PICmicro™ MCUs operate over the standard voltage range. Devices are also

off ered which operate ov er an e xtended v oltage range (and reduced frequency range). Table 1-1

shows all possib le memory types and voltage range designators f or the PIC16CXXX MCU family.

The designators are in bold typeface.

Table 1-1: Device Memory Type and Voltage Range Designators

As you can see in Table 1-2, Microchip speciﬁcations its extended range devices at a more con-

ser vative voltage range until device characterization has ensured they will be able to meet the

goal of their ﬁnal design speciﬁcations.

Table 1-2: Typical Voltage Ranges for Each Device Type

Memory Type Voltage Range

Standard Extended

EPROM PIC16CXXX PIC16LCXXX

ROM PIC16CRXXX PIC16LCRXXX

Flash PIC16FXXX PIC16LFXXX

Note:Not all memory types may be available for a particular device.

T ypical V oltage Range (1) EPROM ROM Flash

Standard C4.5 - 6.0V CR 4.5 - 6.0V F4.5 - 6.0V

Extended Before device characterization LC 3.0 - 6.0V LCR 3.0 - 6.0V LF 3.0 - 6.0V

Final speciﬁcation (2) LC 2.5 - 6.0V LCR 2.5 - 6.0V LF 2.0 - 6.0V

Note 1: De vices fabricated in Microchip’s 120K Process Technology will have a maximum limit on VDD of 5.5V. New

device data sheets will specify Microchip’s technology designation

2: This voltage range depends on the results of device characterization.

 1997 Microchip Technology Inc. DS31001A-page 1-9

Section 1. Introduction

Introduction

1.5.3 Packaging V arieties

Depending on the development phase of your project, one of three package types would be used:

The ﬁrst is a de vice with an erasure window . Typically these are f ound in packages with a ceramic

body. These devices are used for the development phase, since the device’s program memory

can be erased and reprogrammed many times.

The second package type is a lo w cost plastic pac kage . This package type is used in production

where device cost is to be kept to a minimum.

Lastly, there is the DIE option. A DIE is an unpackaged device that has been tested. DIEs are

used in low cost designs and designs where board space is at a minimum. Table 1-3 shows a

quick summary of this.

Table 1-3: Typical Package Uses

Package Type Typical Usage

Windowed Development Mode

Plastic Production

DIE Special Applications, such as those which require minimum board space

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-10  1997 Microchip Technology Inc.

1.5.3.4 UV Erasable Devices

The UV erasable version of EPROM program memor y devices is optimal for prototype develop-

ment and pilot programs.

These de vices can be erased and reprogrammed to any of the conﬁgur ation modes. Third party

programmers are also available; refer to Microchip’s

Third Party Guide

(DS00104) for a list of

sources.

The amount of time required to completely erase a UV erasable device depends on: the wave-

length of the light, its intensity, distance from UV source, the process technology of the device

(how small are the memory cells).

1.5.3.5 One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers expecting code changes and

updates.

OTP devices, packaged in plastic packages, permit the user to program them once. In addition

to the program and data EPROM memories, the conﬁguration bits must be programmed.

1.5.3.6 Flash Devices

A Flash de vice allo ws its memory to be changed by an electric charge. This means that the sys-

tem can be designed so that programming may be performed in-circuit. Since no window is

required, the lower cost plastic packages can used for these devices.

1.5.3.7 EEPROM Devices

An EEPROM device allows its memor y to be erased by an electric charge. This means that the

system can be designed so that erasure and reprogr amming may be performed in-circuit. Since

no window is required, the lower cost plastic packages can used for these devices.

Note: Fluorescent lights and sunlight both emit ultra violet light at the er asure wav elength.

Leaving a UV erasable device’s window uncovered could cause, over time, the

devices memory cells to become erased. The erasure time for a ﬂuorescent light is

about three years , while sunlight requires only about one week. To pre vent the mem-

or y cells from losing data, an opaque label should be placed over the erasure win-

dow.

 1997 Microchip Technology Inc. DS31001A-page 1-11

Section 1. Introduction

Introduction

1.5.3.8 ROM Devices

ROM devices have their program memory ﬁx ed at the time of the silicon manufacture. Since the

program memory cannot be changed, the device can be housed in the lower cost plastic pack-

age.

1.5.3.9 DIE

The DIE option allows the board siz e to become as small as physically possible . The DIE Support

document (DS30258) explains general information about using and designing with DIE. There

are also individual speciﬁcation sheets that detail DIE speciﬁc infor mation. Manufacturing with

DIE requires special knowledge and equipment. This means that the number of manufacturing

houses that support DIE will be limited. If y ou decide to use the DIE option, please research y our

manufacturing sites to ensure that they will be able to meet the specializ ed requirements of DIE

use.

1.5.3.10 Specialized Services

F or OTP customers with established code, Microchip offers two specialized services. These two

services, Quick Turn Production Programming and Serialized Quick Tur n Production Program-

ming, that allow customers to shorten their manufacturing cycle time.

1.5.3.11 Quick Turn Production (QTP) Programming

Microchip offers this programming service for factory production orders. This service is made

av ailable for users who choose not to program a medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to the OTP devices but with all EPROM loca-

tions and conﬁguration options already programmed by the factor y. Certain code and prototype

veriﬁcation procedures apply before production shipments are available. Please contact your

local Microchip sales ofﬁce for more details.

1.5.3.12 Serialized Quick Turn Production (SQTPSM) Programming

Microchip offers a this unique programming service where a few user-deﬁned locations in each

device are programmed with different serial numbers. The serial numbers may be random,

pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an

entry-code, password or ID number.

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-12  1997 Microchip Technology Inc.

1.6 Style and Symbol Conventions

Throughout this document, certain style and f ont format changes are used. Most f ormat changes

imply a distinction should be made for the emphasized text. The MCU industry has many symbols

and non-conventional word deﬁnitions/abbreviations. Table 1-4 provides a description for many

of the conv entions contained in this document. A glossary is provided in the “Glossary” section,

which contains more word and abbreviation deﬁnitions that are used throughout this manual.

1.6.1 Document Conventions

Table 1-4 deﬁnes some of the symbols and terms used throughout this manual.

Table 1-4: Document Conventions

Symbol or Term Description

set To force a bit/register to a value of logic ‘1’.

clear To force a bit/register to a value of logic ‘0’.

reset 1) To force a register/bit to its default state.

2) A condition in which the device places itself after a device reset

occurs. Some bits will be forced to ‘0’ (such as interrupt enable bits),

while others will be forced to ‘1’ (such as the I/O data direction bits).

0xnn or nnh Designates the number ‘nn’ in the hexadecimal number system. These

conventions are used in the code examples.

B’bbbbbbbb’ Designates the number ‘bbbbbbbb’ in the binary number system. This

convention is used in the text and in ﬁgures and tables.

R-M-W Read - Modify - Write. This is when a register or port is read, then the

value is modiﬁed, and that value is then written back to the register or

port. This action can occur from a single instruction (such as bit set ﬁle,

BSF) or a sequence of instructions.

: (colon) Used to specify a range, or the concatenation of registers / bits / pins.

An e xample is TMR1H:TMR1L is the concatenation of two 8-bit registers

to form a 16-bit timer value, while SSPM3:SSPM0 are 4-bits used to

specify the mode of the SSP module. Concatenation order (left-right)

usually speciﬁes a positional relationship (MSb to LSb, higher to lower).

< > Speciﬁes bit(s) locations in a particular register.

An e xample is SSPCON<SSPM3:SSPM0> (or SSPCON<3:0>) speciﬁes

the register and associated bits or bit positions.

Courier Font Used f or code examples , binary numbers, and f or Instruction Mnemonics

in the text.

Times Font Used for equations and variables.

Times, Bold Font,

Italics

Used in explanatory text for items called out from a graphic/equa-

tion/example.

Note Notes present information that we wish to reemphasize, either to help

you avoid a common pitfall, or make you aware of operating differences

between some de vice f amily members . A Note is alwa ys in a shaded box

(as below), unless used in a table, where it is at the bottom of the table

(as in this table).

Note: This is a note in a note box.

Caution(1) A caution statement describes a situation that could potentially damage

software or equipment.

Warning(1) A warning statement describes a situation that could potentially cause

personnel harm.

Note 1: The inf ormation in a caution or a warning is provided for y our protection. Please read

each caution and warning carefully.

 1997 Microchip Technology Inc. DS31001A-page 1-13

Section 1. Introduction

Introduction

1.6.2 Electrical Speciﬁcations

Throughout this manual there will be ref erences to electrical speciﬁcation parameter numbers . A

parameter number represents a unique set of characteristics and conditions that is consistent

between every data sheet, though the actual parameter value may vary from device to device.

The “Electrical Speciﬁcations” section sho ws all the speciﬁcations that are documented f or all

devices. No one device has all these speciﬁcations. This section is intended to let you know the

types of parameters that Microchip speciﬁes. The value of each speciﬁcation is device depen-

dent, though we strongly attempt to keep them consistent across all devices.

Table 1-5: Electrical Speciﬁcation Parameter Numbering Convention

Parameter

Number

Format Comment

Dxxx DC Speciﬁcation

Axxx DC Speciﬁcation for Analog peripherals

xxx Timing (AC) Speciﬁcation

PDxxx Device Programming DC Speciﬁcation

Pxxx Device Programming Timing (AC) Speciﬁcation

Legend: xxx: represents a number.

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-14  1997 Microchip Technology Inc.

1.7 Related Documents

Microchip , as well as other sources, off ers additional documentation which can aid in y our de v el-

opment with PICmicro MCUs. These lists contain the most common documentation but other

documents ma y also be a v ailab le . Please check the Microchip w eb site (www.micr ochip.com) f or

the latest published technical documentation.

1.7.1 Microchip Documentation

The following documents are available from Microchip. Many of these documents provide appli-

cation speciﬁc infor mation that give actual examples of using, programming and designing with

PICmicro MCUs.

1. MPASM User’s Guide (DS33014)

This document explains how to use Microchip’s MPASM assembler.

2. MPLAB™-C Compiler User’s Guide (DS51014)

This document explains how to use Microchip’s MPLAB-C C compiler.

3. MPLAB User’s Guide (DS51025)

This document e xplains how to use Microchip’s MPLAB Integrated De velopment En viron-

ment.

4. MPLAB Editor User’s Guide (DS30420)

This document explains how to use Microchip’s MPLAB built-in editor.

5. PICMASTER® User’s Guide (DS30421)

This document explains how to use Microchip’s PICMASTER In-Circuit Emulator.

6. MPSIM User’s Guide (DS30027)

This document explains how to use Microchip’s MPLAB Simulator.

7. PRO MATE® User’s Guide (DS30082)

This document explains how to use Microchip’s PRO MATE universal programmer.

8. PICSTART®-Plus User’s Guide (DS51028)

This document explains how to use Microchip’s PICSTART-Plus low-cost universal pro-

grammer.

fuzzy

TECH®-MP User’s Guide (DS30389)

This document explains how to use the

fuzzy

TECH-MP fuzzy logic code generator.

10. MP-DriveWay™ User’s Guide (DS51027)

This document explains how to use the MP-DriveWay code generator.

11.

fuzzy

TECH-MP Fuzzy Logic Handbook (DS30238)

This document explains the basics of

fuzzy

TECH-MP fuzzy.

12. Embedded Control Handbook Volume I (DS00092)

This document contains a plethora of application notes. This is useful for insight on how

to use the device (or par ts of it) as well as getting star ted on your par ticular application

due to the availability of extensive code ﬁles.

13. Embedded Control Handbook Volume II (DS00167)

This document contains the Math Libraries for PICmicro MCUs.

14. In-Circuit Serial Programming Guide™ (DS30277)

This document discusses implementing In-Circuit Serial Programming.

15. PICDEM-1 User’s Guide (DS351079)

This document explains how to use Microchip’s PICDEM-1 demo board.

16. PICDEM-2 User’s Guide (DS30374)

This document explains how to use Microchip’s PICDEM-2 demo board.

17. PICDEM-3 User’s Guide (DS33015)

This document explains how to use Microchip’s PICDEM-3 demo board.

18. Third Party Guide (DS00104)

This document lists Microchip’s third parties, as well as various consultants.

19. DIE Support (DS30258)

This document gives information on using Microchip products in DIE form.

 1997 Microchip Technology Inc. DS31001A-page 1-15

Section 1. Introduction

Introduction

1.7.2 Third Party Documentation

There are several documents available from third party sources around the world. Microchip

does not review these documents for technical accuracy, however they may be a helpful source

for understanding the operation of Microchip MCU devices. This is not necessar ily a complete

list, but are the documents that w e were a ware of at the time of printing. For more inf ormation on

how to contact some of these sources, as well as any new sources that we become aware of,

please visit the Microchip web site.

DOCUMENT LANGUAGE

The PIC16C5X Microcontroller: A Practical Approach to

Embedded Control

Bill Rigby/ Terry Dalby, Tecksystems Inc.

0-9654740-0-3............................................................................................................English

Easy PIC'n

David Benson, Square 1 Electronics

0-9654162-0-8............................................................................................................English

A Beginners Guide to the Microchip PIC®

Nigel Gardner, Bluebird Electronics

1-899013-01-6............................................................................................................English

PIC Microcontroller Operation and Applications

DN de Beer, Cape Technikon.....................................................................................English

Digital Systems and Programmable Interface Controllers

WP Verburg, Pretoria Technikon ................................................................................English

Mikroprozessor PIC16C5X

Michael Rose, Hüthig

3-7785-2169-1...........................................................................................................German

Mikroprozessor PIC17C42

Michael Rose, Hüthig

3-7785-2170-5...........................................................................................................German

Les Microcontrolleurs PIC et mise en oeuvre

Christian Tavernier , Dunod

2-10-002647-X............................................................................................................French

Micontrolleurs PIC a structure RISC

C.F. Urbain, Publitronic

2-86661-058-X............................................................................................................French

New Possibilities with the Microchip PIC

RIGA .........................................................................................................................Russian

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-16  1997 Microchip Technology Inc.

DOCUMENT LANGUAGE

PIC16C5X/71/84 Development and Design, Part 1

United Tech Electronic Co. Ltd

957-21-0807-7.......................................................................................................... Chinese

PIC16C5X/71/84 Development and Design, Part 2

United Tech Electronic Co. Ltd

957-21-1152-3.......................................................................................................... Chinese

PIC16C5X/71/84 Development and Design, Part 3

United Tech Electronic Co. Ltd

957-21-1187-6.......................................................................................................... Chinese

PIC16C5X/71/84 Development and Design, Part 4

United Tech Electronic Co. Ltd

957-21-1251-1.......................................................................................................... Chinese

PIC16C5X/71/84 Development and Design, Part 5

United Tech Electronic Co. Ltd

957-21-1257-0.......................................................................................................... Chinese

PIC16C84 MCU Architecture and Software Development

ICC Company

957-8716-79-6.......................................................................................................... Chinese

 1997 Microchip Technology Inc. DS31001A-page 1-17

Section 1. Introduction

Introduction

1.8 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally f or the PIC16CXXX Mid-Range MCU family (that is the y

may be wr itten for the Base-Line, or the High-End families), but the concepts are pertinent, and

could be used (with modiﬁcation and possible limitations). The current application notes related

to an introduction to Microchip’s PICmicro MCUs are:

Title Application Note #

A Comparison of Low End 8-bit Microcontrollers AN520

PIC16C54A EMI Results AN577

Continuous Improvement AN503

Improving the Susceptibility of an Application to ESD AN595

Plastic Packaging and the Effects of Surface Mount Soldering Techniques AN598

PICmicro MID-RANGE MCU FAMILY

DS31001A-page 1-18  1997 Microchip Technology Inc.

1.9 Revision History

Revision A

This is the initial released revision of Microchip’s PICmicro MCUs Introduction.

 1997 Microchip Technology Inc.   DS31002A page 2-1
M
Oscillator
2
Section 2. Oscillator
HIGHLIGHTS
This section of the manual contains the following major topics:
2.1 Introduction....................................................................................................................2-2
2.2 Oscillator Conﬁgurations................................................................................................2-2
2.3 Crystal Oscillators / Ceramic Resonators......................................................................2-4
2.4 External RC Oscillator..................................................................................................2-12
2.5 Internal 4 MHz RC Oscillator .......................................................................................2-13
2.6 Effects of Sleep Mode on the On-chip Oscillator .........................................................2-17
2.7 Effects of Device Reset on the On-chip Oscillator.......................................................2-17
2.8 Design Tips..................................................................................................................2-18
2.9 Related Application Notes............................................................................................2-19
2.10 Revision History...........................................................................................................2-20

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-2  1997 Microchip Technology Inc.

2.1 Introduction

The internal oscillator circuit is used to generate the device clock. The device clock is required

for the device to execute instructions and for the peripherals to function. Four device clock peri-

ods generate one internal instruction clock (TCY) cycle.

There are up to eight diff erent modes which the oscillator ma y ha v e. There are two modes which

allow the selection of the internal RC oscillator clock out (CLKOUT) to be driv en on an I/O pin, or

allow that I/O pin to be used for a general purpose function. The oscillator mode is selected by

the de vice conﬁguration bits . The de vice conﬁgur ation bits are nonv olatile memory locations and

the operating mode is determined by the v alue written during de vice programming. The oscillator

modes are:

• LP Low Frequency (Power) Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resistor/Capacitor (same as EXTRC with CLKOUT)

• EXTRC External Resistor/Capacitor

• EXTRC External Resistor/Capacitor with CLKOUT

• INTRC Internal 4 MHz Resistor/Capacitor

• INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT

These oscillator options are made av ailab le to allow a single device type the ﬂexibility to ﬁt appli-

cations with different oscillator requirements. The RC oscillator option saves system cost while

the LP cr ystal option saves power. Conﬁguration bits are used to select the various options. For

more details on the device conﬁguration bits, see the “Device Characteristics” section.

2.2 Oscillator Conﬁgurations

2.2.1 Oscillator Types

Mid-Range devices can have up to eight different oscillator modes. The user can program up to

three de vice conﬁguration bits (FOSC2, FOSC1 and FOSC0) to select one of these eight modes:

• LP Low Frequency (Power) Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resistor/Capacitor (same as EXTRC with CLKOUT)

• EXTRC External Resistor/Capacitor

• EXTRC External Resistor/Capacitor with CLKOUT

• INTRC Internal 4 MHz Resistor/Capacitor

• INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT

The main diff erence between the LP, XT, and HS modes is the gain of the internal inverter of the

oscillator circuit which allows the different frequency ranges. Table 2-1 and Table 2-2 give infor-

mation to aid in selecting an oscillator mode. In general, use the oscillator option with the low est

possible gain which still meet speciﬁcations. This will result in lower dynamic currents (IDD). The

frequency range of each oscillator mode is the recommended (tested) frequency cutoffs, b ut the

selection of a different gain mode is acceptable as long as a thorough validation is perfor med

(voltage, temperature, component variations (Resistor, Capacitor, and internal microcontroller

oscillator circuitry)).

The RC mode and the EXTRC with CLK OUT mode ha ve the same functionality. The y are named

like this to help describe their operation vs. the other oscillator modes.

 1997 Microchip Technology Inc. DS31002A-page 2-3

Section 2. Oscillator

Oscillator

Table 2-1: Selecting the Oscillator Mode for Devices with FOSC1:FOSC0

Table 2-2: Selecting the Oscillator Mode for Devices with FOSC2:FOSC0

Conﬁguration bits

FOSC1:FOSC0 OSC

Mode

OSC

Feedback

Inverter

Gain

Comment

1 1 RC — Least expensive solution for device oscillation

(only an external resistor and capacitor is

required). Most variation in time-base.

Device’s default mode.

1 0 HS High Gain High frequency application.

Oscillator circuit’s mode consumes the most

current of the three crystal modes.

0 1 XT Medium Gain Standard crystal/resonator frequency.

Oscillator circuit’s mode consumes the middle

current of the three crystal modes.

0 0 LP Low Gain Low power/frequency applications.

Oscillator circuit’s mode consumes the least

current of the three crystal modes.

Conﬁguration

bits

FOSC2:FOSC0

OSC

Mode

OSC

Feedback

Inverter

Gain

Comment

1 1 1 EXTRC

with

CLKOUT

— Inexpensive solution for device oscillation. Most

variation in timebase. CLKOUT is enabled on

pin. Device’s default mode.

1 1 0 EXTRC — Inexpensive solution for device oscillation. Most

variation in timebase.

CLKOUT is disabled (use as I/O) on pin.

1 0 1 INTRC

with

CLKOUT

— Least expensive solution for device oscillation.

4 MHz oscillator, which can be tuned.

CLKOUT is enabled on pin.

1 0 0 INTRC — Least expensive solution for device oscillation.

4 MHz oscillator, which can be tuned.

CLKOUT is disabled (use as I/O) on pin.

0 1 1 — — Reserved

0 1 0 HS High Gain High frequency application.

Oscillator circuit’s mode consumes the most

current of the three crystal modes.

0 0 1 XT Medium Gain Standard crystal/resonator frequency.

Oscillator circuit’s mode consumes the middle

current of the three crystal modes.

0 0 0 LP Low Gain Low power/frequency applications.

Oscillator circuit’s mode consumes the least

current of the three crystal modes.

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-4  1997 Microchip Technology Inc.

2.3 Crystal Oscillators / Ceramic Resonators

In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins

to establish oscillation (Figure 2-1). The PICmicro oscillator design requires the use of a parallel

cut crystal. Using a series cut crystal may give a frequency out of the crystal manufacturer’s

speciﬁcations. When in XT, LP or HS modes, the device can have an external clock source drive

the OSC1 pin (Figure 2-3).

Figure 2-1: Crystal or Ceramic Resonator Operation (HS, XT or LP Oscillator Mode)

XTAL

OSC2

(1)

OSC1

(2) SLEEP

To internal logic (3)

PIC16CXXX

To internal logic (3)

Note 1: A series resistor, RS, may be required for AT strip cut crystals.

2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ.

3: Depending on the device, the buffer to the internal logic may be

either before or after the oscillator inverter.

 1997 Microchip Technology Inc. DS31002A-page 2-5

Section 2. Oscillator

Oscillator

2.3.1 Oscillator / Resonator Start-up

As the device voltage increases from VSS, the oscillator will start its oscillations. The time

required for the oscillator to start oscillating depends on many factors. These include:

• Crystal / resonator frequency

• Capacitor values used (C1 and C2 in Figure 2-1)

• De vice VDD rise time

• System temperature

• Series resistor value (and type) if used (Rs in Figure 2-1)

• Oscillator mode selection of de vice (which selects the gain of the internal oscillator inverter)

• Crystal quality

• Oscillator circuit layout

• System noise

Figure 2-2 graphs an example oscillator / resonator start-up. The peak-to-peak voltage of the

oscillator wavefor m can be quite low (less than 50% of device VDD) where the waveform is cen-

tered at VDD/2 (refer to parameters D033 and D043 in the “Electrical Speciﬁcations” section).

Figure 2-2: Example Oscillator / Resonator Start-up Characteristics

Voltage

Crystal Start-up Time Time

De vice VDD

Maximum VDD of System

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-6  1997 Microchip Technology Inc.

2.3.2 Component Selection

Figure 2-1 is a diagram of the devices cr ystal or ceramic resonator circuitr y. The resistance for

the f eedback resistor , RF, is typically within the 2 to 10 MΩ range. This v aries with device voltage ,

temperature, and process v ariations. A series resistor , Rs, may be required if an AT strip cut crys-

tal is used. Be sure to include the device’s operating voltage and the de vice’s manufacturing pro-

cess when determining resistor requirements. As you can see in Figure 2-1, the connection to

the de vice’s internal logic is device dependent. See the applicab le data sheet for de vice speciﬁcs.

The typical values of capacitors ( C1, C2) are given in Table 2-3 and Table 2-4. Each de vice’ s data

sheet will give the speciﬁc values that Microchip tested.

Table 2-3: Typical Capacitor Selection for Ceramic Resonators

Ranges tested:

Mode Frequency

(1)

XT 455 kHz

2.0 MHz

4.0 MHz

22 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz

20.0 MHz

10 - 68 pF

10 - 22 pF

TBD

Resonators used:

455 kHz Panasonic EFO-A455K04B ±0.3%

2.0 MHz Murata Erie CSA2.00MG ±0.5%

4.0 MHz Murata Erie CSA4.00MG ±0.5%

8.0 MHz Murata Erie CSA8.00MT ±0.5%

16.0 MHz Murata Erie CSA16.00MX ±0.5%

20.0 MHz TBD TBD

Note 1: Recommended values of C1 and C2 are identical to the ranges tested above.

Higher capacitance increases the stability of the oscillator but also increases the

start-up time. These values are for design guidance only. Since each resonator has

its own characteristics, the user should consult the resonator man ufacturer for appro-

priate values of external component or verify oscillator performance.

2: All resonators tested required external capacitors.

 1997 Microchip Technology Inc. DS31002A-page 2-7

Section 2. Oscillator

Oscillator

Table 2-4: Typical Capacitor Selection for Crystal Oscillator

Mode Freq

(1)

LP 32 kHz

200 kHz 68 - 100 pF

15 - 30 pF 68 - 100 pF

15 - 30 pF

XT 100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

HS 8 MHz

10 MHz

20 MHz

15 - 30 pF

Crystals used:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

100 kHz Epson C-2 100.00 KC-P ± 20 PPM

200 kHz STD XTL 200.000 kHz ± 20 PPM

2.0 MHz ECS ECS-20-S-2 ± 50 PPM

4.0 MHz ECS ECS-40-S-4 ± 50 PPM

10.0 MHz ECS ECS-100-S-4 ± 50 PPM

20.0 MHz ECS ECS-200-S-4 ± 50 PPM

Note 1: Higher capacitance increases the stability of the oscillator but also increases the

start-up time. These values are for design guidance only. A series resistor, Rs, may

be required in HS mode as well as XT mode to avoid overdriving crystals with low

drive level speciﬁcation. Since each crystal has its own characteristics, the user

should consult the crystal manufacturer for appropriate values of external compo-

nents or verify oscillator performance.

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-8  1997 Microchip Technology Inc.

2.3.3 Tuning the Oscillator Circuit

Since Microchip devices have wide operating ranges (frequency, voltage, and temperature;

depending on the par t and version ordered) and exter nal components (cr ystals, capacitors,...),

of varying quality and manuf acture; validation of operation needs to be performed to ensure that

the component selection will comply with the requirements of the application.

There are many f actors that go into the selection and arrangement of these external components.

These factors include:

• ampliﬁer gain

• desired frequency

• resonant frequency(s) of the crystal

• temperature of operation

• supply voltage range

• start-up time

• stability

• crystal life

• power consumption

• simpliﬁcation of the circuit

• use of standard components

• combination which results in fewest components

 1997 Microchip Technology Inc. DS31002A-page 2-9

Section 2. Oscillator

Oscillator

2.3.3.1 Determining Best Values for Crystals, Clock Mode, C1, C2, and Rs

The best method for selecting components is to apply a little knowledge and a lot of trial, mea-

surement, and testing.

Crystals are usually selected by their parallel resonant frequency only, however other parame-

ters may be impor tant to your design, such as temperature or frequency tolerance. Application

Note AN588 is an e xcellent ref erence if y ou would lik e to know more about crystal operation and

their ordering information.

The PICmicros™ internal oscillator circuit is a parallel oscillator circuit, which requires that a par-

allel resonant crystal be selected. The load capacitance is usually speciﬁed in the 20 pF to 32 pF

range. The crystal will oscillate closest to the desired frequency with capacitance in this range. It

ma y be necessary to sometimes juggle these values a bit, as described later , in order to achie v e

other beneﬁts.

Clock mode is primarily chosen by using the FOSC par ameter speciﬁcation (parameter 1A) in the

device’s data sheet, based on frequency. Clock modes (except RC) are simply gain selections,

lower gain for lower frequencies, higher gain for higher frequencies. It is possible to select a

higher or lower gain, if desired, based on the speciﬁc needs of the oscillator circuit.

C1 and C2 should also be initially selected based on the load capacitance as suggested by the

crystal manufacturer and the tables supplied in the device data sheet. The values given in the

Microchip data sheet can only be used as a starting point, since the crystal manufacturer , supply

voltage, and other factors already mentioned may cause your circuit to differ from the one used

in the factory characterization process.

Ideally, the capacitance is chosen (within the r ange of the recommended crystal load preferab ly)

so that it will oscillate at the highest temperature and low est VDD that the circuit will be expected

to perf orm under . High temperature and low VDD both ha ve a limiting aff ect on the loop gain, such

that if the circuit functions at these e xtremes, the designer can be more assured of proper oper-

ation at other temperatures and supply voltage combinations. The output sine wave should not

be clipped in the highest gain environment (highest VDD and lowest temperature) and the sine

output amplitude should be great enough in the low est gain environment (lowest VDD and highest

temperature) to cov er the logic input requirements of the cloc k as listed in the de vice data sheet.

A method for improving star t-up is to use a value of C2 greater than C1. This causes a greater

phase shift across the crystal at power-up, which speeds oscillator start-up.

Besides loading the crystal for proper frequency response, these capacitors can have the effect

of lowering loop gain if their value is increased. C2 can be selected to affect the overall gain of

the circuit. A higher C2 can lower the gain if the crystal is being over driven (see also discussion

on Rs). Capacitance values that are too high can store and dump too much current through the

cr ystal, so C1 and C2 should not become excessively large. Unfor tunately, measuring the watt-

age through a crystal is tricky b usiness , but if you do not stray too far from the suggested v alues

you should not have to be concerned with this.

A series resistor , Rs, is added to the circuit if, after all other external components are selected to

satisf action, the crystal is still being over driv en. This can be determined by looking at the OSC2

pin, which is the driven pin, with an oscilloscope. Connecting the probe to the OSC1 pin will load

the pin too much and negativ ely aff ect perf ormance. Remember that a scope probe adds its o wn

capacitance to the circuit, so this may have to be accounted for in your design, i.e. if the circuit

worked best with a C2 of 20 pF and scope probe was 10 pF, a 30 pF capacitor may actually be

called f or. The output signal should not be clipping or squashed. Overdriving the crystal can also

lead to the circuit jumping to a higher harmonic level or even crystal damage.

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-10  1997 Microchip Technology Inc.

The OSC2 signal should be a nice clean sine wave that easily spans the input minimum and max-

imum of the clock input pin (4V to 5V peak to peak for a 5V VDD is usually good). An easy way

to set this is to again test the circuit at the minimum temperature and maximum VDD that the

design will be e xpected to perform in, then look at the output. This should be the maximum ampli-

tude of the clock output. If there is clipping or the sine wave is squashing near VDD and VSS at

the top and bottom, and increasing load capacitors will risk too much current through the crystal

or push the value too far from the manufacturer’s load speciﬁcation, then add a trimpot between

the output pin and C2, and adjust it until the sine wa ve is clean. K eeping it fairly close to maximum

amplitude at the low temperature and high VDD combination will assure this is the maximum

amplitude the cr ystal will see and prevent overdriving. A ser ies resistor, Rs, of the closest stan-

dard value, can now be inserted in place of the trimpot. If Rs is too high, perhaps more than

20k ohms, the input will be too isolated from the output, making the clock more susceptible to

noise. If you ﬁnd a value this high is needed to prevent overdriving the crystal, try increasing C2

to compensate. Tr y to get a combination where Rs is around 10k or less, and load capacitance

is not too far from the 20 pF or 32 pF manufacturer speciﬁcation.

2.3.3.1.1 Start-up

The most difﬁcult time f or the oscillator to start-up is when waking up from sleep . This is because

the load capacitors have both par tially charged to some quiescent value, and phase differential

at wak e-up is minimal. Thus, more time is required to achieve stable oscillation. Remember also

that low v oltage, high temperatures, and the lower frequency clock modes also impose limitations

on loop gain, which in turn affects start-up. Each of the following factors makes thing worse:

• a low frequency design (with its low gain clock mode)

• a quiet environment (such as a battery operated device)

• operating outside the noisy RF area (such as in a shielded box)

• low voltage

• high temperature

• waking up from sleep.

Noise actually helps a design for oscillator start-up, since it helps kick start the oscillator.

2.3.4 External Clock Input

If the PICmicro’ s internal oscillator is not being used, and the device will be driv en from an e xter-

nal clock, be sure to set the oscillator mode to one of the crystal modes (LP, XT, or HS). That is,

something other than one of the RC modes, since RC mode will ﬁght with the injected input. Ide-

ally you would select the mode that corresponds to the frequency injected, but this is of less

impor tance here since the clock is only driving its inter nal logic, and not a cr ystal loop circuit. It

ma y be possible to select a clock mode lo w er than would be needed by an oscillator circuit, and

thereby sa v e some of the po wer that would be used exercising the inv erting ampliﬁer . Make sure

the OSC2 signal amplitude covers the needed logic thresholds of the device.

Figure 2-3: External Device Clock Input Operation (HS, XT or LP Oscillator Modes)

clock from

external system PIC16CXXX

OSC1

OSC2

Open

Note 1: A resistor to ground may be used to reduce system noise.

This may increase system current.

(1)

 1997 Microchip Technology Inc. DS31002A-page 2-11

Section 2. Oscillator

Oscillator

2.3.5 External Crystal Oscillator Circuit for Device Clock

Sometimes more than one device needs to be clocked from a single crystal. Since Microchip

does not recommend connecting other logic to the PICmicro’ s internal oscillator circuit, an exter-

nal crystal oscillator circuit is recommended. Each de vice will then hav e an external clock source,

and the number of de vices that can be driven will depend on the buff er drive capability. This circuit

is also useful when more than one device (PICmicro) needs to operate synchronously to each

other.

Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be

built. Prepac kaged oscillators provide a wide operating range and better stability. A well-designed

crystal oscillator will pro vide good performance with TTL gates. Two types of crystal oscillator cir-

cuits can be used; one with series resonance, or one with parallel resonance.

Figure 2-4 shows implementation of an external parallel resonant oscillator circuit. The circuit is

designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the

180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the nega-

tive feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region.

Figure 2-4: External Parallel Resonant Crystal Oscillator Circuit

Figure 2-5 shows an e xternal series resonant oscillator circuit. This circuit is also designed to use

the fundamental frequency of the crystal. The inver ter perfor ms a 180-degree phase shift in a

series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the

inverters in their linear region.

Figure 2-5: External Series Resonant Crystal Oscillator Circuit

When the device is clocked from an exter nal clock source (as in Figure 2-4 or Figure 2-5) then

the microcontroller’s oscillator must be conﬁgured for LP, XT or HS mode (Figure 2-3).

20 pF

+5V

20 pF

10kΩ

4.7 kΩ

10 kΩ

74AS04

XTAL

10 kΩ

74AS04

CLKIN

To Other

Devices

PIC16CXXX

330 kΩ

74AS04 74AS04 PIC16CXXX

CLKIN

To Other

Devices

XTAL

330 kΩ

74AS04

0.1 µF

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-12  1997 Microchip Technology Inc.

2.4 External RC Oscillator

F or timing insensitiv e applications the “EXTRC” device option offers additional cost savings. The

RC oscillator frequency is a function of; the supply voltage, the resistor (REXT) and capacitor

(CEXT) values , and the operating temperature. In addition to this , the oscillator frequency will vary

from unit to unit due to normal process parameter variation. Furthermore, the difference in lead

frame capacitance between pac kage types will also affect the oscillation frequency, especially for

low CEXT values. The user also needs to take into account variation due to tolerance of external

REXT and CEXT components used. Figure 2-6 shows how the RC combination is connected to a

PIC16CXXX. For REXT values below 2.2 kΩ, oscillator operation may become unstable, or stop

completely. For very high REXT values (e.g. 1 MΩ), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping REXT between 3 kΩ and 100 kΩ.

Figure 2-6: EXTRC Oscillator Mode

Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend

using values above 20 pF for noise and stability reasons. With no or small external capacitance,

the oscillation frequency can vary dramatically due to changes in e xternal capacitances, such as

PCB trace capacitance and package lead frame capacitance.

See characterization data for RC frequency variation from part to part due to normal process

variation. The variation is larger for larger resistance (since leakage current variation will affect

RC frequency more f or large R) and for smaller capacitance (since v ariation of input capacitance

will affect RC frequency more).

See characterization data for var iation of oscillator frequency due to VDD for given REXT/CEXT

values as well as frequency variation due to operating temperature for given REXT, CEXT, and

VDD values.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used

for test pur poses or to synchronize other logic (see Figure 4-3: "Clock/Instruction Cycle" in

the “Architecture” section, for waveform).

2.4.1 RC Start-up

As the de vice voltage increases, the RC will start its oscillations immediately after the pin voltage

levels meet the input threshold speciﬁcations (parameters D032 and D042 in the “Electrical

Speciﬁcations” section). The time required for the RC to start oscillating depends on many fac-

tors. These include:

• Resistor value used

• Capacitor value used

• De vice VDD rise time

• System temperature

OSC2/CLKOUT

CEXT

VDD

REXT

VSS

PIC16CXXX

OSC1

Fosc/4 (1)

Internal

clock

Fosc

Note 1: This output may also be able to be conﬁgured as a general purpose I/O pin.

 1997 Microchip Technology Inc. DS31002A-page 2-13

Section 2. Oscillator

Oscillator

2.5 Internal 4 MHz RC Oscillator

The internal RC oscillator (not on all devices) provides a ﬁxed 4 MHz (nominal) system clock at

VDD = 5V and 25°C , see the device data sheet’ s “Electrical Speciﬁcations” section f or inf ormation

on variation over voltage and temperature.

The value in the OSCCAL register is used to tune the frequency of the internal RC oscillator . The

calibration value that Microchip programs into the device will “trim” the internal oscillator to

remov e process variation from the oscillator frequency. The CAL3:CAL0 bits are used f or ﬁne cal-

ibration within a frequency window. Higher values of CAL3:CAL0 (from 0000 to 1111) yields

higher clock speeds.

When a 4 MHz internal RC oscillator frequency cannot be achieved by a CAL3:CAL0 value, the

RC oscillator frequency can be increased or decreased by an offset frequency. The CALFST and

CALSLW bits are used to enable a positiv e or negative frequency offset to place the internal RC

frequency within the CAL3:CAL0 trim window.

Setting the CALFST bit offsets the internal RC for a higher frequency, while setting the CALSL W

bit offsets the internal RC for a lower frequency.

Upon a device reset, the OSCCAL register is forced to the midpoint value (CAL3:CAL0 = 7h,

CALFST and CALSLW providing no offset).

R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0

CAL3 CAL2 CAL1 CAL0 CALFST CALSLW — —

bit 7 bit 0

bit 7:4 CAL3:CAL0: Internal RC Oscillator Calibration bits

0000 = Lowest clock frequency within the trim range

•

1111 = Highest clock frequency within the trim range

bit 3 CALFST: Oscillator Range Offset bit

1 = Increases the frequency of the internal RC oscillator into the CAL3:CAL0 trim window

0 = No offset provided

bit 2 CALSLW: Oscillator Range Offset bit

1 = Decreases the frequency of the internal RC oscillator into the CAL3:CAL0 trim window

0 = No offset provided

Note: When both bits are set, the CALFST bit overrides the CALSLW bit.

bit 1:0 Unimplemented: Read as '0'

Note: These bits should be written as ‘0’ when modifying the OSCCAL register, for com-

patibility with future devices.

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note: OSCCAL is used to remove process variation from the internal RC oscillator of the

device. The OSCCAL value should not be modiﬁed from the Microchip supplied

value , and all timing critical functions should be adjusted by the application softw are.

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-14  1997 Microchip Technology Inc.

Figure 2-7 shows the possib le device frequencies from the uncalibrated point (at V DD = 5V, 25°C,

and OSCCAL = 70h), and the changes achievable by the OSCCAL register.

Figure 2-7: Ideal Internal RC Oscillator Frequency vs. OSCCAL Register Value

Figure 2-8 shows an example of a device where by selecting one of the CAL3:CAL0 values, the

frequency can corrected to 4 MHz. These bits can be considered the ﬁne trimming of the

frequency. Sometimes the device frequency at the uncalibrated point cannot be corrected to 4

MHz by the ﬁne trimming of the CAL3:CAL0 bits v alue. Theref ore two additional bits are a vailab le

which give a large frequency offset (positive and negative) to move the frequency within the

range where the ﬁne trimming can work. These bits are the CALSLW and CALFST bits, which

offset the internal RC frequency. The action of these bits are shown in Figure 2-9, and

Figure 2-10.

Figure 2-8: CAL3:CAL0 Trimming of Internal RC Oscillator Frequency Offset

Frequency

CAL3:CAL0 = 07h

CALFST = 0

CALSLW = 0

See X-axis

CAL3:CAL0

Trim Window

CAL3:CAL0 = Fh

CALFST = 1

CALSLW = x

CAL3:CAL0 = 0h

CALFST = 0

CALSLW = 1

CAL3:CAL0 = 0h

CALFST = 0

CALSLW = 0

CAL3:CAL0 = Fh

CALFST = 0

CALSLW = 0

4 MHz

(slowest frequency) (fastest frequency)

Frequency

CAL3:CAL0

Trim Window

4 MHz ± 1.5%

CAL3:CAL0 = 0000 CAL3:CAL0 = 1111

Internal RC

Frequency at

> 4 MHz

< 4 MHz

One of the 16 possible calibration points

(@ 5V, 25˚C)

device reset

CALFST = 0

CALFLW = 0

CAL3:CAL0 = 7h

 1997 Microchip Technology Inc. DS31002A-page 2-15

Section 2. Oscillator

Oscillator

Figure 2-9: CALFST Positive Internal RC Oscillator Frequency Offset

Figure 2-10: CALSLW Negative Internal RC Oscillator Frequency Offset

CAL3:CAL0

Trim Window

CAL3:CAL0 = 0000 CAL3:CAL0 = 1111

Internal RC

Frequency at

CALFST offset

Internal RC

Frequency with

CALFST = 1

CALSLW = x

Frequency

4 MHz ± 1.5%

< 4 MHz

(@ 5V, 25˚C)

One of the 16 possible CAL3:CAL0 calibration points

device reset

CALFST = 0

CALFLW = 0

Frequency

CAL3:CAL0

Trim Window

CAL3:CAL0 = 0000 CAL3:CAL0 = 1111

Internal RC

Frequency at

Internal RC

Frequency with

CALSLW = 1

CALFST = 0

CALSLW offset

device reset

One of the 16 possible CAL3:CAL0 calibration points

4 MHz ± 1.5%

> 4 MHz

(@ 5V, 25˚C)

CALSLW = 0

CALFST = 0

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-16  1997 Microchip Technology Inc.

A calibration instruction is programmed into the last address of the implemented program

memor y. This instruction contains the calibration value for the internal RC oscillator. This value

is programmed as a RETLW XX instruction where XX is the calibration value. In order to retrieve

the calibration v alue, issue a CALL YY instruction where YY is the last location in the device’ s user

accessible prog ram memory. The calibration value is now loaded in the W register. The program

should then perf orm a MOVWF OSCCAL instruction to load the value into the internal RC oscillator

calibration register. Table 2-5 shows the location of the calibration value depending on the size

of the program memory.

Table 2-5: Calibration Value Location

2.5.1 Clock Out

The internal RC oscillator can be conﬁgured to provide a clock out signal on the CLKOUT pin

when the conﬁguration word address (2007h) is programmed with FOSC2, FOSC1, FOSC0

equal to ‘101’ for Internal RC or ‘111’ for External RC. CLKOUT, which is divided by 4, can be

used for test purposes or to synchronize other logic.

When the calibration v alue of the internal RC oscillator is accidently erased, the cloc k out f eature

allows the user to determine what the calibration value should be. This is achieved by writing a

program which modiﬁes (increments/decrements) the value of the OSCCAL register. When the

CLKOUT pin is at 4 MHz (± 1.5%) at 5V and 25˚C, the OSCCAL register has the correct calibra-

tion value. This value then needs to be written to a por t or shifted out ser ially, so that the value

can be written down and programmed into the calibration location.

Program

Memory Size

(Words)

Calibration V alue

Location

512 1FFh

1K 3FFh

2K 7FFh

4K FFFh

8K 1FFFh

Note 1: Erasing the device (windowed devices) will also erase the factory programmed

calibration value for the internal oscillator.

Prior to erasing a windowed device, the internal oscillator calibration value must be

saved. It is a good idea to wr ite this value on the package of the device to ensure

that the calibration value is not accidently lost.

This sav ed valued must be restored into program memory calibration location bef ore

programming the device.

Note 2: OSCCAL<1:0> are unimplemented and should be written as ‘0’. This will help

ensure compatibility with future devices.

 1997 Microchip Technology Inc. DS31002A-page 2-17

Section 2. Oscillator

Oscillator

2.6 Effects of Sleep Mode on the On-chip Oscillator

When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off

and the device is held at the beginning of an instr uction cycle (Q1 state). With the oscillator off,

the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents ha ve

been remov ed, sleep mode achie ves the lo west current consumption of the de vice (only leakage

currents). Enabling any on-chip feature that will operate during sleep will increase the current

consumed during sleep. The user can w ake from SLEEP through e xternal reset, Watchdog Timer

Reset or through an interrupt.

Table 2-6: OSC1 and OSC2 Pin States in Sleep Mode

2.7 Effects of Device Reset on the On-chip Oscillator

De vice resets have no effect on the on-chip crystal oscillator circuitry. The oscillator will contin ue

to operate as it does under normal execution. While in reset, the device logic is held at the Q1

state so that when the device exits reset, it is at the beginning of an instruction cycle.

The OSC2 pin, when used as the external clockout (EXTRC mode), will be held low during

reset, and as soon as the MCLR pin is at VIH (input high voltage), the RC will start to oscillate.

See Table 3-1, in the “Reset” section, for time-outs due to Sleep and MCLR reset.

2.7.1 Power-up Delays

There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up

Timer, OST, intended to k eep the chip in RESET until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT), which provides a ﬁxed delay of 72 ms (nominal) on power-up only

(POR and BOR). The PWRT is designed to keep the part in RESET while the power supply sta-

bilizes. With these two timers on-chip, most applications need no external reset circuitry. For

additional information on reset operation, see the “Reset” section.

OSC Mode OSC1 Pin OSC2 Pin

EXTRC Floating, e xternal resistor should

pull high At logic low

INTRC N.A. N.A.

LP, XT, and HS Feedback inverter disabled, at

quiescent voltage level Feedback inverter disabled, at

quiescent voltage level

See Table 3-1, in the “Reset” section, for time-outs due to Sleep and MCLR reset.

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-18  1997 Microchip Technology Inc.

2.8 Design Tips

Question 1:

When looking at the OSC2 pin after power -up with an oscilloscope, there is

no clock. What can cause this?

Answer 1:

1. Executing a SLEEP instruction with no source for wake-up (such as, WDT, MCLR, or an

Interrupt). Verify that the code does not put device to sleep without pro viding for wak e-up.

If it is possible, tr y waking it up with a low pulse on MCLR. Powering up with MCLR held

low will also give the crystal oscillator more time to start-up, but the Program Counter will

not advance until the MCLR pin is high.

2. The wrong clock mode is selected for the desired frequency. For a blank device, the

default oscillator is EXTRC. Most parts come with the clock selected in the default RC

mode, which will not start oscillation with a crystal or resonator . Verify that the clock mode

has been programmed correctly.

3. The proper power-up sequence has not been f ollowed. If a CMOS part is powered through

an I/O pin prior to power-up, bad things can happen (latch up , improper start-up etc.) It is

also possible for brown-out conditions, noisy power lines at start-up, and slow VDD rise

times to cause problems. Tr y powering up the device with nothing connected to the I/O,

and power-up with a known, good, fast-rise, power supply. It is not as much of a problem

as it ma y sound, but the possibility exists . Ref er to the power-up inf ormation in the de vice

data sheet for considerations on brown-out and power-up sequences.

4. The C1 and C2 capacitors attached to the crystal have not been connected properly or are

not the correct values. Make sure all connections are correct. The device data sheet val-

ues f or these components will almost alwa ys get the oscillator running, they just might not

be the optimal values for your design.

Question 2:

The PICmicro starts, but runs at a frequency m uch higher than the resonant

frequency of the crystal.

Answer 2:

The gain is too high for this oscillator circuit. Refer to subsection 2.3 “Crystal Oscillators /

Ceramic Resonators” to aid in the selection of C2 (ma y need to be higher) Rs (ma y be needed)

and clock mode (wrong mode may be selected). This is especially possible for low frequency

crystals, like the common 32.768 kHz.

Question 3:

The design runs ﬁne, but the frequency is slightly off, what can be done to

adjust this?

Answer 3:

Changing the value of C1 has some aff ect on the oscillator frequency. If a SERIES resonant crys-

tal is used, it will resonate at a diff erent frequency than a PARALLEL resonant crystal of the same

frequency call-out.

Question 4:

The board works ﬁne, then suddenly quits, or loses time.

Answer 4:

Other than the obvious software checks that should be done to investigate losing time, it is pos-

sible that the amplitude of the oscillator output is not high enough to reliab ly trigger the oscillator

input.

Question 5:

I’m using a device with the internal RC oscillator and I have accidently

erased the calibration value. What can I do?

Answer 5:

If the frequency of the device does not matter, you can continue to use the device.

If the frequency of the device does matter, you can purchase a new windowed device, or follow

the suggestion in subsection 2.5.1 “Clock Out. ”

 1997 Microchip Technology Inc. DS31002A-page 2-19

Section 2. Oscillator

Oscillator

2.9 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to the oscillator

are:

Title Application Note #

PIC16/17 Oscillator Design Guide AN588

Low Power Design using PIC16/17 AN606

PICmicro MID-RANGE MCU FAMILY

DS31002A-page 2-20  1997 Microchip Technology Inc.

2.10 Revision History

Revision A

This is the initial released revision of the PICmicro oscillators description.

 1997 Microchip Technology Inc. DS31003A page 3-1

Reset

Section 3. Reset

HIGHLIGHTS

This section of the manual contains the following major topics:

3.1 Introduction....................................................................................................................3-2

3.2 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST),

Brown-out Reset (BOR), and Parity Error Reset (PER).................................................3-4

3.3 Registers and Status Bit Values...................................................................................3-10

3.4 Design Tips..................................................................................................................3-16

3.5 Related Application Notes............................................................................................3-17

3.6 Revision History...........................................................................................................3-18

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-2  1997 Microchip Technology Inc.

3.1 Introduction

The reset logic is used to place the device into a known state. The source of the reset can be

determined by using the device status bits. The reset logic is designed with features that reduce

system cost and increase system reliability.

Devices differentiate between various kinds of reset:

a) Power-on Reset (POR)

b) MCLR reset during normal operation

c) MCLR reset during SLEEP

d) WDT reset during normal operation

e) Brown-out Reset (BOR)

f) Parity Error Reset (PER)

Most registers are unaffected by a reset; their status is unknown on POR and unchanged by all

other resets. The other registers are forced to a “reset state” on Power-on Reset, MCLR, WDT

reset, Brown-out Reset, Parity Error Reset, and on MCLR reset during SLEEP.

The on-chip parity bits that can be used to verify the contents of program memory.

Most registers are not aff ected by a WDT w ake-up , since this is vie wed as the resumption of nor-

mal operation. Status bits T O, PD, POR, BOR, and PER are set or cleared differently in different

reset situations as indicated in Table 3-2. These bits are used in softw are to determine the nature

of the reset. See Table 3-4 for a full description of the reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 3-1. This block diagram

is a superset of reset features. To determine the features that are available on a speciﬁc device,

please refer to the device’s Data Sheet.

All new devices will have a noise ﬁlter in the MCLR reset path to detect and ignore small pulses .

See parameter 30 in the “Electrical Speciﬁcations” section for pulse width speciﬁcation.

Note: While the PICmicro™ is in a reset state, the internal phase clock is held at Q1

(beginning of an instruction cycle).

 1997 Microchip Technology Inc. DS31003A-page 3-3

Section 3. Reset

Reset

Figure 3-1: Simpliﬁed Block Diagram of a Super-set On-chip Reset Circuit

MCLR / VPP Pin (3)

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

On-chip(1)

RC OSC

WDT Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT (4)

SLEEP

See Table 3-1 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin or the INTRC oscillator.

2: Features in dashed boxes not available on all devices, see device’s Data Sheet.

3: In some devices, this pin may be conﬁgured as a general purpose Input.

4: The early PICmicro devices hav e the conﬁguration bit deﬁned as PWR TE = 1 is enab led, while all other

devices the conﬁguration bit is deﬁned as PWRTE = 0 is enabled.

Brown-out

Reset BODEN

CLKIN

10-bit Ripple-counter

Program

Memory

Parity

MPEEN

MCLRE

Weak Pull-up (2)

VDD

MCLRE

I/O Pull-up

Enable

(2)

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-4  1997 Microchip Technology Inc.

3.2 Power-on Reset (POR), Power-up Timer (PWRT),

Oscillator Start-up Timer (OST), Brown-out Reset (BOR), and Parity Error Reset (PER)

3.2.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of

the POR, just tie the MCLR pin directly (or through a resistor) to VDD as shown in Figure 3-2. This

will eliminate exter nal RC components usually needed to create a Power-on Reset. A minimum

rise time for VDD is required. See parameter D003 and parameter D004 in the “Electrical Spec-

iﬁcations” section for details.

Figure 3-2: Using On-Chip POR

When the device exits the reset condition (begins normal operation), the device oper ating param-

eters (voltage , frequency, temperature, etc.) must be within their operating ranges , otherwise the

de vice will not function correctly. Ensure the delay is long enough to get all oper ating parameters

within speciﬁcation.

Figure 3-3 shows a possib le POR circuit for a slow po wer supply ramp up . The e xternal P ower-on

Reset circuit is only required if VDD power-up time is too slow. The diode, D, helps discharge the

capacitor quickly when VDD powers down.

Figure 3-3: External Power-on Reset Circuit (For Slow VDD Power-up)

VDD

MCLR

PIC16CXXX

VDD

R (1)

Note: The resistor is optional.

VDD

MCLR

PIC16CXXX

VDD

Note: R < 40 kΩ is recommended to ensure that the voltage drop across R does not

exceed 0.2V. A larger voltage drop will degrade VIH level on the MCLR/VPP pin.

VDD

 1997 Microchip Technology Inc. DS31003A-page 3-5

Section 3. Reset

Reset

3.2.2 Power-up Timer (PWRT)

The Power-up Timer provides a nominal 72 ms delay on Power-on Reset (POR) or Brown-out

Reset (BOR), see parameter 33 in the “Electrical Speciﬁcations” section. The P o wer-up Timer

operates on a dedicated internal RC oscillator. The device is kept in reset as long as the PWRT

is active. The PWRT delay allows VDD to rise to an acceptable level. The power-up timer enable

conﬁguration bit can enable/disable the Power-up Timer. The Power-up Timer should always be

enabled when Brown-out Reset is enabled. The polarity of the Power-up Timer conﬁguration bit

is now PWRTE = 0 for enabled, while the initial deﬁnition of the bit was PWRTE = 1 for enabled.

Since all new de vices will use the PWR TE = 0 f or enab led, the te xt will describe the operation for

such devices. Please refer to the individual Data Sheet to ensure the correct polarity for this bit.

The power-up time delay will vary from device to device due to VDD, temperature, and process

variations. See DC parameters for details.

3.2.3 Oscillator Start-up Timer (OST)

The Oscillator Star t-Up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input)

after the PWR T delay is o ver . This ensures that the crystal oscillator or resonator has started and

is stable.

The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset,

Brown-out Reset, or wake-up from SLEEP.

The OST counts the oscillator pulses on the OSC1/CLKIN pin. The counter only starts increment-

ing after the amplitude of the signal reaches the oscillator input thresholds. This delay allows the

crystal oscillator or resonator to stabiliz e bef ore the de vice e xits the OST dela y. The length of the

time-out is a function of the crystal/resonator frequency.

Figure 3-4 shows the operation of the OST circuit in conjunction with the po wer-up timer. F or lo w

frequency crystals this start-up time can become quite long. That is because the time it tak es the

low frequency oscillator to start oscillating is longer than the power-up timer’s delay. So the time

from when the power-up timer times-out, to when the oscillator starts to oscillate is a dead time.

There is no minimum or maximum time for this dead time (

DEADTIME

Figure 3-4: Oscillator Start-up Time

VDD

MCLR

Oscillator

OST TIME_OUT

PWRT TIME_OUT

INTERNAL RESET

TOSC1

TOST

TPWRT

POR or BOR Trip Point

Tosc1 = time for the crystal oscillator to react to an oscillation level detectable by the

Oscillator Start-up Timer (OST).

TOST = 1024TOSC.

TDEADTIME

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-6  1997 Microchip Technology Inc.

3.2.4 Power-up Sequence

On power-up, the time-out sequence is as follows: First the internal POR is detected, then, if

enabled, the PWRT time-out is invoked. After the PWRT time-out is over, the OST is activated.

The total time-out will vary based on oscillator conﬁguration and PWR TE bit status. For e xample ,

in RC mode with the PWR TE bit set (PWR T disabled), there will be no time-out at all. Figure 3-5,

Figure 3-6 and Figure 3-7 depict time-out sequences.

Since the time-outs occur from the internal POR pulse, if MCLR is kept low long enough, the

time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 3-7).

This is useful for testing purposes or to synchronize more than one device operating in parallel.

If the device voltage is not within the electrical speciﬁcations by the end of a time-out, the

MCLR/VPP pin must be held low until the v oltage is within the de vice speciﬁcation. The use of an

external RC delay is sufﬁcient for many of these applications.

Table 3-1 shows the time-outs that occur in various situations, while Figure 3-5 through

Figure 3-8 show four different cases that can happen on powering up the device.

Table 3-1: Time-out in Various Situations

Figure 3-5: Time-out Sequence on Power-up (MCLR Tied to VDD)

Oscillator

Conﬁguration

Power-up Timer Brown-out Reset Wake-up

from

SLEEP

Enabled Disabled

XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms — (1) 72 ms — (1)

Note 1: Devices with the Internal/External RC option have a nominal 250 µs delay.

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

 1997 Microchip Technology Inc. DS31003A-page 3-7

Section 3. Reset

Reset

Figure 3-6: Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 1

Figure 3-7: Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 2

Figure 3-8: Slow Rise Time (MCLR Tied to VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V 5V

TPWRT

TOST

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-8  1997 Microchip Technology Inc.

3.2.5 Brown-out Reset (BOR)

On-chip Brown-out Reset circuitry places the device into reset when the device voltage falls

below a trip point (BVDD). This ensures that the de vice does not continue program e x ecution out-

side the valid oper ation range of the device. Brown-out resets are typically used in AC line appli-

cations or large battery applications where large loads ma y be s witched in (such as automotiv e),

and cause the device voltage to temporarily fall below the speciﬁed operating minimum.

The BODEN conﬁguration bit can disable (if clear/programmed) or enable (if set) the Brown-out

Reset circuitry. If VDD falls belo w BVDD (Typically 4.0V, parameter D005 in the “Electrical Spec-

iﬁcations” section), for greater than parameter 35, the brown-out situation will reset the chip. A

reset is not guaranteed to occur if VDD falls belo w BVDD f or less than parameter 35 . The chip will

remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be inv ok ed

and will keep the chip in reset an additional 72 ms . If VDD drops below BVDD while the Power-up

Timer is running, the chip will go back into Reset and the Power-up Timer will be re-initialized.

Once VDD rises above BVDD, the Power-up Timer will again start a 72 ms time delay. Figure 3-9

shows typical Brown-out situations.

With the BODEN bit set, all voltages below BVDD will hold the device in the reset state. This

includes during the power-up sequence.

Figure 3-9: Brown-out Situations

Note: Bef ore using the on-chip brown-out for a voltage supervisory function (monitor bat-

tery deca y), please revie w the electrical speciﬁcations to ensure that they meet your

requirements.

72 ms

VDD

Internal

Reset

BVDD

VDD

Internal

Reset 72 ms

<72 ms

72 ms

BVDD

VDD

Internal

Reset

BVDD

 1997 Microchip Technology Inc. DS31003A-page 3-9

Section 3. Reset

Reset

Some devices do not have the on-chip bro wn-out circuit, and in other cases there are some appli-

cations where the Brown-out Reset trip point of the device may not be at the desired level.

Figure 3-10 and Figure 3-11 are two examples of external circuitry that may be implemented.

Each needs to be evaluated to determine if they match the requirements of the application.

Figure 3-10: External Brown-out Protection Circuit 1

Figure 3-11: External Brown-out Protection Circuit 2

This circuit will activate reset when VDD goes below (Vz + 0.7V)

where Vz = Zener voltage.

Note 1: Internal Brown-out Reset circuitry should be disabled when using this circuit.

2: Resistors should be adjusted for the characteristics of the transistor.

VDD

33 kΩ

10 kΩ

40 kΩ

VDD

MCLR

PIC16CXXX

R2 40 kΩ

VDD

MCLR

PIC16CXXX

VDD

Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns

off when VDD is below a certain level such that:

2: Internal Brown-out Reset circuitry should be disabled when using this circuit.

3: Resistors should be adjusted for the characteristics of the transistor.

VDD • R1

R1 + R2 = 0.7V

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-10  1997 Microchip Technology Inc.

3.3 Registers and Status Bit Values

Table 3-2: Status Bits and Their Signiﬁcance

POR BOR(1) TO PD Condition

0x11Power-on Reset

0x0xIllegal, T O is set on POR

0xx0Illegal, PD is set on POR

1(2) 011Brown-out Reset

1(2) 1(2) 01WDT Reset

1(2) 1(2) 00WDT W ake-up

1(2) 1(2) uuMCLR reset during normal operation

1(2) 1(2) 10MCLR reset during SLEEP

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: Not all devices have BOR circuitry.

2: These bits are unchanged for the giv en conditions, and when initializ ed (set) after a

POR or a BOR will read as a '1'.

 1997 Microchip Technology Inc. DS31003A-page 3-11

Section 3. Reset

Reset

Table 3-3: Initialization Condition for Special Registers

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx u--- -10x

MCLR reset during normal operation 000h 000u uuuu u--- -uuu

MCLR reset during SLEEP 000h 0001 0uuu u--- -uuu

WDT reset 000h 0000 1uuu u--- -uuu

WDT Wake-up PC + 1 uuu0 0uuu u--- -uuu

Brown-out Reset 000h 0001 1uuu u--- -uu0

Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu u--- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wak e-up is due to an interrupt and global enable bit, GIE, is set the PC is

loaded with the interrupt vector (0004h) after execution of PC+1.

2: If a status bit is not implemented, that bit will be read as ‘0’.

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-12  1997 Microchip Technology Inc.

Table 3-4: Initialization Conditions for Special Function Registers

Brown-out Reset

MCLR Reset during:

- normal operation

- SLEEP or

WDT Reset

Wake-up from SLEEP

through:

- interrupt

- WDT time-out

ADCAPL 0000 0000 0000 0000 uuuu uuuu

ADCAPH 0000 0000 0000 0000 uuuu uuuu

ADCON0 0000 00-0 0000 00-0 uuuu uu-u

ADCON1 ---- -000 ---- -000 ---- -uuu

ADRES xxxx xxxx uuuu uuuu uuuu uuuu

ADTMRL 0000 0000 0000 0000 uuuu uuuu

ADMRH 0000 0000 0000 0000 uuuu uuuu

CCP1CON --00 0000 --00 0000 --uu uuuu

CCP2CON 0000 0000 0000 0000 uuuu uuuu

CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2H xxxx xxxx uuuu uuuu uuuu uuuu

CMCON 00-- 0000 00-- 0000 uu-- uuuu

EEADR xxxx xxxx uuuu uuuu uuuu uuuu

EECON1 ---0 x000 ---0 q000 ---0 uuuu

EECON2 -- -

EEDATA xxxx xxxx uuuu uuuu uuuu uuuu

FSR xxxx xxxx uuuu uuuu uuuu uuuu

GPIO --xx xxxx --uu uuuu --uu uuuu

I2CADD 0000 0000 0000 0000 uuuu uuuu

I2CBUF xxxx xxxx uuuu uuuu uuuu uuuu

I2CCON 0000 0000 0000 0000 uuuu uuuu

I2CSTAT --00 0000 --00 0000 --uu uuuu

INDF -- -

INTCON 0000 000x 0000 000u uuuu uuuu(1)

LCDCON 00-0 0000 00-0 0000 uu-u uuuu

LCDD00 to LCDD15 xxxx xxxx uuuu uuuu uuuu uuuu

LCDPS ---- 0000 ---- 0000 ---- uuuu

LCDSE 1111 1111 1111 1111 uuuu uuuu

OPTION_REG 1111 1111 1111 1111 uuuu uuuu

OSCCAL 0111 00-- uuuu uu-- uuuu uu--

PCL 0000 0000 0000 0000 PC + 1(2)

PCLATH ---0 0000 ---0 0000 ---u uuuu

PCON ---- --0u ---- --uu ---- --uu

PIE1 0000 0000 0000 0000 uuuu uuuu

PIE2 ---- ---0 ---- ---0 ---- ---u

PIR1 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

3: See Table 3-3 for reset value for speciﬁc condition.

 1997 Microchip Technology Inc. DS31003A-page 3-13

Section 3. Reset

Reset

PIR2 ---- ---0 ---- ---0 ---- ---u

PORTA --xx xxxx --uu uuuu --uu uuuu

PORTB xxxx xxxx uuuu uuuu uuuu uuuu

PORTC xxxx xxxx uuuu uuuu uuuu uuuu

PORTD xxxx xxxx uuuu uuuu uuuu uuuu

PORTE ---- -xxx ---- -uuu ---- -uuu

PORTF 0000 0000 0000 0000 uuuu uuuu

PORTG 0000 0000 0000 0000 uuuu uuuu

PR2 1111 1111 1111 1111 1111 1111

PREFA 0000 0000 0000 0000 uuuu uuuu

PREFB 0000 0000 0000 0000 uuuu uuuu

RCSTA 0000 -00x 0000 -00x uuuu -uuu

RCREG 0000 0000 0000 0000 uuuu uuuu

SLPCON 0011 1111 0011 1111 uuuu uuuu

SPBRG 0000 0000 0000 0000 uuuu uuuu

SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu

SSPCON 0000 0000 0000 0000 uuuu uuuu

SSPADD 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 0000 0000 0000 0000 uuuu uuuu

STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)

T1CON --00 0000 --uu uuuu --uu uuuu

T2CON -000 0000 -000 0000 -uuu uuuu

TMR0 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H xxxx xxxx uuuu uuuu uuuu uuuu

TMR2 0000 0000 0000 0000 uuuu uuuu

TRIS --11 1111 --11 1111 --uu uuuu

TRISA --11 1111 --11 1111 --uu uuuu

TRISB 1111 1111 1111 1111 uuuu uuuu

TRISC 1111 1111 1111 1111 uuuu uuuu

TRISD 1111 1111 1111 1111 uuuu uuuu

TRISE 0000 -111 0000 -111 uuuu -uuu

TRISF 1111 1111 1111 1111 uuuu uuuu

TRISG 1111 1111 1111 1111 uuuu uuuu

TXREG 0000 0000 0000 0000 uuuu uuuu

TXSTA 0000 -010 0000 -010 uuuu -uuu

VRCON 000- 0000 000- 0000 uuu- uuuu

Wxxxx xxxx uuuu uuuu uuuu uuuu

Table 3-4: Initialization Conditions for Special Function Registers (Cont.’d)

Brown-out Reset

MCLR Reset during:

- normal operation

- SLEEP or

WDT Reset

Wake-up from SLEEP

through:

- interrupt

- WDT time-out

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

3: See Table 3-3 for reset value for speciﬁc condition.

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-14  1997 Microchip Technology Inc.

3.3.1 Power Control (PCON) and STATUS Registers

The Power Control (PCON) register contains a status bit to allow differentiation between a

P o wer-on Reset (POR) to an e xternal MCLR Reset or WDT Reset. It also contains a status bit to

determine if a Brown-out Reset (BOR) occurred. The power control/status register, PCON has

up to four bits.

The BOR (Brown-out Reset) bit, is unknown on a Power-on-reset. It must initially be set by the

user and check ed on subsequent resets to see if BOR = '0' indicating that a Brown-out Reset has

occurred. The BOR status bit is a “don’t care” bit and is not necessarily predictable if the

brown-out circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

The POR (P o wer-on Reset) bit, is cleared on a P o wer-on Reset and is unaff ected otherwise. The

user sets this bit following a Power-on Reset. On subsequent resets if POR is ‘0’, it will indicate

that a Power-on Reset must have occurred.

The PER (P arity Error Reset) bit, is cleared on a P arity Error Reset and must be set by user soft-

ware. It will also be set on a Power-on Reset.

The MPEEN (Memory Parity Error Enable) bit, reﬂects the status of the MPEEN bit in conﬁgur a-

tion word. It is unaffected by any reset or interrupt.

Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked

on subsequent resets to see if BOR is clear, indicating a brown-out has occurred.

The BOR status bit is a don't care and is not necessarily predictable if the brown-out

circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

R-u U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

MPEEN — — — — PER POR BOR

bit 7 bit 0

bit 7 MPEEN: Memory Parity Error Circuitry Status bit

This bit reﬂects the value of the MPEEN conﬁguration bit.

bit 6:3 Unimplemented: Read as '0'

bit 2 PER: Memory Parity Error Reset Status bit

1 = No parity error reset occurred

0 = A program memory fetch parity error occurred

(must be set in software after a Power-on Reset or Parity Error Reset occurs)

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset or

Power-on Reset occurs)

Legend

R = Readable bit W = Writable bit u = unchanged bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note: Not all bits may be implemented.

 1997 Microchip Technology Inc. DS31003A-page 3-15

Section 3. Reset

Reset

The STATUS register contains two bits (TO and PD), which when used in conjunction with the

PCON register bits provide the user with enough inf ormation to determine the cause of the reset.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC C

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit clear.

bit 6:5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. For devices with only Bank0 and Bank1 the IRP bit is reserved,

always maintain this bit clear.

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carr y/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-16  1997 Microchip Technology Inc.

3.4 Design Tips

Question 1:

When m y system is subjected to an en vironment with ESD and EMI, it oper -

ates erratically.

Answer 1:

If the device you are using does not hav e ﬁltering to the on-chip master clear circuit (Appendix C),

ensure that proper e xternal ﬁltering is placed on the MCLR pin to remove narro w pulses . Electri-

cal Speciﬁcation parameter 35 speciﬁes the pulse width required to cause a reset.

Question 2:

With JW (windowed) de vices my system resets and operates pr operly. With

an OTP device, my system does not operate properly.

Answer 2:

The most common reason f or this is that the windo wed device (JW) has not had its window cov-

ered. The bac kground light causes the de vice to power-up in a diff erent state than would typically

be seen in a device where no light is present. In most cases all the General Purpose RAM and

Special Function Registers were not initialized properly.

 1997 Microchip Technology Inc. DS31003A-page 3-17

Section 3. Reset

Reset

3.5 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to Resets are:

Title Application Note #

P ower-up Troub le Shooting AN607

Power-up Considerations AN522

PICmicro MID-RANGE MCU FAMILY

DS31003A-page 3-18  1997 Microchip Technology Inc.

3.6 Revision History

Revision A

This is the initial released revision of the Reset description.

 1997 Microchip Technology Inc. DS31004A page 4-1

Architecture

Section 4. Architecture

HIGHLIGHTS

This section of the manual contains the following major topics:

4.1 Introduction....................................................................................................................4-2

4.2 Clocking Scheme/Instruction Cycle ...............................................................................4-5

4.3 Instruction Flow/Pipelining.............................................................................................4-6

4.4 I/O Descriptions .............................................................................................................4-7

4.5 Design Tips..................................................................................................................4-12

4.6 Related Application Notes............................................................................................4-13

4.7 Revision History...........................................................................................................4-14

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-2  1997 Microchip Technology Inc.

4.1 Introduction

The high perfor mance of the PICmicro™ devices can be attributed to a number of architectural

features commonly found in RISC microprocessors. These include:

• Harvard architecture

• Long W ord Instructions

• Single W ord Instructions

• Single Cycle Instructions

• Instruction Pipelining

• Reduced Instruction Set

• Register File Architecture

• Orthogonal (Symmetric) Instructions

Figure 4-2 shows a simple core memory bus arrangement for Mid-Range MCU devices.

Harvard Architecture:

Harv ard architecture has the program memory and data memory as separate memories and are

accessed from separate b uses. This improv es bandwidth ov er traditional v on Neumann architec-

ture in which program and data are fetched from the same memory using the same bus. To exe-

cute an instruction, a von Neumann machine must mak e one or more (generally more) accesses

across the 8-bit bus to f etch the instruction. Then data ma y need to be f etched, operated on, and

possibly written. As can be seen from this description, that bus can be e xtremely conjested. While

with a Harvard architecture, the instruction is fetched in a single instruction cycle (all 14-bits).

While the program memory is being accessed, the data memor y is on an independent bus and

can be read and written. These separated buses allow one instruction to execute while the next

instruction is fetched. A comparison of Harvard vs. von-Neumann architectures is shown in

Figure 4-1.

Figure 4-1: Harvard vs. von Neumann Block Architectures

Long W ord Instructions:

Long word instructions hav e a wider (more bits) instruction bus than the 8-bit Data Memory Bus.

This is possible because the tw o b uses are separ ate . This further allows instructions to be sized

differently than the 8-bit wide data word which allows a more efﬁcient use of the program mem-

ory, since the program memory width is optimized to the architectural requirements.

Single W ord Instructions:

Single Word instruction opcodes are 14-bits wide making it possible to have all single word

instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single

cycle. With single word instructions, the number of words of program memor y locations equals

the number of instructions for the device. This means that all locations are valid instructions.

Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device

with 4-KBytes of program memory would allow approximately 2K of instructions. This 2:1 r atio is

generalized and dependent on the application code. Since each instruction may take multiple

bytes, there is no assurance that each location is a valid instruction.

Program

Memory

Data

Memory

Program

Memory

and

Data

CPU CPU 8

814

Harvard von-Neumann

 1997 Microchip Technology Inc. DS31004A-page 4-3

Section 4. Architecture

Architecture

Instruction Pipeline:

The instruction pipeline is a two-stage pipeline which ov erlaps the fetch and e x ecution of instruc-

tions. The f etch of the instruction takes one TCY, while the ex ecution takes another TCY. However,

due to the overlap of the fetch of current instruction and execution of previous instruction, an

instruction is fetched and another instruction is executed every single TCY.

Single Cycle Instructions:

With the Program Memory bus being 14-bits wide, the entire instruction is fetched in a single

machine cycle (TCY). The instr uction contains all the infor mation required and is executed in a

single cycle. There may be a one cycle delay in execution if the result of the instruction modiﬁed

the contents of the Program Counter. This requires the pipeline to be ﬂushed and a new instruc-

tion to be fetched.

Reduced Instruction Set:

When an instruction set is well designed and highly or thogonal (symmetric), fewer instructions

are required to perf orm all needed tasks. With fe wer instructions, the whole set can be more rap-

idly learned.

The register ﬁles/data memory can be directly or indirectly addressed. All special function regis-

ters, including the program counter, are mapped in the data memory.

Orthogonal (Symmetric) Instructions:

Orthogonal instructions make it possible to carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of “special instructions” make programming

simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly. The mid-range instruc-

tion set uses only two non-register oriented instructions, which are used for tw o of the cores f ea-

tures. One is the SLEEP instruction which places the device into the low est pow er use mode. The

other is the CLRWDT instruction which veriﬁes the chip is operating properly by preventing the

on-chip Watchdog Timer (WDT) from overﬂowing and resetting the device.

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-4  1997 Microchip Technology Inc.

Figure 4-2: General Mid-range PICmicro Block Diagram

EPROM

Program

Memory

8K x 14

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

368 x 8

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4

RA5

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

Brown-out

Reset (2)

Note 1: The high order bits of the Direct Address for the RAM are from the STATUS register.

2: Not all devices have this feature, please refer to device data sheet.

3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions.

The multiplexing combinations are device dependent.

USARTs

CCPs Comparators Synchronous

A/DTimer0 Timer1 Timer2

Serial Port

RA3

RA2

RA1

RA0

up to

RB0/INT

RB1

RB2

RB3

RB4

RB5

RB6

RB7

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

Data EEPROM

up to

256 x 8

Other LCD Drivers

Voltage

Reference

Modules

Peripheral Modules (Note 3)

PORTF RF0

RF1

RF2

RF3

RF4

RF5

RF6

RF7

PORTG RG0

RG1

RG2

RG3

RG4

RG5

RG6

RG7

Parallel

Slave Port

General Purpose I/O

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

Internal

RC clock (2)

(Note 3)

 1997 Microchip Technology Inc. DS31004A-page 4-5

Section 4. Architecture

Architecture

4.2 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping

quadrature clocks, namely Q1, Q2, Q3, and Q4. Inter nally, the program counter (PC) is incre-

mented every Q1, and the instr uction is fetched from the program memory and latched into the

instruction register in Q4. The instruction is decoded and executed during the following Q1

through Q4. The clocks and instruction execution ﬂow are illustrated in Figure 4-3, and

Example 4-1.

Figure 4-3: Clock/Instruction Cycle

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

TCY1TCY2TCY3

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-6  1997 Microchip Technology Inc.

4.3 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). F etch takes one instruction

cycle while decode and e xecute takes another instruction cycle. Ho wev er , due to Pipelining, each

instruction effectively executes in one cycle. If an instruction causes the program counter to

change (e.g. GOTO) then an extra cycle is required to complete the instruction (Example 4-1).

The instruction fetch begins with the program counter incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in

cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data

memory is read during Q2 (operand read) and written during Q4 (destination write).

Example 4-1 shows the operation of the two stage pipeline for the instruction sequence shown.

At time TCY0, the ﬁrst instruction is f etched from progr am memory. During TCY1, the ﬁrst instruc-

tion executes while the second instruction is fetched. During TCY2, the second instruction exe-

cutes while the third instruction is fetched. During TCY3, the f ourth instruction is fetched while the

third instruction (CALL SUB_1) is executed. When the third instruction completes execution, the

CPU forces the address of instruction f our onto the Stack and then changes the Program Counter

(PC) to the address of SUB_1. This means that the instruction that was fetched during TCY3 needs

to be “ﬂushed” from the pipeline. During TCY4, instruction four is ﬂushed (e x ecuted as a NOP) and

the instruction at address SUB_1 is fetched. Finally during TCY5, instruction ﬁve is executed and

the instruction at address SUB_1 + 1 is fetched.

Example 4-1: Instruction Pipeline Flow

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

Fetch SUB_1 + 1

 1997 Microchip Technology Inc. DS31004A-page 4-7

Section 4. Architecture

Architecture

4.4 I/O Descriptions

Table 4-1 giv es a brief description of the functions that may be m ultiplex ed to a port pin. Multiple

functions ma y exist on one port pin. When multiple xing occurs, the peripheral module’ s functional

requirements ma y f orce an ov erride of the data direction (TRIS bit) of the port pin (such as in the

A/D and LCD modules).

Table 4-1: I/O Descriptions

Pin Name Pin

Type Buffer

Type Description

Analog Input Channels

AN0 I Analog

AN1 I Analog

AN2 I Analog

AN3 I Analog

AN4 I Analog

AN5 I Analog

AN6 I Analog

AN7 I Analog

AN8 I Analog

AN9 I Analog

AN10 I Analog

AN11 I Analog

AN12 I Analog

AN13 I Analog

AN14 I Analog

AN15 I Analog

AVDD P P Analog Power

AVSS P P Analog Ground

C1 I Analog LCD V oltage Generation

C2 I Analog LCD V oltage Generation

CCP1 I/O ST Capture1 input/Compare1 output/PWM1 output

CCP2 I/O ST Capture2 input/Compare2 output/PWM2 output.

CDAC O Analog A/D ramp current source output. Normally connected to external

capacitor to generate a linear voltage ramp.

CK I/O ST USART Synchronous Clock, always associated with TX pin function

(See related TX, RX, DT)

CLKIN I ST/CMOS External clock source input. Always associated with pin function

OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT pins)

CLKOUT O — Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

Always associated with OSC2 pin function. (See related OSC2,

OSC1)

CMPA O — Comparator A output

CMPB O — Comparator B output

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Analog input or output

I = input O = output

P = Power L = LCD Driver

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-8  1997 Microchip Technology Inc.

COM0 L — LCD Common Driver0

COM1 L — LCD Common Driver1

COM2 L — LCD Common Driver2

COM3 L — LCD Common Driver3

CS I TTL chip select control for parallel slave port (See related RD and WR)

DT I/O ST USART Synchronous Data. Always associated RX pin function. (See

related RX, TX, CK)

GP is a bi-directional I/O port. Some pins of port GP can be software

programmed for internal weak pull-ups on the inputs.

GP0 I/O TTL/ST TTL input buffer as general purpose I/O, Schmitt Trigger input buffer

when used as the serial programming mode.

GP1 I/O TTL/ST TTL input buffer as general pur pose I/O, Schmitt Tr igger input buffer

when used as the serial programming mode.

GP2 I/O ST

GP3 I TTL

GP4 I/O TTL

GP5 I/O TTL

INT I ST External Interrupt

MCLR/VPP I/P ST Master clear (reset) input or programming voltage input. This pin is

an active low reset to the device.

NC — — These pins should be left unconnected.

OSC1 I ST/CMOS Oscillator crystal input or external clock source input. ST buff er when

conﬁgured in RC mode. CMOS otherwise.

OSC2 O — Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

PBTN I ST Input with weak pull-up resistor , can be used to gener ate an interrupt.

PSP0 I/O TTL Parallel Slave Port for interfacing to a microprocessor port. These

pins have TTL input buffers when PSP module is enabled.

PSP1 I/O TTL

PSP2 I/O TTL

PSP3 I/O TTL

PSP4 I/O TTL

PSP5 I/O TTL

PSP6 I/O TTL

PSP7 I/O TTL PORTA is a bi-directional I/O port.

RA0 I/O TTL

RA1 I/O TTL

RA2 I/O TTL

RA3 I/O TTL

RA4 I/O ST RA4 is an open drain when conﬁgured as output.

RA5 I/O TTL

Table 4-1: I/O Descriptions (Cont.’d)

Pin Name Pin

Type Buffer

Type Description

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Analog input or output

I = input O = output

P = Power L = LCD Driver

 1997 Microchip Technology Inc. DS31004A-page 4-9

Section 4. Architecture

Architecture

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-ups on all inputs.

RB0 I/O TTL

RB1 I/O TTL

RB2 I/O TTL

RB3 I/O TTL

RB4 I/O TTL Interrupt on change pin.

RB5 I/O TTL Interrupt on change pin.

RB6 I/O TTL/ST Interrupt on change pin. Serial programming clock. TTL input

buffer as general purpose I/O, Schmitt Trigger input buffer when

used as the serial programming clock.

RB7 I/O TTL/ST Interrupt on change pin. Serial programming data. TTL input

buffer as general purpose I/O, Schmitt Trigger input buffer when

used as the serial programming data.

PORTC is a bi-directional I/O port.

RC0 I/O ST

RC1 I/O ST

RC2 I/O ST

RC3 I/O ST

RC4 I/O ST

RC5 I/O ST

RC6 I/O ST

RC7 I/O ST

RD I TTL Read control for parallel slave port (See also WR and CS pins)

PORTD is a bi-directional I/O port.

RD0 I/O ST

RD1 I/O ST

RD2 I/O ST

RD3 I/O ST

RD4 I/O ST

RD5 I/O ST

RD6 I/O ST

RD7 I/O ST PORTE is a bi-directional I/O port.

RE0 I/O ST

RE1 I/O ST

RE2 I/O ST

RE3 I/O ST

RE4 I/O ST

RE5 I/O ST

RE6 I/O ST

RE7 I/O ST

Table 4-1: I/O Descriptions (Cont.’d)

Pin Name Pin

Type Buffer

Type Description

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Analog input or output

I = input O = output

P = Power L = LCD Driver

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-10  1997 Microchip Technology Inc.

REFA O CMOS Programmable reference A output.

REFB O CMOS Programmable reference B output.

PORTF is a digital input or LCD Segment Driver Port

RF0 I/O ST

RF1 I/O ST

RF2 I/O ST

RF3 I/O ST

RF4 I/O ST

RF5 I/O ST

RF6 I/O ST

RF7 I/O ST PORTG is a digital input or LCD Segment Driver Port

RG0 I/O ST

RG1 I/O ST

RG2 I/O ST

RG3 I/O ST

RG4 I/O ST

RG5 I/O ST

RG6 I/O ST

RG7 I/O ST

RX I ST USART Asynchronous Receive

SCL I/O ST Synchronous serial clock input/output for I2C mode.

SCLA I/O ST Synchronous serial clock for I2C interface.

SCLB I/O ST Synchronous serial clock for I2C interface.

SDA I/O ST I2C™ Data I/O

SDAA I/O ST Synchronous serial data I/O for I2C interface

SDAB I/O ST Synchronous serial data I/O for I2C interface

SCK I/O ST Synchronous serial clock input/output for SPI mode.

SDI I ST SPI Data In

SDO O — SPI Data Out (SPI mode)

SS I ST SPI Slave Select input

SEG00 to

SEG31 I/L ST LCD Segment Driver00 through Driver31.

SUM O AN AN1 summing junction output. This pin can be connected to an exter-

nal capacitor for averaging small duration pulses.

T0CKI I ST Timer0 external clock input

T1CKI I ST Timer1 external clock input

T1OSO O CMOS Timer1 oscillator output

T1OSI I CMOS Timer1 oscillator input

TX O — USART Asynchronous Transmit (See related RX)

Table 4-1: I/O Descriptions (Cont.’d)

Pin Name Pin

Type Buffer

Type Description

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Analog input or output

I = input O = output

P = Power L = LCD Driver

I2C is a trademark of Philips Corporation.

 1997 Microchip Technology Inc. DS31004A-page 4-11

Section 4. Architecture

Architecture

VLCD1 P — LCD Voltage

VLCD2 P — LCD Voltage

VLCD3 P — LCD Voltage

VLCD ADJ I Analog LCD V oltage Generation

VREF I Analog Analog High Voltage Reference input.

DR reference voltage output on devices with comparators.

VREF+ I Analog Analog High Voltage Reference input.

Usually multiplexed onto an analog pin.

VREF- I Analog Analog Low Voltage Reference input.

Usually multiplexed onto an analog pin.

VREG O — This pin is an output to control the gate of an external N-FET

for voltage regulation.

VSS P — Ground reference for logic and I/O pins.

VDD P — Positive supply for logic and I/O pins.

WR I TTL Write control for parallel slave port (See CS and RD pins also).

Table 4-1: I/O Descriptions (Cont.’d)

Pin Name Pin

Type Buffer

Type Description

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Analog input or output

I = input O = output

P = Power L = LCD Driver

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-12  1997 Microchip Technology Inc.

4.5 Design Tips

No related design tips at this time.

 1997 Microchip Technology Inc. DS31004A-page 4-13

Section 4. Architecture

Architecture

4.6 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to Architecture

are:

Title Application Note #

No related application notes at this time.

PICmicro MID-RANGE MCU FAMILY

DS31004A-page 4-14  1997 Microchip Technology Inc.

4.7 Revision History

Revision A

This is the initial released revision of the PICmicro’s Architecture description.

 1997 Microchip Technology Inc.   DS31005A page 5-1
M
CPU and ALU
5
Section 5. CPU and ALU
HIGHLIGHTS
This section of the manual contains the following major topics:
5.1 Introduction....................................................................................................................5-2
5.2 General Instruction Format............................................................................................5-4
5.3 Central Processing Unit (CPU)......................................................................................5-4
5.4 Instruction Clock ............................................................................................................5-4
5.5 Arithmetic Logical Unit (ALU).........................................................................................5-5
5.6 STATUS Register ...........................................................................................................5-6
5.7 OPTION_REG Register.................................................................................................5-8
5.8 PCON Register..............................................................................................................5-9
5.9 Design Tips..................................................................................................................5-10
5.10 Related Application Notes............................................................................................5-11
5.11 Revision History...........................................................................................................5-12

PICmicro MID-RANGE MCU FAMILY

DS31005A-page 5-2  1997 Microchip Technology Inc.

5.1 Introduction

The Central Processing Unit (CPU) is responsib le f or using the inf ormation in the program mem-

ory (instructions) to control the operation of the device. Many of these instructions operate on

data memory. To operate on data memory, the Arithmetic Logical Unit (ALU) is required. In addi-

tion to performing arithmetical and logical operations, the ALU controls status bits (which are

found in the STATUS register). The result of some instructions force status bits to a v alue depend-

ing on the state of the result.

The machine codes that the CPU recognizes are show in Table 5-1 (as well as the instruction

mnemonics that the MPASM uses to generate these codes).

 1997 Microchip Technology Inc. DS31005A-page 5-3

Section 5. CPU and ALU

CPU and ALU

Table 5-1: Mid-Range MCU Instruction Set

Mnemonic,

Operands Description Cycles 14-Bit Instruction Word Status

Bits

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

bfff-

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear W atchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is

driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

PICmicro MID-RANGE MCU FAMILY

DS31005A-page 5-4  1997 Microchip Technology Inc.

5.2 General Instruction Format

The Mid-Range MCU instructions can be broken down into four general formats as shown in

Figure 5-1. As can be seen the opcode f or the instruction v aries from 3-bits to 6-bits. This v ariable

opcode size is what allows 35 instructions to be implemented.

Figure 5-1: General Format for Instructions

5.3 Central Processing Unit (CPU)

The CPU can be thought of as the “br ains” of the device. It is responsible for fetching the correct

instruction for execution, decoding that instruction, and then executing that instruction.

The CPU sometimes works in conjunction with the ALU to complete the ex ecution of the instruc-

tion (in arithmetic and logical operations).

The CPU controls the program memory address bus, the data memory address bus, and

accesses to the stack.

5.4 Instruction Clock

Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4). The Q cycle time is the same

as the device oscillator cycle time (TOSC). The Q cycles provide the timing/designation for the

Decode, Read, Process Data, Write, etc., of each instruction cycle. The f ollo wing diagram sho ws

the relationship of the Q cycles to the instruction cycle.

The four Q cycles that make up an instruction cycle (TCY) can be generalized as:

Q1: Instruction Decode Cycle or forced No operation

Q2: Instruction Read Data Cycle or No operation

Q3: Process the Data

Q4: Instruction Write Data Cycle or No operation

Each instruction will show a detailed Q cycle operation for the instruction.

Figure 5-2: Q Cycle Activity

Byte-oriented ﬁle register operations

13 8 7 6 0 d = 0 for destination W

OPCODE d f (FILE #) d = 1 for destination f

f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #) b = 3-bit bit address

f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal) k = 8-bit immediate value

13 11 10 0

OPCODE k (literal) k = 11-bit immediate value

General

CALL and GOTO instructions only

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

TCY1TCY2TCY3

Tosc

 1997 Microchip Technology Inc. DS31005A-page 5-5

Section 5. CPU and ALU

CPU and ALU

5.5 Arithmetic Logical Unit (ALU)

PICmicro MCUs contain an 8-bit ALU and an 8-bit working register. The ALU is a general pur-

pose arithmetic and logical unit. It performs arithmetic and Boolean functions between the data

in the working register and any register ﬁle.

Figure 5-3: Operation of the ALU and W Register

The ALU is 8-bits wide and is capable of addition, subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand

instructions, typically one operand is the working register (W register). The other operand is a ﬁle

ister or a ﬁle register.

The W register is an 8-bit w orking register used for ALU oper ations . It is not an addressable reg-

ister.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit

Carry (DC), and Zero (Z) bits in the STATUS register . The C and DC bits operate as a borrow bit

and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for

examples.

W Register

File

d bit, or from instruction

8-bit literal

(from instruction word)

d = '0' or d = '1'

(SFR’s)

and

General

Purpose

RAM

(GPR)

ALU

Literal Instructions

Special

Function

Registers

8-bit register value

(from direct or indirect

address of instruction)

PICmicro MID-RANGE MCU FAMILY

DS31005A-page 5-6  1997 Microchip Technology Inc.

5.6 STATUS Register

The STATUS register, sho wn in Figure 5-1, contains the arithmetic status of the ALU, the RESET

status and the bank select bits for data memory. Since the selection of the Data Memor y banks

is controlled by this register, it is required to be present in every bank. Also , this register is in the

same relative position (offset) in each bank (see Figure 6-5: “Register File Map” in the “Mem-

ory Organization” section).

The STATUS register can be the destination for any instruction, as with any other register. If the

STATUS register is the destination for an instruction that affects the Z, DC or C bits , then the write

to these three bits is disabled. These bits are set or cleared according to the device logic. Fur-

thermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the

STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to

alter the STATUS register because these instr uctions do not affect the Z, C or DC bits from the

STATUS register. For other instructions, not affecting any status bits, see Table 5-1.

Note 1: Some devices do not require the IRP and RP1 (STATUS<7:6>) bits. These bits are

not used by the Section 5. CPU and ALU and should be maintained clear. Use of

these bits as general purpose R/W bits is NOT recommended, since this ma y affect

upward code compatibility with future products.

Note 2: The C and DC bits operate as a borrow and digit borro w bit, respectively, in subtrac-

tion.

 1997 Microchip Technology Inc. DS31005A-page 5-7

Section 5. CPU and ALU

CPU and ALU

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC C

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit clear.

bit 6:5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. For devices with only Bank0 and Bank1 the IRP bit is reserved,

always maintain this bit clear.

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carr y/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31005A-page 5-8  1997 Microchip Technology Inc.

5.7 OPTION_REG Register

The OPTION_REG register is a readable and writable register which contains v arious control bits

to conﬁgure the TMR0/WDT prescaler, the external INT Interrupt, TMR0, and the weak pull-ups

on PORTB.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler

to the Watchdog Timer.

 1997 Microchip Technology Inc. DS31005A-page 5-9

Section 5. CPU and ALU

CPU and ALU

5.8 PCON Register

The Power Control (PCON) register contains ﬂag bit(s), that together with the TO and PD bits,

allows the user to differentiate between the device resets.

Note 1: BOR is unknown on Power-on Reset. It must then be set by the user and checked

on subsequent resets to see if BOR is clear, indicating a brown-out has occurred.

The BOR status bit is a don't care and is not necessarily predictable if the brown-out

circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

Note 2: It is recommended that the POR bit be cleared after a power-on reset has been

detected, so that subsequent power-on resets may be detected.

R-u U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

MPEEN — — — — PER POR BOR

bit 7 bit 0

bit 7 MPEEN: Memory Parity Error Circuitry Status bit

This bit reﬂects the value of the MPEEN conﬁguration bit.

bit 6:3 Unimplemented: Read as '0'

bit 2 PER: Memory Parity Error Reset Status bit

1 = No error occurred

0 = A program memory fetch parity error occurred

(must be set in software after a Power-on Reset occurs)

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31005A-page 5-10  1997 Microchip Technology Inc.

5.9 Design Tips

Question 1:

My program algorithm does not seem to function correctly.

Answer 1:

1. The destination of the instruction may be specifying the W register (d = 0) instead of the

ﬁle register (d = 1).

2. The register bank select bits (RP1:RP0 or IRP) ma y not be properly selected. Also if inter-

rupts are used, the register bank select bits may not be properly restored when e xiting the

interrupt handler.

Question 2:

I cannot seem to modify the STATUS register ﬂags.

Answer 2:

if the STATUS register is the destination for an instruction that affects the Z, DC, or C bits, the

write to these bits is disabled. These bits are set or cleared based on device logic. Therefore, to

modify bits in the STATUS register it is recommended to use the BCF and BSF instructions.

 1997 Microchip Technology Inc. DS31005A-page 5-11

Section 5. CPU and ALU

CPU and ALU

5.10 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to the CPU or

the ALU are:

Title Application Note #

Fixed Point Routines AN617

IEEE 754 Compliant Floating Point Routines AN575

Digital Signal Processing with the PIC16C74 AN616

Math Utility Routines AN544

Implementing IIR Digital Filters AN540

Implementation of Fast Fourier Transforms AN542

Tone Generation AN543

Servo Control of a DC Brushless Motor AN532

Implementation of the Data Encryption Standard using the PIC17C42 AN583

PIC16C5X / PIC16CXX Utility Math Routines AN526

Real Time Operating System for PIC16/17 AN585

PICmicro MID-RANGE MCU FAMILY

DS31005A-page 5-12  1997 Microchip Technology Inc.

5.11 Revision History

Revision A

This is the initial released revision of the CPU and ALU description.

 1997 Microchip Technology Inc. DS31006A page 6-1

Memory

Organization

Section 6. Memory Organization

HIGHLIGHTS

This section of the manual contains the following major topics:

6.1 Introduction....................................................................................................................6-2

6.2 Program Memory Organization......................................................................................6-2

6.3 Data Memory Organization............................................................................................6-8

6.4 Initialization..................................................................................................................6-14

6.5 Design Tips..................................................................................................................6-16

6.6 Related Application Notes............................................................................................6-17

6.7 Revision History...........................................................................................................6-18

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-2  1997 Microchip Technology Inc.

6.1 Introduction

There are two memory blocks in the Section 6. Memory Organization; prog ram memory and data

memor y. Each block has its own bus, so that access to each block can occur dur ing the same

oscillator cycle.

The data memory can further be broken down into General Purpose RAM and the Special Func-

tion Registers (SFRs). The operation of the SFRs that control the “core” are described here. The

SFRs used to control the peripheral modules are described in the section discussing each indi-

vidual peripheral module.

6.2 Program Memory Organization

Mid-Range MCU de vices have a 13-bit prog r am counter capable of addressing an 8K x 14 pro-

gram memory space. The width of the program memory bus (instruction word) is 14-bits. Since

all instructions are a single word, a device with an 8K x 14 prog ram memory has space for 8K of

instructions. This makes it much easier to determine if a device has sufﬁcient program memor y

for a desired application.

This program memory space is divided into four pages of 2K words each (0h - 7FFh, 800h -

FFFh, 1000h - 17FFh, and 1800h - 1FFFh). Figure 6-1 shows the program memory map as well

as the 8 le vel deep hardw are stac k. Depending on the device , only a portion of this memory may

be implemented. Please refer to the device data sheet for the available memory.

To jump between the program memory pages, the high bits of the Program Counter (PC) must

be modiﬁed. This is done by writing the desired value into a SFR called PCLATH (Program

Counter Latch High). If sequential instructions are executed, the program counter will cross the

page boundaries without any user intervention. For devices that have less than 8K words,

accessing a location above the physically implemented address will cause a wraparound. That

is, in a 4K-word device accessing 17FFh actually addresses 7FFh. 2K-w ord devices (or less) do

not require paging.

 1997 Microchip Technology Inc. DS31006A-page 6-3

Section 6. Memory Organization

Memory

Organization

Figure 6-1: Architectural Program Memory Map and Stack

PC<12:8>

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt V ector

On-chip Program

Memory (Page 1)

Memory (Page 0)

CALL, RETURN

RETFIE, RETLW

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

0FFFh

1000h

17FFh

1800h

PC<12:0> PCL

PCLATH

Note 1: Not all devices implement the entire program memory space

2: Calibration Data may be programmed into program memory locations.

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-4  1997 Microchip Technology Inc.

6.2.1 Reset Vector

On any device, a reset forces the Program Counter (PC) to address 0h. We call this address the

“Reset Vector Address” since this is the address that program execution will branch to when a

device reset occurs.

Any reset will also clear the contents of the PCLATH register. This means that any branch at the

Reset Vector Address (0h) will jump to that location in PAGE0 of the program memory.

6.2.2 Interrupt Vector

When an interrupt is acknowledged the PC is f orced to address 0004h. W e call this the “Interrupt

Vector Address”. When the PC is forced to the interrupt vector, the PCLATH register is not mod-

iﬁed. Once in the service interrupt routine (ISR), this means that before any write to the PC, the

PCLATH register should be written with the value that will specify the desired location in program

memory. Before the PCLATH register is modiﬁed b y the Interrupt Service Routine (ISR) the con-

tents of the PCLATH may need to be sa ved, so it can be restored before returning from the ISR.

6.2.3 Calibration Information

Some devices have calibration information stored in their program memory. This information is

programmed b y Microchip when the de vice is under ﬁnal test. The use of these values allo ws the

application to achie ve better results . The calibration inf ormation is typically at the end of program

memory, and is implemented as a RETLW instruction with the literal value being the speciﬁed cal-

ibration information.

Note: For windowed devices, write down all calibration values BEFORE erasing. This

allows the device’s calibration values to be restored when the device is re-pro-

grammed. When possible writing the values on the package is recommended.

 1997 Microchip Technology Inc. DS31006A-page 6-5

Section 6. Memory Organization

Memory

Organization

6.2.4 Program Counter (PC)

The program counter (PC) speciﬁes the address of the instruction to f etch for ex ecution. The PC

is 13-bits wide. The low b yte is called the PCL register . This register is readab le and writable. The

high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly

readable or writable. All updates to the PCH register go through the PCLATH register.

Figure 6-2 shows the four situations for the loading of the PC. Situation 1 shows how the PC is

loaded on a write to PCL (PCLATH<4:0> → PCH). Situation 2 shows how the PC is loaded during

a GOTO instruction (PCLATH<4:3> → PCH). Situation 3 shows how the PC is loaded during a

CALL instruction (PCLATH<4:3> → PCH), with the PC loaded (PUSHed) onto the Top of Stack.

Situation 4 shows how the PC is loaded during one of the return instructions where the PC

loaded (POPed) from the Top of Stack.

Figure 6-2: Loading of PC In Different Situations

PC 12 8 7 0

5PCLATH<4:0>

PCLATH ALU result

Opcode <10:0>

PC 12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

Situation 1 - Instruction with PCL as destination

Situation 2 - GOTO Instruction

STACK (13-bits x 8)

Top of STACK

STACK (13-bits x 8)

Top of STACK

Opcode <10:0>

PC 12 11 10 0

PCLATH<4:3>

PCLATH

PCH PCL

Situation 3 - CALL Instruction STACK (13-bits x 8)

Top of STACK

Opcode <10:0>

PC 12 11 10 0

PCLATH

PCH PCL

Situation 4 - RETURN, RETFIE, or RETLW Instruction STACK (13-bits x 8)

Top of STACK

Note: PCLATH is never updated with the contents of PCH.

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-6  1997 Microchip Technology Inc.

6.2.4.1 Computed GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL).

When doing a table read using a computed GOTO method, care should be exercised if the table

location crosses a PCL memory boundary (each 256 byte block).

6.2.5 Stack

The stack allows a combination of up to 8 program calls and interrupts to occur. The stack con-

tains the return address from this branch in program execution.

Mid-Range MCU de vices have an 8-level deep x 13-bit wide hardw are stack. The stack space is

not part of either program or data space and the stac k pointer is not readable or writab le. The PC

is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch.

The stack is POP ed in the e vent of a RETURN, RETLW or a RETFIE instruction e xecution. PCLATH

is not modiﬁed when the stack is PUSHed or POPed.

After the stack has been PUSHed eight times , the ninth push overwrites the value that w as stored

from the ﬁrst push. The tenth push overwrites the second push (and so on). An example of the

overwriting of the stack is shown in Figure 6-3.

Figure 6-3: Stack Modiﬁcation

Note: Any write to the Program Counter (PCL), will cause the lower ﬁve bits of the PCLATH

to be loaded into PCH.

Push1 Push9

Push2 Push10

Push3

Push4

Push5

Push6

Push7

Push8

Top of STACK

STACK

Note 1: There are no status bits to indicate stack overﬂow or stack underﬂow conditions.

Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that

occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions,

or the vectoring to an interrupt address.

 1997 Microchip Technology Inc. DS31006A-page 6-7

Section 6. Memory Organization

Memory

Organization

6.2.6 Program Memory Paging

Some devices have program memory sizes greater then 2K words, but the CALL and GOTO

instructions only have a 11-bit address range. This 11-bit address range allows a branch within

a 2K program memory page size. To allow CALL and GOTO instructions to address the entire 1K

program memory address range, there must be another tw o bits to specify the progr am memory

page. These paging bits come from the PCLATH<4:3> bits (Figure 6-2). When doing a CALL or

GOTO instruction, the user must ensure that page bits (PCLATH<4:3>) are programmed so that

the desired program memory page is addressed (Figure 6-2). When one of the return instruc-

tions is executed, the entire 13-bit PC is POPed from the stack. Therefore, manipulation of the

PCLATH<4:3> is not required for the return instructions.

Example 6-1 shows the calling of a subroutine in page 1 of the program memory. This example

assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are

used).

Example 6-1: Call of a Subroutine in Page1 from Page0

Note: Devices with program memory sizes 2K words and less, ignore both paging bits

(PCLATH<4:3>), which are used to access program memory when more than one

page is available. The use of PCLATH<4:3> as general purpose read/write bits (for

these de vices) is not recommended since this may affect upward compatibility with

future products.

Devices with program memory sizes between 2K words and 4K words, ignore the

paging bit (PCLATH<4>), which is used to access program memory pages 2 and 3

(1000h - 1FFFh). The use of PCLATH<4> as a general pur pose read/write bit (for

these de vices) is not recommended since this may affect upward compatibility with

future products.

ORG 0x500

BSF PCLATH,3 ; Select Page1 (800h-FFFh)

CALL SUB1_P1 ; Call subroutine in Page1 (800h-FFFh)

: ;

ORG 0x900 ;

SUB1_P1: ; called subroutine Page1 (800h-FFFh)

: ;

RETURN ; return to Call subroutine in Page0 (000h-7FFh)

;

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-8  1997 Microchip Technology Inc.

6.3 Data Memory Organization

Data memor y is made up of the Special Function Registers (SFR) area, and the General Pur-

pose Registers (GPR) area. The SFRs control the operation of the device, while GPRs are the

general area for data storage and scratch pad operations.

The data memory is bank ed for both the GPR and SFR areas. The GPR area is banked to allow

greater than 96 bytes of general pur pose RAM to be addressed. SFRs are for the registers that

control the peripheral and core functions. Banking requires the use of control bits for bank selec-

tion. These control bits are located in the STATUS Register (STATUS<7:5>). Figure 6-5 shows

one of the data memory map organizations, this organization is device dependent.

To move v alues from one register to another register , the value m ust pass through the W register .

This means that for all register-to-register moves, two instruction cycles are required.

The entire data memory can be accessed either directly or indirectly. Direct addressing may

require the use of the RP1:RP0 bits. Indirect addressing requires the use of the File Select Reg-

ister (FSR). Indirect addressing uses the Indirect Register P ointer (IRP) bit of the STATUS regis-

ter for accesses into the Bank0 / Bank1 or the Bank2 / Bank3 areas of data memory.

6.3.1 General Purpose Registers (GPR)

Some Mid-Range MCU de vices ha ve banked memory in the GPR area. GPRs are not initialized

by a Power-on Reset and are unchanged on all other resets.

The register ﬁle can be accessed either directly, or using the File Select Register FSR, indirectly.

Some devices have areas that are shared across the data memory banks, so a read / write to

that area will appear as the same location (value) regardless of the current bank. W e ref er to this

area as the Common RAM.

6.3.2 Special Function Registers (SFR)

The SFRs are used by the CPU and Peripheral Modules for controlling the desired operation of

the device. These registers are implemented as static RAM.

The SFRs can be classiﬁed into two sets, those associated with the “core” function and those

related to the peripheral functions. Those registers related to the “core” are described in this sec-

tion, while those related to the operation of the peripheral features are described in the section

of that peripheral feature.

All Mid-Range MCU devices have banked memory in the SFR area. Switching between these

banks requires the RP0 and RP1 bits in the STATUS register to be conﬁgured for the desired

bank. Some SFRs are initialized by a Power-on Reset and other resets, while other SFRs are

unaffected.

The register ﬁle can be accessed either directly, or using the File Select Register FSR, indirectly.

Note: The Special Function Register (SFR) Area may have General Purpose Registers

(GPRs) mapped in these locations.

 1997 Microchip Technology Inc. DS31006A-page 6-9

Section 6. Memory Organization

Memory

Organization

6.3.3 Banking

The data memory is partitioned into four banks. Each bank contains General Purpose Registers

and Special Function Registers. Switching between these banks requires the RP0 and RP1 bits

in the STATUS register to be conﬁgured for the desired bank when using direct addressing. The

IRP bit in the STATUS register is used for indirect addressing.

Table 6-1: Direct and Indirect Addressing of Banks

Each Bank e xtends up to 7Fh (128 bytes). The lower locations of each bank are reserved f or the

Special Function Registers. Above the Special Function Registers are General Pur pose Regis-

ters. All data memory is implemented as static RAM. All Banks may contain special function reg-

isters. Some “high use” special function registers from Bank0 are mirrored in the other banks for

code reduction and quicker access.

Through the evolution of the products, there are a f ew variations in the la yout of the Data Memory .

The data memory organization that will be the standard for all new devices is shown in

Figure 6-5. This Memory map has the last 16-bytes mapped across all memory banks. This is to

reduce the software o v erhead f or conte xt switching. The registers in bold will be in ev ery device .

The other registers are peripheral dependent. Not every peripheral’s registers are shown,

because some ﬁle addresses hav e a diff erent registers from those shown. As with all the ﬁgures,

tables , and speciﬁcations presented in this reference guide, v erify the details with the device spe-

ciﬁc data sheet.

Figure 6-4: Direct Addressing

Accessed

Bank Direct

(RP1:RP0) Indirect

(IRP)

00 00

10 1

21 01

31 1

Data

Memory

Direct Addressing

bank select location select

RP1 RP0 6 0

from opcode

00 01 10 11

7Fh

00h

7Fh Bank0 Bank1 Bank2 Bank3

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-10  1997 Microchip Technology Inc.

Figure 6-5: Register File Map

File

Address File

Address

INDF 00h INDF 80h INDF 100h INDF 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h 105h 185h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h PORTF 107h TRISF 187h

PORTD 08h TRISD 88h PORTG 108h TRISG 188h

PORTE 09h TRISE 89h 109h 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch 10Ch 18Ch

PIR2 0Dh PIE2 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh 10Eh 18Eh

TMR1H 0Fh OSCCAL 8Fh 10Fh 18Fh

T1CON 10h 90h 110h 190h

TMR2 11h 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD 93h 113h 193h

SSPCON 14h SSPATAT 94h 114h 194h

CCPR1L 15h 95h 115h 195h

CCPR1H 16h 96h 116h 196h

CCP1CON 17h 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah 9Ah 11Ah 19Ah

CCPR2L 1Bh 9Bh 11Bh 19Bh

CCPR2H 1Ch 9Ch 11Ch 19Ch

CCP2CON 1Dh 9Dh 11Dh 19Dh

ADRES 1Eh 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

Registers (2)

20h General

Purpose

Registers (3)

A0h

EFh

General

Purpose

Registers (3)

120h

16Fh

General

Purpose

Registers (3)

1A0h

1EFh

7Fh

Mapped in

Bank0

70h - 7Fh (4)

F0h

FFh

Mapped in

Bank0

70h - 7Fh (4)

170h

17Fh

Mapped in

Bank0

70h - 7Fh (4)

1F0h

1FFh

Bank0 Bank1 Bank2 (5) Bank3

(5)

Note 1: Registers in BOLD will be present in every device.

2: Not all locations may be implemented. Unimplemented locations will read as '0'.

3: These locations may not be implemented. Depending on the device, accesses to the unimplemented loca-

tions operate differently. Please refer to the speciﬁc device data sheet for details.

4: Some device do not map these registers into Bank0. In devices where these registers are mapped into

Bank0, these registers are referred to as common RAM

5: Some devices may not implement these banks. Locations in unimplemented banks will read as ’0’.

6: General Purpose Registers (GPRs) may be located in the Special Function Register (SFR) area.

 1997 Microchip Technology Inc. DS31006A-page 6-11

Section 6. Memory Organization

Memory

Organization

The map in Figure 6-6 shows the register ﬁle memory map of some 18-pin devices.

Unimplemented registers will read as '0'.

Figure 6-6: Register File Map

File

Address File

Address

INDF 00h INDF 80h

TMR0 01h OPTION_REG 81h

PCL 02h PCL 82h

STATUS 03h STATUS 83h

FSR 04h FSR 84h

PORTA 05h TRISA 85h

PORTB 06h TRISB 86h

07h PCON 87h

ADCON0 /

EEDATA (2) 08h ADCON1 /

EECON1 (2) 88h

ADRES /

EEADR (2) 09h ADRES /

EECON2 (2) 89h

PCLATH 0Ah PCLATH 8Ah

INTCON 0Bh INTCON 8Bh

General

Purpose

Registers (3)

0Ch

7Fh

General

Purpose

Registers (4)

8Ch

FFh

Bank0 Bank1

Note 1: Registers in BOLD will be present in every device.

2: These registers may not be implemented, or are implemented as other registers in

some devices.

3: Not all locations may be implemented. Unimplemented locations will read as ’0’.

4: These locations are unimplemented in Bank1. Access to these unimplemented

locations will access the corresponding Bank0 register.

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-12  1997 Microchip Technology Inc.

6.3.4 Indirect Addressing, INDF, and FSR Registers

Indirect addressing is a mode of addressing data memor y where the data memory address in

the instruction is not ﬁxed. An SFR register is used as a pointer to the data memory location that

is to be read or written. Since this pointer is in RAM, the contents can be modiﬁed by the pro-

gram. This can be useful for data tables in the data memory. Figure 6-7 shows the operation of

indirect addressing. This shows the moving of the value to the data memor y address speciﬁed

by the value of the FSR register.

Indirect addressing is possible b y using the INDF register . Any instruction using the INDF register

actually accesses the register pointed to by the File Select Register , FSR. Reading the INDF reg-

ister itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a

no-operation (although status bits may be affected). An effective 9-bit address is generated by

the concatenation of the IRP bit (STA TUS<7>) with the 8-bit FSR register , as shown in Figure 6-8.

Figure 6-7: Indirect Addressing

Opcode Address

File Address = INDF

FSR

Instruction

Executed

Instruction

Fetched

RAM

Opcode File IRP

RP1:RP0 9

Address = 0h

Address != 0

 1997 Microchip Technology Inc. DS31006A-page 6-13

Section 6. Memory Organization

Memory

Organization

Figure 6-8: Indirect Addressing

Example 6-2 shows a simple use of indirect addressing to clear RAM (locations 20h-2Fh) in a

minimum number of instructions. A similar concept could be used to move a deﬁned number of

bytes (block) of data to the USART transmit register (TXREG). The starting address of the block

of data to be transmitted could easily be modiﬁed by the program.

Example 6-2: Indirect Addressing

Data

Memory

Indirect Addressing

IRP FSR register

bank select location select

00 01 10 11 00h

7Fh

00h

7Fh Bank0 Bank1 Bank2 Bank3

BCF STATUS, IRP ; Indirect addressing Bank0/1

MOVLW 0x20 ; Initialize pointer to RAM

MOVWF FSR ;

NEXT CLRF INDF ; Clear INDF register

INCF FSR,F ; Inc pointer

BTFSS FSR,4 ; All done?

GOTO NEXT ; NO, clear next

CONTINUE ;

: ; YES, continue

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-14  1997 Microchip Technology Inc.

6.4 Initialization

Example 6-3 shows how the bank switching occurs for Direct addressing, while Example 6-4

shows some code to do initialization (clearing) of General Purpose RAM.

Example 6-3: Bank Switching

CLRF STATUS ; Clear STATUS register (Bank0)

: ;

BSF STATUS, RP0 ; Bank1

: ;

BCF STATUS, RP0 ; Bank0

: ;

MOVLW 0x60 ; Set RP0 and RP1 in STATUS register, other

XORWF STATUS, F ; bits unchanged (Bank3)

: ;

BCF STATUS, RP0 ; Bank2

: ;

BCF STATUS, RP1 ; Bank0

 1997 Microchip Technology Inc. DS31006A-page 6-15

Section 6. Memory Organization

Memory

Organization

Example 6-4: RAM Initialization

CLRF STATUS ; Clear STATUS register (Bank0)

MOVLW 0x20 ; 1st address (in bank) of GPR area

MOVWF FSR ; Move it to Indirect address register

Bank0_LP

CLRF INDF0 ; Clear GPR at address pointed to by FSR

INCF FSR ; Next GPR (RAM) address

BTFSS FSR, 7 ; End of current bank ? (FSR = 80h, C = 0)

GOTO Bank0_LP ; NO, clear next location

;

; Next Bank (Bank1)

; (** ONLY REQUIRED IF DEVICE HAS A BANK1 **)

;

MOVLW 0xA0 ; 1st address (in bank) of GPR area

MOVWF FSR ; Move it to Indirect address register

Bank1_LP

CLRF INDF0 ; Clear GPR at address pointed to by FSR

INCF FSR ; Next GPR (RAM) address

BTFSS STATUS, C ; End of current bank? (FSR = 00h, C = 1)

GOTO Bank1_LP ; NO, clear next location

;

; Next Bank (Bank2)

; (** ONLY REQUIRED IF DEVICE HAS A BANK2 **)

;

BSF STATUS, IRP ; Select Bank2 and Bank3

; for Indirect addressing

MOVLW 0x20 ; 1st address (in bank) of GPR area

MOVWF FSR ; Move it to Indirect address register

Bank2_LP

CLRF INDF0 ; Clear GPR at address pointed to by FSR

INCF FSR ; Next GPR (RAM) address

BTFSS FSR, 7 ; End of current bank? (FSR = 80h, C = 0)

GOTO Bank2_LP ; NO, clear next location

;

; Next Bank (Bank3)

; (** ONLY REQUIRED IF DEVICE HAS A BANK3 **)

;

MOVLW 0xA0 ; 1st address (in bank) of GPR area

MOVWF FSR ; Move it to Indirect address register

Bank3_LP

CLRF INDF0 ; Clear GPR at address pointed to by FSR

INCF FSR ; Next GPR (RAM) address

BTFSS STATUS, C ; End of current bank? (FSR = 00h, C = 1)

GOTO Bank3_LP ; NO, clear next location

: ; YES, All GPRs (RAM) is cleared

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-16  1997 Microchip Technology Inc.

6.5 Design Tips

Question 1:

Program execution seems to get lost.

Answer 1:

When a device with more then 2K words of program memory is used, the calling of subroutines

ma y require that the PCLATH register be loaded prior to the CALL (or GOTO) instruction to specify

the correct program memory page that the routine is located on. The following instructions will

correctly load PCLATH register, regardless of the program memory location of the label SUB_1.

MOVLW HIGH (SUB_1) ; Select Program Memory Page of

MOVWF PCLATH ; Routine.

CALL SUB_1 ; Call the desired routine

SUB_1 : ; Start of routine

RETURN ; Return from routine

Question 2:

I need to initialize RAM to ’0’s. What is an easy way to do that?

Answer 2:

Example 6-4 shows this . If the device y ou are using does not use all 4 data memory banks, some

of the code may be removed.

 1997 Microchip Technology Inc. DS31006A-page 6-17

Section 6. Memory Organization

Memory

Organization

6.6 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-r ange MCU family (that is they may be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to memory are:

Title Application Note #

Implementing a Table Read AN556

PICmicro MID-RANGE MCU FAMILY

DS31006A-page 6-18  1997 Microchip Technology Inc.

6.7 Revision History

Revision A

This is the initial released revision of the Memory Organization description.

 1997 Microchip Technology Inc.   DS31007A page 7-1
M
Data EEPROM
7
Section 7. Data EEPROM
HIGHLIGHTS
This section of the manual contains the following major topics:
7.1 Introduction....................................................................................................................7-2
7.2 Control Register.............................................................................................................7-3
7.3 EEADR...........................................................................................................................7-4
7.4 EECON1 and EECON2 Registers.................................................................................7-4
7.5 Reading the EEPROM Data Memory ............................................................................7-5
7.6 Writing to the EEPROM Data Memory...........................................................................7-5
7.7 Write V erify.....................................................................................................................7-6
7.8 Protection Against Spurious Writes ...............................................................................7-7
7.9 Data EEPROM Operation During Code Protected Conﬁguration..................................7-7
7.10 Initialization....................................................................................................................7-7
7.11 Design Tips ....................................................................................................................7-8
7.12 Related Application Notes..............................................................................................7-9
7.13 Revision History...........................................................................................................7-10

PICmicro MID-RANGE MCU FAMILY

DS31007A-page 7-2  1997 Microchip Technology Inc.

7.1 Introduction

The EEPROM data memory is readable and writable during normal operation (full VDD range).

This memor y is not directly mapped in the register ﬁle space. Instead it is indirectly addressed

through the Special Function Registers. There are f our SFRs used to read and write this memory .

These registers are:

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EED ATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM loca-

tion being accessed. The 8-bit EEADR register can access up to 256 locations of Data EEPROM.

The EEADR register can be thought of as the indirect addressing register of the Data EEPROM.

EECON1 contains the control bits, while EECON2 is the register used to initiate the read/write.

Some de vices will implement less then the entire memory map . The address range alwa ys starts

at 0h, and goes throughout the memory a vailable. Table 7-1 shows some of the possible common

device memory sizes and the address range for those sizes.

Table 7-1: Possible Data EEPROM Memory Sizes

The EEPROM data memory allows byte read and write. A byte write automatically erases the

location and writes the new data (erase before write). The EEPROM data memory is rated for

high erase/write cycles. The write time is controlled by an on-chip timer. The wr ite-time will vary

with voltage and temperature as well as from chip to chip. Please refer to the AC speciﬁcations

for exact limits.

When the de vice is code protected, the CPU may continue to read and write the data EEPROM

memory. The device programmer can no longer access this memory.

Data EEPROM

Size (1) Address Range

64 0h - 3Fh

128 0h - 7Fh

256 0h - FFh

Note 1: Presently, devices are only offered with 64

bytes of Data EEPROM.

 1997 Microchip Technology Inc. DS31007A-page 7-3

Section 7. Data EEPROM

Data EEPROM

7.2 Control Register

U-0 U-0 U-0 R/W-1 R/W-1 R/W-x R/S-0 R/S-x

— — — EEIF (1) WRERR WREN WR RD

bit 7 bit 0

bit 7:5 Unimplemented: Read as '0'

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR reset or any WDT reset during normal operation)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = initiates a write cycle. The bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read. Read takes one cycle. RD is cleared in hardware.

The RD bit can only be set (not cleared) in software.

0 = Does not initiate an EEPROM read

Legend

R = Readable bit W = Writable bit S = Settable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note 1: Future devices will have this bit in the PIR register.

PICmicro MID-RANGE MCU FAMILY

DS31007A-page 7-4  1997 Microchip Technology Inc.

7.3 EEADR

The EEADR register can address up to a maximum of 256 bytes of data EEPROM.

The unused address bits are decoded. This means that these bits must always be '0' to ensure

that the address is in the Data EEPROM memory space.

7.4 EECON1 and EECON2 Registers

EECON1 is the control register with ﬁve low order bits physically implemented. The upper-three

bits are unimplemented and read as '0's.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at completion of the read or wr ite operation. The

inability to clear the WR bit in software prevents the accidental, premature termination of a write

operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset

during normal operation. In these situations, following reset, the user can check the WRERR bit

and rewrite the location. The data and address will be unchanged in the EEDATA and

EEADR registers.

Interrupt ﬂag bit EEIF is set when write is complete. It must be cleared in software.

EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is

used exclusively in the Data EEPROM write sequence.

 1997 Microchip Technology Inc. DS31007A-page 7-5

Section 7. Data EEPROM

Data EEPROM

7.5 Reading the EEPROM Data Memory

To read a data memory location, the user must write the address to the EEADR register and then

set control bit RD (EECON1<0>). The data is available, in the ver y next instruction cycle, in the

EED ATA register; therefore it can be read b y the next instruction. EED ATA will hold this value until

another read or until it is written to by the user (during a write operation).

Example 7-1: Data EEPROM Read

7.6 Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must ﬁrst write the address to the EEADR register

and the data to the EED ATA register. Then the user must f ollo w a speciﬁc sequence to initiate the

write for each byte.

Example 7-2: Data EEPROM Write

The write will not initiate if the above sequence is not exactly followed (wr ite 55h to EECON2,

write AAh to EECON2, then set WR bit) f or each b yte. W e strongly recommend that interrupts be

disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents

accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost pro-

grams). The user should keep the WREN bit clear at all times, except when updating EEPROM.

The WREN bit is not cleared by hardware

After a write sequence has been initiated, clear ing the WREN bit will not affect this write cycle.

The WR bit will be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF m ust

be cleared by software.

BCF STATUS, RP0 ; Bank0

MOVLW CONFIG_ADDR ; Any location in Data EEPROM memory space

MOVWF EEADR ; Address to read

BSF STATUS, RP0 ; Bank1

BSF EECON1, RD ; EE Read

BCF STATUS, RP0 ; Bank0

MOVF EEDATA, W ; W = EEDATA

BSF STATUS, RP0 ; Bank1

BCF INTCON, GIE ; Disable INTs.

BSF EECON1, WREN ; Enable Write

Required

Sequence

MOVLW 55h ;

MOVWF EECON2 ; 55h must be written to EECON2

MOVLW AAh ; to start write sequence

MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit begin write

BSF INTCON, GIE ; Enable INTs.

PICmicro MID-RANGE MCU FAMILY

DS31007A-page 7-6  1997 Microchip Technology Inc.

7.7 Write Verify

Depending on the application, good programming practice may dictate that the value written to

the Data EEPROM be veriﬁed (Example 7-3) as the value that was intended to be written. This

should be used in applications where an EEPROM bit will be stressed near the speciﬁcation limit.

The Total Endurance disk will help determine your comfort level.

Example 7-3: Write Verify

BCF STATUS, RP0 ; Bank0

: ; Any code can go here

: ;

MOVF EEDATA, W ; Must be in Bank0

BSF STATUS, RP0 ; Bank1

READ

BSF EECON1, RD ; YES, Read the value written

BCF STATUS, RP0 ; Bank0

;

; Is the value written (in W reg) and read (in EEDATA) the same?

;

SUBWF EEDATA, W ;

BTFSS STATUS, Z ; Is difference 0?

GOTO WRITE_ERR ; NO, Write error

: ; YES, Good write

: ; Continue program

 1997 Microchip Technology Inc. DS31007A-page 7-7

Section 7. Data EEPROM

Data EEPROM

7.8 Protection Against Spurious Writes

There are conditions when the device may not want to write to the data EEPROM memor y. To

protect against spurious EEPROM writes, v arious mechanisms have been b uilt-in. On power-up ,

WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write.

The write initiate sequence and the WREN bit together help prevent an accidental write during

brown-outs, power glitches, and software malfunction.

7.9 Data EEPROM Operation During Code Protected Conﬁguration

When the de vice is code protected, the CPU is able to read and write data to the Data EEPROM.

F or ROM devices , there are two code protection bits. One f or the ROM prog ram memory and one

f or the Data EEPR OM memory. See the Device Progr amming Speciﬁcation f or more information

about these bits.

7.10 Initialization

The Data EEPROM module does not have an initialization sequence such as other modules. To

do a read of the Data EEPROM refer to Example 7-1. To do a write to the Data EEPROM refer

to Example 7-2, and to verify that the write completed successfully refer to Example 7-3.

As for the General Pur pose RAM, it is a good idea to initialize all Data EEPROM locations to a

known state. This initialization may take place at the time of device programming or an applica-

tion diagnostic mode, since on reset you may not want the Data EEPROM to be cleared.

An Application Diagnostic mode ma y be a condition on the I/O pins that the de vice tests f or after

the de vice power-ups . Then depending on this mode, the de vice would do some diagnostic func-

tion. The state for the I/O pins w ould need to be something that would not be possible without the

injected levels to force this diagnostic mode.

PICmicro MID-RANGE MCU FAMILY

DS31007A-page 7-8  1997 Microchip Technology Inc.

7.11 Design Tips

Question 1:

Why do the data EEPROM locations not contain the data that I wrote?

Answer 1:

There are a few possibilities, but the most likely is that you did not exactly follow the write

sequence as shown in Example 7-2. If you are using this code segment ensure that all interrupts

are disabled during this sequence.

Question 2:

Why is the data in the data EEPROM is getting corrupted?

Answer 2:

The data will only change when a Data EEPROM write occurs. Inadvertent writes may occur

when the de vice is in a bro wn-out condition (out of oper ating speciﬁcation) and the device is not

being f orced to the reset state . During a brown-out, either the internal brown-out circuitry should

be enabled (when available) or external circuitr y should be used to reset the PICmicro MCU to

ensure that no data EEPROM writes occur when the device is out of the valid operating range.

 1997 Microchip Technology Inc. DS31007A-page 7-9

Section 7. Data EEPROM

Data EEPROM

7.12 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to data

EEPROM are:

Title Application Note #

EEPROM Endurance Tutorial AN601

How to get 10 Million Cycles out of your Microchip Serial EEPROM AN602

Basic Serial EEPROM Operation AN536

Everything a System Engineer needs to know about Serial EEPROM Endurance AN537

Using the Microchip Endurance Predictive Software AN562

PICmicro MID-RANGE MCU FAMILY

DS31007A-page 7-10  1997 Microchip Technology Inc.

7.13 Revision History

Revision A

This is the initial released revision of the Data EEPROM description.

 1997 Microchip Technology Inc.   DS31008A page 8-1
M
Interrupts
8
Section 8. Interrupts
HIGHLIGHTS
This section of the manual contains the following major topics:
8.1 Introduction....................................................................................................................8-2
8.2 Control Registers...........................................................................................................8-5
8.3 Interrupt Latency..........................................................................................................8-10
8.4 INT and External Interrupts..........................................................................................8-10
8.5 Context Saving During Interrupts.................................................................................8-11
8.6 Initialization..................................................................................................................8-14
8.7 Design Tips..................................................................................................................8-16
8.8 Related Application Notes............................................................................................8-17
8.9 Revision History...........................................................................................................8-18

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-2  1997 Microchip Technology Inc.

8.1 Introduction

PICmicro MCUs can hav e man y sources of interrupt. These sources generally include one inter-

rupt source for each peripheral module, though some modules may generate multiple interrupts

(such as the USART module). The current interrupts are:

• INT Pin Interrupt (external interrupt)

• TMR0 Overﬂow Interrupt

• PORTB Change Interrupt (pins RB7:RB4)

• Comparator Change Interrupt

• Parallel Slave Port Interrupt

• USART Interrupts

• Receive Interrupt

• Transmit Interrupt

• A/D Conversion Complete Interrupt

• LCD Interrupt.

• Data EEPROM Write Complete Interrupt

• Timer1 Overﬂow Interrupt

• Timer2 Overﬂow Interrupt

• CCP Interrupt

• SSP Interrupt

There is a minimum of one register used in the control and status of the interrupts. This register

is:

• INTCON

Additionally, if the de vice has peripheral interrupts, then it will hav e registers to enable the periph-

eral interrupts and registers to hold the interrupt ﬂag bits. Depending on the device, the registers

are:

• PIE1

• PIR1

• PIE2

• PIR2

We will gener ically refer to these registers as PIR and PIE. If future devices provide more inter-

rupt sources, they will be supported by additional register pairs, such as PIR3 and PIE3.

The Interrupt Control Register, INTCON, records individual ﬂag bits for core interrupt requests.

It also has various individual enable bits and the global interrupt enable bit.

 1997 Microchip Technology Inc. DS31008A-page 8-3

Section 8. Interrupts

Interrupts

The Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all un-masked interrupts or

disables (if cleared) all interrupts. Individual interrupts can be disabled through their correspond-

ing enable bits in the INTCON register. The GIE bit is cleared on reset.

The “return from interrupt” instruction, RETFIE, e xits the interrupt routine as well as sets the GIE

bit, which allows any pending interrupt to execute.

The INTCON register contains these interrupts: INT Pin Interrupt, the RB P ort Change Interrupt,

and the TMR0 Overﬂow Interrupt. The INTCON register also contains the Peripheral Interrupt

Enable bit, PEIE. The PEIE bit will enable/disable the peripheral interrupts from vectoring when

the PEIE bit is set/cleared.

When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the

return address is pushed into the stack and the PC is loaded with 0004h. Once in the interr upt

service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits.

Generally the interrupt ﬂag bit(s) must be cleared in software before re-enabling the global inter-

rupt to avoid recursive interrupts.

Once in the interrupt service routine the source(s) of the interrupt can be deter mined by polling

the interrupt ﬂag bits. Individual interrupt ﬂag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

Note 1: Individual interrupt ﬂag bits are set regardless of the status of their corresponding

mask bit or the GIE bit.

Note 2: When an instruction that clears the GIE bit is executed, any interrupts that were

pending f or ex ecution in the next cycle are ignored. The CPU will execute a NOP in

the cycle immediately following the instruction which clears the GIE bit. The inter-

rupts which were ignored are still pending to be serviced when the GIE bit is set

again.

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-4  1997 Microchip Technology Inc.

Figure 8-1: Interrupt Logic

TMR1IE

TMR1IF

TMR2IE

TMR2IF

INTF

INTE

RBIF

RBIE

T0IF

T0IE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

INTCON RegisterPIR/PIE Registers

ADCIE

ADCIF

ADIE

ADIF

CCP1IE

CCP1IF

CCP2IE

CCP2IF

CMIE

CMIF

EEIE

EEIF

LCDIE

LCDIF

PBIE

PBIF

PSPIE

PSPIF

RCIE

RCIF

SSPIE

SSPIF

OVFIE

OVFIF

TXIE

TXIF

GPIF

GPIE

(EEIE 2)

Note 1: This shows all current Interrupt bits (at time of manual printing) for

all PICmicro Mid-Range MCUs. Which bits pertain to a speciﬁc

device is dependent upon the device type and peripherals imple-

mented. See speciﬁc device data sheet.

2: Some of the original Mid-Range devices had only one peripheral

module. These devices do not have the PEIE bit, and have the mod-

ule enable bit in the INTCON register.

(ADIE 2)

Clear GIE bit

 1997 Microchip Technology Inc. DS31008A-page 8-5

Section 8. Interrupts

Interrupts

8.2 Control Registers

Generally devices have a minimum of three registers associated with interrupts. The INTCON

Enable bit, PEIE, and the PIE / PIR register pair which enable the peripheral interrupts and dis-

play the interrupt ﬂag status.

8.2.1 INTCON Register

The INTCON Register is a readable and writable register which contains v arious enable and ﬂag

bits.

Note: Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state

of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).This

feature allows for software polling.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE (3) T0IE INTE (2) RBIE (1,

2) T0IF INTF (2) RBIF (1, 2)

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 overﬂow interrupt

0 = Disables the TMR0 overﬂow interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt

0 = Disables the INT external interrupt

bit 3 RBIE (1): RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred (must be cleared in software)

0 = The INT external interrupt did not occur

bit 0 RBIF (1): RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note 1: In some devices , the RBIE bit ma y also be kno wn as GPIE and the RBIF bit ma y be

know as GPIF.

Note 2: Some devices may not have this feature. For those devices this bit is reserved.

Note 3: In devices with only one peripheral interrupt, this bit may be EEIE or ADIE.

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-6  1997 Microchip Technology Inc.

8.2.2 PIE Register(s)

Depending on the number of peripheral interrupt sources, there ma y be multiple P eripheral Inter-

rupt Enable registers (PIE1, PIE2). These registers contain the individual enable bits for the

Per ipheral interrupts. These registers will be gener ically referred to as PIE. If the device has a

PIE register, The PEIE bit must be set to enable any of these peripheral interrupts.

Although, the PIE register bits have a general bit location with each register, future devices may

not have consistent placement. Bit location inconsistencies will not be a problem if you use the

supplied Microchip Include ﬁles for the symbolic use of these bits. This will allow the Assem-

bler/Compiler to automatically take care of the placement of these bits by specifying the correct

Note: Bit PEIE (INTCON<6>) must be set to enable any of the peripheral interrupts.

 1997 Microchip Technology Inc. DS31008A-page 8-7

Section 8. Interrupts

Interrupts

R/W-0

(Note 1)

bit 7 bit 0

bit TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt

0 = Disables the TMR1 overﬂow interrupt

bit TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

bit SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit ADCIE: Slope A/D Converter comparator Trip Interrupt Enable bit

1 = Enables the Slope A/D interrupt

0 = Disables the Slope A/D interrupt

bit OVFIE: Slope A/D TMR Overﬂow Interrupt Enable bit

1 = Enables the Slope A/D TMR overﬂow interrupt

0 = Disables the Slope A/D TMR overﬂow interrupt

bit PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit LCDIE: LCD Interrupt Enable bit

1 = Enables the LCD interrupt

0 = Disables the LCD interrupt

bit CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note 1: The bit position of the enable bits is device dependent. Please refer to the device

data sheet for bit placement.

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-8  1997 Microchip Technology Inc.

8.2.3 PIR Register(s)

Depending on the number of peripheral interrupt sources, there ma y be multiple P eripheral Inter-

rupt Flag registers (PIR1, PIR2). These registers contain the individual ﬂag bits f or the peripheral

interrupts. These registers will be generically referred to as PIR.

Although, the PIR bits hav e a gener al bit location within each register, future devices ma y not be

able to be consistent with that. It is recommended that you use the supplied Microchip Include

ﬁles for the symbolic use of these bits. This will allow the Assembler/Compiler to automatically

take care of the placement of these bits within the speciﬁed register.

Note 1: Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state

of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

Note 2: User software should ensure the appropriate interrupt ﬂag bits are cleared (by soft-

ware) prior to enabling an interrupt, and after servicing that interrupt.

R/W-0

(Note 1)

bit 7 bit 0

bit TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂowed (must be cleared in software)

0 = TMR1 register did not overﬂow

bit TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete

0 = Waiting to transmit/receive

bit RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)

0 = The USART receive buffer is empty

bit TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0 = The USART transmit buffer is full

bit ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

 1997 Microchip Technology Inc. DS31008A-page 8-9

Section 8. Interrupts

Interrupts

bit ADCIF: Slope A/D Converter Comparator Trip Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit OVFIF: Slope A/D TMR Overﬂow Interrupt Flag bit

1 = Slope A/D TMR overﬂowed (must be cleared in software)

0 = Slope A/D TMR did not overﬂow

bit PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred

bit EEIF: EE Write Complete Interrupt Flag bit

1 = The data EEPROM write operation is complete (must be cleared in software)

0 = The data EEPROM write operation is not complete

bit LCDIF: LCD Interrupt Flag bit

1 = LCD interrupt has occurred (must be cleared in software)

0 = LCD interrupt has not occurred

bit CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note 1: The bit position of the ﬂag bits is device dependent. Please refer to the device data

sheet for bit placement.

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-10  1997 Microchip Technology Inc.

8.3 Interrupt Latency

Interrupt latency is deﬁned as the time from the interr upt event (the interr upt ﬂag bit gets set) to

the time that the instruction at address 0004h starts execution (when that interrupt is enabled).

For synchronous interrupts (typically internal), the latency is 3TCY.

For asynchronous interr upts (typically external), such as the INT or Port RB Change Interrupt,

the interrupt latency will be 3 - 3.75TCY (instruction cycles). The exact latency depends upon

when the interrupt event occurs (Figure 8-2) in relation to the instruction cycle.

The latency is the same for both one and two cycle instructions.

8.4 INT and External Interrupts

The external interrupt on the INT pin is edge triggered: either rising if the INTEDG bit

(OPTION<6>) is set, or f alling, if the INTEDG bit is clear. When a v alid edge appears on the INT

pin, the INTF ﬂag bit (INTCON<1>) is set. This interrupt can be enabled/disabled b y setting/clear-

ing the INTE enable bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt

service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor

from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides

whether or not the processor branches to the interrupt vector following wake-up. See the

“Watchdog Timer and Sleep Mode” section for details on SLEEP and for timing of wake-up

from SLEEP through INT interrupt.

Figure 8-2: INT Pin and Other External Interrupt Timing

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time.

Latency is the same whether Instruction (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

Note: Any interrupts caused by e xternal signals (such as timers, capture , change on port)

will have similar timing.

 1997 Microchip Technology Inc. DS31008A-page 8-11

Section 8. Interrupts

Interrupts

8.5 Context Saving During Interrupts

During an interr upt, only the retur n PC value is saved on the stack. Typically, users may wish to

sav e key registers during an interrupt e.g. W register and STATUS register. This has to be imple-

mented in software.

The action of saving inf ormation is commonly referred to as “PUSHing, ” while the action of restor-

ing the infor mation before the return is commonly referred to as “POPing.” These (PUSH, POP)

are not instruction mnemonics, but are conceptual actions . This action can be implemented by a

sequence of instructions. For ease of code transportability, these code segments can be made

into MACROs (see MPASM Assembler User’s Guide for details on creating macros).

Example 8-1 stores and restores the STATUS and W registers for devices with common RAM

(such as the PIC16C77). The user register , W_TEMP, must be deﬁned across all banks and must

be deﬁned at the same offset from the bank base address (i.e., W_TEMP is deﬁned at 0x70 -

0x7F in Bank0). The user register, STATUS_TEMP, must be deﬁned in Bank0, in this example

STATUS_TEMP is also in Bank0.

The steps of Example 8-1:

1. Stores the W register regardless of current bank.

2. Stores the STATUS register in Bank0.

3. Executes the Interrupt Service Routine (ISR) code.

4. Restores the STATUS (and bank select bit register).

5. Restores the W register.

If additional locations need to be saved before executing the Interrupt Service Routine (ISR)

code, the y should be saved after the STATUS register is saved (step 2), and restored before the

STATUS register is restored (step 4).

Example 8-1: Saving the STATUS and W Registers in RAM

(for Devices with Common RAM)

MOVWF W_TEMP ; Copy W to a Temporary Register

; regardless of current bank

SWAPF STATUS,W ; Swap STATUS nibbles and place

; into W register

MOVWF STATUS_TEMP ; Save STATUS to a Temporary register

; in Bank0

: (Interrupt Service Routine (ISR) )

SWAPF STATUS_TEMP,W ; Swap original STATUS register value

; into W (restores original bank)

MOVWF STATUS ; Restore STATUS register from

; W register

SWAPF W_TEMP,F ; Swap W_Temp nibbles and return

; value to W_Temp

SWAPF W_TEMP,W ; Swap W_Temp to W to restore original

; W value without affecting STATUS

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-12  1997 Microchip Technology Inc.

Example 8-2 stores and restores the STATUS and W registers f or de vices without common RAM

(such as the PIC16C74A). The user register, W_TEMP, must be deﬁned across all banks and

must be deﬁned at the same offset from the bank base address (i.e., W_TEMP is deﬁned at 0x70

- 0x7F in Bank0). The user register, STATUS_TEMP, must be deﬁned in Bank0.

Within the 70h - 7Fh range (Bank0), where ver W_TEMP is e xpected the corresponding locations

in the other banks should be dedicated for the possible saving of the W register.

The steps of Example 8-2:

1. Stores the W register regardless of current bank.

2. Stores the STATUS register in Bank0.

3. Executes the Interrupt Service Routine (ISR) code.

4. Restores the STATUS (and bank select bit register).

5. Restores the W register.

If additional locations need to be saved before executing the Interrupt Service Routine (ISR)

code, the y should be saved after the STATUS register is saved (step 2), and restored before the

STATUS register is restored (step 4).

Example 8-2: Saving the STATUS and W Registers in RAM

(for Devices without Common RAM)

MOVWF W_TEMP ; Copy W to a Temporary Register

; regardless of current bank

SWAPF STATUS,W ; Swap STATUS nibbles and place

; into W register

BCF STATUS,RP0 ; Change to Bank0 regardless of

; current bank

MOVWF STATUS_TEMP ; Save STATUS to a Temporary register

; in Bank0

: (Interrupt Service Routine (ISR) )

SWAPF STATUS_TEMP,W ; Swap original STATUS register value

; into W (restores original bank)

MOVWF STATUS ; Restore STATUS register from

; W register

SWAPF W_TEMP,F ; Swap W_Temp nibbles and return

; value to W_Temp

SWAPF W_TEMP,W ; Swap W_Temp to W to restore original

; W value without affecting STATUS

 1997 Microchip Technology Inc. DS31008A-page 8-13

Section 8. Interrupts

Interrupts

Example 8-3 stores and restores the STATUS and W registers for devices with general purpose

RAM only in Bank0 (such as the PIC16C620). The Bank must be tested bef ore sa ving any of the

user registers. , W_TEMP, must be deﬁned across all banks and must be deﬁned at the same

offset from the bank base address. The user register , STATUS_TEMP, must be deﬁned in Bank0.

The steps of Example 8-3:

1. Test current bank.

2. Stores the W register regardless of current bank.

3. Stores the STATUS register in Bank0.

4. Executes the Interrupt Service Routine (ISR) code.

5. Restores the STATUS (and bank select bit register).

6. Restores the W register.

If additional locations need to be saved before executing the Interrupt Service Routine (ISR)

code, the y should be saved after the STATUS register is saved (step 2), and restored before the

STATUS register is restored (step 4).

Example 8-3: Saving the STATUS and W Registers in RAM

(for Devices with General Purpose RAM Only in Bank0)

Push

BTFSS STATUS, RP0 ; In Bank 0?

GOTO RP0CLEAR ; YES,

BCF STATUS, RP0 ; NO, Force to Bank 0

MOVWF W_TEMP ; Store W register

SWAPF STATUS, W ; Swap STATUS register and

MOVWF STATUS_TEMP ; store in STATUS_TEMP

BSF STATUS_TEMP, 1 ; Set the bit that corresponds to RP0

GOTO ISR_Code ; Push completed

RP0CLEAR

MOVWF W_TEMP ; Store W register

SWAPF STATUS, W ; Swap STATUS register and

MOVWF STATUS_TEMP ; store in STATUS_TEMP

;

ISR_Code

: (Interrupt Service Routine (ISR) )

;

Pop

SWAPF STATUS_TEMP, W ; Restore Status register

MOVWF STATUS ;

BTFSS STATUS, RP0 ; In Bank 1?

GOTO Restore_WREG ; NO,

BCF STATUS, RP0 ; YES, Force Bank 0

SWAPF W_TEMP, F ; Restore W register

SWAPF W_TEMP, W ;

BSF STATUS, RP0 ; Back to Bank 1

RETFIE ; POP completed

Restore_WREG

SWAPF W_TEMP, F ; Restore W register

SWAPF W_TEMP, W ;

RETFIE ; POP completed

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-14  1997 Microchip Technology Inc.

8.6 Initialization

Example 8-4 shows the initialization and enab ling of de vice interrupts, where PIE1_MASK1 value

is the value to write into the interrupt enable register.

Example 8-5 shows how to create macro deﬁnitions for functions. Macros must be deﬁned

bef ore they are used. F or deb ugging ease, it may help if macros are placed in other ﬁles that are

included at assembly time. This allows the source to be viewed without all the clutter of the

required macros. These ﬁles must be included before the macro is used, but it simpliﬁes deb ug-

ging, if all include ﬁles are done at the top of the source ﬁle. Example 8-6 shows this structure.

Example 8-7 shows a typical Interrupt Ser vice Routine structure. This ISR uses macros for the

saving and restoring of registers before the execution of the interrupt code.

Example 8-4: Initialization and Enabling of Interrupts

Example 8-5: Register Saving / Restoring as Macros

PIE1_MASK1 EQU B‘01101010’ ; This is the Interrupt Enable

: ; Register mask value

CLRF STATUS ; Bank0

CLRF INTCON ; Disable interrupts and clear some flags

CLRF PIR1 ; Clear all flag bits

BSF STATUS, RP0 ; Bank1

MOVLW PIE1_MASK1 ; This is the initial masking for PIE1

MOVWF PIE1 ;

BCF STATUS, RP0 ; Bank0

BSF INTCON, GIE ; Enable Interrupts

PUSH_MACRO MACRO ; This Macro Saves register contents

MOVWF W_TEMP ; Copy W to a Temporary Register

; regardless of current bank

SWAPF STATUS,W ; Swap STATUS nibbles and place

; into W register

MOVWF STATUS_TEMP ; Save STATUS to a Temporary register

; in Bank0

ENDM ; End this Macro

;

POP_MACRO MACRO ; This Macro Restores register contents

SWAPF STATUS_TEMP,W ; Swap original STATUS register value

; into W (restores original bank)

MOVWF STATUS ; Restore STATUS register from

; W register

SWAPF W_TEMP,F ; Swap W_Temp nibbles and return

; value to W_Temp

SWAPF W_TEMP,W ; Swap W_Temp to W to restore original

; W value without affecting STATUS

ENDM ; End this Macro

 1997 Microchip Technology Inc. DS31008A-page 8-15

Section 8. Interrupts

Interrupts

Example 8-6: Source File Template

Example 8-7: Typical Interrupt Service Routine (ISR)

LIST p = p16C77 ; List Directive,

; Revision History

;

#INCLUDE <P16C77.INC> ; Microchip Device Header File

;

#INCLUDE <MY_STD.MAC> ; Include my standard macros

#INCLUDE <APP.MAC> ; File which includes macros specific

; to this application

; Specify Device Configuration Bits

__CONFIG _XT_OSC & _PWRTE_ON & _BODEN_OFF & _CP_OFF & _WDT_ON

;

org 0x00 ; Start of Program Memory

RESET_ADDR : ; First instruction to execute after a reset

end

org ISR_ADDR ;

PUSH_MACRO ; MACRO that saves required context registers,

; or in-line code

CLRF STATUS ; Bank0

BTFSC PIR1, TMR1IF ; Timer1 overflow interrupt?

GOTO T1_INT ; YES

BTFSC PIR1, ADIF ; NO, A/D interrupt?

GOTO AD_INT ; YES, do A/D thing

: ; NO, do this for all sources

: ;

BTFSC PIR1, LCDIF ; NO, LCD interrupt

GOTO LCD_INT ; YES, do LCD thing

BTFSC INTCON, RBIF ; NO, Change on PORTB interrupt?

GOTO PORTB_INT ; YES, Do PortB Change thing

INT_ERROR_LP1 ; NO, do error recovery

GOTO INT_ERROR_LP1 ; This is the trap if you enter the ISR

; but there were no expected

; interrupts

T1_INT ; Routine when the Timer1 overflows

: ;

BCF PIR1, TMR1IF ; Clear the Timer1 overflow interrupt flag

GOTO END_ISR ; Ready to leave ISR (for this request)

AD_INT ; Routine when the A/D completes

: ;

BCF PIR1, ADIF ; Clear the A/D interrupt flag

GOTO END_ISR ; Ready to leave ISR (for this request)

LCD_INT ; Routine when the LCD Frame begins

: ;

BCF PIR1, LCDIF ; Clear the LCD interrupt flag

GOTO END_ISR ; Ready to leave ISR (for this request)

PORTB_INT ; Routine when PortB has a change

: ;

END_ISR ;

POP_MACRO ; MACRO that restores required registers,

; or in-line code

RETFIE ; Return and enable interrupts

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-16  1997 Microchip Technology Inc.

8.7 Design Tips

Question 1:

An algorithm does not give the correct results.

Answer 1:

Assuming that the algorithm is correct and that interrupts are enabled during the algorithm,

ensure that are registers that are used by the algorithm and by the interrupt service routine are

saved and restored. If not some registers may be corrupted by the execution of the ISR.

Question 2:

My system seems to lock up.

Answer 2:

If interrupts are being used, ensure that the interr upt ﬂag is cleared after servicing that interrupt

(but before executing the RETFIE instruction). If the interr upt ﬂag remains set when the RETFIE

instruction is ex ecuted, program e xecution immediately returns to the interrupt v ector, since there

is an outstanding enabled interrupt.

 1997 Microchip Technology Inc. DS31008A-page 8-17

Section 8. Interrupts

Interrupts

8.8 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to this section

are:

Title Application Note #

Using the PortB Interrupt On Change as an External Interrupt AN566

PICmicro MID-RANGE MCU FAMILY

DS31008A-page 8-18  1997 Microchip Technology Inc.

8.9 Revision History

Revision A

This is the initial released revision of the interrupt description.

 1997 Microchip Technology Inc.   DS31009A page 9-1
M
I/O Ports
9
Section 9. I/O Ports
HIGHLIGHTS
This section of the manual contains the following major topics:
9.1 Introduction....................................................................................................................9-2
9.2 PORTA and the TRISA Register ....................................................................................9-4
9.3 PORTB and the TRISB Register....................................................................................9-6
9.4 PORTC and the TRISC Register....................................................................................9-8
9.5 PORTD and the TRISD Register....................................................................................9-9
9.6 PORTE and the TRISE Register..................................................................................9-10
9.7 PORTF and the TRISF Register ..................................................................................9-11
9.8 PORTG and the TRISG Register.................................................................................9-12
9.9 GPIO and the TRISGP Register ..................................................................................9-13
9.10 I/O Programming Considerations.................................................................................9-14
9.11 Initialization..................................................................................................................9-16
9.12 Design Tips ..................................................................................................................9-17
9.13 Related Application Notes............................................................................................9-19
9.14 Revision History...........................................................................................................9-20

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-2  1997 Microchip Technology Inc.

9.1 Introduction

General purpose I/O pins can be considered the simplest of peripherals. They allow the

PICmicro™ to monitor and control other devices. To add ﬂexibility and functionality to a device,

some pins are multiplexed with an alternate function(s). These functions depend on which

peripheral features are on the device. In general, when a per ipheral is functioning, that pin may

not be used as a general purpose I/O pin.

F or most ports, the I/O pin’s direction (input or output) is controlled by the data direction register,

called the TRIS register. TRIS<x> controls the direction of PORT<x>. A ‘1’ in the TRIS bit corre-

sponds to that pin being an input, while a ‘0’ corresponds to that pin being an output. An easy

way to remember is that a ‘1’ looks like an I (input) and a ‘0’ looks like an O (output).

The PORT register is the latch for the data to be output. When the PORT is read, the de vice reads

the levels present on the I/O pins (not the latch). This means that care should be taken with

read-modify-write commands on the ports and changing the direction of a pin from an input to an

output.

Figure 9-1 shows a typical I/O port. This does not take into account peripheral functions that ma y

be multiple x ed onto the I/O pin. Reading the POR T register reads the status of the pins whereas

writing to it will write to the port latch. All write operations (such as BSF and BCF instructions) are

read-modify-write operations. Therefore a write to a por t implies that the port pins are read, this

value is modiﬁed, and then written to the port data latch.

Figure 9-1: Typical I/O Port

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

VSS

I/O pin

Note: I/O pin has protection diodes to VDD and VSS.

VDD

RD TRIS Schmitt

Trigger

TTL or

 1997 Microchip Technology Inc. DS31009A-page 9-3

Section 9. I/O Ports

I/O Ports

When peripheral functions are multiple xed onto general I/O pins, the functionality of the I/O pins

may change to accommodate the requirements of the per ipheral module. Examples of this are

the Analog-to-Digital (A/D) converter and LCD driver modules, which force the I/O pin to the

peripheral function when the device is reset. In the case of the A/D, this prev ents the de vice from

consuming excess current if any analog levels were on the A/D pins after a reset occurred.

With some peripherals, the TRIS bit is overridden while the peripheral is enabled. Therefore,

read-modify-write instr uctions (BSF, BCF, XORWF) with TRIS as destination should be avoided.

The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

POR T pins ma y be m ultiple xed with analog inputs and analog VREF input. The operation of each

of these pins is selected, to be an analog input or digital I/O, by clearing/setting the control bits

in the ADCON1 register (A/D Control Register1). When selected as an analog input, these pins

will read as ‘0’s.

The TRIS registers control the direction of the port pins, even when they are being used as ana-

log inputs. The user must ensure the TRIS bits are maintained set when using the pins as analog

inputs.

Note 1: If pins are multiple x ed with Analog inputs , then on a Power-on Reset these pins are

conﬁgured as analog inputs, as controlled by the ADCON1 register. Reading por t

pins conﬁgured as analog inputs read a ‘0’.

Note 2: If pins are multiple xed with compar ator inputs, then on a P o wer-on Reset these pins

are conﬁgured as analog inputs, as controlled b y the CMCON register. Reading port

pins conﬁgured as analog inputs read a ‘0’.

Note 3: If pins are multiplexed with LCD driver segments, then on a Power-on Reset these

pins are conﬁgured as LCD driver segments, as controlled by the LCDSE register.

To conﬁgure the pins as a digital port, the corresponding bits in the LCDSE register

must be cleared. Any bit set in the LCDSE register overrides any bit settings in the

corresponding TRIS register .

Note 4: Pins may be m ultiple xed with the P ar allel Slav e P ort (PSP). For the PSP to function,

the I/O pins must be conﬁgured as digital inputs and the PSPMODE bit must be set.

Note 5: At present the Parallel Slave Port (PSP) is only multiplexed onto PORTD and

POR TE. The microprocessor port becomes enabled when the PSPMODE bit is set.

In this mode, the user must make sure that the TRISE bits are set (pins are conﬁg-

ured as digital inputs) and that POR TE is conﬁgured for digital I/O . POR TD will over-

ride the values in the TRISD register. In this mode the PORTD and PORTE input

buffers are TTL. The control bits for the PSP operation are located in TRISE.

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-4  1997 Microchip Technology Inc.

9.2 PORTA and the TRISA Register

The RA4 pin is a Schmitt Trigger input and an open drain output. All other RA port pins hav e TTL

input le vels and full CMOS output driv ers. All pins hav e data direction bits (TRIS registers) which

can conﬁgure these pins as output or input.

Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode . Clear-

ing a bit in the TRISA register puts the contents of the output latch on the selected pin(s).

Example 9-1: Initializing PORTA

Figure 9-2: Block Diagram of RA3:RA0 and RA5 Pins

CLRF STATUS ; Bank0

CLRF PORTA ; Initialize PORTA by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0xCF ; Value used to initialize data direction

MOVWF TRISA ; PORTA<3:0> = inputs PORTA<5:4> = outputs

; TRISA<7:6> always read as '0'

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

VSS

I/O pin

To Peripheral Module(s)

Note: I/O pin has protection diodes to VDD and VSS.

Analog

input

mode TTL

VDD

RD TRIS or ST

input

buffer

 1997 Microchip Technology Inc. DS31009A-page 9-5

Section 9. I/O Ports

I/O Ports

Figure 9-3: Block Diagram of RA4 Pin

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

Schmitt

Trigger

input

buffer

VSS

To Peripheral Module

Note: I/O pin has protection diodes to VSS only.

RD TRIS

RA4 pin

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-6  1997 Microchip Technology Inc.

9.3 PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional por t. The corresponding data direction register is TRISB.

Setting a bit in the TRISB register puts the corresponding output driver in a high-impedance input

mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected

pin(s).

Example 9-2: Initializing PORTB

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the

pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automati-

cally turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on a

Power-on Reset.

Figure 9-4: Block Diagram of RB3:RB0 Pins

CLRF STATUS ; Bank0

CLRF PORTB ; Initialize PORTB by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0xCF ; Value used to initialize data direction

MOVWF TRISB ; PORTB<3:0> = inputs, PORTB<5:4> = outputs

; PORTB<7:6> = inputs

Data Latch

RBPU(2) P

VDD

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

To Peripheral Module

I/O

pin(1)

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups , set the appropriate TRIS bit(s) and clear

the RBPU bit (OPTION<7>).

 1997 Microchip Technology Inc. DS31009A-page 9-7

Section 9. I/O Ports

I/O Ports

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as

inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin conﬁgured as an output is e xcluded

from the interrupt on change compar ison). The input pins (of RB7:RB4) are compared with the

old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed

together to generate the RB Port Change Interrupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interr upt service routine, can

clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the mismatch condition.

b) Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF. Reading PORTB will end the mismatch

condition, and allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four

pins allow easy interface to a keypad and make it possible for wake-up on key-depression.

The interrupt on change feature is recommended f or w ak e-up on ke y depression and oper ations

where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recom-

mended while using the interrupt on change feature.

Figure 9-5: Block Diagram of RB7:RB4 Pins

Data Latch

From other

RBPU(2) P

VDD

I/O

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin(1)

Buffer

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION<7>).

3: In sleep mode the device is in Q1 state.

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-8  1997 Microchip Technology Inc.

9.4 PORTC and the TRISC Register

PORTC is an 8-bit bi-directional port. Each pin is individually conﬁgurable as an input or output

through the TRISC register. PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions , care should be tak en in deﬁning TRIS bits for each PORTC

pin. Some peripherals ov erride the TRIS bit to mak e a pin an output, while other peripherals o ver-

ride the TRIS bit to make a pin an input.

Example 9-3: Initializing PORTC

Figure 9-6: PORTC Block Diagram (Peripheral Output Override)

CLRF STATUS ; Bank0

CLRF PORTC ; Initialize PORTC by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0xCF ; Value used to initialize data direction

MOVWF TRISC ; PORTC<3:0> = inputs, PORTC<5:4> = outputs

; PORTC<7:6> = inputs

Data Latch

TRIS Latch

RD TRIS

VSS

VDD

RD PORT

WR PORT

WR TRIS

Schmitt

Trigger

Peripheral input

Peripheral OE(2)

Data Bus

PORT/PERIPHERAL Select(1)

Peripheral Data-out

RD PORT

Note 1: Port/Peripheral select signal selects between port data and peripheral output.

2: Peripheral OE (output enable) is only activated if peripheral select is active.

3: I/O pins have diode protection to VDD and VSS.

I/O pin

 1997 Microchip Technology Inc. DS31009A-page 9-9

Section 9. I/O Ports

I/O Ports

9.5 PORTD and the TRISD Register

POR TD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually conﬁgur ab le as

an input or output.

Example 9-4: Initializing PORTD

Figure 9-7: Typical PORTD Block Diagram (in I/O Port Mode)

CLRF STATUS ; Bank0

CLRF PORTD ; Initialize PORTD by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0xCF ; Value used to initialize data direction

MOVWF TRISD ; PORTD<3:0> = inputs, PORTD<5:4> = outputs

; PORTD<7:6> = inputs

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

Schmitt

Trigger

input

buffer

Note: I/O pins have protection diodes to VDD and VSS.

I/O pin

RD TRIS

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-10  1997 Microchip Technology Inc.

9.6 PORTE and the TRISE Register

POR TE can be up to an 8-bit port with Schmitt Trigger input buff ers . Each pin is individually con-

ﬁgurable as an input or output.

Example 9-5: Initializing PORTE

Figure 9-8: Typical PORTE Block Diagram (in I/O Port Mode)

CLRF STATUS ; Bank0

CLRF PORTE ; Initialize PORTE by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0x03 ; Value used to initialize data direction

MOVWF TRISE ; PORTE<1:0> = inputs, PORTE<7:2> = outputs

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

Schmitt

Trigger

input

buffer

I/O pin

RD TRIS

Note: I/O pins have protection diodes to VDD and VSS.

Note: On some de vices with POR TE, the upper bits of the TRISE register are used f or the

Parallel Slave Port control and status bits.

 1997 Microchip Technology Inc. DS31009A-page 9-11

Section 9. I/O Ports

I/O Ports

9.7 PORTF and the TRISF Register

PORTF is a digital input only por t. Each pin is multiplexed with an LCD segment driver. These

pins have Schmitt Trigger input buffers.

Example 9-6: Initializing PORTF

Figure 9-9: PORTF LCD Block Diagram

BCF STATUS, RP0 ; Select Bank2

BSF STATUS, RP1 ;

BCF LCDSE, SE16 ; Make all PORTF

BCF LCDSE, SE12 ; digital inputs

RD PORT

Schmitt

Trigger

input

buffer

Digital Input/

LCDSE<n>

LCD Segment Data

LCD Segment LCD Output pin

Data Bus

RD TRIS

VDD

Output Enable

Note: I/O pins have protection diodes to VDD and VSS.

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-12  1997 Microchip Technology Inc.

9.8 PORTG and the TRISG Register

PORTG is a digital input only por t. Each pin is multiplexed with an LCD segment driver. These

pins have Schmitt Trigger input buffers.

Example 9-7: Initializing PORTG

Figure 9-10: PORTG LCD Block Diagram

BCF STATUS, RP0 ; Select Bank2

BSF STATUS, RP1 ;

BCF LCDSE, SE27 ; Make all PORTG

BCF LCDSE, SE20 ; and PORTE<7> digital inputs

RD PORT

Schmitt

Trigger

input

buffer

Digital Input/

LCDSE<n>

LCD Segment Data

LCD Segment Output Enable LCD Output pin

Data Bus

RD TRIS

VDD

 1997 Microchip Technology Inc. DS31009A-page 9-13

Section 9. I/O Ports

I/O Ports

9.9 GPIO and the TRISGP Register

GPIO is an 8-bit I/O register. Only the low order six bits are implemented (GP5:GP0). Bits 7 and

6 are unimplemented and read as ‘0’s. Any GPIO pin (except GP3) can be programmed

individually as input or output. The GP3 pin is an input only pin.

The TRISGP register controls the data direction for GPIO pins. A ‘1’ in a TRISGP register bit

puts the corresponding output driver in a hi-impedance mode. A ‘0’ puts the contents of the

output data latch on the selected pins, enab ling the output b uff er. The exceptions are GP3 which

is input only and its TRIS bit will always read as '1'. Upon reset, the TRISGP register is all ‘1’s,

making all pins inputs.

A read of the GPIO por t, reads the pins not the output data latches. Any input must be present

until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain

unchanged until the output latch is rewritten.

Example 9-8: Initializing GPIO

Figure 9-11: Block Diagram of GP5:GP0 Pins

The conﬁguration word can set several I/O’s to alternate functions. When acting as alternate

functions the pins will read as ‘0’ during por t read. The GP0, GP1, and GP3 pins can be conﬁg-

ured with weak pull-ups and also with interrupt on change. The interrupt on change and weak

pull-up functions are not pin selectable. Interrupt on change is enabled by setting INTCON<3>.

If the de vice conﬁguration bits select one of the external oscillator modes, the GP4 and GP5 pin’ s

GPIO functions are overridden and these pins are used for the oscillator.

CLRF STATUS ; Bank0

CLRF GPIO ; Initialize GPIO by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0xCF ; Value used to initialize data direction

MOVWF TRISGP ; GP<3:0> = inputs GP<5:4> = outputs

; TRISGP<7:6> always read as '0'

Note 1: I/O pins have protection diodes to VDD and VSS.

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

pin(1)

Reg

Latch

Reset

GP3 is input only with no data latch and no output drivers.

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-14  1997 Microchip Technology Inc.

9.10 I/O Programming Considerations

When using the ports (and GPIO) as I/O , design considerations need to be tak en into account to

ensure that the operation is as intended.

9.10.1 Bi-directional I/O Ports

Any instruction which perf orms a write operation actually does a read followed by a write opera-

tion. The BCF and BSF instr uctions, for example, read the register into the CPU, execute the bit

operation, and write the result back to the register . Caution must be used when these instructions

are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5

of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation

takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used

as a bi-directional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal

present on the pin itself would be read into the CPU and re written to the data latch of this partic-

ular pin, ov erwriting the pre vious content. As long as the pin stays in the input mode , no prob lem

occurs. However, if bit0 is switched to an output, the content of the data latch may now be

unknown.

Reading the port register, reads the values of the port pins. Writing to the port register writes the

value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port,

the value of the port pins is read, the desired operation is performed on this value , and the v alue

is then written to the port latch.

Example 9-9 shows the effect of two sequential read-modify-write instructions on an I/O port.

Example 9-9: Read-Modify-Write Instructions on an I/O Port

A pin conﬁgured as an output, actively driving a Low or High should not be driven from external

devices at the same time in order to change the level on this pin (“wired-or,” “wired-and”). The

resulting high output currents may damage the chip.

; Initial PORT settings: PORTB<7:4> Inputs

; PORTB<3:0> Outputs

; PORTB<7:6> have external pull-ups and are not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ---------

BCF PORTB, 7 ; 01pp pppp 11pp pppp

BCF PORTB, 6 ; 10pp pppp 11pp pppp

BSF STATUS, RP0 ;

BCF TRISB, 7 ; 10pp pppp 11pp pppp

BCF TRISB, 6 ; 10pp pppp 10pp pppp

;

; Note that the user may have expected the pin values to be 00pp ppp.

; The 2nd BCF caused RB7 to be latched as the pin value (high).

 1997 Microchip Technology Inc. DS31009A-page 9-15

Section 9. I/O Ports

I/O Ports

9.10.2 Successive Operations on an I/O Port

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading,

the data must be valid at the beginning of the instruction cycle (Figure 9-12). Therefore, care

must be e x ercised if a write f ollo wed b y a read oper ation is carried out on the same I/O port. The

sequence of instructions should be such to allow the pin voltage to stabilize (load dependent)

bef ore the next instruction which causes that ﬁle to be read into the CPU is e x ecuted. Otherwise,

the pre vious state of that pin may be read into the CPU r ather than the new state. When in doubt,

it is better to separate these instructions with a NOP or another instruction not accessing this I/O

port.

Figure 9-12: Successive I/O Operation

Figure 9-13 shows the I/O model which causes this situation. As the effective capacitance (C)

becomes larger, the r ise/fall time of the I/O pin increases. As the device frequency increases or

the effective capacitance increases, the possibility of this subsequent PORTx read-modify-write

instruction issue increases. This effective capacitance includes the effects of the board traces.

The best way to address this is to add an series resistor at the I/O pin. This resistor allows the

I/O pin to get to the desired level before the next instruction.

The use of NOP instructions between the subsequent PORTx read-modify-write instructions, is a

lower cost solution, but has the issue that the number of NOP instructions is dependent on the

effective capacitance C and the frequency of the device.

Figure 9-13: I/O Connection Issues

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to

PORTB NOP

Port pin

sampled here

NOP

MOVF PORTB,W

Instruction

executed MOVWF PORTB

write to

PORTB

NOP

MOVF PORTB,W

TPD

This example shows a write to PORTB followed by a read from PORTB.

Note: Data setup time = (0.25TCY - TPD)

whereTCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be

problematic due to external capacitance.

PIC16CXXX

I/O

C(1)

Q4 Q1 Q2 Q3 Q4 Q1

VIL

BSF PORTx, PINy

Q2 Q3

BSF PORTx, PINz

PORTx, PINy

Read PORTx, PINy as low

BSF PORTx, PINz clears the value

to be driven on the PORTx, PINy pin.

Note: This is not a capacitor to ground, but the effectiv e capac-

itive loading on the trace.

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-16  1997 Microchip Technology Inc.

9.11 Initialization

See the section describing each port for examples of initialization of the ports.

Note: It is recommended that when initializing the port, the data latch (PORT register)

should be initialized ﬁrst, and then the data direction (TRIS register). This will elim-

inate a possible pin glitch, since the PORT data latch values power up in a random

state.

 1997 Microchip Technology Inc. DS31009A-page 9-17

Section 9. I/O Ports

I/O Ports

9.12 Design Tips

Question 1:

Code will not toggle any I/O por ts, but the oscillator is running. What can I

be doing wrong?

Answer 1:

1. Have the TRIS registers been initialized properly? These registers can be written to

directly in the second bank (Bank1). In most cases the user is not switching to Bank1

(BSF STATUS,RP0) before writing zeros to the TRIS register.

2. If you are setting up the TRIS registers properly in Bank1 (RP0 = 1), you may not be

returning to Bank0 before writing to the ports (BCF STATUS,RP0).

3. Is there a peripheral multiplexed onto those pins that are enabled?

4. Is the W atchdog Timer enabled (done at programming)? If it is enab led, is it being cleared

properly with a CLRWDT instruction at least every 9 ms (or more if prescaled)?

5. Are you using the correct instructions to write to the port? More than one person has used

the MOVF command when they should have used MOVWF.

6. For parts with interrupts, are the interrupts disabled? If not, try disabling them to v erify they

are not interfering.

Question 2:

When m y pr ogram reads a port, I get a different v alue than what I put in the

port register. What can cause this?

Answer 2:

1. When a port is read, it is always the pin that is read, regardless of its being set to input or

output. So if a pin is set to an input, you will read the value on the pin regardless of the

2. If a pin is set to output, sa y it has a one in the data latch; if it is shorted to ground y ou will

still read a zero on the pin. This is very useful for building fault tolerant systems, or han-

dling I2C™ bus conﬂicts . (The I2C bus is only driv en lo w, and the pin is tristated for a one.

If the pin is low and you are not driving it, some other device is trying to take the bus).

3. Mid-Range MCU devices all have at least one open drain (or open collector) pin. These

pins can only drive a zero or tristate. For most Mid-Range devices this is pin RA4. Open

drain pins must have a pull-up resistor to have a high state. This pin is useful for driving

odd voltage loads. The pull-up can be connected to a voltage (typically less than VDD)

which becomes the high state.

Question 3:

I have a PIC16CXXX with pin RB0 conﬁgured as an interrupt input, but am

not getting interrupted. When I change my routine to poll the pin, it reads

the high input and operates ﬁne. What is the problem?

Answer 3:

PORTB accepts TTL input levels (on most parts), so when you have an input of say 3V (with

VDD = 5V), you will read a one. However the buffer to the interrupt structure from pin RB0 is

Schmitt Trigger, which requires a higher voltage (than TTL input) before the high input is regis-

tered. So it is possible to read a one, but not get the interrupt. The interrupt was given a Schmitt

Trigger input with hysteresis to minimize noise prob lems. It is one thing to hav e short noise spikes

on a pin that is a data input that can potentially cause bad data, but quite another to permit noise

to cause an interrupt, hence the difference.

I2C is a trademark of Philips Corporation.

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-18  1997 Microchip Technology Inc.

Question 4:

When I perform a BCF instruction, other pins get cleared in the port. Why?

Answer 4:

1. Another case where a read-modify-write instruction ma y seem to change other pin v alues

unexpectedly can be illustrated as follows: Suppose you make PORTC all outputs and

drive the pins low. On each of the por t pins is an LED connected to ground, such that a

high output lights it. Across each LED is a 100 µF capacitor. Let's also suppose that the

processor is running very fast, say 20 MHz. Now if you go down the port setting each pin

in order ; BSF PORTC,0 then BSF PORTC,1 then BSF PORTC,2 and so on, you may see

that only the last pin was set, and only the last LED actually turns on. This is because the

capacitors take a while to charge. As each pin was set, the pin before it was not charged

yet and so was read as a zero. This zero is written back out to the port latch (r-m-w,

remember) which clears the bit you just tried to set the instruction before. This is usually

only a concern at high speeds and for successive port operations, but it can happen, so

take it into consideration.

2. If this is on a PIC16C7XX device, you have not conﬁgured the I/O pins properly in the

ADCON1 register. If a pin is conﬁgured for analog input, any read of that pin will read a

zero, regardless of the voltage on the pin. This is an exception to the normal rule that the

pin state is alwa ys read. You can still conﬁgure an analog pin as an output in the TRIS reg-

ister , and drive the pin high or low b y writing to it, but you will alwa ys read a zero . Theref ore

if you e x ecute a Read-Modify-Write instruction (see previous question) all analog pins are

read as zero, and those not directly modiﬁed by the instruction will be wr itten back to the

port latch as zero. A pin conﬁgured as analog is e xpected to ha ve values that may be nei-

ther high nor low to a digital pin, or ﬂoating. Floating inputs on digital pins are a no-no , and

can lead to high current draw in the input buffer, so the input buffer is disabled.

 1997 Microchip Technology Inc. DS31009A-page 9-19

Section 9. I/O Ports

I/O Ports

9.13 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to I/O ports are:

Title Application Note #

Improving the Susceptibility of an Application to ESD AN595

Clock Design using Low Power/Cost Techniques AN615

Implementing Wake-up on Keystroke AN528

Interfacing to AC Power Lines AN521

Multiplexing LED Drive and a 4 x 4 Keypad Sampling AN529

Using PIC16C5X as an LCD Drivers AN563

Serial Port Routines Without Using TMR0 AN593

Implementation of an Asynchronous Serial I/O AN510

Using the PORTB Interrupt on Change Feature as an External Interrupt AN566

Implementing Wake-up on Keystroke AN522

Apple Desktop Bus AN591

Software Implementation of Asynchronous Serial I/O AN555

Communicating with the I2C Bus using the PIC16C5X AN515

Interfacing 93CX6 Serial EEPROMs to the PIC16C5X Microcontrollers AN530

Logic Powered Serial EEPROMs AN535

Interfacing 24LCXXB Serial EEPROMs to the PIC16C54 AN567

Using the 24XX65 and 24XX32 with Stand-alone PIC16C54 Code AN558

PICmicro MID-RANGE MCU FAMILY

DS31009A-page 9-20  1997 Microchip Technology Inc.

9.14 Revision History

Revision A

This is the initial released revision of the I/O Ports description.

 1997 Microchip Technology Inc.   DS31010A page 10-1
M
Parallel 
Slave Port
10
Section 10. Parallel Slave Port
HIGHLIGHTS
This section of the manual contains the following major topics:
10.1 Introduction..................................................................................................................10-2
10.2 Control Register...........................................................................................................10-3
10.3 Operation .....................................................................................................................10-4
10.4 Operation in Sleep Mode .............................................................................................10-5
10.5 Effect of a Reset...........................................................................................................10-5
10.6 PSP Wa vef orms...........................................................................................................10-5
10.7 Design Tips ..................................................................................................................10-6
10.8 Related Application Notes............................................................................................10-7
10.9 Revision History...........................................................................................................10-8

PICmicro MID-RANGE MCU FAMILY

DS31010A-page 10-2  1997 Microchip Technology Inc.

10.1 Introduction

Some devices have an 8-bit wide Parallel Slave Port (PSP). This port is multiplexed onto one of

the de vices I/O ports. The POR T operates as an 8-bit wide P arallel Slav e P ort, or microprocessor

port, when the PSPMODE control bit is set. In this mode, the input buffers are TTL.

In slav e mode the module is asynchronously readable and writable b y the e xternal world through

RD control input pin and the WR control input pin.

It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can

read or write the PORT latch as an 8-bit latch. Setting the PSPMODE bit enables port pins to be

the RD input, the WR input, and the CS (chip select) input.

There are actually two 8-bit latches, one for data-out (from the PICmicro) and one for data input.

The user writes 8-bit data to PORT data latch and reads data from the port pin latch (note that

they have the same address). In this mode, the TRIS register is ignored, since the microproces-

sor is controlling the direction of data ﬂow.

Figure 10-1 shows the block diagram for the PSP.

Figure 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)

Note 1: At present the Parallel Slave Port (PSP) is only multiplexed onto PORTD and

POR TE. The microprocessor port becomes enabled when the PSPMODE bit is set.

In this mode, the user must make sure that PORTD and PORTE are conﬁgured as

digital I/O. That is, peripheral modules multiplexed onto the PSP functions are dis-

abled (such as the A/D).

When PORTE is conﬁgured for digital I/O. PORTD will override the values in the

TRISD register.

Note 2: In this mode the PORTD and PORTE input buffers are TTL. The control bits for the

PSP operation are located in TRISE.

Data bus

WR Port

RD Port

One bit of PORTD

Set interrupt ﬂag

PSPIF

PSP7:PSP0

TTL

Read

Chip Select

Write

Note: I/O pins have protection diodes to VDD and VSS.

TTL

 1997 Microchip Technology Inc. DS31010A-page 10-3

Section 10. Parallel Slave Port

Parallel

Slave Port

10.2 Control Register

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0

bit 7 bit 0

bit 7 IBF: Input Buffer Full Status bit

1 = A word has been received and waiting to be read by the CPU

0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overﬂow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read

(must be cleared in software)

0 = No overﬂow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode

0 = General purpose I/O mode

bit 3 Unimplemented: Read as '0'

bit 2 TRISE2: RE2 direction control bit

1 = Input

0 = Output

bit 1 TRISE1: RE1 direction control bit

1 = Input

0 = Output

bit 0 TRISE0: RE0 direction control bit

1 = Input

0 = Output

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31010A-page 10-4  1997 Microchip Technology Inc.

10.3 Operation

A write to the PSP from the external system, occurs when both the CS and WR lines are ﬁrst

detected low . When either the CS or WR lines become high (edge triggered), the Input Buffer Full

status ﬂag bit IBF (TRISE<7>) is set on the Q4 clock cycle , f ollo wing the next Q2 cycle, to signal

the write is complete. The interr upt ﬂag bit, PSPIF, is also set on the same Q4 clock cycle. The

IBF ﬂag bit is inhibited from being cleared f or additional TCY cycles (see parameter 66). If the IBF

ﬂag bit is cleared by reading the PORTD input latch, and this has to be a read-only instr uction

(i.e., MOVF) and not a read-modify-write instruction. The input Buff er Ov erﬂow status ﬂag bit IBO V

(TRISE<5>) is set if a second write to the Par allel Slave P ort is attempted when the previous b yte

has not been read out of the buffer.

A read from the PSP from the exter nal system, occurs when both the CS and RD lines are ﬁrst

detected low. The Output Buffer Full status ﬂag bit OBF (TRISE<6>) is cleared immediately indi-

cating that the PORTD latch was read by the external bus. When either the CS or RD pin

becomes high (edge triggered), the interrupt ﬂag bit PSPIF is set on the Q4 cloc k cycle, f ollowing

the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to

PORTD by the user ﬁrmware.

Input Buffer Full Status Flag bit IBF, is set if a received word is waiting to be read by the CPU.

Once the PORT input latch is read, the IBF bit is cleared. The IBF bit is a read only status bit.

Output Buff er Full Status Flag bit OBF, is set if a word written to POR T latch is w aiting to be read

by the e xternal b us. Once the PORTD output latch is read b y the microprocessor , OBF is cleared.

Input Buffer Overﬂow Status Flag bit IBOV is set if a second write to the microprocessor port is

attempted when the previous word has not been read by the CPU (the ﬁrst word is retained in

the buffer).

When not in Parallel Slave Por t mode, the IBF and OBF bits are held clear. However, if ﬂag bit

IBOV was previously set, it must be cleared in the software.

An interrupt is generated and latched into ﬂag bit PSPIF when a read or a write operation is com-

pleted. Interr upt ﬂag bit PSPIF must be cleared by user software and the interrupt can be dis-

abled by clearing interrupt enable bit PSPIE.

Table 10-1: PORTE Functions

Name Function

RD Read Control Input in parallel slave port mode:

1 = Not a read operation

0 = Read operation. Reads PORTD register (if chip selected)

WR Write Control Input in parallel slave port mode:

1 = Not a write operation

0 = Write operation. Writes PORTD register (if chip selected)

CS Chip Select Control Input in parallel slave port mode:

1 = Device is not selected

0 = Device is selected

Note: The PSP may have other functions multiplexed onto the same pins. For the PSP to

operate, the pins must be conﬁgured as digital I/O.

 1997 Microchip Technology Inc. DS31010A-page 10-5

Section 10. Parallel Slave Port

Parallel

Slave Port

10.4 Operation in Sleep Mode

When in sleep mode the microprocessor may still read and wr ite the Parallel Slave Por t. These

actions will set the PSPIF bit. If the PSP interrupts are enab led, this will wak e the processor from

sleep mode so that the PSP data latch may be either read, or wr itten with the next value for the

microprocessor.

10.5 Effect of a Reset

After any reset the PSP is disabled and PORTD and PORTE are forced to their default mode.

10.6 PSP Waveforms

Figure 10-2 shows the waveform for a write from the microprocessor to the PSP, while

Figure 10-3 shows the waveform for a read of the PSP by the microprocessor.

Figure 10-2: Parallel Slave Port Write Waveforms

Figure 10-3: Parallel Slave Port Read Waveforms

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

OBF

PSPIF

PORTD<7:0>

Note: The IBF ﬂag bit is inhibited from being cleared until after this point.

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

PICmicro MID-RANGE MCU FAMILY

DS31010A-page 10-6  1997 Microchip Technology Inc.

10.7 Design Tips

Question 1:

Migrating from the PIC16C74 to the PIC16C74A, the operation of the PSP

seems to have changed.

Answer 1:

Yes, a design change was made so the PIC16C74A is edge sensitive (while the PIC16C74 was

level sensitive). See Appendix C.9 for more information.

 1997 Microchip Technology Inc. DS31010A-page 10-7

Section 10. Parallel Slave Port

Parallel

Slave Port

10.8 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to the Parallel

Slave Port are:

Title Application Note #

Using the 8-bit Parallel Slave Port AN579

PICmicro MID-RANGE MCU FAMILY

DS31010A-page 10-8  1997 Microchip Technology Inc.

10.9 Revision History

Revision A

This is the initial released revision of the Parallel Slave Port description.

 1997 Microchip Technology Inc.   DS31011A page 11-1
Timer0
11
M
Section 11. Timer0
HIGHLIGHTS
This section of the manual contains the following major topics:
11.1 Introduction..................................................................................................................11-2
11.2 Control Register...........................................................................................................11-3
11.3 Operation .....................................................................................................................11-4
11.4 TMR0 Interrupt.............................................................................................................11-5
11.5 Using Timer0 with an External Clock...........................................................................11-6
11.6 TMR0 Prescaler...........................................................................................................11-7
11.7 Design Tips ................................................................................................................11-10
11.8 Related Application Notes..........................................................................................11-11 
11.9 Revision History.........................................................................................................11-12

PICmicro MID-RANGE MCU FAMILY

DS31011A-page 11-2  1997 Microchip Technology Inc.

11.1 Introduction

The Timer0 module has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Clock source selectable to be external or internal

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 11-1 shows a simpliﬁed block diagram of the Timer0 module.

Figure 11-1: Timer0 Block Diagram

Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler

to the Watchdog Timer.

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 11-6 for detailed block diagram).

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0 Set interrupt

ﬂag bit T0IF

on overﬂow

 1997 Microchip Technology Inc. DS31011A-page 11-3

Section 11. Timer0

Timer0

11.2 Control Register

The OPTION_REG register is a readable and writable register which contains v arious control bits

to conﬁgure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups

on PORTB.

Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler

to the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU (1) INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU (1): Weak Pull-up Enable bit

1 = Weak pull-ups are disabled

0 = Weak pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2:0 PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

Note 1: Some devices call this bit GPPU. Devices that have the RBPU bit, have the weak

pull-ups on PORTB, while devices that have the GPPU have the weak pull-ups on

the GPIO Port.

PICmicro MID-RANGE MCU FAMILY

DS31011A-page 11-4  1997 Microchip Technology Inc.

11.3 Operation

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 mod-

ule will increment every instr uction cycle (without prescaler). If the TMR0 register is written, the

increment is inhibited for the following two instruction cycles (Figure 11-2 and Figure 11-3). The

user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit (OPTION<5>). In counter mode, Timer0 will

increment either on e very rising or falling edge of the T0CKI pin. The incrementing edge is deter-

mined by the Timer0 Source Edge Select the T0SE bit (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external clock input are discussed in detail in Subsec-

tion 11.5 “Using Timer0 with an External Clock” .

The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog

Timer. The prescaler assignment is controlled in software by the PSA control bit (OPTION<3>).

Clearing the PSA bit will assign the prescaler to the Timer0 module. The prescaler is not readable

or writable. When the prescaler is assigned to the Timer0 module, prescale v alues of 1:2, 1:4,...,

1:256 are selectable . Subsection 11.6 “TMR0 Prescaler” details the oper ation of the prescaler.

Any write to the TMR0 register will cause a 2 instr uction cycle (2TCY) inhibit. That is, after the

TMR0 register has been written with the new v alue , TMR0 will not be incremented until the third

instruction cycle later (Figure 11-2). When the prescaler is assigned to the Timer0 module, any

write to the TMR0 register will immediately update the TMR0 register and clear the prescaler . The

incrementing of Timer0 (TMR0 and Prescaler) will also be inhibited 2 instruction cycles (TCY). So

if the prescaler is conﬁgured as 2, then after a write to the TMR0 register TMR0 will not increment

for 4 Timer0 clocks (Figure 11-3). After that, TMR0 will increment every prescaler number of

clocks later.

Figure 11-2: Timer0 Timing: Internal Clock/No Prescale

Figure 11-3: Timer0 Timing: Internal Clock/Prescale 1:2

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T

MO VWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,W MO VF TMR0,WMO VF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MO VWF TMR0 MO VF TMR0,WMO VF TMR0,WMOVF TMR0,W MO VF TMR0,WMOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

 1997 Microchip Technology Inc. DS31011A-page 11-5

Section 11. Timer0

Timer0

11.4 TMR0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This

overﬂow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE

(INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service rou-

tine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from

SLEEP since the timer is shut-off during SLEEP. See Figure 11-4 for Timer0 interrupt timing.

Figure 11-4: TMR0 Interrupt Timing

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit

FEh

GIE bit

INSTRUCTION

Instruction

fetched

PC PC +1 PC +1 0004h 0005h

Instruction

executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4TCY where TCY = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

FLOW

PICmicro MID-RANGE MCU FAMILY
DS31011A-page 11-6  1997 Microchip Technology Inc.
11.5  Using Timer0 with an External Clock 
When an exter nal clock input is used for Timer0, it must meet cer tain requirements as detailed
in 11.5.1 “External Clock Synchronization.”  These requirements ensure the external clock
can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.5.1 External Clock Synchronization
When no prescaler is used, the e xternal clock input is the same as the prescaler output.  The syn-
chronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase clocks (Figure 11-5). Therefore, it is nec-
essary f or  T0CKI to be high f or at least 2Tosc (and a small RC dela y of 20 ns) and low f or at least
2Tosc (and a small RC delay of 20 ns). Refer to  parameters 40 , 41 and 42 in the electrical spec-
iﬁcation of the desired device.
When a prescaler is used, the e xternal clock input is divided by an asynchronous ripple-counter
type prescaler so that the prescaler output is symmetrical. For the external clock to meet the
sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessar y
f or T0CKI to hav e a period of at least 4Tosc (and a small RC delay of 40 ns) divided b y the pres-
caler value .  The only requirement on T0CKI high and low time is that the y do not violate the min-
imum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical
speciﬁcation of the desired device.
11.5.2 TMR0 Increment Delay
Since the prescaler output is synchronized with the internal clocks, there is a small delay from
the time the exter nal clock edge occurs to the time the Timer0 module is actually incremented.
Figure 11-5 shows the delay from the external clock edge to the timer incrementing.
Figure 11-5: Timer0 Timing with External Clock     
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
(3) (1)

 1997 Microchip Technology Inc. DS31011A-page 11-7

Section 11. Timer0

Timer0

11.6 TMR0 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the

Watchdog Timer (Figure 11-6). For simplicity, this counter is being referred to as “prescaler” in

the Timer0 description. Thus , a prescaler assignment for the Timer0 module means that there is

no postscaler for the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale

ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g.,

CLRF TMR0, MOVWF TMR0, BSF TMR0,x....etc.) will clear the prescaler. When assigned to WDT,

a CLRWDT instruction will clear the prescaler along with the Watchdog Timer . The prescaler is not

readable or writable.

Figure 11-6: Block Diagram of the Timer0/WDT Prescaler

Note: There is only one prescaler available which is mutually exclusively shared between

the Timer0 module and the Watchdog Timer.

T0CKI pin

T0SE

CLKOUT (=Fosc/4)

SYNC

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set T0IF ﬂag bit

on Overﬂow

PSA

T0CS

PICmicro MID-RANGE MCU FAMILY

DS31011A-page 11-8  1997 Microchip Technology Inc.

11.6.1 Switching Prescaler Assignment

The prescaler assignment is fully under software control, i.e., it can be changed “on the ﬂy” during

program execution.

In Example 11-1, the ﬁrst modiﬁcation of the OPTION_REG does not need to be included if the

ﬁnal desired prescaler is other then 1:1. If the ﬁnal prescaler value is to be 1:1, then a temporary

prescale value is set (other than 1:!), and the ﬁnal prescale v alue is set in the last modiﬁcation of

OPTION_REG.

Example 11-1: Changing Prescaler (Timer0→WDT)

To change prescaler from the WDT to the Timer0 module use the sequence shown in

Example 11-2.

Example 11-2: Changing Prescaler (WDT→Timer0)

Note: To avoid an unintended device RESET, the following instruction sequence

(shown in Example 11-1) must be executed when changing the prescaler

assignment from Timer0 to the WDT. This sequence must be follo wed e v en if

the WDT is disabled.

1) BSF STATUS, RP0 ;Bank1

Lines 2 and 3 do

NOT have to be

included if the ﬁnal

desired prescale

value is other than

1:1. If 1:1 is ﬁnal

desired value, then a

temporary prescale

value is set in lines 2

and 3 and the ﬁnal

prescale value will

be set in lines 10

and 11.

2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of

3) MOVWF OPTION_REG ;other than 1:1

4) BCF STATUS, RP0 ;Bank0

5) CLRF TMR0 ;Clear TMR0 and prescaler

6) BSF STATUS, RP1 ;Bank1

7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value

8) MOVWF OPTION_REG ;

9) CLRWDT ;Clears WDT and prescaler

10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT

11) MOVWF OPTION_REG ;

12) BCF STATUS, RP0 ;Bank0

CLRWDT ; Clear WDT and prescaler

BSF STATUS, RP0 ; Bank1

MOVLW b'xxxx0xxx' ; Select TMR0, new prescale

MOVWF OPTION_REG ; value and clock source

BCF STATUS, RP0 ; Bank0

 1997 Microchip Technology Inc. DS31011A-page 11-9

Section 11. Timer0

Timer0

11.6.2 Initialization

Since Timer0 has a software programmable clock source, there are two examples to show the

initialization of Timer0 with each source. Example 11-3 shows the initialization for the internal

clock source (timer mode), while Example 11-4 shows the initialization for the external clock

source (counter mode).

Example 11-3: Timer0 Initialization (Internal Clock Source)

Example 11-4: Timer0 Initialization (External Clock Source)

CLRF TMR0 ; Clear Timer0 register

CLRF INTCON ; Disable interrupts and clear T0IF

BSF STATUS, RP0 ; Bank1

MOVLW 0xC3 ; PortB pull-ups are disabled,

MOVWF OPTION_REG ; Interrupt on rising edge of RB0

; Timer0 increment from internal clock

; with a prescaler of 1:16.

BCF STATUS, RP0 ; Bank0

;** BSF INTCON, T0IE ; Enable TMR0 interrupt

;** BSF INTCON, GIE ; Enable all interrupts

;

; The TMR0 interrupt is disabled, do polling on the overflow bit

;

T0_OVFL_WAIT

BTFSS INTCON, T0IF

GOTO T0_OVFL_WAIT

; Timer has overflowed

CLRF TMR0 ; Clear Timer0 register

CLRF INTCON ; Disable interrupts and clear T0IF

BSF STATUS, RP0 ; Bank1

MOVLW 0x37 ; PortB pull-ups are enabled,

MOVWF OPTION_REG ; Interrupt on falling edge of RB0

; Timer0 increment from external clock

; on the high-to-low transition of T0CKI

; with a prescaler of 1:256.

BCF STATUS, RP0 ; Bank0

;** BSF INTCON, T0IE ; Enable TMR0 interrupt

;** BSF INTCON, GIE ; Enable all interrupts

;

; The TMR0 interrupt is disabled, do polling on the overflow bit

;

T0_OVFL_WAIT

BTFSS INTCON, T0IF

GOTO T0_OVFL_WAIT

; Timer has overflowed

PICmicro MID-RANGE MCU FAMILY

DS31011A-page 11-10  1997 Microchip Technology Inc.

11.7 Design Tips

Question 1:

I am implementing a counter/clock, but the clock loses time or is

inaccurate.

Answer 1:

If you are polling TMR0 to see if it has rolled over to zero. You could do this by executing:

wait MOVF TMR0,W ; read the timer into W

BTFSS STATUS,Z ; see if it was zero, if so,

; break from loop

GOTO wait ; if not zero yet, keep waiting

Two possible scenarios to lose clock cycles are:

1. If you are incrementing TMR0 from the internal instruction clock, or an external source that

is about as f ast, the overﬂo w could occur during the two cycle GOTO, so you could miss it.

In this case the TMR0 source should be prescaled.

Or you could do a test to see if it has rolled o ver b y checking f or less than a nominal value:

Wait movlw 3

subwf TMR0,W

btfsc STATUS,C

goto Wait

2. When writing to TMR0, two instruction clock cycles are lost. Often you ha ve a speciﬁc time

period you want to count, say 100 decimal. In that case you might put 156 into TMR0

(256 - 100 = 156). Ho w ever, since two instruction cycles are lost when you write to TMR0

(for internal logic synchronization), you should actually write 158 to the timer.

 1997 Microchip Technology Inc. DS31011A-page 11-11

Section 11. Timer0

Timer0

11.8 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to Timer0 are:

Title Application Note #

Frequency Counter Using PIC16C5X AN592

A Clock Design using the PIC16C54 for LED Display and Switch Inputs AN590

PICmicro MID-RANGE MCU FAMILY

DS31011A-page 11-12  1997 Microchip Technology Inc.

11.9 Revision History

Revision A

This is the initial released revision of the Timer0 Module description.

 1997 Microchip Technology Inc.   DS31012A page 12-1
M
Timer1
12
Section 12. Timer1
HIGHLIGHTS
This section of the manual contains the following major topics:
12.1 Introduction..................................................................................................................12-2
12.2 Control Register...........................................................................................................12-3
12.3 Timer1 Operation in Timer Mode .................................................................................12-4
12.4 Timer1 Operation in Synchronized Counter Mode.......................................................12-4
12.5 Timer1 Operation in Asynchronous Counter Mode......................................................12-5 
12.6 Timer1 Oscillator..........................................................................................................12-7
12.7 Sleep Operation...........................................................................................................12-9
12.8 Resetting Timer1 Using a CCP Trigger Output ............................................................12-9
12.9 Resetting of Timer1 Register Pair (TMR1H:TMR1L)....................................................12-9
12.10 Timer1 Prescaler..........................................................................................................12-9
12.11 Initialization................................................................................................................12-10
12.12 Design Tips................................................................................................................12-12
12.13 Related Application Notes..........................................................................................12-13
12.14 Revision History.........................................................................................................12-14

PICmicro MID-RANGE MCU FAMILY

DS31012A-page 12-2  1997 Microchip Technology Inc.

12.1 Introduction

The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and

TMR1L) which are readable and writable . The TMR1 Register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The Timer1 Interrupt, if enabled, is generated on

overﬂow which is latched in the TMR1IF interrupt ﬂag bit. This interrupt can be enabled/disabled

by setting/clearing the TMR1IE interrupt enable bit.

Timer1 can operate in one of three modes:

• As a synchronous timer

• As a synchronous counter

• As an asynchronous counter

The operating mode is determined by clock select bit, TMR1CS (T1CON<1>), and the synchro-

nization bit, T1SYNC (Figure 12-1).

In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on

every rising edge of the external clock input on pin T1CKI.

Timer1 can be turned on and off using theTMR1ON control bit (T1CON<0>).

Timer1 also has an internal “reset input”, which can be generated by a CCP module.

Timer1 has the capability to operate off an e xternal crystal. When the Timer1 oscillator is enab led

(T1OSCEN is set), the T1OSI and T1OSO pins become inputs . That is, their corresponding TRIS

values are ignored.

Figure 12-1: Timer1 Block Diagram

TMR1H TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS1:T1CKPS0 SLEEP input

T1OSCEN

Enable

Oscillator(1) FOSC/4

Internal

Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8 Synchronize

det

Synchronized

clock input

T1OSO/

T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned

off. This eliminates power drain.

Set TMR1IF ﬂag bit

on Overﬂow TMR1

T1CKI

CLR

CCP Special Trigger

 1997 Microchip Technology Inc. DS31012A-page 12-3

Section 12. Timer1

Timer1

12.2 Control Register

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7:6 Unimplemented: Read as '0'

bit 5:4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable bit

1 = Oscillator is enabled

0 = Oscillator is shut off. The oscillator inverter and feedback resistor are turned off to

eliminate power drain

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY
DS31012A-page 12-4  1997 Microchip Technology Inc.
12.3  Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock
to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since
the internal clock is always synchronized.
12.4  Timer1 Operation in Synchronized Counter Mode
Counter mode is selected by setting the TMR1CS bit.  In this mode the timer increments on e v ery
rising edge of clock input on the T1OSI pin when the oscillator enable bit (T1OSCEN) is set, or
the T1OSO/T1CKI pin when the T1OSCEN bit is cleared.
If the T1SYNC bit is cleared, then the external clock input is synchronized with internal phase
clocks . The synchronization is done after the prescaler stage. The prescaler is an asynchronous
ripple-counter.
In this conﬁguration, during SLEEP mode, Timer1 will not increment even if the external clock is
present, since the synchronization circuit is shut off. The prescaler however will continue to
increment.
12.4.1 External Clock Input Timing for Synchronized Counter Mode
When an e xternal cloc k input is used for Timer1 in synchronized counter mode, it m ust meet cer-
tain requirements. The external clock requirement is due to internal phase clock (Tosc) synchro-
nization. Also, there is a delay in the actual incrementing of TMR1 after synchronization.
When the prescaler is 1:1, the e xternal clock input is the same as the prescaler output.  The syn-
chronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler
output on alternating Tosc clocks of the inter nal phase clocks. Therefore, it is necessary for the
T1CKI pin to be high for at least 2Tosc (and a small RC delay) and low for at least 2Tosc (and a
small RC delay).  Refer to parameters 45, 46, and 47 in the “Electrical Speciﬁcations”  section.     
When a prescaler other than 1:1 is used, the e xternal clock input is divided by the asynchronous
ripple-counter prescaler so that the prescaler output is symmetrical. In order for the external
clock to meet the sampling requirement, the ripple-counter must be taken into account. There-
fore, it is necessar y for the T1CKI pin to have a period of at least 4Tosc (and a small RC delay)
divided by the prescaler value. Another requirement on the T1CKI pin high and low time is that
they do not violate the minimum pulse width requirements). Refer to parameters 40, 42, 45, 46,
and 47 in the “Electrical Speciﬁcations” section.     

 1997 Microchip Technology Inc. DS31012A-page 12-5

Section 12. Timer1

Timer1

12.5 Timer1 Operation in Asynchronous Counter Mode

If T1SYNC (T1CON<2>) is set, the e xternal clock input is not synchronized. The timer continues

to increment asynchronously to the internal phase clocks. The timer will continue to run during

SLEEP and can generate an interrupt on overﬂow which will wake-up the processor. However,

special precautions in software are needed to read/write the timer (Subsection 12.5.2 “Reading

and Writing Timer1 in Asynchronous Counter Mode”). Since the counter can operate in

sleep, Timer1 can be used to implement a true real-time clock.

In asynchronous counter mode, Timer1 cannot be used as a time-base for capture or compare

operations.

12.5.1 External Clock Input Timing with Unsynchronized Clock

If the T1SYNC control bit is set, the timer will increment completely asynchronously. The input

clock m ust meet certain minimum high time and low time requirements . Refer to the De vice Data

Sheet Electrical Speciﬁcations Section, timing parameters 45, 46, and 47.

12.5.2 Reading and Writing Timer1 in Asynchronous Counter Mode

Reading TMR1H or TMR1L while the timer is running from an exter nal asynchronous clock, will

guarantee a valid read (taken care of in hardware). However, the user should keep in mind that

reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may

overﬂow between the reads.

F or writes, it is recommended that the user simply stop the timer and write the desired values . A

write contention may occur b y writing to the timer registers while the register is incrementing. This

may produce an unpredictable value in the timer register.

Reading the 16-bit value requires some care, since two separate reads are required to read the

entire 16-bits. Example 12-1 shows why this may not be a straight forward read of the 16-bit

Example 12-1: Reading 16-bit Register Issues

TMR1 Sequence 1 Sequence 2

Action TMPH:TMPL Action TMPH:TMPL

04FFh READ TMR1L xxxxh READ TMR1H xxxxh

0500h Store in TMPL xxFFh Store in TMPH 04xxh

0501h READ TMR1H xxFFh READ TMR1L 04xxh

0502h Store in TMPH 05FFh Store in TMPL 0401h

PICmicro MID-RANGE MCU FAMILY

DS31012A-page 12-6  1997 Microchip Technology Inc.

Example 12-2 shows a routine to read the 16-bit timer v alue with e xperiencing the issues shown

in Example 12-1. This is useful if the timer cannot be stopped.

Example 12-2: Reading a 16-bit Free-Running Timer

Writing a 16-bit value to the 16-bit TMR1 register is straight forward. First the TMR1L register is

cleared to ensure that there are many Timer1 cloc k/oscillator cycles before there is a rollo ver into

the TMR1H register. The TMR1H register is then loaded, and ﬁnally the TMR1L register is loaded.

Example 12-3 shows this:

Example 12-3: Writing a 16-bit Free Running Timer

; All interrupts are disabled

MOVF TMR1H, W ; Read high byte

MOVWF TMPH ;

MOVF TMR1L, W ; Read low byte

MOVWF TMPL ;

MOVF TMR1H, W ; Read high byte

SUBWF TMPH, W ; Sub 1st read with 2nd read

BTFSC STATUS,Z ; Is result = 0

GOTO CONTINUE ; Good 16-bit read

;

; TMR1L may have rolled over between the read of the high and low bytes.

; Reading the high and low bytes now will read a good value.

;

MOVF TMR1H, W ; Read high byte

MOVWF TMPH ;

MOVF TMR1L, W ; Read low byte

MOVWF TMPL ;

; Re-enable the Interrupt (if required)

CONTINUE ; Continue with your code

; All interrupts are disabled

CLRF TMR1L ; Clear Low byte, Ensures no

; rollover into TMR1H

MOVLW HI_BYTE ; Value to load into TMR1H

MOVWF TMR1H, F ; Write High byte

MOVLW LO_BYTE ; Value to load into TMR1L

MOVWF TMR1H, F ; Write Low byte

; Re-enable the Interrupt (if required)

CONTINUE ; Continue with your code

 1997 Microchip Technology Inc. DS31012A-page 12-7

Section 12. Timer1

Timer1

12.6 Timer1 Oscillator

A cr ystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (ampliﬁer output). It

is enabled by setting the T1OSCEN control bit (T1CON<3>). The oscillator is a low power

oscillator, rated up to 200 kHz operation. It will continue to run during SLEEP. It is primarily

intended f or a 32 kHz crystal, which is an ideal frequency for real-time k eeping. Table 12-1 shows

the capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator . The user must provide a softw are time delay

to ensure proper oscillator start-up.

Table 12-1: Capacitor Selection for the Timer1 Oscillator

Note: This allows the counter to operate (increment) when the device is in sleep mode,

which allows Timer1 to be used as a real-time clock.

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF

200 kHz 15 pF 15 pF

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

100 kHz Epson C-2 100.00 KC-P ± 20 PPM

200 kHz STD XTL 200.000 kHz ± 20 PPM

Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up

time.

2: Since each resonator/crystal has its own characteristics, the user should consult the

resonator/crystal manufacturer for appropriate values of external components.

PICmicro MID-RANGE MCU FAMILY

DS31012A-page 12-8  1997 Microchip Technology Inc.

12.6.1 Typical Application

This f eature is typically used in applications where real-time needs to be kept, b ut it is also desir-

able to have the lowest possible power consumption. The Timer1 oscillator allows the device to

be placed in sleep, while the timer continues to increment. When Timer1 overﬂows the interrupt

could wake-up the device so that the appropriate registers could be updated.

Figure 12-2: Timer1 Application

44 x 4

Keypad

current sink

TMR1

VSS

PIC16CXXX

VDD

32 kHz

Backup

Battery

power-down

detect

T1OSI

T1OSO

OSC1

 1997 Microchip Technology Inc. DS31012A-page 12-9

Section 12. Timer1

Timer1

12.7 Sleep Operation

When Timer1 is conﬁgured for asynchronous operation, the TMR1 registers will continue to

increment for each timer clock (or prescale multiple of clocks). When the TMR1 register over-

ﬂows, the TMR1IF bit will get set, and if enabled generate an interrupt that will wake the

processor from sleep mode.

The Timer1 oscillator will add a delta current, due to the operation of this circuitr y. That is, the

power-down current will no longer only be the leakage current of the device, but also the active

current of the Timer1 oscillator and other Timer1 circuitry.

12.8 Resetting Timer1 Using a CCP Trigger Output

If a CCP module is conﬁgured in compare mode to generate a “special event trigger”

(CCP1M3:CCP1M0 = 1011), this signal resets Timer1.

Timer1 must be conﬁgured for either timer or synchronized counter mode to take advantage of

the special event trigger feature. If Timer1 is r unning in asynchronous counter mode, this reset

operation may not work, and should not be used.

In the event that a write to Timer1 coincides with a special event trigger from the CCP module,

the write will take precedence.

In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period

12.9 Resetting of Timer1 Register Pair (TMR1H:TMR1L)

TMR1H and TMR1L registers are not reset on a POR or any other reset, only b y the CCP special

event triggers.

T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset. In any other reset,

the register is unaffected.

12.10 Timer1 Prescaler

The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.

Table 12-2: Registers Associated with Timer1 as a Timer/Counter

Note: The special event trigger from the CCP module does not set interrupt ﬂag bit

TMR1IF.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

resets

INTCON GIE PEIE T0IE INTE RBIE(2) T0IF INTF RBIF(2) 0000 000x 0000 000u

PIR TMR1IF (1) 00

PIE TMR1IE (1) 00

TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.

Shaded cells are not used by the Timer1 module.

Note 1: The placement of this bit is device dependent.

2: These bits may also be named GPIE and GPIF.

PICmicro MID-RANGE MCU FAMILY

DS31012A-page 12-10  1997 Microchip Technology Inc.

12.11 Initialization

Since Timer1 has a software programmable clock source, there are three examples to show the

initialization of each mode. Example 12-4 shows the initialization for the internal clock source,

Example 12-5 shows the initialization f or the e xternal cloc k source, and Example 12-6 shows the

initialization of the external oscillator mode.

Example 12-4: Timer1 Initialization (Internal Clock Source)

Example 12-5: Timer1 Initialization (External Clock Source)

CLRF T1CON ; Stop Timer1, Internal Clock Source,

; T1 oscillator disabled, prescaler = 1:1

CLRF TMR1H ; Clear Timer1 High byte register

CLRF TMR1L ; Clear Timer1 Low byte register

CLRF INTCON ; Disable interrupts

BSF STATUS, RP0 ; Bank1

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x30 ; Internal Clock source with 1:8 prescaler

MOVWF T1CON ; Timer1 is stopped and T1 osc is disabled

BSF T1CON, TMR1ON ; Timer1 starts to increment

;

; The Timer1 interrupt is disabled, do polling on the overflow bit

;

T1_OVFL_WAIT

BTFSS PIR1, TMR1IF

GOTO T1_OVFL_WAIT

;

; Timer has overflowed

;

BCF PIR1, TMR1IF

CLRF T1CON ; Stop Timer1, Internal Clock Source,

; T1 oscillator disabled, prescaler = 1:1

CLRF TMR1H ; Clear Timer1 High byte register

CLRF TMR1L ; Clear Timer1 Low byte register

CLRF INTCON ; Disable interrupts

BSF STATUS, RP0 ; Bank1

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x32 ; External Clock source with 1:8 prescaler

MOVWF T1CON ; Clock source is synchronized to device

; Timer1 is stopped and T1 osc is disabled

BSF T1CON, TMR1ON ; Timer1 starts to increment

;

; The Timer1 interrupt is disabled, do polling on the overflow bit

;

T1_OVFL_WAIT

BTFSS PIR1, TMR1IF

GOTO T1_OVFL_WAIT

;

; Timer has overflowed

;

BCF PIR1, TMR1IF

 1997 Microchip Technology Inc. DS31012A-page 12-11

Section 12. Timer1

Timer1

Example 12-6: Timer1 Initialization (External Oscillator Clock Source)

CLRF T1CON ; Stop Timer1, Internal Clock Source,

; T1 oscillator disabled, prescaler = 1:1

CLRF TMR1H ; Clear Timer1 High byte register

CLRF TMR1L ; Clear Timer1 Low byte register

CLRF INTCON ; Disable interrupts

BSF STATUS, RP0 ; Bank1

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x3E ; External Clock source with oscillator

MOVWF T1CON ; circuitry, 1:8 prescaler, Clock source

; is asynchronous to device

; Timer1 is stopped

BSF T1CON, TMR1ON ; Timer1 starts to increment

;

; The Timer1 interrupt is disabled, do polling on the overflow bit

;

T1_OVFL_WAIT

BTFSS PIR1, TMR1IF

GOTO T1_OVFL_WAIT

;

; Timer has overflowed

;

BCF PIR1, TMR1IF

PICmicro MID-RANGE MCU FAMILY

DS31012A-page 12-12  1997 Microchip Technology Inc.

12.12 Design Tips

Question 1:

Timer1 does not seem to be keeping accurate time.

Answer 1:

There are a few reasons that this could occur

1. You should never write to Timer1, where that could cause the loss of time. In most cases

that means you should not write to the TMR1L register, but if the conditions are ok, you

ma y write to the TMR1H register . Normally you write to the TMR1H register if you want the

Timer1 overﬂow interrupt to be sooner then the full 16-bit time-out.

2. You should ensure the your layout uses good PCB layout techniques so that noise does

not couple onto the Timer1 oscillator lines.

 1997 Microchip Technology Inc. DS31012A-page 12-13

Section 12. Timer1

Timer1

12.13 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to Timer1 are:

Title Application Note #

Using Timer1 in Asynchronous Clock Mode AN580

Low Power Real Time Clock AN582

Yet another Clock using the PIC16C92X AN649

PICmicro MID-RANGE MCU FAMILY

DS31012A-page 12-14  1997 Microchip Technology Inc.

12.14 Revision History

Revision A

This is the initial released revision of the Timer1 module description.

 1997 Microchip Technology Inc.   DS31013A page 13-1
M
Timer2
13
Section 13. Timer2
HIGHLIGHTS
This section of the manual contains the following major topics:
13.1 Introduction..................................................................................................................13-2
13.2 Control Register...........................................................................................................13-3
13.3 Timer Clock Source......................................................................................................13-4
13.4 Timer (TMR2) and Period (PR2) Registers..................................................................13-4
13.5 TMR2 Match Output.....................................................................................................13-4
13.6 Clearing the Timer2 Prescaler and Postscaler.............................................................13-4
13.7 Sleep Operation...........................................................................................................13-4
13.8 Initialization..................................................................................................................13-5
13.9 Design Tips ..................................................................................................................13-6
13.10 Related Application Notes............................................................................................13-7
13.11 Revision History...........................................................................................................13-8

PICmicro MID-RANGE MCU FAMILY

DS31013A-page 13-2  1997 Microchip Technology Inc.

13.1 Introduction

Timer2 is an 8-bit timer with a prescaler, a postscaler, and a period register. Using the prescaler

and postscaler at their maximum settings, the overﬂow time is the same as a 16-bit timer.

Timer2 is the PWM time-base when the CCP module(s) is used in the PWM mode.

Figure 13-1 shows a block diagram of Timer2. The postscaler counts the number of times that

the TMR2 register matched the PR2 register. This can be useful in reducing the overhead of the

interrupt service routine on the CPU performance.

Figure 13-1: Timer2 Block Diagram

Comparator

TMR2 Sets ﬂag

TMR2 reg

output (1)

Reset

Postscaler

Prescaler

PR2 reg

FOSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note: TMR2 register output can be software selected b y the SSP Module as a baud clock.

TOUTPS3:TOUTPS0

T2CKPS1:T2CKPS0

 1997 Microchip Technology Inc. DS31013A-page 13-3

Section 13. Timer2

Timer2

13.2 Control Register

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit

7bit 0

bit 7 Unimplemented: Read as '0'

bit 6:3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1:0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31013A-page 13-4  1997 Microchip Technology Inc.

13.3 Timer Clock Source

The Timer2 module has one source of input clock, the device clock (FOSC/4). A prescale option

of 1:1, 1:4 or 1:16 is software selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).

13.4 Timer (TMR2) and Period (PR2) Registers

The TMR2 register is readable and writable, and is cleared on all device resets. Timer2 incre-

ments from 00h until it matches PR2 and then resets to 00h on the ne xt increment cycle . PR2 is

a readable and writable register.

TMR2 is cleared when a WDT, POR, MCLR, or a BOR reset occurs, while the PR2 register is set.

Timer2 can be shut off (disabled from incrementing) by clearing the TMR2ON control bit

(T2CON<2>). This minimizes the power consumption of the module.

13.5 TMR2 Match Output

The match output of TMR2 goes to two sources:

1. Timer2 Postscaler

2. SSP Clock Input

There are four bits which select the postscaler. This allows the postscaler a 1:1 to 1:16 scaling

(inclusive). After the postscaler overﬂows, the TMR2 interrupt ﬂag bit (TMR2IF) is set to indicate

the Timer2 overﬂow. This is useful in reducing the softw are o v erhead of the Timer2 interrupt ser-

vice routine, since it will only execute once every postscaler # of matches.

The match output of TMR2 is also routed to the Synchronous Serial Port module, which ma y soft-

ware select this as the clock source for the shift clock.

13.6 Clearing the Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR reset, W atchdog Timer Reset, Brown-out Reset,

or Parity Error Reset)

13.7 Sleep Operation

During sleep, TMR2 will not increment. The prescaler will retain the last prescale count, ready f or

operation to resume after the device wakes from sleep.

Table 13-1: Registers Associated with Timer2

Note: When T2CON is written TMR2 does not clear.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR, PER

Value on

all other

resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

PIR TMR2IF (1) 00

PIE TMR2IE (1) 00

TMR2 Timer2 module’s register 0000 0000 0000 0000

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0'.

Shaded cells are not used by the Timer2 module.

Note 1: The position of this bit is device dependent.

 1997 Microchip Technology Inc. DS31013A-page 13-5

Section 13. Timer2

Timer2

13.8 Initialization

Example 13-1 shows how to initialize the Timer2 module, including specifying the Timer2 pres-

caler and postscaler.

Example 13-1: Timer2 Initialization

CLRF T2CON ; Stop Timer2, Prescaler = 1:1,

; Postscaler = 1:1

CLRF TMR2 ; Clear Timer2 register

CLRF INTCON ; Disable interrupts

BSF STATUS, RP0 ; Bank1

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x72 ; Postscaler = 1:15, Prescaler = 1:16

MOVWF T2CON ; Timer2 is off

BSF T2CON, TMR2ON ; Timer2 starts to increment

;

; The Timer2 interrupt is disabled, do polling on the overflow bit

;

T2_OVFL_WAIT

BTFSS PIR1, TMR2IF ; Has TMR2 interrupt occurred?

GOTO T2_OVFL_WAIT ; NO, continue loop

;

; Timer has overflowed

;

BCF PIR1, TMR2IF ; YES, clear flag and continue.

PICmicro MID-RANGE MCU FAMILY

DS31013A-page 13-6  1997 Microchip Technology Inc.

13.9 Design Tips

No related Design Tips at this time.

 1997 Microchip Technology Inc. DS31013A-page 13-7

Section 13. Timer2

Timer2

13.10 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to the Timer2

Module are:

Title Application Note #

Using the CCP Module AN594

Air Flow Control using Fuzzy Logic AN600

Adaptive Differential Pulse Code Modulation using PICmicros AN643

PICmicro MID-RANGE MCU FAMILY

DS31013A-page 13-8  1997 Microchip Technology Inc.

13.11 Revision History

Revision A

This is the initial released revision of the TImer2 module description.

 1997 Microchip Technology Inc.   DS31014A page 14-1
M
CCP
14
Section 14. Compare/Capture/PWM (CCP)
HIGHLIGHTS
This section of the manual contains the following major topics:
14.1 Introduction..................................................................................................................14-2
14.2 Control Register...........................................................................................................14-3
14.3 Capture Mode ..............................................................................................................14-4
14.4 Compare Mode ............................................................................................................14-6
14.5 PWM Mode ..................................................................................................................14-8
14.6 Initialization................................................................................................................14-12
14.7 Design Tips ................................................................................................................14-15
14.8 Related Application Notes..........................................................................................14-17
14.9 Revision History.........................................................................................................14-18

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-2  1997 Microchip Technology Inc.

14.1 Introduction

Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a

16-bit capture register , as a 16-bit compare register or as a 10-bit PWM master/sla ve Duty Cycle

special event trigger.

Each CCP module has 3 registers. Multiple CCP modules may e xist on a single de vice. Through-

out this section we use generic names for the CCP registers. These generic names are shown

in Table 14-1.

Table 14-1: Speciﬁc to Generic CCP Nomenclature

Table 14-2 shows the resources of the CCP modules, in each of its modes. While Table 14-3

shows the interactions between the CCP modules, where CCPx is one CCP module and CCPy

is another CCP module.

Table 14-2: CCP Mode - Timer Resource

Table 14-3: Interaction of Two CCP Modules

Generic Name CCP1 CCP2 Comment

CCPxCON CCP1CON CCP2CON CCP control register

CCPRxH CCPR1H CCPR2H CCP High byte

CCPRxL CCPR1L CCPR2L CCP Low byte

CCPx CCP1 CCP2 CCP pin

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1

Timer2

CCPx Mode CCPy Mode Interaction

Capture Capture Same TMR1 time-base .

Capture Compare The compare should be conﬁgured for the special event trigger,

which clears TMR1.

Compare Compare The compare(s) should be conﬁgured for the special e v ent trigger ,

which clears TMR1.

PWM PWM The PWMs will have the same frequency, and update rate

(TMR2 interrupt).

PWM Capture None

PWM Compare None

 1997 Microchip Technology Inc. DS31014A-page 14-3

Section 14. CCP

CCP

14.2 Control Register

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

bit 7:6 Unimplemented: Read as '0'

bit 5:4 DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0

Capture Mode:

Unused

Compare Mode:

Unused

PWM Mode:

These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight

bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3:0 CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCPx module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode,

Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)

1001 = Compare mode,

Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)

1010 = Compare mode,

Generate software interrupt on compare match

(CCPIF bit is set, CCP pin is unaffected)

1011 = Compare mode,

Trigger special event (CCPIF bit is set)

11xx = PWM mode

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-4  1997 Microchip Technology Inc.

14.3 Capture Mode

In Capture mode, CCPRxH:CCPRxL captures the 16-bit value of the TMR1 register when an

event occurs on pin CCPx. An event is deﬁned as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is

made, the interrupt request ﬂag bit, CCPxIF, is set. The CCPxIF bit must be cleared in software.

If another capture occurs bef ore the value in register CCPRx is read, the pre vious captured value

will be lost.

As can be seen in Figure 14-1, a capture does not reset the 16-bit TMR1 register. This is so

Timer1 can also be used as the timebase for other operations. The time between two captures

can easily be computed as the difference between the value of the second capture that of the

ﬁrst capture. When Timer1 overﬂows, the TMR1IF bit will be set and if enabled an interrupt will

occur, allowing the time base to be extended to greater than 16-bits.

14.3.1 CCP Pin Conﬁguration

In Capture mode, the CCPx pin should be conﬁgured as an input by setting its corresponding

TRIS bit.

Figure 14-1: Capture Mode Operation Block Diagram

The prescaler can be used to get a very ﬁne average resolution on a constant input frequency.

F or example, if we have a stable input frequency and we set the prescaler to 1:16, then the total

error f or those 16 periods is 1 TCY. This gives an eff ective resolution of TCY/16, which at 20 MHz

is 12.5 ns. This technique is only v alid where the input frequency is “stab le” over the 16 samples .

Without using the prescaler (1:1), each sample would have a resolution of TCY.

Note: Timer1 must be running in timer mode or synchronized counter mode for the CCP

module to use the capture feature. In asynchronous counter mode, the capture

operation may not work.

Note: If the CCPx pin is conﬁgured as an output, a write to the port can cause a capture

condition.

CCPRxH CCPRxL

TMR1H TMR1L

Set ﬂag bit CCPxIF

Capture

Enable

Q’s CCPxCON<3:0>

CCPx Pin

Prescaler

÷ 1, 4, 16

and

edge detect

 1997 Microchip Technology Inc. DS31014A-page 14-5

Section 14. CCP

CCP

14.3.2 Changing Between Capture Modes

When the Capture mode is changed, a capture interrupt may be generated. The user should

keep the CCPxIE bit clear to disable these interrupts and should clear the CCPxIF ﬂag bit

following any such change in operating mode.

14.3.2.1 CCP Prescaler

There are f our prescaler settings , speciﬁed b y bits CCPxM3:CCPxM0. Whenever the CCP mod-

ule is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This

means that any reset will clear the prescaler counter.

Switching from one capture prescale setting to another ma y generate an interrupt. Also , the pres-

caler counter will not be cleared, therefore the ﬁrst capture may be from a nonzero prescaler.

Example 14-1 shows the recommended method f or switching between capture prescale settings.

This example also clears the prescaler counter and will not generate the interrupt.

Example 14-1: Changing Between Capture Prescalers

To clear the Capture prescaler count, the CCP module must be conﬁgured into any non-capture

CCP mode (Compare, PWM, or CCP off modes).

14.3.3 Sleep Operation

When the de vice is placed in sleep, Timer1 will not increment (since it is in synchronous mode),

but the prescaler will continue to count events (not synchronized). When a speciﬁed capture

event occurs, the CCPxIF bit will be set, but the capture register will not be updated. If the CCP

interrupt is enabled, the device will wake-up from sleep. The value in the 16-bit TMR1 register is

not transf erred to the 16-bit capture register , b ut since the timer was not incrementing, this v alue

should not hav e any meaning. Eff ectiv ely, this allo ws the CCP pin to be used as another e xternal

interrupt.

14.3.4 Effects of a Reset

The CCP module is off, and the value in the capture prescaler is forced to 0.

CLRF CCP1CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load the W reg with the new prescaler

; mode value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with this value

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-6  1997 Microchip Technology Inc.

14.4 Compare Mode

In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control bits CCPxM3:CCPxM0 (CCPxCON<3:0>).

At the same time, a compare interrupt is also generated.

Figure 14-2: Compare Mode Operation Block Diagram

Note: Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP

module is using the compare f eature. In Asynchronous Counter mode, the compare

operation may not work.

CCPRxH CCPRxL

TMR1H TMR1L

Comparator

Output

Logic

Special Event

Trigger

Set ﬂag bit CCPxIF

match

CCPx Pin

TRIS CCPxCON<3:0>

Mode Select

Output Enable

 1997 Microchip Technology Inc. DS31014A-page 14-7

Section 14. CCP

CCP

14.4.1 CCP Pin Operation in Compare Mode

The user must conﬁgure the CCPx pin as an output by clearing the appropriate TRIS bit.

Selecting the compare output mode, forces the state of the CCP pin to the state that is opposite

of the match state. So if the Compare mode is selected to force the output pin lo w on match, then

the output will be forced high until the match occurs (or the mode is changed).

14.4.2 Software Interrupt Mode

When generate Software Interrupt mode is chosen, the CCPx pin is not affected. Only a CCP

interrupt is generated (if enabled).

14.4.3 Special Event Trigger

In this mode, an internal hardware trigger is generated which may be used to initiate an action.

The special event trigger output of CCPx resets the TMR1 register pair. This allows the CCPRx

For some devices, the special trigger output of the CCP module resets the TMR1 register pair,

and starts an A/D conversion (if the A/D module is enabled).

14.4.4 Sleep Operation

When the de vice is placed in sleep, Timer1 will not increment (since in synchronous mode), and

the state of the module will not change. If the CCP pin is driving a value, it will continue to dr ive

that value. When the device wakes-up, it will continue form this state.

14.4.5 Effects of a Reset

The CCP module is off.

Note: Clearing the CCPxCON register will force the CCPx compare output latch to the

default low level. This is not the Port I/O data latch.

Note: The special event trigger will not set the Timer1 interrupt ﬂag bit, TMR1IF.

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-8  1997 Microchip Technology Inc.

14.5 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM

output. Since the CCPx pin is multiplexed with the PORT data latch, the corresponding TRIS bit

must be cleared to make the CCPx pin an output.

Figure 14-3 shows a simpliﬁed block diagram of the CCP module in PWM mode.

F or a step by step procedure on ho w to set up the CCP module for PWM oper ation, see Subsec-

tion 14.5.3 “Set-up for PWM Operation.”

Figure 14-3: Simpliﬁed PWM Block Diagram

A PWM output (Figure 14-4) has a time-base (period) and a time that the output stays high (duty

cycle). The frequency of the PWM is the inverse of the period (1/period).

Figure 14-4: PWM Output

Note: Clearing the CCPxCON register will force the CCPx PWM output latch to the def ault

low level. This is not the port I/O data latch.

CCPRxL

CCPRxH (Slave)

Comparator

TMR2

Comparator

PR2

Duty cycle registers CCPxCON<5:4>

Clear Timer, CCPx pin

and latch the Duty Cycle

TRIS<y>

CCPx

Timer2 Module

(Note 1)

CCP Module

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to

create 10-bit time-base.

(DCxB9:DCxB2)

(DCxB1:DCxB0)

Period = PR2 + 1

TMR2 = PR2 + 1, TMR2 forced to 0h

TMR2 = Duty Cycle

TMR2 = PR2 + 1, TMR2 forced to 0h

Duty Cycle =

DCxB9:DCxB0

 1997 Microchip Technology Inc. DS31014A-page 14-9

Section 14. CCP

CCP

14.5.1 PWM Period

The PWM period is speciﬁed by writing to the PR2 register. The PWM period can be calculated

using the following formula:

PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value), speciﬁed in units of time

PWM frequency (FPWM) is deﬁned as 1 / [PWM period].

When TMR2 is equal to PR2, the following three events occur on the next increment cycle:

• TMR2 is cleared

• The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set)

• The PWM duty cycle is latched from CCPRxL into CCPRxH

14.5.2 PWM Duty Cycle

The PWM duty cycle is speciﬁed by writing to the CCPRxL register and to the DCxB1:DCxB0

(CCPxCON<5:4>) bits. Up to 10-bit resolution is av ailab le: the CCPRxL contains the eight MSbs

and CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by DCxB9:DCxB0.

The following equation is used to calculate the PWM duty cycle:

PWM duty cycle = (DCxB9:DCxB0 bits value) • Tosc • (TMR2 prescale value), in units of time

The DCxB9:DCxB0 bits can be written to at any time, b ut the duty cycle value is not latched into

CCPRxH until after a match between PR2 and TMR2 occurs (which is the end of the current

period). In PWM mode, CCPRxH is a read-only register.

The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle.

This double buffering is essential for glitchless PWM operation.

When CCPRxH and 2-bit latch match the value of TMR2 concatenated with the internal 2-bit

Q clock (or two bits of the TMR2 prescaler), the CCPx pin is cleared. This is the end of the duty

cycle.

Maximum PWM resolution (bits) for a given PWM frequency:

Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The

postscaler could be used to have a ser vo update rate at a different frequency than

the PWM output.

Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not

be cleared. This allows a duty cycle of 100%.

log( FPWM

log(2)

FOSC )bits

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-10  1997 Microchip Technology Inc.

14.5.2.2 Minimum Resolution

The minimum resolution (in time) of each bit of the PWM duty cycle depends on the prescaler of

Timer2.

Table 14-4: Minimum Duty Cycle Bit Time

Example 14-2: PWM Period and Duty Cycle Calculation

At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and a

20 MHz oscillator , i.e ., 0 ≤ DCxB9:DCxB0 ≤ 255. An y value g reater than 255 will result in a 100%

duty cycle.

In order to achie ve higher resolution, the PWM frequency must be decreased. In order to achie v e

higher PWM frequency, the resolution must be decreased.

Table 14-5 lists example PWM frequencies and resolutions for Fosc = 20 MHz. The TMR2 pres-

caler and PR2 values are also shown.

Table 14-5: Example PWM Frequencies and Bit Resolutions at 20 MHz

Prescaler

Value T2CKPS1:T2CKPS0 Minimum Resolution

(Time)

10 0 T

OSC

40 1 T

16 1 x 4 TCY

Desired PWM frequency is 78.125 kHz,

Fosc = 20 MHz

TMR2 prescale = 1

1/78.125 kHz= [(PR2) + 1] • 4 • 1/20 MHz • 1

12.8 µs = [(PR2) + 1] • 4 • 50 ns • 1

PR2 = 63

Find the maximum resolution of the duty cycle that can be used with a 78.125 kHz frequency

and 20 MHz oscillator:

1/78.125 kHz= 2PWM RESOLUTION • 1/20 MHz • 1

12.8 µs= 2

PWM RESOLUTION • 50 ns • 1

256 = 2PWM RESOLUTION

log(256) = (PWM Resolution) • log(2)

8.0 = PWM Resolution

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler

(1, 4, 16) 1641111

PR2 V alue 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum

Resolution (bits) 10 10 10 8 7 5.5

 1997 Microchip Technology Inc. DS31014A-page 14-11

Section 14. CCP

CCP

14.5.3 Set-up for PWM Operation

The following steps conﬁgure the CCP module for PWM operation:

1. Establish the PWM period by writing to the PR2 register.

2. Establish the PWM duty cycle by writing to the DCxB9:DCxB0 bits.

3. Make the CCPx pin an output by clearing the appropriate TRIS bit.

4. Establish the TMR2 prescale value and enable Timer2 by writing to T2CON.

5. Conﬁgure the CCP module for PWM operation.

14.5.4 Sleep Operation

When the device is placed in sleep, Timer2 will not increment, and the state of the module will

not change. If the CCP pin is driving a value, it will contin ue to driv e that value. When the device

wakes-up, it will continue from this state.

14.5.5 Effects of a Reset

The CCP module is off.

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-12  1997 Microchip Technology Inc.

14.6 Initialization

The CCP module has three modes of operation. Example 14-3 shows the initialization of capture

mode, Example 14-4 sho ws the initialization of compare mode, and Example 14-5 shows the ini-

tialization of PWM mode.

Example 14-3: Capture Initialization

CLRF CCP1CON ; CCP Module is off

CLRF TMR1H ; Clear Timer1 High byte

CLRF TMR1L ; Clear Timer1 Low byte

CLRF INTCON ; Disable interrupts and clear T0IF

BSF STATUS, RP0 ; Bank1

BSF TRISC, CCP1 ; Make CCP pin input

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x06 ; Capture mode, every 4th rising edge

MOVWF CCP1CON ;

BSF T1CON, TMR1ON ; Timer1 starts to increment

;

; The CCP1 interrupt is disabled,

; do polling on the CCP Interrupt flag bit

;

Capture_Event

BTFSS PIR1, CCP1IF

GOTO Capture_Event

;

; Capture has occurred

;

BCF PIR1, CCP1IF ; This needs to be done before next compare

 1997 Microchip Technology Inc. DS31014A-page 14-13

Section 14. CCP

CCP

Example 14-4: Compare Initialization

CLRF CCP1CON ; CCP Module is off

CLRF TMR1H ; Clear Timer1 High byte

CLRF TMR1L ; Clear Timer1 Low byte

CLRF INTCON ; Disable interrupts and clear T0IF

BSF STATUS, RP0 ; Bank1

BCF TRISC, CCP1 ; Make CCP pin output if controlling state of pin

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x08 ; Compare mode, set CCP1 pin on match

MOVWF CCP1CON ;

BSF T1CON, TMR1ON ; Timer1 starts to increment

;

; The CCP1 interrupt is disabled,

; do polling on the CCP Interrupt flag bit

;

Compare_Event

BTFSS PIR1, CCP1IF

GOTO Compare_Event

;

; Compare has occurred

;

BCF PIR1, CCP1IF ; This needs to be done before next compare

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-14  1997 Microchip Technology Inc.

Example 14-5: PWM Initialization

CLRF CCP1CON ; CCP Module is off

CLRF TMR2 ; Clear Timer2

MOVLW 0x7F ;

MOVWF PR2 ;

MOVLW 0x1F ;

MOVWF CCPR1L ; Duty Cycle is 25% of PWM Period

CLRF INTCON ; Disable interrupts and clear T0IF

BSF STATUS, RP0 ; Bank1

BCF TRISC, PWM1 ; Make pin output

CLRF PIE1 ; Disable peripheral interrupts

BCF STATUS, RP0 ; Bank0

CLRF PIR1 ; Clear peripheral interrupts Flags

MOVLW 0x2C ; PWM mode, 2 LSbs of Duty cycle = 10

MOVWF CCP1CON ;

BSF T2CON, TMR2ON ; Timer2 starts to increment

;

; The CCP1 interrupt is disabled,

; do polling on the TMR2 Interrupt flag bit

;

PWM_Period_Match

BTFSS PIR1, TMR2IF

GOTO PWM_Period_Match

;

; Update this PWM period and the following PWM Duty cycle

;

BCF PIR1, TMR2IF

 1997 Microchip Technology Inc. DS31014A-page 14-15

Section 14. CCP

CCP

14.7 Design Tips

Question 1:

What timers can I use for the capture and compare modes?

Answer 1:

The capture and compare modes are designed around Timer1, so no other timer can be used f or

these functions. This also means that if multiple CCP modules (in parts with more than one) are

being used for a capture or compare function, they will share the same timer.

Question 2:

What timers can I use with the PWM mode?

Answer 2:

The PWM mode is designed around Timer2, so no other timer can be used for this function. (It

is the only timer with a period register associated with it.) If multiple CCP modules (in parts with

more than one) are doing PWM they will share the same timer, meaning they will ha v e the same

PWM period and frequency.

Question 3:

Can I use one CCP module to do capture (or compare) AND PWM at the

same time, since they use different timers as their reference?

Answer 3:

The timers may be different, but other logic functions are shared. However you can switch from

one mode to the other. For a device with two CCP modules, you can also have CCP1 set up for

PWM and CCP2 set up for capture or compare (or vice versa) since they are two independent

modules.

Question 4:

How does a reset affect the CCP module?

Answer 4:

Any reset will turn the CCP module off. See the section on resets to see reset values.

Question 5:

I am setting up the CCP1CON module for “Compare Mode, trigger special

event” (1011) whic h resets TMR1. When a compare matc h occurs, will I have

both the TMR1 and the CCP1 interrupts pending (TMR1IF is set, CCP1IF is

set)?

Answer 5:

The CCP1IF ﬂag will be set on the match condition. TMR1IF is set when Timer1 overﬂows, and

the special trigger reset of Timer1 is not considered an overﬂow. However, if both the CCPR1L

and CCPR1H registers are set at FFh, then an overﬂow occurs at the same time as the match,

which will then set both CCP1IF and TMR1IF.

Question 6:

How do I use Timer2 as a general purpose timer, with an interrupt ﬂag on

rollover?

Answer 6:

Timer2 alwa ys resets to zero when it equals PR2 and ﬂag bit TMR2IF alwa ys gets set at this time.

By putting FFh into PR2, you will get an interrupt on overﬂow at FFh, as you would with Timer0,

f or instance. Quite often it is desir able to ha ve an e v ent occur at a periodic rate, perhaps an inter-

rupt driv en e v ent. Normally an initial value w ould be placed into the timer so that the ov erﬂow will

occur at the desired time. This value would have to be placed back into the timer every time it

overﬂowed to mak e the interrupts occur at the same desired rate. The beneﬁt of Timer2 is that a

value can be written to PR2 that will cause it to reset at your desired time inter val. This means

you do not ha ve the housek eeping chore of reloading the timer ev ery time it ov erﬂows, since PR2

maintains its value.

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-16  1997 Microchip Technology Inc.

Question 7:

I am using a CCP module in PWM mode. The duty cycle being output is

almost always 100%, even when my program writes a value like 7Fh to the

duty cycle register, which should be 50%. What am I doing wrong?

Answer 7:

1. The value in CCPRxL is higher than PR2. This happens quite often when a user desires

a f ast PWM output frequency and will write a small v alue in the PR2. In this case, if a v alue

of 7Eh were written to PR2, then a value 7Fh in CCPRxL will result in 100% duty cycle.

2. If the TRIS bit corresponding to the CCP output pin you are using is conﬁgured as an input,

the PWM output cannot drive the pin. In this case the pin would ﬂoat and duty cycle may

appear to be 0%, 100% or some other ﬂoating value.

Question 8:

I want to determine a signal frequency using the CCP module in capture

mode to ﬁnd the period. I am currently resetting Timer1 on the ﬁrst edge,

then using the value in the capture register on the second edge as the time

period. The problem is that my code to clear the timer does not occur until

almost twelve instructions after the ﬁrst capture edge (interrupt latency

plus saving of register s in interrupt) so I cannot measure very fast frequen-

cies. Is there a better way to do this?

Answer 8:

You do not need to zero the counter to ﬁnd the diff erence between two pulse edges . J ust take the

ﬁrst captured value and put it into another set of registers. Then when the second capture event

occurs, just subtract the ﬁrst event from the second. Assuming that your pulse edges are not so

f ar apart that the counter can wrap around past the last capture value, the answer will always be

correct. This is illustrated by the following example:

1. First captured value is FFFEh. Store this value in two registers.

2. The second capture value is 0001h (the counter has incremented three times).

3. 0001h - FFFEh = 0003, which is the same as if you had cleared Timer1 to zero and let it

count to 3. (Theoretically, except that there was a delay getting to the code that clears

Timer1, so actual values would differ).

The interrupt overhead is no w less important because the v alues are captured automatically. F or

even faster inputs do not enable interrupts and just test the ﬂag bit in a loop. If you must also

capture very long time periods, such that the timer can wrap around past the previous capture

value, then consider using an auto-scaling technique that starts with a large prescale and

shorten the prescale as you converge on the exact frequency.

 1997 Microchip Technology Inc. DS31014A-page 14-17

Section 14. CCP

CCP

14.8 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to the CCP

modules are:

Title Application Note #

Using the CCP Modules AN594

Implementing Ultrasonic Ranging AN597

Air Flow Control Using Fuzzy Logic AN600

Adaptive Differential Pulse Code Modulation AN643

PICmicro MID-RANGE MCU FAMILY

DS31014A-page 14-18  1997 Microchip Technology Inc.

14.9 Revision History

Revision A

This is the initial released revision of the CCP module description.

 1997 Microchip Technology Inc. DS31015A page 15-1

SSP

Section 15. Synchronous Serial Port (SSP)

HIGHLIGHTS

This section of the manual contains the following major topics:

15.1 Introduction..................................................................................................................15-2

15.2 Control Registers .........................................................................................................15-3

15.3 SPI Mode .....................................................................................................................15-6

15.4 SSP I2C Operation.....................................................................................................15-16

15.5 Initialization................................................................................................................15-26

15.6 Design Tips ................................................................................................................15-28

15.7 Related Application Notes..........................................................................................15-29

15.8 Revision History.........................................................................................................15-30

Note: Please refer to Appendix C.2 or the device data sheet to determine which devices

use this module.

I2C is a trademark of Philips Corporation.

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-2  1997 Microchip Technology Inc.

15.1 Introduction

The Synchronous Serial Por t (SSP) module is a serial interface useful for communicating with

other peripherals or microcontroller devices . These peripheral de vices ma y be serial EEPR OMs,

shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two

modes:

• Serial Peripheral Interface (SPI™)

• Inter-Integrated Circuit (I2C™)

- Slave mode

- I/O slope control, and Start and Stop bit detection to ease software implementation of

Master and Multi-master modes

SPI is a registered trademark of Motorola Corporation.

I2C is a trademark of Philips Corporation.

 1997 Microchip Technology Inc. DS31015A-page 15-3

Section 15. SSP

SSP

15.2 Control Registers

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P S R/W UA BF

bit 7 bit 0

bit 7 SMP: SPI data input sample phase

SPI Master Mode

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave Mode

SMP must be cleared when SPI is used in slave mode

bit 6 CKE: SPI Clock Edge Select (Figure 15-3, Figure 15-4, and Figure 15-5)

CKP = 0 (SSPCON<4>)

1 = Data transmitted on rising edge of SCK

0 = Data transmitted on falling edge of SCK

CKP = 1 (SSPCON<4>)

1 = Data transmitted on falling edge of SCK

0 = Data transmitted on rising edge of SCK

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit

(I2C mode only. This bit is cleared when the SSP module is disabled)

1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)

0 = Stop bit was not detected last

bit 3 S: Start bit

(I2C mode only. This bit is cleared when the SSP module is disabled)

1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)

0 = Start bit was not detected last

bit 2 R/W: Read/Write bit information (I2C mode only)

This bit holds the R/W bit inf ormation f ollowing the last address match. This bit is only valid from

the address match to the next start bit, stop bit, or not ACK bit.

1 = Read

0 = Write

bit 1 UA: Update Address (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2C modes)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit (I2C mode only)

1 = Transmit in progress, SSPBUF is full

0 = Transmit complete, SSPBUF is empty

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-4  1997 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overﬂow Indicator bit

In SPI mode:

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case

of ov erﬂo w, the data in SSPSR is lost and the SSPBUF is no longer updated. Overﬂow can

only occur in slave mode. The user must read the SSPBUF, even if only transmitting data,

to avoid setting overﬂow. In master mode the overﬂow bit is not set since each new recep-

tion (and transmission) is initiated by writing to the SSPBUF register.

0 = No overﬂow

In I2C mode:

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a

“don‘t care” in transmit mode. SSPOV must be cleared in software in either mode.

0 = No overﬂow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly conﬁgured as input or output.

In SPI mode:

1 = Enables serial port and conﬁgures SCK, SDO, SDI, and SS as the source of the

serial port pins

0 = Disables serial port and conﬁgures these pins as I/O port pins

In I2C mode:

1 = Enables the serial port and conﬁgures the SDA and SCL pins as the source of the

serial port pins

0 = Disables serial port and conﬁgures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2C mode:

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch) (Used to ensure data setup time)

 1997 Microchip Technology Inc. DS31015A-page 15-5

Section 15. SSP

SSP

bit 3:0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = FOSC/4

0001 = SPI master mode, clock = FOSC/16

0010 = SPI master mode, clock = FOSC/64

0011 = SPI master mode, clock = TMR2 output/2

0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin

0110 = I2C slave mode, 7-bit address

0111 = I2C slave mode, 10-bit address

1000 = Reserved

1001 = Reserved

1010 = Reserved

1011 = I2C firmware controlled master mode (slave idle)

1100 = Reserved

1101 = Reserved

1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ’0’ - n = Value at POR reset

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-6  1997 Microchip Technology Inc.

15.3 SPI Mode

The SPI mode allows 8-bits of data to be synchronously transmitted and received simulta-

neously. All four modes of SPI are suppor ted, as well as Microwire™ (sample edge) when the

SPI is in the master mode.

To accomplish communication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally a fourth pin may be used when in a slave mode of operation:

• Slave Select (SS)

15.3.1 Operation

When initializing the SPI, se veral options need to be speciﬁed. This is done by programming the

appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These

control bits allow the following to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of SCK)

• Data Input Sample Phase

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

Figure 15-1 shows the block diagram of the SSP module, when in SPI mode.

Figure 15-1: SSP Block Diagram (SPI Mode)

Read Write

Internal

data bus

SDI

SDO

SCK

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0 shift clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TCY

Prescaler

4, 16, 64

TRIS bit of SCK pin

Edge

Select

 1997 Microchip Technology Inc. DS31015A-page 15-7

Section 15. SSP

SSP

The SSP consists of a transmit/receiv e Shift Register (SSPSR) and a buffer register (SSPB UF).

The SSPSR shifts the data in and out of the device, MSb ﬁrst. The SSPBUF holds the data that

was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been

received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF

(SSPSTAT<0>), and interr upt ﬂag bit, SSPIF, are set. This double buffering of the received data

(SSPBUF) allows the next byte to start reception bef ore reading the data that was just received.

Any write to the SSPBUF register during transmission/reception of data will be ignored, and the

write collision detect bit, WCOL (SSPCON<7>), will be set. User software m ust clear the WCOL

bit so that it can be determined if the following write(s) to the SSPBUF register completed suc-

cessfully. When the application software is expecting to receive valid data, the SSPBUF should

be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF

(SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission

is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally the SSP Interrupt is used to deter mine when the transmis-

sion/reception has completed. The SSPBUF m ust be read and/or written. If the interrupt method

is not going to be used, then software polling can be done to ensure that a write collision does

not occur. Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The

shaded instruction is only required if the received data is meaningful (some SPI applications are

transmit only).

Example 15-1: Loading the SSPBUF (SSPSR) Register

The SSPSR is not directly readable or writable, and can only be accessed from addressing the

SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status

conditions.

BCF STATUS, RP1 ;Specify Bank1

BSF STATUS, RP0 ;

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

GOTO LOOP ;No

BCF STATUS, RP0 ;Specify Bank0

MOVF SSPBUF, W ;W reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

Microwire is a trademark of National Semiconductor.

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-8  1997 Microchip Technology Inc.

15.3.2 Enabling SPI I/O

To enable the serial por t the SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or

reconﬁgure SPI mode, clear the SSPEN bit which re-initializes the SSPCON register, and then

set the SSPEN bit. This conﬁgures the SDI, SDO, SCK, and SS pins as ser ial port pins. For the

pins to behave as the serial por t function, they must have their data direction bits (in the TRIS

• SDI must have the TRIS bit set

• SDO must have the TRIS bit cleared

• SCK (Master mode) must have the TRIS bit cleared

• SCK (Slave mode) must have the TRIS bit set

•SS

must have the TRIS bit set

Any serial port function that is not desired ma y be ov erridden by programming the corresponding

data direction (TRIS) register to the opposite value . An example would be in master mode where

you are only sending data (to a display driver), then both SDI and SS could be used as general

purpose outputs by clearing their corresponding TRIS register bits.

 1997 Microchip Technology Inc. DS31015A-page 15-9

Section 15. SSP

SSP

15.3.3 Typical Connection

Figure 15-2 shows a typical connection between two microcontrollers. The master controller

(Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both

shift registers on their programmed cloc k edge, and latched on the edge of the cloc k speciﬁed by

the SMP bit. Both processors should be programmed to same Clock Polarity (CKP), then both

controllers would send and receive data at the same time. Whether the data is meaningful (or

dummy data) depends on the application software. This leads to three scenarios for data trans-

mission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

Figure 15-2: SPI Master/Slave Connection

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-10  1997 Microchip Technology Inc.

15.3.4 Master Operation

The master can initiate the data transfer at any time because it controls the SCK. The master

determines when the slave (Processor 2) is to broadcast data by the software protocol.

In master mode the data is transmitted/receiv ed as soon as the SSPBUF register is written to. If

the SPI is only going to receive, the SDO output could be disabled (programmed as an input).

The SSPSR register will continue to shift in the signal present on the SDI pin at the progr ammed

clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal

received b yte (interrupts and status bits appropriately set). This could be useful in receiver appli-

cations as a “line activity monitor” mode.

The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then

would give waveforms for SPI communication as shown in Figure 15-3, Figure 15-4, and

Figure 15-5 where the MSb is transmitted ﬁrst. In master mode, the SPI clock rate (bit rate) is

user programmable to be one of the following:

•F

OSC/4 (or TCY)

•F

OSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate of 5 Mbps (at 20 MHz).

Figure 15-3: SPI Mode Waveform, Master Mode

4 clock

modes

Input

Sample (SMP = 0)

Input

Sample (SMP = 1)

SDI (SMP = 0) bit7 bit0

SDO (CKE = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit0

SDI (SMP = 1)

SSPIF

Write to

SSPBUF

SSPSR to

SSPBUF

SDO (CKE = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SCK (CKP = 0,

CKE = 0)

SCK (CKP = 0,

CKE = 1)

SCK (CKP = 1,

CKE = 0)

SCK (CKP = 1,

CKE = 1)

Next Q4 cycle

after Q2 ↓

 1997 Microchip Technology Inc. DS31015A-page 15-11

Section 15. SSP

SSP

15.3.5 Slave Operation

In slav e mode , the data is transmitted and receiv ed as the e xternal clock pulses appear on SCK.

When the last bit is latched, the interrupt ﬂag bit SSPIF is set.

The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then

would give waveforms for SPI communication as shown in Figure 15-3, Figure 15-4, and

Figure 15-5 where the MSb is transmitted ﬁrst. When in sla ve mode the e xternal clock must meet

the minimum high and low times.

In sleep mode, the slave can transmit and receive data. When a byte is received, the device will

wake-up from sleep, if the interrupt is enabled.

Figure 15-4: SPI Mode Waveform (Slave Mode With CKE = 0)

SCK (CKP = 1,

SCK (CKP = 0,

Input

Sample (SMP = 0)

SDI bit7 bit0

SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0

SSPIF

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

optional

Next Q4 Cycle

after Q2↓

bit7

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-12  1997 Microchip Technology Inc.

15.3.6 Slave Select Mode

When in slave select mode, the SS pin allows multi-drop for multiple slaves with a single

master. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRIS bit, for the

SS pin, must be set f or the slave select mode to be enabled. When the SS pin is lo w, trans-

mission and reception are enabled and the SDO pin is driven. When the SS pin goes high,

the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes

a ﬂoating output. External pull-up/ pull-down resistors may be desirable, depending on the

application.

When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI

module will reset if the SS pin is set to VDD. If the SPI is used in Slave Mode with the CKE bit is

set, then the SS pin control must be enabled.

When the SPI module resets, the bit counter is f orced to 0. This can be done by either by forcing

the SS pin to a high level or clearing the SSPEN bit (Figure 15-6).

To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the

SPI needs to operate as a receiver the SDO pin can be conﬁgured as an input. This disables

transmissions from the SDO . The SDI can alwa ys be left as an input (SDI function) since it cannot

create a bus conﬂict.

Figure 15-5: SPI Mode Waveform (Slave Select Mode With CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SSPIF

Interrupt

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

not optional

Next Q4 cycle

after Q2↓

 1997 Microchip Technology Inc. DS31015A-page 15-13

Section 15. SSP

SSP

Figure 15-6: Slave Synchronization Waveform

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit7

SDO bit7 bit6 bit7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit0

bit7 bit0

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-14  1997 Microchip Technology Inc.

15.3.7 Sleep Operation

In master mode all module clocks are halted, and the transmission/reception will remain in that

state until the de vice wak es from sleep. After the device returns to normal mode, the module will

continue to transmit/receive data.

In slav e mode, the SPI transmit/receiv e shift register operates asynchronously to the de vice. This

allows the de vice to be placed in sleep mode, and data to be shifted into the SPI transmit/receiv e

shift register. When all 8-bits have been received, the SSP interrupt ﬂag bit will be set and if

enabled will wake the device from sleep.

 1997 Microchip Technology Inc. DS31015A-page 15-15

Section 15. SSP

SSP

15.3.8 Effects of a Reset

A reset disables the SSP module and terminates the current transfer.

Table 15-1: Registers Associated with SPI Operation

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on all

other resets

INTCON GIE PEIE T0IE INTE RBIE(2) T0IF INTF RBIF(2) 0000 000x 0000 000u

PIR SSPIF (1) 00

PIE SSPIE (1) 00

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

TRISA — — PORTA Data Direction Register --11 1111 --11 1111

TRISC PORTC Data Direction Control Register 1111 1111 1111 1111

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI

mode.

Note 1: The position of this bit is device dependent.

2: These bits may also be named GPIE and GPIF.

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-16  1997 Microchip Technology Inc.

15.4 SSP I2C Operation

The SSP module in I2C mode fully implements all slave functions, except general call support,

and provides interrupts on start and stop bits in hardware to facilitate software implementations

of the master functions. The SSP module implements the standard mode speciﬁcations as well

as 7-bit and 10-bit addressing. Appendix A gives an overview of the I2C bus speciﬁcation.

Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SD A pin,

which is the data. The user must conﬁgure these pins as inputs through the TRIS bits. The SSP

module functions are enabled by setting SSP Enable bit, SSPEN (SSPCON<5>).

A “glitch” filter is on the SCL and SDA pins when the pin is an input. This ﬁlter operates in both

the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there

is a slew rate control of the pin that is independent of device frequency.

Figure 15-7: SSP Block Diagram (I2C Mode)

Read Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Address Match

Set, Reset

S, P bits

(SSPSTAT reg)

SCL

shift

clock

MSb LSb

SDA

 1997 Microchip Technology Inc. DS31015A-page 15-17

Section 15. SSP

SSP

The SSP module has ﬁve registers for I2C operation. They are:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly accessible

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I2C operation. Four mode selection bits

(SSPCON<3:0>) allow one of the following I2C modes to be selected:

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Firmware controlled Multi-Master mode (start and stop bit interrupts enabled)

•I

2C Firmware controlled Multi-Master mode (start and stop bit interrupts enabled)

•I

2C Firmware controlled Master mode, slave is idle

Bef ore selecting any I2C mode, the SCL and SD A pins must be prog rammed to inputs b y setting

the appropriate TRIS bits. Selecting an I2C mode, by setting the SSPEN bit, enables the SCL

and SDA pins to be used as the clock and data lines in I2C mode.

The SSPSTAT register gives the status of the data transfer. This infor mation includes detection

of a START or STOP bit, speciﬁes if the received byte w as data or address, if the next byte is the

completion of 10-bit address, and if this will be a read or write data transfer.

The SSPBUF is the register to which transf er data is written to or read from. The SSPSR register

shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a

doubled buffered receiver. This allows reception of the next byte to begin before reading the last

byte of received data. When the complete byte is received, it is transferred to the SSPBUF reg-

ister and ﬂag bit SSPIF is set. If another complete byte is received before the SSPBUF register

is read, a receiver overﬂow has occurred and the SSPOV bit (SSPCON<6>) is set and the byte

in the SSPSR is lost.

The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high

byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of

the address needs to be loaded (A7:A0).

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-18  1997 Microchip Technology Inc.

15.4.1 Slave Mode

In slav e mode, the SCL and SDA pins must be conﬁgured as inputs (TRIS set). The SSP module

will override the input state with the output data when required (slave-transmitter).

When an address is matched or the data transfer after an address match is received, the hard-

ware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF reg-

ister with the received value currently in the SSPSR register.

There are cer tain conditions that will cause the SSP module not to give this ACK pulse. These

are if either (or both):

a) The buffer full bit, BF (SSPSTAT<0>), was set before the message completed.

b) The overﬂow bit, SSPOV (SSPCON<6>), was set before the message completed.

In this case, the SSPSR register v alue is not loaded into the SSPBUF, b ut the SSPIF and SSPO V

bits are set. Table 15-2 sho ws what happens when a data transf er byte is receiv ed, given the sta-

tus of bits BF and SSPO V. The shaded cells show the condition where user software did not prop-

erly clear the overﬂo w condition. Flag bit BF is cleared by reading the SSPB UF register while bit

SSPOV is cleared through software.

The SCL clock input m ust ha ve a minimum high and low time for proper operation. The high and

low times of the I2C speciﬁcation as well as the requirement of the SSP module is shown in

Device Data Sheet electrical speciﬁcations parameters 100 and 101.

 1997 Microchip Technology Inc. DS31015A-page 15-19

Section 15. SSP

SSP

15.4.1.1 Addressing

Once the SSP module has been enabled, it waits for a START condition to occur. Following the

START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled

with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to

the value of the SSPADD register . The address is compared on the falling edge of the eighth clock

(SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the f ollo wing events

occur:

a) The SSPSR register value is loaded into the SSPBUF register on the falling edge of the

eight SCL pulse.

b) The buffer full bit, BF, is set on the falling edge of the eigth SCL pulse.

c) An ACK pulse is generated.

d) SSP interrupt ﬂag bit, SSPIF, is set (interrupt is generated if enabled) - on the f alling edge

of the ninth SCL pulse.

In 10-bit address mode, two address bytes need to be received by the slave. The ﬁve Most

Signiﬁcant bits (MSbs) of the ﬁrst address byte specify if this is a 10-bit address. The R/W bit

(SSPSTAT<2>) must specify a write so the sla ve de vice will receive the second address b yte. F or

a 10-bit address the ﬁrst byte w ould equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs

of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9 for

slave-transmitter:

1. Receive ﬁrst (high) byte of Address (the SSPIF, BF, and UA (SSPSTAT<1>) bits are set).

2. Update the SSPADD register with second (low) byte of Address (clears the UA bit and

releases the SCL line).

3. Read the SSPBUF register (clears the BF bit) and clear the SSPIF ﬂag bit.

4. Receive second (low) byte of Address (the SSPIF, BF, and UA bits are set).

5. Update the SSPADD register with the high byte of Address. This will clear the UA bit and

releases SCL line.

6. Read the SSPBUF register (clears the BF bit) and clear the SSPIF ﬂag bit.

7. Receive repeated START condition.

8. Receive ﬁrst (high) byte of Address (the SSPIF and BF bits are set).

9. Read the SSPBUF register (clears the BF bit) and clear the SSPIF ﬂag bit.

Table 15-2: Data Transfer Received Byte Actions

Note: Following the RESTART condition (step 7) in 10-bit mode, the user only needs to

match the ﬁrst 7-bit address. The user does not update the SSPADD f or the second

half of the address.

Status Bits as Data

Transfer is Received

SSPSR → SSPBUF Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

00 Yes Yes Yes

10 No No Yes

11 No No Yes

0 1 Yes No Yes

Note:Shaded cells show the conditions where the user software did not properly clear the overﬂow

condition.

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-20  1997 Microchip Technology Inc.

15.4.1.2 Reception

When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the

SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.

When the address byte o v erﬂo w condition exists, then no acknowledge (ACK) pulse is given. An

overﬂow condition is deﬁned as either the BF bit (SSPSTAT<0>) is set or the SSPOV bit

(SSPCON<6>) is set. So when a byte is received, with these conditions, and attempts to move

from the SSPSR register to the SSPBUF register, no acknowledge pulse is given.

An SSP interrupt is generated for each data transfer byte. The SSPIF ﬂag bit must be cleared in

software. The SSPSTAT register is used to determine the status of the receive byte.

Figure 15-8: I2C Waveforms for Reception (7-bit Address)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1SDA

SCL 123456789123456789123

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK Receiving Data

Receiving Data D0

D3D4

D6D7

ACK

R/W=0

Receiving Address

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

 1997 Microchip Technology Inc. DS31015A-page 15-21

Section 15. SSP

SSP

Figure 15-9: I2C Waveforms for Reception (10-bit Address)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

S1234 56 789 1 2345 67 89 1 2345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Bus Master

terminates

transfer

(PIR1<3>)

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated.

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF ﬂag

ACK

R/W = 1

Cleared in software

Dummy read of SSPBUF

to clear BF ﬂag Read of SSPBUF

clears BF ﬂag

Cleared by hardware when

SSPADD is updated.

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-22  1997 Microchip Technology Inc.

15.4.1.3 Transmission

When the R/W bit of the incoming address byte is set and an address match occurs , the R/W bit

of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The

ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be

loaded into the SSPBUF register , which also loads the SSPSR register . Then the SCL pin should

be enabled by setting the CKP bit (SSPCON<4>). The master m ust monitor the SCL pin prior to

asserting another clock pulse . The sla v e devices may be holding off the master by stretching the

clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that

the SDA signal is valid during the SCL high time (Figure 15-10).

An SSP interrupt is generated for each data transfer byte. The SSPIF ﬂag bit must be cleared in

software, and the SSPSTAT register is used to determine the status of the byte transfer. The

SSPIF ﬂag bit is set on the falling edge of the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of

the ninth SCL input pulse. If the SD A line was high (not ACK), then the data transfer is complete .

When the not A CK is latched by the sla v e, the sla v e logic is reset and the sla ve then monitors for

another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be

loaded into the SSPBUF register , which also loads the SSPSR register . Then the SCL pin should

be enabled by setting the CKP bit.

Figure 15-10: I2C Waveforms for Transmission (7-bit Address)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACKTransmitting DataR/W = 1Receiving Address

123456789 123456789 P

cleared in software

SSPBUF is written in software From SSP interrupt

service routine

Set bit after writing to SSPBUF

SData in

sampled SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written-to

before the CKP bit can be set)

R/W = 0

 1997 Microchip Technology Inc. DS31015A-page 15-23

Section 15. SSP

SSP

Figure 15-11: I2C Waveforms for Transmission (10-bit Address)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8

R/W=1

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Master sends NACK

(PIR1<3>)

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated.

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated.

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF ﬂag

Receive First Byte of Address

12345 789

D7 D6 D5 D4 D3 D1

ACK

Transmitting Data Byte

Dummy read of SSPBUF

to clear BF ﬂag

Cleared in software

Write of SSPBUF

initiates transmit

Cleared in software

Transmit is complete

CKP has to be set for clock to be released

Bus Master

terminates

transfer

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-24  1997 Microchip Technology Inc.

15.4.1.4 Clock Arbitration

Clock arbitr ation has the SCL pin to inhibit the master device from sending the next clock pulse.

The SSP module in I2C slave mode will hold the SCL pin low when the CPU needs to respond

to the SSP interrupt (SSPIF bit is set and the CKP bit is cleared). The data that needs to be trans-

mitted will need to be written to the SSPBUF register , and then the CKP bit will need to be set to

allow the master to generate the required clocks.

15.4.2 Master Mode (Firmware)

Master mode of operation is supported b y interrupt generation on the detection of the START and

STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP

module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is idle

with both the S and P bits clear.

In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRIS

bit(s). The output level is always low, irrespective of the value(s) in the PORT register. So when

transmitting data, a '1' data bit must have it’s TRIS bit set (input) and a '0' data bit must have it’s

TRIS bit cleared (output). The same scenario is true for the SCL line with the TRIS bit.

The following ev ents will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the sla v e mode idle (SSPM3:SSPM0 = 1011)

or with the slav e active (SSPM3:SSP0 = 1110 or 1111). When the slave modes are enab led, the

software needs to differentiate the source(s) of the interrupt.

15.4.3 Multi-Master Mode (Firmware)

In multi-Master mode, the interrupt generation on the detection of the START and STOP condi-

tions allows the determination of when the bus is free. The STOP (P) and START (S) bits are

cleared from a reset or when the SSP module is disabled. Control of the I2C bus may be taken

when the P bit (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear . When the

bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition

occurs.

In Multi-Master operation, the SDA line must be monitored to see if the signal level is the

e xpected output lev el. This check only needs to be done when a high lev el is output. If a high le vel

is expected and a low level is present, the device needs to release the SDA and SCL lines (set

the TRIS bits). There are two stages where this arbitration can be lost, they are:

• Address transfer

• Data transfer

When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the

address transfer stage, communication to the device may be in progress. If addressed an ACK

pulse will be generated. If arbitration was lost during the data transf er stage , the de vice will need

to retransfer the data at a later time.

 1997 Microchip Technology Inc. DS31015A-page 15-25

Section 15. SSP

SSP

15.4.4 Sleep Operation

While in sleep mode, the I2C module can receiv e addresses or data, and when an address match

or complete byte tr ansfer occurs w ake the processor from sleep (if the SSP interrupt is enab led).

15.4.5 Effect of a Reset

A reset disables the SSP module and terminates the current transfer.

Table 15-3: Registers Associated with I2C Operation

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on all

other resets

INTCON GIE PEIE T0IE INTE RBIE(2) T0IF INTF RBIF(2) 0000 000x 0000 000u

PIR SSPIF (1) 00

PIE SSPIE (1) 00

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.

Shaded cells are not used by SSP in I2C mode.

Note 1: The positions of these bits are device dependent.

2: These bits may also be named GPIE and GPIF.

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-26  1997 Microchip Technology Inc.

15.5 Initialization

Example 15-2: SPI Master Mode Initialization

CLRF STATUS ; Bank 0

CLRF SSPSTAT ; SMP = 0, CKE = 0, and clear status bits

BSF SSPSTAT, CKE ; CKE = 1

MOVLW 0x31 ; Set up SPI port, Master mode, CLK/16,

MOVWF SSPCON ; Data xmit on falling edge (CKE=1 & CKP=1)

; Data sampled in middle (SMP=0 & Master mode)

BSF STATUS, RP0 ; Bank 1

BSF PIE, SSPIE ; Enable SSP interrupt

BCF STATUS, RP0 ; Bank 0

BSF INTCON, GIE ; Enable, enabled interrupts

MOVLW DataByte ; Data to be Transmitted

; Could move data from RAM location

MOVWF SSPBUF ; Start Transmission

 1997 Microchip Technology Inc. DS31015A-page 15-27

Section 15. SSP

SSP

15.5.1 SSP Module / Basic SSP Module Compatibility

When upgrading from the Basic SSP module, the SSPSTAT register contains two additional

control bits. These bits are only used in SPI mode and are:

• SMP, SPI data input sample phase

• CKE, SPI Clock Edge Select

To be compatible with the SPI of the Basic SSP module, these bits m ust be appropriately conﬁg-

ured. If these bits are not at the states shown in Table 15-4, improper SPI communication may

occur.

Table 15-4: New Bit States for Compatibility

Basic SSP Module SSP Module

CKP CKP CKE SMP

1 100

0 000

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-28  1997 Microchip Technology Inc.

15.6 Design Tips

Question 1:

Using SPI mode, I do not seem able to talk to an SPI device.

Answer 1:

Ensure that you are using the correct SPI mode for that device. This SPI suppor ts all four SPI

modes so you should be able to get it to function. Check the clock polarity and the clock phase.

Question 2:

Using I

C mode, I do not seem able to make the master mode work.

Answer 2:

This SSP module does not hav e master mode fully automated in hardware , see Application Note

AN578 f or software which uses the SSP module to implement master mode. If you require a fully

automated hardware implementation of I2C Master Mode, please refer to the Microchip Line Card

for devices that have the Master SSP module.

Question 3:

Using I

C mode, I write data to the SSPBUF register, but the data did not

transmit.

Answer 3:

Ensure that you set the CKP bit to release the I2C clock.

Note: At the time of printing only the High-end family of devices (PIC17CXXX) have

devices with the Master SSP module implemented.

 1997 Microchip Technology Inc. DS31015A-page 15-29

Section 15. SSP

SSP

15.7 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-

tion notes ma y not be written speciﬁcally for the Mid-Range MCU f amily (that is they ma y be writ-

ten for the Base-Line, or High-End families), but the concepts are per tinent, and could be used

(with modiﬁcation and possible limitations). The current application notes related to the SSP

Module are:

Title Application Note #

Use of the SSP Module in the I 2C Multi-Master Environment. AN578

Using Microchip 93 Series Serial EEPROMs with Microcontroller SPI Ports AN613

Software Implementation of I2C Bus Master AN554

Use of the SSP module in the Multi-master Environment AN578

Interfacing PIC16C64/74 to Microchip SPI Serial EEPROM AN647

Interfacing a Microchip PIC16C92x to Microchip SPI Serial EEPROM AN668

PICmicro MID-RANGE MCU FAMILY

DS31015A-page 15-30  1997 Microchip Technology Inc.

15.8 Revision History

Revision A

This is the initial released revision of the SSP module description.

 1997 Microchip Technology Inc. DS31016A page 16-1

BSSP

Section 16. Basic Sychronous Serial Port (BSSP)

HIGHLIGHTS

This section of the manual contains the following major topics:

16.1 Introduction..................................................................................................................16-2

16.2 Control Registers .........................................................................................................16-3

16.3 SPI™ Mode..................................................................................................................16-6

16.4 SSP I2C Operation.....................................................................................................16-15

16.5 Initialization................................................................................................................16-23

16.6 Design Tips ................................................................................................................16-24

16.7 Related Application Notes..........................................................................................16-25

16.8 Revision History.........................................................................................................16-26

Note: Please refer to Appendix C.2 or the device data sheet to determine which devices

use this module.

SPI is a trademark of Motorola Corporation.

I2C is a trademark of Philips Corporation.

PICmicro MID-RANGE MCU FAMILY

DS31016A-page 16-2  1997 Microchip Technology Inc.

16.1 Introduction

The Basic Synchronous Serial P ort (BSSP) module is a serial interface useful f or communicating

with other peripheral or microcontroller devices. These peripheral devices may be Serial

EEPROMs, shift registers, display dr ivers, A/D conver ters, etc. The BSSP module can operate

in one of two modes:

• Serial Peripheral Interface (SPI™)

• Inter-Integrated Circuit (I2C™)

- Slave mode

- I/O slope control, Start and Stop bits to ease software implementation of Master and

Multi-master modes

I2C is a trademark of Philips Corporation.

 1997 Microchip Technology Inc. DS31016A-page 16-3

Section 16. BSSP

BSSP

16.2 Control Registers

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — D/A P S R/W UA BF

bit 7 bit 0

bit 7:6 Unimplemented: Read as '0'

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit

(I2C mode only. This bit is cleared when the SSP module is disabled)

1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)

0 = Stop bit was not detected last

bit 3 S: Start bit

(I2C mode only. This bit is cleared when the SSP module is disabled)

1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)

0 = Start bit was not detected last

bit 2 R/W: Read/Write bit information (I2C mode only)

This bit holds the R/W bit inf ormation f ollowing the last address match. This bit is only valid from

the address match to the next start bit, stop bit, or not ACK bit.

1 = Read

0 = Write

bit 1 UA: Update Address (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2C modes)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit (I2C mode only)

1 = Transmit in progress, SSPBUF is full

0 = Transmit complete, SSPBUF is empty

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

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DS31016A-page 16-4  1997 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overﬂow Indicator bit

In SPI mode:

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case

of overﬂow, the data in SSPSR is lost. Overﬂow can only occur in slave mode. The user

must read the SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master

mode the overﬂow bit is not set since each new reception (and tr ansmission) is initiated by

writing to the SSPBUF register.

0 = No overﬂow

In I2C mode:

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a

“don‘t care” in transmit mode. SSPOV must be cleared in software in either mode.

0 = No overﬂow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly conﬁgured as input or output.

In SPI mode:

1 = Enables serial port and conﬁgures SCK, SDO, SDI, and SS as the source of the

serial port pins

0 = Disables serial port and conﬁgures these pins as I/O port pins

In I2C mode:

1 = Enables the serial port and conﬁgures the SDA and SCL pins as the source of the

serial port pins

0 = Disables serial port and conﬁgures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2C mode:

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch) (Used to ensure data setup time)

 1997 Microchip Technology Inc. DS31016A-page 16-5

Section 16. BSSP

BSSP

bit 3:0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = FOSC/4

0001 = SPI master mode, clock = FOSC/16

0010 = SPI master mode, clock = FOSC/64

0011 = SPI master mode, clock = TMR2 output/2

0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin

0110 = I2C slave mode, 7-bit address

0111 = I2C slave mode, 10-bit address

1000 = Reserved

1001 = Reserved

1010 = Reserved

1011 = I2C Firmware controlled Master mode (slave idle)

1100 = Reserved

1101 = Reserved

1110 = I2C Firmware controlled Multi-Master mode,

7-bit address with start and stop bit interrupts enabled

1111 = I2C Firmware controlled Master mode,

10-bit address with start and stop bit interrupts enabled

Legend

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’ - n = Value at POR reset

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DS31016A-page 16-6  1997 Microchip Technology Inc.

16.3 SPI™ Mode

The SPI mode allows 8-bits of data to be synchronously transmitted and received simulta-

neously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally a fourth pin may be used when in a slave mode of operation:

• Slave Select (SS)

16.3.1 Operation

When initializing the SPI, se veral options need to be speciﬁed. This is done by programming the

appropriate control bits in the SSPCON register (SSPCON<5:0>). These control bits allow the

following to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Output/Input data on the Rising/Falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

Figure 16-1 shows the block diagram of the SSP module, when in SPI mode.

Figure 16-1: SSP Block Diagram (SPI Mode)

Read Write

Internal

data bus

SDI

SDO

SCK

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0 shift clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TCY

Prescaler

4, 16, 64

TRIS bit of SCK pin

Edge

Select

SPI is a trademark of Motorola Corporations.

 1997 Microchip Technology Inc. DS31016A-page 16-7

Section 16. BSSP

BSSP

The SSP consists of a transmit/receiv e Shift Register (SSPSR) and a Buff er register (SSPB UF).

The SSPSR shifts the data in and out of the de vice, MSB ﬁrst. The SSPBUF holds the data that

was previously written to the SSPSR, until the received data is ready. Once the 8-bits of data

hav e been received, that inf ormation is moved to the SSPB UF register . Then the b uffer full detect

bit, BF (SSPSTAT <0>), and interrupt ﬂag bit, SSPIF, are set. This double b uffering of the received

data (SSPBUF) allows the ne xt b yte to start reception bef ore reading the data that was receiv ed.

Any write to the SSPBUF register during transmission/reception of data will be ignored, and the

write collision detect bit, WCOL (SSPCON<7>), will be set. User software m ust clear the WCOL

bit so that it can be determined if the following write(s) to the SSPBUF register completed suc-

cessfully. When the application software is expecting to receive valid data, the SSPBUF should

be read bef ore the ne xt b yte of data to transf er is written to the SSPBUF. Buffer full bit, BF (SSP-

STAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is

complete). When the SSPBUF is read, the BF bit is cleared. This data ma y be irrelev ant if the SPI

is only a transmitter. Generally the SSP Interrupt is used to determine when the transmis-

sion/reception has completed. The SSPBUF can then be read (if data is meaningful) and/or the

SSPBUF (SSPSR) can be written. If the interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does not occur . Example 16-1 shows the load-

ing of the SSPBUF (SSPSR) f or data tr ansmission. The shaded instruction is only required if the

received data is meaningful (some SPI applications are transmit only).

Example 16-1: Loading the SSPBUF (SSPSR) Register

The SSPSR is not directly readable or writable, and can only be accessed from addressing the

SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status

conditions.

BCF STATUS, RP1 ;Specify Bank1

BSF STATUS, RP0 ;

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

GOTO LOOP ;No

BCF STATUS, RP0 ;Specify Bank0

MOVF SSPBUF, W ;W reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

PICmicro MID-RANGE MCU FAMILY

DS31016A-page 16-8  1997 Microchip Technology Inc.

16.3.2 Enabling SPI I/O

To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>), must be set. To reset or recon-

ﬁgure SPI mode, clear the SSPEN bit which re-initializ es the SSPCON register, and then set the

SSPEN bit. This conﬁgures the SDI, SDO, SCK, and SS pins as ser ial port pins. For the pins to

behave as the serial port function, they must have their data direction bits (in the TRIS register)

appropriately programmed. That is:

• SDI must have the TRIS bit set

• SDO must have the TRIS bit cleared

• SCK (Master mode) must have the TRIS bit cleared

• SCK (Slave mode) must have the TRIS bit set

•SS

must have the TRIS bit set

Any serial port function that is not desired ma y be ov erridden by programming the corresponding

data direction (TRIS) register to the opposite value . An example would be in master mode where

you are only sending data (to a display driver), then both SDI and SS could be used as general

purpose outputs by clearing their corresponding TRIS register bits.

 1997 Microchip Technology Inc. DS31016A-page 16-9

Section 16. BSSP

BSSP

16.3.3 Typical Connection

Figure 16-2 shows a typical connection between two microcontrollers. The master controller

(Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both

shift registers on their programmed clock edge, and latched on the opposite edge of the clock.

Both processors should be programmed to same Clock Polarity (CKP), then both controllers

would send and receiv e data at the same time . Whether the data is meaningful (or dummy data)

depends on the application software. This leads to three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

Figure 16-2: SPI Master/Slave Connection

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master (SSPM3:SSPM0 = 00xxb)

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave (SSPM3:SSPM0 = 010xb)

Serial Clock

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DS31016A-page 16-10  1997 Microchip Technology Inc.

16.3.4 Master Operation

The master can initiate the data transfer at any time because it controls the SCK. The master

determines when the slave (Processor 2) wishes to broadcast data by the software protocol.

In master mode the data is transmitted/receiv ed as soon as the SSPBUF register is written to. If

the SPI is only going to receive, the SDO output could be disabled (programmed as an input).

The SSPSR register will continue to shift in the signal present on the SDI pin at the progr ammed

clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal

received b yte (interrupts and status bits appropriately set). This could be useful in receiver appli-

cations as a “line activity monitor” mode.

The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This

then would give waveforms for SPI communication as shown in Figure 16-5 and Figure 16-5

where the MSb is transmitted ﬁrst. In master mode, the SPI clock r ate (bit rate) is user program-

mable to be one of the following:

•F

OSC/4 (or TCY)

•F

OSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate of 5 Mbps (at 20 MHz).

Figure 16-3: SPI Mode Waveform (Master Mode)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SSPIF

Interrupt ﬂag

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

 1997 Microchip Technology Inc. DS31016A-page 16-11

Section 16. BSSP

BSSP

16.3.5 Slave Operation

In slav e mode , the data is transmitted and receiv ed as the e xternal clock pulses appear on SCK.

When the last bit is latched the SSPIF interrupt ﬂag bit is set.

The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This

then would give waveforms for SPI communication as shown in Figure 16-5 and Figure 16-5

where the MSb is transmitted ﬁrst. When in slave mode the exter nal clock must meet the mini-

mum high and low times.

In sleep mode, the slave can transmit and receive data and wake the device from sleep if the

interrupt is enabled.

Figure 16-4: SPI Mode Waveform (Slave Mode w/o SS Control)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SSPIF

Interrupt ﬂag

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

Next Q4 Cycle

after Q2 ↓

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DS31016A-page 16-12  1997 Microchip Technology Inc.

16.3.6 Slave Select Mode

The SS pin allows a synchronous slave mode. The SPI must be in slave mode

(SSPCON<3:0> = 04h) and the TRIS bit must be set the for the synchronous slave mode to be

enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is

driven. When the SS pin goes high, the SDO pin is no longer dr iven, even if in the middle of a

transmitted byte, and becomes a ﬂoating output. If the SS pin is taken low without resetting SPI

mode, the transmission will continue from the point at which it was taken high. To clear the bit

counter the Basic SSP module must be disab led and then re-enabled. External pull-up/pull-down

resistors may be desirable, depending on the application.

To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the

SPI needs to operate as a receiver the SDO pin can be conﬁgured as an input. This disables

transmissions from the SDO . The SDI can alwa ys be left as an input (SDI function) since it cannot

create a bus conﬂict.

Figure 16-5: SPI Mode Waveform (Slave Mode with ss Control)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SSPIF

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

Next Q4 Cycle

after Q2 ↓

 1997 Microchip Technology Inc. DS31016A-page 16-13

Section 16. BSSP

BSSP

Figure 16-6: Slave Synchronization Waveform

SCK

(CKP = 1)

SCK

(CKP = 0)

Input

Sample

SDI

SDO bit7 bit6 bit5

SSPIF

Interrupt

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit0

bit5 bit0

bit7

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DS31016A-page 16-14  1997 Microchip Technology Inc.

16.3.7 Sleep Operation

In master mode all module clocks are halted, and the transmission/reception will remain in that

state until the de vice wak es from sleep. After the device returns to normal mode, the module will

continue to transmit/receive data.

In slav e mode, the SPI transmit/receiv e shift register operates asynchronously to the de vice. This

allows the de vice to be placed in sleep mode, and data to be shifted into the SPI transmit/receiv e

shift register. When all 8-bits have been received, the SSP interrupt ﬂag bit will be set and if

enabled will wake the device from sleep.

16.3.8 Effects of a Reset

A reset disables the SSP module and terminates the current transfer.

Table 16-1: Registers Associated with SPI Operation

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

resets

INTCON GIE PEIE T0IE INTE RBIE(2) T0IF INTF RBIF(2) 0000 000x 0000 000u

PIR SSPIF (1) 00

PIE SSPIE (1) 00

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.

Shaded cells are not used by the SSP in SPI mode.

Note 1: The position of this bit is device dependent.

2: These bits can also be named GPIE and GPIF.

 1997 Microchip Technology Inc. DS31016A-page 16-15

Section 16. BSSP

BSSP

16.4 SSP I2C Operation

The SSP module in I2C mode fully implements all sla ve functions, except General Call Support,

and provides interrupts on start and stop bits in hardware to facilitate software implementations

of the master functions. The SSP module implements the standard and fast mode speciﬁcations

as well as 7-bit and 10-bit addressing. Appendix A giv es an overview of the I2C bus speciﬁcation.

Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SD A pin,

which is the data. The user must conﬁgure these pins as inputs through the TRIS bits. The SSP

module functions are enabled by setting SSP Enable bit, SSPEN (SSPCON<5>).

A “glitch” ﬁlter is on the SCL and SDA pins when the pin is an input. This ﬁlter operates in both

the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there

is a slew rate control of the pin that is independent of device frequency.

Figure 16-7: SSP Block Diagram (I2C Mode)

Read Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

SCL

shift

clock

MSb LSb

SDA

PICmicro MID-RANGE MCU FAMILY

DS31016A-page 16-16  1997 Microchip Technology Inc.

The SSP module has ﬁve registers for I2C operation. They are:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly accessible

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I2C operation. Four mode selection bits

(SSPCON<3:0>) allow one of the following I2C modes to be selected:

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Firmware controlled Multi-Master mode, 7-bit address (start and stop bit interrupts

enabled)

•I

2C Firmware controlled Multi-Master mode, 10-bit address (start and stop bit interrupts

enabled)

•I

2C Firmware controlled Master mode, slave is idle

Bef ore selecting any I2C mode, the SCL and SD A pins must be prog rammed to inputs b y setting

the appropriate TRIS bits. Selecting an I2C mode, by setting the SSPEN bit, enables the SCL

and SDA pins to be used as the clock and data lines in I2C mode.

The SSPSTAT register gives the status of the data transfer. This infor mation includes detection

of a START or STOP bit, speciﬁes if the received byte w as data or address, if the next byte is the

completion of 10-bit address, and if this will be a read or write data transfer. The SSPSTAT reg-

ister is read only.

The SSPBUF is the register to which transf er data is written to or read from. The SSPSR register

shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a

doubled buffered receiver. This allows reception of the next byte to begin before reading the last

byte of received data. When the complete byte is received, it is transferred to the SSPBUF reg-

ister and the SSPIF ﬂag bit is set. If another complete byte is received before the SSPBUF reg-

ister is read, a receiver overﬂow has occurred and bit SSPOV (SSPCON<6>) is set.

The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high

byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of

the address needs to be loaded (A7:A0).

 1997 Microchip Technology Inc. DS31016A-page 16-17

Section 16. BSSP

BSSP

16.4.1 Slave Mode

In slave mode, the SCL and SDA pins must be conﬁgured as inputs (TRIS bits set). The SSP

module will override the input state with the output data when required (slave-transmitter).

When an address is matched or the data transfer after an address match is received, the hard-

ware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF reg-

ister with the received value currently in the SSPSR register.

There are cer tain conditions that will cause the SSP module not to give this ACK pulse. These

are if either (or both):

a) The buffer full bit, BF (SSPSTAT<0>), was set before the transfer was received.

b) The overﬂow bit, SSPOV (SSPCON<6>), was set before the transfer was received.

In this case, the SSPSR register v alue is not loaded into the SSPBUF, but bit SSPIF and SSPO V

bits are set. Table 16-2 sho ws what happens when a data transf er byte is receiv ed, given the sta-

tus of the BF and SSPOV bits. The shaded cells show the condition where user softw are did not

properly clear the overﬂow condition. The BF ﬂag bit is cleared by reading the SSPBUF register

while the SSPOV bit is cleared through software.

The SCL clock input m ust ha ve a minimum high and low time for proper operation. The high and

low times of the I2C speciﬁcation as well as the requirement of the SSP module are given in

parameter 100 and parameter 101 of the “Electrical Speciﬁcations” section.

PICmicro MID-RANGE MCU FAMILY

DS31016A-page 16-18  1997 Microchip Technology Inc.

16.4.1.1 Addressing

Once the SSP module has been enabled, it waits for a START condition to occur. Following the

START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled

with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to

the value of the SSPADD register . The address is compared on the falling edge of the eighth clock

(SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the f ollo wing events

occur:

a) The SSPSR register value is loaded into the SSPBUF register on the falling edge of the

eight SCL pulse.

b) The buffer full bit, BF, is set on the falling edge of the eight SCL pulse.

c) An ACK pulse is generated.

d) SSP interrupt ﬂag bit, SSPIF, is set (interrupt is generated if enabled) - on the f alling edge

of the ninth SCL pulse.

In 10-bit address mode, two address bytes need to be received by the slave. The ﬁve Most

Signiﬁcant bits (MSbs) of the ﬁrst address byte specify if this is a 10-bit address. The R/W bit

(SSPSTAT<2>) must specify a wr ite, so the slave device will receive the second address byte.

F or a 10-bit address the ﬁrst byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two

MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9

for slave-transmitter:

1. Receive ﬁrst (high) byte of Address (the SSPIF, BF, and UA (SSPSTAT<1>) bits are set).

2. Update the SSPADD register with second (low) byte of Address (clears the UA bit and

releases the SCL line).

3. Read the SSPBUF register (clears the BF bit) and clear the SSPIF ﬂag bit.

4. Receive second (low) byte of Address (the SSPIF, BF, and UA bits are set).

5. Update the SSPADD register with the ﬁrst (high) byte of Address. This will clear the UA bit

and release the SCL line.

6. Read the SSPBUF register (clears the BF bit) and clear the SSPIF ﬂag bit.

7. Receive repeated START condition.

8. Receive ﬁrst (high) byte of Address (the SSPIF and BF bits are set).

9. Read the SSPBUF register (clears the BF bit) and clear the SSPIF ﬂag bit.

Table 16-2: Data Transfer Received Byte Actions

Note: Following the RESTART condition (step 7) in 10-bit mode, the user only needs to

match the ﬁrst 7-bit address. The user does not update the SSPADD f or the second

half of the address.

Status bits as data

transfer is received

SSPSR → SSPBUF Generate ACK

pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

00 Yes Yes Yes

10 No No Yes

11 No No Yes

0 1 Yes No Yes

Note:Shaded cells show the conditions where the user software did not properly clear the overﬂow con-

dition

 1997 Microchip Technology Inc. DS31016A-page 16-19

Section 16. BSSP

BSSP

16.4.1.2 Reception

When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the

SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.

When the address byte o v erﬂo w condition exists, then no acknowledge (ACK) pulse is given. An

overﬂow condition is deﬁned as either the BF bit (SSPSTAT<0>) is set or the SSPOV bit

(SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer byte. The SSPIF ﬂag bit must be cleared in

software, and the SSPSTAT register is used to determine the status of the byte.

Figure 16-8: I2C Waveforms for Reception (7-bit Address)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1SDA

SCL 123456789123456789123

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK Receiving Data

Receiving Data D0

D3D4

D6D7

ACK

R/W=0

Receiving Address

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

PICmicro MID-RANGE MCU FAMILY

DS31016A-page 16-20  1997 Microchip Technology Inc.

16.4.1.3 Transmission

When the R/W bit of the incoming address byte is set and an address match occurs , the R/W bit

of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The

ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be

loaded into the SSPBUF register , which also loads the SSPSR register . Then the SCL pin should

be enabled by setting the CKP bit (SSPCON<4>). The master m ust monitor the SCL pin prior to

asserting another clock pulse . The sla v e devices may be holding off the master by stretching the

clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that

the SDA signal is valid during the SCL high time (Figure 16-9).