15 MHz Rail-to-Rail
Operational Amplifiers
Data Sheet
OP162/OP262/OP462
Rev. G
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Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
FEATURES
Wide bandwidth: 15 MHz
Low offset voltage: 325 µV max
Low noise: 9.5 nV/√Hz @ 1 kHz
Single-supply operation: 2.7 V to 12 V
Rail-to-rail output swing
Low TCVOS: 1 µV/°C typ
High slew rate: 13 V/µs
No phase inversion
Unity-gain stable
APPLICATIONS
Portable instrumentation
Sampling ADC amplifier
Wireless LANs
Direct access arrangement
Office automation
GENERAL DESCRIPTION
The OP162 (single), OP262 (dual), and OP462 (quad) rail-to-
rail 15 MHz amplifiers feature the extra speed new designs
require, with the benefits of precision and low power operation.
With their incredibly low offset voltage of 45 µV (typical) and
low noise, they are perfectly suited for precision filter applica-
tions and instrumentation. The low supply current of 500 µA
(typical) is critical for portable or densely packed designs. In
addition, the rail-to-rail output swing provides greater dynamic
range and control than standard video amplifiers.
These products operate from single supplies as low as 2.7 V to
dual supplies of ±6 V. The fast settling times and wide output
swings recommend them for buffers to sampling A/D converters.
The output drive of 30 mA (sink and source) is needed for
many audio and display applications; more output current can
be supplied for limited durations. The OPx62 family is specified
over the extended industrial temperature range (–40°C to
+125°C). The single OP162 amplifiers are available in 8-lead
SOIC package. The dual OP262 amplifiers are available in
8-lead SOIC and TSSOP packages. The quad OP462 amplifiers
are available in 14-lead, narrow-body SOIC and TSSOP
packages.
PIN CONFIGURATIONS
Figure 1. 8-Lead Narrow-Body SOIC (S Suffix)
Figure 2. 8-Lead Narrow-Body SOIC (S Suffix)
Figure 3. 8-Lead TSSOP (RU Suffix)
Figure 4. 14-Lead Narrow-Body SOIC (S Suffix)
Figure 5. 14-Lead TSSOP (RU Suffix)
NULL 1
–IN A 2
+IN A 3
V– 4
NULL
8
V+
7
OUT A
6
NC
5
NC = NO CONNECT
OP162
TOP VIEW
(Not to Scale)
00288-001
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
OP262
TOP VIEW
(Not to Scale)
00288-003
TOP VIEW
(Not to Scale)
1
2
3
4
OP262
–IN A
+IN A
V–
OUT A
8
7
6
5
OUT B
–IN B
+IN B
V+
00288-004
OUT A
1
–IN A
2
+IN A
3
V+
4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B
5
+IN C
10
–IN B
6
–IN C
9
OUT B
7
OUT C
8
OP462
TOP VIEW
(Not to Scale)
00288-005
1
2
3
4
5
6
7
OP462
–IN A
+IN A
V+
OUT B
–IN B
+IN B
OUT A
14
13
12
11
10
9
8
–IN D
+IN D
V–
OUT C
–IN C
+IN C
OUT D
TOP VIEW
(Not to Scale)
00288-006
OP162/OP262/OP462 Data Sheet
Rev. G | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
Applications ..................................................................................... 12
Functional Description .............................................................. 12
Offset Adjustment ...................................................................... 12
Rail-to-Rail Output .................................................................... 12
Output Short-Circuit Protection .............................................. 12
Input Overvoltage Protection ................................................... 13
Output Phase Reversal ............................................................... 13
Power Dissipation....................................................................... 13
Unused Amplifiers ..................................................................... 14
Power-On Settling Time ............................................................ 14
Capacitive Load Drive ............................................................... 14
Total Harmonic Distortion and Crosstalk .............................. 15
PCB Layout Considerations ...................................................... 15
Applications Circuits ...................................................................... 16
Single-Supply Stereo Headphone Driver................................. 16
Instrumentation Amplifier........................................................ 16
Direct Access Arrangement ...................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 20
REVISION HISTORY
5/12—Rev. F to Rev. G
Deleted MSOP Throughout ............................................................ 1
Deleted Figure 2; Renumbered Sequentially................................. 1
Deleted Spice-Macro Model Section ............................................ 18
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 20
1/05—Rev. E to Rev. F
Changes to Absolute Maximum Ratings Table 4 and Table 5 .... 6
Change to Figure 36 ....................................................................... 13
Changes to Ordering Guide .......................................................... 20
12/04—Rev. D to Rev. E
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 3
Changes to Package Type................................................................. 6
Change to Figure 16 ......................................................................... 8
Change to Figure 22 ......................................................................... 9
Change to Figure 36 ....................................................................... 13
Change to Figure 37 ....................................................................... 14
Changes to Ordering Guide .......................................................... 20
10/02—Rev. C to Rev. D
Deleted 8-Lead Plastic DIP (N-8) .................................... Universal
Deleted 14-Lead Plastic DIP (N-14) ................................ Universal
Edits to ORDERING GUIDE........................................................ 19
Edits to Figure 30 ............................................................................ 19
Edits to Figure 31 ............................................................................ 19
Updated Outline Dimensions ....................................................... 19
Data Sheet OP162/OP262/OP462
Rev. G | Page 3 of 20
SPECIFICATIONS
@ VS = 5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS OP162G, OP262G, OP462G 45 325 µV
–40°C ≤ TA ≤ +125°C 800 µV
H grade, –40°C ≤ TA ≤ +125°C 1 mV
D grade 0.8 3 mV
–40°C ≤ TA ≤ +125°C 5 mV
Input Bias Current
I
B
360
600
nA
–40°C ≤ TA ≤ +125°C 650 nA
Input Offset Current IOS ±2.5 ±25 nA
–40°C ≤ TA ≤ +125°C ±40 nA
Input Voltage Range VCM 0 4 V
Common-Mode Rejection CMRR 0 V ≤ VCM ≤ 4.0 V, –40°C ≤ TA ≤ +125°C 70 110 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, 0.5 ≤ VOUT ≤ 4.5 V 30 V/mV
RL = 10 kΩ, 0.5 ≤ VOUT ≤ 4.5 V 65 88 V/mV
RL = 10 kΩ, –40°C ≤ TA ≤ +125°C 40 V/mV
Long-Term Offset Voltage1 VOS G grade 600 µV
Offset Voltage Drift2 ∆VOS/∆T 1 µV/°C
Bias Current Drift
∆
IB/
∆
T 250 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing High VOH IL = 250 µA, –40°C ≤ TA ≤ +125°C 4.95 4.99 V
IL = 5 mA 4.85 4.94 V
Output Voltage Swing Low VOL IL = 250 µA, –40°C ≤TA ≤ +125°C 14 50 mV
IL = 5 mA 65 150 mV
Short-Circuit Current ISC Short to ground ±80 mA
Maximum Output Current IOUT ±30 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 7 V 120 dB
–40°C ≤ TA ≤ +125°C 90 dB
Supply Current/Amplifier ISY OP162, VOUT = 2.5 V 600 750 µA
–40°C ≤ TA ≤ +125°C 1 mA
OP262, OP462, VOUT = 2.5 V 500 700 µA
–40°C ≤ TA ≤ +125°C 850 µA
DYNAMIC PERFORMANCE
Slew Rate SR 1 V < VOUT < 4 V, RL = 10 kΩ 10 V/µs
Settling Time tS To 0.1%, AV = –1, VO = 2 V step 540 ns
Gain Bandwidth Product GBP 15 MHz
Phase Margin φm 61 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.5 µV p-p
Voltage Noise Density
e
n
f = 1 kHz
9.5
nV/√Hz
Current Noise Density in f = 1 kHz 0.4 pA/√Hz
1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
2 Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.
OP162/OP262/OP462 Data Sheet
Rev. G | Page 4 of 20
@ VS = 3.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS OP162G, OP262G, OP462G 50 325 µV
G, H grades, –40°C ≤ TA ≤ +125°C 1 mV
D grade
0.8
3
mV
–40°C ≤ TA ≤ +125°C 5 mV
Input Bias Current IB 360 600 nA
Input Offset Current IOS ±2.5 ±25 nA
Input Voltage Range VCM 0 2 V
Common-Mode Rejection
CMRR
0 V ≤ V
CM
≤ 2.0 V, –40°C ≤ T
A
≤ +125°C
70
110
dB
Large Signal Voltage Gain AVO RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V 20 V/mV
RL = 10 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V 20 30 V/mV
Long-Term Offset Voltage1 VOS G grade 600 µV
OUTPUT CHARACTERISTICS
Output Voltage Swing High VOH IL = 250 µA 2.95 2.99 V
IL= 5 mA 2.85 2.93 V
Output Voltage Swing Low VOL IL = 250 µA 14 50 mV
IL= 5 mA 66 150 mV
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 7 V,
–40°C ≤ TA ≤ +125°C 60 110 dB
Supply Current/Amplifier ISY OP162, VOUT = 1.5 V 600 700 µA
–40°C ≤ TA ≤ +125°C 1 mA
OP262, OP462, VOUT = 1.5 V 500 650 µA
–40°C ≤ TA ≤ +125°C 850 µA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 10 V/µs
Settling Time tS To 0.1%, AV = –1, VO = 2 V step 575 ns
Gain Bandwidth Product GBP 15 MHz
Phase Margin
φ
m
59
Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.5 µV p-p
Voltage Noise Density en f = 1 kHz 9.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.4 pA/√Hz
1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
Data Sheet OP162/OP262/OP462
Rev. G | Page 5 of 20
@ VS = ±5.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 3. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS OP162G, OP262G, OP462G 25 325 µV
−40°C ≤ TA ≤ +125°C 800 µV
H grade, –40°C ≤ TA ≤ +125°C 1 mV
D grade 0.8 3 mV
−40°C ≤ TA ≤ +125°C 5 mV
Input Bias Current IB 260 500 nA
−40°C ≤ TA ≤ +125°C 650 nA
Input Offset Current IOS ±2.5 ±25 nA
−40°C ≤ TA ≤ +125°C ±40 nA
Input Voltage Range VCM –5 +4 V
Common-Mode Rejection CMRR −4.9 V ≤ VCM ≤ +4.0 V, –40°C ≤ TA ≤ +125°C 70 110 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, –4.5 V ≤ VOUT ≤ +4.5 V 35 V/mV
RL = 10 kΩ, –4.5 V ≤ VOUT ≤ +4.5 V 75 120 V/mV
−40°C ≤ TA ≤ +125°C 25 V/mV
Long-Term Offset Voltage1 VOS G grade 600 µV
Offset Voltage Drift2
∆
VOS/
∆
T 1 µV/°C
Bias Current Drift
∆
IB/
∆
T 250 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing High VOH IL = 250 µA, –40°C ≤ TA ≤ +125°C 4.95 4.99 V
IL= 5 mA 4.85 4.94 V
Output Voltage Swing Low VOL IL = 250 µA, –40°C ≤ TA ≤ +125°C –4.99 –4.95 V
IL= 5 mA –4.94 –4.85 V
Short-Circuit Current ISC Short to ground ±80 mA
Maximum Output Current IOUT ±30 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±1.35 V to ±6 V,
−
40°C ≤ TA ≤ +125°C
60
110
dB
Supply Current/Amplifier ISY OP162, VOUT = 0 V 650 800 µA
−40°C ≤ TA ≤ +125°C 1.15 mA
OP262, OP462, VOUT = 0 V 550 775 µA
−40°C ≤ TA ≤ +125°C 1 mA
Supply Voltage Range VS 3.0 (±1.5) 12 (±6) V
DYNAMIC PERFORMANCE
Slew Rate SR −4 V < VOUT < 4 V, RL = 10 kΩ 13 V/µs
Settling Time tS To 0.1%, AV = –1, VO = 2 V step 475 ns
Gain Bandwidth Product GBP 15 MHz
Phase Margin φm 64 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.5 µV p-p
Voltage Noise Density en f = 1 kHz 9.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.4 pA/√Hz
1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125°C, with an LTPD of 1.3.
2 Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.
OP162/OP262/OP462 Data Sheet
Rev. G | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Min
Supply Voltage ±6 V
Input Voltage1 ±6 V
Differential Input Voltage2 ±0.6 V
Internal Power Dissipation
SOIC (S) Observe Derating Curves
TSSOP (RU) Observe Derating Curves
Output Short-Circuit Duration Observe Derating Curves
Storage Temperature Range –65°C to +150°C
Operating Temperature Range –40°C to +125°C
Junction Temperature Range –65°C to +150°C
Lead Temperature Range
(Soldering, 10 sec) 300°C
1 For supply voltages greater than 6 V, the input voltage is limited to less than
or equal to the supply voltage.
2 For differential input voltages greater than 0.6 V, the input current should be
limited to less than 5 mA to prevent degradation or destruction of the input
devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Package Type θJA1 θJC Unit
8-Lead SOIC (S) 157 56 °C/W
8-Lead TSSOP (RU) 208 °C/W
14-Lead SOIC (S) 105 °C/W
14-Lead TSSOP (RU) 148 °C/W
1 θJA is specified for the worst-case conditions, that is, θJA is specified for a
device soldered in circuit board for SOIC, and TSSOP packages.
ESD CAUTION
Data Sheet OP162/OP262/OP462
Rev. G | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. OP462 Input Offset Voltage Distribution
Figure 7. OP462 Input Offset Voltage Drift (TCVOS)
Figure 8. OP462 Input Bias Current vs. Common-Mode Voltage
Figure 9. OP462 Input Offset Voltage vs. Temperature
Figure 10. OP462 Input Bias Current vs. Temperature
Figure 11. OP462 Input Offset Current vs. Temperature
V
S
= 5V
T
A
= 25°C
COUNT =
720 OP AMPS
INPUT OFFSET VOLTAGE (µV)
QUANTITY (Amplifiers)
250
200
150
50
100
0
–200 –140 –80 –20 10040 160
00288-007
V
S
= 5V
T
A
= 25°C
COUNT =
360 OP AMPS
INPUT OFFSET DRIFT, TCV
OS
(µV,°C)
QUANTITY (Amplifiers)
100
80
60
20
40
00.2 0.3 0.5 0.7 0.9 1.31.1 1.5
00288-008
COMMON-MODE VOLTAGE (V)
INPUT CURRENT (nA)
420
340
260
180
100 0 0.5 1.0 1.5 2.0 3.02.5 3.5 4.0
00288-009
V
S
= 5V
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
125
100
75
50
25
0
–75 –50 –25 0 25 50 10075 125 150
00288-010
V
S
= 5V
TEMPERATURE (°C)
INPUT BIAS CURRENT (nA)
0
–100
–200
–300
–400
–500
–50 –25 0 25 50 10075 125 150
00288−011
V
S
= 5V
TEMPERATURE (°C)
INPUT OFFSET CURRENT (nA)
15
10
5
0
–75 –50 –25 0 25 50 10075 125 150
00288−012
V
S
= 5V
OP162/OP262/OP462 Data Sheet
Rev. G | Page 8 of 20
Figure 12. OP462 Output High Voltage vs. Temperature
Figure 13. OP462 Output Low Voltage vs. Temperature
Figure 14. OP462 Open-Loop Gain vs. Temperature
Figure 15. Output Low Voltage to Supply Rail vs. Load Current
Figure 16. Supply Current/Amplifier vs. Temperature
Figure 17. OP462 Supply Current/Amplifier vs. Supply Voltage
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE (V)
5.12
5.06
5.00
4.94
4.88
4.82
–75 –50 –25 0 25 50 10075 125 150
00288-013
V
S
= 5V
I
OUT
= 250µA
I
OUT
= 5mA
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (mV)
0.100
0.080
0.060
0.040
0.020
0.000
–75 –50 –25 0 25 50 10075 125 150
00288-014
V
S
= 5V
I
OUT
= 250µA
I
OUT
= 5mA
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
100
80
60
40
20
0
–75 –50 –25 0 25 50 10075 125 150
00288-015
V
S
= 5V
R
L
= 10kΩ
R
L
= 2kΩ
R
L
= 600kΩ
LOAD CURRENT (mA)
OUTPUT LOW VOLTAGE (mV)
100
80
60
40
20
00 1 2 3 4 5 6 7
00288-016
V
S
= 3V
V
S
= 10V
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–75 –50 –25 0 25 10075 125 150
00288-017
V
S
= 5V
V
S
= 10V
V
S
= 3V
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
0.7
0.6
0.5
0.4
0 2 4 6 8 10 12
00288-018
T
A
= 25°C
Data Sheet OP162/OP262/OP462
Rev. G | Page 9 of 20
Figure 18. Open-Loop Gain and Phase vs. Frequency (No Load)
Figure 19. Closed-Loop Gain vs. Frequency
Figure 20. Maximum Output Swing vs. Frequency
Figure 21. Step Size vs. Settling Time
Figure 22. Small-Signal Overshoot vs. Capacitance
Figure 23. Voltage Noise Density vs. Frequency
FREQUENCY (Hz)
GAIN (dB)
50
40
30
20
10
0
–10
–20
–30
PHASE SHIFT (dB)
45
90
135
180
225
270
100k 1M 10M 100M
00288-019
VS = 5V
TA = 25°C
GAIN
PHASE
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
60
40
20
0
–20
–30
10k 100k 1M 10M 100M
00288-020
V
S
= 5V
T
A
= 25°C
R
L
= 830Ω
C
L
= 5pF
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (V p-p)
5
4
3
2
1
0
10k 100k 1M 10M
00288-021
V
S
= 5V
A
VCL
= 1
R
L
= 10kΩ
C
L
= 15pF
T
A
= 25°C
DISTORTION<1%
SETTLING TIME (nS)
STEP SIZE (V)
3
1
–1
–3
2
4
0
–2
–4 0 200 400 600 800 1000
00288-022
0.01%
0.1%
0.01%
0.1%
VS = 5V
TA = 25°C
CAPACITANCE (pF)
OVERSHOOT (%)
60
40
50
30
20
10
010 100 1000
00288-023
V
S
= 5V
T
A
= 25°C
T
A
= ±50mV
R
L
= 10kΩ
+OS
–OS
FREQUENCY (Hz)
NOISE DENSITY (nV/√Hz)
70
60
50
40
30
10
20
01 10 100 1k
00288-024
V
S
= 5V
T
A
= 25°C
OP162/OP262/OP462 Data Sheet
Rev. G | Page 10 of 20
Figure 24. Current Noise Density vs. Frequency
Figure 25. Output Impedance vs. Frequency
Figure 26. CMRR vs. Frequency
Figure 27. PSRR vs. Frequency
Figure 28. 0.1 Hz to 10 Hz Noise
Figure 29. No Phase Reversal (VIN = 12 V p-p, VS = ±5 V, AV = 1)
FREQUENCY (Hz)
NOISE DENSITY (pA/Hz)
7
6
5
4
3
1
2
01 10 100 1k
00288-025
V
S
= 5V
T
A
= 25C
FREQUENCY (Hz)
OUTPUT IMPEDANCE ()
300
250
200
150
50
100
0
100k 1M 10M
00288-026
V
S
= 5V
T
A
= 25C
A
VCL
= 10
A
VCL
= 1
FREQUENCY (Hz)
CMRR (dB)
90
80
70
60
50
30
40
201k 10k 100k 1M 10M
00288-027
V
S
= 5V
T
A
= 25C
FREQUENCY (Hz)
PSRR (dB)
90
80
70
60
50
30
40
201k 10k 100k 1M 10M
00288-028
V
S
= 5V
T
A
= 25C
+PSRR –PSRR
00288-029
100
90
10
0%
V
S
= 5V
A
V
= 100k
e
n
= 0.5V p-p
2s20mV
10
0%
100
90
00288-030
V
IN
= 12V p-p
V
S
= 5V
A
V
= 1
2V
2V
20s
Data Sheet OP162/OP262/OP462
Rev. G | Page 11 of 20
Figure 30. Small Signal Transient Response
Figure 31. Large Signal Transient Response
00288-031
10
0%
100
90
200ns20mV
V
S
= 5V
A
V
= 1
T
A
= 25C
C
L
= 100pF
00288-032
10
0%
100
90
100s
500mV
V
S
= 5V
A
V
= 1
T
A
= 25C
C
L
= 100pF
OP162/OP262/OP462 Data Sheet
Rev. G | Page 12 of 20
APPLICATIONS
FUNCTIONAL DESCRIPTION
The OPx62 family is fabricated using Analog Devices’ high
speed complementary bipolar process, also called XFCB. This
process trench isolates each transistor to lower parasitic capaci-
tances for high speed performance. This high speed process has
been implemented without sacrificing the excellent transistor
matching and overall dc performance characteristic of Analog
Devices’ complementary bipolar process. This makes the OPx62
family an excellent choice as an extremely fast and accurate low
voltage op amp.
Figure 32 shows a simplified equivalent schematic for the OP162.
A PNP differential pair is used at the input of the device. The
cross connecting of the emitters lowers the transconductance of
the input stage improving the slew rate of the device. Lowering
the transconductance through cross connecting the emitters has
another advantage in that it provides a lower noise factor than if
emitter degeneration resistors were used. The input stage can
function with the base voltages taken all the way to the negative
power supply, or up to within 1 V of the positive power supply.
Figure 32. Simplified Schematic
Two complementary transistors in a common-emitter
configuration are used for the output stage. This allows the
output of the device to swing to within 50 mV of either supply
rail at load currents less than 1 mA. As load current increases,
the maximum voltage swing of the output decreases. This is due
to the collector-to-emitter saturation voltages of the output
transistors increasing. The gain of the output stage, and conse-
quently the open-loop gain of the amplifier, is dependent on the
load resistance connected at the output. Because the dominant pole
frequency is inversely proportional to the open-loop gain, the
unity-gain bandwidth of the device is not affected by the load
resistance. This is typically the case in rail-to-rail output
devices.
OFFSET ADJUSTMENT
Because the OP162/OP262/OP462 have an exceptionally low
typical offset voltage, adjustment to correct offset voltage may
not be needed. However, the OP162 has pinouts to attach a
nulling resistor. Figure 33 shows how the OP162 offset voltage
can be adjusted by connecting a potentiometer between Pin 1
and Pin 8, and connecting the wiper to VCC. It is important to
avoid accidentally connecting the wiper to VEE, as this can damage
the device. The recommended value for the potentiometer is
20 kΩ.
Figure 33. Offset Adjustment Schematic
RAIL-TO-RAIL OUTPUT
The OP162/OP262/OP462 have a wide output voltage range
that extends to within 60 mV of each supply rail with a load
current of 5 mA. Decreasing the load current extends the output
voltage range even closer to the supply rails. The common-mode
input range extends from ground to within 1 V of the positive
supply. It is recommended that there be some minimal amount
of gain when a rail-to-rail output swing is desired. The minimum
gain required is based on the supply voltage and can be found as
1−
=
S
S
V,min
V
V
A
where VS is the positive supply voltage. With a single-supply
voltage of 5 V, the minimum gain to achieve rail-to-rail output
should be 1.25.
OUTPUT SHORT-CIRCUIT PROTECTION
To achieve a wide bandwidth and high slew rate, the output of
the OP162/OP262/OP462 are not short-circuit protected. Shorting
the output directly to ground or to a supply rail may destroy the
device. The typical maximum safe output current is ±30 mA.
Steps should be taken to ensure the output of the device will not
be forced to source or sink more than 30 mA.
In applications where some output current protection is needed,
but not at the expense of reduced output voltage headroom, a
low value resistor in series with the output can be used. This is
shown in Figure 34. The resistor is connected within the feed-
back loop of the amplifier so that if VOUT is shorted to ground
V
CC
V
EE
+IN
–IN VOUT
00288-033
–5V
20kΩ
OP162
+5V
VOS
3
24
7
8
1
6
00288-034
Data Sheet OP162/OP262/OP462
Rev. G | Page 13 of 20
and VIN swings up to 5 V, the output current will not exceed
30 mA. For single 5 V supply applications, resistors less than
169 Ω are not recommended.
Figure 34. Output Short-Circuit Protection
INPUT OVERVOLTAGE PROTECTION
The input voltage should be limited to ±6 V, or damage to the
device can occur. Electrostatic protection diodes placed in the
input stage of the device help protect the amplifier from static
discharge. Diodes are connected between each input as well as
from each input to both supply pins as shown in the simplified
equivalent circuit in Figure 32. If an input voltage exceeds either
supply voltage by more than 0.6 V, or if the differential input
voltage is greater than 0.6 V, these diodes energize causing
overvoltage damage.
The input current should be limited to less than 5 mA to
prevent degradation or destruction of the device by placing an
external resistor in series with the input at risk of being overdriven.
The size of the resistor can be calculated by dividing the maxi-
mum input voltage by 5 mA. For example, if the differential
input voltage could reach 5 V, the external resistor should be
5 V/5 mA = 1 kΩ. In practice, this resistor should be placed in
series with both inputs to balance any offset voltages created by
the input bias current.
OUTPUT PHASE REVERSAL
The OP162/OP262/OP462 are immune to phase reversal as
long as the input voltage is limited to ±6 V. Figure 29 shows the
output of a device with the input voltage driven beyond the
supply voltages. Although the device’s output does not change
phase, large currents due to input overvoltage could result,
damaging the device. In applications where the possibility of an
input voltage exceeding the supply voltage exists, overvoltage
protection should be used, as described in the previous section.
POWER DISSIPATION
The maximum power that can be safely dissipated by the
OP162/OP262/OP462 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
is 150°C; device performance suffers when this limit is
exceeded. If this maximum is only momentarily exceeded,
proper circuit operation will be restored as soon as the die
temperature is reduced. Leaving the device in an “overheated”
condition for an extended period can result in permanent
damage to the device.
To calculate the internal junction temperature of the OPx62, use
the formula
TJ = PDISS × θJA + TA
where:
TJ is the OPx62 junction temperature.
PDISS is the OPx62 power dissipation.
θJA is the OPx62 package thermal resistance, junction-to-
ambient temperature.
TA is the ambient temperature of the circuit.
The power dissipated by the device can be calculated as
PDISS = ILOAD × (VS – VOUT)
where:
ILOAD is the OPx62 output load current.
VS is the OPx62 supply voltage.
VOUT is the OPx62 output voltage.
Figure 35 and Figure 36 provide a convenient way to determine
if the device is being overheated. The maximum safe power
dissipation can be found graphically, based on the package type
and the ambient temperature around the package. By using the
previous equation, it is a simple matter to see if PDISS exceeds the
device’s power derating curve. To ensure proper operation, it is
important to observe the recommended derating curves shown
in Figure 35 and Figure 36.
Figure 35. Maximum Power Dissipation vs. Temperature for
8-Lead Package Types
OPx62
VIN
VOUT
169Ω
5V
00288-035
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (Watts)
0.9
0.7
0.8
0.5
0.6
0.1
0.2
0.3
0.4
020 40 60 10080 120
00288-036
8-LEAD SOIC
8-LEAD MSOP
8-LEAD TSSOP
OP162/OP262/OP462 Data Sheet
Rev. G | Page 14 of 20
Figure 36. Maximum Power Dissipation vs. Temperature for
14-Lead Package Types
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in a dual or a
quad package be configured as a unity-gain follower with a
1 kΩ feedback resistor connected from the inverting input to
the output, and the noninverting input tied to the ground plane.
POWER-ON SETTLING TIME
The time it takes for the output of an op amp to settle after a
supply voltage is delivered can be an important consideration in
some power-up-sensitive applications. An example of this
would be in an A/D converter where the time until valid data
can be produced after power-up is important.
The OPx62 family has a rapid settling time after power-up.
Figure 37 shows the OP462 output settling times for a single-
supply voltage of VS = +5 V. The test circuit in Figure 38 was
used to find the power-on settling times for the device.
Figure 37. Oscilloscope Photo of VS and VOUT
Figure 38. Test Circuit for Power-On Settling Time
CAPACITIVE LOAD DRIVE
The OP162/OP262/OP462 are high speed, extremely accurate
devices that tolerate some capacitive loading at their outputs. As
load capacitance increases, unity-gain bandwidth of an OPx62
device decreases. This also causes an increase in overshoot and
settling time for the output. Figure 40 shows an example of this
with the device configured for unity gain and driving a 10 kΩ
resistor and 300 pF capacitor placed in parallel.
By connecting a series R-C network, commonly called a
“snubber” network, from the output of the device to ground,
this ringing can be eliminated and overshoot can be
significantly reduced. Figure 39 shows how to set up the
snubber network, and Figure 41 shows the improvement in
output response with the network added.
Figure 39. Snubber Network Compensation for Capacitive Loads
Figure 40. A Photo of a Ringing Square Wave
AMBIENT TEMPERATURE (C)
MAXIMUM POWER DISSIPATION (Wa tts)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.1
0.2
020 45 70 95 120
00288-037
14-LEAD SOIC
14-LEAD TSSOP
10
0%
100
90
500ns
2V
50mV
VS = 5V
AV = 1
RL = 10k
00288-038
OP462
V
OUT
0 TO +5V
SQUARE
10K
00288-039
1
OPx62
V
IN
V
OUT
R
X
C
X
C
L
5V
00288-040
00288-041
50mV 1s
100
90
10
0%
V
S
= 5V
A
V
= 1
C
L
= 300pF
R
L
= 10k
Data Sheet OP162/OP262/OP462
Rev. G | Page 15 of 20
Figure 41. A Photo of a Nice Square Wave at the Output
The network operates in parallel with the load capacitor, CL,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor are empirically
determined to minimize overshoot and maximize unity-gain
bandwidth. Table 6 shows a few sample snubber networks for
large load capacitors.
Table 6. Snubber Networks for Large Capacitive Loads
CLOAD RX CX
< 300 pF 140 Ω 10 nF
500 pF 100 Ω 10 nF
1 nF 80 Ω 10 nF
10 nF 10 Ω 47 nF
Higher load capacitance will reduce the unity-gain bandwidth
of the device. Figure 42 shows unity-gain bandwidth vs.
capacitive load. The snubber network does not provide any
increase in bandwidth, but it substantially reduces ringing and
overshoot, as shown between Figure 40 and Figure 41.
Figure 42. Unity-Gain Bandwidth vs. CLOAD
TOTAL HARMONIC DISTORTION AND CROSSTALK
The OPx62 device family offers low total harmonic distortion
making it an excellent choice for audio applications. Figure 43
shows a graph of THD plus noise figures at 0.001% for the
OP462.
Figure 44 shows the worst case crosstalk between two amplifiers
in the OP462. A 1 V rms signal is applied to one amplifier while
measuring the output of an adjacent amplifier. Both amplifiers
are configured for unity gain and supplied with ±2.5 V.
Figure 43. THD + N vs. Frequency
Figure 44. Crosstalk vs. Frequency
PCB LAYOUT CONSIDERATIONS
Because the OP162/OP262/OP462 can provide gains at high
frequency, careful attention to board layout and component
selection is recommended. As with any high speed application,
a good ground plane is essential to achieve the optimum
performance. This can significantly reduce the undesirable
effects of ground loops and I × R losses by providing a low
impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground
plane.
Use chip capacitors for supply bypassing, with one end of the
capacitor connected to the ground plane and the other end
connected within 1/8 inch of each power pin. An additional
large tantalum electrolytic capacitor (4.7 μF to 10 μF) should be
connected in parallel. This capacitor provides current for fast,
large-signal changes at the device’s output; therefore, it does not
need to be placed as close to the supply pins.
00288-042
10
0%
100
90
50mV 1s
V
S
= 5V
A
V
= 1
C
L
= 300pF
R
L
= 10k
WITH SNUBBER:
R
X
= 140
C
X
= 10nF
CLOAD
BANDWIDTH (MHz)
10
7
8
9
5
6
4
3
2
1
0
10pF 100pF 1nF 10nF
00288-043
FREQUENCY (Hz)
THD+N (%)
0.010
0.001
0.000120 100 1k 10k 20k
00288-044
VS = 2.5V
AV = 1
VIN = 1.0V rms
RL = 10k
BANDWIDTH:
<10Hz TO 22kHz
FREQUENCY (Hz)
XTALK (dBV)
–40
–90
–80
–70
–60
–50
–140
–130
–120
–110
–100
20 100 1k 10k 20k
00288-045
A
V
= 1
V
IN
= 1.0V rms
(0dBV)
R
L
= 10k
V
S
= 2.5V
OP162/OP262/OP462 Data Sheet
Rev. G | Page 16 of 20
APPLICATIONS CIRCUITS
SINGLE-SUPPLY STEREO HEADPHONE DRIVER
Figure 45 shows a stereo headphone output amplifier that can
operate from a single 5 V supply. The reference voltage is
derived by dividing the supply voltage down with two 100 kΩ
resistors. A 10 µF capacitor prevents power supply noise from
contaminating the audio signal and establishes an ac ground for
the volume control potentiometers.
The audio signal is ac-coupled to each noninverting input
through a 10 µF capacitor. The gain of the amplifier is con-
trolled by the feedback resistors and is (R2/R1) + 1. For this
example, the gain is 6. By removing R1, the amplifier would
have unity gain. To short-circuit protect the output of the
device, a 169 Ω resistor is placed at the output in the feedback
network. This prevents any damage to the device if the head-
phone output becomes shorted. A 270 µF capacitor is used at
the output to couple the amplifier to the headphone. This value
is much larger than that used for the input because of the low
impedance of headphones, which can range from 32 Ω to 600 Ω
or more.
Figure 45. Headphone Output Amplifier
INSTRUMENTATION AMPLIFIER
Because of their high speed, low offset voltages, and low noise
characteristics, the OP162/OP262/OP462 can be used in a wide
variety of high speed applications, including precision instru-
mentation amplifiers. Figure 46 shows an example of such an
application.
Figure 46. High Speed Instrumentation Amplifier
The differential gain of the circuit is determined by RG, where
G
DIFF
R
A2
1+=
with the RG resistor value in kΩ. Removing RG sets the circuit
gain to unity.
The fourth op amp, OP462-D, is optional and is used to
improve CMRR by reducing any input capacitance to the
amplifier. By shielding the input signal leads and driving the
shield with the common-mode voltage, input capacitance is
eliminated at common-mode voltages. This voltage is derived
from the midpoint of the outputs of OP462-A and OP462-B by
using two 10 kΩ resistors followed by OP462-D as a unity-gain
buffer.
It is important to use 1% or better tolerance components for the
2 kΩ resistors, as the common-mode rejection is dependent on
their ratios being exact. A potentiometer should also be connected
in series with the OP462-C noninverting input resistor to ground
to optimize common-mode rejection.
The circuit in Figure 46 was implemented to test its settling
time. The instrumentation amp was powered with −5 V, so the
input step voltage went from −5 V to +4 V to keep the OP462
within its input range. Therefore, the 0.05% settling range is
when the output is within 4.5 mV. Figure 47 shows the positive
slope settling time to be 1.8 µs, and Figure 48 shows a settling
time of 3.9 µs for the negative slope.
OP262-A
5V
169Ω270µF
47kΩ
L VOLUME
CONTROL
R1 = 10kΩ
10µF
10µF
10kΩ
5V
100kΩ
10µF
100kΩ
R2 = 50kΩ
LEFT IN
OP262-B
5V
169Ω270µF
47kΩ
HEADPHONE
RIGHT
HEADPHONE
LEFT
10kΩ
R VOLUME
CONTROL
10µF
RIGHT IN
R2 = 50kΩ
10µF
R1 = 10kΩ
00288-046
OP462-A
OP462-B
OP462-C
OP462-D
–V
IN
+V
IN
1kΩ
10kΩ
2kΩ
1.9kΩ
200Ω
10 TURN
(OPTIONAL)
OUTPUT
R
G
1kΩ
10kΩ
2kΩ
2kΩ
00288-047
Data Sheet OP162/OP262/OP462
Rev. G | Page 17 of 20
Figure 47. Positive Slope Settling Time
Figure 48. Negative Slope Settling Time
DIRECT ACCESS ARRANGEMENT
Figure 49 shows a schematic for a 5 V single-supply transmit/
receive telephone line interface for 600 Ω transmission systems.
It allows full-duplex transmission of signals on a transformer-
coupled 600 Ω line. Amplifier A1 provides gain that can be
adjusted to meet the modem output drive requirements. Both
A1 and A2 are configured to apply the largest possible differential
signal to the transformer. The largest signal available on a single
5 V supply is approximately 4.0 V p-p into a 600 Ω transmission
system. Amplifier A3 is configured as a difference amplifier to
extract the receive information from the transmission line for
amplification by A4. A3 also prevents the transmit signal from
interfering with the receive signal. The gain of A4 can be adjusted
in the same manner as A1 to meet the modem’s input signal
requirements. Standard resistor values permit the use of SIP
(single in-line package) format resistor arrays. Couple this with
the OP462 14-lead SOIC or TSSOP package and this circuit
offers a compact solution.
Figure 49. Single-Supply Direct Access Arrangement for Modems
00288-048
10
0%
100
90
1s
5mV 2V
00288-049
10
0%
100
90
5mV
1µs
10
0%
100
90
1s
5mV 2V
6.2V
6.2V
TRANSMIT
TXA
RECEIVE
RXA
2k
P1
TX GAIN
ADJUST
A1
A2
A3
A4
A1, A2 = 1/2 AD8532
A3, A4 = 1/2 AD8532
R3
360
Z
O
600
R1
10k
R13
10k
R10
10k
R9
10k
R11
10kC2
0.1F
C1
0.1F
10F
R12
10k
R7
10k
R8
10k
R5
10k
R6
10k
R14
14.3k
R2
9.09k
1:1
T1
TO TELEPHONE
LINE 12
3
76
5
2
31
6
57
P2
RX GAIN
ADJUST
2k
5V DC
MIDCOM
671-8005
00288-050
OP162/OP262/OP462 Data Sheet
Rev. G | Page 18 of 20
OUTLINE DIMENSIONS
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body
S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
Figure 51. 8-Lead Thin Shrink Small Outline Package [TSSOP)
(RU-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
C
OPLANARITY
0.10
85
41
PIN 1
0.65 BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
0.20
0.09
8°
0°
6.40 BSC
4.50
4.40
4.30
3.10
3.00
2.90
COPLANARITY
0.10
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Data Sheet OP162/OP262/OP462
Rev. G | Page 19 of 20
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Figure 53. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body
S-Suffix (R-14)
Dimensions shown in millimeters and (inches)
COM P LIANT T O JEDE C S TANDARDS M O-153-AB- 1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PI N 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
CONTROLLING DIMENSIONSARE I N M IL LI M E TERS ; INCH DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS - 012- AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
45°
OP162/OP262/OP462 Data Sheet
Rev. G | Page 20 of 20
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
OP162GSZ −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP162GSZ-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP162GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP262DRUZ-REEL −40°C to +125°C 8-Lead TSSOP RU-8
OP262GS −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP262GS-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP262GS-REEL7 −40°C to +125°C 8-Lead SOIC_ S-Suffix (R-8)
OP262GSZ −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP262GSZ-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8)
OP262GSZ-REEL7
−40°C to +125°C
8-Lead SOIC_N
S-Suffix (R-8)
OP262HRU-REEL −40°C to +125°C 8-Lead TSSOP RU-8
OP262HRUZ −40°C to +125°C 8-Lead TSSOP RU-8
OP262HRUZ-REEL −40°C to +125°C 8-Lead TSSOP RU-8
OP462GS −40°C to +125°C 14-Lead SOIC_ S-Suffix (R-14)
OP462GS-REEL −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14)
OP462GS-REEL7 −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14)
OP462GSZ −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14)
OP462GSZ-REEL −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14)
OP462GSZ-REEL7 −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14)
OP462HRU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
OP462HRUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00288-0-5/12(G)
