LTC2207-14/LTC2206-14 14-Bit, 105Msps/80Msps ADCs Description Features Sample Rate: 105Msps/80Msps nn 77.3dBFS Noise Floor nn 98dB SFDR nn SFDR >82dB at 250MHz (1.5V P-P Input Range) nn PGA Front End (2.25V P-P or 1.5VP-P Input Range) nn 700MHz Full Power Bandwidth S/H nn Optional Internal Dither nn Optional Data Output Randomizer nn Single 3.3V Supply nn Power Dissipation: 947mW/762mW nn Optional Clock Duty Cycle Stabilizer nn Out-of-Range Indicator nn Pin-Compatible Family nn 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) nn 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) nn 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) nn 40Msps: LTC2204 (16-Bit) nn 25Msps: LTC2203 (16-Bit) Single-Ended Clock nn 10Msps: LTC2202 (16-Bit) Single-Ended Clock nn 48-Pin 7mm x 7mm QFN Package The LTC(R)2207-14/LTC2206-14 are 105Msps/80Msps, sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700MHz. The input range of the ADC can be optimized with the PGA front end. Applications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. nn The LTC2207-14/LTC2206-14 are perfect for demanding communications applications, with AC performance that includes 77.3dB SNR and 98dB spurious free dynamic range (SFDR). Ultralow jitter of 80fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include 1.5LSB INL, 1LSB DNL (no missing codes) over temperature. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. Telecommunications Receivers nn Cellular Base Stations nn Spectrum Analysis nn Imaging Systems nn ATE nn nn Typical Application LTC2207-14: 32K Point FFT, fIN = 14.86MHz, -1dBFS, PGA = 0, 105Msps 3.3V SENSE OVDD 2.2F AIN + ANALOG INPUT AIN- 1.25V COMMON MODE BIAS VOLTAGE + - INTERNAL ADC REFERENCE GENERATOR 14-BIT PIPELINED ADC CORE S/H AMP ENC- 0 -10 -20 OF CLKOUT+ CLKOUT- D13 * * * D0 OUTPUT DRIVERS CORRECTION LOGIC AND SHIFT REGISTER -30 OGND CLOCK/DUTY CYCLE CONTROL ENC+ 0.5V TO 3.6V 0.1F AMPLITUDE (dBFS) VCM PGA SHDN DITH MODE OE RAND -50 -60 -70 -80 -90 3.3V VDD GND -40 0.1F 0.1F 0.1F -100 -110 -120 2207614 TA01 ADC CONTROL INPUTS For more information www.linear.com/LTC2207-14 0 10 30 40 20 FREQUENCY (MHz) 50 2207614 TA01b 220714614fd 1 LTC2207-14/LTC2206-14 Absolute Maximum Ratings OVDD = VDD (Notes 1, 2) Pin Configuration TOP VIEW 48 GND 47 PGA 46 RAND 45 MODE 44 OE 43 OF 42 D13 41 D12 40 D11 39 D10 38 OGND 37 OVDD Supply Voltage (VDD).................................... -0.3V to 4V Digital Output Ground Voltage (OGND)......... -0.3V to 1V Analog Input Voltage (Note 3)....... -0.3V to (VDD + 0.3V) Digital Input Voltage..................... -0.3V to (VDD + 0.3V) Digital Output Voltage................. -0.3V to (OVDD + 0.3V) Power Dissipation............................................. 2000mW Operating Temperature Range LTC2207-14C/LTC2206-14C...................... 0C to 70C LTC2207-14I/LTC2206-14I....................-40C to 85C Storage Temperature Range................... -65C to 150C Digital Output Supply Voltage (OVDD)........... -0.3V to 4V SENSE 1 VCM 2 VDD 3 VDD 4 GND 5 AIN+ 6 AIN- 7 GND 8 ENC+ 9 ENC- 10 GND 11 VDD 12 36 OVDD 35 D9 34 D8 33 D7 32 D6 31 OGND 30 CLKOUT+ 49 VDD 13 VDD 14 GND 15 SHDN 16 DITH 17 NC 18 NC 19 D0 20 D1 21 D2 22 OGND 23 OVDD 24 29 CLKOUT- 28 D5 27 D4 26 D3 25 OVDD UK PACKAGE 48-LEAD (7mm x 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49) MUST BE SOLDERED TO PCB BOARD TJMAX = 125C, JA = 29C/W Order Information LEAD FREE FINISH TAPE AND REEL LTC2207CUK-14#PBF PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2207CUK-14#TRPBF LTC2207UK-14 48-Lead (7mm x 7mm) Plastic Plastic QFN 0C to 70C LTC2206CUK-14#PBF LTC2206CUK-14#TRPBF LTC2206UK-14 48-Lead (7mm x 7mm) Plastic Plastic QFN 0C to 70C LTC2207IUK-14#PBF LTC2207IUK-14#TRPBF LTC2207UK-14 48-Lead (7mm x 7mm) Plastic Plastic QFN -40C to 85C LTC2206IUK-14#PBF LTC2206IUK-14#TRPBF LTC2206UK-14 48-Lead (7mm x 7mm) Plastic Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) PARAMETER CONDITIONS TYP MAX UNITS Integral Linearity Error Differential Analog Input (Note 5) l MIN 0.4 1.5 LSB Differential Linearity Error Differential Analog Input l 0.1 1 LSB Offset Error (Note 6) l 1 10.3 mV Gain Error External Reference l Full-Scale Drift Internal Reference External Reference Offset Drift Transition Noise 2 V/C 10 0.2 2.3 %FS 30 15 ppm/C ppm/C 0.8 LSBRMS 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ - AIN-) 3.135V VDD 3.465V l MIN VIN, CM Analog Input Common Mode Differential Input (Note 7) l 1 IIN Analog Input Leakage Current 0V AIN+, AIN- VDD (Note 8) l ISENSE SENSE Input Leakage Current 0V SENSE VDD (Note 9) l IMODE MODE Pin Pull-Down Current to GND TYP MAX UNITS 1.5 to 2.25 1.25 VP-P 1.5 V -1 1 A -4 3 A Sample Mode ENC+ < ENC- Hold Mode ENC+ > ENC- 10 A 6.7 1.8 pF pF CIN Analog Input Capacitance tAP Sample-and-Hold Acquisition Delay Time 1 ns tJITTER Sample-and-Hold Acquisition Delay Time Jitter 80 fsRMS CMRR Analog Input Common Mode Rejection Ratio 1V < (AIN+ = AIN-) <1.5V 80 dB BW-3dB Full Power Bandwidth RS 25 700 MHz Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4) SYMBOL PARAMETER SNR CONDITIONS MIN LTC2206-14 TYP MAX Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), TA = 25C l 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 77.3 75.1 76 75.8 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1), TA = 25C l 140MHz Input (1.5V Range, PGA = 1) 73.1 72.9 Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), TA = 25C l 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 85 84 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1), TA = 25C l 140MHz Input (1.5V Range, PGA = 1) dBFS dBFS 77.2 77.2 75 dBFS dBFS dBFS 76.9 75 dBFS dBFS 76.2 74.5 74.6 dBFS dBFS dBFS 75.8 75.1 75.8 75.1 dBFS dBFS 98 98 98 98 dBc dBc 93 93 98 dBc dBc dBc 90 94 dBc dBc 85 90 90 dBc dBc dBc 81 85 dBc dBc 77.2 77.2 75 76 75.8 76.2 74.5 74.6 93 93 98 73.1 72.9 85 84 90 94 82 81 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) LTC2207-14 TYP MAX UNITS 77.3 75.1 76.9 75 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) SFDR MIN 85 90 90 81 85 82 81 220714614fd For more information www.linear.com/LTC2207-14 3 LTC2207-14/LTC2206-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SFDR 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) Spurious Free Dynamic Range 4th Harmonic or Higher MIN 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) LTC2206-14 TYP MAX 100 100 l 90 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) l 86.5 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), TA = 25C l 15MHz Input (2.25V Range, PGA = 0 15MHz Input (1.5V Range, PGA = 1) 75.9 75.7 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) SFDR SFDR 4 Spurious Free Dynamic Range at -25dBFS Dither "OFF" Spurious Free Dynamic Range at -25dBFS Dither "ON" dBc dBc 100 100 dBc dBc 100 100 dBc dBc 95 97 dBc dBc 89 93 89 93 dBc dBc 77 74.9 77 74.9 dBFS dBFS 77.1 77.1 75.3 dBFS dBFS dBFS 76.7 75 dBFS dBFS 74.8 74.5 74.5 dBFS dBFS dBFS 100 100 90 95 97 77.1 77.1 75.3 86.5 75.9 75.7 76.7 75 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1), TA = 25C l 140MHz Input (1.5V Range, PGA = 1) 72.7 72.5 LTC2207-14 TYP MAX UNITS 100 100 100 100 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) S/(N+D) Signal-to-Noise Plus Distortion Ratio MIN 74.8 74.5 74.5 72.7 72.5 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 74.1 73.7 74.4 73.7 dBFS dBFS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dBFS dBFS 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dBFS dBFS 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dBFS dBFS 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 97 97 97 97 dBFS dBFS 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 96 96 96 96 dBFS dBFS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 108 108 108 108 dBFS dBFS 107 107 dBFS dBFS 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) l 95 107 107 95 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 107 107 107 107 dBFS dBFS 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 102 102 102 102 dBFS dBFS 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dBFS dBFS 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 Common Mode Bias Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 VCM Output Tempco IOUT = 0 40 ppm/C VCM Line Regulation 3.135V VDD 3.465V 1 mV/ V VCM Output Resistance -1mA | IOUT | 1mA 2 l MIN TYP MAX UNITS 1.15 1.25 1.35 V Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC-) VID Differential Input Voltage (Note 7) VICM Common Mode Input Voltage Internally Set Externally Set (Note 7) RIN Input Resistance (See Figure 2) 6 k CIN Input Capacitance (Note 7) 3 pF l 0.2 1.4 V 1.6 3 V LOGIC INPUTS (DITH, PGA, SHDN, RAND) VIH High Level Input Voltage VDD = 3.3V l VIL Low Level Input Voltage VDD = 3.3V l IIN Input Current VIN = 0V to VDD l CIN Input Capacitance (Note 7) High Level Output Voltage VDD = 3.3V 2 V 0.8 V 10 A 1.5 pF 3.299 3.29 V V LOGIC OUTPUTS OVDD = 3.3V VOH VOL Low Level Output Voltage VDD = 3.3V IO = -10A IO = -200A l IO = 160A IO = 1.60A l 3.1 0.01 0.1 0.4 V V ISOURCE Output Source Current VOUT = 0V -50 mA ISINK Output Sink Current VOUT = 3.3V 50 mA VOH High Level Output Voltage VDD = 3.3V IO = -200A 2.49 V VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V VOH High Level Output Voltage VDD = 3.3V IO = -200A 1.79 V VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V OVDD = 2.5V OVDD = 1.8V 220714614fd For more information www.linear.com/LTC2207-14 5 LTC2207-14/LTC2206-14 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN LTC2206-14 TYP MAX MIN LTC2207-14 TYP MAX 3.135 3.3 3.465 3.135 3.3 3.465 VDD Analog Supply Voltage PSHDN Shutdown Power OVDD Output Supply Voltage IVDD Analog Supply Current DC Input l 231 275 PDIS Power Dissipation DC Input l 762 908 l SHDN = VDD 0.2 l 0.5 0.2 3.6 0.5 UNITS V mW 3.6 V 287 350 mA 947 1155 mW Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN LTC2206-14 TYP MAX MIN 80 1 l 1 Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l 5.94 4.06 6.25 6.25 500 500 4.52 3.10 Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l 5.94 4.06 6.25 6.25 500 500 4.52 3.10 LTC2207-14 TYP MAX UNITS 105 MHz 4.762 4.762 500 500 ns ns 4.762 4.762 500 500 ns ns fS Sampling Frequency tL ENC Low Time tH ENC High Time tAP Sample-and-Hold Aperture Delay tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l -0.6 0 0.6 -0.6 0 0.6 ns tOE DATA Access time Bus Relinquish time CL = 5pF (Note 7) (Note 7) l l 5 5 15 15 5 5 15 15 ns ns -0.7 Pipeline Latency 7 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 105MHz (LTC2207-14), 80MHz (LTC220614) differential ENC+/ENC- = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise specified. 6 -0.7 7 ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a "best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -1/2LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: The dynamic current of the switched capacitors analog inputs can be large compared to the leakage current and will vary with the sample rate. Note 9: Leakage current will have higher transient current at power up. Keep drive resistance at or below 1k. 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 Timing Diagram tAP ANALOG INPUT N+4 N N+3 N+2 tH ENC N+1 tL - ENC+ tD N-7 D0-D13, OF N-6 N-5 N-4 N-3 tC CLKOUT+ CLKOUT - 2207614 TD01 Typical Performance Characteristics LTC2207-14: Differential Nonlinearity (DNL) vs Output Code 1.0 0.5 0.8 0.4 0.6 0.3 0.2 0 -0.2 -0.4 0 -0.1 -0.4 -0.5 100000 50000 0 0 8201 2048 4096 6144 8192 10240 12288 14336 16384 OUTPUT CODE 2207614 G01 -20 -20 -20 -30 -30 -30 -60 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) 0 -10 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 -110 -110 -110 -120 -120 0 10 30 40 20 FREQUENCY (MHz) 50 2207614 G04 0 10 30 40 20 FREQUENCY (MHz) 50 2207614 G05 8211 2207614 G03 0 -50 8205 8207 8209 OUTPUT CODE LTC2207-14: 64K Point FFT, fIN = 15.1MHz, -25dBFS, PGA = 0, RAND "On", Dither "Off" -10 -40 8203 2207614 G02 LTC2207-14: 32K Point FFT, fIN = 14.86MHz, -1dBFS, PGA = 0, RAND "On", Dither "Off" LTC2207-14: 32K Point FFT, fIN = 5.23MHz, -1dBFS, PGA = 0, RAND "On", Dither "Off" AMPLITUDE (dBFS) 150000 -0.2 -0.3 2048 4096 6144 8192 10240 12288 14336 16384 OUTPUT CODE 200000 0.2 -0.8 0 250000 0.1 -0.6 -1.0 LTC2207-14: AC Grounded Input Histogram COUNT 0.4 DNL ERROR (LSB) INL ERROR (LSB) LTC2207-14: Integral Nonlinearity (INL) vs Output Code -120 0 10 30 40 20 FREQUENCY (MHz) 50 2207614 G06 220714614fd For more information www.linear.com/LTC2207-14 7 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2207-14: 64K Point FFT, fIN = 15.1MHz, -25dBFS, PGA = 0, RAND "On", Dither "On" LTC2207-14: SFDR vs Input Level, fIN = 15.1MHz, PGA = 0, RAND "On", Dither "Off" 0 LTC2207-14: SFDR vs Input Level, fIN = 15.1MHz, PGA = 0, RAND "On", Dither "On" 120 120 100 100 -20 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 SFDR (dBc AND dBFS) -10 80 60 40 20 -100 80 60 40 20 -110 -120 0 10 30 40 20 FREQUENCY (MHz) 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 50 2207614 G08 2207614 G07 LTC2207-14: 32K Point 2-Tone FFT, fIN = 14.87MHz and 18.56MHz, -15dBFS, PGA = 0, RAND "On", Dither "Off' LTC2207-14: 32K Point FFT, fIN = 70.24MHz, -1dBFS, PGA = 0, RAND "On", Dither "Off' 0 0 -10 -10 -20 -20 -20 -30 -30 -30 -50 -60 -70 -80 AMPLITUDE (dBFS) 0 -40 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 -110 -110 -110 -120 -120 0 10 30 40 20 FREQUENCY (MHz) 50 0 10 30 40 20 FREQUENCY (MHz) 2207614 G10 -120 50 LTC2207-14: 32K Point 2-Tone FFT, fIN = 69.2MHz and 76.5MHz, -7dBFS, PGA = 0, RAND "On", Dither "Off' -20 -20 -20 -30 -30 -30 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) 0 -10 -60 -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -100 -110 -110 -110 -120 -120 10 30 40 20 FREQUENCY (MHz) 50 2207614 G15 8 0 10 30 40 20 FREQUENCY (MHz) 50 2207614 G13 50 -40 -90 0 30 40 20 FREQUENCY (MHz) LTC2207-14: 32K Point 2-Tone FFT, fIN = 69.2MHz and 76.5MHz, -15dBFS, PGA = 0, RAND "On", Dither "Off' 0 -50 10 2207614 G12 -10 -40 0 2207614 G11 LTC2207-14: 32K Point FFT, fIN = 70.24MHz, -1dBFS, PGA = 1, RAND "On", Dither "Off' 0 2207614 G09 -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2207-14: 32K Point 2-Tone FFT, fIN = 14.87MHz and 18.56MHz, -7dBFS, PGA = 0, RAND "On", Dither "Off' AMPLITUDE (dBFS) 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 -120 0 10 30 40 20 FREQUENCY (MHz) 50 2207614 G14 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2207-14: 64K Point FFT, fIN = 70.1MHz, -25dBFS, PGA = 0, RAND "On", Dither "On' LTC2207-14: 32K Point FFT, fIN = 174.8MHz, -1dBFS, PGA = 1, RAND "On", Dither "Off' 0 0 -10 -10 -20 -20 -20 -30 -30 -30 -40 -50 -60 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2207-14: 64K Point FFT, fIN = 70.1MHz, -25dBFS, PGA = 0, RAND "On", Dither "Off' -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 -110 -110 -110 -120 -120 0 10 30 40 20 FREQUENCY (MHz) 50 0 10 30 40 20 FREQUENCY (MHz) -120 50 10 0 30 40 20 FREQUENCY (MHz) 2207614 G17 2207614 G16 LTC2207-14: 32K Point FFT, fIN = 250.11MHz, -1dBFS, PGA = 1, RAND "On", Dither "Off' 2207614 G18 LTC2207-14: SFDR vs Input Level, fIN = 140.1MHz, PGA = 1, RAND "On", Dither "Off" 0 50 LTC2207-14: SFDR vs Input Level, fIN = 140.1MHz, PGA = 1, RAND "On", Dither "On" 120 120 100 100 -20 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 SFDR (dBc AND dBFS) -10 80 60 40 20 -100 80 60 40 20 -110 -120 0 10 30 40 20 FREQUENCY (MHz) 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 50 2207614 G20 2207614 G19 LTC2207-14: SFDR (HD2 and HD3) vs Input Frequency LTC2207-14: SNR and SFDR vs Sample Rate, fIN = 5.1MHz, -1dBFS 78 110 100 77 105 76 100 80 SNR (dBFS) PGA = 1 85 PGA = 0 75 75 73 72 65 71 0 400 100 300 200 INPUT FREQUENCY (MHz) 500 2207614 G22 PGA = 0 74 70 60 SNR AND SFDR (dBFS) 105 90 70 0 2207614 G21 LTC2207-14: SNR vs Input Frequency 95 SFDR (dBc) 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 PGA = 1 SFDR 95 90 85 SNR 80 75 0 100 200 400 300 INPUT FREQUENCY (MHz) 500 2207614 G23 70 0 25 50 75 100 125 150 175 200 SAMPLE RATE (Msps) 2207614 G24 220714614fd For more information www.linear.com/LTC2207-14 9 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS 340 105 100 VDD = 3.3V 300 SFDR 95 90 85 VDD = 3.47V 280 VDD = 3.13V 260 240 SNR 80 220 75 70 2.8 3.2 3.0 3.4 SUPPLY VOLTAGE (V) 200 3.6 10 30 90 70 110 50 SAMPLE RATE (Msps) 130 90 80 SFR 2.5 50000 8191 2207614 G31 60 0.5 0.4 0.6 0.3 0.4 0.2 0 -0.2 -0.4 0.2 0.1 0 -0.1 -0.2 -0.3 -0.8 -0.4 -1.0 -0.5 0 2048 4096 6144 8192 102401228814336 16384 OUTPUT CODE 0 2048 4096 6144 8192 102401228814336 16384 OUTPUT CODE 2207614 G30 LTC2206-14: 32K Point FFT, fIN = 14.86MHz, -1dBFS, PGA = 0, RAND = "On", Dither "Off" 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 70 LTC2206-14: Differential Nonlinearity (DNL) vs Output Code AMPLITUDE (dBFS) AMPLITUDE (dBFS) 200000 100000 50 2207614 G27 LTC2206-14: 32K Point FFT, fIN = 5.23MHz, -1dBFS, PGA = 0, RAND = "On", Dither "Off" 150000 40 2207614 G29 250000 10 30 0.8 LTC2206-14: AC Grounded Input Histogram 8189 70 1.0 2207614 G28 8187 8185 OUTPUT CODE SNR DCS ON DUTY CYCLE (%) -0.6 70 8183 SFDR DCS OFF 80 60 150 DNL ERROR (LSB) SFDR INL ERROR (LSB) SNR (dBFS) AND SFDR (dBc) 100 0 8181 90 LTC2206-14: Integral Nonlinearity (INL) vs Output Code 110 1.5 1.0 2.0 INPUT COMMON MODE (V) SFDR DCS ON 2207614 G26 LTC2207-14: SNR and SFDR vs Analog Input Common Mode Voltage, fIN = 5.1MHz, -1dBFS 60 0.5 100 SNR DCS OFF 2207614 G25 COUNT LTC2207-14: SNR and SFDR vs Duty Cycle, 105Msps 110 320 IVDD (mA) SNR AND SFDR (dBFS) LTC2207-14: IVDD vs Sample Rate, fIN = 5.1MHz, -1dBFS SNR (dBFS) AND SFDR (dBc) 110 LTC2207-14: SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz, -1dBFS 0 10 30 20 FREQUENCY (MHz) 40 2207614 G32 -120 0 10 30 20 FREQUENCY (MHz) 40 2207614 G33 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2206-14: 64K Point FFT, fIN = 15.1MHz, -25dBFS, PGA = 0, RAND = "On", Dither "On" 0 -10 -20 -20 -30 -30 -40 -50 -60 -70 -80 -60 -70 -80 -100 -100 -110 -110 10 30 20 FREQUENCY (MHz) -120 40 100 -50 -90 0 120 -40 -90 -120 60 40 0 10 30 20 FREQUENCY (MHz) 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 40 LTC2206-14: 32K Point 2-Tone FFT, fIN = 14.87MHz and 18.56MHz, -7dBFS, PGA = 0, RAND = "On", Dither "Off" AMPLITUDE (dBFS) 100 80 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 0 LTC2206-14: 32K Point 2-Tone FFT, fIN = 14.87MHz and 18.56MHz, -15dBFS, PGA = 0, RAND = "On", Dither "Off" AMPLITUDE (dBFS) 120 0 10 30 20 FREQUENCY (MHz) 2207614 G37 -120 40 0 -10 -20 -20 -20 -30 -30 -30 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) 0 -60 -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -100 -110 -110 -110 -120 -120 10 30 20 FREQUENCY (MHz) 40 2207614 G40 0 10 30 20 FREQUENCY (MHz) 40 -40 -90 0 30 20 FREQUENCY (MHz) LTC2206-14: 32K Point 2-Tone FFT, fIN = 69.2MHz and 76.5MHz, -7dBFS, PGA = 0, RAND = "On", Dither "Off" -10 -50 10 2207614 G39 LTC2206-14: 32K Point FFT, fIN = 70.24MHz, -1dBFS, PGA = 1, RAND = "On", Dither "Off" -40 0 2207614 G38 LTC2206-14: 32K Point FFT, fIN = 70.24MHz, -1dBFS, PGA = 0, RAND = "On", Dither "Off" 0 2207614 G36 2207614 G35 LTC2206-14: SFDR vs Input Level, fIN = 15.1MHz, PGA = 0, RAND = "On", Dither "On" SFDR (dBc AND dBFS) 80 20 2207614 G34 AMPLITUDE (dBFS) LTC2206-14: SFDR vs Input Level, fIN = 15.1MHz, PGA = 0, RAND = "On", Dither "Off" SFDR (dBc AND dBFS) 0 -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2206-14: 64K Point FFT, fIN = 15.1MHz, -25dBFS, PGA = 0, RAND = "On", Dither "Off" 40 2207614 G43 -120 0 10 30 20 FREQUENCY (MHz) 40 2207614 G41 220714614fd For more information www.linear.com/LTC2207-14 11 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS 0 -10 -20 -20 -20 -30 -30 -30 -40 -50 -60 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 -10 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 -110 -110 -110 -120 -120 10 30 20 FREQUENCY (MHz) 40 0 10 30 20 FREQUENCY (MHz) -20 -20 -30 -30 -60 -70 -80 -60 -70 -80 -100 -100 -110 -110 10 30 20 FREQUENCY (MHz) -120 40 100 -50 -90 40 0 10 30 20 FREQUENCY (MHz) 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 40 SFDR (dBc) 80 LTC2206-14: SNR vs Input Frequency, RAND = "On", DITH = "On" 60 105 79 100 78 95 77 90 76 85 PGA = 1 80 PGA = 0 75 40 20 0 2207614 G49 74 73 72 65 71 0 PGA = 0 75 70 60 200 300 100 400 INPUT FREQUENCY (MHz) 0 2207614 G48 LTC2206-14: SFDR (HD2 and HD3) vs Input Frequency 100 12 60 2207614 G47 120 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 80 20 2207614 G46 LTC2206-14: SFDR vs Input Level, fIN = 140.1MHz, PGA = 1, RAND = "On", Dither "On" 40 120 -40 -90 0 30 20 FREQUENCY (MHz) LTC2206-14: SFDR vs Input Level, fIN = 140.1MHz, PGA = 1, RAND = "On", Dither "Off" SFDR (dBc AND dBFS) 0 -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 -10 -50 10 2207614 G45 LTC2206-14: 32K Point FFT, fIN = 250.11MHz, -1dBFS, PGA = 1, RAND = "On", Dither "Off" -40 0 2207614 G44 LTC2206-14: 32K Point FFT, fIN = 170.21MHz, -1dBFS, PGA = 1, RAND = "On", Dither "Off" -120 -120 40 SNR (dBFS) 0 2207614 G42 SFDR (dBc AND dBFS) LTC2206-14: 64K Point FFT, fIN = 70.1MHz, -25dBFS, PGA = 0, RAND = "On", Dither "On" LTC2206-14: 64K Point FFT, fIN = 70.1MHz, -25dBFS, PGA = 0, RAND = "On", Dither "Off" LTC2206-14: 32K Point 2-Tone FFT, fIN = 69.2MHz and 76.5MHz, -15dBFS, PGA = 0, RAND = "On", Dither "Off" 500 2207614 G50 70 PGA = 1 0 400 100 300 200 INPUT FREQUENCY (MHz) 500 2207614 G51 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2206-14: SNR and SFDR vs Sample Rate, fIN = 5.1MHz, -1dBFS 110 110 95 90 85 80 SNR 75 70 320 VDD = 3.3V 100 SFDR 300 95 IVDD (mA) 100 90 85 80 35 60 110 85 SAMPLE RATE (Msps) 135 3.2 3.4 3.0 SUPPLY VOLTAGE (V) 2207614 G52 130 150 0.10 70 SNR DCS OFF 50 60 100 0.06 SFDR GAIN ERROR DRIFT (%) SNR (dBFS) AND SFDR (dBc) SNR DCS ON 95 90 85 SNR 80 -0.02 -0.06 70 70 0.5 1.5 2.0 1.0 ANALOG INPUT COMMON MODE (V) 2207614 G55 2.5 -0.10 -50 -30 30 50 -10 10 TEMPERATURE (C) 70 90 2207614 G57 2207614 G56 Gain Error Drift vs Temperature, Internal Reference, 5 Units Drift from 25C Input Offset Voltage Drift vs Temperature, 5 Units, Drift from 25C 0.3 1.5 INPUT OFFSET VOLTAGE DRIFT (mV) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -50 0.02 75 DUTY CYCLE (%) GAIN ERROR DRIFT (%) SNR (dBFS) AND SFDR (dBc) SFDR DCS OFF 40 90 70 110 50 SAMPLE RATE (Msps) 105 100 30 30 Gain Error Drift vs Temperature, External Reference, 5 Units, Drift from 25C 110 SFDR DCS ON 60 10 2207614 G54 LTC2206-14: SNR and SFDR vs Analog Input Common Mode Voltage, fIN = 5.1MHz, -1dBFS 110 80 200 3.6 2207614 G53 LTC2206-14: SNR and SFDR vs Duty Cycle, 80Msps 90 VDD = 3.13V 260 220 70 2.8 160 VDD = 3.47V 280 240 SNR 75 10 LTC2206-14: IVDD vs Sample Rate, fIN = 5.1MHz, -1dBFS 340 105 SFDR SNR AND SFDR (dBFS) SNR AND SFDR (dBFS) 105 LTC2206-14: SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz, -1dBFS -30 30 50 -10 10 TEMPERATURE (C) 70 90 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -50 -30 2207614 G58 -10 10 30 50 TEMPERATURE (C) 70 90 2207614 G59 220714614fd For more information www.linear.com/LTC2207-14 13 LTC2207-14/LTC2206-14 TYPICAL PERFORMANCE CHARACTERISTICS Full-Scale Settling After Wake Up from Shutdown or Starting Encode Clock 1.0 5 0.8 4 0.6 3 FULL-SCALE ERROR (%) FULL-SCALE ERROR (%) Mid-Scale Settling After Wake Up from Shutdown or Starting Encode Clock 0.4 0.2 0 -0.2 -0.4 2 1 0 -1 -2 -0.6 -3 -0.8 -4 -1.0 0 50 100 150 200 250 300 350 400 450 500 TIME AFTER WAKE-UP OR CLOCK START (s) -5 0 100 200 300 400 500 600 700 800 900 1000 TIME FROM WAKE-UP OR CLOCK START (s) 2207614 G61 2207614 G60 Pin Functions SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2F. Ceramic chip capacitors are recommended. VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin. Bypass to GND with 0.1F ceramic chip capacitors. SHDN (Pin 16): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 17): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. NC (Pins 18, 19): No Connect. GND (Pins 5, 8, 11, 15, 48): ADC Power Ground. D0-D13 (Pins 20-22, 26-28, 32-35 and 39-42): Digital Outputs. D13 is the MSB. AIN+ (Pin 6): Positive Differential Analog Input. OGND (Pins 23, 31 and 38): Output Driver Ground. AIN- (Pin 7): Negative Differential Analog Input. OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1F capacitor. ENC+ (Pin 9): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. ENC- (Pin 10): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC-. Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1F capacitor for a single-ended Encode signal. 14 CLKOUT- (Pin 29): Data Valid Output. CLKOUT- will toggle at the sample rate. Latch the data on the falling edge of CLKOUT-. CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+ will toggle at the sample rate. Latch the data on the rising edge of CLKOUT+. 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 PIN FUNCTIONS OF (Pin 43): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred. OE (Pin 44): Output Enable Pin. Low enables the digital output drivers. High puts digital outputs in Hi-Z state. MODE (Pin 45): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 46): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D13 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin 47): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.25VP-P. High selects a front-end gain of 1.5, input range of 1.5VP-P. GND (Exposed Pad, Pin 49): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. Block Diagram AIN+ AIN- VDD INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER ADC CLOCKS RANGE SELECT SENSE PGA VCM BUFFER ADC REFERENCE DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER OVDD CLKOUT+ CLKOUT- OF CONTROL LOGIC OUTPUT DRIVERS * * * VOLTAGE REFERENCE ENC+ ENC- OGND SHDN PGA RAND MODE DITH D13 D12 D1 D0 2207614 F01 OE Figure 1. Functional Block Diagram 220714614fd For more information www.linear.com/LTC2207-14 15 LTC2207-14/LTC2206-14 Operation DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = -20Log ((V22 + V32 + V42 + ... VN2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 16 If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC- voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 Applications Information CONVERTER OPERATION The LTC2207-14/LTC2206-14 are CMOS pipelined multistep converters with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven clock cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2207-14/LTC2206-14 have two phases of operation, determined by the state of the differential ENC+/ ENC- input pins. For brevity, the text will refer to ENC+ greater than ENC- as ENC high and ENC+ less than ENC- as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages oper- ate out-of-phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "input S/H" shown in the Block Diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. 220714614fd For more information www.linear.com/LTC2207-14 17 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Sample/hold operation and input drive Input Drive Impedance Sample/Hold Operation As with all high performance, high speed ADCs the dynamic performance of the LTC2207-14/LTC2206-14 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample-and-hold circuit will connect the 4.9pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. Figure 2 shows an equivalent circuit for the LTC2207-14/ LTC2206-14 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias For the best performance it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. LTC2207-14/LTC2206-14 VDD AIN+ CPARASITIC 1.8pF VDD CSAMPLE 4.9pF AIN- The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing 0.5625V for the 2.25V range (PGA = 0) or 0.375V for the 1.5V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 2) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2F capacitor or greater. CSAMPLE 4.9pF CPARASITIC 1.8pF VDD 1.6V 6k ENC+ ENC- 6k 1.6V 2207614 F02 Figure 2. Equivalent Input Circuit 18 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Input drive circuits Input Filtering A first order RC lowpass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC220714/LTC2206-14 have a very broadband S/H circuit, DC to 700MHz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended RC filter. Figures 3, 4a and 4b show three examples of input RC filtering at three ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated-this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2207-14/ LTC2206-14 do not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than flux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25V. Figure 4b shows the same circuit with components suitable for higher input frequencies. 50 VCM 2.2mF Transformer Coupled Circuits 0.1F Figure 3 shows the LTC2207-14/LTC2206-14 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50 can reduce the input bandwidth and increase 0.1F 5 AIN+ 10 ANALOG INPUT T1 1:1 25 0.1F 25 10 4.7pF 4.7pF 5 AIN- 4.7pF T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F LTC2207-14/ LTC2206-14 2207614 F04a Figure 4a. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz VCM 2.2F 50 50 5 AIN+ 10 T1 35 0.1F 10 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F 8.2pF LTC2207-14/ LTC2206-14 8.2pF 2.2F 0.1F 25 35 8.2pF 5 ANALOG INPUT 5 AIN- 0.1F T1 1:1 0.1F 25 2207614 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 150MHz VCM T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F AIN+ 2.2pF 5 2.2pF LTC2207-14/ LTC2206-14 AIN- 2207614 F04b Figure 4b. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 250MHz to 500MHz 220714614fd For more information www.linear.com/LTC2207-14 19 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. Reference Operation Figure 6 shows the LTC2207-14/LTC2206-14 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2207-14/LTC2206-14 have three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.25VP-P (PGA = 0). A 1.25V output VCM is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; it will not be stable without this capacitor. The minimum value required for stability is 2.2F. The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and is not accessible for external use. The SENSE pin can be driven 5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1F (or larger) ceramic capacitor. PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.25VP-P; PGA = 1 selects an input range of 1.5VP-P. The 2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be worse by up to approximately 2dB. See the Typical Performance Characteristics section. VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT + CM - AIN+ 25 12pF + - LTC2207-14/ LTC2206-14 2.2F AIN- 25 AMPLIFIER = LTC6600-20, LT1993, ETC. LTC2207-14/ LTC2206-14 12pF TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE RANGE SELECT AND GAIN CONTROL SENSE PGA 2.5V BANDGAP REFERENCE 2207614 F05 Figure 5. DC Coupled Input with Differential Amplifier INTERNAL ADC REFERENCE VCM BUFFER 1.25V 2.2F 2207614 F06 Figure 6. Reference Circuit 20 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION VCM 1.25V 2.2F 2 3.3V 1F SENSE 6 LT1461-2.5 LTC2207-14/ LTC2206-14 2.2F 4 2207614 F07 Figure 7. A 2.25V Range ADC with an External 2.5V Reference VDD LTC2207-14/ LTC2206-14 VDD TO INTERNAL ADC CLOCK DRIVERS 1.6V 6k ENC+ VDD 1.6V 6k ENC- 2207614 F08a Figure 8a. Equivalent Encode Input Circuit 0.1F ENC+ T1 50 8.2pF 0.1F 100 LTC2207-14/ LTC2206-14 50 0.1F ENC- 2207614 F08b T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 8b. Transformer Driven Encode 220714614fd For more information www.linear.com/LTC2207-14 21 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION ENC+ VTHRESHOLD = 1.6V 1.6V ENC- LTC2207-14/ LTC2206-14 0.1F 2207614 F09 Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V Q0 D0 ENC+ LTC2207-14/ ENC- LTC2206-14 Q0 2207614 F10 Figure 10. ENC Drive Using a CMOS to PECL Translator 22 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Driving the Encode Inputs Maximum and Minimum Encode Rates The noise performance of the LTC2207-14/LTC2206-14 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. The maximum encode rate for the LTC2207-14 is 105Msps. The maximum encode rate for the LTC2206-14 is 80Msps. For the ADC to operate properly the encode signal should have a 50% (5%) duty cycle. Each half cycle must be at least 4.52ns for the LTC2207-14 internal circuitry to have enough settling time for proper operation. For the LTC220614, each half cycle must be at least 5.94ns. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.4V to 3V. Each input may be driven from ground to VDD for single-ended drive. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2207-14/LTC2206-14 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2207-14/LTC2206-14 is 1Msps. 220714614fd For more information www.linear.com/LTC2207-14 23 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Digital outputs Table 1. MODE Pin Function Digital Output Buffers Figure 11 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2207-14/LTC2206-14 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the output buffer has a series resistor of 33 on chip. MODE Output Format Clock Duty Cycle Stabilizer 0(GND) Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2's Complement On VDD 2's Complement Off Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. A logic high on the OF pin indicates an overflow or underflow. Output Clock The ADC has a delayed version of the encode input available as a digital output. Both a noninverted version, CLKOUT+ and an inverted version CLKOUT- are provided. The CLKOUT+/CLKOUT- can be used to synchronize the Lower OVDD voltages will also help reduce interference from the digital outputs. LTC2207-14/LTC2206-14 Data Format OF The LTC2207-14/LTC2206-14 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the MODE pin. LTC2207-14/LTC2206-14 VDD OF D13 D13/D0 D12 D2 OVDD CLKOUT+ CLKOUT D12/D0 * * * D2/D0 0.5V TO 3.6V VDD 0.1F D1 D1/D0 OVDD DATA FROM LATCH PREDRIVER LOGIC 33 TYPICAL DATA OUTPUT OGND RAND = HIGH, SCRAMBLE ENABLED RAND D0 2207614 F12 2207614 F11 Figure 11. Equivalent Circuit for a Digital Output Buffer 24 D0 Figure 12. Functional Equivalent of Digital Output Randomizer 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION converter data to the digital system. This is necessary when using a sinusoidal encode. Data can be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT-. CLKOUT+ falls and CLKOUT- rises as the data outputs are updated. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is "Randomized" by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output Randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the VDD of the ADC. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Internal Dither The LTC2207-14/LTC2206-14 are 14-bit ADCs with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. PC BOARD CLKOUT FPGA OF D13/D0 D13 LTC2207-14/ LTC2206-14 D12/D0 D12 D2/D0 * * * D2 D1/D0 D1 D0 D0 2207614 F13 Figure 13. Descrambling a Scrambled Digital Output For more information www.linear.com/LTC2207-14 220714614fd 25 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION LTC2207-14/LTC2206-14 AIN+ ANALOG INPUT AIN- 14-BIT PIPELINED ADC CORE S/H AMP CLOCK/DUTY CYCLE CONTROL ENC + DIGITAL SUMMATION OUTPUT DRIVERS CLKOUT OF D13 * * * D0 MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR PRECISION DAC ENC - DITH 2207614 F14 DITHER ENABLE HIGH = DITHER ON, LOW = DITHER OFF Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit As shown in Figure 14, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off. Grounding and Bypassing The LTC2207-14/LTC2206-14 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2207-14/LTC2206-14 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In 26 particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2207-14/LTC2206-14 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2207-14/LTC220614 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible. 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Silkscreen Top Top Side 220714614fd For more information www.linear.com/LTC2207-14 27 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Inner Layer 2 Inner Layer 3 Inner Layer 4 28 Inner Layer 5 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION Bottom Side Silkscreen Bottom For more information www.linear.com/LTC2207-14 220714614fd 29 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION RANDOMIZER (REQUIRES CHANGE IN SELECTED DEVICE IN PSCOPE) 0V 3.3V NOT PROVIDED BY DC718 JUMPERS ARE SHOWN IN DEFAULT POSITIONS CLOCK POLARITY PGA SENSE CLOCK OUT MSB DIGITAL OUTPUTS TO DC718 (2.5V CMOS) ANALOG INPUT (50) LSB ENABLE DITHER ENC CLOCK INPUT (50) 22076 DC918C SHUTDOWN Ordering Guide: DEMO BOARD NUMBER PART NUMBER RESOLUTION SPEED INPUT FREQUENCY USB I/F BOARD DC918C-A LTC2207CUK 16-Bit 105Msps 1MHz to 70MHz DC718 DC918C-B LTC2207CUK 16-Bit 105Msps 70MHz to 140MHz DC718 DC918C-C LTC2206CUK 16-Bit 80Msps 1MHz to 70MHz DC718 DC918C-D LTC2206CUK 16-Bit 80Msps 70MHz to 140MHz DC718 DC918C-E LTC2205CUK 16-Bit 65Msps 1MHz to 70MHz DC718 DC918C-F LTC2205CUK 16-Bit 65Msps 70MHz to 140MHz DC718 DC918C-G LTC2204CUK 16-Bit 40Msps 1MHz to 70MHz DC718 DC918C-H LTC2207CUK-14 14-Bit 105Msps 1MHz to 70MHz DC718 DC918C-I LTC2207CUK-14 14-Bit 105Msps 70MHz to 140MHz DC718 DC918C-J LTC2206CUK-14 14-Bit 80Msps 1MHz to 70MHz DC718 DC918C-K LTC2206CUK-14 14-Bit 80Msps 70MHz to 140MHz DC718 DC918C-L LTC2205CUK-14 14-Bit 65Msps 1MHz to 70MHz DC718 See Web site for ordering details or contact local sales. 30 220714614fd For more information www.linear.com/LTC2207-14 For more information www.linear.com/LTC2207-14 C30 0.01F C10 0.01F R31 * ASSEMBLY TYPE DC918C-A DC918C-B DC918C-C DC918C-D DC918C-E DC918C-F DC918C-G DC918C-H DC918C-I DC918C-J DC918C-K DC918C-L 5 4 T2 1 2 U1 LTC2207CUK LTC2207CUK LTC2206CUK LTC2206CUK LTC2205CUK LTC2205CUK LTC2204CUK LTC2207CUK-14 LTC2207CUK-14 LTC2206CUK-14 LTC2206CUK-14 LTC2205CUK-14 R9 10 C5 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF C15 0.1F R28 49.9 R27 49.9 C5 * R26 5.1 C7, C28 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF C16 0.1F R29 5.1 1 R30 86.6 182 86.6 182 86.6 182 86.6 86.6 182 86.6 182 86.6 R1 10k SENSE VCM VDD VDD GND AIN+ 3 VDD R6 OPEN R2 10k R3 1k R7 1k R4 OPEN OVP GND 1 3 2 U1* 2 2 1 3 GND VDD JP6 DITH + 36 35 34 33 32 31 30 29 CLKOUT- 28 D7 27 D6 26 D5 25 OVDD OVDD D11 D10 D9 D8 OGND CLKOUT+ INPUT FREQUENCY BITS Msps 16 105 1MHz < AIN < 70MHz 105 70MHz < AIN < 140MHz 16 16 80 1MHz < AIN < 70MHz 80 70MHz < AIN < 140MHz 16 16 65 1MHz < AIN < 70MHz 65 70MHz < AIN < 140MHz 16 16 40 1MHz < AIN < 70MHz 14 105 1MHz < AIN < 70MHz 105 70MHz < AIN < 140MHz 14 14 80 1MHz < AIN < 70MHz 80 70MHz < AIN < 140MHz 14 14 65 1MHz < AIN < 70MHz 1 JP5 3 SHDN GND VDD R21, 10k R20 10k 7 AIN- 8 GND 9 ENC+ 10 ENC- 11 GND 12 VDD 1 2 3 4 5 6 C2 2.2F L1 56nH 18nH 56nH 18nH 56nH 18nH 56nH 56nH 18nH 56nH 18nH 56nH 3 JP3 1 JP4 1 PGA RAND 2 2 VDD VDD GND GND OPEN VDD R31, R32 86.6 43.2 86.6 43.2 86.6 43.2 86.6 86.6 43.2 86.6 43.2 86.6 C17 0.1F R33 100 R10 10 R14 10 C11 8.2pF C3 0.01F C8 2.2F R8 100 R13 10 R12 33.2 R11 3 33.2 T3 MABAES0060 WBC1-1L MABAES0060 WBC1-1L MABAES0060 WBC1-1L MABAES0060 MABAES0060 WBC1-1L MABAES0060 WBC1-1L MABAES0060 C12 0.01F C9 0.01F 1 1 5 C6 0.01F 3 R32 * 5 2 2 T1 MABA007159000000 4 3 4*T3 MABA-007159000000 C7 * * L1 * VERSION TABLE J3 ENCODE INPUT C28 * C4 0.01F J2 ANALOG INPUT * R30 2 JP2 SHDN GND 48 PGA 47 RAND 46 MODE 45 OE 44 3 JP1 DD OF 43 D15 42 D14 41 D13 40 D12 39 OGND 38 37 OV 13 VDD 14 VDD 15 GND 16 SHDN 17 DITH 18 D0 19 D1 20 D2 21 D3 22 D4 23 OGND OVDD 24 VDD C27 100F 6.3V OPT. C1 0.1F 2 1 E4 E3 11 12 13 14 15 16 17 18 19 11 12 13 14 15 16 17 18 19 A7 A6 A5 A4 A3 A2 A1 A0 T/R GND VCC 20 OVP A7 A6 A5 A4 A3 A2 A1 A0 T/R GND VCC 20 OVP 4 5 C22 1F R25 1 U7 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 10 C14 0.1F LT1763 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 RN1A RN1B RN1C RN1D RN2A RN2B RN2C RN2D RN3A RN3B RN3C RN3D RN4A RN4B RN4C RN4D OVP 1 A0 2 A1 3 A2 4 A3 R23 100k R22 105k VCC 8 WP 7 6 SCL 5 SDA C20 10F 6.3V R17 10k 33 R5 U6 24LC025 C21, 0.01F 1 IN OUT 2 7 GND ADJ 3 6 GND GND 4 5 SHDN BYP 8 1 2 74VCX245BQX B7 B6 B5 B4 B3 B2 B1 B0 OE U2 74VCX245BQX B7 B6 B5 B4 B3 B2 B1 B0 OE U2 C19 3 U5 0.1F NC7SV86P5X VDD VDD 3.3V 4 U4 NC7SV86P5X E1 C23 4.7F GND C18 0.1F VDD 3 5 OVP 2 4 6 8 20 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 20 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C25 0.1F OVP R19 10k C13 0.1F 2207614 F15 C26 0.1F 3201S-40G1 OGND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J1 R18 10k 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 LTC2207-14/LTC2206-14 APPLICATIONS INFORMATION 31 220714614fd LTC2207-14/LTC2206-14 Package Description Please refer to http://www.linear.com/product/LTC2207-14#packaging for the most recent package drawings. UK Package 48-Lead Plastic QFN (7mm x 7mm) (Reference LTC DWG # 05-08-1704 Rev C) 0.70 0.05 5.15 0.05 5.50 REF 6.10 0.05 7.50 0.05 (4 SIDES) 5.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 47 48 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 CHAMFER C = 0.35 5.50 REF (4-SIDES) 5.15 0.10 5.15 0.10 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 32 (UK48) QFN 0406 REV C 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 220714614fd For more information www.linear.com/LTC2207-14 LTC2207-14/LTC2206-14 Revision History (Revision history begins at Rev D) REV DATE DESCRIPTION D 01/16 Updated Pin Configuration. PAGE NUMBER 2 220714614fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation as described herein will not infringe on existing patent rights. that the interconnection of its circuits For more information www.linear.com/LTC2207-14 33 LTC2207-14/LTC2206-14 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1747 12-Bit, 80Msps ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: -94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN LTC2205 16-Bit, 65Msps, 3.3V ADC 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm x 9mm QFN Package LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN LTC2249 14-Bit, 80Msps ADC 230mW, 73dB SNR, 5mm x 5mm QFN Package LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm x 5mm QFN Package LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm x 5mm QFN Package LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm x 5mm QFN Package LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm x 5mm QFN Package LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm x 5mm QFN Package LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN LTC2299 Dual 14-Bit, 80Msps ADC 230mW, 71.6dB SNR, 5mm x 5mm QFN Package LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 450 MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step LT5515 1.5 GHz to 2.5GHz Direct Conversion Quadrature High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator Demodulator LT5516 800MHz to 1.5GHz Direct Conversion Quadrature High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator Demodulator LT5517 40MHz to 900MHz Direct Conversion Quadrature High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator Demodulator LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 34 Linear Technology Corporation 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2207-14 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2207-14 220714614fd LT 0116 REV D * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2006