Features
•High Pe rformance, Low Power Atmel® AVR® 8-Bit Microcontroller
•Advanced RISC Architecture
– 130 Po we rful Instructions – Most Single Cloc k Cycle Execu t io n
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Thro ug hp ut at 16 MHz
– On-Chip 2-c y cle Multiplier
•High Endurance Non-volatile Memory segments
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While -Wri te Operation
– Programming Lock for Software Security
•JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•Peripheral Features
– 4 × 25 Segment LCD Driver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
•Special Microcontroller Features
– Power -on Reset and Pr ogrammab le Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Red uction, Power-save, Power-down, and
Standby
•I/O and Packages
– 54 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
•Speed Grade:
– ATmega169PV: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 8 MHz @ 2.7V - 5.5V
– ATmega169P: 0 - 8 MHz @ 2.7V - 5.5V, 0 - 16 MHz @ 4.5V - 5.5V
•Tempe rature range:
–-40°C to 85°C Industrial
•Ultra-Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 330 µA
32 kHz, 1.8V: 10 µA (including Oscillator)
32 kHz, 1.8V: 25 µA (including Oscillator and LCD)
– Power-down Mode:
0.1 µA at 1.8V
– Power-save Mode:
0.6 µA at 1.8V (Including 32 kHz RTC)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega169P
ATmega169PV
Preliminary
Rev. 8018P–AVR–08/10
2
8018P–AVR–08/10
ATmega169P
1. Pin Configurations
1.1 Pinout - TQFP/QFN/MLF
Figure 1-1. 64A (TQFP) and 64M1 (Q FN/MLF) Pinout ATmega169P
Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol-
dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen
from the board.
64
63
62
47
46
48
45
44
43
42
41
40
39
38
37
36
35
33
34
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16
15
17
61
60
18
59
20
58
19
21
57
22
56
23
55
24
54
25
53
26
52
27
51
29
28
50
49
32
31
30
PC0 (SEG12)
VCC
GND
PF0 (ADC0)
PF7 (ADC7/TDI)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
AREF
GND
AVCC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
LCDCAP
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC2A/PCINT15) PB7
(T1/SEG24) PG3
(OC1B/PCINT14) PB6
(T0/SEG23) PG4
(OC1A/PCINT13) PB5
PC1 (SEG11)
PG0 (SEG14)
(SEG15) PD7
PC2 (SEG10)
PC3 (SEG9)
PC4 (SEG8)
PC5 (SEG7)
PC6 (SEG6)
PC7 (SEG5)
PA7 (SEG3)
PG2 (SEG4)
PA6 (SEG2)
PA5 (SEG1)
PA4 (SEG0)
PA3 (COM3)
PA0 (COM0)
PA1 (COM1)
PA2 (COM2)
PG1 (SEG13)
(SEG16) PD6
(SEG17) PD5
(SEG18) PD4
(SEG19) PD3
(SEG20) PD2
(INT0/SEG21) PD1
(ICP1/SEG22) PD0
(TOSC1) XTAL1
(TOSC2) XTAL2
RESET/PG5
GND
VCC
INDEX CORNER
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8018P–AVR–08/10
ATmega169P
1.2 Pinout - DRQFN
Figure 1-2. 64MC (DRQFN) Pinout ATmega169P
Top view Bottom view
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A9
B8
A10
B9
A11
B10
A12
B11
A13
B12
A14
B13
A15
B14
A16
B15
A17
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A34
B30
A33
B29
A32
B28
A31
B27
A30
B26
A29
B25
A28
B24
A27
B23
A26
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A17
B15
A16
B14
A15
B13
A14
B12
A13
B11
A12
B10
A11
B9
A10
B8
A9
A26
B23
A27
B24
A28
B25
A29
B26
A30
B27
A31
B28
A32
B29
A33
B30
A34
Table 1-1. DRQFN-64 Pinout ATmega169P.
A1 PE0 A9 PB7 A18 PG1 (SEG13) A26 PA2 (COM2)
B1 VLCDCAP B8 PB6 B16 PG0 (SEG14) B23 PA3 (COM3)
A2 PE1 A10 PG3 A19 PC0 (SEG12) A27 PA1 (COM1)
B2 PE2 B9 PG4 B17 PC1 (SEG11) B24 PA0 (COM0)
A3 PE3 A11 RESET A20 PC2 (SEG10) A28 VCC
B3 PE4 B10 VCC B18 PC3 (SEG9) B25 GND
A4 PE5 A12 GND A21 PC4 (SEG8) A29 PF7
B4 PE6 B11 XTAL2 (TOSC2) B19 PC5 (SEG7) B26 PF6
A5 PE7 A13 XTAL1 (TOSC1) A22 PC6 (SEG6) A30 PF5
B5 PB0 B12 PD0 (SEG22) B20 PC7 (SEG5) B27 PF4
A6 PB1 A14 PD1 (SEG21) A23 PG2 (SEG4) A31 PF3
B6 PB2 B13 PD2 (SEG20) B21 PA7 (SEG3) B28 PF2
A7 PB3 A15 PD3 (SEG19) A24 PA6 (SEG2) A32 PF1
B7 PB5 B14 PD4 (SEG18) B22 PA4 (SEG0) B29 PF0
A8 PB4 A16 PD5 (SEG17) A25 PA5 (SEG1) A33 AREF
B15 PD7 (SEG15) B30 AVCC
A17 PD6 (SEG16) A34 GND
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8018P–AVR–08/10
ATmega169P
2. Overview
The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut-
ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to op timize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORTA
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORTA
DATA REGISTER
PORTD
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI
USART
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PORTE DRIVERS
PORTA DRIVERS
PORTF DRIVERS
PORTD DRIVERS
PORTC DRIVERS
PB0 - PB7PE0 - PE7
PA0 - PA7PF0 - PF7
VCC
GND
AREF
XTAL1
XTAL2
CONTROL
LINES
+
-
ANALOG
COMPARATOR
PC0 - PC7
8-BIT DATA BUS
RESET
AVCC CALIB. OSC
DATA DIR.
REG. PORTC
DATA REGISTER
PORTC
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARY-
SCAN
DATA DIR.
REG. PORTF
DATA REGISTER
PORTF
ADC
PD0 - PD7
DATA DIR.
REG. PORTG
DATA REG.
PORTG
PORTG DRIVERS
PG0 - PG4
UNIVERSAL
SERIAL INTERFACE
AVR CPU
LCD
CONTROLLER/
DRIVER
5
8018P–AVR–08/10
ATmega169P
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achiev ing throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega169P provides the following features: 16 Kbytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip
Debugging support and programming, a comp lete On-chip LCD controller with internal step-up
voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a
serial programmable USART, Universal Serial Interface with Star t Condition Detect or, an 8-
channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer and the LCD contr oller continues to run, allowing th e user to maintain a timer b ase and
operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleepin g. This allows very fast start-up com-
bined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8 -bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, t he At mel ATmega1 69 P is a po we rful microcontroller that provides a hig hly flex-
ible and cost effective solut ion to many embedded control applications.
The ATmega169P AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluatio n kits.
6
8018P–AVR–08/10
ATmega169P
2.2 Pin Descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3 Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega 169P as listed on
”Alternate Functions of Port A” on page 73 .
2.2.4 Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega 169P as listed on
”Alternate Functions of Port B” on page 74 .
2.2.5 Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both hig h sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega169P as listed on ”Alternate
Functions of Port C” on page 77.
2.2.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both hig h sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special feature s of the ATmega169P as listed on
”Alternate Functions of Port D” on page 79.
7
8018P–AVR–08/10
ATmega169P
2.2.7 Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port E pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega 169P as listed on
”Alternate Functions of Port E” on page 81 .
2.2.8 Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors ( selecte d for each bi t). The Por t F outpu t buffe rs have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tr i-stated when a reset co ndition becomes active, even if the cloc k is not runnin g. If th e
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated eve n if a reset occurs.
Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on
page 83.
2.2.9 Port G (PG5:PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the ATmega169P as listed on
page 85.
2.2.10 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gen erate a
reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page
333. Shorter pulses are no t gu ar a nte e d to gen er at e a re se t.
2.2.11 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.12 XTAL2
Output from the inverting Oscillator amplifier.
2.2.13 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
8
8018P–AVR–08/10
ATmega169P
2.2.14 AREF
This is the analog reference pin for the A/D Converter.
2.2.15 LCDCAP
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-
ure 23-2 on page 236. This capacitor acts as a reservoir for LCD power (VLCD). A large
capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value.
9
8018P–AVR–08/10
ATmega169P
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note: 1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
10
8018P–AVR–08/10
ATmega169P
5. About Code Examples
This documentatio n contains simple co de examples that br iefly sh ow how to u se various parts of
the device. Be aware th at not all C compiler vendors include bit def initions in the header files
and interrupt ha ndlin g in C is com piler d epe nd ent. Please con firm wit h the C com piler d ocume n-
tation for more details.
These code ex amples assume that the part specific he ader file is included before compilation.
For I/O registers located in extended I/O map, "I N", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
11
8018P–AVR–08/10
ATmega169P
6. AVR CP U Core
6.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
6.2 Architectural Overview
Figure 6-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism , the AVR uses a Harvard architecture – with
separate memories and buses for progr am and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
12
8018P–AVR–08/10
ATmega169P
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficien t address calculations. One of the these addre ss pointers
can also be used as an address pointer for loo k up tables in Flash prog ram memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single regi ster operation s can also be executed in th e ALU. After an ar ithmetic opera-
tion, the Stat us Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat. Every program memory address contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts an d subroutine calls, the retur n address Program Count er (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O fun ctions. The I/O Memory can be access ed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega169P
has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
6.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or betwee n a re gister an d an immedi ate ar e execut ed . The ALU ope ra tio ns are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
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8018P–AVR–08/10
ATmega169P
6.4 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. Note that the Stack is implemented as
growing from higher to lower memory locations. The Stack Pointer Register always points to the
top of the Stack. The Stack Pointer points to the data SRAM Stac k area where the Subroutine
and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be define d by the program before any subroutine calls ar e
executed or interrupts are enabled. Initial Stack Pointer value equals the last add ress of the
internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure
7-2 on page 21.
See Table 6- 1 for Stack Pointer details.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Table 6-1. Stack Pointer instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
POP Incremented by 1 Data is popped from the stack
RET
RETI Incremented by 2 Return address is popped from the stack with return from
subroutine or return from interrupt
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8018P–AVR–08/10
ATmega169P
6.4.1 SPH and SPL – Stack Pointer
6.5 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generate d f rom th e selected clo ck source f or the
chip. No internal clock division is used.
Figure 6- 2 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-2. The Parallel Instruction Fetches and Instruction Executions
Figure 6-3 shows the int ernal timi ng con cept for th e Regi ster File . In a single clock cycl e an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-3. Single Cycle ALU Operation
Bit 151413121110 9 8
0x3E (0x5E) – – – – – SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
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6.6 Reset and Interrupt Handling
The AVR provides several different inte rrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be wr itten logic one to gether with th e Global Inter rupt
Enable bit in the Status Register in orde r to enable the interrupt. Depending on the Program
Counter value, interrupts ma y be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section ”Memory Program-
ming” on page 296 for details.
The lowest addresses in the progra m memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 56. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interru pt Vectors can be moved t o the star t of the Bo ot Flash sect ion by setti ng the IVSEL
bit in the MCU Control Register (MCUCR). Refer to ”Interrupt s” on page 56 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page
280.
When an interrupt occurs, th e Global Interrupt Enable I-bit is cleared and all interrup ts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is au tomatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit posi tion(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. The se
interrupts do not nece ssarily have I nterrupt Fla gs. If t he interr upt condit ion disappear s before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The f ollowing e xa mple sho ws how this can be used to a void interrupts during the
timed EEPROM write sequence.
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
6.6.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clo ck cycles t he pr og ram vect or add ress fo r t he actua l interr up t ha nd ling rout ine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is in creased by fo ur clock cycles. This incre ase comes in additi on to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and t he I-bit in SREG is set.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
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6.7 Status Register
The Status Regist er conta ins infor mation a bout the result of th e most recently e xecuted ari thme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the I nstru ction Se t Re ference. This will in many case s re move the n eed f or using t he
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an inte rr up t. T his mu st be ha nd le d by so ftw ar e.
6.7.1 SREG – AVR Status Register
The SREG is defined as:
• Bit 7 – I: Globa l Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See t he “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or betwee n the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
Bit 76543210
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
6.8 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruc tion set. In order t o achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit outpu t operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 6-4 shows the structure of the 32 general pur pose working registers in the CPU.
Figure 6-4. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 6-4, each register is also assigned a data me mory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memo ry organization provides great fle xibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-regist er Low Byte
R29 0x1D Y-regist er High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
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6.8.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect ad dressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 6- 5.
Figure 6-5. The X-, Y-, and Z-registers
In the differ ent a ddr essing modes the se ad dr ess regist er s have fun cti ons a s fi xed d isp lacement ,
automatic increment, and automatic decrement (see the instruction set reference for details).
15 XH XL 0
X-register 707 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 707 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7070
R31 (0x1F) R30 (0x1E)
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7. AVR Memories
This section describes the different memories in the ATmega169P. The AVR architecture has
two main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega169P features an EEPROM Memory for data storage. All three memory spaces are lin-
ear and regular.
7.1 In-System Reprogrammable Flash Program Memory
The ATmega169P contains 16 Kbytes On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K
× 16. For software security, the Flash Program memory space is divided into two sections, Boot
Program section and Appli cation Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega169P
Program Counter (PC) is 13 bits wide, thus addressing the 8K program memory locations. The
operation of Boot Program section and associa ted Boot Lock bits for software protection are
described in detail in ”Boot Loader Support – Rea d-While-Write Self-Programming” on pag e
280. ”Memory Programming” on page 296 contains a detailed description on Flash data serial
downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-
ing” on page 14.
Figure 7-1. Program Memory Map
0x0000
0x1FFF
Program Memory
Application Flash Section
Boot Flash Section
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7.2 SRAM Data Memory
Figure 7-2 shows how the ATmega169P SRAM Memory is organized.
The ATmega169P is a complex microcontroller with more peripheral units than can be sup-
ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/ STD and LD/LDS/LDD instruc-
tions can be used.
The lower 1,280 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 1024 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacemen t mode reaches 63 add ress locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 1,024 bytes of internal data SRAM in the ATmega169 P are all accessible through all these
addressing modes. The Register File is described in ”General Purpose Register File” on page
18.
Figure 7-2. Data Memory Map
32 Registers
64 I/O Registers
Internal SRAM
(1024 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x04FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
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7.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figur e 7-3.
Figure 7-3. On-chip Data SRAM Access Cycles
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7.3 EEPROM Data Memory
The ATmega169P contains 512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. This section describes the access between the EEPROM and
the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
”Serial Downloading” on page 310, ”Programming via the JTAG Interface” on page 316, and
”Parallel Programming Parameters, Pin Mapping, and Commands” on page 299 respectively.
7.3.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 7-1 on page 24. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, so me precautions must be taken. In heavily filtered
power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See ”Preventing EEPROM Corruption” on page 27 for details on how to avoid proble ms in
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
The following procedure should be followed when writing the EEPROM (the order of steps 3 and
4 is not essential). See ”EEPROM Register Description” on page 28 for supplementary descrip-
tion for each register bit:
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, wr ite a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If t he F l as h is n e ve r b ein g up da te d by the CPU, step 2 can be omitted. See ”Boot Loader
Support – Read-While-Write Self-Programming” on page 280 for details about Boot
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
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When the write access time has elapsed , the EEWE bit is cleared by hardware. The user soft-
ware can poll this bit a nd wait f or a zero bef ore wr iting th e next byte. When EEWE has b een set,
the CPU is halted for two cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM access es. Table 7-1 lists the ty pical pro-
gramming time for EEPROM access from the CPU.
Table 7-1. EEPROM Programming Time
Symbol Number of Calibrated
RC Oscillator Cycles Typical Programming Time
EEPROM write (from CPU) 27 072 3.3 ms
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The following code examples show one assembly and one C function for writing to the
EEPROM. To avoid that interrupts will occur during execution of these functions, the examples
assume that interrupts are controlled (for example by disabling interrupts globally). The exam-
ples also assume that no Flash Boot Loader is present in the software. If such code is present,
the EEPROM write function must also wait for any ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
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The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functio ns.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
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7.3.2 EEPROM Write During Power-down Sleep Mode
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the clock continues running, and as a
consequence, the device does not enter Power-down entirely. It is therefore recommended to
verify that the EEPROM write operation is completed before entering Power-down.
7.3.3 Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be co rrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues a re the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write seque nce to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly , if the su pp ly voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match th e needed d etection le vel, an e xternal low VCC reset Protection circuit can
be used. If a reset occurs while a write operation is in progress , the write operation will be com-
pleted provided that the power supply voltage is sufficient.
7.4 I/O Memory
The I/O space definition of the ATmega169P is shown in ”Register Summary” on page 373.
All ATmega169P I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/L DS/LDD and ST/STS/STD in structions, transferring dat a between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these re giste rs, the
value of single bits can b e checked b y using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instruct ions, 0x20 must be ad ded to these addresse s. The ATmega169P is a com -
plex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Exten ded I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
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7.5 General Purpose I/O Registers
The ATmega169P contains three General Purpose I/O Registers. These registers can be used
for storing any information, and they are particularly useful for storing global variables and Sta-
tus Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-
accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.5.1 GPIOR2 – Ge n era l Purpo se I/O Re gi st er 2
7.5.2 GPIOR1 – Ge n era l Purpo se I/O Re gi st er 1
7.5.3 GPIOR0 – Ge n era l Purpo se I/O Re gi st er 0
7.6 EEPROM Register Description
7.6.1 EEARH and EEARL – EEPROM Address Register
• Bits 15:9 – Res: Reserved Bits
These bits are reserve d and will always read as zero.
• Bits 8:0 – EEAR8:0 : EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
Bit 76543210
0x2B (0x4B) MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x2A (0x4A) MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x1E (0x3E) MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 151413121110 9 8
0x22 (0x42) –––––––EEAR8EEARH
0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543210
Read/Write RRRRRRRR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 X
XXXXXXXX
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7.6.2 EEDR – EEPROM Data Register
• Bits 7:0 – EEDR7:0 : EEPROM Data
For the EEPROM write oper ation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
7.6.3 EECR – EEPROM Control Register
• Bits 7..4 – Res: Reserved Bits
These bits are reserve d and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are c orrectly set up, the EEWE bit must be written to one to write the value in to the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
erwise no EEPROM write takes place.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is se t up in t he EEAR Regist er, the EERE bit must be writ ten to a log ic one to trigge r the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
Bit 76543210
0x20 (0x40) MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x1F (0x3F) – – – – EERIE EEMWE EEWE EERE EECR
Read/Write RRRRR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 X 0
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8. System Clock and Clock Options
8.1 Clock Systems and their Distribution
Figure 8-1 presents the principal clock systems in the AVR and th eir distribution . All of th e clocks
need not be active at a given time . In order to red uce power co nsumption, the clo cks to modu les
not being used can be halted by using different sleep modes, as described in ”Power Manage-
ment and Sleep Modes” on page 40. The clock systems are detailed below.
Figure 8-1. Clock Distribution
8.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
8.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detecte d by asynchronous logic, allowing such interrupts to be detected even if t he I/O
clock is halted. Also no te that start co ndition det ection in th e USI module is carried out asynchro-
nously when clkI/O is halted, enabling USI start condition detection in all sleep modes.
8.1.3 Flash Clock – clkFLASH
The Flash clock controls o peration of t he Flash in terface. Th e Flash clock is usually active simul-
taneously with the CPU clock.
General I/O
Modules
Asynchronous
Timer/Counter CPU Core RAM
clk
I/O
clk
ASY
AVR Clock
Control Unit clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Timer/Counter
Oscillator Crystal
Oscillator Low-frequency
Crystal Oscillator
External Clock
LCD Controller
System Clock
Prescaler
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8.1.4 Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller
to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated
clock domain allows using this Timer/Counter as a real-time counter even when the device is in
sleep mode. It also allows the LCD controller output to continue while the rest of the device is in
sleep mode.
8.1.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to re duce noise ge ner ated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion
results.
8.2 Clock Sources
The device has the follo wing clock source options, selectable by Flash Fuse bits as shown
below. The cloc k fr om t he se lected so ur ce is i npu t t o th e AVR clo c k gene ra to r, an d rou te d t o the
appropriate modules.
Note: 1. F or all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before com-
mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the
start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 8-
2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Charac-
teristics” on page 338.
Table 8-1. Device Clocking Options Select(1)
Device Clocking Option CKSEL3:0
External Crystal/Ceramic Resonator 1111 - 1000
External Low-frequency Crystal 0111 - 0110
Calibrated Internal RC Oscillator 0010
Exter nal Clock 0000
Reserved 0011, 0001, 0101, 0100
Table 8-2. Number of Watchdog Oscillator Cycles
Ty p Time-out (VCC = 5.0V) Ty p Time-out (VCC = 3.0V) Number of Cycles
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 64K (65,536)
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8.3 Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 progra mmed. The default
clock source setting is the Internal RC Oscillator with longest start-up time and an initial system
clock presca ling of 8. This defa ult setting ensure s that all users ca n make their des ired clock
source setting using an In-System or Parallel programmer.
8.4 Calibrated Internal RC Oscillator
B default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and
temperature dep endent, th is clock can be very accurately ca librated by the user. See Ta ble 28-2
on page 332 and ”Internal Oscillator Speed” on page 365 for more details. Th e device is shipped
with the CKDIV8 Fuse program med . See ”System Clock Prescaler” on page 37 for more details.
This clock may be sele ct ed as th e s ystem c loc k by p ro gram m in g th e CKS E L F us es as sh own in
Table 8-3. If selected, it will operate with no external components. During reset, hardware loads
the pre-progr ammed calibration value into the O SCCAL Register and thereby auto matically cali-
brates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table
28-2 on page 332.
By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on
page 38, it is possible to get a higher calibration accuracy than by using the factory calibration.
The accuracy of th is calibration is shown as User calibration in Table 28-2 on page 332.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the
Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-
bration value, see the section ”Calibration Byte” on page 299.
Notes: 1. The device is shipped with this option selected.
2. The frequency ranges are preliminary values. Actual values are TBD.
3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8
Fuse can be programmed in order to divide the internal frequency by 8.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 8-4.
Note: 1. The device is shipped with this option selected.
Table 8-3. Internal Calibrated RC Oscillator Operating Modes(1)(3)
Frequency Range(2) (MHz) CKSEL3:0
7.3 - 8.1 0010
Table 8-4. Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions Start-up Time from Power-
down and Power-save Additional Delay from
Reset (VCC = 5.0V) SUT1:0
BOD enabled 6 CK 14CK 00
Fast rising po wer 6 CK 14CK + 4.1 ms 01
Slowly rising power 6 CK 14CK + 65 ms(1) 10
Reserved 11
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8.5 Crystal Oscillator
XTAL1 and XTAL2 are input and output , respectively, of an inver ting amplifier which ca n be con-
figured for use as an O n-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a
ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optim al value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 8-5. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Figure 8-2. Crystal Oscillator Connections
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 8-5.
Notes: 1. This option should not be used with crystals, only with ceramic resonators.
Table 8-5. Crystal Oscillator Operating Modes
CKSEL3:1 Frequency Range (MHz) Recommended Range for Capacitors C1 and
C2 for Use with Crystals (pF)
100(1) 0.4 - 0.9 –
101 0.9 - 3.0 12 - 22
110 3.0 - 8.0 12 - 22
111 8.0 - 12 - 22
XTAL2 (TOSC2)
XTAL1 (TOSC1)
GND
C2
C1
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The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
8-6.
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application . These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
8.6 Low-frequency Crystal Oscillator
The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal.
When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR
must be taken into consideration. Both values are specified by the crystal vendor. ATmega169P
oscillator is optimized for ve ry low power consumption, and thus when selecting crystals, see
Table 8-7 for maximum ESR recommendat ions on 9 pF and 6.5 pF crystals.
Table 8-7. Maximum ESR Recommendation for 32.768 kHz Watch Crystal
Note: 1. Maximum ESR is typical value based on characterization
The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 8-8 on
page 35 at each TOSC pin.
Table 8-6. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0 SUT1:0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
0 00 258 CK(1) 14CK + 4.1 ms Ceramic resonator, fast
rising power
0 01 258 CK(1) 14CK + 65 ms Ceramic resonator , slowly
rising power
010 1K CK
(2) 14CK Ceramic resonator, BOD
enabled
011 1K CK
(2) 14CK + 4.1 ms Ceramic resonator, fast
rising power
100 1K CK
(2) 14CK + 65 ms Ceramic resonator , slowly
rising power
1 01 16K CK 14CK Crystal Oscillator , BOD
enabled
1 10 16K CK 14CK + 4.1 ms Crystal Oscillator , fast
rising power
1 11 16K CK 14CK + 65 ms Crystal Oscillator, slowly
rising power
Crystal CL (pF) Max ESR [kΩ](1)
6.5 60
935
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The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using:
where
Ce - is optional external capacitors as described in Figure 8-2 on page 33.
Ci - is is the pin capacitance in Table 8-8.
CL - is the load capacitance for a 32.768 kHz crystal specified by the crystal vendor.
CS - is the total stray capacitance for one TOSC pin.
Crystals specifying load capacitance (CL) higher than the ones given in the Table 8 -8, require
external capacitors applied as described in Figure 8-2 on page 33.
The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or
“0111” as shown in Table 8-10. Start-up times are determined by the SUT Fuses as shown in
Table 8-9.
Note: 1. This option should only be used if frequ ency stability at start-up is not important for the
application
Table 8-8. Capacitance for Low-Frequency Crystal Oscillator
Device 32 kHz Osc. Type Cap (Xtal1/Tosc1) Cap (Xtal2/Tosc2)
ATmega169P System Osc. 16 pF 6 pF
Timer Osc. 16 pF 6 pF
Table 8-9. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
SUT1..0 Additional Delay from Reset (VCC = 5. 0V) Recommended Us age
00 14 CK Fast rising power or BOD enabled
01 14 CK + 4 ms Slowly rising power
10 14 CK + 65 ms Stable frequency at start-up
11 Reserved
Table 8-10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
CKSEL3..0 Start-up Time from
Power-down and Power-save Recommended Usage
0110(1) 1K CK
0111 32K CK Stable frequency at start-up
Ce Ci+2CL⋅Cs
–=
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8.7 External Cloc k
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure
8-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 8-3. External Clock Drive Configuration
When this clock source is selected, start-up times are de termined by the SUT Fuses as sh own in
Table 8-12.
When applying an external clock, it is required t o avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implemen t run-time change s of the interna l
clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page
37 for details.
Table 8-11. Crystal Oscillator Clock Frequency
CKSEL3..0 Frequency Range
0000 0 - 16 MHz
Table 8-12. Start-up Times for the External Clock Selection
SUT1..0 Start-up Time from Power-
down and Power-save Additional Delay from
Reset (VCC = 5.0V) Recommended Usage
00 6 CK 14CK BOD enabled
01 6 CK 14CK + 4.1 ms Fa st rising power
10 6 CK 14CK + 65 ms Slowly rising po wer
11 Reserved
NC
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
GND
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8.8 Timer/Counter Oscillator
ATmega169P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter
Oscillator. See ”Low-frequency Cr ystal Oscillator” on page 34 for details on the oscillator and
crystal require m en ts .
ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and
XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the
oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be
used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See ”Asynchronous operation of the Timer/Counter” on page 150 for furthe r
description on selecting external clock as input instead of a 32.768 kHz watch crystal.
8.9 Clock Output Buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when chip clock is used to drive other circuits on the system. The clock will be output
also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-
grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output when the CKOUT Fuse is programmed.
8.10 System Clock Prescaler
The ATmega169P system clock can be divided by setting the ”CLKPR – Clock Prescale Regis-
ter” on page 38. This feature can be used to decrease the system clock frequency and power
consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.
clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 8-13.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing presca ler setting to make sure the write proce dure is
not interrupted.
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8.11 Register Description
8.11.1 OSCCAL – Oscillator Calibration Register
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration v alue is
automatically writt en to this register du ring chip reset, giving the Factory calibrated frequency as
specified in Table 28-2 on page 332. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 28-
2 on page 332. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write acc esses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowe st frequ ency in that range, a nd a setting of 0x7F g ives the highest fr equency in t he
range.
8.11.2 CLKPR – Clock Prescale Regist er
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As t he divider divide s the master clock input t o the MCU, the spe ed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 8-13 on page 39.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
Bit 76543210
(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 76543210
(0x61) CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
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“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application softwar e must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with t he CKDIV8 Fuse programmed.
Table 8-13. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1000 256
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
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9. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving-
power. The AVR provides various sleep modes allowing the user to tailor the power
consumptio n to the ap p licat ion ’s re qu ire m en ts.
9.1 Sleep Modes
Figure 8- 1 o n pa g e 3 0 presents the different clock systems in the ATmega169P, and their distri-
bution. The figure is helpful in selecting an appropriate sleep mode. Table 9-1 shows the
different sleep modes and their wake up sources.
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which
sleep mode will be activated by the SLEEP instruction. See Table 9-2 on page 45 for a
summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, exe cutes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wake s u p fr om slee p. I f a r eset occurs d uri ng sle ep mod e,
the MCU wakes up and executes from the Reset Vector.
Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains Oscillators W ake-up Sources
Sleep
Mode
clkCPU
clkFLASH
clkIO
clkADC
clkASY
Main Clock
Source Enabled
Timer Osc
Enabled
INT0 and
Pin Change
USI Start
Condition
LCD
Controller
Timer2
SPM/ EEPROM
Ready
ADC
Other
I/O
Idle XXX X X
(2) XXXXXXX
ADC NRM X X X X(2) X(3) XX
(2) X(2) XX
Power-
down X(3) X
Power-
save XXX
(3) XXX
Standby(1) XX
(3) X
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9.2 Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator,
ADC, USI, Timer/Counters, Watchdog, and the interrupt system to con tinue operating. This
sleep mode basically halts clkCPU an d clkFLASH, while allowing the other clocks to run.
Idle mode enables the M CU to wake up from external triggered interrupts as well a s internal
ones like the Timer O verflow and USART Transmit Complete interru pts. If wake-up from the
Analog Comparato r interrupt is not required , the Analog Comparator can b e powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
9.3 ADC Noise Reduction Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI
start condition det ection, Time r/Counter 2, LCD Controller, and the Watchdog to continue opera t-
ing (if enabled). This sleep m ode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conve rsion star ts automa tically when this mode is enter ed. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an LCD controlle r interrupt, USI start conditio n interrupt, a Timer/Counter2 interr upt, an
SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can
wake up the MCU from ADC Noise Reduction mode.
9.4 Power-down Mode
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Osc illator is stopped, while the external interrupts, the
USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-
nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level
interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically
halts all generated clo cks, allowing operation of asynchronous modules on ly.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 61
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in ”Clock Sources” on page 31.
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9.5 Power-save Mode
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 and /or the LCD controller are enabled, they will keep running during sleep.
The device can wake up from either Timer Overflow or Output Compare event from
Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2,
and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD co ntroller
interrupt.
If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended
instead of Power-save mode.
The LCD co ntroller a nd Timer/ Counter2 can be clo cked both synchron ously and asynchronously
in Power-save mode. The clock source for the two modules can be selected independent of
each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous
clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the
Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note
that even if the synchronous clock is running in Power-save, this clock is only available for the
LCD controller and Timer/Counter2.
9.6 Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock o ption is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
9.7 Power Reduction Register
The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 45, pro-
vides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the sa me state as before shutdo wn.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. See ”Supply Cu rr en t of I /O mo dules” o n p age 34 3 for examples. In all other
sleep modes, the clock is already stopped.
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9.8 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possi ble of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
9.8.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to ”ADC - Analog to Digital Conver ter” on page
216 for details on ADC operation.
9.8.2 Analog Co mp ara tor
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Inte rnal Voltage Reference will be enabled, indepe ndent of sleep
mode. Refer to ”AC - Analog Comparator” on page 212 for details on how to configure the Ana-
log Compara tor .
9.8.3 Brown-out Detector
If the Brown-ou t Detector is not needed by th e application, this mo dule should be turned off . If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
nificantly to the total current consumption. Refer to ”Brown-out Detec tion” on page 50 for details
on how to configure the Brown-out Detector.
9.8.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disable d as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to ”Internal Volt-
age Reference” on page 51 for details on the start-up time.
9.8.5 Watchdog Timer
If the Watchdog Timer is not needed in the application , the module should be turned off. If th e
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to ”Watchdog Timer” on pa ge 51 for d et ails on ho w to configu re the Wa tchd og Time r.
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9.8.6 Port Pins
When entering a sleep mode, all port pins should be configured to use m inimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 69 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to VCC/2 on an input pin can cause significan t current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 215 and ”DIDR0 – Digital
Input Disable Register 0” on page 233 for details.
9.8.7 JTAG Interface and On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or
Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will
contribute significantly to the total current consumption. There are three alternative ways to
avoid this:
• Disable OCDEN Fuse.
• Disable JTAGEN Fuse.
• Write one to the JTD bit in MCUCSR.
The TDO pin is left floating wh en the JTAG interf ace is enabled while th e JTAG TAP controller is
not shifting data. If the hardware connected to the TDO pin does not pull up the logic le vel,
power consumption will increase. Note that the TDI pin for the next device in the scan chain con-
tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or
leaving the JTAG fuse unprogrammed disables the JTAG interface.
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9.9 Register Description
9.9.1 SMCR – Sle ep Mo d e Cont rol Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 9-2.
Note: 1. Standby mode is only recommended for use with external crystals or resonators.
• Bit 1 – SE: Sleep Enable
The SE bit must be written to lo gic one to make the MCU enter the sle ep mode when the SLEEP
instruction is execut ed. To avoid t he MCU ent erin g the sleep mode un less it is the programmer’s
purpose, it is recomm ended to write the Sle ep Enable ( SE) bit to o ne just bef ore the e xecution of
the SLEEP instruction and to clear it immediately after waking up.
9.9.2 PRR – Power Reduction Register
• Bit 7:5 - Res: Reserved bits
These bits are reserve d and will always read as zero.
• Bit 4 - PRLCD: Power Reduction LCD
Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled
and the display discharged before shut down . See ”Disabling the LCD” on page 244 for details
on how to disable th e LCD cont ro ller .
Bit 76543210
0x33 (0x53) –––– SM2 SM1 SM0 SE SMCR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 9-2. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000Idle
0 0 1 ADC Noise Reduction
0 1 0 Power-down
0 1 1 Power-save
100Reserved
101Reserved
1 1 0 Standby(1)
111Reserved
Bit 7 6 5 4 3 2 1 0
(0x64) – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC PRR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 mo dule. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re initialized to ensure proper
operation.
• Bit 1 - PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When
waking up the USART again, the USART should be re initialized to ensure proper ope ration.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to th is bit shuts down t he ADC. The ADC must be disabled before sh ut down.
The analog comparator cannot use the ADC input MUX when the ADC is shut down.
Note: The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control
and Status Register” on page 214.
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10. System Control and Reset
10.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute
Jump – instruction to the reset handling routine. If the program never enables an inter rupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa. The circuit diagram in Figure 1 0-1 on page 48
shows the reset logic. Table 28-4 on pa ge 333 defines the electrical parameters of the reset
circuitry.
The I/O ports of the AVR are im mediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have g one inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections f or the delay period are presented in ”Clock Sources” on page 31.
10.2 Reset Sources
The ATmega169P has five sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below th e Pow er-on Reset
threshold (VPOT).
• External Reset. The MCU is reset when a low le vel is present on the RESET p in f or longer than
the minimum pulse length.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog is enabled.
• Brown- out Reset. The MCU is reset when th e supply voltage VCC is below the Bro wn-out Reset
threshold (VBOT) and the Brown-out Detecto r is enabled.
• JTAG AVR Reset. The MCU is reset as long as t here is a logic one in the Reset Register, one
of the scan chains of the JTAG system. Refer to the section ”IEEE 1149.1 (JTAG) Boundary-
scan” on page 259 for details.
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Figure 10-1. Reset Logic
10.2.1 Power-on Reset
A Power-on Reset (POR) pulse is ge nerated by an On-chip detection circuit. The detection level
is defined in ”System and Reset Characteristics” on page 333. The POR is activated whenever
VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) cir cuit ensures that the device is reset from Power-on . Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 10-2. MCU Start-up, RESET Tied to VCC
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
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Figure 10-3. MCU Start-up, RESET Extended Externally
10.2.2 External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see ”System and Reset Characteristics” on page 333) will generate a
reset, even if the clock is not running. Sh orter pulses are not guaranteed to generate a re set.
When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the
delay counter st arts the MCU after the Time-out period – tTOUT – has expired.
Figure 10-4. External Reset During Operation
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
CC
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10.2.3 Brown-out Detection
ATmega169P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level
during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be
selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level shou ld be interpreted as VBOT+ =
VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.When the BOD is enable d, and VCC decreases to a
value below the trigger level (VBOT- in Figure 10-5), the Brown-out Reset is im mediately acti-
vated. When VCC increases above the trigger level (VBOT+ in Figure 10- 5), the delay counter
starts the MCU after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for lon-
ger than tBOD given in ”System and Reset Characteristics” on page 333.
Figure 10-5. Brown-out Reset During Operation
10.2.4 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
”Watchdo g T ime r” on pa g e 51 for details on operation of the Watchdog Timer.
Figure 10-6. Watchdog Rese t Du rin g Oper a tion
VCC
RESET
TIME-OUT
INTERNAL
RESET
VBOT- VBOT+
tTOUT
CK
CC
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10.3 Internal Voltage Reference
ATmega169P features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
10.3.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time tha t may influence the way it should be used. T he
start-up time is given in ”System and Reset Characteristics” on page 333. To save power, the
reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandg ap reference is connected to the Analog Compar ator (by sett ing the
AC BG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
10.4 Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at VCC = 5V. See character iza tio n data f or typ ica l values at othe r VCC levels. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in Table 10-2 on page 55. The WDR – Watchdog Reset – instruction resets the Watch-
dog Timer. The Watchdo g Timer is also rese t when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expi res witho ut anot her Watchd og Reset , the ATme ga169P rese ts and executes f rom the
Reset Vector. For timing details on the Watchdog Reset, refer to Table 10-2 on page 55.
To prevent uninte ntional disabling of the Wa tchdog or unintentional ch ange of time-out period ,
two different safety levels are selected by the fuse WDTON as shown in Table 10-1 Refer to
”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 52 for
details.
Table 10-1. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON Safety
Level WDT Initial
State How to Disable the
WDT How to Change Time-
out
Unprogrammed 1 Disa bled Timed sequence Timed sequence
Programmed 2 Enabled Alwa ys enab led Timed sequence
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Figure 10-7. Watchdog Timer
10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for chan gin g configu ra tion dif f ers slightly between the two safety levels. Separate
procedures are described for each level.
10.4.1.1 Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to 1 without any re st r ict ion . A t imed seq uen ce is need ed when cha ngi ng th e Watchd og Time -o ut
period or disabling an enabled Wa tch dog Time r. To disab le an e nab led Watc hd og Timer , an d/or
changing the Watchdo g Time-out, the following procedure must be followed:
1. In the same oper ation, write a logic on e to WDCE and WDE. A logic one m ust be written
to WDE regardless of the previous value of the WDE bit.
2. Within the next f ou r clock cycles, in th e same oper ation, write the WDE and WDP bits as
desired, but with the WDCE bit cleared.
10.4.1.2 Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
always is set, the WDE must be written to one to start the timed sequence.
Within the next four clock cycles, in the same operation, wr ite the WDP bits as desired, but with
the WDCE bit cleared. The value written to the WDE bit is irrelevant.
WATCHDOG
OSCILLATOR
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Note: 1. See ”About Code Examples” on page 10.
Assembly Code Example(1)
WDT_off:
; Reset WDT
wdr
; Write logical one to WDCE and WDE
in r16, WDTCR
ori r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example(1)
void WDT_off(void)
{
/* Reset WDT */
__watchdog_reset();
/* Write logical one to WDCE and WDE */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
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10.5 Register Description
10.5.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Po wer-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occu rs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
10.5.2 WDTCR – Watchdog Timer Control Register
• Bits 7:5 – Res: Reserved Bits
These bits are reserve d and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the W DE bit is written to logic z ero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits. See ”Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 52.
Bit 76543210
0x35 (0x55) ––– JTRF WDRF BORF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
Bit 76543210
(0x60) – – – WDCE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Wa tchdog Timer f unction is di sabled. WDE can only be cle ared if th e WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same oper ation, write a logic on e to WDCE and WDE. A logic one m ust be written
to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above. See ”Timed Sequences for Changing the Configuration of the Watchdog
Timer” on page 52.
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in Table 10-2.
Note: Also see Figure 29-54 on page 366.
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are co ntrolled (f or example by disabling inte rrupts globally)
so that no interrupts will occur during execution of these functions.
Table 10-2. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0 Number of WDT
Oscillator Cycles Typical Time-out at
VCC = 3.0V T ypical Time-out at
VCC = 5.0V
0 0 0 16K cycles 15.4 ms 14.7 ms
0 0 1 32K cycles 30.8 ms 29.3 ms
0 1 0 64K cycles 61.6 ms 58.7 ms
0 1 1 128K cycles 0.12 s 0.12 s
1 0 0 256K cycles 0.25 s 0.23 s
1 0 1 512K cycles 0.49 s 0.47 s
1 1 0 1,024K cycles 1.0 s 0.9 s
1 1 1 2,048K cycles 2.0 s 1.9 s
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11. Interrupts
This section describes the specifics of the interrupt handling as performed in ATmega169P. For
a general explanation of the AVR interrupt handling, refer to ”Reset and Inte rrupt Handling” on
page 15.
11.1 Interrupt Vectors in ATmega169P
Notes: 1. When the BOOTRST Fuse is progr ammed, the de vice will jump to the Boot Loader address at
reset, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 280.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Inte rrupt Vector will th en be the address in this table
added to the start address of the Boot Flash Section.
Table 11-1. Reset and Interru pt Vector s
Vector
No. Program
Address(2) Source Interrupt Definition
1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset, and JTAG AVR Reset
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 PCINT0 Pin Change Interrupt Request 0
4 0x0006 PCINT1 Pin Change Interrupt Request 1
5 0x0008 TIMER2 COMP Timer/Counter2 Compare Match
6 0x000A TIMER2 OVF Timer/Counter2 Overflow
7 0x000C TIMER1 CAPT Timer/Counter1 Capture Event
8 0x000E TIMER1 COMPA Timer/Counter1 Compare Match A
9 0x0010 TIMER1 COMPB Timer/Counter1 Compare Match B
10 0x0012 TIMER1 OVF Timer/Counter1 Overflow
11 0x0014 TIMER0 COMP Timer/Counter0 Compare Match
12 0x0016 TIMER0 OVF Timer/Counter0 Overflow
13 0x0018 SPI, STC SPI Serial Transfer Complete
14 0x001A USART, RX USART0, Rx Complete
15 0x001C USART, UDREn USART0 Data Register Empty
16 0x001E USART, TX USART0, Tx Complete
17 0x0020 USI START USI Start Condition
18 0x00 22 USI OVERFLOW USI Overflow
19 0x0024 ANALOG COMP Analog Comparator
20 0x0026 ADC ADC Conversion Complete
21 0x0028 EE READY EEPROM Ready
22 0x002A SPM READY Store Program Memory Ready
23 0x002C LCD LCD Start of Frame
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Table 11-2 on page 57 shows reset and Interrupt Vectors placement for the various combina-
tions of BOOTRST and IVSEL settings. If the program never en ables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This
is also the case if the Reset Vector is in the Application section while the In te rrup t Vecto rs are in
the Boot section or vice versa.
Note: 1. The Boot Reset Address is shown in Table 26-6 on page 292. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega169P is:
Address Labels Code Comments
0x0000 jmp RESET ; Reset Handler
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp PCINT0 ; PCINT0 Handler
0x0006 jmp PCINT1 ; PCINT0 Handler
0x0008 jmp TIM2_COMP ; Timer2 Compare Handler
0x000A jmp TIM2_OVF ; Timer2 Overflow Handler
0x000C jmp TIM1_CAPT ; Timer1 Capture Handler
0x000E jmp TIM1_COMPA ; Timer1 CompareA Handler
0x0010 jmp TIM1_COMPB ; Timer1 CompareB Handler
0x0012 jmp TIM1_OVF ; Timer1 Overflow Handler
0x0014 jmp TIM0_COMP ; Timer0 Compare Handler
0x0016 jmp TIM0_OVF ; Timer0 Overflow Handler
0x0018 jmp SPI_STC ; SPI Transfer Complete Handler
0x001A jmp USART_RXCn ; USART0 RX Complete Handler
0x001C jmp USART_DRE ; USART0,UDRn Empty Handler
0x001E jmp USART_TXCn ; USART0 TX Complete Handler
0x0020 jmp USI_STRT ; USI Start Condition Handler
0x0022 jmp USI_OVFL ; USI Overflow Handler
0x0024 jmp ANA_COMP ; Analog Comparator Handler
0x0026 jmp ADC ; ADC Conversion Complete Handler
0x0028 jmp EE_RDY ; EEPROM Ready Handler
0x002A jmp SPM_RDY ; SPM Ready Handler
0x002C jmp LCD_SOF ; LCD Start of Frame Handler
;
0x002E RESET: ldi r16, high(RAMEND); Main program start
0x002F out SPH,r16 Set Stack Pointer to top of RAM
0x0030 ldi r16, low(RAMEND)
Table 11-2. Reset and Interru pt Vect or s Place m en t(1)
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x0000 0x0002
1 1 0x0000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x0002
0 1 Boot Reset Address Boot Reset Address + 0x0002
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0x0031 out SPL,r16
0x0032 sei ; Enable interrupts
0x0033 <instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2 Kbytes and the
IVSEL bit in the MCUCR Register is set before an y interrupts are enabled, the most typical and
general program setup for the Reset and In terrupt Vector Addresses is:
Address Labels Code Comments
0x0000 RESET: ldi r16,high(RAMEND); Main program start
0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0002 ldi r16,low(RAMEND)
0x0003 out SPL,r16
0x0004 sei ; Enable interrupts
0x0005 <instr> xxx
;
.org 0x1C02
0x1C02 jmp EXT_INT0 ; IRQ0 Handler
0x1C04 jmp PCINT0 ; PCINT0 Handler
... ... ... ;
0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2 Kbytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
.org 0x0002
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp PCINT0 ; PCINT0 Handler
... ... ... ;
0x002C jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0x1C00
0x1C00 RESET: ldi r16,high(RAMEND); Main program start
0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1C02 ldi r16,low(RAMEND)
0x1C03 out SPL,r16
0x1C04 sei ; Enable interrupts
0x1C05 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2 Kbytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
;
.org 0x1C00
0x1C00 jmp RESET ; Reset handler
0x1C02 jmp EXT_INT0 ; IRQ0 Handler
0x1C04 jmp PCINT0 ; PCINT0 Handler
... ... ... ;
0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler
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ATmega169P
;
0x1C2E RESET: ldi r16,high(RAMEND); Main program start
0x1C2F out SPH,r16 ; Set Stack Pointer to top of RAM
0x1C30 ldi r16,low(RAMEND)
0x1C31 out SPL,r16
0x1C32 sei ; Enable interrupts
0x1C33 <instr> xxx
11.2 Moving Interrupts Between Application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table, see
”MCUCR – MCU Control Register” on page 60.
To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be fol-
lowed to change the IVSEL bit:
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired v alue to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disa bled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while ex ecuting from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section ”Boot Loader Support – Read-While-
Write Self-Programming” on page 280 for details on Boot Lock bits.
The following example shows how interrupts are moved.
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11.2.1 MCUCR – MCU Control Register
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual add ress of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section ”Boot Loader Support – Read-While-Write
Self-Programming ” on page 280 for details.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the description in ”Moving Interrupts Between Application and Boo t
Space” on page 59. See Code Example.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ori r17, (1<<IVSEL)
out MCUCR, r17
ret
C Code Example
void Move_interrupts(void)
{
uchar temp;
/* Get MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp | (1<<IVCE);
/* Move interrupts to Boot Flash section
*/ MCUCR = temp | (1<<IVSEL);
}
Bit 76543210
0x35 (0x55) JTD - - PUD –– IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value00000000
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12. External Interrupts
The External Interrupts are trig gered by the INT0 pin or any of the PCINT15..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as
outputs. This f eatu re provid es a way of ge ner ating a so ft ware int er rupt . Th e pin chang e int erru pt
PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if
any enabled PCINT7..0 pin toggles. The PCM SK1 and PCMSK0 Registers control which pins
contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asyn-
chronously. This implies that these interrupts can b e used for waking the part also from sle ep
modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A – EICRA. When the
INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as
the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the
presence of an I/O clock, described in ”Clock Systems an d their Distribution” on page 30. Low
level interrupt on INT0 is de tected asynchrono usly. This implies that this interrupt can be used
for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all
sleep modes except Idle mode.
Note that if a level trigger ed interrupt is used for wake-up from Power-down, the required le vel
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in ”System Clock and Clock Options” on page 30.
12.1 Pin Change Interrupt Timing
An example of timing of a pi n change interrupt is shown in Figure 12-1.
Figure 12-1. Pin Change Interrupt
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
PCIF
PCINT(0) pin_sync pcint_syn
pin_lat
D Q
LE
pcint_setflag PCIF
clk clk
PCINT(0) in PCMSK(x)
pcint_in_(0) 0
x
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12.2 Register Description
12.2.1 EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 12-1. The value on the INT0 pin is sampled before detecting
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interr upt. Shorter pulses are not gu aranteed to generate an int errupt. If low level
interrupt is selected, the low level must be held until the comple tion of the currently executing
instruction to generate an interrupt.
12.2.2 EIMSK – External Interrupt Mask Register
• Bit 7 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corres ponding interrupt of Pin Change Inter rupt Request is executed from the PCI1
Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register.
• Bit 6 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.
• Bit 0 – INT0: External Interrupt Request 0 Enab le
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the
External Interrupt Control Register A (EICRA) define whether the external interrupt is activated
on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
Bit 76543210
(0x69) –––––– ISC01 ISC00 EICRA
Read/Write RRRRRRR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Table 12-1. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
Bit 76543210
0x1D (0x3D) PCIE1 PCIE0 –––––INT0EIMSK
Read/Write R/W R/W R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
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ATmega169P
interrupt reque st even if INT0 is conf igured as an out put. The corre sponding inte rrupt of Ext ernal
Interrupt Request 0 is executed from the INT0 Interrupt Vector.
12.2.3 EIFR – External Interrupt Flag Register
• Bit 7 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 6 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic chang e on the INT0 pin trigger s an interr upt requ est, INT F0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
12.2.4 PCMSK1 – Pin Change Mask Register 1
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15 :8 is set and t he PCIE1 bit in EIMSK is set, pin change inter rupt is enabled on the
corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit 76543210
0x1C (0x3C) PCIF1 PCIF0 ––––– INTF0 EIFR
Read/Write R/W R/W R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x6C) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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ATmega169P
12.2.5 PCMSK0 – Pin Change Mask Register 0
• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCI E 0 b it in EIM SK is set, pin cha nge in te rru p t is enab led on the cor -
responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit 76543210
(0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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13. I/O-Ports
13.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if conf igured a s output) or enablin g/disabling o f pull-up resistors (if con figured as
input). Each output buffer has symmetrical drive characteristics with both hig h sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to bo th VCC and Ground as indicated in Figure 13-1 on page 65. Refer to
”Electrical Characteristics” on page 329 for a complete list of parameters.
Figure 13-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the p ort, and a lower case “n” represe nts the bit numb er. However,
when using the regist er or bit defin es in a program , the precise f orm must be used. For examp le,
PORTB3 for bit no. 3 in Port B, her e docume nt ed ge ner ally as PO RT xn. The physical I /O Regis-
ters and bit locations are listed in ”Register Description for I/O-Ports” on page 88.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all po rts when set.
Using the I/O port as G eneral Digital I/O is described in ”Ports as General Digital I/O” on page
66. Most port pins are m ultiplexed with alternate function s for the peripheral features o n the
device. How each alternate function interferes with the port pin is described in ”Alternate Port
Functions” on page 71. Refer to the individual module sections for a full description of the alter-
nate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the por t as general digital I/O.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
Pxn
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ATmega169P
13.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 show s a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 13-2. General Digital I/O(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
13.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register
Description for I/O-Ports” on page 88, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch t he pull-up resist or off, PORTxn h as to be written logic zero or the pi n has to
be configured as an output pin. The port pins are tr i-stated when rese t condition becomes a ctive,
even if no clocks are runn in g.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
Q D
CLR
PORTxn
Q
QD
CLR
DDxn
PINxn
DATA BU S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
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ATmega169P
13.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
13.2.3 Switching Between Input an d Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull- up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the differenc e between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use e ither the tri-st ate ({DDxn, PORTxn} = 0b00) or th e output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 13-1 summarizes the control signals for the pin value.
13.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register b it. As sh ow n in Figure 13-2 on page 66, the PINxn Register b it a nd th e pr eced-
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure 13-3 on
page 68 shows a timing diagram of the synchronization when reading an externally applied pin
value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min
respectively.
Table 13-1. Port Pin Configurations
DDxn PORTxn PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
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Figure 13-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock pe riod depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 13-4. Synchronization when Rea ding a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
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ATmega169P
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Note: 1. F or the assemb ly program, two temporary registers are used to minimize the time from pull-
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
13.2.5 Digital Input Enab le and Sleep Modes
As shown in Figure 13-2 on page 66, the digital input signal can be clamped to ground at the
input of the Schmidt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power
consumption if some input signa ls ar e left floa ti ng, or have an analo g signa l level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in ”Alternate Port Functions” on page 71.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge , Falling Edge, or Any Logic Change on Pin” while the ext ernal interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
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13.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensur e that these pins have a def ined level. Even
though most of t he digital inputs are d isabled in the deep sleep modes as descr ibed above, fl oat-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to VCC or GND is not recommended, sin ce this may ca use excess ive curr ents if the pin is
accidentally configured as an output.
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13.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5
shows how the port pin control signals from the simplified Figure 13-2 on page 66 can be over-
ridden by alternate functions. The overriding signals may not be present in all port pins, but the
figure serves as a generic description applicable to all port pins in the AVR microcontroller
family.
Figure 13-5. Alternate Port Funct ions(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 13-2 on page 72 summarize s the function of the overriding signals. The pin and port
indexes from Figure 13-5 on pa ge 71 are not shown in the succ eeding tables. The overriding
signals are generated internally in the modules having the alternate function.
clk
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
QD
CLR
Q
QD
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA BUS
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Pxn
I/O
0
1
PTOExn
WPx
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
WPx: WRITE PINx
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The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 13-2. Gene ric Description of Overriding Signals for Alternate Functions
Signal Name Full Name Description
PUOE Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled b y the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
PUOV Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
and PUD Register bits.
DDOE Data Direction
Override Enable
If this signal is set, the Output Driver Enab le is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
DDOV Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bi t.
PVOE Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the port
value is controlled b y the PVO V signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
PVOV Po rt Value
Override Value If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
PTOE Port Toggle
Override Enable If PTOE is set, the PORTxn Register bit is inverted.
DIEOE Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
DIEOV Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Nor mal
mode, sleep mode).
DI Digital In put
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the outpu t of th e schmitt trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
AIO Analog
Input/Output
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
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13.3.1 Alternate Functions of Port A
The Port A has an alternate function as COM0:3 and SEG0:3 for th e LCD Controller.
Table 13-4 and Table 13-5 on page 74 relates the alternate functions of Port A to the overriding
signals shown in Figure 13-5 on page 71.
Table 13-3. Port A Pins Alternate Functions
Port Pin Alternate Function
PA7 SEG3 (LCD Front Plane 3)
PA6 SEG2 (LCD Front Plane 2)
PA5 SEG1 (LCD Front Plane 1)
PA4 SEG0 (LCD Front Plane 0)
PA3 COM3 (LCD Back Plane 3)
PA2 COM2 (LCD Back Plane 2)
PA1 COM1 (LCD Back Plane 1)
PA0 COM0 (LCD Back Plane 0)
Table 13-4. Overriding Signals for Alternate Functions in PA7..PA4
Signal Name PA7/SEG3 PA6/SEG2 PA5/SEG1 PA4/SEG0
PUOE LCDEN LCDEN LCDEN LCDEN
PUOV0000
DDOE LCDEN LCDEN LCDEN LCDEN
DDOV 0 0 0 0
PVOE0000
PVOV0000
PTOE––––
DIEOE LCDEN LCDEN LCDEN LCDEN
DIEOV 0 0 0 0
DI ––––
AIO SEG3 SEG2 SEG1 SEG0
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13.3.2 Alternate Functions of Port B
The Port B pins with alternate functions are sh own in Table 13-6.
The alternate pin configuration is as follows:
• OC2A/PCINT15, Bit 7
OC2, Output Comp are Match A output: The PB7 pin can serve as an externa l output for the
Timer/Counter2 Out pu t Compar e A. Th e pin ha s to be config ured as an out put (DDB7 se t ( one ))
to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.
PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt
source.
Table 13-5. Overriding Signals for Alternate Functions in PA3..PA0
Signal Name PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0
PUOE LCDEN •
(LCDMUX>2) LCDEN •
(LCDMUX>1) LCDEN •
(LCDMUX>0) LCDEN
PUOV0000
DDOE LCDEN •
(LCDMUX>2) LCDEN •
(LCDMUX>1) LCDEN •
(LCDMUX>0) LCDEN
DDOV 0 0 0 0
PVOE0000
PVOV0000
PTOE––––
DIEOE LCDEN •
(LCDMUX>2) LCDEN •
(LCDMUX>1) LCDEN •
(LCDMUX>0) LCDEN
DIEOV 0 0 0 0
DI––––
AIOCOM3COM2COM1COM0
Table 13-6. Port B Pins Alternate Functions
Port Pin Alternate Functions
PB7 OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change
Interrupt15).
PB6 OC1B/PCINT14 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change
Interrupt14).
PB5 OC1A/PCINT13 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change
Interrupt13).
PB4 OC0A/PCINT12 (Output Compare and PWM Output A for Timer/Counter0 or Pin Change
Interrupt12).
PB3 MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt11).
PB2 MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt10).
PB1 SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt9).
PB0 SS/PCINT8 (SPI Slave Select input or Pin Change Interrupt8).
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• OC1B/PCINT14, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the
Timer/Counter1 Out pu t Compar e B. Th e pin ha s to be config ured as an out put (DDB6 se t ( one ))
to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.
PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt
source.
• OC1A/PCINT13, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the
Timer/Counter1 Out pu t Compar e A. Th e pin ha s to be config ured as an out put (DDB5 se t ( one ))
to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt
source.
• OC0A/PCINT12, Bit 4
OC0A, Output Compare Match A output: The PB4 pin can serve as an external output for the
Timer/Counter0 Out pu t Compar e A. Th e pin ha s to be config ured as an out put (DDB4 se t ( one ))
to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.
PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt
source.
• MISO/PCINT11 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master,
this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as
a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an
input, the pull-up can still be controlled by the PORTB3 bit.
PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external interrupt
source.
• MOSI/PCINT10 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI. Whe n the SPI is enabled as a Slave,
this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as
a Master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an
input, the pull-up can still be controlled by the PORTB2 bit.
PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external interrupt
source.
• SCK/PCINT9 – Por t B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave,
this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as
a Master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an
input, the pull-up can still be controlled by the PORTB1 bit.
PCINT9, Pin Change I nterrupt Source 9: The PB1 pin can serve as an external interrupt source.
•SS
/PCINT8 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven
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low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
PCINT8, Pin Change I nterrupt Source 8: The PB0 pin can serve as an external interrupt source.
Table 13-7 and Table 13-8 on page 77 relate the alternate functions of Port B to the overriding
signals shown in Figur e 13-5 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT consti-
tute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-7. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name PB7/OC2A/
PCINT15 PB6/OC1B/
PCINT14 PB5/OC1A/
PCINT13 PB4/OC0A/
PCINT12
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE OC2A ENABLE OC1B ENABLE OC1A ENABLE OC0A ENABLE
PVOV OC2A OC1B OC1A OC0A
PTOE – – – –
DIEOE PCINT15 • PCIE1 PCINT1 4 • PCIE1 PCINT13 • PCIE1 PCINT12 • PCIE1
DIEOV 1 1 1 1
DI PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT
AIO – – – –
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13.3.3 Alternate Functions of Port C
The Port C has an alternate function as the SEG5:12 for the LCD Controller.
Table 13-8. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name PB3/MISO/
PCINT11 PB2/MOSI/
PCINT10 PB1/SCK/
PCINT9 PB0/SS/
PCINT8
PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD
DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
DDOV 0 0 0 0
PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0
PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0
PTOE – – – –
DIEOE PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1
DIEOV 1 1 1 1
DI PCINT11 INPUT
SPI MSTR INPUT PCINT10 INPUT
SPI SLAVE INPUT PCINT9 INPUT
SCK INPUT PCINT8 INPUT
SPI SS
AIO – – – –
Table 13-9. Port C Pins Alternate Functions
Port Pin Alternate Function
PC7 SEG5 (LCD Front Plane 5)
PC6 SEG6 (LCD Front Plane 6)
PC5 SEG7 (LCD Front Plane 7)
PC4 SEG8 (LCD Front Plane 8)
PC3 SEG9 (LCD Front Plane 9)
PC2 SEG10 (LCD Front Plane 10)
PC1 SEG11 (LCD Front Plane 11)
PC0 SEG12 (LCD Front Plane 12)
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Table 13-10 and Table 13- 11 relate the alternate functions of Port C to the overriding signals
shown in Figure 13-5 on page 71.
Table 13-10. Overriding Signals for Alternate Functions in PC7..PC4
Signal
Name PC7/SEG5 PC6/SEG6 PC5/SEG7 PC4/SEG8
PUOE LCDEN LCDEN LCDEN LCDEN
PUOV0000
DDOE LCDEN LCDEN LCDEN LCDEN
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOE LCDEN LCDEN LCDEN LCDEN
DIEOV0000
DI––––
AIO SEG5 SEG6 SEG7 SEG8
Table 13-11. Overriding Signals for Alternate Functions in PC3..PC0
Signal
Name PC3/SEG9 PC2/SEG10 PC1/SEG11 PC0/SEG12
PUOE LCDEN LCDEN LCDEN LCDEN
PUOV 0 0 0 0
DDOE LCDEN LCDEN LCDEN LCDEN
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
PTOE – – – –
DIEOE LCDEN LCDEN LCDEN LCDEN
DIEOV 0 0 0 0
DI – – – –
AIO SEG9 SEG10 SEG11 SEG12
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13.3.4 Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 13-12.
The alternate pin configuration is as follows:
• SEG15 - SEG20 – Port D, Bit 7:2
SEG15-SEG20, LCD front plan e 15-20.
•INT0
/SEG21 – Port D, Bit 1
INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the
MCU.
SEG21, LCD front plan e 21 .
• ICP1/SEG22 – Port D, Bit 0
ICP1 – Input Capture pin1: The PD0 pin can act as an Input Capture pin for Timer/Counter1.
SEG22, LCD front plan e 22 .
Table 13-12. Port D Pins Alternate Functions
Port Pin Alternate Function
PD7 SEG15 (LCD front plane 15)
PD6 SEG16 (LCD front plane 16)
PD5 SEG17 (LCD front plane 17)
PD4 SEG18 (LCD front plane 18)
PD3 SEG19 (LCD front plane 19)
PD2 SEG20 (LCD front plane 20)
PD1 INT0/SEG21 (External Interrupt0 Input or LCD front plane 21)
PD0 ICP1/SEG22 (Timer/Counter1 Input Capture pin or LCD front plane 22)
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Table 13-13 and Table 13-14 relates the alte rnate functions o f Port D to the overridin g signals
shown in Figure 13-5 on page 71.
Table 13-13. Overriding Signals for Alternate Functions PD7..PD4
Signal
Name PD7/SEG15 PD6/SEG16 PD5/SEG17 PD4/SEG18
PUOE LCDEN •
(LCDPM>1) LCDEN •
(LCDPM>1) LCDEN •
(LCDPM>2) LCDEN •
(LCDPM>2)
PUOV0000
DDOE LCDEN •
(LCDPM>1) LCDEN •
(LCDPM>1) LCDEN •
(LCDPM>2) LCDEN •
(LCDPM>2)
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOE LCDEN •
(LCDPM>1) LCDEN •
(LCDPM>1) LCDEN •
(LCDPM>2) LCDEN •
(LCDPM>2)
DIEOV0000
DI––––
AIO SEG15 SEG16 SEG17 SEG18
Table 13-14. Overriding Signals for Alternate Functions in PD3..PD0
Signal
Name PD3/SEG19 PD2/SEG20 PD1/INT0/SEG21 PD0/ICP1/SEG22
PUOE LCDEN •
(LCDPM>3) LCDEN •
(LCDPM>3) LCDEN •
(LCDPM>4) LCDEN •
(LCDPM>4)
PUOV0000
DDOE LCDEN •
(LCDPM>3) LCDEN •
(LCDPM>3) LCDEN •
(LCDPM>4) LCDEN •
(LCDPM>4)
DDOV 0 0 0 0
PVOE0000
PVOV0000
PTOE––––
DIEOE LCDEN •
(LCDPM>3) LCDEN •
(LCDPM>3) LCDEN + (INT0
ENABLE) LCDEN •
(LCDPM>4)
DIEOV 0 0 LCDEN • (INT0
ENABLE) 0
DI – – INT0 INPUT ICP1 INPUT
AIO – –
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13.3.5 Alternate Functions of Port E
The Port E pins with alternate functions are sh own in Table 13-15.
• PCINT7 – Port E, Bit 7
PCINT7, Pin Change I nterrupt Source 7: The PE7 pin can serve as an external interrupt source.
CLKO, Divided System Clock: The divided system clock can be output on the PE7 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTE7 and DDE7 settings. It will also be output during reset.
• DO/PCINT6 – Port E, Bit 6
DO, Universal Serial Interface Data output.
PCINT6, Pin Change I nterrupt Source 6: The PE6 pin can serve as an external interrupt source.
• DI/SDA/PCINT5 – P ort E, Bit 5
DI, Universal Serial Interface Data input.
SDA, Two-wire Serial Interface Data:
PCINT5, Pin Change I nterrupt Source 5: The PE5 pin can serve as an external interrupt source.
• USCK/SCL/PCINT4 – Port E, Bit 4
USCK, Universal Serial Interface Clock.
SCL, Two-wire Serial Interface Clock.
PCINT4, Pin Change I nterrupt Source 4: The PE4 pin can serve as an external interrupt source.
• AIN1/PCINT3 – Port E, Bit 3
AIN1 – Analog Com parat or Neg ati ve input . This pi n is dire ctly connect ed to t he ne gat ive inpu t of
the Analog Comparator.
PCINT3, Pin Change I nterrupt Source 3: The PE3 pin can serve as an external interrupt source.
Table 13-15. Port E Pins Alternate Functions
Port Pin Alternate Function
PE7 PCINT7 (Pin Change Interrupt7)
CLKO (Divided System Clock)
PE6 DO/PCINT6 (USI Data Output or Pin Change Interrupt6)
PE5 DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5)
PE4 USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or Pin
Change Interrupt4)
PE3 AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3)
PE2 XCK/AIN0/ PCINT2 (USART Exter nal Clock or Analog Comparator Positive Input or Pin
Change Interrupt2)
PE1 TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1)
PE0 RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0)
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• XCK/AIN0/PCINT2 – Port E, Bit 2
XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is
output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper-
ates in synchronous mode.
AIN0 – Analog Comparator Positive input. This pin is directly co nnected to the positive input of
the Analog Comparator.
PCINT2, Pin Change I nterrupt Source 2: The PE2 pin can serve as an external interrupt source.
• TXD/PCINT1 – P ort E, Bit 1
TXD0, UART0 Transmit pin.
PCINT1, Pin Change I nterrupt Source 1: The PE1 pin can serve as an external interrupt source.
• RXD/PCINT0 – Port E, Bit 0
RXD, USART Receive pin. Receive Data (Data input pin for the USAR T). When the USART
Receiver is enabled this pin is configured as an input rega rdless of the value of DDE0. When the
USART forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
PCINT0, Pin Change I nterrupt Source 0: The PE0 pin can serve as an external interrupt source.
Table 13-16 and Table 13-17 on page 83 relates the alternate functions of Port E to the overrid-
ing signals shown in Figure 13-5 on page 71.
Note: 1. CKOUT is one if the CKOUT Fuse is programmed
Table 13-16. Overriding Signals for Alternate Functions PE7:PE4
Signal
Name PE7/PCINT7 PE6/DO/
PCINT6 PE5/DI/SDA/
PCINT5 PE4/USCK/SCL/
PCINT4
PUOE 0 0 USI_TWO-WIRE USI_TWO-WIRE
PUOV 0 0 0 0
DDOE CKOUT(1) 0 USI_TWO-WIRE USI_TWO-WIRE
DDOV 1 0 (SDA + POR T E5) •
DDE5 (USI_SCL_HOLD •
PORTE4) + DDE4
PVOE CKOUT(1) USI_THREE-
WIRE USI_TWO-WIRE •
DDE5 USI_TWO-WIRE • DDE4
PVOV clkI/O DO 0 0
PTOE – – 0 USITC
DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 (PCINT5 • PCIE0) +
USISIE (PCINT4 • PCIE0) +
USISIE
DIEOV 1 1 1 1
DI PCINT7 INPUT PCINT6 INPUT DI/SDA INPUT
PCINT5 INPUT USCKL/SCL INPUT
PCINT4 INPUT
AIO – – – –
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Note: 1. AIN0D and AIN1D is described in ”DIDR1 – Digital Input Disable Register 1” on page 215.
13.3.6 Alternate Functions of Port F
The Port F has an alternate fu nction as analog input for the ADC as shown in Table 13-18. If
some Port F pins are configured as outputs, it is essential that these do not switch when a con-
version is in progress. This might corrupt the result of the conversion. If the JTAG interface is
enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even
if a reset occurs.
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Te st Data I n: Serial input d ata to be shifted in t o the I nstruction Register or Data Re g-
ister (scan chains). When the JTAG interface is enabled, this pi n can not be used as an I/O pin.
Table 13-17. Overr iding Signals for Alternate Functions in PE3:PE0
Signal
Name PE3/AIN1/
PCINT3 PE2/XCK/AIN0/
PCINT2 PE1/TXD/
PCINT1 PE0/RXD/PCINT0
PUOE 0 0 TXENn RXENn
PUOV 0 0 0 PORTE0 • PUD
DDOE 0 0 TXENn RXENn
DDOV 0 0 1 0
PVOE 0 XCK OUTPUT ENABLE TXENn 0
PVOV 0 XCK TXD 0
PTOE – – – –
DIEOE (PCINT3 • PCIE0)
+ AIN1D(1) (PCINT2 • PCIE0) +
AIN0D(1) PCINT1 • PCIE0 PCINT0 • PCIE0
DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 1 1
DI PCINT3 INPUT XCK/PCINT2 INPUT PCINT1 INPUT RXD/PCINT0 INPUT
AIO AIN1 INPUT AIN0 INPUT – –
Table 13-18. Port F Pins Alternate Functions
Port Pin Alternate Function
PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5 ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
PF3 ADC3 (ADC input channel 3)
PF2 ADC2 (ADC input channel 2)
PF1 ADC1 (ADC input channel 1)
PF0 ADC0 (ADC input channel 0)
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• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out
data, the TDO pin drives actively. In other states the pin is pulled high.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/ O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3-0.
Table 13-19. Overr iding Signals for Alternate Functions in PF7:PF4
Signal
Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK
PUOE JTAGEN JTAGEN JTAGEN JTAGEN
PUOV 1 1 1 1
DDOE JTAGEN JTAGEN JTAGEN JTAGEN
DDOV 0 SHIFT_IR + SHIFT_DR 0 0
PVOE 0 JTAGEN 0 0
PVOV 0 TDO 0 0
PTOE – – – –
DIEOE JTAGEN JTAGEN JTAGEN JTAGEN
DIEOV 0 0 0 1
DI – – – –
AIO TDI
ADC7 INPUT ADC6 INPUT TMS
ADC5 INPUT TCK
ADC4 INPUT
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13.3.7 Alternate Functions of Port G
The alternate pin configuration is as follows:
Note: 1. Port G, PG5 is input only. Pull-up is always on.
See Table 27-3 on page 297 for RSTDISBL fuse.
The alternate pin configuration is as follows:
• RESET – Por t G, Bit 5
RESET: External Reset input. When the RSTDISBL Fuse is programmed (‘0’), PG5 will function
as input with pull-up always on.
• T0/SEG23 – Port G, Bit 4
T0, Timer/Counter0 Counter Source.
SEG23, LCD front plan e 23
• T1/SEG24 – Port G, Bit 3
T1, Timer/Counter1 Counter Source.
SEG24, LCD front plan e 24
Table 13-20. Overr iding Signals for Alternate Functions in PF3:PF0
Signal
Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0
PUOE0000
PUOV0000
DDOE0000
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOE0000
DIEOV0000
DI––––
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
Table 13-21. Port G Pins Alternate Functions(1)
Port Pin Alternate Function
PG5 RESET
PG4 T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23)
PG3 T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24)
PG2 SEG4 (LCD Front Plane 4)
PG1 SEG13 (LCD Front Plane 13)
PG0 SEG14 (LCD Front Plane 14)
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• SEG4 – Port G, Bit 2
SEG4, LCD front plane 4
• SEG13 – Port G, Bit 1
SEG13, Segment dr ive r 13
• SEG14 – Port G, Bit 0
SEG14, LCD front plan e 14
Table 13-21 on page 85 and Tab le 13-22 relates th e alternate funct ion s of Po rt G to th e ov er rid -
ing signals shown in Figure 13-5 on page 71.
Table 13-22. Overr iding Signals for Alternate Functions in PG4
Signal
Name PG4/T0/SEG23
PUOE LCDEN • (LCDPM>5)
PUOV 0
DDOE LCDEN • (LCDPM>5)
DDOV 1
PVOE 0
PVOV 0
PTOE – – – –
DIEOE LCDEN • (LCDPM>5)
DIEOV 0
DI T0 INPUT
AIO SEG23
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Table 13-23. Overr iding Signals for Alternate Functions in PG3:0
Signal
Name PG3/T1/SEG24 PG2/SEG4 PG1/SEG13 PG0/SEG14
PUOE LCDEN •
(LCDPM>6) LCDEN LCDEN •
(LCDPM>0) LCDEN • (LCDPM>0)
PUOV 0 0 0 0
DDOE LCDEN •
(LCDPM>6) LCDEN LCDEN •
(LCDPM>0) LCDEN • (LCDPM>0)
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
PTOE – – – –
DIEOE LCDEN •
(LCDPM>6) LCDEN LCDEN •
(LCDPM>0) LCDEN • (LCDPM>0)
DIEOV 0 0 0 0
DI T1 INPUT – – –
AIO SEG24 SEG4 SEG13 SEG14
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13.4 Register Description for I/O-Ports
13.4.1 MCUCR – MCU Control Register
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disab led even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Con-
figuring the Pin” on page 66 for more details about this feature.
13.4.2 PORTA – Port A Data Register
13.4.3 DDRA – Port A Data Direction Register
13.4.4 PINA – Port A Input Pins Address
13.4.5 PORTB – Port B Data Register
13.4.6 DDRB – Port B Data Direction Register
13.4.7 PINB – Port B Input Pins Address
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) JTD --PUD– – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x02 (0x22) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x01 (0x21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x00 (0x20) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
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13.4.8 PORTC – Port C Data Register
13.4.9 DDRC – Port C Data Direction Register
13.4.10 PINC – Port C Input Pins Ad dress
13.4.11 PORTD – Port D Data Register
13.4.12 DDRD – Port D Data Direction Register
13.4.13 PIND – Port D Input Pins Ad dress
13.4.14 PORTE – Por t E Data Reg i st er
13.4.15 DDRE – P ort E Data Direction Register
Bit 76543210
0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x07 (0x27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x06 (0x26) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x0E (0x2E) PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x0D (0x2D) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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13.4.16 PINE – Port E Input Pins Address
13.4.17 PORTF – Port F Data Register
13.4.18 DDRF – Port F Data Direction Register
13.4.19 PINF – Port F Input Pins Address
13.4.20 PORTG – Port G Data Register
13.4.21 DDRG – Port G Data Direction Registe r
13.4.22 PING – Port G Input Pins Address
Bit 76543210
0x0C (0x2C) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x11 (0x31) PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x10 (0x30) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x0F (0x2F) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x14 (0x34) ––
PORTG4 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x13 (0x33) – – DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 DDRG
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x12 (0x32) – – PING5 PING4 PING3 PING2 PING1 PING0 PING
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 N/A N/A N/A N/A N/A
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14. 8-bit Timer/Counter0 with PWM
14.1 Features
•Single Compare Unit Counter
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Frequency Generator
•External Event Counter
•10-bit Clock Prescaler
•Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)
14.2 Overview
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-
fied block diagram is shown in Figure 14-1. For the actual placement of I/O pins, refer to Figure
1-1 on page 2. CPU accessible I/O Registe rs, inc ludin g I/O bit s and I/ O pins, are sh own in b old.
The device-specific I/O Register and bit locations are listed in the ”8-bit Timer/Counter Register
Description” on page 10 2.
Figure 14-1. 8-bit Timer/Counter Block Diagram
14.2.1 Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-
rupt request (abbreviated to Int.Req. in the figure ) signals are all visible in the Timer Interrupt
Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-
ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked inter nally, via the pre scaler, or by an external clock source on
the T0 pin. T he Clock Se lect logic blo ck controls which clock so urce and edge the Timer/Cou nter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
Timer/Counter
DATA BU S
=
TCNTn
Waveform
Generation OCn
= 0
Control Logic
=
0xFF
BOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCRn
TCCRn
Clock Select
Tn
Edge
Detector
( From Prescaler )
clk
Tn
TOP
OCn
(Int.Req.)
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The double buffered Outpu t Compare Register (OCR0A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output
Compare Unit” on page 93. for details. The compare match event will also set the Compare Flag
(OCF0A) which can be used to generate an Output Compare interrupt request.
14.2.2 Definitions
Many register and bit reference s in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare unit number, in this case unit A. However, when using the register or bit defines in a
program, the precise form must be used, that is, TCNT0 for accessing Timer/Counter0 counter
value and so on.
The definitions in Table 14-1 are also used extensively throughout the document.
14.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Tim er/Counter Cont rol Regi ster ( TCCR0A). For deta ils on clock sources an d pres-
caler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 135.
14.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
14-2 shows a block diagram of the counter and its surroundings.
Figure 14-2. Counter Unit Block Diagram
Table 14-1. Timer/Counter Definitions
BOTTOM The counter reaches the BOTTOM whe n it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches t he TOP when it become s equa l to the highe st value in th e
count sequence. The TOP valu e can be assigned to be the fixed value 0xFF
(MAX) or the valu e stored in the OCR0A Register. T he assignment is d ependent
on the mode of operation.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear
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Signal description (internal signals):
count Increment or de cre m en t TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTnTimer/Co un te r clo ck, re fe rr ed to as clk T0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or inte rnal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over ) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A). There are close connections between how the
counter behaves (counts) and how waveforms a re generated on the Output Compare output
OC0A. For more details about advanced counting sequences and waveform generation, see
”Modes of Operation” on page 96.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
14.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set
the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and
Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare
interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed. Alternatively,
the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The
Waveform Generator uses the match signal to generate an output according to operating mode
set by the WGM01:0 bits an d Compare Output mo de (COM0A1:0) bits. Th e max and bottom sig-
nals are used by the Waveform Generator for handling the special cases of the extreme values
in some modes of operation (See ”Modes of Operation” on page 96.).
Figure 14-3 on page 94 shows a block diagram of the Output Compare unit.
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Figure 14-3. Output Compare Unit, Block Diagram
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Time r on Compare ( CTC) modes o f operation , the do uble buff-
ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is
disabled the CPU will access the OCR0A directly.
14.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0A) bit. Forc ing compare match will not s et the
OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare
match had occurred (the COM0A1:0 bit s settings define whether the OC0A pin is set, cleared or
toggled).
14.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-
ized to the same value as TCNT0 wit hout trigg ering an inte rrupt when t he Timer/Coun ter clock is
enabled.
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnx1:0
bottom
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14.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the Output Compare unit,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do no t write t he TCNT0 value eq ual to BOTTOM whe n the co unter is down
counting.
The setup of the OC0 A should be perfo rmed before setting th e Data Direction Register for th e
port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-
pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when
changing between Wa veform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare value.
Changing the COM0A1:0 bits will take effect immediately.
14.6 Compare Match Output Unit
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator
uses the COM0A1:0 bits for defining th e Output Compare (OC0A) state at the next compare
match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 14- 4 shows a sim-
plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits,
and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-
ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the
OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System
Reset occur, the OC0A Register is reset to “0”.
Figure 14-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform
Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis-
ible on the pin. The port override function is independent of the Waveform Generation mode.
PORT
DDR
DQ
DQ
OCn
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BU S
FOCn
clk
I/O
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The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation. See ”8-bit Timer/Counter Register Description” on page 102.
14.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on
the OC0A Register is to be performed on the next compare match. For compare output actions
in the non-PWM m ode s r ef er to Ta ble 1 4- 3 on page 1 03. For fast PWM mode, refer to Table 14-
4 on page 103, and for phase correct PWM re fe r to Table 14-5 on page 103.
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0A strobe bits.
14.7 Modes of Operation
The mode of o perat ion , th at is, the beh avior of t he Timer/ Cou nter an d the Ou t put Com par e pins,
is defined by the combin ation of the Wavef orm Generat ion mode (WGM 01:0) an d Compare Out-
put mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM 0A1: 0 bit s co ntro l whet h er th e o ut pu t sh ould be set, clear ed , or to gg led at
a compare match (See ”Compare Match Output Unit” on page 95.).
For detailed timing information refer to Figure 14-8, Figure 14-9, Figure 14-10 and Figure 14-11
in ”Timer/Counte r Timing Diagrams” on page 100.
14.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflo w interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compar e u nit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou t-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
14.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to
manipulate the count er resolut io n. In CTC mode the counter is clear ed to zero wh en the counter
value (TCNT0) matches the OCR0A. The OCR0A de fines the top value for the counter, hence
also its resolution. This m ode allows greater control of the compare ma tch output frequency. It
also simplifies the op e ra tio n of coun tin g exte rn al ev en ts.
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The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0)
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
Figure 14-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low pres caler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generatin g a wavefor m out put in CT C mod e, t he OC0A ou tput can be se t to toggle it s logica l
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of op erat ion, the T OV0 Flag is se t in the same tim er clock cycle tha t the
counter counts from MAX to 0x00.
14.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-
gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In
non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare
match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Outpu t mode,
the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
1 4
Period
2 3
(COMnx1:0 = 1)
fOCnx
fclk_I/O
2N1OCRnx+()⋅⋅
--------------------------------------------------=
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In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a his-
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. Th e small horizo ntal line marks on th e TCNT0 slopes represe nt compare
matches between OCR0A and TCNT0.
Figure 14-6. Fast PWM Mode, Timing Diagram
The Timer/Counter O verflow Flag (TOV0) is set each t ime the coun ter reache s MAX. If the inte r-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0A1:0 to three (See Table 14-4 on page 103). The actual
OC0A value will only be visible on the port pin if the data direction for the port pin is set as out-
put. The PWM wave form is generat ed b y settin g (or clear ing) t he O C0A Regist er a t the compa re
match between OCR0A and TCNT0 , and clearing (or setting) the OC0A Register at the timer
clock cycle the counter is cleare d (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the pre scale factor (1, 8, 64, 256, or 1024).
The extreme values for th e OCR0A Re gister rep resents sp ecial cases wh en gen erating a PW M
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0A to toggle its logical level on ea ch compare match (COM0A1:0 = 1). The wave form
generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCn
OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
fOCnxPWM
fclk_I/O
N256⋅
------------------=
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feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-
put Compare unit is enabled in the fast PWM mode.
14.7.4 Phase Correct PWM Mode
The phase c orrect PWM mode (WGM01:0 = 1) pr ovides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-
inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match
between TCNT0 and OCR0A while upcounting, and set on the compare match while down-
counting. In inverting Outp ut Compar e mod e, the oper ation is in vert ed. The dual- slope o perat ion
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the counter
reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one
timer clock cycle . The timing di agram for t he phase correct PWM mod e is shown on Figure 1 4-7.
The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-in verted and inverted PWM outputs. The small horizontal
line marks on the TC NT 0 slo pe s re pr es en t com p ar e ma tc he s be twe e n OC R 0A an d TCNT 0 .
Figure 14-7. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Counter Over flow Flag (TOV0) is set each time the counter reache s BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can b e genera ted by setti ng the COM0A1 :0 t o three (See Table 14-5 on page 103).
The actual OC0A value will only be visible on the port pin if the data direction for the port pin is
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Update
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set as output. The PWM waveform is generated b y clearing (or se tting) the OC0A Reg ister at the
compare match between OCR0A and TCNT0 when the counter increments, and setting (or
clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter
decrements. The PWM frequency for the output when using ph ase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases wh en generating a PWM
waveform output in the phase correct PWM mo de. If the OCR0A is set equal to BO TTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 14-7 on page 99 OCn has a transition from high to low
even though there is no Compare Match. The point of this tr ansition is to guar antee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, lik e in Figure 14-7 on page 99. When the OCR0A value
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX mu st corr espond to the result of an
up-counting Compare Match.
• The timer starts counting from a v alue higher than the one in OCR0A, and for that reason
misses the Compare Match and hence th e OCn change that w ould ha v e happe ned on the w a y
up.
14.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable sign al in the following figures. Th e figures include information on whe n Interrupt
Flags are set. Figure 14-8 cont ains timing data for basic Timer/Counter op eration. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 14-8. Timer/Counter Timing Diagram, no Prescaling
Figure 14-9 on page 101 shows the same timing data, but with the prescaler enabled.
fOCnxPCPWM
fclk_I/O
N510⋅
------------------=
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 14-10 shows the setting of OCF0A in all modes excep t CTC mode.
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8)
Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
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14.9 8-bit Timer/Counter Register Description
14.9.1 TCCR0A – Timer/Count er Cont rol Register A
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non -PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits se tting. Note that the FO C0A bit is impleme nted as a str obe. Ther efore it is
the value present in the COM0A1:0 bits that determines the ef fect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the co unting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See Table 14-2 and ”Modes of Operation”
on page 96.
Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
However, the functionality an d location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM0A1 :0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output dr iver.
Bit 76543210
0x24 (0x44) FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 TCCR0A
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 14-2. Waveform Generation Mod e Bit Des crip tio n()
Mode WGM01
(CTC0) WGM00
(PWM0) Timer/Counter Mode
of Operation TOP Update of
OCR0A at T OV0 Flag Set
on
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Ph ase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR0A Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM M AX
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When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 14- 3 shows the COM0A1:0 bit functionality when the WGM01:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mo de” on
page 97 for more details.
Table 14-5 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
rect PWM mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at T OP. See ”Phase Correct PWM Mode” on
page 99 for more details.
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 14-3. Compare Output Mode, non-PWM Mode
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on compare match
1 0 Clear OC0A on compare match
1 1 Set OC0A on compare match
Table 14-4. Compare Output Mode, Fast PWM Mode(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01Reserved
10
Clear OC0A on compare match, set OC0A at BOTTOM
(non-inverting mode)
11
Set OC0A on compare match, clear OC0A at BOTTOM
(inverting mode)
Table 14-5. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01Reserved
10
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when down counting.
11
Set OC0A on compare match when up-co unting. Clear OC0A on
compare match when down counting.
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If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
14.9.2 TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.
14.9.3 OCR0A – Output Compare Regist er A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0 ). A match can be used to generate an Output Com pare interrupt, or to
generate a waveform output on the OC0A pin.
14.9.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register
Table 14-6. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
001clk
I/O/(No prescaling)
010clk
I/O/8 (From prescaler)
011clk
I/O/64 (From prescaler)
100clk
I/O/256 (From prescaler)
101clk
I/O/1024 (F rom prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
Bit 76543210
0x26 (0x46) TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x27 (0x47) OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x6E) ––––––OCIE0ATOIE0TIMSK0
Read/Write RRRRRRR/WR/W
Initial Value00000000
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• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Reg ister is set (one), the
Timer/Counte r0 Compare M a tch A interrup t is en ab le d. T h e co rr es po nd in g interrupt is e x e cu te d
if a compare match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter 0 occurs, that is, when the TOV0 bit is s et in the Timer/ Counter 0 Inter-
rupt Flag Register – TIFR0.
14.9.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bit 1 – OCF0A: Out put Compare Flag 0 A
The OCF0A bit is set ( one) when a compare matc h occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counte r0 Compare match Interrupt
Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Inter rupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflo w occurs in Time r/Coun te r0 . TO V0 is clear ed by har d-
ware when executing the corre spon ding int erru pt han dling vecto r. Alt ernat ively, TOV0 is clear ed
by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at
0x00.
Bit 76543210
0x15 (0x35) ––––––OCF0ATOV0 TIFR0
Read/Write RRRRRRR/WR/W
Initial Value 0 0 0 0 0 0 0 0
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15. 16-bit Timer/Counter1
15.1 Features
•True 16-bit Design (that is, allows 16-bit PWM)
•Two independent Output Compare Units
•Double Buffered Output Compare Registers
•One Input Capture Unit
•Input Capture Noise Canceler
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Variable PWM Period
•Frequency Generator
•External Event Counter
•Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
15.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this sec-
tion are written in general form . A lower case “n” replace s the Timer/Counter number, and a
lower case “x” replaces the Output Compare unit number. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT1 for accessing
Timer/Counter 1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1 on page 107. For
the actual placement of I/O pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers,
including I/O bit s and I/O pins, are sh own in bold. The de vice-specific I/O R egister and bit loca-
tions are listed in the Section 15.11 ”16-bit Timer/Counter Register Description” on page 128.
The PRTIM1 bit in Section 9.9.2 ”PRR – Power Reduction Register” on page 45 must be written
to zero to enable Timer/Counter1 module.
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Figure 15-1. 16-bit Timer/Counter Block Diagram(1)
Note: 1. Ref er to Figure 1-1 on page 2, Table 13-5 on page 74, and Table 13-11 on page 78 for
Timer/Counter1 pin placement and description.
15.2.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Inpu t Capture Regis-
ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These proced ures are described in the section ”Accessing 16-bit Registers” on
page 109. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no
CPU access re strictions. Int errupt requests (abbreviated to Int.Req. in the figure) signals are all
visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with
the Timer Interrupt Ma sk Re gist er (TI M SK1) . TI FR1 and TIMSK1 ar e no t sho wn in the figu re .
The Timer/Counter can be clocked inter nally, via the pre scaler, or by an external clock source on
the T1 pin. T he Clock Se lect logic blo ck controls which clock so urce and edge the Timer/Cou nter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1).
The double buffere d Outp ut Compa re Registers (O CR1A/B) are compared with the Timer /Coun-
ter value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See ”Out-
Clock Select
Timer/Counter
DATA B U S
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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put Compare Units” on page 115. The compare match event will also set the Compare Match
Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”AC
- Analog Compara tor” on page 212.) Th e Inpu t Capture unit includes a dig ital filt ering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using
OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in ru n ti me. I f a fixed TOP valu e is req uired , t he ICR1 Reg i ster ca n be used
as an alternative, freeing the OCR1A to be used as PWM output.
15.2.2 Definitions
The following definitions are used extensively throughout the section:
15.2.3 Compatibility
The 16-bit Timer/Counter has been updated an d improved from previous versions of the 16-bit
AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version
regarding:
• All 16-bit Timer/Counter related I/O Register address locations, including Ti mer Interrupt
Registers.
• Bit locations inside all 16-bit Timer/Counter Reg iste r s, including Time r Int er rupt Regist er s.
• Interrupt Vectors.
The following control bits have cha nged name, but have same functionalit y and register locatio n:
• PWM10 is changed to WGM10.
• PWM11 is changed to WGM11.
• CTC1 is changed to WGM12.
The following bits are added to the 16-bit Timer/Counter Control Registers:
• FOC1A and FOC 1B ar e ad de d to TCCR1C.
• WGM13 is added to TCCR1B.
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special
cases.
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,
or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is
dependent of the mode of operation.
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15.3 Accessing 16-bit Registers
The TCNT1, OCR1A/B, a nd ICR1 a re 16-b it re gisters tha t can b e acce ssed by t he AVR CPU via
the 8-bit data bu s. Th e 1 6- bit re giste r must be byte accessed u s ing tw o rea d o r write op erat ions.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers within each 16-bit
timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a
16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are bo th copied into the 16-bit re gister in the sam e clock cycle. When the lo w byte of
a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-
rary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-
bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byt e. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCR1A/B and ICR1 Registers. Not e that when using “C”, the compiler hand les the 16-bit
access.
Note: 1. See ”About Code Examples” on page 10.
The assembly code examp le returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-
ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both
Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
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the main code and the inte rrupt code updat e th e te mpora ry reg iste r, th e main code must di sable
the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents.
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. See ”About Code Examples” on page 10.
The assembly code examp le returns the TCNT1 value in the r17:r16 register pair.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
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The following code examples show how to do an atomic write of the TCNT1 Register contents.
Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. See ”About Code Examples” on page 10.
The assembly code example requires that the r17:r16 register pair contains the value to be writ-
ten to TCNT1.
15.3.1 Reusing the Temporary High Byte Register
If writing to more t han one 16 -bit regist er where the high byte is the same f or all regi sters writte n,
then the high byte on ly needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
15.4 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits
located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and
prescaler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 135.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
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15.5 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 15-2 shows a block diagram of the counter and its surroundings.
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
Count Increment or de cre m en t TCNT1 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT1 (set all bits to zero).
clkT1Timer/Counter clock.
TOP Signalize that TCNT1 has reached maximum value.
BOTTOM Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-
taining the upper ei ght bits of the co unter, an d Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Regist er can only be ind irect ly accessed by the CPU. When the CPU d oes an
access to the TCNT1H I/O locat ion, the CPU accesses the h igh byte tempor ary register (TEMP).
The temporary register is updated with the TCNT1H value when the T CNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mo de o f oper at ion us ed, the cou nt er is cleared , in cr eme nted , o r decr em ent ed
at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clkT1 is present or not. A CPU write overrides (h as priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connectio ns between how the counter behaves (counts) and how wavefor ms
are generate d on the Out put Compare ou tputs OC1x. For more details abo ut advanced co unting
sequences and waveform generation, see ” Modes of Operation” on page 118.
TEMP (8-bit)
DATA BUS
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clkTn
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
15.6 Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time -stamp in dicating t ime o f occurre nce. The externa l signal indica ting an e vent, or mul-
tiple events, ca n be app lied via the ICP1 pin o r al ter natively, via the analog- comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-
nal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 15-3. The elements of
the block diagram t hat are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
Figure 15-3. Input Capture Unit Block Diagram
When a change of the lo gic level (a n event) oc curs on the Input Capt ure pin ( ICP1), a lt ernat ively
on the Analog Comparat or output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNT1) is written to the Input Capture Re gister (ICR1). The Input Capture Flag (ICF1) is set at
the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),
the Input Capture Fla g generates an Input Capture interru pt. The ICF1 Flag is automatically
cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software
by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied
into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will
access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-
ICFn (Int.Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA BUS
(8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACIC* ICNC ICES
ACO*
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tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location
before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers”
on page 109.
15.6.1 Input Capture Trigger Sour ce
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The An alog Comparator is selected as trigger source by setting the Analog
Comparator In put Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled
using the same techniqu e as for th e T1 pin (Figur e 16-1 on page 1 35). The edge d etector is a lso
identical. However, when the noise canceler is ena bled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-
form Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
15.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monit ored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled t he noise can celer intr oduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the sy stem clock and is therefore not affected by the
prescaler.
15.6.3 Using the Input Capture Unit
The main challeng e when using the Inpu t Capture unit is to assign enoug h processor capacity
for handling the incoming events. The time between two events is critica l. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dep endent on the maximum number of clock
cycles it takes to hand le an y of th e ot he r int er ru pt req ue sts .
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during op eration, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changin g the edge sensing must be done as early as po ssible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
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cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 Flag is not required (if an interrupt handler is used).
15.7 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set th e Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-
pare Flag generates an Output Compare interru pt. The OCF1x Flag is auto matically cleared
when the inter rupt is executed. Altern atively the OCF1x Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See ”Modes of Oper ation” on page 118.)
A special feature of Output Compar e unit A allows i t to defi ne the Timer/ Counte r TOP value (th at
is, counter resolution). In addition to the counter resolution, the TOP value defines the period
time for waveforms generated by the Waveform Generator.
Figure 15-4 shows a b lock diagram o f the Ou tput Comp are u nit. The small “ n” in the re gister and
bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 15-4. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Time r on Compare (CTC) modes of ope ration, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
OCFnx (Int.Req.)
=
(16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS
(8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx1:0WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
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prevents the occurrence of odd-length, non-symm etrical PWM pulses, thereby making the out-
put glitch-free.
The OCR1x Register access may seem co mplex, but this is not case. Wh en the double buff ering
is enabled, the CPU has access to the OC R1x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)
Register is only chan ged by a w rite operation ( the Timer/Counter does not upda te this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). Howeve r, it is a good practice to read the low byte first as whe n
accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Reg-
ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the va lue written. Then whe n the low byte (OCR1xL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to ”Accessing 16-bit Registers”
on page 109.
15.7.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the
OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare
match had occurred (the COMx1:0 bits settings define whether the O C1x pin is set, cleared or
toggled).
15.7.2 Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.
15.7.3 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT1 when using any of the Output Compare
units, independent of whether the Timer/Counter is running or not. If the value written to TCNT1
equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform
generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The
compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly,
do not write the TCNT1 value equal to BOTTOM when the counter is down counting.
The setup of the OC1x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com-
pare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when
changing between Wa veform Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value.
Changing the COM1x1:0 bits will take effect immediately.
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15.8 Compare Match Output Unit
The Compare Output mode (COM1x1:0) bit s have t wo functions. Th e Waveform Gen erator uses
the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.
Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified
schematic of th e logic affecte d by the COM1x1: 0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the
OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset
occur, the OC1x Register is reset to “0”.
Figure 15-5. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but the re are some exce ptions. Refer t o Table 1 5-1 on p age 128, Table 15-2 on page 128
and Table 15-3 on page 129 for details.
The design of the Output Compare pin logic allows initializat ion of the OC1x state before t he out-
put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of
operation. See ”16-bit Timer/Counte r Register Descript ion” on page 128.
The COM1x1:0 bi ts have no effect on the Input Capture unit.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA B U S
FOCnx
clk
I/O
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15.8.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the
OC1x Register is t o be performed on the next com pare match. F or compare output actions in t he
non-PWM modes refer to Table 15-1 on pag e 128. For fast PWM mode refer to Table 15-2 on
page 128, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on
page 129.
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC1x strobe bits.
15.9 Modes of Operation
The mode of o perat ion , th at is, the beh avior of t he Timer/ Cou nter an d the Ou t put Com par e pins,
is defined by the combination of the Waveform Generat ion mode (WGM13:0) and Compare Out-
put mode (COM1x1: 0) bits. The Co mpare Output mode bits do not aff ect the counti ng sequence,
while the Waveform Gener ation mode bits do . The COM1x1:0 bi ts control whether th e PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM1x1:0 bits control whe ther the output should be set, cleared or to ggle at a compare
match. (See ”Compare Match Output Unit” on page 117.)
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 126.
15.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, obse rve that the maximum
interval betwee n the e xtern al event s must not exceed the r esolutio n of t he count er. If the inter val
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
15.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), th e OCR1A or ICR1 Register
are used to manipulat e th e counte r re so lut ion . I n CT C mode t he coun te r is cleare d to zero when
the counter value (TCNT1) matche s either th e OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =
12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This
mode allows greate r contr ol of the co mpa re mat ch out put f reque ncy. I t also simpl ifie s the o per a-
tion of counting exter nal events.
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The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNT1)
increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)
is cleared.
Figure 15-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reach es the TOP value by either
using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-
ever, changing th e TOP to a value close to BOTTOM when the cou nter is run ning with no ne or a
low prescaler value must be done with care since the CTC mode does not have the double buff-
ering feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the compare match. The counter will then have to count to its max-
imum value (0xFFFF) and wr ap around startin g at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generatin g a wavefor m out put in CT C mod e, t he OC1A ou tput can be se t to toggle it s logica l
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-
quency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The wavefo rm frequency is
defined by the fo llow i ng equation:
The N variable represents th e pr escaler factor (1, 8, 64 , 25 6, or 1024).
As for the Normal mode of op erat ion, the T OV1 Flag is se t in the same tim er clock cycle tha t the
counter counts from MAX to 0x0000.
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 4
Period
2 3
(COMnA1:0 = 1)
fOCnA
fclk_I/O
2N1OCRnA+()⋅⋅
---------------------------------------------------=
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15.9.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation optio n. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared
on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare
Output mode output is set on compar e match and clear ed at BOTTOM. Due to th e single-slope
operation, t he operating fr equency of the f ast PWM mode can be twice as high as the phase cor-
rect and phase and frequency correct PWM modes that use dual-slope operation. This high
frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capaci-
tors), hence reduces total system cost.
The PWM resolut ion f or f ast PWM ca n be fixe d to 8- bit, 9 -bit, o r 10-bit , o r def in ed by ei th er I CR1
or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the
maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =
14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-7. The figure
shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-invert ed an d inver ted PWM ou tput s. The small ho rizonta l lin e m arks on th e TCNT1
slopes represent compare matches between OCR1x a nd TCNT1. The OC1x Interrupt Flag will
be set when a comp ar e m atch occurs.
Figure 15-7. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition
the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A
RFPWM
TOP 1+()log 2()log
-----------------------------------=
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
1 7
Period
2 3 4 5 6 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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or ICR1 is used fo r defining t he TOP value. If o ne of the inte rrupts are enab led, the interr upt han-
dler routine can be used for updating the TOP and compare values.
When changing the TOP value the prog ram must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP
value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low
value when the counter is ru nning wit h none or a low prescaler value, there is a r isk that t he new
ICR1 value written is lower than the current value of TCNT1. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location
to be written anytime. When the OCR1A I/O location is written the value written will be put into
the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done
at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Regis ter for defining TOP work s well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow ge neration of PWM waveforms on the OC1x pins.
Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by se tting the COM1x1:0 to thre e (see Table 15-2 on page 128). The actual
OC1x value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at
the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable re pr esents the pres cale r divider (1, 8, 64, 25 6, or 10 24 ).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output i n the fast PWM mode. If the OCR1x is set equal to BOTT OM (0x0000) the ou t-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only
if OCR1A is used to define the TOP v alue (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is
similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com-
pare unit is enabled in the fast PWM mode.
fOCnxPWM
fclk_I/O
N1TOP+()⋅
-----------------------------------=
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15.9.4 Phase Correct PWM Mode
The ph ase correct Pulse Width Modulation or phase co rrect PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and fre quency correct PWM m ode, based on a du al-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mod e, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while down counting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower m aximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferre d for motor control application s.
The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set
to 0x0003), an d the ma ximu m resolu tio n is 16-b it ( I CR1 or OCR1 A set to MAX). Th e PWM r eso-
lution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing dia gram for the phase correct PWM mode is shown on Figure 15-8. The figure
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes repre sent compare matches betwe en OCR1x and TCNT1. The OC1x Inter-
rupt Flag will be set when a compare match occurs.
Figure 15-8. Phase Correct PWM Mode , Tim in g Dia gr am
RPCPWM
TOP 1+()log 2()log
-----------------------------------=
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
123
8018P–AVR–08/10
ATmega169P
The Timer/Count er Ove rfl ow Flag (TOV1) is se t each t ime th e co unte r r ea ches BO TTOM. When
either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord-
ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the prog ram must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x Registers are written. As the third period shown in Figure 15-8 on page 122 illustrates,
changing the TOP actively while the Timer/Co unter is running in the p hase correct mode ca n
result in an unsymmetrical output. The reason for this can be found in the time of update of the
OCR1x Register. Since the OCR1x update occu rs at TOP, the PWM period starts and ends at
TOP. This implies that the lengt h of the falling slope is determined by the pre vious TOP value,
while the length of the rising slope is determined by the new TO P value. When these two values
differ the two slopes of the period will differ in length. The difference in length gives the unsym-
metrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changin g the TOP value while the Timer/ Counter is running. When using a static
TOP value there are pr actically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to tw o will produce a non-inverted PWM and an inverted
PWM output can be gener at ed by sett in g th e COM1x1: 0 to t hree (Se e Tab l e 15- 3 on page 129).
The actual OC1x value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x
Register at the compare matc h between OCR1x and TCNT1 when the counte r increments , and
clearing (or setting) the OC1 x Register at compare match between OCR1x and TCNT1 when
the counter decreme nts. The PWM fre quency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable re pr esents the pres cale r divider (1, 8, 64, 25 6, or 10 24 ).
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phas e correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
fOCnxPCPWM
fclk_I/O
2NTOP⋅⋅
----------------------------=
124
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ATmega169P
15.9.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pu lse Width Mod ulation, or phase and frequen cy correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TO P to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while
upcounting, and set on the compare match while down counting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM mo de s, th es e mo de s ar e pr eferred for moto r co ntr o l app lica tio ns.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 15-
8 on page 122 and Figure 15-9 on page 125).
The PWM resolution for the phase and frequency correct PWM m ode can be defin ed by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and
the maximum resolution is 16-bit (ICR1 or OCR1A set t o MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). Th e
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 15-9 on page 125. The figure shows phase and fre-
quency correct PWM mo de wh en OCR1A or ICR1 is used t o defi ne TOP. Th e TCNT1 va lue is in
the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-invert ed an d inver ted PWM ou tput s. The small ho rizonta l lin e m arks on th e TCNT1
slopes represent compare matches between OCR1x a nd TCNT1. The OC1x Interrupt Flag will
be set when a comp ar e m atch occurs.
RPFCPWM
TOP 1+()log 2()log
-----------------------------------=
125
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ATmega169P
Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x
Registers are updat ed with the doub le buffer value ( at BOTTO M). Wh en either OCR1A o r ICR1
is used for defining the TO P value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.
The Interrupt Flags can then be used to generate an int er rup t ea ch ti me t he count er re aches the
TOP or BOTTOM value.
When changing the TOP value the prog ram must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
As Figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetri-
cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
Using the ICR1 Regis ter for defining TOP work s well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is a ctively changed by chang ing the TOP value, using t he OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be g enera ted by setting the COM 1x1:0 to three (See Table 15-3 on
page 129). The actual OC1x value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-
ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable re pr esents the pres cale r divider (1, 8, 64, 25 6, or 10 24 ).
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
fOCnxPFCPWM
fclk_I/O
2NTOP⋅⋅
----------------------------=
126
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ATmega169P
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be set to
high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic val-
ues. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A
output will toggle with a 50% duty cycle.
15.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a
clock enable sign al in the following figures. Th e figures include information on whe n Interrupt
Flags are set, and when the OCR1x Register is up dated with the OCR1x buffer value (only for
modes utilizing double buffering). Figure 15-10 shows a timing diagra m for the se tting of OCF1x.
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 15-11 shows the same timing data, but with th e prescaler enabled.
Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
Figure 15-12 on page 127 shows the count sequence close to TOP in various modes. When
using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM.
The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
clk
Tn
(clkI/O/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
127
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ATmega169P
BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at
BOTTOM.
Figure 15-12. Timer/Counter Timing Diagram, no Prescaling
Figure 15-13 shows the same timing data, but with th e prescaler enabled.
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
TOVn (FPWM)
and ICFn (if used
as T OP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clkI/O
TOVn (FPWM)
and ICFn (if used
as T OP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
128
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15.11 16-bit Timer/Counter Register Description
15.11.1 TCCR1A – Timer/Counter1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC 1B pin mu st be set in or de r to ena ble the out put dr ive r.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting. Table 15-1 shows the COM1x1:0 bit functionality when the
WGM13:0 bits are set t o a Normal or a CTC mode (non-PWM).
Table 15-2 shows the COM1x1 :0 bit functionality when the WGM13:0 bits are set to the fast
PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ig nored, but the set or clear is done at TOP. See ”Fast PWM
Mode” on page 120. for more details.
Bit 7 6 5 4 3 2 1 0
(0x80) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 15-1. Compare Output Mode, non-PWM
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on Compare Match.
10
Clear OC1A/OC1B on Compare Match (Set output to
low level).
11
Set OC1A/OC1B on Compare Match (Set output to
high level).
Table 15-2. Compare Output Mode, Fast PWM(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
01
WGM13:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
F or all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
10
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BO TTOM (non-inverting mode)
11
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BO TTOM (inv erting mode)
129
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Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
correct or the ph as e an d freq u en cy co rr ect , PW M m od e.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
”Phase Correct PWM Mode” on page 122. for more details.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13: 2 bit s found in t he TCCR1B Register, these bit s contr ol the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 15-4 on page 130. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. (See ”Modes of Operation” on page
118.)
Table 15-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port ope ration, OC1A/OC1B disconnected.
01
WGM13:0 = 9 or 11: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
F or all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
10
Clear OC1A/OC1B on Compare Match when up-
counting. Set OC1A/OC1B on Compare Match when
down counting.
11
Set OC1A/OC1B on Compare Match when up-
counting. Clear OC1A/OC1B on Compare Match
when down counting.
130
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ATmega169P
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
15.11.2 TCCR1B – Timer/Counter1 Control Register B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal va lued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects wh ich edge on the Input Captur e pin (ICP1) that is used to trigg er a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (pos itive) edge will trigger the capture.
Table 15-4. Waveform Generation Mode Bit Description(1)
Mode WGM13 WGM12
(CTC1) WGM11
(PWM11) WGM10
(PWM10) Timer/Counter Mode of
Operation TOP Update of
OCR1x at TOV1 Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase Correct, 10-b it 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCR1A Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF BO T TOM T OP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF BO T TOM T OP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM T OP
81000
PWM, Phase and Frequency
Correct ICR1 BOTTOM BOTTOM
91001
PWM, Phase and Frequency
Correct OCR1A BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM
12 1 1 0 0 CTC ICR1 Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICR1 BOTT OM TOP
15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP
Bit 76543210
(0x81) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
131
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ATmega169P
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this int errupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Re gister), the ICP1 is disconnected and consequen tly the Input Ca p-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure
15-10 on page 126 and Figure 15-11 on page 126.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
15.11.3 TCCR1C – Timer/Counter1 Control Register C
• Bit 7 – FOC1A: Force Output Compare for Unit A
• Bit 6 – FOC1B: Force Output Compare for Unit B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
Table 15-5. Clock Select Bit Description
CS12 CS11 CS10 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
I/O/1 (No prescaling)
010clk
I/O/8 (From prescaler)
011clk
I/O/64 (From prescaler)
100clk
I/O/256 (From prescaler)
101clk
I/O/1024 (From prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.
Bit 76543210
(0x82) FOC1A FOC1B – – – – – – TCCR1C
Read/Write R/W R/W R R R R R R
Initial Value 0 0 0 0 0 0 0 0
132
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ATmega169P
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
15.11.4 TCNT1H and TCNT1L – Timer/Counter1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing 16-bit
Registers” on page 109.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks ( rem oves) the comp ar e matc h on the followin g timer clock
for all compare units.
15.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
15.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1 ). A match can be used to generate an Output Com pare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compa re Register s are 16-b it in size. To ensure t hat both the high and low bytes are
written simultaneously when th e CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEM P). This temporary register is shared by all the other
16-bit register s. See ”Accessing 16-bit Registers” on page 109.
Bit 76543210
(0x85) TCNT1[15:8] TCNT1H
(0x84) TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x89) OCR1A[15:8] OCR1AH
(0x88) OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x8B) OCR1B[15:8] OCR1BH
(0x8A) OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
133
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15.11.7 ICR1H and ICR1L – Input Capture Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or opt ionally on t he Analo g Comparat or o utput f or Timer/ Counter 1). The Input Capture
can be used for defining the counter TOP value.
The Input Captur e Registe r is 16-bit in size . To en sure tha t both the high and low byt es are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). Th is temporary register is shared by all the other 16-bit
registers. See ”Accessing 16-bit Registers” on page 109.
15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), th e Timer/Counter1 I nput Capture interru pt is enabled. The co rresponding Interru pt
Vector (See ”Interrupts” on page 56.) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), th e Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See ”Interrupts” on page 56.) is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), th e Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See ”Interrupts” on page 56.) is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See ”Interrupts” on page 56.) is executed when the TOV1 Flag, located in TIFR1, is set.
Bit 76543210
(0x87) ICR1[15:8] ICR1H
(0x86) ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x6F) ––ICIE1–– OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGM1 3:0 t o be used as the TOP value, the ICF1 F lag is set when the coun-
ter reaches the TO P value.
ICF1 is automatically cleared when the Input Ca pture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by wr iting a logic one to its bit location.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to Table 15-4 on pag e 130 for the TOV1
Flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Bit 76543210
0x16 (0x36) ––ICF1–– OCF1B OCF1A TOV1 TIFR1
Read/Write R R R/W R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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16. Timer/Counter0 and Timer/Counter1 Prescalers
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
16.1 Prescaler Reset
The prescaler is free running, that is, operates independently of the Clock Select logic of the
Timer/Counter, and it is shared b y Timer/Counter1 and Time r/Counter0. Since the prescale r is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled a nd clo cked by th e prescale r ( 6 > CSn2: 0 > 1). The numb er of syst em clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchron izing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
16.2 Internal Clock Source
The Timer/Counter can be clocked d ire ctly by the system clock ( by se ttin g the CSn2 :0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or
fCLK_I/O/1024.
16.3 External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the p in syn chro nization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 16-1
on page 135 shows a functional equivalent block diagram of the T1/T0 synchronization and
edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 16-1. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been app lied to the T1/T0 pin to the counter is updated.
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clkI/O
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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a ri sk that a false Tim er/Counter clo ck pulse is gene rated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) give n a 50/50% duty cycle. Since th e edge detecto r uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, du e to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an exter nal clock source is less than fclk_I/O/2.5.
An external clock source can not be presca le d.
Figure 16-2. Prescaler for Timer/Counter0 and Timer/ Counter1(1)
Note: 1. The synchroni zation logic on the input pins (T1/T0) is shown in Figure 16-1 on page 135.
PSR10
Clear
clk
T1
clk
T0
T1
T0
clk
I/O
Synchronization
Synchronization
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16.4 Register Description
16.4.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counte r Synchronization Mode
Writing the TSM b i t to on e a ctiva te s the Tim er/Counter Synch r on iza tio n mo d e. In th is m o de , th e
value that is written t o the PSR2 and PSR1 0 bits is kept, hence keeping th e correspond ing pres-
caler reset signals asserted. This ensures that the correspo nding Timer/Co unte rs are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,
and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared im mediately by har dware, except if the TSM bit is set. Note tha t Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM – – – – – PSR2 PSR10 GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The
main features are:
•Single Compare Unit Counter
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Frequency Generator
•10-bit Clock Prescaler
•Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
17.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual
placement of I/O p ins, re fer to Fig ure 1 -1 on pa ge 2. CPU accessible I/O Registers, including I/O
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the Section 17.10 ”8-bit Timer/Counter Register Description” on page 153.
Figure 17-1. 8-bit Timer/Counter Block Diagram
17.1.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter-
rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
Timer/Counter
DATA BUS
=
TCNTn
Waveform
Generation OCnx
= 0
Control Logic
= 0xFF
TOPBOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCnx
(Int.Req.)
Synchronization Unit
OCRnx
TCCRnx
ASSRn
Status flags
clkI/O
clkASY
Synchronized Status flags
asynchronous mode
select (ASn)
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clkTn
clkI/O
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(TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2).
TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Cou nter uses to incremen t (or decrement) its value. The Timer/ Counter is inac-
tive when no clo ck source is selected. The out put from th e Clock Select logic is referre d to as the
timer clock (clkT2).
The double buffered Outpu t Compare Register (OCR2A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC2A). See ”Output
Compare Unit” on page 140. for details. The compare match event will also set the Compare
Flag (OCF2A) which can be used t o generate an Output Compar e interrupt request.
17.1.2 Definitions
Many register and bit references in this document a re written in general form. A lowe r case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, that is, TCNT2 for accessing
Timer/Counter 2 counter value and so on.
The definitions in Table 17-1 are also used extensively throughout the section.
17.2 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. W hen the A S2
bit in the ASSR Register is written to logic one, th e clock sour ce is taken fr om the Timer /Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see ”ASSR
– Asynchronous Status Register” on page 156. For details on clock sources and prescaler, see
”Timer/Counter Prescaler” on page 152.
17.3 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
17-2 on page 140 shows a block diagram of the counter and its surrounding environment.
Table 17-1. Timer/Counter Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches t he TOP when it become s equa l to the highe st value in th e
count sequence. The TOP valu e can be assigned to be the fixed value 0xFF
(MAX) or the valu e stored in the OCR2A Register. T he assignment is d ependent
on the mode of operation.
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Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or de cre m en t TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkT2Timer/Counter clock.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mo de o f oper at ion us ed, the cou nt er is cleared , in cr eme nted , o r decr em ent ed
at each timer clock (clkT2). clkT2 can be generated from an external or inte rnal clock source,
selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over ) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A). There are close connections between how the
counter behaves (counts) and how waveforms a re generated on the Output Compare output
OC2A. For more details about advanced counting sequences and waveform generation, see
”Modes of Operation” on page 143.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
17.4 Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match will set
the Output C ompare Flag (O CF2A) at the next tim er clock cycle. If en abled (OCIE2A = 1) , the
Output Compare Fl ag genera tes an Outp ut Compare int errupt. The OCF2A Flag is aut omatically
cleared when the interrupt is executed. Alternatively, the OCF2A Flag can be cleared by soft-
ware by writing a logical one to its I/O bit location. The Waveform Generator uses the match
signal to generate an output according to operating mode set by the WGM21:0 bits and Com-
pare Output mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform
Generator for handling the special cases of the ext reme values in some modes of op eration
(”Modes of Operation” on page 143).
Figure 17-3 on page 141 shows a block diagram of the Output Compare unit.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
topbottom
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
I/O
clk
Tn
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Figure 17-3. Output Compare Unit, Block Diagram
The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Nor mal and Clear Timer on Compare (CTC ) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare
Register to either top o r bottom of the counting sequence . The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is
disabled the CPU will access the OCR2A directly.
17.4.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2A) bit. Forc ing compare match will not s et the
OCF2A Flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare
match had occurred (the COM2A1:0 bit s settings define whether the OC2A pin is set, cleared or
toggled).
17.4.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial-
ized to the same value as TCNT2 wit hout trigg ering an inte rrupt when t he Timer/Coun ter clock is
enabled.
17.4.3 Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the Output Compare unit,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do no t write t he TCNT2 value eq ual to BOTTOM whe n the co unter is down
counting.
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnx1:0
bottom
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The setup of the OC2 A should be perfo rmed before setting th e Data Direction Register for th e
port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com-
pare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when
changing between Wa veform Generation modes.
Be aware that the COM2A1:0 bits are not double buffered together with the compare value.
Changing the COM2A1:0 bits will take effect immediately.
17.5 Compare Match Output Unit
The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator
uses the COM2A1:0 bits for defining th e Output Compare (OC2A) state at the next compare
match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 17- 4 shows a sim-
plified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits,
and I/O pins in the fi gur e are shown in bo ld. On ly the par ts of t he gener al I/O Po rt Contr ol Regis-
ters (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the
OC2A state, th e re fe re nc e is for th e int er na l OC2 A Regi ste r, not th e OC2 A pin .
Figure 17-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform
Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is vis-
ible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2A state before the
output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of
operation. See ”8-bit Timer/Counter Register Description” on page 153.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BUS
FOCnx
clk
I/O
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17.5.1 Compare Output Mode and Waveform Generation
The Waveform Generat or uses the COM2A1: 0 bits differe ntly in nor mal, CTC, and PWM modes.
For all modes, setting the COM2A1:0 = 0 tells the Wave form Generator that no a ction on the
OC2A Register is to be performed on the next compare match. For compare output actions in
the non-PWM modes refer to Table 17-3 on page 154. For fast PWM mode, refer to Table 17-4
on page 154, and for pha se co rr ect PWM refer to Table 17-5 on page 154.
A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2A strobe bits.
17.6 Modes of Operation
The mode of o perat ion , th at is, the beh avior of t he Timer/ Cou nter an d the Ou t put Com par e pins,
is defined by the combin ation of the Wavef orm Generat ion mode (WGM 21:0) an d Compare Out-
put mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM2A1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM 2A1: 0 bit s co ntro l whet h er th e o ut pu t sh ould be set, clear ed , or to gg led at
a compare match. ( See ”Compare Match Outp ut Unit” on page 142.)
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 148.
17.6.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflo w interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compar e u nit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou t-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
17.6.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to
manipulate the count er resolut io n. In CTC mode the counter is clear ed to zero wh en the counter
value (TCNT2) matches the OCR2A. The OCR2A de fines the top value for the counter, hence
also its resolution. This m ode allows greater control of the compare ma tch output frequency. It
also simplifies the op e ra tio n of coun tin g exte rn al ev en ts.
The timin g diagram for the CT C mode is show n in Figure 17-5 on page 144. The counter value
(TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then coun-
ter (TCNT2) is clea re d.
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Figure 17-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is
running with none or a low prescaler value must be done with care since the CTC mode does
not have the double buffering feature. If the new value written to OCR2A is lower than the cur-
rent value of TCNT2, the counter will miss the compare match. The counter will then have to
count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match
can occur.
For generatin g a wavefor m out put in CT C mod e, t he OC2A ou tput can be se t to toggle it s logica l
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC2A =
fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
17.6.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-
gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In
non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare
match between TCNT2 and OCR2A, and set at BOTTOM. In inverting Compare Outpu t mode,
the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slop e operation. This hig h frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
TCNTn
OCnx
(Toggle)
OCnx Interrupt Flag Set
1 4
Period
2 3
(COMnx1:0 = 1)
fOCnx
fclk_I/O
2N1OCRnx+()⋅⋅
--------------------------------------------------=
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PWM mode is shown in Figure 17-6. The TCNT2 value is in the timing diagram shown as a his-
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. Th e small horizo ntal line marks on th e TCNT2 slopes represe nt compare
matches between OCR2A and TCNT2.
Figure 17-6. Fast PWM Mode, Timing Diagram
The Timer/Counter O verflow Flag (TOV2) is set each t ime the coun ter reache s MAX. If the inte r-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM2A1:0 to three (See Table 17-4 on page 154). The actual
OC2A value will only be visible on the port pin if the data direction for the port pin is set as out-
put. The PWM wave form is generat ed b y settin g (or clear ing) t he O C2A Regist er a t the compa re
match between OCR2A and TCNT2 , and clearing (or setting) the OC2A Register at the timer
clock cycle the counter is cleare d (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases wh en generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0
bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2A to toggle its logical level on ea ch compare match (COM2A1:0 = 1). The wave form
generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This fea-
ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
fOCnxPWM
fclk_I/O
N256⋅
------------------=
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17.6.4 Phase Correct PWM Mode
The phase c orrect PWM mode (WGM21:0 = 1) pr ovides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-
inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match
between TCNT2 and OCR2A while upcounting, and set on the compare match while down-
counting. In inverting Outp ut Compar e mod e, the oper ation is in vert ed. The dual- slope o perat ion
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the counter
reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one
timer clock cycle . The timing di agram for t he phase correct PWM mod e is shown on Figure 1 7-7.
The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-in verted and inverted PWM outputs. The small horizontal
line marks on the TC NT 2 slo pe s re pr es en t com p ar e ma tc he s be twe e n OC R 2A an d TCNT 2 .
Figure 17-7. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Counter Over flow Flag (TOV2) is set each time the counter reache s BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can b e genera ted by setti ng the COM2A1 :0 t o three (See Table 17-5 on page 154).
The actual OC2A value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated b y clearing (or se tting) the OC2A Reg ister at the
compare match between OCR2A and TCNT2 when the counter increments, and setting (or
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Update
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clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter
decrements. The PWM frequency for the output when using ph ase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases wh en generating a PWM
waveform output in the phase correct PWM mo de. If the OCR2A is set equal to BO TTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 17-7 on page 146 OCn has a transition from high to low
even though there is no Compare Match. The point of this tr ansition is to guar antee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, lik e in Figure 17-7 on p age 146. When the OCR2 A v alue
is MAX the OCn pin value is the same as the result of a down-counting compare match. To
ensure symmetry around BOTTOM the OCn value at MAX mu st corr espond to the result of an
up-counting Compare Match.
• The timer starts counting from a v alue higher than the one in OCR2A, and for that reason
misses the Compare Match and hence th e OCn change that w ould ha v e happe ned on the w a y
up.
fOCnxPCPWM
fclk_I/O
N510⋅
------------------=
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17.7 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2)
is therefore shown as a clock en able signal. In asynchronous mode, clkI/O should be replaced by
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing Diagram, no Prescaling
Figure 17-9 shows the same timing data, but with the prescaler enabled.
Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 17-10 on page 149 shows the setting of OCF2A in all modes exce pt CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
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Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)
Figure 17-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
OCFnx
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
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17.8 Asynchronous operation of the Timer/Counter
17.8.1 Asynchronous Operation of Timer/Counter2
When Timer/Coun ter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2.
b. Select clock source by setting AS2 as appropriate.
c. Write new values to TCNT2, OCR2A, and TCCR2A.
d. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
e. Clear the Timer/Counter2 Interrupt Flags.
f. Enable interrupts, if needed.
• The CPU main clock frequency must be more than four times the Oscillator frequency.
• When writing to one of the re gisters TCNT2, OCR2 A, or T CCR2A, the v a lue is tra nsferred to a
tempora ry register, and latched after two positive edges on TOSC1. The user should not write
a new value before the contents of the temporary register have been transferred to its
destination. Each of the three mentioned registers have their individual temporary register,
which means that, fo r exa mple, writing to TCNT2 does n ot disturb an OCR2A write in progress .
To detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented.
• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,
OCR2A, or TCCR2A, the user must wait until the written register has been updated if
Timer/Counter2 is used to wak e up the device. Otherwise, the MCU will enter sleep mode
bef ore the changes are eff ectiv e. This is particularly important if the Output Compar e2 interrupt
is used to wake up the device, since the Output Compare function is disabled during writing to
OCR2A or TCNT2. If t he write cycle is not finished, and the MCU enters sle ep mode bef ore t he
OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the
MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction
mode, precautions must be taken if the user wants to re-enter one of these modes: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake -up and re-
entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device
will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or
ADC Noise Reduction mode is suffi cient, the following algorithm can be used to ensure that
one TOSC1 cycle has elapsed:
a. Write a value to TCCR2A, TCNT2, or OCR2A.
b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the 32.768 kHz Oscillator f or Timer/Counter2 is
always running, except in Power-down and Standby modes. After a Power-up Reset or wake-
up from Power-down or Standby mode, the user should be a w are of the fact that this Oscillator
might take as long as one second to stabilize. The user is advised to wait for at least one
second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby
mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up
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from Power-down or Standby mode due to unstable cloc k signal upon start-up, no matter
whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place f or e v ery rising T OSC1 edge. When waking up from Powe r-sa v e mode, and the I/O cloc k
(clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep)
until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from P ower-
sav e mode is essentially unpr edictab le, as it depends on the w ak e-up time. The recommended
procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2A or TCCR2A.
b. Wait for the corresponding Update Busy Flag to be cle ared.
c. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchroniz ed to the processor clock.
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17.9 Timer/Counter Prescaler
Figure 17-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main
system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be conne cted between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. If
applying an external clock on TOSC1, the EXCLK bit in ASSR must be set.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,
clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre-
dictable prescaler.
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clkI/O clkT2S
TOSC1
AS2
CS20
CS21
CS22
clkT2S
/8
clkT2S
/64
clkT2S
/128
clkT2S
/1024
clkT2S
/256
clkT2S
/32
0
PSR2
Clear
clkT2
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17.10 8-bit Timer/Counter Register Description
17.10.1 TCCR2A – Timer/ Co un t er Cont rol Register A
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is o nly active when th e WGM bits specify a n on-PWM mode. Ho wever, for ensu r-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A1:0 bits that determines t he effect of the forced compare .
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the co unting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See Table 17-2 and ”Modes of Operation”
on page 143.
Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
However, the functionality an d location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM2A1 :0: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected
to. However, not e that the Data Dire ction Register ( DDR) bit correspondi ng to OC2A pin must be
set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM21:0 bit setting. Table 17- 3 on page 154 shows the CO M2A1:0 bit functionality when the
WGM21:0 bits are set to a normal or CTC mode (non-PWM).
Bit 765 4 3210
(0xB0) FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 TCCR2A
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 17-2. Waveform Generation Mod e Bit Des crip tio n(1)
Mode WGM21
(CTC2) WGM20
(PWM2) Timer/Counter Mode of
Operation TOP Update of
OCR2A at TOV2 Flag
Set on
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR2A Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM MAX
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Table 17-4 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 144
for more details.
Table 17-5 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to phase cor-
rect PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at T OP. See ”Phase Correct PWM Mode” on
page 146 for more details.
Table 17-3. Compare Output Mode, non-PWM Mode
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 Toggle OC2A on compare match.
1 0 Clear OC2A on compare match.
1 1 Set OC2A on compare match.
Table 17-4. Compare Output Mode, Fast PWM Mode(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
01Reserved
10
Clear OC2A on compare match, set OC2A at BOTTOM
(non-inverting mode).
11
Set OC2A on compare match, clear OC2A at BOTTOM
(inverting mode).
Table 17-5. Compare Output Mode, Phase Correct PWM Mode(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
01Reserved
10
Clear OC2A on compare match when up-counting. Set OC2A on
compare match when down counting.
11
Set OC2A on compare match when up-counting. Clear OC2A on
compare match when down counting.
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• Bit 2:0 – CS22:0: Clock Select
The three Clock Se lect bits select the cl ock source to be use d by the Timer/Co unter, see Table
17-6.
17.10.2 TCNT2 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2A Register.
17.10.3 OCR2A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2 ). A match can be used to generate an Output Com pare interrupt, or to
generate a waveform output on the OC2A pin.
Table 17-6. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
T2S/(No prescaling)
010clk
T2S/8 (From prescaler)
011clk
T2S/32 (From prescaler)
100clk
T2S/64 (From prescaler)
101clk
T2S/128 (From prescaler)
110clk
T2S/256 (From prescaler)
111clk
T2S/1024 (From prescaler)
Bit 76543210
(0xB2) TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0xB3) OCR2A[7:0] OCR2A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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17.10.4 TIMSK2 – Timer/Counter2 Interrupt Mask Register
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counte r2 Compare M a tch A interrup t is en ab le d. T h e co rr es po nd in g interrupt is e x e cu te d
if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/ Coun te r2 occurs, t ha t is, whe n t he TOV2 bit is set in th e T imer /Count er 2 Inte r-
rupt Flag Register – TIFR2.
17.10.5 TIFR2 – Timer/Counter2 Interrupt Flag Register
• Bit 1 – OCF2A: Out put Compare Flag 2 A
The OCF2A bit is set ( one) when a compare matc h occurs between the Timer/Counter2 and the
data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counte r2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Inter rupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflo w occurs in Time r/Coun te r2 . TO V2 is clear ed by har d-
ware when executing the corre spon ding int erru pt han dling vecto r. Alt ernat ively, TOV2 is clear ed
by writing a logic one to th e flag. When t he SREG I- bit, TO IE2 A (Timer /Co unte r2 Ove rfl ow Inte r-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes coun ting direction at 0x00.
17.10.6 ASSR – Asynchronous Status Register
• Bit 4 – EXCLK: Enable External Clock Input
When EXCLK is written to one, an d asynchronous clock is select ed, the e xternal clo ck input buf-
fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
Bit 76543210
(0x70) –––––– OCIE2A TOIE2 TIMSK2
Read/Write RRRRRRR/WR/W
Initial Value00000000
Bit 76543210
0x17 (0x37) –––––– OCF2A TOV2 TIFR2
Read/Write RRRRRRR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0xB6) – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB ASSR
Read/Write R R R R/W R/W R R R
Initial Value 0 0 0 0 0 0 0 0
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32 kHz crystal. Writing to EXCLK should be done before asynchronou s operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is
written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pi n. When the value of AS2 is cha nged, the contents of TCN T2, OCR2A, and
TCCR2A might be corr up te d.
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchrono usly and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated f rom the tem porary st orage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Re gister2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading
TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the tem-
porary storag e register is read.
17.10.7 GTCCR – General Timer/Counter Control Register
• Bit 1 – PSR2: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is op erating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the ”Bit 7 – TSM: Timer/Counter Syn-
chronization Mode” on pag e 137 for a description of the Timer/Counter Synchronization mode.
Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM – – – – – PSR2 PSR10 GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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18. SPI – Serial Peripheral Interface
18.1 Features
•Full-duplex, Three-wire Synchronous Data Tr ansfer
•Master or Slave Operation
•LSB Fir st or MSB First Data Transfer
•Seven Programmable Bit Rates
•End of Transmission Interrupt Fl ag
•Write Collision Flag Protection
•Wake-up from Idle Mode
•Double Speed (CK/2) Master SPI Mode
18.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega169P and peripheral devices or between several AVR devices.
The PRSPI bit in ”PRR – Power Redu ction Register” on page 45 must be written to zero to
enable SPI module.
Figure 18-1. SPI Block Diagram(1)
Note: 1. Ref er to Figure 1-1 on page 2, and Table 13-6 on page 74 for SPI pin placement.
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
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The interconnect ion between Mast er and Slave CPUs with SPI is shown in Figure 18-2. The sys-
tem consists of two shift Register s, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective shift Regist ers, and the Master generates
the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-
ter to Slave on t he Ma ster Out – Slave In, M OSI, line , and f rom Slave t o Maste r on th e M aste r In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, an d the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this sta te, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Inte rrupt Enable bit, SPIE , in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 18-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the minimum low and high periods should be:
Low period: longer than 2 CPU clock cycles.
High period: longer than 2 CPU clock cycles.
SHIFT
ENABLE
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When the SPI is enab led, th e data di rection of the MO SI, MISO , SCK, and SS pins is overrid den
according to Table 18-1. For more details on automatic port overrides, refer to ”Alternate Port
Functions” on page 71.
Note: 1. See ”Alternate Functions of Port B” on page 74 for a detailed description of how to define the
direction of the user defined SPI pi ns.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be re placed by the
actual data direction bits for these pins. For example if MOSI is placed on pin PB5, replace
DD_MOSI with DDB5 and DDR_SPI with DDRB.
Table 18-1. SPI Pin Overrides(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Input
MISO Input User Defined
SCK User Defined Input
SS User Defined Input
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Note: 1. ”About Code Examples” on page 10
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out SPDR,r16
Wait_Transmit:
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
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The following code examples show how to initialize the SPI as a Slave and how to perform a
simple reception.
Note: 1. ”About Code Examples” on page 10.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output, all others input
ldi r17,(1<<DD_MISO)
out DDR_SPI,r17
; Enable SPI
ldi r17,(1<<SPE)
out SPCR,r17
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
; Read received data and return
in r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return Data Register */
return SPDR;
}
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18.3 SS Pin Functionality
18.3.1 Slave Mode
When the SPI is configured as a Slave, th e Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin
is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
18.3.2 Master Mod e
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured a s an inpu t, it m ust be held h igh to ensu re Mast er SPI operat ion. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starti ng to se nd data t o it. To avoid bus con t ention , th e SPI syst em takes t he fo llowing
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enab led, and t he I-bit in SREG is
set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-ena ble SPI Master
mode.
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18.4 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
18-3 and Figure 18-4. Data bits are shifted out and latch ed in on op posite ed ges of the SCK sig-
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 18-3 on page 165 and Table 18-4 on page 165, as done below:
Figure 18-3. SPI Transfer Format with CPHA = 0
Figure 18-4. SPI Transfer Format with CPHA = 1
Table 18-2. CPOL Functionality
Leading Edge Trailing eDge SPI Mode
CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0
CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1
CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2
CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3
Bit 1
Bit 6
LSB
MSB
SCK (CPOL = 0)
mode 0
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 1)
mode 2
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
MSB first (DORD = 0)
LSB first (DORD = 1)
SCK (CPOL = 0)
mode 1
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 1)
mode 3
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
MSB first (DORD = 0)
LSB first (DORD = 1)
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18.5 Register Description
18.5.1 SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to on e, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable S PI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 18-3 on page 164 and Figure 18-4 on page 164 for an example. The
CPOL functionality is summarized below:
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) ed ge of SCK. Refer to Figure 18-3 on page 16 4 and Figure 18-4 on page 164 for an
example. The CPOL functionality is summarized below:
Bit 76543210
0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 18-3. CPOL Functionality
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising
Table 18-4. CPHA Functionality
CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
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• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits contr ol the SCK ra te of t he dev ice configur ed as a Mast er. SPR1 and SPR0 ha ve
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is
shown in the following table:
18.5.2 SPSR – SPI Status Register
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generate d if SPIE in
SPCR is set and global interru pts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and t he SPI F b it) ar e cleare d b y fi r st r eading t h e SPI Stat u s Regi ste r wit h WCOL set ,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserve d and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 18-5). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4
or lower.
The SPI interface on the ATmega169P is also used for program memory and EEPROM down-
loading or uploading. See page 310 for serial program ming and verification.
Table 18-5. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
fosc/4
001
fosc/16
010fosc/64
011fosc/128
100
fosc/2
101fosc/8
110fosc/32
111
fosc/64
Bit 76543210
0x2D (0x4D) SPIF WCOL – – – – – SPI2X SPSR
Read/Write RRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
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18.5.3 SPDR – SPI Data Register
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shif t Reg i ste r Rece ive bu ffer to be read.
Bit 76543210
0x2E (0x4E) MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial ValueXXXXXXXXUndefined
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19. USART
19.1 Features
•Full Duplex Operation (Independent Serial Rece ive and Transmit Registers)
•Asynchronous or Synchronous Op eration
•Master or Slave Clocked Synchronous Operation
•High Resolution Baud Rate Generator
•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
•Odd or Even Parity Gen e ration and Parity Check Supporte d by Hardware
•Data OverRun Detection
•Framing Error Detection
•Noise Filterin g Includes False Start Bit Detection and D igital Low Pass Filte r
•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
•Multi-processor Communication Mode
•Double Speed Asynchronous Communication Mode
19.2 Overview
The Universal Syn chronous and Asynchronous serial Re ceiver and Transmitter (USART) is a
highly flexible serial communication device.
The PRUSART0 bit in ”PRR – Power Reduction Register” on page 45 must be written to zero to
enable USART0 module.
A simplified block diagram of the USART Tr ansm itter is shown in Fi gure 19 -1 on pag e 169. CPU
accessible I/O Registers and I/O pins are shown in bold.
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Figure 19-1. USART Block Diagram(1)
Note: 1. Ref er to Figure 1-1 on page 2 , Table 13-13 on page 80, and Table 13-7 on page 76 for USART
pin placement.
The dashed boxe s in the blo ck diagr am se parat e th e thr ee main pa rts of the USART ( list ed fro m
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave ope ra tion, a nd th e b au d rat e gener at or. The XCK (T ra nsfer Clo ck) pin is o nly
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register , Par it y Ge ner at or a nd Cont rol lo gic f or h an dling d iff er ent seria l f r ame for mats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception . In addition to the recovery
units, the Receiver includes a Parity Che cker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver
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19.2.1 AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers.
• Baud Rate Generation.
• Transmitter Operation.
• Transmit Buffer Functionality.
• Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
• A second Buff er Register has been added. The tw o Buff er Registers oper ate as a circula r FIFO
buffe r. Theref ore the UDRn must on ly be read once for each incoming data! More important is
the fact that the Error Flag s (FEn and DORn) and the ninth data bit (RXB8n) are buffered with
the data in the receive buffer. Therefore the status bits must always be read before the UDRn
Register is read. Otherwise the error status will be lost since the buffer state is lost.
• The Receiver Shift Register can now act as a third buff er level. This is done by allowing the
received data to remain in the serial Shift Register (see Figure 19-1 on page 169) if the Buffer
Registers are full, until a new start bit is detected. The USART is therefore more resistant to
Data OverRun (DORn) error cond itio ns.
The following control bits have cha nged name, but have same functionalit y and register locatio n:
• CHR9 is changed to UCSZn2.
• OR is changed to DORn.
19.3 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchrono us, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCK pin is only active when using synchronous mode.
Figure 19-2 on page 171 shows a block diagram of the clock generation logic.
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Figure 19-2. Clock Generation Logic, Block Diagram
Signal description:
txclk Transmitter clock (Internal Signal).
rxclk Receiver base clock (Internal Signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave
operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc XTAL pin frequency (System Clock).
19.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The descrip tion in this section refers to Figure 19-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or bau d rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The Transmitter divides th e
baud rate g enerato r clock outpu t by 2, 8 or 16 d epending on mode. Th e baud r ate genera tor ou t-
put is used directly by the Re ceiver’s clo c k and data recovery units. Howe ver, th e re co very unit s
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCK bits.
Table 19-1 on page 172 con tains equa tions for calcula ting th e bau d rat e (in bit s p er second ) and
for calculating the UBRRn value for each mode of operation using an internally generated clock
source.
Prescaling
Down-Counter /2
UBRR
/4 /2
fosc
UBRR+1
Sync
Register
OSC
XCK
Pin
txclk
U2X
UMSEL
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK rxclk
0
1
1
0
Edge
Detector
UCPOL
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Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps) .
fOSC System Oscillator clock frequency.
UBRRn Contents of the UBRRHn and UBRRLn Regi sters, (0-4095).
Some examples of UBRRn values for some system clock frequencies are found in Table 19-4 on
page 190.
19.3.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will red uce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchro nous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
19.3.3 Exte rnal Clock
External clocking is used by the synchronous sl ave modes of operation. The description in this
section refers to Figure 19-2 on page 171 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector b efore it can be used by the Transmitter and Rece iver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
Note that fosc depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
Table 19-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating Baud
Rate(1) Equation for Calculati ng UBRRn
Value
Asynchronous Nor mal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
BAUD fOSC
16 UBRRn1+()
------------------------------------------=
UBRRnfOSC
16BAUD
------------------------1–=
BAUD fOSC
8UBRRn1+()
---------------------------------------=
UBRRnfOSC
8BAUD
-------------------- 1–=
BAUD fOSC
2UBRRn1+()
---------------------------------------=
UBRRnfOSC
2BAUD
-------------------- 1–=
fXCK
fOSC
4
-----------
<
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19.3.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either cloc k input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
Figure 19-3. Synchronous Mode XCK Timing.
The UCPOLn bit UCRSC selects which X CK clock edge is used for data sampling and which is
used for data change. As Figure 19-3 shows, when UCPOLn is zero the data will be changed at
rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
19.4 Frame Formats
A serial frame is define d to be o ne char acter of da ta bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as va lid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts w ith the s tart bit f ollowe d by t he leas t signif icant da ta b it. Then the next da ta bit s,
up to a total of nin e, are succeed ing, endin g with t he most sig nificant bit. If enab led, the pa rity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 19-4 on page 174 illustrates the possible combinations of the frame forma ts. Bits inside
brackets are optional.
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample
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Figure 19-4. Frame Formats
St Start bit, always low.
(n) Data bits (0 to 8).
PParity bit. Can be odd or even.
Sp Stop bit, always high.
IDLE No transfers on the communication line (RxD or TxD). An IDLE line must
be high.
The frame format used by the USART is set by the UCSZn2:0, UPM1n:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitt er use t he same se tting. Not e that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USART Character SiZe (UCSZn 2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPM1n:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores
the second stop bit. An FEn (Frame Error FEn) will therefore only be detected in the cases
where the first stop bit is zer o.
19.4.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
Peven Parity bit using even parity.
Podd Parity bit using odd parity.
dnData bit n of the character.
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)
FRAME
Peven dn1–…d3d2d1d00
Podd
⊕⊕⊕⊕⊕⊕
dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕
=
=
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19.5 USART Initialization
The USART has to be initialized bef ore any communication can take place. The init ialization pro-
cess normally consists of setting the baud rate, setting frame format and enabling the
Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
Before doing a re -in itia liza tio n with cha ng ed bau d rat e o r fr ame form at , be sure th at ther e are no
ongoing transmissions dur ing the per iod the reg ist ers are ch ang ed. Th e TXCn Flag can be used
to check that the Transmitter has completed all transfers, and the RXCn Flag can be used to
check that there are no unread data in the receive buffer. Note that the TXCn Flag must be
cleared befo re eac h tra n s m issio n (b ef or e UDRn is written) if it is used for this purpose.
The following simple USART initializatio n code examples show one assembly and one C func-
tion that are equal in functionality. The examples assume asynchronous operation using polling
(no interru pts enable d) and a fixed fr ame format . The bau d rate is given as a funct ion paramet er.
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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16
Registers.
Note: 1. See ”About Code Examples” on page 10.
More advanced initialization ro ut ines can be mad e th at include fr ame forma t a s para met ers , dis-
able interrupts and so on. However, many applications use a fixed setting of the baud and
control registers, and for these types of applications the initialization code can be placed directly
in the main routine, or be combined with initialization code for other I/O modules.
Assembly Code Example(1)
USART_Init:
; Set baud rate
sts UBRRH0, r17
sts UBRRL0, r16
; Enable receiver and transmitter
ldi r16, (1<<RXEN0)|(1<<TXEN0)
sts UCSR0B,r16
; Set frame format: 8data, 2stop bit
ldi r16, (1<<USBS0)|(3<<UCSZ00)
sts UCSR0C,r16
ret
C Code Example(1)
#define FOSC 1843200// Clock Speed
#define BAUD 9600
#define MYUBRR FOSC/16/BAUD-1
void main( void )
{
...
USART_Init ( MYUBRR );
...
}
void USART_Init( unsigned int ubrr)
{
/* Set baud rate */
UBRRH0 = (unsigned char)(ubrr>>8);
UBRRL0 = (unsigned char)ubrr;
/* Enable receiver and transmitter */
UCSR0B = (1<<RXEN0)|(1<<TXEN0);
/* Set frame format: 8data, 2stop bit */
UCSRnC = (1<<USBS0)|(3<<UCSZ00);
}
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19.6 Data Transmission – The USART Transmitter
The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRn B
Register. When the Transmitter is enabled , the normal port operation of the TxD pin is overrid-
den by the USART and given the function as the Transmitter’s serial output. The baud rate,
mode of operation and fram e format must be set up once befor e doing any tran smissions. I f syn-
chronous operation is used, the clock on the XCK pin will be overridden and used as
transmission clock.
19.6.1 Sending Frames with 5 to 8 Data Bit
A data transmission is in itiated by loa ding the transmit buffer with t he data to be t ransmitted. The
CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the
transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new
frame. The Shif t Regi ster is loaded wit h new dat a if it is in id le stat e ( no ongoin g tr ansmission ) or
immediately after the last sto p bit of the pr evious frame is transmitte d. When th e Shift Register is
loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,
U2Xn bit or by XCK dependin g on mode of op er at ion .
The following code examples show a simple USART transmit function based on polling of the
Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-
nificant bits written to the UDRn are ignored. The USART has to be initialized before the function
can be used. For the assembly code, the data to be sen t is assumed to be store d in Register
R16.
Note: 1. See ”About Code Examples” on page 10.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,
the interrupt routine writes the data into the buffer.
Assembly Code Example(1)
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSR0A,UDREn
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
sts UDR0,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSR0A & (1<<UDRE0)) )
;
/* Put data into buffer, sends the data */
UDR0 = data;
}
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19.6.2 Sending Frames with 9 Data Bit
If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in
UCSRnB before the low byte of the character is written to UDRn. The following code examples
show a transmit function that handles 9-bit characters. For the assembly code, the data to be
sent is assumed to be stored in registers R17:R16.
Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-
tents of the UCSRnB is static. For example, only the TXB8n bit of the UCSRnB Register is
used after initialization.
2. See ”About Code Examples” on page 10.
The ninth bit can be used for indicating an address frame when using multi processor communi-
cation mode or for ot he r pr ot oc ol ha nd lin g as fo r ex a m ple syn chr o niza tio n.
Assembly Code Example(1)(2)
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSR0A,UDRE0
rjmp USART_Transmit
; Copy 9th bit from r17 to TXB80
cbi UCSR0B,TXB80
sbrc r17,0
sbi UCSR0B,TXB80
; Put LSB data (r16) into buffer, sends the data
sts UDR0,r16
ret
C Code Example(1)(2)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSR0A & (1<<UDRE0))) )
;
/* Copy 9th bit to TXB8n */
UCSR0B &= ~(1<<TXB80);
if ( data & 0x0100 )
UCSR0B |= (1<<TXB80);
/* Put data into buffer, sends the data */
UDR0 = data;
}
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19.6.3 Transmitter Flags and Interrupts
The USART Transmitter has two flags that indicate its state: USART Data Register Empty
(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty (U DREn) Flag indicates whether the tran smit buffer is ready to re ceive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Register. For compat-
ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the
USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
transmission is used, the Data Register Empty interrupt routine must either write new data to
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writin g a one to its b it locatio n. The TXCn Flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the tra nsmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART
Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt
is executed.
19.6.4 Parity Generator
The Parity Gene rator calculat es the par ity bit f or the serial frame data. When parity bit is enabled
(UPM1n = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
19.6.5 Disabling the Transmitter
The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo-
ing and pending transmissions are completed, that is, when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxD pin.
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19.7 Data Reception – The USART Receiver
The USART Receiver is enable d by writing the Receive Enable (RXENn) bit in the UCSRnB
Register to one. When the Receiver is enabled, the nor mal pin oper ation of the RxD pi n is over -
ridden by the USART and given th e fu nction as the Receiver’s serial input. The baud rate, mode
of operation and fram e format must be set up once befo re any serial reception can be don e. If
synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
19.7.1 Receiving Frames with 5 to 8 Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until
the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When
the first stop bit is received, that is, a complete serial frame is present in the Receive Sh ift Regis-
ter, the contents of the Shift Register will be moved into the receive buffer. The receive buffer
can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the
Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant
bits of the data read from the UDRn will be masked to zero. The USART has to be initi alized
before the function can be used.
Note: 1. See ”About Code Examples” on page 10.
The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,
before readin g the buffer and returning the value.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSR0A, RXC0
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDR0
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSR0A & (1<<RXC0)) )
;
/* Get and return received data from buffer */
return UDR0;
}
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19.7.2 Receiving Frames with 9 Data Bits
If 9-bit charact ers are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB
before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Sta-
tus Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O
location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,
DORn and UPEn bits, which all are stored in the FIFO, will change.
The following code example shows a simple USART receive function that handles both nine bit
characters and the status bits.
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Note: 1. ”About Code Examples” on page 10.
The rece ive function example r eads all th e I/O Registers into the Register File before any com-
putation is done. This gives an optimal receive buffer utilization since the buffer location read will
be free to accept new data as early as possible.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSR0A, RXC0
rjmp USART_Receive
; Get status and 9th bit, then data from buffer
in r18, UCSR0A
in r17, UCSR0B
in r16, UDR0
; If error, return -1
andi r18,(1<<FE0)|(1<<DOR0)|(1<<UPE0)
breq USART_ReceiveNoError
ldi r17, HIGH(-1)
ldi r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr r17
andi r17, 0x01
ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSR0A;
resh = UCSR0B;
resl = UDR0;
/* If error, return -1 */
if ( status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
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19.7.3 Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complet e (RXCn) Flag ind icates if t here are unre ad data presen t in the receive buf-
fer. This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (that is, does not contain any unread data). If the Rece iver is disab led (RXENn =
0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receiv e
Complete interrupt will be executed as long as the RXCn Flag is se t (provided that global inter-
rupts are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-
rupt will occur once the interrupt routine terminates.
19.7.4 Receiv e r Error Flags
The USART Receiver has three Error Flag s: Frame Er ror (FEn), Data OverRun (DORn) and
Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is
that they are located in the receive buffer together with the frame for which they indicate the
error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the
receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.
Another equality for the Error Flags is that they can not be alte red by software doing a write to
the flag location. However, all flags must be set to zero when the UCSRnA is written for upward
compatibility of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn ) Flag indicates the state of the first stop bit of the next read able frame
stored in th e rec eive b uffer. The FEn Flag is zero when t he st op b it was c orre ctly re ad ( as on e),
and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of -sync conditions, detecting br eak conditions and protocol h andling. The FEn
Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,
except for the first, stop bits. For com patibility with future devices, always set this bit to zero
when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver bu ffer full condition. A
Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-
ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there
was one or more serial frame lost between the frame last read from UDRn, and the next frame
read from UDRn. For compatibility with future devices, alway s write this bit to zero when writing
to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates tha t the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see ”Parity Bit Calculation” on pa ge 174 and ”Parity Checker” on page 184.
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19.7.5 Parity Checker
The Parity Checke r is active when the hig h USART Parit y mode (U PM1n) bit is set. Typ e of Par-
ity Check to be performed (odd or even) is selected by the UPM0n bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit f rom the serial fr ame. The resu lt of the ch eck is stored in the rece ive buffe r together
with the rece ive d da ta an d sto p bit s. T h e Par i ty E rr or (UPEn) Flag ca n th en b e r ea d by so ftware
to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPM1n = 1). This bit is
valid until the receive buffer (UDRn) is read.
19.7.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immed iate. Data from ongoing
receptions will therefore be lost. When disabled (that is, t he RXENn is set to zero) the Receiver
will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost.
19.7.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be
emptied of its contents. Unrea d data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Note: 1. See ”About Code Examples” on page 10.
Assembly Code Example(1)
USART_Flush:
sbis UCSR0A, RXC0
ret
in r16, UDR0
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSR0A & (1<<RXC0) ) dummy = UDR0;
}
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19.8 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
19.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxD line is idle (that is, no communication activity).
Figure 19-5. Start Bit Sampling
When the clock reco very logic detects a h igh (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sampl e as shown in
the figure. T he clock re covery logic then uses sam ples 8 , 9, and 1 0 for Nor mal mod e, and sam -
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), t o decide if a valid start bit is re ceive d. If two or m ore o f these thre e samples have log ical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
19.8.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode. Figure 19-6 on page 186 shows the sampling of the
data bits and the parity bit. Each of the samples is given a number that is equal to the state of
the recovery unit.
12345678 9 10 11 12 13 14 15 16 12
STARTIDLE
00
BIT 0
3
1234 5 678120
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
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Figure 19-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by ha ving th e samp le num ber inside boxes. The majority vo t ing pr ocess is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 19-7 sh ows th e sampling of the st op bit an d the ea rlie st po ssib le begin ning of the st art bit
of the next frame.
Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done fo r the other bits in the fr ame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low tr ansit ion ind i cating the start bit of a n ew fra me can com e r igh t aft er the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 19-7. For Double Speed mode the first low level must be delayed to
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
19.8.3 Asynchronous Operational Range
The operational ra nge of the Receiver is dependent on the mism atch between the received bit
rate and the inter nally gene rated baud ra te. If the Tra nsmitter is sending f rames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 19-2 on page 187) base frequency, the Receiver will not be able to synchronize the
frames to the start bit.
12345678 9 10 11 12 13 14 15 16 1
BIT n
1234 5 6781
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12345678 9 10 0/1 0/1 0/1
STOP 1
1234 5 6 0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A) (B) (C)
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The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
DSum of character size and parity size (D = 5 to 10 bit).
SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
SFFirst sample number used for majority voting. SF = 8 for normal speed and SF = 4
for Double Speed mode.
SMMiddle sample number used for majority voting. SM = 9 for normal speed and
SM= 5 for Double Speed mode.
Rslow is the ratio of the slowe st incoming dat a rate that can be accepted in relation to t he
receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be
accepted in relation to the receiver baud rate.
Table 19-2 and Ta ble 19-3 list the maximum receiver baud rate error that can be tolerated. Note
that Normal Speed mode has higher toleration of baud rate variations.
Table 19-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2Xn = 0)
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max
Receiver Error (%)
5 93.20 106.67 +6.67/-6.8 ±3.0
6 94.12 105.79 +5.79/-5.88 ±2.5
7 94.81 105.11 +5.11/-5.19 ±2.0
8 95.36 104.58 +4.58/-4.54 ±2.0
9 95.81 104.14 +4.14/-4.19 ±1.5
10 96.17 103.78 +3.78/-3.83 ±1.5
Table 19-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2Xn = 1)
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max
Receiver Error (%)
5 94.12 105.66 +5.66/-5.88 ±2.5
6 94.92 104.92 +4.92/-5.08 ±2.0
7 95.52 104.35 +4.35/-4.48 ±1.5
8 96.00 103.90 +3.90/-4.00 ±1.5
9 96.39 103.53 +3.53/-3.61 ±1.5
10 96.70 103.23 +3.23/-3.30 ±1.0
Rslow
D1+()S
S1–DS⋅SF
++
-------------------------------------------=
Rfast
D2+()S
D1+()SS
M
+
-----------------------------------=
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The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The Receiver’s system clock
(XTAL) will always have some minor instability over the supply voltage range and the tempera-
ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a
resonator th e syste m clock ma y diff er more t han 2% dep en ding o f th e reson ator s t oler ance . The
second source for the error is more controllable. The baud rate generator can not always do an
exact division of t he system fr equency to get th e b aud rate wan ted. I n this case an UBRRn value
that gives an acceptable low error can be used if possible.
19.9 Multi-processor Communication Mode
Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering
function of incoming frames received b y the USART Receiver. Frames that do not contain
address information will be ignored and not put into the receive buffer. This effectively reduces
the number of incoming frames that has to be handled by the CPU, in a system with multiple
MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn
setting, but has to be used differently when it is a part of a system utilizing the Multi-processor
Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-
cates if the frame contains data or address information. If the Receiver is set up for frames with
nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When
the frame type bit (the first sto p or t he ninth b it) is o ne, th e f rame con tai ns a n add ress. When t he
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
19.9.1 Using MPCMn
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7). The
ninth bit (TXB8n) must be set when an a ddress frame (TXB8n = 1) or cle ared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following proce dure should be used to exchang e data in Multi-processor Communicatio n
mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is
set).
2. The Master MCU sends an address frame, and all slave s rece ive and read this fr a me. In
the Slave MCUs, the RXCn Flag in UCSRnA will be set as nor mal.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so,
it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and
keeps the MPCMn setting.
4. The addressed MCU will receive all data frames until a new address frame is received.
The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.
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5. When the last data frame is received by the addressed MCU, the addressed MCU sets
the MPCMn bit and waits for a new address frame from master. The process then
repeats from 2.
Using any of the 5-bit to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes full-
duplex operation difficult since the Transmitter and Receiver uses the same character size set-
ting. If 5-bit to 8-bit character frames are used, the Transmitter must be set to use two stop bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
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19.10 Examples of Baud Rate Setting
For standard crystal and resona tor frequencies, the most commonly us ed baud rates for asyn-
chronous operation can be generated by using the UBRRn settings in Table 19-4. UBRRn
values which yield an ac tual baud rate differing less than 0.5% fr om the target baud rate, are
bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resis-
tance when the error ratings are high, especially for large serial frames (see ”Asynchronous
Operational Range” on page 186). The error values are calculated using the following equation:
Note: 1. UBRRn = 0, Error = 0%.
Error[%] BaudRateClosest Match
BaudRate
-------------------------------------------------------- 1–
⎝⎠
⎛⎞
100%•=
Table 19-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
Baud
Rate
(bps)
fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%
4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%
9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%
14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%
19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%
28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%
38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%
57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%
76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%
115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%
230.4k––––––00.0%––––
250k––––––––––00.0%
Max.(1) 62.5 Kbps 125 Kbps 115.2 Kbps 230.4 Kbps 125 Kbps 250 Kbps
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Note: 1. UBRRn = 0, Error = 0.0%
Table 19-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%
4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%
9600 230.0%470.0%250.2%510.2%470.0%950.0%
14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%
19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%
28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%
38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%
57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%
76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%
115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%
230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%
250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%
0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%
1M ––––––––––0-7.8%
Max.(1) 230.4 Kbps 460.8 Kbps 250 Kbps 0.5 Mbps 460.8 Kbps 921.6 Kbps
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Note: 1. UBRRn = 0, Error = 0.0%
Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%
4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%
9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%
14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%
19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%
28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%
38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%
57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%
76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%
115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%
230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%
250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%
0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%
1M ––00.0%––––0-7.8%1-7.8%
Max.(1) 0.5 Mbps 1 Mbps 691.2 Kbps 1.38 24 Mbps 921.6 Kbps 1.8432 Mbps
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Note: 1. UBRRn = 0, Error = 0.0%
Table 19-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%
4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%
9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%
14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%
19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%
28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%
38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%
57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%
76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%
115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%
230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%
250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%
0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%
1M 00.0%10.0%––––––––
Max.(1) 1 Mbps 2 Mb ps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps
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19.11 USART Register Description
19.11.1 UDRn – USART I/O Data Register
The USART Transmit Data Buffer Regist er and USART Receive Data Buffer Regist ers share t he
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is en abled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO w ill change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-
Write instructions (SBI and CBI) on this location. Be careful when using bit test in structions
(SBIC and SBIS), since these also will change the state of the FIFO.
19.11.2 UCSRnA – USART Control and Status Register A
• Bit 7 – RXCn: USART Receive Complete n
This flag bit is set when th ere are unr ead data in the rece ive buffer a nd cleared whe n the rece ive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag
can be used to generate a Receive Com plete interrupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete n
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXC Flag bit is auto-
matically cleared when a transmit comple te interrup t is execut ed, or it can be clea red by writin g
a one to its bit location. The TXC Fla g can gen er ate a Tra nsmit Complete int err upt (see descr ip-
tion of the TXCIE bit).
• Bit 5 – UDREn: USART Data Register Empty n
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDR En
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIEn bit).
Bit 76543210
(0xC6) RXB[7:0] UDRn (Read)
TXB[7:0] UDRn (Write)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0xC0) RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn UCSRnA
Read/Write R R/W R R R R R/W R/W
Initial Value 0 0 1 0 0 0 0 0
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UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FEn: Frame Error n
This bit is set if the n ext charact er in th e rece ive bu ffer h ad a Fra me Error when received , th at is,
when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the
receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
Always set this bit to zero when writing to UCSRnA.
• Bit 3 – DORn: Data OverRun n
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDRn) is read . Always set this
bit to zero when writing to UCSRnA.
• Bit 2 – UPEn: USART Parity Error n
This bit is set if the next character in the receive buffer had a Parity Error when received and the
Parity Checking was enabled at that point (UPM1n = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USART Transmission Speed n
This bit only has effect for the asynchronous ope ration. Write this bit to zero when using syn-
chronous operatio n.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer r ate for asynchronous communication .
• Bit 0 – MPCMn: Multi-processor Communication Mode n
This bit enables the Multi-processor Communication mod e. When the MPCMn bit is written to
one, all the incoming fra mes received by the USART Receiver that do not contain address infor-
mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed
information see ”Multi-processor Communication Mode” on page 188.
19.11.3 UCSRnB – USART Control and Status Register n B
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the RXC bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables in terrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
Bit 76543210
(0xC1) RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n UCSRnB
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value00000000
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• Bit 5 – UDRIEn: USART Data Register Empty Inte rrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated on ly if the UDRIEn bit is written to one, the Global Inter rupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set .
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing a nd pending transmissions are completed, that is,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxD port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZ1n:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the rece ived char acter when op erating wit h serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
19.11.4 UCSRnC – USART Control and Status Register n C
• Bit 6 – UMSELn: USAR T Mode Select n
This bit selects betwe en asynchronous and synchronous mode of operation.
• Bit 5:4 – UPMn[1:0]: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Bit 76543210
(0xC2) – UMSELn UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 19-8. UMSELn Bit Settings
UMSELn Mode
0 Asynchronous Operation
1 Synchronous Operation
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Receiver will generate a parity value for the incoming data and compare it to the UPM0n setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
• Bit 2:1 – UCSZn[1:0]: Character Size
The UCSZn[1:0] bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bi t sets the relat ionship be tween dat a output change an d dat a input samp le,
and the synchronous clock (XCK).
Table 19-9. UPM Bits Settings
UPMn1 UPMn0 Parity Mode
00Disabled
01Reserved
1 0 Enab led, Even Parity
1 1 Enabled, Odd Parity
Table 19-10. USBSn Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 19-11. UCSZ Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
100Reserved
101Reserved
110Reserved
1 1 1 9-bit
Table 19-12. UCPOLn Bit Settings
UCPOLn Transmitted Data Changed
(Output of TxD Pin) Received Data Sampled (Input on RxD
Pin)
0 Rising XCK Edge Falling XCK Edge
1 Falling XCK Edge Rising XCK Edge
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19.11.5 UBRRLn and UBRRHn – USART Baud Rate Registers
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRHn is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRHn contains the four
most significant bits , and the UBRRLn contains the eig ht least significant bits of the USART
baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud
rate is changed. Writing UBRRLn will trigger an immediate update of the baud rate prescaler.
Bit 151413121110 9 8
(0xC5) –––– UBRRn[11:8] UBRRHn
(0xC4) UBRRn[7:0] UBRRLn
76543210
Read/Write R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
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20. USI – Universal Serial Interface
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rat es and use s less code spa ce than solution s based on soft ware only. I nterr upts
are included to minimize the processor load. The main features of t he USI are:
•Two-wire Synchronous Data Transfer (Master or Slave)
•Three-wire Synchronous Data Transfer (Master or Slave)
•Data Received Interrupt
•Wakeup from Idle Mode
•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
•Two-wire Start Condition Detector with Interrupt Capability
20.1 Overview
A simplified block diagram of the USI is shown on Figure 20-1. For the actual placement of I/O
pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins,
are shown in bold. The device-specif ic I/O Re gister and bit lo cations are listed in t he ”USI Regi s-
ter Descriptions” on page 207.
Figure 20-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and outp ut pin, which delays the change of data ou tput to the opposite clock
edge of the data inpu t sam pling . The seri al inp ut is alwa ys sample d fro m th e Dat a In put ( DI) p in
independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Bo th the Seria l Registe r an d the coun ter are clocke d simultaneously by th e same clock
source. This allows the count er to co unt the n umber of bits r eceived or transmit ted and g enera te
DATA BUS
USIPF
USITC
USICLK
USICS0
USICS1
USIOIFUSIOIE
USIDC
USISIF
USIWM0
USIWM1
USISIE Bit7
Two-wire Clock
Control Unit
DO (Output only)
DI/SDA (Input/Open Drain)
USCK/SCL (Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
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an interrupt when the transfer is complete. Note that when an external clock source is selected
the counter counts both clock edges. In this case the counter counts the number of edges, and
not the number of bits. The clock can be selected from three different source s: The USCK pin,
Timer/Counter0 Compare Match or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on
the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-
dition is detected, or after the counter overflows.
20.2 Functional Descriptions
20.2.1 Three-wire Mode
The USI Three-wire mo de is comp liant to the Serial Periph eral Int erface ( SPI) mo de 0 and 1, b ut
does not have the slave select (SS) pin functionality. However, this feature can be implemented
in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 20-2. Three-wire Mode Operation, Simplified Diagram
Figure 20-2 shows two USI units operating in Three-wire mode, one as Master and one as
Slave. The two Shift Registers are interconnected in such way that after eight USCK clocks, the
data in each register are interchanged. The same clock also increments the USI’s 4-bit counter.
The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a
transfer is completed. The clock is generated by the Master device software by toggling the
USCK pin via the PORT Re gis ter or by writing a one to the USITC bit in USICR.
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
PORTxn
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Figure 20-3. Three-wire Mode, Timing Diagram
The Three-wire mode t iming is show n in Fig ure 20 -3 At the t op of th e f igur e is a USCK cycle re f-
erence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The
USCK timing is shown for bo th external clock modes. In External Clo ck mode 0 (USICS0 = 0), DI
is sampled at positiv e edges, and DO is changed (Da ta Register is shifted by one) a t negative
edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mod e 0, that is,
samples data at negative and chan ges the output at positive edges. The USI clock modes corre-
sponds to the S P I da ta m od e 0 an d 1.
Referring to the timing diagram (Figure 20-3), a bus transfer involves the following steps:
1. The Sla ve device and Master de vice set s u p its d at a out put and, dep en ding on th e pr ot o-
col used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the Serial Data Register. Enabling of the output is done by set-
ting the corresponding bit in the port Data Direction Register. Note that point A and B
does not have any specific order, but both must be at least one half USCK cycle before
point C where the data is sampled. This must be done to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
2. The Master gene r at es a clock pulse by software togg ling the USCK line t wice (C a nd D) .
The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the
first edge (C), and the data output is changed on the opposite e dge (D). The 4-bit cou nter
will count both edges.
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (that is, 16 clock edges) the counter will overflow and indicate
that the tr ansfer is completed. The data b yt es tra nsferred mu st no w be pr ocessed before
a new transf er can be initiated. The overflow interrupt will wake up the processor if it is
set to Idle mode. Depending of the protocol used the slave device can now set its output
to high impedance.
20.2.2 SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer:
sts USIDR,r16
ldi r16,(1<<USIOIF)
sts USISR,r16
ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
SPITransfer_loop:
sts USICR,r16
lds r16, USISR
sbrs r16, USIOIF
MSB
MSB
654321LSB
1 2 3 4 5 6 7 8
654321LSB
USCK
USCK
DO
DI
DCBA E
CYCLE
( Reference )
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rjmp SPITransfer_loop
lds r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register
r16 prior to the functi on is called is transferred to the Slave device, and when the transfe r is com-
pleted the data received from the Slave is stored back into the r16 Register.
The second and third instructions clears the USI Counter Overflow Flag and the USI counter
value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock,
count at USITC strobe, and toggle USCK. The loop is repeated 16 times.
The following code demonstrates ho w to use the USI module as a SPI Master with maximum
speed (fsck = fck/4):
SPITransfer_Fast:
sts USIDR,r16
ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
sts USICR,r16 ; MSB
sts USICR,r17
sts USICR,r16
sts USICR,r17
sts USICR,r16
sts USICR,r17
sts USICR,r16
sts USICR,r17
sts USICR,r16
sts USICR,r17
sts USICR,r16
sts USICR,r17
sts USICR,r16
sts USICR,r17
sts USICR,r16 ; LSB
sts USICR,r17
lds r16,USIDR
ret
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20.2.3 SPI Slave Operation Example
The following code demonstrates how to use the USI module as a SPI Slave:
init:
ldi r16,(1<<USIWM0)|(1<<USICS1)
sts USICR,r16
...
SlaveSPITransfer:
sts USIDR,r16
ldi r16,(1<<USIOIF)
sts USISR,r16
SlaveSPITransfer_loop:
lds r16, USISR
sbrs r16, USIOIF
rjmp SlaveSPITransfer_loop
lds r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO is configured as output and USCK pin is configured as input in the DDR Register. The
value stored in register r16 prior to the function is called is transferred to the master device, and
when the transfer is completed the data received from the Master is stored back into the r16
Register.
Note that the first two instructions is for initialization only and needs only to be executed
once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop
is repeated until the USI Coun ter Overflow Flag is set.
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20.2.4 Two-wire Mode
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-
iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
Figure 20-4. Two-wire Mode Operation, Simplified Diagram
Figure 20 -4 shows two USI units operating in Two-wire mode, one as Master and one as Slave.
It is only the physical layer that is shown since the system operation is highly dependent of the
communica tion s chem e us ed. T he main diffe renc es be twee n th e Ma ster and Slave ope ratio n at
this level, is the serial clock generation which is always done by the Master, and only the Slave
uses the clock control unit. Clock generation must be implemented in software, but the shift
operation is done automatically by both devices. Note that only clo cking on negative edge for
shifting data is of practical use in this mode. The slave can insert wait states at start or end of
transfer by forcing the SCL clock low. This means that the Master must always check if the SC L
line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is comple ted. The clock is generated by the ma ster by toggling the USCK pin via the
PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
MASTER
SLAVE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDA
SCL
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Two-wire Clock
Control Unit
HOLD
SCL
PORTxn
SDA
SCL
VCC
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Figure 20-5. Two-wire Mode, Typical Timing Diag ram
Referring to the timing diagram (Figure 20-5), a bus transfer involves the following steps:
1. The a start condition is generated by the Master by forcing the SDA low line while the
SCL line is high (A). SDA can be forced low either b y writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that the
Data Direction Registe r bit must be set to one for the output to be enabled. The sla ve
de vice’s start detector logic (Figure 20-6) detects the st art condition and sets the USISIF
Flag. The flag can ge ne rate an inte rrupt if nece ssa ry.
2. In addition, the start detector will hold the SCL line low after the Master has forced an
negative edge on this line (B). This allows the Slave to wake up from sleep or complete
its other tasks b ef or e setting u p the Shift Re gister to receive the addre ss . This is done by
clearing the start condition flag and reset the counter.
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
samples the data and shift it into the Serial Register at the positive edge of the SCL
clock.
4. After eight bits are transferred containing slave address and data direction (read or
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the Master has addressed, it releases t he SCL line and waits for a new start
condition.
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
before holding the SCL line low again (that is, the Counter Register m ust be set to 14
before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its
output. If the bit is set, a master read op eration is in pro gress (th at is, t he sla ve drives the
SDA line) The slave can hold the SCL line low after the acknowledge (E).
6. Multiple b ytes can now be tra nsmitted, all in same direction, until a st op condition is give n
by the Master (F). Or a new start condition is given.
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 20-6. Start Condition Detector, Logic Diagram
PS ADDRESS
1 - 7 8 9
R/W ACK ACK
1 - 8 9
DATA ACK
1 - 8 9
DATA
SDA
SCL
A B D EC F
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR
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20.2.5 Start Condition Detector
The start condition det ector is show n in Figur e 20- 6 on pa ge 205 The SDA line is delayed ( in the
range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is
only enabled in Two-wire mode.
The start condition detect or is wor king asyn chronou sly and can there fore wake u p the pr ocessor
from the Power-down sleep mo de. However, the protocol used might h ave restrictions on the
SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time s et by
the CKSEL Fuses (see ”Clock Systems and their Distribution” on page 30) must also be taken
into the consideration. Refer to the ”Bit 7 – USISIF: Start Condition Interrupt Flag” on page 207
for further details.
20.2.6 Clock speed considerations.
Maximum frequency for SCL and SCK is f_CK /4. This is also the maximum data transmit and
receieve rate in both tw o- and t hree-wire m ode. In two-wire slave mo de the T wo-wire Clock Con-
trol Unit will hold the SCL low until the slav e is ready to receive more data. This may reduce the
actual data rate in two -wir e m od e.
20.3 Alternative USI Usage
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
20.3.1 Half-duplex Asynchronous Data Transfer
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact
and higher performance UART than by software only.
20.3.2 4-bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
20.3.3 12- bit Ti mer/C ounter
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
20.3.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
20.3.5 Softwa re Interrupt
The counter over flow interrupt can be used as a software interrupt triggered by a clock strobe.
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20.4 USI Register Descriptions
20.4.1 USIDR – USI Data Register
The USI uses no buffering of the Serial Register, that is, when accessing the Data Register
(USIDR) the Serial Re gister is accessed directly. If a serial clock occurs at the same cycle the
register is written, the register will contain the value written and no shift is performed. A (left) shift
operation is performed depending of the USICS1..0 bits setting. The shift operation can be con-
trolled by an external clock edge, by a Timer/C ounter0 Compare Match, or directly by software
using the USICLK strobe bit. Note that even when no wire m ode is selected (USIWM1..0 = 0)
both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used
by the Shift Register.
The output pin in u se, DO or SDA depe nding on the wire mode, is co nnected via the output latch
to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) dur-
ing the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1),
and constantly open when an internal clock source is used (USICS1 = 0). The output will be
changed immediately when a new MSB written as long as the latch is open. The latch ensures
that data input is sampled and data output is changed on opposite clock edges.
Note that the corr esponding Data Dir ection Register to the p in must be set to one for enabling
data output from the Shift Register .
20.4.2 USISR – USI Status Register
The Status Regist er contains Interrupt Flags, line Status Flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is
detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &
USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF
bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) wh en the 4-bit counter overflows (that is, at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.
Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.
Bit 7 6 5 4 3 2 1 0
(0xBA) MSB LSB USIDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0xB9) USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 USISR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.
The flag is clear ed by writing a one to t his bit. Note that this is not an In terrupt Flag . This signal is
useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag
is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire
bus master arbit ration.
• Bits 3..0 – USICNT3:0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or
written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge
detector, by a Timer/Counter0 Com pare Match, or by software using USICLK or USITC strobe
bits. The clock source depends of the setting of the USICS1:0 bits. For external clock operation
a special feature is added that allows the clock to be generated by writing to the USITC strobe
bit. This feature is enabled by write a one to the USICLK bit while setting an external clock
source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1:0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
20.4.3 USICR – USI Control Register
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enab les the Start Condition detecto r interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. Refer to the ”Bit 7 – USISIF: Start Condition Interrupt Flag” on page 207 for further
details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this b it to one en ables the Count er Overflow int errupt. If th ere is a pending interrupt when
the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.
Refer to the ”Bit 6 – USIOIF: Co un te r Over flow Interrupt Fla g” on pag e 207 for further details.
• Bit 5:4 – USIWM1:0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and Shift Register can therefore be clocked exter-
Bit 7 6 5 4 3 2 1 0
(0xB8) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0
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nally, and data input sampled, even when outputs are disabled. The relations between
USIWM1:0 and the USI op er a tion is sum ma riz ed in Table 20-1 on page 210.
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Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectiv ely
to av oid confusion between the modes of operation.
• Bit 3:2 – USICS1:0: Clock Source Select
These bits set the clock so urce fo r th e Shift Reg ist er an d count er . The da ta ou tp ut lat c h ensur es
that the outpu t is changed at the opposite edge of the sampling of the data input (DI/SDA) when
using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare
Match clock option is selected, the output latch is transparent and therefore the output is
changed immediately. Clearing the USICS1..0 bits enables software strobe option. When using
this option, writing a one to the USICLK bit clocks both the Shift Register and the counter. For
external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects
between external clocking and sof tware clocking by the USITC strobe bit.
Table 20-1. Relations between USIWM1:0 and the USI Operation
USIWM1 USIWM0 Description
00
Outputs, clock hold, and star t detector disabled. Port pins operates as
normal.
01
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORT
Register in this mode. However, the corresponding DDR bit still controls the
data direction. When the port pin is set as input the pins pull-up is controlled
by the PORT bit.
The Data Input (DI) and Ser ial Clock (USCK) pins do not affect the normal
port operation. When operating as master, clock pulses are software
generated by toggling the PORT Register, while the data direction is set to
output. The USITC bit in the USICR Register can be used for this purpose.
10
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1).
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and
uses open-collector output drives. The output drivers are enabled by setting
the corresponding bit for SDA and SCL in the DDR Register.
When the output driver is enabled for the SDA pin, the output driver will force
the line SDA lo w if the output of the Shift Register or the corresponding bit in
the PORT Register is z ero. Otherwise the SD A line will not be driven (that is, it
is released). When the SCL pin output dr iver is enabled the SCL line will be
f orced low if the corresponding bit in the PORT Register is zero , or b y the start
detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and
the output is enabled. Clearing the Start Condition Flag (USISIF) releases the
line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-
ups on the SDA and SCL port pin are disabled in Two-wire mode.
11
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except that the
SCL line is also held low when a counter overflow occurs , and is held low until
the Counter Overflow Flag (USIOIF) is cleared.
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Table 20-2 shows the relationship between the USICS1:0 and USICLK setting and clock source
used for the Shift Register and the 4-bit counter.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to
increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software
clock strobe option is selected. The output will change immediately when the clock strobe is exe-
cuted, that is, in the same instruction cycle. The value shifted into the Shift Register is sampled
the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see Tabl e 20 -2 ).
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independe nt of the setting in t he Data Direction Register, b ut if the PORT value is
to be shown on th e pin the DDRE4 must be set as output (to one ). This feature all ows easy clock
generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
Table 20-2. Relations between the USICS1:0 and USICLK Setting
USICS1 USICS0 USICLK Shift Register Clock Source 4-bit Counter Clock Source
0 0 0 No Clo ck No Clock
001
Software cloc k strobe
(USICLK) Software cloc k strobe
(USICLK)
01X
Timer/Counter0 Compar e
Match Timer/Counter0 Compare
Match
1 0 0 External, positive edge External, both edges
1 1 0 External, negative edge External, both edges
1 0 1 External, positiv e edge Software clock strobe (USITC)
1 1 1 External, negative edge Software clock strobe (USITC)
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21. AC - Analog Comparator
The Analog Comparat or compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger
the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate
interrupt, exclusive to the Analog Comparator. Th e user can select Interrupt triggering on com-
parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 21-1.
The Power Reduction ADC bit, PRADC, in ”PRR – Power Reduction Register” on page 45 must
be disabled by writing a logical zero to be able to use the ADC input MUX.
Figure 21-1. Analog Comparator Block Diagram(2)
Notes: 1. See Table 21-1 on pag e 213.
2. Refer to Figure 1-1 on page 2 and Table 13-5 on page 74 for Analog Comparator pin
placement.
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
ADEN
(1)
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21.1 Analog Comparator Multiplexed Input
It is possible to select any of the ADC7:0 pins to replace the negative input to the Analog Com-
parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be
switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in
ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2:0 in ADMUX
select the input pin to replace the negative input to the Analog Comparator, as shown in Table
21-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog
Comparator.
Table 21-1. Analog Comparator Multiplexed Input
ACME ADEN MUX2:0 Analog Comparator Negative Input
0 x xxx AIN1
1 1 xxx AIN1
1 0 000 ADC0
1 0 001 ADC1
1 0 010 ADC2
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7
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21.2 Analog Comparator Register Description
21.2.1 ADCSRB – ADC Control and Status Register B
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (A DEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see ”Analog Comparator Multiplexed Input” on page 213.
21.2.2 ACSR – Analog Comparator Cont rol and Status Re gi st er
• Bit 7 – ACD: Analog Comparat or Disable
When this bit is written logic one, the power to the Ana log Comparator is swit ched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AI N0 is ap plied to the positive input of the Analog Compar-
ator. See ”Internal Voltage Reference” on page 51.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is ex ecut ed if the ACIE bit is se t
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling ve ctor. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is writte n logic one and t he I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be trig-
gered by the Ana log Comp arat or. The compar ator o utput is in this case directly connecte d to the
Bit 76543210
(0x7B) – ACME –––ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
Initial Value00000000
Bit 76543210
0x30 (0x50) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0
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Input Capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Cou nter1 Input Capture interru pt. When written logic zero, no connection
between the Analog Compa ra to r and t he I np ut Ca pt ure f unct ion e xists. To make the comp ar ator
trigger the Time r/Counter1 Input Ca pture interrupt, the IC IE1 bit in the Timer Interrup t Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determin e which comparator even ts that trigger the Analog Compa rator interr upt. The
different settings are shown in Table 21-2 on page 215.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Inte rrupt Enable bit in the ACSR Reg ister. Ot herwise an inter rupt can occu r when the
bits are changed.
21.2.3 DIDR1 – Digital Input Disable Register 1
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disa ble
When this bit is writte n logic one , the digita l input buf fer on the AI N1/0 pin is disa bled. The corr e-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffe r.
Table 21-2. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle.
01Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Rising Ou tput Edge.
Bit 76543210
(0x7F) –––––– AIN1D AIN0D DIDR1
Read/Write RRRRRRR/WR/W
Initial Value 0 0 0 0 0 0 0 0
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22. ADC - Analog to Digital Converter
22.1 Features
•10-bit Resolution
•0.5 LSB Integral Non-linearity
•±2 LSB Absolute Accuracy
•13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock)
•Up to 15 ksps at Maximum Resolution (200 kHz ADC clock)
•Eight Multiplexed Single Ended Input Chan nels
•Optional Left Adjust men t for ADC Result Readout
•0 - VCC ADC Input Voltage Range
•Selectable 1.1V ADC Reference Voltag e
•Free Running or Single Conversion Mode
•ADC Start Conversion by Auto Triggering on Interrupt Sources
•Interrupt on ADC Conversion Complete
•Sleep Mode Noise Canceler
22.2 Overview
The ATmega169P features a 10-bit successive approximation ADC. The ADC is connected to
an 8-channel Analog Multiplexer which allows eight single -ended voltage inputs constructe d
from the pins of Port F. The single-ended voltage input s refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 22-1
on page 217.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than
±0.3V from VCC. See the paragraph ”ADC Noise Canceler” on page 222 on how to connect this
pin.
Internal reference voltages of nominally 1.1V or AVCC are pro vided O n-chip. The vo ltage r efer-
ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.
The Power Reduction ADC bit, PRADC, in ”PRR – Power Reduction Register” on page 45 must
be written to zero to en able the ADC module.
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ATmega169P
Figure 22-1. Analog to Digital Converter Block Schema tic
22.3 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
the AREF pin mi nus 1 LSB. Op tionally, AVCC o r an in te rn al 1.1 V re fe rence volt ag e may be co n-
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be deco upled by an external capacitor at the AREF pin to im prove
noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, ca n be selected as single ended
inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-
age reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the ADC
before enterin g po we r sa ving s lee p m od es .
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right ad justed, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX) ADC CTRL. & STATUS
REGISTER (ADCSRA) ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADATE
ADSC
ADEN
ADIF ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
MUX3
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
MUX DECODER
MUX4
AVCC
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
REFS0
REFS1
ADLAR
+
-
CHANNEL SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
DIFFERENTIAL
AMPLIFIER
AREF
BANDGAP
REFERENCE
PRESCALER
SINGLE ENDED / DIFFERENTIAL SELECTION
GND
POS.
INPUT
MUX
NEG.
INPUT
MUX
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
START
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If the result is left ad justed and no more than 8-bit precision is requ ired, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, an d a conversion completes b efore ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interr upt which can be trigge red when a conversion co mpletes. When ADC
access to the Data Registers is prohibited be tween reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
22.4 Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and w ill be cleared by hardware
when the conversio n is com pleted . If a dif fere nt data channel is selected wh ile a co nver sion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting con-
versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is di sabled or t he Global In terr upt Enable b it in SREG is cleared. A conversion can th us
be triggered with out causing an interr upt. However, the Interrup t Flag must be cleare d in order to
trigger a new conversion at the next interrupt event.
Figure 22-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source make s the ADC start a new conver sion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and up dating the ADC Data Register . The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START CLKADC
.
.
.
.EDGE
DETECTOR
ADATE
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If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be us ed to determine if a conversion is in pr ogress. The ADSC bit will be
read as one during a conversion, independently of how the conversio n was started.
22.5 Prescaling and Conversion Timing
Figure 22-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps runnin g for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample- and-h old ta kes pla ce 1. 5 ADC clock cycles aft er t he sta rt of a norma l con ver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver sion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU cloc k c ycle s ar e used for synchronization log ic. Wh en u sin g Dif fer e ntia l m ode , along
with Auto triggering from a so urce other than the ADC Conversion Com plete, each conversion
will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after
every conversion.
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
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In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 22-1 on page
221.
Figure 22-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 22-5. ADC Timing Diagram, Single Conversion
Figure 22-6. ADC Timing Diagram, Auto Triggered Conversion
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1212
13 14 15 16 17 18 19 20 21 22 23 24 25 1 2
First Conversion Next
Conversion
3
MUX and REFS
Update MUX and REFS
Update
Conversion
Complete
123456789 10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete MUX and REFS
Update
1 2 3 4 5 6 7 8 910 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
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Figure 22-7. ADC Timing Diagram, Free Running Conversion
22.6 Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continu ously updated until a conve rsion is started. Once the conver sion starts, the
channel and reference se lection is locked to e nsure a sufficient sampling t ime for the ADC. Co n-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note tha t the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or refe rence select ion values
to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact tim e of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot te ll if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
Table 22-1. ADC Conversion Time
Condition Sample & Hold (Cycles from
Start of Conversion) Conversion Time (Cycles)
First conversion 13.5 25
Normal conv ersions, single ended 1.5 13
Auto Triggered conversi o ns 2 13.5
11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
34
Conversion
Complete Sample & Hold
MUX and REFS
Update
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ATmega169P
22.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the chann el before sta rting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is t o wa it for the co nversio n to complete b efore cha nging the ch annel sele ction.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the cha nnel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
22.6.2 ADC Voltage Reference
The referenc e voltage for the ADC (VREF) indicates the conversion range for the ADC. Single
ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as
either AVCC, internal 1.1V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is gener-
ated from the internal bandgap reference (VBG) through an internal buffer. In either case, the
external AREF pin is directly connected to the ADC, and the reference voltage can be made
more immune to noise by connecting a capacitor between the AREF pin and gro und. VREF can
also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high
impedant sour ce, and only a capacitive load should be connected in a system.
If the user has a fixed volt age source connect ed to the AREF pin, the user ma y not use the oth er
reference voltage options in the application, as they will be shorted to the external voltage. If no
external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as
reference selection. The first ADC conversion result after switching reference voltage source
may be inaccurate, and the user is advised to discard this result.
22.7 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and o ther I/O pe ripherals. The noise ca nceler can be used with ADC
Noise Reduc tion an d Id le m ode. To m ake use of th is fe atur e, th e fo llowing proce dur e sh ould b e
used:
a. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be select ed and the ADC conv ersion complete interrupt must be enab led.
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt
will wak e up the CPU and e x ecute the ADC Con v ersion Complete interrupt routine. If
another interrupt wakes up the CPU before the ADC conversion is complete, that
interrupt will be ex ecuted, and an ADC Conv ersion Complete interrupt request will be
generated when the ADC conv ersion completes. The CPU will remain in active mode
until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
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22.7.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 22-8 An analog
source applied to ADCn is subjecte d to the pin ca pacitance and inp ut leakage of that pin, re gard-
less of whether that channel is selected as input for the ADC. When the channel is selected, the
source must dr ive the S/H capacitor th rough the series re sistance (combined resistance in the
input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the samp ling time wi ll be n egligible . I f a sour ce with higher impe d-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.
Figure 22-8. Analog Input Circuitry
ADCn
I
IH
1..100 kΩ
C
S/H
= 14 pF
V
CC
/2
I
IL
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ATmega169P
22.7.2 Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
a. Keep analog sig nal paths as short as possible. M ak e sure analog t racks run ov er the
analog ground plane, and keep them well away from high-speed switching digital
tracks.
b. The AVCC pin on the device should be connect ed to the digital VCC supply voltage
via an LC network as shown in Figure 22-9.
c. Us e the ADC no ise ca nc ele r fu nct ion to re du ce indu ce d noise fro m th e CPU.
d. If any ADC port pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
Figure 22-9. ADC Power Connections
VCC
GND
100 nF
Ground Plane
(ADC0) PF0
(ADC7) PF7
(ADC1) PF1
(ADC2) PF2
(ADC3) PF3
(ADC4) PF4
(ADC5) PF5
(ADC6) PF6
AREF
GND
AVCC
52
53
54
55
56
57
58
59
60
6161
6262
6363
6464
1
51
LCDCAP
PA0
10 µH
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22.7.3 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at
0.5 LSB). Ideal value: 0 LSB.
Figure 22-10. Offset Error
• Gain Error: After adjusting for offset, the Gain Erro r is found as the deviation of the last
transit ion (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB .
Figure 22-11. Gain Error
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.
Output Code
V
REF
Input Voltage
Ideal ADC
Actual ADC
Offset
Error
Output Code
V
REF
Input Voltage
Ideal ADC
Actual ADC
Gain
Error
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Figure 22-12. Integral Non-linearity (INL)
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval
between two adjacent tr ansitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
Figure 22-13. Differential Non-linearity (DNL)
• Quantization Error: Due to the quantization of the inp ut v olta ge into a finite n umber of co des , a
range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to
an ideal transition for any code. This is the compound effect of offset, gain error, differential
error, non-linearity, and quantization er ror. Ideal value: ±0.5 LSB.
Output Code
VREF Input Voltage
Ideal ADC
Actual ADC
INL
Output Code
0x3FF
0x000
0V
REF
Input Voltage
DNL
1 LSB
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22.8 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
For single ended conversion, the result is
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 22-3 on page 229 an d Table 22-4 on page 230). 0x 000 represents analog ground, and
0x3FF represents the selected reference voltage minus one LSB.
Figure 22-14. Differential Measurement Range
ADC VIN 1024⋅
VREF
--------------------------=
ADC VPOS VNEG
–()512⋅
VREF
-----------------------------------------------------=
0
Output Code
0x1FF
0x000
VREF Differential Input
Voltage (Volts)
0x3FF
0x200
- VREF
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ADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result).
Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ADCR = 512 × (300 - 500) / 1100 = -93 = 0x3A3.
ADCL will thus read 0xC0, and ADCH will read 0xD8. Writing zero to ADLAR right adjusts the
result: ADCL = 0xA3, ADCH = 0x03.
Table 22-2. Corre lation Between Input Voltag e and Output Codes
VADCn Read Code Corresponding Decimal Value
VADCm + VREF 0x1FF 511
VADCm + 511/512 VREF 0x1FF 511
VADCm + 510/512 VREF 0x1FE 510
... ... ...
VADCm + 1/512 VREF 0x001 1
VADCm 0x000 0
VADCm - 1/512 VREF 0x3FF -1
... ... ...
VADCm - 511/512 VREF 0x201 -511
VADCm - VREF 0x200 -512
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22.9 ADC Register Description
22.9.1 ADMUX – ADC Multiplexe r Selection Register
• Bit 7:6 – REFS1:0 : Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 22-3. If these b its are
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADL AR to left adjust the resu lt. Oth erwise, the r esult is ri ght adju sted. Changing t he
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see ”ADCL and ADCH – ADC Data Register” on
page 232.
• Bits 4:0 – MUX4:0: Analog Channel Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
See Table 22-4 on page 230 for details. If these bits are changed during a conversion, the
change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Bit 76543210
(0x7C) REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 22-3. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection
0 0 AREF, In terna l Vref tur ned off
0 1 AVCC with external capacitor at AREF pin
10Reserved
1 1 Internal 1.1V Voltage Reference with external capacitor at AREF pin
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Table 22-4. Inpu t Channel Selections
MUX4..0 Single Ended Input Positive Differential Input Negative Differential Input
00000 ADC0
N/A
00001 ADC1
00010 ADC2
00011 ADC3
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7
01000
01001
01010
01011
01100
01101
01110
01111
10000 ADC0 ADC1
10001 ADC1 ADC1
10010 N/A ADC2 ADC1
10011 ADC3 ADC1
10100 ADC4 ADC1
10101 ADC5 ADC1
10110 ADC6 ADC1
10111 ADC7 ADC1
11000 ADC0 ADC2
11001 ADC1 ADC2
11010 ADC2 ADC2
11011 ADC3 ADC2
11100 ADC4 ADC2
11101 ADC5 ADC2
11110 1.1V (VBG)N/A
11111 0V (GND)
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22.9.2 ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mod e, write this bit t o one to start ea ch conversion. In Free Running mode,
write this bit to one to st art th e first conversion. Th e first conversion af ter ADSC ha s been writt en
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive e dge of the select ed trigger signal. The trigger sou rce is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Re gisters are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the fl ag. Beware that if doing a Read-Modify-
Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions ar e used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is wr itte n to on e a n d t he I- bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
Bit 76543210
(0x7A) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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22.9.3 ADCL and ADCH – ADC Data Register
22.9.3.1 ADLAR = 0
22.9.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.When ADCL is
read, the ADC Data Regist er is not updated until ADCH is read. Consequent ly, if the result is lef t
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLA R is set, the result is left adjusted. If ADLAR is cleared (default), th e result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on
page 227.
Table 22-5. ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
000 2
001 2
010 4
011 8
100 16
101 32
110 64
111 128
Bit 151413121110 9 8
(0x79) – – – – – – ADC9 ADC8 ADCH
(0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 151413121110 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 – – – – – – ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
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22.9.4 ADCSRB – ADC Control and Status Register B
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use. To ensure compatibility with future devices, this bit must be
written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
22.9.5 DIDR0 – Digital Input Disable Register 0
• Bit 7:0 – ADC7D ..ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this
bit should be written logic one to r educe power consumption in the digital input buffer.
Bit 76543210
(0x7B) –ACME ––– ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
Initial Value00000000
Table 22-6. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Co mparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
Bit 76543210
(0x7E) ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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23. LCD Controller
23.1 Features
•Display Capacity of 25 Segments and Four Common Terminals
•Support Static, 1/2, 1/3 an d 1/ 4 D uty
•Support Static, 1/2, 1/3 Bias
•On-chip LCD Power Supply, only One External Capacitor needed
•Display Possible in Power -save Mode for Low Power Consumption
•Software Selectable Low Power Waveform Capability
•Flexible Selection of Frame Frequency
•Software Selection between System Clock or an External Asynchronous Clock Source
•Equal Source and Sink Capability to maximize LCD Life Time
•LCD Interrupt Can be Used for Display Data Update or Wake-up from Sleep Mode
•Segment and Common Pins not Needed for Driving the Display Can be Used as Ordinary I/O Pins
•Latching of Display Data gives Full Freed om in Register Update
23.2 Overview
The LCD Controller/driver is intended for monochrome passive liquid crystal display (LCD) with
up to four common terminals and up to 25 segment terminals.
A simplified block diagram of the LCD Controller/Driver is shown in Figure 23-1 on page 235. For
the actual placement of I/O pins, see ”64A (TQFP) and 64M1 (QFN/MLF) Pinout ATmega169P”
on page 2.
An LCD consists of several segments (pixels or complete symbols) which can be visible or non
visible. A segment has t wo e lect rodes wit h liqui d cr yst al be twee n the m. When a volta ge ab ove a
threshold voltage is applied across the liquid crystal, the segment becomes visible.
The voltage must alternate to avoid an electrophoresis effect in the liquid crystal, which
degrades the display. Hence the waveform across a segment must not have a DC-component .
The PRLCD bit in ”PRR – Power Reduction Register” on page 45 must be written to zero to
enable the LCD module.
23.2.1 Definitions
Several terms are used when de scribing LCD. The def inition s in Table 23-1 are used througho ut
this document.
Table 23-1. Definitions
LCD A passive display panel with terminals leading directly to a segment
Segment The least viewing element (pixel) which can be on or off
Common Denotes how many segments are connected to a segment terminal
Duty 1/(Number of common terminals on a actual LCD display)
Bias 1/(Number of voltage levels used driving a LCD display -1)
Frame Rate Number of times the LCD segments is energized per second.
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Figure 23-1. LCD Module Block Diagram
23.2.2 LCD Clock Sources
The LCD Controller can be clocked by an internal synchronous or an external asynchronous
clock source. The cloc k source clkLCD is by default equal to the system clock, clkI/O. When the
LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the
TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage
offset across LCD segments.
23.2.3 LCD Prescaler
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits
selects clkLCD divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by
1 to 8.
Output from the clock divider clkLCD_PS is used as clock source for the LCD timing.
23.2.4 LCD Memor y
The display memory is available through I/O Registers grouped for each common terminal.
When a bit in the display memory is written to one, the corresponding segment is energized (on),
and non-energized when a bit in the display memory is written to zero.
Clock
Multiplexer
12-bit Prescaler
0
1
Divide by 1 to 8
LCD
Timing
LCDCRB
LCDFRR
clk
i/o
TOSC
LCDCRA
D
A
T
A
B
U
S
clk
LCD
/4096
clk
LCD
/2048
clk
LCD
/128
clk
LCD
/1024
clk
LCD
/512
clk
LCD
/256
clk
LCD
/64
clk
LCD
/16
Analog
Switch
Array
lcdcs
lcdcd2:0
lcdps2:0
clk
LCD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM0
COM1
COM2
COM3
LCD Buffer/
Driver
V
LCD
LCDDR 18 -15
LCDDR 13 -10
LCDDR 8 - 5
LCDDR 3 - 0
LATCH
array LCD Ouput
Decoder
LCDCCR lcdcc3:0 Contrast Controller/
Power Supply
clk
LCD_PS
LCD
CAP
25 x
4:1
MUX
LCD_voltage_ok
2/3 V
LCD
1/2 V
LCD
1/3 V
LCD
Display
Configuration
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To energize a segment, an absolute voltage above a certain threshold must be applied. This is
done by letting th e output voltage o n corresponding COM pi n and SEG pin have opp osite phase.
For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage lev-
els must be app lied. Otherwise, no n-energized seg ments on COM0 would be energized for all
non-selected comm on.
Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0
compared to none addressed COM lines. Non-energized segments are in phase with the
addressed COM0, and energized segments have opposite phase and large amplitude. For
waveform f igures refe r to ”Mode of Operation” on page 237. Latched data from LCDDR4 -
LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and
sets up signals controlling the a nalog switches to produce an output waveform. Next, COM1 is
addressed, and latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continu-
ous until all COM lines are addressed according to number of common (duty). The display data
are latched before a new frame start.
23.2.5 LCD Contrast Controller/Power Supply
The peak value (VLCD) on the output waveform determines the LCD Contrast. VLCD is controlled
by software from 2.6V to 3.35V independent of VCC. An internal signal inhibits output to the LCD
until VLCD has reached its target value.
23.2.6 LCDCAP
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-
ure 23-2. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces
ripple on VLCD but increases the time until VLCD reaches its target value.
It is possible to use an external power supply. This power can be applied to LCDCAP before
VCC. Externally applied V LCD can be both above and below VCC. Maximum VLCD is 5.5V.
Figure 23-2. LCDCAP Connection
23.2.7 LCD Buffer Driver
Intermediate voltage levels are generated from buffers/drivers. The buffers are active the
amount of time specif ied by LCDDC[2:0] in ”LCDCCR – LCD Contrast Control Register” on page
250. Then LCD output pins are tri-stated and buffers are switched off. Shortening the drive time
will reduce power consumption, but displays with high internal resistance or capacitance may
need longer drive tim e to achieve sufficient contrast.
321
64
63
62
LCDCAP
VLCD
(Optional)
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23.2.8 Minimizing Power Consumption
By keeping the percentag e of the time the LCD d rivers are turned on a t a minimum, the power
consumption of the LCD driver can be minimized. This can be achieved by using the lowest
acceptable frame rate, and using low power waveform if possible. The drive time should be kept
at the lowest setting that achieves satisfactory contrast for a particu lar display, while allowing
some headroom for production variations between individual LCD drivers and displays. Note
that some of the highest LCD voltage settings may result in high power consumption when VCC
is below 2.0V. The recommended maximum LCD voltage is 2*(VCC - 0.2V).
23.3 Mode of Operation
23.3.1 Static Duty and Bias
If all segments on a LCD have one electrode common, then each segment must have a unique
terminal.
This kind of display is driven with the waveform shown in Figure 23-3. SEG0 - COM0 is the volt-
age across a segment that is on, and SEG1 - COM0 is the voltage across a segment that is off.
Figure 23-3. Driving a LCD with One Common Term in al
23.3.2 1/2 Duty and 1/2 Bias
For LCD with two common terminals (1/2 duty) a more complex waveform must be used to indi-
vidually control seg m en ts. Although 1/3 bia s ca n b e selected 1/2 bias is m os t com m o n fo r th es e
displays. Waveform is shown in Figure 23-4 on page 238. SEG0 - COM0 is the volt age ac ross a
segment that is on, and SEG0 - COM1 is the voltage across a segment that is off.
VLCD
GND
VLCD
GND
VLCD
GND
-VLCD
SEG0
COM0
SEG0 - COM0
Frame Frame
VLCD
GND
VLCD
GND
GND
SEG1
COM0
SEG1 - COM0
Frame Frame
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Figure 23-4. Driving a LCD with Two Common Terminals
V
LCD
GND
V
LCD
1
/
2
V
LCD
GND
V
LCD
1
/
2
V
LCD
GND
-1
/
2
V
LCD
-V
LCD
SEG0
COM0
SEG0 - COM0
Frame Frame
V
LCD
GND
V
LCD
1
/
2
V
LCD
GND
V
LCD
1
/
2
V
LCD
GND
-1
/
2
V
LCD
-V
LCD
SEG0
COM1
SEG0 - COM1
Frame Frame
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23.3.3 1/3 Duty and 1/3 Bias
1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is
shown in Figure 23-5. SEG0 - COM0 is the voltage across a segment that is on and SEG0-
COM1 is the voltage across a segment that is off.
Figure 23-5. Driving a LCD with Three Common Terminals
23.3.4 1/4 Duty and 1/3 Bias
1/3 bias is optimal for LCD displays with four common terminals (1/4 duty). Waveform is shown
in Figure 23-6. SEG0 - COM0 is the voltage across a segment that is on and SEG0 - COM1 is
the voltage across a segment that is off.
Figure 23-6. Driving a LCD with Four Common Terminals
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
-
1
/
3
V
LCD
-
2
/
3
V
LCD
-V
LCD
SEG0
COM0
SEG0 - COM0
Frame Frame
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
-
1
/
3
V
LCD
-
2
/
3
V
LCD
-V
LCD
SEG0
COM1
SEG0 - COM1
Frame Frame
VLCD
2/3VLCD
1/3VLCD
GND
VLCD
2/3VLCD
1/3VLCD
GND
VLCD
2/3VLCD
1/3VLCD
GND
-1/3VLCD
-2/3VLCD
-VLCD
SEG0
COM0
SEG0 - COM0
Frame Frame
VLCD
2/3VLCD
1/3VLCD
GND
VLCD
2/3VLCD
1/3VLCD
GND
VLCD
2/3VLCD
1/3VLCD
GND
-1/3VLCD
-2/3VLCD
-VLCD
SEG0
COM1
SEG0 - COM1
Frame Frame
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23.3.5 Low Power Waveform
To reduce toggle activity and hence power consumption a low power waveform can be selected
by writing LCDAB to one. Low power waveform requires two subsequent frames with the same
display data to obtain zero DC voltage. Consequ ently dat a lat chin g and Inte rr upt Flag is only set
every second frame. Default and low power waveform is shown in Figure 23-7 for 1/3 duty and
1/3 bias. For other selections of duty and bias, the effect is similar.
Figure 23-7. Default and Low Power Waveform
23.3.6 Operation in Sleep Mode
When synchronous LCD clock is selected (LCDCS = 0) the LCD display will operate in Idle
mode and Power-save mode with any clock source.
An asynchronous clock from TOSC1 can be selected as LCD clock by writing the LCDCS bit to
one when Calibrated Internal RC Oscillator is selected as system clock source. The LCD will
then operate in Idle mode, ADC Noise Reduction mode and Power-save mode.
When EXCLK in ASSR Register is written to one, and asynchronous clock is selected, the exter-
nal clock input buffer is enabled and an external clock can be input on Timer Oscillator 1
(TOSC1) pin instead of a 32 kHz cryst al. See ”Asynchr onous oper ation o f the Time r/Count er” on
page 150 for further details.
Before entering Power-down mode , Standby mode or ADC Noise Redu ction mode wit h synchro-
nous LCD clock selected, the user have to disable the LCD. Refer to ”Disabling the LCD” on
page 244.
23.3.7 Display Blanking
When LCDBL is written to one, the LCD is blanked after completing the curren t frame. All seg-
ments and common pins are connected to GND, discharging the LCD. Display memory is
preserved. Display blanking sh ould be used before disabling the LCD to avoid DC voltage
across segments, and a slowly fading image.
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
-
1
/
3
V
LCD
-
2
/
3
V
LCD
-V
LCD
SEG0
COM0
SEG0 - COM0
Frame Frame
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
V
LCD
2
/
3
V
LCD
1
/
3
V
LCD
GND
-
1
/
3
V
LCD
-
2
/
3
V
LCD
-V
LCD
SEG0
COM0
SEG0 - COM0
Frame Frame
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23.3.8 Port Mask
For LCD with less than 25 segment terminals, it is possib le to mask some of the unused pins
and use them as ordinary po rt pins instead . Refer to Ta ble 23-3 on page 24 7 for deta ils. Unused
common pins are automatically configured as port pins.
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23.4 LCD Usage
The following section de scr ib es ho w to use th e LCD .
23.4.1 LCD Initi aliza ti on
Prior to enabling the LCD some initialization must be preformed. The initialization process nor-
mally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but
can also be adjusted during operation.
Consider the following LCD as an example:
Figure 23-8. LCD usage example.
Display: TN Positive, Reflective
Number of common ter minals: 3
Number of segment terminals: 21
Bias system: 1/3 Bias
Drive system: 1/3 Duty
Operating voltage: 3.0 ±0.3V
1b
1c
2a
2b
2c2e
2f
2d
2g
COM3
COM0 COM1 COM2
SEG0
SEG1
SEG2
1b,1c
2c
2f
2a
2d
2g
2b
2e
..
COM2
SEG0
SEG1
SEG2
ATmega169
COM1
COM0
Connection table
LCD
51 50 49
48
47
46
45
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Note: 1. See ”About Code Examples” on page 10.
Before a re-initialization is done, the LCD controller/driver should be disabled.
23.4.2 Updating the LCD
Display memory (LCDDR0, LCDDR1, ..), LCD Blanking (LCDBL), Low power waveform
(LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There are no
restrictions on writing these LCD Register locations, but an LCD data update may be split
between two frames if data are latched while an update is in progress. To avoid this, an interrupt
routine can be used to update Display memory, LCD Blanking, Low power waveform, and con-
trast cont rol, just after data are latched.
Assembly Code Example(1)
LCD_Init:
; Use 32 kHz crystal oscillator
; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins
ldi r16, (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2)
sts LCDCRB, r16
; Using 16 as prescaler selection and 7 as LCD Clock Divide
; gives a frame rate of 49 Hz
ldi r16, (1<<LCDCD2) | (1<<LCDCD1)
sts LCDFRR, r16
; Set segment drive time to 125 µs and output voltage to 3.3 V
ldi r16, (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1)
sts LCDCCR, r16
; Enable LCD, default waveform and no interrupt enabled
ldi r16, (1<<LCDEN)
sts LCDCRA, r16
ret
C Code Example(1)
Void LCD_Init(void);
{
/* Use 32 kHz crystal oscillator */
/* 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins */
LCDCRB = (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2);
/* Using 16 as prescaler selection and 7 as LCD Clock Divide */
/* gives a frame rate of 49 Hz */
LCDFRR = (1<<LCDCD2) | (1<<LCDCD1);
/* Set segment drive time to 125 µs and output voltage to 3.3 V*/
LCDCCR = (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1);
/* Enable LCD, default waveform and no interrupt enabled */
LCDCRA = (1<<LCDEN);
}
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In the example belo w we assume SEG10 an d COM1 and SEG4 in COM 0 are the only segm ents
changed from frame to frame. Data are stored in r20 and r21 for simplicity
Note: 1. See ”About Code Examples” on page 10.
23.4.3 Disabling the LCD
In some application it may be necessary to disable the LCD. This is the case if the MCU enters
Power-down mode where no clo ck source is present.
The LCD should be completely discharged before being disabled. No DC voltage should be left
across any segment. Th e be st way t o ach ieve this is to use the LCD Blanking feature that drives
all segment pins and common pin s t o GND.
When the LCD is disabled, port function is activated again. Therefore, the user must check that
port pins connected to a LCD ter minal are either tri-state or output low (sink).
Assembly Code Example(1)
LCD_update:
; LCD Blanking and Low power waveform are unchanged.
; Update Display memory.
sts LCDDR0, r20
sts LCDDR6, r21
ret
C Code Example(1)
Void LCD_update(unsigned char data1, data2);
{
/* LCD Blanking and Low power waveform are unchanged. */
/* Update Display memory. */
LCDDR0 = data1;
LCDDR6 = data2;
}
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Note: 1. See ”About Code Examples” on page 10.
Assembly Code Example(1)
LCD_disable:
; Wait until a new frame is started.
Wait_1:
lds r16, LCDCRA
sbrs r16, LCDIF
rjmp Wait_1
; Set LCD Blanking and clear interrupt flag
; by writing a logical one to the flag.
ldi r16, (1<<LCDEN)|(1<<LCDIF)|(1<<LCDBL)
sts LCDCRA, r16
; Wait until LCD Blanking is effective.
Wait_2:
lds r16, LCDCRA
sbrs r16, LCDIF
rjmp Wait_2
; Disable LCD.
ldi r16, (0<<LCDEN)
sts LCDCRA, r16
ret
C Code Example(1)
Void LCD_disable(void);
{
/* Wait until a new frame is started. */
while ( !(LCDCRA & (1<<LCDIF)) )
;
/* Set LCD Blanking and clear interrupt flag */
/* by writing a logical one to the flag. */
LCDCRA = (1<<LCDEN)|(1<<LCDIF)|(1<<LCDBL);
/* Wait until LCD Blanking is effective. */
while ( !(LCDCRA & (1<<LCDIF)) )
;
/* Disable LCD */
LCDCRA = (0<<LCDEN);
}
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23.5 LCD Register Description
23.5.1 LCDCRA – LCD Control and Status Register A
• Bit 7 – LCDEN: LCD Enable
Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned
off immediately. Turning the LCD Controller/Driver off while driving a display, enables ordinary
port function , and DC voltage can be applied to the display if ports are configured as output. It is
recommended to drive output to ground if the LCD Controller/Driver is disabled to discha rge the
display.
• Bit 6 – LCDAB: LCD Low Power Waveform
When LCDAB is written logic zero, the default waveform is output on the LCD pins. When
LCDAB is written logic one, the Low Power Waveform is output on the LCD pins. If this bit is
modified during display operation the change takes place at the beginning of a new frame.
• Bit 5 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 4 – LCDIF: LCD Interrupt Flag
This bit is set by hardwar e at the b egin ning of a ne w f rame , at the same ti me as t he di splay da ta
is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and the I-bit in SREG
are set. LCDIF is cleared by hardware when executing the correspo nding Interrupt Handling
Vector. Alternatively, writing a logical one to the flag clears LCDIF. Beware that if doing a Read-
Modify-Write on LCDCRA, a pending interrupt can be disabled. If Low Power Waveform is
selected the Interrupt Flag is set every second frame.
• Bit 3 – LCDIE: LCD Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the LCD St art of Frame Interrupt is
enabled.
• Bit 2 – LCDBD: LCD Buffer Disable
The intermediate voltage levels in the LCD are generated by an internal resistive voltage divider
and passed through buffer to increase the current driving capability. By writing this bit to one the
buffers are turned off and bypassed, resulting in decreased power consumption. The total resis-
tance of the voltage divider is nominally 400 kΩ between LCDCAP and GND.
• Bit 1 – LCDCCD: LCD Contrast Control Disable
Writing this bit to one disables the internal power supply for the LCD driver. The desired voltage
must be applied to the LCDCAP pin from an external power supply. To avoid conflict between
internal and external power supply, this bit must be written as '1' prior to or simultaneously with
writing '1' to the LCDEN bit.
Bit 7 6 5 4 3 2 1 0
(0xE4) LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL LCDCRA
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 0 – LCDBL: LCD Blanking
When this bit is written to one, the display will be blanked after completion of a frame. All seg-
ment and common pins will be driven to ground.
23.5.2 LCDCRB – LCD Control and Status Register B
• Bit 7 – LCDCS: LCD Clock Select
When this bit is written to ze ro, the system clock is used. When this b it is written to one, the
external asynchronous clock source is used. The asynchronous clock source is either
Timer/Counter Oscillator or external clock, depending on EXCLK in ASSR. See ”Asynchronous
operation of the Timer/Counter” on page 150 for further details.
• Bit 6 – LCD2B: LCD 1/2 Bias Select
When this bit is written to zero, 1/3 bias is used. When this bit is written to one, ½ bias is used.
Refer to the LCD Manufacture for recommended bias selection.
• Bit 5:4 – LCDMUX1:0: LCD Mux Select
The LCDMUX1:0 bits dete rmine the duty cycle. Comm on pins that are no t used are ordinary po rt
pins. The differ en t du ty se lections are show n in Table 23-2.
Note: 1. 1/2 bias when LCD2B is written to one and 1/3 otherwise.
• Bit 3 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDPM2:0: LCD Port Mask
The LCDPM2:0 bits determine the number of port pins to be used as segment drivers. The dif-
ferent selections ar e shown in Tabl e 23 -3 . Unused pins can be used as ordinary port pins.
Bit 765 4 3210
(0xE5) LCDCS LCD2B LCDMUX1 LCDMUX0 – LCDPM2 LCDPM1 LCDPM0 LCDCRB
Read/Write R/W R/W R/W R/W R R/W R/W R/W
Initial Value000 0 0000
Table 23-2. LCD Duty Select
LCDMUX1 LCDMUX0 Duty Bias COM Pin I/O Port Pin
0 0 Static Static COM0 COM1:3
0 1 1/2 1/2 or 1/3(1) COM0:1 COM2:3
101/31/2
or 1/3(1) COM0:2 COM3
111/41/2
or 1/3(1) COM0:3 None
Table 23-3. LCD Port Mask
LCDPM2 LCDPM1 LCDPM0 I/O P ort in Use as Segm ent
Driver Maximum Number of
Segments
0 0 0 SEG0:12 13
0 0 1 SEG0:14 15
0 1 0 SEG0:16 17
0 1 1 SEG0:18 19
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23.5.3 LCDFRR – LCD Frame Rate Register
• Bit 7 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS2:0: LCD Prescaler Sel ect
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in Table
23-4. Together they determine the prescaled LCD clock (clkLCD_PS), which is clocking the LCD
module.
1 0 0 SEG0:20 21
1 0 1 SEG0:22 23
1 1 0 SEG0:23 24
1 1 1 SEG0:24 25
Table 23-3. LCD Port Mask (Continued)
LCDPM2 LCDPM1 LCDPM0 I/O P ort in Use as Segm ent
Driver Maximum Number of
Segments
Bit 76543210
(0xE6) – LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 LCDFRR
Read/Write R R/W R/W R/W R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 23-4. LCD Prescaler Select
LCDPS2 LCDPS1 LCDPS0
Output from
Prescaler
clkLCD/N
Applied Prescaled LCD Clock Frequency
when LCDCD2:0 = 0, Duty = 1/4, and
Frame Rate = 64Hz
000clk
LCD/16 8.1 kHz
001clk
LCD/64 33 kHz
010clk
LCD/128 66 kHz
011clk
LCD/256 130 kHz
100clk
LCD/512 260 kHz
101clk
LCD/1024 520 kHz
110clk
LCD/2048 1 MHz
111clk
LCD/4096 2 MHz
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• Bit 3 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in Table 23-5. This Clock Divider gives extra flexibility in frame rate selection.
The frame frequency can be calculated by the following equation:
Where:
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see Ta b le 23 -5).
This is a very flexible sche me, and use rs are en couraged t o calculate th eir own tab le to inves ti-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation
is shown in Table 23-6.
Table 23-5. LCD Clock Divide
LCDCD2 LCDCD1 LCDCD0 Output from Prescaler
divided b y (D): clkLCD = 32.768 kHz, N = 16, and
Duty = 1/4, gives a fram e rate of:
000 1 256Hz
001 2 128Hz
0 1 0 3 85.3Hz
011 4 64Hz
1 0 0 5 51.2Hz
1 0 1 6 42.7Hz
1 1 0 7 36.6Hz
111 8 32Hz
Table 23-6. Example of frame rate calculation
clkLCD duty K N LCDCD2:0 D Frame Rate
4 MHz 1/4 8 2048 011 4 4000000/(8*2048*4) = 61Hz
4 MHz 1/3 6 2048 011 4 4000000/(6*2048*4) = 81Hz
32.768 kHz Static 8 16 000 1 32768/(8*16*1) = 256Hz
32.768 kHz 1/2 8 16 100 5 3276 8/(8*16*5) = 51Hz
fframe
fclkLCD
KND⋅⋅()
--------------------------=
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23.5.4 LCDCCR – LCD Contrast Contr ol Register
• Bits 7:5 – LCDDC2:0: LDC Display Configuration
The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescale d LCD
clock period, even if the selected drive time is longer. When using static bias or blanking, drive
time will always be one half prescaled LCD clock period.
• Bit 4 – LCDMDT: LCD Maximum Drive Time
Writing this bit to one turns the LCD drivers on 100% on the time, regardless of the drive time
configured by LCDDC2:0.
• Bits 3:0 – LCDCC3:0: LCD Contrast Control
The LCDCC3:0 bits determine the maximum voltage VLCD on segment and common pins. The
different selections are shown in Table 23 -8 on page 251. New values take effect every begin-
ning of a new frame.
Bit 76543210
(0xE7) LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 23-7. LCD Display Configuration
LCDDC2 LCDDC1 LCDDC0 Nominal drive time
0 0 0 30 0 µs
00170 µs
0 1 0 15 0 µs
0 1 1 45 0 µs
1 0 0 57 5 µs
1 0 1 85 0 µs
1 1 0 11 50 µs
11150% of clk
LCD_PS
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23.5.5 LCD Memor y Mapping
Write a LCD memory bit to one and the corresponding segment will be energized (visible).
Unused LCD Memory bits for the actual display can be used freely as storage.
Table 23-8. LCD Contrast Control
LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum Voltage VLCD
0000 2.60V
0001 2.65V
0010 2.70V
0011 2.75V
0100 2.80V
0101 2.85V
0110 2.90V
0111 2.95V
1000 3.00V
1001 3.05V
1010 3.10V
1011 3.15V
1100 3.20V
1101 3.25V
1110 3.30V
1111 3.35V
Bit 76543210
––––––––LCDDR19
COM3 –––––––SEG324LCDDR18
COM3 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 LCDDR17
COM3 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 LCDDR16
COM3 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 LCDDR15
––––––––LCDDR14
COM2 –––––––SEG224LCDDR13
COM2 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 LCDDR12
COM2 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 LCDDR11
COM2 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 LCDDR10
––––––––LCDDR9
COM1 –––––––SEG124LCDDR8
COM1 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 LCDDR7
COM1 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 LCDDR6
COM1 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 LCDDR5
––––––––LCDDR4
COM0 –––––––SEG024LCDDR3
COM0 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 LCDDR2
COM0 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 LCDDR1
COM0 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 LCDDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
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24. JTAG Interface and On-chip Debug System
24.0.1 Features
•JTAG (IEEE std. 1149.1 Compliant) Interfac e
•Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
•Debugger Access to:
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
–Program Counter
– EEPROM and Flash Memories
•Extensive On-chip Debug Support for Break Conditions, Including
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
•Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•On-chip Debugging Suppor ted by AVR Studio®
24.1 Overview
The AVR IEEE std. 1149.1 complia nt JTAG interface can be used for:
• Testing PCBs by using the JTAG Boundary-scan capability.
• Programming the non-volatile memories, Fuses and Lock bits.
• On-chip de bugging.
A brief description is given in the following sections. Detailed descriptions for Pro gramming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections ”Program-
ming via the JTAG Interface” on page 316 and ”IEEE 1149.1 (JTAG) Boundary-scan” on page
259, r espectively. The On-chip Debug support is considered being private JTAG instr uctions,
and distributed within ATMEL and to select ed third party vendors only.
Figure 24-1 on page 254 shows a block diagram of the JTAG interface and the On-chip Debug
system. The TAP Controller is a st ate machine co ntrolled by the TCK an d TMS signals. The TAP
Controller selects either the JTAG Instruction Register or one of several Data Registers as the
scan chain (Shift Register) between the TDI – input and TDO – output. The Instruction Register
holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-leve l te sting . The JTAG Pr og ram ming In te rface ( actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
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24.2 TAP – Test Access Port
The JTAG interface is accessed t hrough fou r of t he AVR’s pins . In JTAG ter minology, t hese pins
constitute the Test Access Port – TAP. These pins are:
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
machine.
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In . Serial input data to be shifted in to the Instruction Register or Data Register
(Scan Chains).
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the
TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP
pins are internally pulled high and the JTAG is enabled for Bounda ry-scan and programming.
The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
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Figure 24-1. Block Diagram
TAP
CONTROLLER
TDI
TDO
TCK
TMS
FLASH
MEMORY
AVR CPU
DIGITAL
PERIPHERAL
UNITS
JTAG / AVR CORE
COMMUNICATION
INTERFACE
BREAKPOINT
UNIT FLOW CONTROL
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
M
U
X
INSTRUCTION
REGISTER
ID
REGISTER
BYPASS
REGISTER
JTAG PROGRAMMING
INTERFACE
PC
Instruction
Address
Data
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
ANALOG
PERIPHERIAL
UNITS
I/O PORT 0
I/O PORT n
BOUNDARY SCAN CHAIN
Analog inputs
Control & Clock lines
DEVICE BOUNDARY
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Figure 24-2. TAP Controller State Diagram
24.3 TAP Contr oller
The TAP contro ller is a 1 6- sta te fi nite st ate m achin e t hat co ntro ls th e oper at ion of t h e Bound ary-
scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions
depicted in Figure 24-2 depend on the signal present on TMS (shown adjacent to each state
transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-
Logic-Reset.
As a definition in this docum e nt, the LSB is shifte d in an d out firs t for all Shift Reg ist er s.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• At the TMS input , ap ply the se qu en ce 1, 1, 0, 0 at the rising edges of TCK to ente r th e Shif t
Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG
instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.
The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
state. The MSB of t he inst ru ction is shift ed in when this st ate is lef t by set ti ng TMS high . While
the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the
TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and
TDO and controls the circuitry surrounding the selected Data Register.
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
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• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the par alle l output from the Sh ift Register path in the Up date- IR st ate . Th e Exit-I R, Pause-
IR, and Exit2-IR states are only used for navigating the state machine.
• At the TMS input, apply t he sequence 1, 0, 0 at the rising edges of TCK t o enter t he Shift Data
Register – Shift-DR state. While in this state, upload the selected Data Register (selected by
the present JTAG instruction in the JTAG Instruction Register) fro m the TDI input at the rising
edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during
input of all bits except the MSB. The MSB of the data is shifted in when this state is left by
setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to
the Data Register captured in the Capture-DR state is shifted out on the TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered betwe en selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note: Independent of the initial state of th e TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in ”Bibliography”
on page 258.
24.4 Using the Boundary-scan Chain
A complete description of the Boundary-scan capabilities are given in the section ”IEEE 1149.1
(JTAG) Boundary-scan” on page 259.
24.5 Using the On-chip Debug System
As shown in Figure 24-1 on page 254, the hardware support for On-chip Debugging consists
mainly of:
• A scan chain on the interface between the internal AVR CPU and the internal peripheral units.
• Break Point unit.
• Communication interface between the CPU and JTAG system.
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped locat ion which is par t of the communicat ion interface be tween the CPU and t he
JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two
Program Memory Break Points, and two combined Break Points. Together, the four Break
Points can be configured as either:
• 4 single Program Memory Break Points.
• 3 Single Program Memory Break Point + 1 single Data Memory Break Point.
• 2 single Program Memory Break Points + 2 single Data Memory Break Points.
• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range
Break Point”).
• 2 single Program Memory Break P oints + 1 Data Memory Break P oint with mask (“r ange Break
Point”).
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A debugger, like the AVR Studio, may however use one or more of these resources for its inter-
nal purpose, leaving less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG
Instructions” on page 257.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the
OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system
to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or
LB2 Lock bits are set. Otherwise, the O n-chip debug system would have provided a back-door
into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR device with
On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.
AVR Studio supports source level execution of Assembly programs assembled with Atmel Cor-
poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.
AVR Studio runs under Microsoft® Windows® 95/98/2000, Windows NT® and Windows XP®.
For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high-
lights are presen ted in this document.
All necessary executio n commands are available in AVR Stud io, both on source level and on
disassembly level. T he user can execute the pr ogram, single step throug h the code either by
tracing into or stepping over functions, st ep out of funct ions, place the cur sor on a stateme nt and
execute until the statement is reached, stop the execution, and reset the execution target. In
addition, the user can have an unlimited number of code Break Points (using the BREAK
instruction) and up to two data memory Break Points, alternatively combined as a mask (range)
Break Point.
24.6 On-chip Debug Specific JTAG Instructions
The On-chip debug su pport is considered be ing privat e JTAG instruction s, and dist ribut ed within
ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.
24.6.1 PRIVATE0; 0x8
Private JTAG instruction for accessing On-chip debug system.
24.6.2 PRIVATE1; 0x9
Private JTAG instruction for accessing On-chip debug system.
24.6.3 PRIVATE2; 0xA
Private JTAG instruction for accessing On-chip debug system.
24.6.4 PRIVATE3; 0xB
Private JTAG instruction for accessing On-chip debug system.
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24.7 On-chip Debug Related Register in I/O Memory
24.7.1 OCDR – On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the reg ist er has been wr it te n. When th e CPU re ads the OCDR Regist er the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shar ed with a standard I/O location . In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is pro grammed, and the debugger ena bles
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for furthe r information on how to use this register.
24.8 Using the JTAG Programming Capabilities
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port. See ”Boundary-scan Related Register in I/O Memory” on page 279.
The JTAG programming capability supports:
• Flash programming an d verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programmin g and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section ”Programming via the JTAG Interface” on page 316.
24.9 Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992.
Bit 7 6543210
0x31 (0x51) MSB/IDRD LSB OCDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0000000
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25. IEEE 1149.1 (JTAG) Boundary-scan
25.1 Features
•JTAG (IEEE std. 1149.1 compliant) Interface
•Boundary-scan Capabilities According to the JTAG Standard
•Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
•Supports the Optional IDCODE Instruction
•Additional Public AVR_RESET Instruction to Reset the AVR
25.2 System Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be
used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the
ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to
have the AVR device in reset during test mode. If not reset, inputs to the de vice may be deter-
mined by the scan operations, and the internal software may be in an undetermined state when
exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high
impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction
can be issued to make the shortest possible scan chain through the device. The device can be
set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and lo ading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial value s to the scan r ing, to avoid da maging the board when issuing the EXT EST
instruction for the first tim e. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins duri ng normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG T CK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
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25.3 Data Registers
The Data Registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Regist er
• Reset Register
• Boundary-scan Chain
25.3.1 By pas s Register
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
25.3.2 Device Identification Register
Figure 25-1 shows the structure of the Device Identification Register.
Figure 25-1. The Format of the Device Identification Register.
25.3.2.1 Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number
follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
25.3.2.2 Part Nu mb e r
The part number is a 16-bit code identifying the component. The JTAG Part Number for
ATmega169P is listed in Table 27-6 on page 299.
25.3.2.3 Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID
for ATMEL is listed in Table 27-6 on page 299.
25.3.3 Reset Register
The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Re gister can a lso replace t he functi on of th e unimplement ed opt ional
JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the fuse set-
tings for the clock options, the part will remain reset for a reset tim e-out period (refer to ”Clock
Sources” on page 31) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 25-2 on page 261.
MSB LSB
Bit 31 28 27 12 11 1 0
Device ID Version Part Number Manufacturer ID 1
4 bits 16 bits 11 bits 1-bit
261
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ATmega169P
Figure 25-2. Reset Register
25.3.4 Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections.
See ”Boundary-scan Chain” on page 262 for a comple te desc rip tio n.
25.4 Boundary-scan Specifi c JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction
is not implemented, but all outputs with tri-state capability can be set in high-impedant state by
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Re gister is selected as path between TDI and TDO for each instruction.
25.4.1 EXTEST; 0x0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package . For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the int erface be tween t he analog an d th e digita l logic is in the scan chain . The con-
tents of the latche d outputs of the Bound ary-scan chain is driven out as soon as the JTAG IR-
Register is loaded with the EXTEST instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Inte rnal Scan Chain is shifted by the TCK input.
• Update-DR: Data from th e scan chain is applied to output pins.
25.4.2 IDCODE; 0x1
Optional JTAG instruction selecting the 32-bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number an d the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
DQ
From
TDI
ClockDR · AVR_RESET
To
TDO
From Other Internal and
External Reset Sources
Internal reset
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The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
25.4.3 SAMPLE_ PRELOAD; 0x2
Mandatory JTAG instruction for pre-loa ding the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boun dary-scan chain is applied to the output lat ches. However , th e
output latch es are not connected to th e pins.
25.4.4 AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
25.4.5 BYPASS; 0xF
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
25.5 Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
25.5.1 Scanning the Digital Port Pins
Figure 25-3 on page 263 shows the Boundary-scan Cell for a bi-directional port pin with pull-up
function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn –
function, and a bi-directional pin cell that combines the three signals Output Control – OCxn,
Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and
pin indexes are not used in the following description:
The Boundary-scan logic is not inclu ded in the fi gures in th e datasheet. Fig ure 25-4 on p age 264
shows a simple digital port pin as described in the section ”I/O-Ports” on p age 65. The Boun d-
ary-scan details from Figure 25-3 on page 263 replaces the dashed box in Figure 25-4 on page
264.
When no alternate port function is present, the Input Data – ID – corre sponds to the PINxn Reg-
ister value (but ID has no synchro nizer), Ou tput Data corre sponds to the PORT Regi ster, Ou tput
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Control corresponds to the Dat a Direction – DD Register, and the Pull-up Enable – PUExn – cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 25-4 on page 264
to make the scan chain read the actual pin value. For Analog function, there is a direct connec-
tion from the external pin to the analog circuit, and a scan chain is inserted on the interface
between the digital logic and the analog circuitry.
Figure 25-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
DQ DQ
G
0
1
0
1
DQ DQ
G
0
1
0
1
0
1
0
1
DQ DQ
G
0
1
Port Pin (PXn)
VccEXTESTTo Next CellShiftDR
Output Control (OC)
Pullup Enable (PUE)
Output Data (OD)
Input Data (ID)
From Last Cell UpdateDRClockDR
FF2 LD2
FF1 LD1
LD0FF0
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Figure 25-4. General Port Pin Schematic Diagram
CLK
RPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
WPx: WRITE PINx REGISTER
PUD: PULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
Q
Q
D
Q
QD
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
I/O
See Boundary-scan
Description for Details!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn RPx: READ PORTx PIN
RRx
RESET
Q
QD
CLR
PORTxn
WPx
0
1
WRx
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ATmega169P
25.5.2 Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active hig h
logic for High Voltage Parallel program ming. An observe-o nly cell as shown in Figure 25-5 is
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 25-5. Observe-only Cell
25.5.3 Scanning the Clock Pins
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 25-6 shows how each Oscillator with external connection is supported in the scan chain.
The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
Oscillator does not have external connections.
Figure 25-6. Boundary-scan Cells for Oscillators and Clock Options
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
From System Pin To System Logic
FF1
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
To System Logic
FF1
0
1
DQ DQ
G
0
1
From
Previous
Cell
ClockDR UpdateDR
ShiftDR
To
Next
Cell EXTEST
From Digital Logic
XTAL1/TOSC1 XTAL2/TOSC2
Oscillator
ENABLE OUTPUT
266
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Table 25-1 summaries the scan registers for the external clock pin XTAL1, oscillators with
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Notes: 1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
the internal Oscillator and th e JTAG TCK clock. If possible, scanning an extern al clock is
preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
configuration is considered fixed f or a giv en application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
25.5.4 Scanning the Analog Comparator
The relevant Compa rator signals regarding Boundary-scan are shown in Figure 25-7. The
Boundary-sca n cell from Figure 25-8 on page 267 is attached to each of these signals. The sig-
nals are described in Table 25-2 on page 267.
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Figure 25-7. Analog Comparator
Table 25-1. Scan Signals for the Oscillator(1)(2)(3)
Enable Signal Scanned
Clock Line Clock Option Scanned Clock Line
when not Used
EXTCLKEN EXTCLK (XTAL1) External Clock 0
OSCON OSCCK External Crystal
Exter nal Ceramic Resonator 1
OSC32EN OSC32CK Low Freq. External Crystal 1
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
AC_IDLE
ACO
ADCEN
ACD
267
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ATmega169P
Figure 25-8. General Boundary-scan cell Used for Signals for Comparator and ADC
Table 25-2. Boundary-scan Signals for the Analog Comparator
Signal
Name
Direction as
Seen from the
Comparator Description
Recommended
Input when Not
in Use
Output Values when
Recommended Inputs
are Used
AC_IDLE input Tur ns off Analog
Comparator when
true 1Depends upon µC code
being executed
ACO output Analog Comparator
Output
Will become input
to µC code being
executed 0
ACME input Uses output signal
from ADC mux when
true 0Depends upon µC code
being executed
ACBG input Bandgap Reference
enable 0Depends upon µC code
being executed
0
1
DQ DQ
G
0
1
From
Previous
Cell
ClockDR UpdateDR
ShiftDR
To
Next
Cell EXTEST
To Analog Circuitry/
To Digital Logic
From Digital Logic/
From Analog Ciruitry
268
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25.5.5 Scanning the ADC
Figure 25-9 shows a block diagram of the ADC with all relevant control and observe signals. The
Boundary-scan cell fr om Figu re 25-5 on pa ge 26 5 is attached to ea ch of th ese signals. Th e ADC
need not be used for pure connectivity testing, since all analog inputs are shared with a digital
port pin as well.
Figure 25-9. Analog to Digital Converter.
The signals ar e described briefly in Table 25-3 on page 269.
10-bit DAC +
-
AREF
PRECH
DACOUT
COMP
MUXEN_7
ADC_7
MUXEN_6
ADC_6
MUXEN_5
ADC_5
MUXEN_4
ADC_4
MUXEN_3
ADC_3
MUXEN_2
ADC_2
MUXEN_1
ADC_1
MUXEN_0
ADC_0
NEGSEL_2
ADC_2
NEGSEL_1
ADC_1
NEGSEL_0
ADC_0
EXTCH
+
-
1x
ST
ACLK
AMPEN
1.11V
ref
IREFEN
AREF
VCCREN
DAC_9..0
ADCEN
HOLD
PRECH
GNDEN
PASSEN
COMP
SCTEST ADCBGEN
To Comparator
1.22V
ref
ACTEN
AREF
269
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ATmega169P
Table 25-3. Boundary-scan Signals for the ADC(1)
Signal
Name
Direction
as Seen
from the
ADC Description
Recommen-
ded Input
when not in
use
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
COMP Output Comparator Output 0 0
ACLK Input
Clock signal to
differential amplifier
implemented as Switch-
cap filters
00
ACTEN Input Enable path from
differential amplifier to
the comparator 00
ADCBGEN Input Enable Band-gap
reference as negative
input to comparator 00
ADCEN Input P ower-on signal to the
ADC 00
AMPEN Input Power-on signal to the
differential amplifier 00
DAC_9 Input Bit 9 of digital value to
DAC 11
DAC_8 Input Bit 8 of digital value to
DAC 00
DAC_7 Input Bit 7 of digital value to
DAC 00
DAC_6 Input Bit 6 of digital value to
DAC 00
DAC_5 Input Bit 5 of digital value to
DAC 00
DAC_4 Input Bit 4 of digital value to
DAC 00
DAC_3 Input Bit 3 of digital value to
DAC 00
DAC_2 Input Bit 2 of digital value to
DAC 00
DAC_1 Input Bit 1 of digital value to
DAC 00
DAC_0 Input Bit 0 of digital value to
DAC 00
EXTCH Input
Connect ADC channels 0
- 3 to by-pass path
around differential
amplifier
11
GNDEN Input Ground the negative
input to comparator when
true 00
270
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ATmega169P
HOLD Input
Sample & Hold signal.
Sample analog signal
when low. Hold signal
when high. If differential
amplifier is used, this
signal must go active
when ACLK is high.
11
IREFEN Input Enables Band-gap
reference as AREF
signal to DAC 00
MUXEN_7 Input Input Mux bit 7 0 0
MUXEN_6 Input Input Mux bit 6 0 0
MUXEN_5 Input Input Mux bit 5 0 0
MUXEN_4 Input Input Mux bit 4 0 0
MUXEN_3 Input Input Mux bit 3 0 0
MUXEN_2 Input Input Mux bit 2 0 0
MUXEN_1 Input Input Mux bit 1 0 0
MUXEN_0 Input Input Mux bit 0 1 1
NEGSEL_2 Input Input Mux for negative
input for differential
signal, bit 2 00
NEGSEL_1 Input Input Mux for negative
input for differential
signal, bit 1 00
NEGSEL_0 Input Input Mux for negative
input for differential
signal, bit 0 00
PASSEN Input Enable pass-gate of
differential amplifier. 11
PRECH Input Precharge output latch of
comparator. (Active low) 11
SCTEST Input
Switch-cap TEST enable.
Output from differential
amplifier is sent out to
Port Pin having ADC_4
00
ST Input
Output of differential
amplifier will settle faster
if this signal is high first
two ACLK periods afte r
AMPEN goes high.
00
VCCREN Input Selects Vcc as the ACC
reference voltage. 00
Table 25-3. Boundary-scan Signals for the ADC(1)
Signal
Name
Direction
as Seen
from the
ADC Description
Recommen-
ded Input
when not in
use
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
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ATmega169P
Note: 1. Incorrect setting of the switches in Figure 25-9 on page 268 will make signal contention and
may damage the part. There are several input choices to the S&H circuitry on the negative
input of the output comparator in Figure 25-9 on page 268. Make sure only one path is
selected from either one ADC pin, Bandgap reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 25-3 on
page 269 should be used. The us er is re com men ded not to use the Differential Amplifier during
scan. Switch-Cap based differential amplifier requires fast operation and accurate timing which
is difficult to obtain when used in a scan chain. Details concerning operations of the differential
amplifier is therefore not provided.
The AVR ADC is based on the analo g circuitry sho wn in Fi gure 2 5-9 on pag e 268 w it h a su cce s-
sive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the
problem is usually to ensure that an applied analog voltage is measure d within some limits. This
can easily be done without running a successive approximation algorithm: apply the lower limit
on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the
upper limit on the digi tal DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as we ll.
When using the ADC, remember the following:
• The port pin f or the ADC channel in use must be configured to be an input with pull-up disab led
to avoid signal content ion.
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
• The D AC values must be stable at the midpoint value 0x200 when ha ving the HOLD signal lo w
(Sample mode).
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to VCC.
The recommended values from Table 25-3 on page 269 are used unless othe r valu es ar e give n
in the algorithm in Table 25-4 on page 272. Only th e DAC and port pin va lues of the Scan Chain
are shown. The column “Actions” describes what JTAG instruction to be used before filling the
Boundary-scan Register with the succeeding columns. The verification should be done on the
data scanned out when scanning in the data on the same row in the table.
The lower limit is: 1024 1.5V0,95 5V⁄⋅⋅ 291 0x123==
The upper limit is: 1 024 1.5V1.05 5V⁄⋅⋅ 323 0x143==
272
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Using this algorithm, the timi ng constraint on the HOLD signal constrains the TC K clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, thold,max
25.6 Boundary-scan Order
Table 25-5 shows the Scan ord er between TDI and TDO when the Boundary-scan chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitu te the most significant bits of the s can chain regardless of which
physical pin they are connected to. In Figure 25-3 on page 263, PXn. Data corresponds to FF0,
PXn. Control corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, bit 5, bit
6, and bit 7 of Port F is not in the scan chain, since these pins constitute the TAP pins when the
JTAG is enabled.
Table 25-4. Algorithm for Usin g th e AD C
Step Actions ADCEN DAC MUXEN HOLD PRECH PA3.
Data PA3.
Control
PA3.
Pull-up_
Enable
1SAMPLE_P
RELOAD 1 0x200 0x08 1 1 0 0 0
2 EXTEST 1 0x200 0x08 0 1 0 0 0
31 0x200 0x08 1 1 0 0 0
41 0x123 0x08 1 1 0 0 0
51 0x123 0x08 1 0 0 0 0
6
Verify the
COMP bit
scanned out
to be 0
1 0x200 0x08 1 1 0 0 0
71 0x200 0x08 0 1 0 0 0
81 0x200 0x08 1 1 0 0 0
91 0x143 0x08 1 1 0 0 0
10 1 0x143 0x08 1 0 0 0 0
11
Verify the
COMP bit
scanned out
to be 1
1 0x200 0x08 1 1 0 0 0
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
197 AC_IDLE
Comparator
196 ACO
195 ACME
194 AINBG
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193 COMP
ADC
192 ACLK
191 ACTEN
190 PRIVATE_SIGNAL1(1)
189 ADCBGEN
188 ADCEN
187 AMPEN
186 DAC_9
185 DAC_8
184 DAC_7
183 DAC_6
182 DAC_5
181 DAC_4
180 DAC_3
179 DAC_2
178 DAC_1
177 DAC_0
176 EXTCH
175 GNDEN
174 HOLD
173 IREFEN
172 MUXEN_7
171 MUXEN_6
170 MUXEN_5
169 MUXEN_4
168 MUXEN_3
ADC
167 MUXEN_2
166 MUXEN_1
165 MUXEN_0
164 NEGSEL_2
163 NEGSEL_1
162 NEGSEL_0
161 PASSEN
160 PRECH
159 ST
158 VCCREN
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
274
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ATmega169P
157 PE0.Data
Port E
156 PE0.Control
155 PE0.Pull-up_Enable
154 PE1.Data
153 PE1.Control
152 PE1.Pull-up_Enable
151 PE2.Data
150 PE2.Control
149 PE2.Pull-up_Enable
148 PE3.Data
147 PE3.Control
146 PE3.Pull-up_Enable
145 PE4.Data
144 PE4.Control
143 PE4.Pull-up_Enable
142 PE5.Data
141 PE5.Control
140 PE5.Pull-up_Enable
139 PE6.Data
138 PE6.Control
137 PE6.Pull-up_Enable
136 PE7.Data
135 PE7.Control
134 PE7.Pull-up_Enable
133 PB0.Data Port B
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
275
8018P–AVR–08/10
ATmega169P
132 PB0.Control
Port B
131 PB0.Pull-up_Enable
130 PB1.Data
129 PB1.Control
128 PB1.Pull-up_Enable
127 PB2.Data
126 PB2.Control
125 PB2.Pull-up_Enable
124 PB3.Data
123 PB3.Control
122 PB3.Pull-up_Enable
121 PB4.Data
120 PB4.Control
119 PB4.Pull-up_Enable
118 PB5.Data
117 PB5.Control
116 PB5.Pull-up_Enable
115 PB6.Data
114 PB6.Control
113 PB6.Pull-up_Enable
112 PB7.Data
111 PB7.Control
110 PB7.Pull-up_Enable
109 PG3.Data
Port G
108 PG3.Control
107 PG3.Pull-up_Enable
106 PG4.Data
105 PG4.Control
104 PG4.Pull-up_Enable
103 PG5 (Observe Only)
102 RSTT Reset Logic
(Observe-only)
101 RSTHV
100 EXTCLKEN
Enable signals f or main Cloc k/Oscillators
99 OSCON
98 RCOSCEN
97 OSC32EN
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
276
8018P–AVR–08/10
ATmega169P
96 EXTCLK (XTAL1)
Clock input and Oscillators for the main clock
(Observe-only)
95 OSCCK
94 RCCK
93 OSC32CK
92 PD0.Data
Port D
91 PD0.Control
90 PD0.Pull-up_Enable
89 PD1.Data
88 PD1.Control
87 PD1.Pull-up_Enable
86 PD2.Data
85 PD2.Control
84 PD2.Pull-up_Enable
83 PD3.Data
82 PD3.Control
81 PD3.Pull-up_Enable
80 PD4.Data
79 PD4.Control
78 PD4.Pull-up_Enable
77 PD5.Data
76 PD5.Control
75 PD5.Pull-up_Enable
74 PD6.Data
73 PD6.Control
72 PD6.Pull-up_Enable
71 PD7.Data
70 PD7.Control
69 PD7.Pull-up_Enable
68 PG0.Data
Port G
67 PG0.Control
66 PG0.Pull-up_Enable
65 PG1.Data
64 PG1.Control
63 PG1.Pull-up_Enable
62 PC0.Data Port C
61 PC0.Control
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
277
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ATmega169P
60 PC0.Pull-up_Enable
Port C
59 PC1.Data
58 PC1.Control
57 PC1.Pull-up_Enable
56 PC2.Data
55 PC2.Control
54 PC2.Pull-up_Enable
53 PC3.Data
52 PC3.Control
51 PC3.Pull-up_Enable
50 PC4.Data
49 PC4.Control
48 PC4.Pull-up_Enable
47 PC5.Data
46 PC5.Control
45 PC5.Pull-up_Enable
44 PC6.Data
43 PC6.Control
42 PC6.Pull-up_Enable
41 PC7.Data
40 PC7.Control
39 PC7.Pull-up_Enable
38 PG2.Data
Port G37 PG2.Control
36 PG2.Pull-up_Enable
35 PA7.Data
Port A
34 PA7.Control
33 PA7.Pull-up_Enable
32 PA6.Data
31 PA6.Control
30 PA6.Pull-up_Enable
29 PA5.Data
28 PA5.Control
27 PA5.Pull-up_Enable
26 PA4.Data
25 PA4.Control
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
278
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ATmega169P
Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.
25.7 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. A BSDL file for ATmega169P
is available.
24 PA4.Pull-up_Enable
Port A
23 PA3.Data
22 PA3.Control
21 PA3.Pull-up_Enable
20 PA2.Data
19 PA2.Control
18 PA2.Pull-up_Enable
17 PA1.Data
16 PA1.Control
15 PA1.Pull-up_Enable
14 PA0.Data
13 PA0.Control
12 PA0.Pull-up_Enable
11 PF3.Data
Port F
10 PF3.Control
9 PF3.Pull-up_Enable
8PF2.Data
7PF2.Control
6 PF2.Pull-up_Enable
5PF1.Data
4PF1.Control
3 PF1.Pull-up_Enable
2PF0.Data
1PF0.Control
0 PF0.Pull-up_Enable
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
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25.8 Boundary-scan Related Register in I/O Memory
25.8.1 MCUCR – MCU Control Register
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
25.8.2 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Bit 76543210
0x35 (0x55) JTD - - PUD – – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value00000000
Bit 76543210
0x34 (0x54) –––JTRFWDRF BORF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
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26. Boot Loader Support – Read-While-Write Self-Programming
26.1 Features
•Read-While-Write Self-Programming
•Flexible Boot Memory Size
•High Security (Separate Boot Lock Bits for a Flexible Protection)
•Separate Fuse to Select Reset Vector
•Optimized P age(1) Size
•Code Efficient Algorithm
•Efficient Read-Modify-Write Support
Note: 1. A page is a section in the Flash consisting of se ver al bytes (see Table 27-7 on page 299) used
during programming. The page organization does not affect normal operation.
26.2 Overview
The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for
downloading and up loading progr am code by the MCU itsel f. This feature allows flexible applica-
tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The
Boot Loader program can use any availab le data interface and associated protocol to read code
and write (program) that code into the Flash memory, or read the code from the program mem-
ory. The program code within the Boot Loader section has the capability to write into the e ntire
Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it
can also erase itself from the code if the feature is not needed anymore. The size of the Boot
Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot
Lock bits which can be set independently. This gives the user a unique flexibility to select differ-
ent levels of protection.
26.3 Application and Boot Loader Flash Sections
The Flash memory is organized in two main sections, the Application section and the Boot
Loader section (s ee Figure 26-2 on pa ge 28 3). The size of the d iffer ent sections is con figured by
the BOOTSZ Fuses as shown in Table 26-6 on page 292 and Figure 26-2 on page 283. These
two sections can have dif ferent level of protection since they have different sets of Lock bits.
26.3.1 Application Section
The Application section is the section of the Flash that is used for storing the application code.
The protection level for the Application section can be selected by the applicat ion Boot Lock bits
(Boot Lock bits 0), see Table 26-2 on page 284. The Application section can never store any
Boot Loader code sin ce the SPM instruction is disab led when executed from the Application
section.
26.3.2 BLS – Boot Loader Section
While the Application section is used for storing the application code, the The Boot Loader soft-
ware must be located in the BLS since the SPM instruction can initiate a programming when
executing from the BLS only. The SPM instruction can access the entire Flash, including the
BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader
Lock bits (Boot Lock bits 1), see Table 26-3 on page 284.
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26.4 Read-While-Write and No Read-While-Write Flash Sections
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-
ware update is depende nt on which address that is being progr ammed. In addition to the two
sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also
divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-
Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 26-
7 on page 293 and Figure 26-2 on page 283. The main difference between the two sections is:
• When erasing or writing a page located inside the RWW section, the NRWW section can be
read during the operation.
• When erasing or writing a page located inside the NR WW section , the CPU is halted during the
entire operation.
Note that the user software ca n never read any code th at is located in side the RWW section dur-
ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which
section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.
26.4.1 RWW – Read-While-Write Section
If a Boot Loader software update is programming a page inside the RWW section, it is possible
to read code from the Flash, but only code that is located in the NRWW section. During an on-
going programming, the software must ensure that the RWW section never is being read. If the
user software is trying to read code that is located inside the RWW section (that is, by a
call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown
state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-
tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy
bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read
as logical one as long as the RWW section is blocked for reading. After a programming is com-
pleted, the RWWSB must be cleared by software before reading code located in the RWW
section. See ”SPMCSR – Store Program Memory Control and Status Register” on page 294. for
details on how to clear RWWSB.
26.4.2 NRWW – No Read-While-Write Section
The code located in the NRWW section can be read when the Boot Loader software is updating
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU
is halted during the entire Page Erase or Page Write operation.
Table 26-1. Read-While-Write Features
Which Section does the Z-pointer
Address During the Programming? Which Section Can be
Read During Programming? Is the
CPU Halted? Read-While-Write
Supported?
RWW Section NRWW Section No Yes
NRWW Section None Yes No
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Figure 26-1. Read-While-Write vs. No Read-While-Write
Read-While-Write
(RWW) Section
No Read-While-Write
(NRWW) Section
Z-pointer
Addresses RWW
Section
Z-pointer
Addresses NRWW
Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation
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Figure 26-2. Memory Sections
Note: 1. The parameters in the figure above are given in Table 26-6 on page 292.
0x0000
Flashend
Program Memory
BOOTSZ = '11'
Application Flash Section
Boot Loader Flash Section
Flashend
Program Memory
BOOTSZ = '10'
0x0000
Program Memory
BOOTSZ = '01'
Program Memory
BOOTSZ = '00'
Application Flash Section
Boot Loader Flash Section
0x0000
Flashend
Application Flash Section
Flashend
End RWW
Start NRWW
Application Flash Section
Boot Loader Flash Section
Boot Loader Flash Section
End RWW
Start NRWW
End RWW
Start NRWW
0x0000
End RWW, End Application
Start NRWW, Start Boot Loader
Application Flash SectionApplication Flash Section
Application Flash Section
Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section
Read-While-Write SectionNo Read-While-Write SectionRead-While-Write SectionNo Read-While-Write Section
End Application
Start Boot Loader
End Application
Start Boot Loader
End Application
Start Boot Loader
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26.5 Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separ at e sets of Boot Lock bits which ca n be set indepen de ntly. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU.
• To protect only the Boot Loader Flash section from a softw are update by the MCU.
• To protect only the Application Flash section from a software update by the MCU.
• Allow software update in the entire Flash.
See Table 26-2 and Table 26-3 for further details. The Boot Lock bits and general Lock bits can
be set in software and in Serial or Parallel Programming mode, but they can be cleared by a
Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the pro-
gramming of the Flash memory by SPM instruc tion. Similarly, the general Read/Write Lock
(Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is at tempted.
Note: 1. “1” means unprogrammed, “0” means programmed
Note: 1. “1” means unprogrammed, “0” means programmed
Table 26-2. Boot Lock Bit0 Protection Modes (Application Section)(1)
BLB0 Mode BLB02 BLB01 Protection
111
No restrictions for SPM or LPM accessing the Application
section.
2 1 0 SPM is not allowed to write to the Application section.
300
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read
from the Application section. If Interrupt Vecto r s are placed in
the Boot Loader section, interrupts are disabled while executing
from the Application section.
401
LPM executing from the Boot Loader section is not allowed to
read from the Application section. If Interrupt Vectors are placed
in the Boot Loader section, interrupts are disabled while
executing from the Application section.
Table 26-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB1 Mode BLB12 BLB11 Protection
111
No restrictions for SPM or LPM accessing the Boot Load er
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
300
SPM is not allowed to write to the Boot Loader section, and LPM
e xecuting from the Application section is not allowed to read
from the Boot Loader section. If Interr upt Vectors are placed in
the Application section, interrupts are disabled while exe c uting
from the Boot Loader section.
401
LPM executing from the Application section is not al lowed to
read from the Boot Loader section. If Interrupt Vectors are
placed in the Application secti on, interrupts are disabled while
executing from the Boot Loader section.
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26.6 Entering the Boot Loader Program
Entering the Boot Loader takes place by a jump or call from the application program. This may
be initiated by a trigge r such as a command received via USART, or SPI interface. Alternatively,
the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash
start address afte r a reset. In th is case, the Boot Loader is star ted after a reset. After the applica-
tion code is loaded, the program can start execut ing the application code. Note that the fuses
cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-
grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be
changed through the serial or parallel pr ogramming interface.
Note: 1. “1” means unprogrammed, “0” means programmed
Table 26-4. Boot Reset Fuse(1)
BOOTRST Reset Address
1 Reset Vector = Application Reset (address 0x0000)
0 Reset Vector = Boot Loader Reset (see Table 26-6 on page 292)
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26.7 Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Since the Flash is organized in pages (see Table 27-7 on page 299), the Program Counter can
be treated as havin g two different sections. One sect ion, consisting of the least signif icant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in Figure 26-3. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the Boot Loader software
addresses the same page in both the Page Erase and Pa ge Write operation. Once a program-
ming operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
The only SPM operation that does no t use the Z-pointer is Setting the Boot Loader Lock bits.
The content of the Z-pointer is ignored and will have no effect on the operation. The LPM
instruction does also use the Z-pointer to store the address. Since this instruction addresses the
Flash byte-b y-b yte, also the LSB (bit Z0) of th e Z- po in te r is used .
Figure 26-3. Addressing the Flash During SPM(1)
Note: 1. The different variables used in Figure 26-3 are listed in Table 26-8 on page 293.
2. PCPAGE and PCWORD are listed in Table 27-7 on page 299.
Bit 151413121110 9 8
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30) Z7Z6Z5Z4Z3Z2Z1Z0
76543210
PROGRAM MEMORY
0115
Z - REGISTER
BIT
0
ZPAGEMSB
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
INSTRUCTION WORD
PA G E PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PA G E
PCWORDPCPAGE
PCMSB PAGEMSB
PROGRAM
COUNTER
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26.8 Self-Programming the Flash
The program memory is updated in a page by page fashion. Before programming a page with
the data stored in th e temporary page buf fer, the page must be erased. The temp orary page bu f-
fer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Writ e operation:
Alternative 1, fill the buffer before a Page Erase
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of t he page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,
the Boot Loader pr ovides an effe ctive Rea d- Modify- Wr ite fe at ure which allo ws t he use r soft ware
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not p ossible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page addre ss used in both the Page Erase and P age Write operation is ad dressing the same
page. See ”Boot Loader: Simple Assembly Code Example” on page 291 for an assem bly code
example.
26.8.1 Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR.(1) The data in R1 and R0 is igno red.
The page address must be written to PCPAGE in the Z-register. Othe r bits in the Z-pointer will
be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
• Page Eras e to the NRWW section: The CPU is halted during the operation.
Note: 1. If an interrupt occurs in the timed sequence the four cycle access cannot be guaranteed. In
order to ensure atomic operation you must disable interrupes before writing to SPMCSR.
26.8.2 Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each addr ess without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
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26.8.3 Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
26.8.4 Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling
the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should
be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in ”Interrupts” on page 56.
26.8.5 Consideration While Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is r ecommended to progra m the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
26.8.6 Prevent Reading the RWW Section During Self-Programming
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Se lf-Pro grammin g the In terr upt Vect or t able should b e move d to the BLS
as described in ”Interrupts” on page 56, or the interrupts must be disabled. Before addressing
the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See ”Boot Loader: Simple Assembly Code Example” on
page 291 for an example.
26.8.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write
“X0001001” to SPMCSR and execu te SPM within four clock cycles after writing SPMCSR.
See Table 26-2 on page 284 and Table 26-3 on page 284 for how the different settings of the
Boot Loader bits affect the Flash access.
If bits 5..0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM
instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-
pointer is don’t care during this operation, but for future compatibility it is recommended to load
the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility it is
also recommended to set bit 7 and bit 6 in R0 to “1” when writing the Lock bits. When program-
ming the Lock bits the entire Flash can be read during the operation.
Bit 76543210
R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1
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26.8.8 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
that the bit is cleare d before writing to the SPMCSR Register.
26.8.9 Reading the Fuse and Lock Bits from Software
It is possib le to read bo th the Fuse and Loc k bits from so ftware. To read t he Lock bits, lo ad the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN
bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read th e Fuse Low byte, load the Z-pointer with 0 x0000 and set the BLBSET
and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles aft er the
BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. Refer to Table 27-5 on page 298 for a
detailed description and mapping of the Fuse Low byte.
Similarly, when read ing the Fu se High byte, load 0 x000 3 in t he Z-p ointer . When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SP MCSR,
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Refer to Table 27-4 on page 298 for detailed description and mapping of the Fuse High byte.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.
Refer to Table 27-3 on page 297 for detailed description and mapping of the Extended Fuse
byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
Bit 76543210
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1
Bit 76543210
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Bit 76543210
Rd – – – – EFB3 EFB2 EFB1 EFB0
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26.8.10 Preventi n g Fl as h Cor ru pt io n
During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and th e same design solutions should be applied.
A Flash program co rr up tion can be cau sed b y two situ a tions when th e voltag e is too low. F irst , a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these de sign recommendations (one is
sufficient):
1. If there is no need f or a Boot Loader update in the system, progra m the Boot Loader Lock
bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (lo w) during periods of insufficient power supply voltage.
This can be done b y e nab ling the int ernal Brown-out Detecto r (BOD) if the op era ting volt-
age matches the de tection le v el. If not, an e xternal low VCC rese t protection circuit can be
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mod e during periods of low VCC. This will pre-
vent the CPU from attempting to decod e and execute instructions, eff ectively protecting
the SPMCSR Register and thus the Flash from unintentional writes .
26.8.11 Programming Time for Flas h when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 26-5 shows the typical pro-
gramming time for Flash accesses fr om the CPU.
Table 26-5. SPM Programming Time
Symbol Min Programming Time Max Programming Time
Flash write (P age Erase, Page Write, and
write Lock bits by SPM) 3.7 ms 4.5 ms
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26.8.12 Boot Loader: Simple Assembly Code Example
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcrval, (1<<PGERS) | (1<<SPMEN)
call Do_spm
; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
; transfer data from RAM to Flash page buffer
ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
Wrloop:
ld r0, Y+
ld r1, Y+
ldi spmcrval, (1<<SPMEN)
call Do_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256
brne Wrloop
; execute Page Write
subi ZL, low(PAGESIZEB) ;restore pointer
sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256
ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)
call Do_spm
; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
; read back and check, optional
ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
subi YL, low(PAGESIZEB) ;restore pointer
sbci YH, high(PAGESIZEB)
Rdloop:
lpm r0, Z+
ld r1, Y+
cpse r0, r1
jmp Error
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sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256
brne Rdloop
; return to RWW section
; verify that RWW section is safe to read
Return:
in temp1, SPMCSR
sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet
ret
; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
rjmp Return
Do_spm:
; check for previous SPM complete
Wait_spm:
in temp1, SPMCSR
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEWE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret
26.8.13 ATmega169P Boot Loader Parameters
In Ta ble 26-6 through Table 26-8 on page 293, the parameters used in the description of the
Self-Programming are given.
Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 283.
Table 26-6. Boot Size Configuration(1)
BOOTSZ1
BOOTSZ0
Boot Size
Pages
Application Flash
Section
Boot Loader
Flash
Section
End
Application
Section
Boot Reset
Address
(Start Boot
Loader
Section)
11
128
words 2 0x0000 - 0x1F7F 0x1F80 - 0x1FFF 0x1F7F 0x1F80
10
256
words 4 0x0000 - 0x1EFF 0x1F00 - 0x1FFF 0x1EFF 0x1F00
01
512
words 8 0x0000 - 0x1DFF 0x1E00 - 0x1FFF 0x1DFF 0x1E00
00
1024
words 16 0x0000 - 0x1BFF 0x1C00 - 0x1FFF 0x1BFF 0x1C00
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Note: 1. F or details about these two section, see ”NRWW – No Read-While-Write Section” on page
281 and ”RWW – Read-W hile-Write Section” on page 281.
Note: 1. Z15:Z14: always ignored
Z0: should be zero for all SPM commands, byte select for the LPM instru ction.
See ”Addressing the Flash During Self-Programming” on page 286 for details about the use of
Z-pointer during Self-Programming.
Table 26-7. Read-While-Write Limit(1)
Section Pages Address
Read-While-Wr ite section (RWW) 112 0x0000 - 0x1BFF
No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF
Table 26-8. Explanation of different variables used in Figure 26-3 on page 286 and the map-
ping to the Z-pointer(1)
Variable Corresponding
Z-value Description
PCMSB 12 Most significant bit in the Program Counter. (The
Program Counter is 13 bits PC[12:0])
PAGEMSB 5 Most significant bit which is used to address the words
within one page (64 words in a page requires six bits PC
[5:0]).
ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB. Because Z0
is not used, the ZPCMSB equals PCMSB + 1.
ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB. Because
Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1.
PCPAGE PC[12:6] Z13:Z7 Progr am Counter page address: P age select, f or Page
Erase and Page Write
PCWORD PC[5:0] Z6:Z1 Program Counter word address: Word select, for filling
temporar y buffer (must be zero during Page Write
operation)
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26.9 Register Description
26.9.1 SPMCSR – Store Program Memory Control and Status Register
The Store Progr am Memory Contro l and Status Regist er contains the co ntrol bits nee ded to con-
trol the Boot Load e r oper at i on s.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Eras e or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega169P and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while
the Flash is busy with a Page Erase or a Pa ge Write (SPMEN is set). If the RWWSRE bit is writ-
ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will
be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is writt en to one at the same t ime as SPMEN, t he next SPM instru ctio n within f our clock
cycles sets Boot Lock bits and genera l Lock bits, accordin g to the data in R0. The dat a in R1 and
the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon
completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg-
ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See ”Reading the Fuse and Lock Bits from Software” on page 289 for
details.
Bit 7 654 3210
0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 2 – PGWRT: Page Write
If this bit is writt en to one at the same t ime as SPMEN, t he next SPM instru ctio n within f our clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is
addressed.
• Bit 1 – PGERS: Page Erase
If this bit is writt en to one at the same t ime as SPMEN, t he next SPM instru ctio n within f our clock
cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSE T, PGWRT’ or PGERS, the followi ng SPM instruction will have a spe-
cial meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruct ion is executed with in fo ur clo ck cycles. Durin g Page Era se and Pa ge Wr ite,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
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27. Memory Programming
27.1 Program And Data Memory Lock Bits
The ATmega169P provides six Lock bits which can be left unprogrammed (“1”) or can be pro-
grammed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be
erased to “1” with the Chip Erase command.
Note: 1. “1” means unprogrammed, “0” means programmed.
Table 27-1. Lock Bit Byte(1)
Lock Bit Byte Bit No Description Default Value
7 – 1 (unprogrammed)
6 – 1 (unprogrammed)
BLB12 5 Boot Lock bit 1 (unprogrammed)
BLB11 4 Boot Lock bit 1 (unprogrammed)
BLB02 3 Boot Lock bit 1 (unprogrammed)
BLB01 2 Boot Lock bit 1 (unprogrammed)
LB2 1 Lock bit 1 (unprogrammed)
LB1 0 Lock bit 1 (unprogrammed)
Table 27-2. Lock Bit Protection Modes(1)(2)
Memory Lock Bits Protection Type
LB Mode LB2 LB1
1 1 1 No memory lock features enabled.
210
Further programming of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.(1)
300
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Boot
Lock bits and Fuse bits are locked in both Serial and Parallel
Programming mode.(1)
BLB0 Mode BLB02 BLB01
111
No restrictions for SPM or LPM accessing the Application
section.
2 1 0 SPM is not all owed to write to the Application section.
300
SPM is not allowed to write to the Application section , and LPM
executing from the Boot Loader section is not allowed to read
from the Application section. If Interrupt Vectors are placed in
the Boot Loader section, interrupts are disabled while executing
from the Application section.
401
LPM executing from the Boot Loader section is not allowed to
read from the Application section. If Interrupt Vectors are placed
in the Boot Loader section, interrupts are disabled while
executing from the Application section.
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Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed.
27.2 Fuse Bits
The ATmega169P has three Fuse bytes. Table 27-3 to Table 27-5 on page 298 describe briefly
the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the
fuses are read as logical zero, “0”, if they are programmed.
Notes: 1. See Table 28-5 on page 334 for BODLEVEL Fuse decoding.
2. Port G, PG5 is input only. Pull-up is always on. See ”Alternate Functions of Port G” on page
85.
BLB1 Mode BLB12 BLB11
111
No restrictions for SPM or LPM accessing the Boot Loader
section.
2 1 0 SPM is not all owed to wri te to the Boot Loader section.
300
SPM is not allowed to write to the Boot Loader section, and LPM
execu ting from the Application section is not allowed to read
from the Boot Loader section. If Interr upt Vectors are pla ced in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
401
LPM executing from the Application section is not allowed to
read from the Boot Loader section. If Interrupt Vectors are
placed in the Application section, inte rrupts are disabled while
execu ting from the Boot Loader section.
Table 27-2. Lock Bit Protection Modes(1)(2) (Continued)
Memory Lock Bits Protection Type
Table 27-3. Extended Fuse Byte
Fuse Low Byte Bit No Description Default Value
–7– 1
–6– 1
–5– 1
–4– 1
BODLEVEL2(1) 3 Brown-out Detector tr igger level 1 (unprogrammed)
BODLEVEL1(1) 2 Brown-out Detector tr igger level 1 (unprogrammed)
BODLEVEL0(1) 1 Brown-out Detector tr igger level 1 (unprogrammed)
RSTDISBL(2) 0 External Reset Disable 1 (unprogrammed)
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Note: 1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOO TSZ1..0 results in maximum Boot Siz e . See Table 26-6 on page 292
for details.
3. See ”WDTCR – Watchdog Timer Control Register” on page 54 for details.
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
and JTAGEN Fuse. A progra mmed OCDEN Fuse enables some parts of the clock system to
be running in all sle ep modes. This may increase the power consumption.
5. If the JTAG interf ace is left unconnected, the JTAGEN fuse should if po ssib le be disab led . This
to avoid static current at the TDO pin in the JTAG interface.
.
Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 28-4 on page 333 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 8-9 on
page 35 for details.
3. The CKOUT Fuse allow the system clock to be output on PORTE7. See ”Clock Output Buffer”
on page 37 for details.
4. See ”System Clock Prescaler” on pag e 37 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Table 27-4. Fuse High Byte
Fuse High Byte Bit No Description Default Value
OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled)
JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled)
SPIEN(1) 5Enable Serial Program and Data
Downloading 0 (programmed, SPI prog.
enabled)
WDTON(3) 4 Watchdog Timer always on 1 (unprogrammed)
EESAVE 3 EEPROM memory is preserved
through the Chip Erase 1 (unprogrammed, EEPROM not
preserved)
BOOTSZ1 2 Select Boot Size (see Table 26-6
on page 292 for details) 0 (progr ammed)(2)
BOOTSZ0 1 Select Boot Size (see Table 26-6
on page 292 for details) 0 (progr ammed)(2)
BOOTRST 0 Select Reset Vector 1 (unprogrammed)
Table 27-5. Fuse Low Byte
Fuse Low Byte Bit No Description Default Value
CKDIV8(4) 7 Divide clock by 8 0 (programmed)
CKOUT(3) 6 Clock output 1 (unprogrammed)
SUT1 5 Select start-up time 1 (unprogrammed)(1)
SUT0 4 Select start-up time 0 (programmed)(1)
CKSEL3 3 Select Clock source 0 (programmed)(2)
CKSEL2 2 Select Clock source 0 (programmed)(2)
CKSEL1 1 Select Clo ck source 1 (unprogrammed)(2)
CKSEL0 0 Select Clock source 0 (programmed)(2)
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27.2.1 Latching of Fuses
The fuse values are latched when the device enters programming mode and chang es of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.
27.3 Signature Bytes
All Atmel microcontrollers have a three- byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space. The signature bytes are given in Table 27-6.
27.4 Calibration Byte
The ATmega169P has a byte calibration value for the internal RC Oscillator. This byte resides in
the high byte of add ress 0x000 in the signature add ress space. During reset, th is byte is auto-
matically written into the OSCCAL Register to ensure correct frequency of the calibrated RC
Oscillator.
27.5 Page Size
27.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, M em ory Lock bits, an d Fuse bit s in the ATmega169P. Pulses are assumed to be
at least 250 ns unless otherwise noted.
27.6.1 Signal Names
In this section, some pins of the ATmega169P are referenced by signal names describing their
functionality du ring parallel programming, see Figure 27-1 on page 300 and Table 27-9 on page
300. Pins not described in Table 27-9 on page 300 are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 27-11 on page 301.
Table 27-6. Device and JTAG ID
Part
Signature Bytes Address JTAG
0x000 0x001 0x002 Part Number Manufacture ID
ATmega169P 0x1E 0x94 0x05 9405 0x1F
Table 27-7. No. of Words in a Page and No. of Pages in the Fl ash
Flash Size Page Size PCWORD No. of Pages PCPA GE PCMSB
8K words (16 Kbytes) 64 words PC[5:0] 128 PC[12:6] 12
Table 27-8. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB
512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
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When pulsing WR or OE, the com mand loaded determines the action executed. The different
Commands are shown in Table 27-12 on page 301.
Figure 27-1. Parallel Programming
Table 27-9. Pin Name Mapping
Signal Name
in Prog ramming Mode Pin Name I/O Function
RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for
new command.
OE PD2 I Output Enable (Active low).
WR PD3 I Write Pulse (Active low).
BS1 PD4 I Byte Select 1 (“0” selects low byte, “1” selects high
byte).
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
PAGEL PD7 I Program Memory and EEPROM data Page Load.
BS2 PA0 I Byte Select 2 (“0” selects low b yte, “1” selects 2’nd high
byte).
DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low).
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0 DAT
A
RESET
PD7
+12V
BS1
XA0
XA1
OE
R
DY/BSY
PAGEL
PA0
WR
BS2
AVCC
+5V
Table 27-10. Pin Values Used to Enter Programming Mode
Pin Symbol Value
PAGEL Prog_enable[3] 0
XA1 Prog_enable[2] 0
XA0 Prog_enable[1] 0
BS1 Prog_enable[0] 0
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Table 27-11. XA1 and XA0 Coding
XA1 XA0 Action when XTAL1 is Pulsed
00
Load Flash or EEPROM Address (High or low address byte determ ined by
BS1).
0 1 Load Data (High or Low data byte for Flash determined by BS1).
1 0 Load Command
1 1 No Action, Idle
Table 27-12. Command Byte Bit Coding
Command Byte Command Executed
1000 0000 Chip Erase
0100 0000 Write Fuse bits
0010 0000 Write Lock bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes and Calibration byte
0000 0100 Read Fuse and Lock bits
0000 0010 Read Flash
0000 0011 Read EEPROM
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27.7 Parallel Programming
27.7.1 Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 4.5V - 5.5V between VCC and GND.
2. Set RESET to “0” and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in Table 27-10 on page 300 to “0000” and wait at least
100 ns.
4. Apply 11.5V - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after
+12V has been applied to RESET, will cause the device to fail entering programming
mode.
5. Wait at least 50 µs before sending a new command.
27.7.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command need s only be loaded once when writing or reading mult iple memory locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming o r reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
27.7.3 Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bit s are
not reset until the program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is progr a mmed.
Load Command “Chip Erase”:
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This st arts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.
27.7.4 Pr ogramming the Flash
The Flash is organized in pages, see Table 27-7 on page 299. When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be pro-
grammed simultaneously. The following procedure describes how to program the entire Flash
memory:
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A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enables add ress loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low b yte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set D ATA = Data low byte (0x00 - 0xFF).
3. Give XTAL1 a positiv e pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte .
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give XTAL1 a positiv e pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte .
2. Giv e PAGEL a positive pulse . This lat ches t he data bytes. ( See F igur e 2 7- 3 on pa ge 304
for signal waveforms)
F. Repeat B through E unt il the entire buffer is filled or until all data within the page is loaded
While the lower bits in t he addre ss are mapped t o words within the pa ge, th e higher b its addr ess
the pages within the FLASH. This is illustrated in Figure 27-2 on page 304. Note that if less than
eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)
in the address low byte are used to address the page when performing a Page Write.
G. Load Address High byte
1. Set XA1, XA0 to “00”. This enables add ress loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page
1. Giv e WR a negative pulse. This starts progr amming of t he entire pa ge of data. RDY/BSY
goes low.
2. Wait until RDY/BSY goes high (See Figur e 27-3 on page 304 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
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J. End Page Programming
1. 1. Set XA1, XA0 to “10”. This en ables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This load s the command, an d the internal write signals are
reset.
Figure 27-2. Addressing the Flash Which is Organized in Pages(1)
Note: 1. PCPAGE and PCWORD are listed in Table 27-7 on page 299.
Figure 27-3. Programming the Flash Waveforms (1)
Note: 1. “XX” is don’t care. The letters refer to the programming description above.
PROGRAM MEMORY
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
INSTRUCTION WORD
PA G E PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PA G E
PCWORDPCPAGE
PCMSB PAGEMSB
PROGRAM
COUNTER
RDY/BSY
WR
OE
RESET +12V
PAGEL
BS2
0x10 ADDR. LOW ADDR. HIGH
DATA DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH
XA1
XA0
BS1
XTAL1
XX XX XX
ABCDEBCDEGH
F
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27.7.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 27-8 on page 299. When programming the
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
follows (refer to ”Programming the F lash” on page 302 for details on Com mand, Address and
Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. C: Load Data (0x00 - 0xFF).
5. E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS to “0”.
2. Give WR a negativ e pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. W ait until to RDY/BSY goes high bef ore p rog ramming the next page (See Figure 27-4 for
signal waveforms).
Figure 27-4. Programming the EEPROM Waveforms
27.7.6 Reading the Flash
The algorithm for reading the Flash m emory is as follows (refer to ”Programming the Flash” on
page 302 for details on Command and Address loading):
1. A: Load Command “0000 0010”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5. Set BS to “1”. The Flash word high byte can now be read at DATA.
6. Set OE to “1”.
RDY/BSY
WR
OE
RESET +12V
PAGEL
BS2
0x11 ADDR. HIGH
DATA ADDR. LOW DATA ADDR. LOW DATA XX
XA1
XA0
BS1
XTAL1
XX
AGBCEBC EL
K
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27.7.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash”
on page 302 for details on Command and Address loading):
1. A: Load Command “0000 0011”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5. Set OE to “1”.
27.7.8 Programming the Fuse Low Bits
The algorith m for progr amming th e Fuse Lo w bits is as follows (ref er to ” Programmin g the Flash”
on page 302 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wa it for RDY/BSY to go high.
27.7.9 Programming the Fuse High Bits
The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the
Flash” on page 302 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS1 to “1” and BS2 to “0”. This selects high fuse byte.
4. Give WR a negative pulse and wa it for RDY/BSY to go high.
5. Set BS1 to “0”. This selects low data byte.
27.7.10 Programming the Extended Fuse Bit s
The algorithm for programming the Extended Fuse bits is as follows (refer to ”Progr amming th e
Flash” on page 302 for details on Command and Data loading):
1. 1. A: Load Command “0100 0000”.
2. 2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended fuse byte.
4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. 5. Set BS2 to “0”. This selects low data byte.
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Figure 27-5. Programming the FUSES Waveforms
27.7.11 Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on
page 302 for details on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
(LB1 and LB2 is programmed), it is not po ssible to program the Boot Lock bits by any
External Programming mode.
3. Give WR a negative pulse and wa it for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
27.7.12 Reading the Fuse and Loc k Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash”
on page 302 for details on Command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be
read at DATA (“0” means programmed).
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be
read at DATA (“0” means programmed).
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now
be read at DATA (“0” means programmed).
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The statu s of the Lock bits can now be read at
DATA (“0” means programmed).
6. Set OE to “1”.
RDY/BSY
WR
OE
RESET +12V
PAGEL
0x40
DATA
DATA XX
XA1
XA0
BS1
XTAL1
AC
0x40 DATA XX
AC
Write Fuse Low byte Write Fuse high byte
0x40 DATA XX
AC
Write Extended Fuse byte
BS2
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Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
27.7.13 Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to ”Programming t he F l as h” o n
page 302 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS to “0”. The selected Signatur e byte can now be read at DATA.
4. Set OE to “1”.
27.7.14 Reading the Calibration Byte
The algorithm for reading the Calibration byte is as follows (refer to ”Programming th e F lash” on
page 302 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibrati on byte can now be read at DATA.
4. Set OE to “1”.
27.7.15 Parallel Programming Characteristics
Figure 27-7. Parallel Programming Timing, Including some General Timing Requirements
Lock Bits 0
1
BS2
Fuse High Byte
0
1
BS1
DATA
Fuse Low Byte 0
1
BS2
Extended Fuse Byte
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
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Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
Note: 1. The timing requirements shown in Figure 27-7 on page 308 (that is, tDVXH, tXHXL, and tXLDX)
also apply to loading operation.
Figure 27-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
Note: 1. The timing requirements shown in Figure 27-7 on page 308 (that is, tDVXH, tXHXL, and tXLDX)
also apply to reading operation.
Table 27-13. Parallel Programming Characteristics, VCC = 5V ±10%
Symbol Parameter Min Typ Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enab l e Curr en t 250 μA
XTAL1
PAGEL
t
PLXH
XLXH
tt
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE) LOAD DATA
(LOW BYTE) LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE) READ DATA
(LOW BYTE) READ DATA
(HIGH BYTE) LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
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Notes: 1. tWLRH is valid for the Write Flash, Wr ite EEPROM, Wr ite Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
27.8 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The se rial interface co nsists of pins SCK, MOSI (i nput) and MI SO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 27-14 on page 311, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
tDVXH Data and Control Val id before XTAL1 High 67
ns
tXLXH XTAL1 Low to XTAL1 High 200
tXHXL XTAL1 Pulse Width High 150
tXLDX Data and Control Hold after XTAL1 Low 67
tXLWL XTAL1 Low to WR Low 0
tXLPH XTAL1 Low to PAGEL high 0
tPLXH PAGEL low to XTAL1 high 150
tBVPH BS1 Valid before PA G E L H ig h 67
tPHPL PA GEL Pulse Width High 150
tPLBX BS1 Hold after PAGEL Lo w 67
tWLBX BS2/1 Hold after WR Low 67
tPLWL PAGEL Low to WR Low 67
tBVWL BS1 Valid to WR Low 67
tWLWH WR Pulse Width Low 150
tWLRL WR Low to RDY/BSY Low 0 1 μs
tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms
tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9
tXLOL XTAL1 Low to OE Low 0
ns
tBVDV BS1 Valid to D ATA valid 0 250
tOLDV OE Low to DATA Valid 250
tOHDZ OE High to DATA Tri-stated 250
Table 27-13. Parallel Programming Characteristics, VCC = 5V ±10%
Symbol Parameter Min Typ Max Units
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27.8.1 Serial Programming Pin Mapping
Figure 27-10. Serial Programming and Verify(1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8V - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
27.8.2 Serial Programming Algorithm
When writing serial data to the ATmega169P, data is clocked on the rising edge of SCK.
When reading data from the ATmega169P, data is clocked on the falling edge of SCK. See Fig-
ure 27-11 on page 313 for timing details.
To program and verify the ATmega169P in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in Table 27-16 on page 314):
1. Power-up sequence:
Apply power between VCC and GN D while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarant ee that SCK is held low d uring power-up. In this
Table 27-14. Pin Mappin g Serial Programming
Symbol Pins I/O Description
MOSI PB2 I Serial Data in
MISO PB3 O Serial Data out
SCK PB1 I Serial Clock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
+1.8V - 5.5V
AVCC
+1.8V - 5.5V
(2)
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case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whethe r the echo is correct or not, all four
bytes of the instruction must be transmitte d. If the 0x53 did not echo bac k, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 27-7 on
page 299. The memory page is loaded one byte at a time by supplying the 6 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 7 MSB of the address . If polling (RDY/BSY) is
not used, the user must wait at least tWD_FLASH before issuing the ne xt page. (See Table
27-15.) Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. A: The EEPROM array is programmed one by te at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY) is not used, the
user must wait at least tWD_EEPROM before issuing the next byte (See Table 27-15). In a
chip erased device, no 0xFF s in the da ta file(s ) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one b yte at a time b y supplying the 2 LSB of th e address and data tog ether with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using
EEPROM page access only b yte locations loaded with the Load EEPROM Memory P age
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is
not used, the user m ust wait at least tWD_EEPROM before issuing the next page (See Table
27-15). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6. Any memo ry location can be v erified b y using the Read instruction which returns the con-
tent at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off
Table 27-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FUSE 4.5 ms
tWD_FLASH 4.5 ms
tWD_EEPROM 3.6 ms
tWD_ERASE 9.0 ms
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Figure 27-11. Serial Programming Waveforms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT
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27.8.3 Serial Programming Instruction set
Table 27-16 and Figure 27-12 on page 315 describes the Instruction set.
Notes: 1. Not all instructions are applicable for all parts
2. a = address
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’).
5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
6. Instructions accessing program memory use a word address. This address may be random within the page range.
7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Table 27-16. Serial Prog ramming Instruction Set
Instruction/Operation
Instruction Format
Byte 1 Byte 2 Byte 3 Byte 4
Programming Enab le $AC $53 $00 $00
Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00
Poll RDY/BSY $F0 $00 $00 data byte out
Load Instructions
Load Extended Address byte(1) $4D $00 Extended adr $00
Load Program Memory Page, High byte $48 $00 adr LSB high data byte in
Load Program Memor y Page, Low byte $40 $00 adr LSB low data byte in
Load EEPROM Memory Page (page access) $C1 $00 0000 00aa data byte in
Read Instructions
Read Program Memory, High byte $28 adr MSB adr LSB high data byte out
Read Program Memory, Low b yte $20 adr MSB adr LSB low data byte out
Read EEPROM Memory $A0 0000 00aa aaaa aaaa data byte out
Read Lock bits $58 $00 $00 data byte out
Read Signature Byte $30 $00 0000 00aa data byte out
Read Fuse bits $50 $00 $00 data byte out
Read Fuse High bits $58 $08 $00 data byte out
Read Extended Fuse Bits $50 $08 $00 data byte out
Read Calibration Byte $38 $00 $00 data byte out
Write Instructions(6)
Write Progra m Me mo ry Page $4C adr MSB adr LSB $00
Write EEPROM Memory $C0 0000 00aa aaaa aaaa data byte in
Write EEPROM Memory Page (page access) $C2 0000 00aa aaaa aa00 $00
Write Lock bits $AC $E0 $00 data byte in
Write Fuse bits $AC $A0 $00 data byte in
Write Fuse High bits $AC $A8 $00 data byte in
Write Extended Fuse Bits $AC $A4 $00 data byte in
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Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 27-12.
Figure 27-12. Serial Programming Instruction example
27.8.4 SPI Se ri al Programming Chara ct e ri st ic s
For characteristics of the SPI module, see ”SPI Timing Characteristics” on page 334.
Byte 1 Byte 2 Byte 3 Byte 4
Adr MSB
Adr LSB
Bit 15 B 0
Serial Programming Instruction
Program Memory/
EEPROM Memory
Page 0
Page 1
Page 2
Page N-1
Page Buffer
Write Program Memory Page/
Write EEPROM Memory Page
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1 Byte 2 Byte 3 Byte 4
Bit 15 B 0
Adr MSB
Adr LSB
Page Offset
Page Number
Adr
dr M
r MS
SB
A
A
Adr
dr LS
LSB
SB
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27.9 Programming via the JTAG Interface
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of t he reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shippe d with the fu se p rogramme d. In addit ion, the JTD bit in MCUCSR must be cleare d.
Alternatively, if the JTD bit is set, the external reset can be fo rced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-
tem Programming via the JTAG interface. Note that this technique can not be used when using
the JTAG pins for Boundary-scan or On-chip Debug. In thes e cases the JTAG pins must be ded-
icated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum fre-
quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input
into a sufficiently low freq ue n cy.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
27.9.1 Programming Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Re gister is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in Figure 27-13 on page 317.
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Figure 27-13. State Machine Sequence for Changing the Instruction Word
27.9.2 AVR_RESET (0xC)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking
the device out from the Reset mode. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the reset will be active as long as there
is a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
27.9.3 PROG_ENABLE (0x4)
The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-
bit Programming Enable Register is selected as Data Register. The active states are the
following:
• Shift-DR: The programming enable signature is shifted into the Data Register.
• Update-DR: The programming enable signature is compared to the correct value, and
Programming mode is entered if the signature is valid.
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
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27.9.4 PROG_COMMANDS (0x5)
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as Data Register. The active
states are the fo llowin g :
• Capture-DR: The result of the previous command is loaded into the Data Register.
• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous
command and sh iftin g in th e new command.
• Update-DR: The programming command is applied to the Flash inputs.
• Run-Test/Idle: One clock cycle is generated, e xecuting the applied command (not always
required, see Table 27-17 on page 321).
27.9.5 PROG_PAGELOAD (0x6)
The AVR specific public JTAG instruct ion to direct ly load the Flash data pag e via the JTAG port.
An 8-bit Flash Data Byte Register is select ed as the Data Register. This is physically the 8 LSBs
of the Prog ramming Command Register. The active states are the following:
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
• Update-DR: The cont ent of t he Flash Data Byt e Register is co pied into a t empor ary register. A
write sequence is initiated that withi n 11 TCK cycles loads the content of the temporary
register into the Flash page buffer. The AVR automatically alternates between writing the low
and the high byte for each new Update-DR state, starting with the low byte for the first Update-
DR encountered after entering the PROG_PAGELOAD command. The Program Counter is
pre-incremented before writing the low byte, except for the first written byte. This ensures that
the first data is written to the address set up by PROG_COMMANDS , and loading the last
location in the page buffer does not make the program counter increment into the next page.
27.9.6 PROG_PAGEREAD (0x7)
The AVR specific public JTAG instruction to directly capture the Flash cont ent via the JTAG port.
An 8-bit Flash Data Byte Register is select ed as the Data Register. This is physically the 8 LSBs
of the Prog ramming Command Register. The active states are the following:
• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte
Register. The AVR automatically alternates betw een reading the lo w and the high b yte f or each
new Capture-DR state, starting with the low byte for the fir st Capture-DR encountered after
entering the PROG_PAGEREAD command. The Program Counter is post-incremented after
reading each high b yte , including the first rea d byte . This ensure s that the first data is captured
from the first address set u p b y PR OG_COMMANDS , and read ing the last location in the page
makes the program count er increment into the next page.
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
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27.9.7 Data Registers
The Data Registers are selected by the JTAG instruction registers described in section ”Pro-
gramming Specific JTAG Instructions” on page 316. The Data Registers relevant for
programming operations are:
• Reset Register
• Programming Enable Register
• Programming Command Register
• Flash Data Byte Register
27.9.8 Reset Register
The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset
as long as there is a high value present in the Reset Register. Depending on the Fuse settings
for the clock options, the part will remain reset for a Reset Time-out period (refer to ”Clock
Sources” on page 31) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 25-2 on page 261.
27.9.9 Programming Enable Register
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-
tents of the register is equal to the programming enable signature, programming via the JTAG
port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when
leaving Programming mode.
Figure 27-14. Programming Enable Register
27.9.10 Programming Command Register
The Programming Command Register is a 15-bit register. This register is used to serially shift in
programming co mmands, and to serially shift out the result of the pre vious command, if any. The
JTAG Programming Instruction Set is shown in Table 27-17 on pa ge 321. The state sequence
when shifting in the programming commands is illustrated in Figure 27-16 o n page 324.
TDI
TDO
D
A
T
A
=DQ
ClockDR & PROG_ENABLE
Programming Enable
0xA370
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Figure 27-15. Programming Command Register
TDI
TDO
S
T
R
O
B
E
S
A
D
D
R
E
S
S
/
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
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Table 27-17. JTAG Programming Instruction Set
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Instruction TDI Sequence TDO Sequence Notes
1a. Chip Erase
0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (2)
2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx
2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)
2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx
2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx
2f. Latch Data 0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx (1)
2g. Write Flash Page
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
2h. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)
3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx
3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)
3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
3d. Read Data Low and High Byte 0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo Low byte
High byte
4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx
4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)
4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx
4e. Latch Data 0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx (1)
4f. Write EEPROM Page
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2)
5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx
5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)
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5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
5d. Read Data Byte 0110011_bbbbbbbb
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx
6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)
6c. Write Fuse Extended Byte
0111011_00000000
0111001_00000000
0111011_00000000
0111011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
6d. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)
6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)
6f. Write Fuse High Byte
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
6g. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)
6h. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)
6i. Write Fuse Low Byte
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2)
7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx
7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)
7c. Write Lock Bits
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
7d. Poll for Lock Bit Write complete 0110011_000 00000 xxxxxox_xxxxxxxx (2)
8a. Enter Fuse/Lock Bit Read 0100011_0000010 0 xxxxxxx_xxxxxxxx
8b. Read Extended Fuse Byte(6) 0111010_00000000
0111011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
8c. Read Fuse High Byte(7) 0111110_00000000
0111111_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
8d. Read Fuse Low Byte(8) 0110010_00000000
0110011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
8e. Read Lock Bits(9) 0110110_00000000
0110111_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_xxoooooo (5)
Table 27-17. JTAG Programming Instruction Set
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Instruction TDI Sequence TDO Sequence Notes
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Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is
nor mally the case).
2. Repeat until o = “1”.
3. Set bits to “0” to program the corresponding Fuse, “1” to unprogramme the Fuse.
4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.
5. “0” = programmed, “1” = unprogrammed.
6. The bit mapping for Fuses Extended byte is listed in Table 27-3 on page 297.
7. The bit mapping for Fuses High byte is listed in Table 27-4 on page 298.
8. The bit mapping for Fuses Low byte is listed in Table 27-5 on pag e 298.
9. The bit mapping for Lock bits byte is listed in Table 27-1 on page 296 .
10.Address bits exceeding PCMSB and EEAMSB (Table 27-7 on page 2 99 and Table 27-8 on page 299).
11.All TDI and TDO sequences are represented by binary digits (0b...).
8f . Read Fuses and Lock Bits
0111010_00000000
0111110_00000000
0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
(5)
Fuse Ext. byte
Fuse High byte
Fuse Low byte
Lock bits
9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx
9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
9c. Read Signature Byte 0110010_00000000
0110011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx
10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
10c. Read Calibration Byte 0110110_00000000
0110111_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
11a. Load No Operation Command 0100011_00000000
0110011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
Table 27-17. JTAG Programming Instruction Set
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Instruction TDI Sequence TDO Sequence Notes
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Figure 27-16. State Machin e Sequence for Changing/Reading the Data Word
27.9.11 Flash Data Byte Register
The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer
before executing Page Write, or to read out/verify the content of the Flash. A state machine sets
up the control signals to the Flash and senses the strobe signals from the Flash, thus only the
data words need to be shifted in/out.
The Flash Data Byt e Regist er actually con sists of the 8-bit scan chain and a 8-bit tempor ary reg-
ister. During page load , the Update-DR state copies the conte nt of the scan chain over to the
temporary register and initiates a write sequence that within 11 TCK cycles loads the content of
the temporary register into the Flash page buffer. The AVR automatically alternates between
writing the low and the high byte for e ach new Update -DR state, startin g with the low b yte f or the
first Update-DR encountered after entering the PROG_PAGELOAD command. The Program
Counter is pre-increment ed before writing the low byte, except for the first writ ten byte. This
ensures that the first data is written to the address set up by PROG_COMMANDS, and loading
the last location in the page buffer does not make the Program Counter increment into the next
page.
During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte
Register during the Capture-DR state. The AVR automatically alternates between reading the
low and the high byte f or each n ew Captur e- DR stat e, sta rt ing with t he low byt e for th e fi rst Ca p-
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
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ture-DR encounte red af t er en te rin g the PROG _PAGEREAD co mmand. Th e Progr am Co unt er is
post-incremented after reading each high byte, including the first read byte. This ensures that
the first data is captured from the first address set up by PROG_COMMANDS, and reading the
last location in the page makes the program counter increment into the next page.
Figure 27-17. Flash Data Byte Register
The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal
operation in which eight bits are shifted for each Flash byte, the clock cycles needed to naviga te
through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-
ter with sufficient number of clock pulses to complete its operation transparently for the user.
However, if too few bits are shifted between each Update-DR state during page load, the TAP
controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at
least 11 TCK cycles between each Update-DR state.
27.9.12 Programming Algorithm
All references below of type “1a”, “1b”, and so on, refer to Table 27-17 on page 321.
27.9.13 Entering Programming Mode
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Re gister.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-
ming Enable Register.
27.9.14 Leaving Programming Mode
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-
ming Enable Register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Re gister.
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
Machine
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27.9.15 Performing Chip Erase
1. Enter JTAG instruction PROG_COMMANDS.
2. Start Chip Erase using programming instruction 1a.
3. Poll for Chip Erase complete using progr amming instruction 1b , or w ait for tWLRH_CE (ref er
to Table 27-13 on page 309).
27.9.16 Programming the Flash
Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase”
on page 326.
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash write using programming instruction 2a.
3. Load address High byte using programming instruction 2b.
4. Load address Low byte usin g programming instruction 2c.
5. Load data using programming instructions 2d, 2e and 2f.
6. Repeat steps 4 and 5 for all instruction words in the page.
7. Write the page using programming instruction 2g.
8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to
Table 27-13 on page 309).
9. Repeat steps 3 to 7 until all data have been programmed.
A more efficient data tra nsfer can be achieved using the PROG_PAGELOAD instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash write using programming instruction 2a.
3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to
Table 27-7 on page 299) is used to address within one page and must be written as 0.
4. Enter JTAG instruction PR OG_PAGELOAD.
5. Load the ent ire page by shifting in all instruction words in the page byte-by-byte, starting
with the LSB of the first instruction in the page and ending with the MSB of the last
instruction in the page. Use Update-DR to copy the contents of the Flash Da ta Byte Re g-
ister into the Flash page location and to auto-incre ment the Program Counter before
each new word.
6. Enter JTAG instruction PROG_COMMANDS.
7. Write the page using programming instruction 2g.
8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to
Table 27-13 on page 309).
9. Repeat steps 3 to 8 until all data have been programmed.
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27.9.17 Reading the Flash
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash read using programming instruction 3a.
3. Load address using programming instructions 3b and 3c.
4. Read data using programming instruction 3d.
5. Repeat steps 3 and 4 until all data have been read.
A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash read using programming instruction 3a.
3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to
Table 27-7 on page 299) is used to address within one page and must be written as 0.
4. Enter JTAG instruction PROG_PAGEREAD.
5. Read the entire page (or Flash) b y shifting out all instruction w ords in the page (or Flash ),
starting with the LSB of the first instruction in the page (Flash) and ending with the MSB
of the last instruction in the page (Flash). The Capture-DR state both captures the data
from the Flash, and also auto-increments the program counter after each word is read.
Note that Capt ure-DR comes before the shift-DR state. Hence, the first byte which is
shifted out contai ns valid data.
6. Enter JTAG instruction PROG_COMMANDS.
7. Repeat steps 3 to 6 until all data have been read.
27.9.18 Programming the EEPROM
Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip
Erase” on page 326.
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable EEPROM write using programming instr uction 4a.
3. Load address High byte using programming instruction 4b.
4. Load address Low byte usin g programming instruction 4c.
5. Load data usin g pr ogramming ins tructions 4d an d 4e.
6. Repeat steps 4 and 5 for all data byte s in the page.
7. Write the data using prog ramming instruction 4f.
8. Poll for EEPROM write complete using programming instruction 4g, or w ait for tWLRH
(refer to Table 27-13 on page 309).
9. Repeat steps 3 to 8 until all data have been programmed.
Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM.
27.9.19 Reading the EEPROM
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable EEPROM read using programming instru ction 5a.
3. Load address using programming instructions 5b and 5c.
4. Read data using programming instruction 5d.
5. Repeat steps 3 and 4 until all data have been read.
Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM.
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27.9.20 Programming the Fuses
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Fuse write using programming instruction 6a.
3. Load data high byte using prog ramming instructions 6b . A bit v alue of “0” will program the
corresponding fuse, a “1” will unprogram the fuse.
4. Write Fuse High byte using programming inst ruction 6c.
5. Poll for Fuse write complete usi ng programming instruction 6d, or wait for tWLRH (refer to
Table 27-13 on page 309).
6. Load data low b yte using programming instructions 6e. A “0” will program the fuse, a “1”
will unprogram the fuse.
7. Write Fuse low b yte using programming instruction 6f.
8. Poll for Fuse write complete usi ng programming instruction 6g, or wait for tWLRH (refer to
Table 27-13 on page 309).
27.9.21 Programming the Lock Bits
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Lock bit write using programming instructio n 7a .
3. Load data using programming instr u ctions 7b. A bit value of “0” will program the corre-
sponding lock bit, a “1” will leave the lock bit unchanged.
4. Write Lock bits using programming instruction 7c.
5. Poll for Lock bit write complete using programming instruc tio n 7d , or wait for tWLRH (refer
to Table 27-13 on page 309).
27.9.22 Reading the Fuses and Lock Bits
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Fuse/Lock bit read using progr amming instruction 8a.
3. To read all Fuses and Lock bits, use prog ramming instruction 8e .
To only read Fuse High byte, use programming instruction 8b.
To only read Fu se Low byte, use programming instru ctio n 8c.
To only read Lock bits, use programming instruction 8d.
27.9.23 Reading the Signature Bytes
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Signature byte read using programming instructio n 9a .
3. Load add re ss 0x 00 usin g pr ogrammin g ins tructio n 9b.
4. Read first signature byte using programm ing instruction 9c.
5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third
signature bytes, respectively.
27.9.24 Reading the Calibration Byte
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Calibration b yte read using programming instruction 10a.
3. Load add re ss 0x 00 usin g pr ogrammin g ins tructio n 10 b.
4. Read the calibration byt e using programming instruction 10c.
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28. Electrical Characteristics
28.1 Absolute Maximum Ratings*
28.2 DC Characteristics
Operating Te mperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin............................................... 40.0 mA
DC Current VCC and GND Pins................................ 400.0 mA
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless oth erwise noted)
Symbol Parameter Condition Min. Typ. Max. Units
VIL Input Low Voltage except
XTAL1 and RESET pins VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V -0.5
-0.5 0.2VCC(1)
0.3VCC(1)
V
VIH Input High V oltage e xcept
XTAL1 and RESET pins VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V 0.7VCC(2)
0.6VCC(2) VCC + 0.5
VCC + 0.5
VIL1 Input Low Voltage
XTAL1 pins VCC = 1.8V - 5.5V -0.5 0.1VCC(1)
VIH1 Input High Voltage,
XTAL1 pin VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V 0.8VCC(2)
0.7VCC(2) VCC + 0.5
VCC + 0.5
VIL2 Input Low Voltage,
RESET pins VCC = 1.8V - 5.5V -0.5 0.1VCC(1)
VIH2 Input High Voltage,
RESET pins VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5
VOL Output Low Voltage (3),
Port A, C, D, E, F, G IOL = 10 mA, VCC = 5V
IOL = 5 mA, VCC = 3V 0.7
0.5
VOL1 Output Low Voltage (3),
Port B IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V 0.7
0.5
VOH Output High Voltage(4),
Port A, C, D, E, F, G IOH = -10 mA, VCC = 5V
IOH = -5 mA, VCC = 3V 4.2
2.3
VOH1 Output High Voltage(4),
Port B IOH = -20 mA, VCC = 5V
IOH = -10 mA, VCC = 3V 4.2
2.3
IIL Input Leakage
Current I/O Pin VCC = 5.5V, pin low
(absolute value) 1µA
IIH Input Leakage
Current I/O Pin VCC = 5.5V, pin high
(absolute value) 1
RRST Reset Pull-up Resistor 30 60 kΩ
RPU I/O Pin Pull-up Resistor 20 50
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Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low.
2. “Min” means the lowest value where the pin is guaranteed to be read as high.
3. Although each I/O port can sink more th an the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V for Port B and 10 mA
at VCC = 5V, 5 mA at VCC = 3V for all other ports) under steady state conditions (non-transient), the following must be
observed:
TQFP and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports A0 - A7, C4 - C7, G2 should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100 mA.
4] The sum of all IOL, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100 mA.
5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA.
If IOL e xceeds the test condition, V OL may ex ceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test con ditions (20 mA at VCC = 5V, 10 mA at VCC = 3V for Port B and 10
mA at VCC = 5V, 5 mA at VCC = 3V for all other ports) under steady state conditions (non-transient), the following must be
observed:
TQFP and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports A0 - A7, C4 - C7, G2 should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100 mA.
4] The sum of all IOH, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100 mA.
5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. All bits set in the ”Power Reduction Register” on page 42.
6. Typical values at 25°C. Maximum values are characterized values and not test limits in producti on.
ICC
Power Supply Current(5)
Active 1 MHz, VCC = 2V 0.35 0 .44
mA
Active 4 MHz, VCC = 3V 2.3 2.5
Active 8 MHz, VCC = 5V 8.4 9.5
Idle 1 MHz, VCC = 2V 0.1 0.2
Idle 4 MHz, VCC = 3V 0,7 0.8
Idle 8 MHz, VCC = 5V 3.0 3.3
Power-save mode(6)
32 kHz TOSC enabled,
VCC = 1.8V 0.55 1.6
µA
32 kHz TOSC enabled,
VCC = 3V 0.8 2.6
Power-down mode(6) WDT enabled, VCC = 3V 6 10
WDT disabled, VCC = 3V 0.2 2
VACIO Analog Comparator
Input Offset Voltage VCC = 5V
Vin = VCC/2 <10 40 mV
IACLK Analog Comparator
Input Leakage Current VCC = 5V
Vin = VCC/2 -50 50 nA
tACPD Analog Comparator
Propagation Delay VCC = 2.7V
VCC = 4.0V 750
500 ns
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min. Typ. Max. Units
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28.3 Speed Grades
Maximum frequency is depending on VCC. As shown in Figure 28-1 and Figure 28-2 on page
332, the Maximum Frequency vs. VCC curve is linear be tween 1.8V < VCC < 4.5V. To calculate
the maximum frequency at a given voltage in this interval, use this equatio n:
To calculate required voltage for a given frequency, use this equation::
At 3 Volt, this gives:
Thus, when VCC = 3V, maximum frequency will be 9.33 MHz.
At 6 MHz this gives:
Thus, a maximum freque ncy of 6 MHz requires VCC = 2.25V.
Figure 28-1. Maximum Frequency vs. VCC, ATmega169PV
Table 28-1. Constants used to calculate maximum speed vs. VCC
Voltage and Frequency range a b Vx Fy
2.7 < VCC < 4.5 or 8 < Frq < 16 8/1.8 1.8/8 2.7 8
1.8 < VCC < 2.7 or 4 < Frq < 8 1.8 4
Frequency a V Vx–()•Fy+=
Voltage b F Fy–()•Vx+=
Frequency 8
1.8
--------32.7–()•8+9.33==
Voltage 1.8
8
--------64–()•1.8+2.25==
8 MHz
4 MHz
1.8V 2.7V 5.5V
Safe Operating Area
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Figure 28-2. Maximum Frequency vs. VCC, ATmega169P
28.4 Clock Characteristics
28.4.1 Calibrated Internal RC Oscillator Accuracy
Notes: 1. Voltage range for ATmega169PV.
2. Voltage range for ATmega169P.
28.4.2 External Clock Drive Waveforms
Figure 28-3. External Clock Drive Waveforms
1
6 MHz
8 MHz
2.7V 4.5V 5.5V
Safe Operating Area
Table 28-2. Calibration Accuracy of Internal RC Osc illator
Frequency VCC Temperature Calibration Accuracy
Factory Calibration 8.0 MHz 3V 25°C±10%
User Calibration 7.3 MHz - 8.1 MHz 1.8V - 5.5V(1)
2.7V - 5.5V(2) -40°C - 85°C±1%
V
IL1
V
IH1
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28.4.3 External Clock Drive
28.5 System and Reset Characteristics
Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
Table 28-3. External Clock Drive
Symbol Parameter
VCC = 1.8V - 5.5V VCC = 2.7V - 5.5V VCC = 4.5V - 5.5V
UnitsMin. Max. Min. Max. Min. Max.
1/tCLCL Oscillator
Frequency 0108016MHz
tCLCL Clock Period 1000 125 62.5
nstCHCX High Time 400 50 25
tCLCX Low Time 400 50 25
tCLCH Rise Time 2.0 1.6 0.5 μs
tCHCL Fall Time 2.0 1.6 0.5
ΔtCLCL
Change in period
from one clock
cycle to the next 222%
Table 28-4. Reset, Brown-out,and Internal Voltage Characteristics
Symbol Parameter Condition Min Typ Max Units
VPOT
Power-on Reset Threshold
Voltage (rising) TA = -40°C
to 85°C 0.7 1.0 1.4 V
Power-on Reset Threshold
Voltage (falling)(1) TA = -40°C
to 85°C 0.05 0.9 1.3
VPSR Power-on Reset Slope Rate 0.1 4.5 V/ms
VRST RESET Pin Threshold Voltage VCC = 3V 0.2VCC 0.9VCC V
tRST Minimum pulse width on RESET
Pin VCC = 3V 2.5 µs
VHYST Brown-out Detector Hysteresis 50 mV
tBOD Min Pulse Width on Brown-out
Reset 2µs
VBG Bandgap reference v oltage VCC = 2.7V,
TA=25°C 1.0 1.1 1.2 V
tBG Bandgap reference start-up time VCC = 2.7V,
TA=25°C 40 70 µs
IBG Bandgap reference current
consumption VCC = 2.7V,
TA=25°C 15 µA
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Note: 1. VBOT may be below nominal minimum operating voltage for some devices . For devices where
this is the case, the device is tested down to VCC = VBOT dur ing the production test. This guar-
antees that a Brown-Out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 110 for ATmega169V.
28.6 SPI Timing Characteristics
See Figure 28-4 on page 335 and Figure 28-5 on page 335 for details.
Table 28-5. BODLEVEL Fuse Coding(1)
BODLEVEL 2..0 Fuses Min VBOT Ty p VBOT Max VBOT Units
111 BOD Disabled
110 1.7 1.8 2.0
V101 2.5 2.7 2.9
100 4.1 4.3 4.5
011
Reserved
010
001
000
Table 28-6. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK per iod Master See Table 18-5 on
page 166
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall ti me Master 3.6
4 Setup Master 10
5Hold Master 10
6 Out to SCK Master 0.5 • tsck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS low to out Slave 15
10 SCK period Slave 4 • tck
11 SCK high/low(1) Slave 2 • tck
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
ns
14 Hold Slave tck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20 • tck
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Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
Figure 28-4. SPI Interface Timing Requirements (Master Mode)
Figure 28-5. SPI Interface Timing Requirements (Slave Mode)
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
61
22
345
8
7
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
336
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ATmega169P
28.7 ADC Characteristics – Preliminary Data
Table 28-7. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
Resolution Single Ended Conversion 10 Bits
Differential C onversion 8
Absolute accuracy
(Including INL, DNL,
quantization error, gain and
offset error)
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 22.5
LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz 4.5
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Noise Reduction Mode
2
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
Noise Reduction Mode
4.5
Integral Non-Linearity (INL) Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 0.5
Differential Non-Linearity (DNL) Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 0.25
Gain Error Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 2
Offset Error Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 2
Conversion Time Free Running Conversion 13 260 µs
Clock Fre quency Single Ended Conversion 50 1000 kHz
AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3
V
VREF Reference Voltage Single Ended Conversion 1.0 AVCC
Differential Conversion 1.0 AVCC - 0.5
VIN
Pin Input Voltage Single Ended Channels GND VREF
Differential Channels GND AVCC
Input Range Single Ended Channels GND VREF
Differential Channels(1) -0.85VREF VREF
Input Bandwidth Single Ended Channels 38.5 kHz
Differential Channels 4
337
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ATmega169P
Note: 1. Voltage difference between channels.
28.8 LCD Controller Characteristics
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
Table 28-7. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
Table 28-8. LCD Controller Characteristics
Symbol Parameter Condition Min Typ Max Units
ILCD LCD Driver Current Total for All COM and SEG pins 6 µA
RSEG SEG Driver Output Impedance 10 kΩ
RCOM COM Driver Output Impedance 2
338
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ATmega169P
29. Typical Characteristics
The following charts show typical behavior. These figures are not tested during m anufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock
source.
All Active- and Idle curr ent consump tion measurement s are done with all bits in t he PRR register
set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is dis-
abled during these measurements. Table 29-1 on page 343 and Table 29-2 on page 343 show
the additiona l current consu mption compar ed to I CC Active and ICC Idle for every I/ O module con-
trolled by the Power Redu ction Register. Se e ”Power Reducti on Register” on page 42 for details.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-
ture. The dominating factors are operating voltage and frequency.
The current drawn fr om capacitive loaded pin s may be estimated (for on e pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-
rent drawn by the Watchdog Timer.
29.1 Active Supply Current
Figure 29-1. Active Supply Current vs. Frequency (0.1 MHz - 1.0 MHz)
5.5V
5.0V
4.5V
4.0V
3.3V
2.7V
1.8V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
I
CC
(mA)
339
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ATmega169P
Figure 29-2. Active Supply Current vs. Frequency (1 MHz - 20 MHz)
Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz
1 MHz - 20 MHz
5.5V
5.0V
4.5V
0
5
10
15
20
25
02468101214161820
Frequency (MHz)
ICC (mA)
4.0V
3.3V
2.7V
1.8V
85°C
25°C
-40°C
0
1
2
3
4
5
6
7
8
9
10
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
ICC (mA)
340
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ATmega169P
Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
Figure 29-5. Active Supply Current vs. VCC (32 kHz Watch Crystal)
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
ICC (mA)
25°C
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
1.5 2 2.5 33.5 4 4.5 5 5.5
V
CC
(V)
ICC (µ A)
341
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ATmega169P
29.2 Idle Supply Current
Figure 29-6. Idle Supply Current vs. Frequency (0.1 MHz - 1.0 MHz)
Figure 29-7. Idle Supply Current vs. Frequency (1 MHz - 20 MHz)
0.1 MHz - 1.0 MHz
5.5V
5.0V
4.5V
4.0V
3.3V
2.7V
1.8V
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
I
CC
(mA)
1 MHz - 20 MHz
5.5V
5.0V
4.5V
0
1
2
3
4
5
6
7
8
9
10
02468101214161820
Frequency (MHz)
ICC (mA)
4.0V
3.3V
2.7V
1.8V
342
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ATmega169P
Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
3
3.5
4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)
85°C
25°C
-40°C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(mA)
343
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ATmega169P
Figure 29-10. Idle Supply Current vs. VCC (32 kHz Watch Crystal)
29.3 Supply Current of I/O modules
The tables and formulas below can b e used to calculate the additional current consumption for
the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules
are controlled by the Powe r Reduction Regist er. See ”P ower Reduction Regist er” on pag e 42 for
details.
25°C
0
2
4
6
8
10
12
14
1.5 2 2.5 33.5 4 4.5 5 5.5
VCC
(V)
I
CC
(µ A)
Table 29-1. Additional Current Consumption for the different I/O modules (absolute values)
PRR bit Typical numbers
VCC = 2V, F = 1 MHz VCC = 3V, F = 4 MHz VCC = 5V, F = 8 MHz
PRADC 18 µA 116 µA 495 µA
PRUSART0 11 µA 79 µA 313 µA
PRSPI 10 µA 72 µA 283 µA
PRTIM1 19 µA 117 µA 4 81 µA
PRLCD 4 µA 32 µA 105 µA
Table 29-2. Additional Current Consumption (percentage) in Active and Idle mode
PRR bit
Additional Current consumption
compared to Active with external clock
(see Figure 29-1 on page 338 and
Figure 29-2 on page 339)
Additional Current consumption
compared to Idle with external clock
(see Figure 29-6 on page 341 and
Figure 29-7 on page 341)
PRADC 5.6% 18.7%
PRUSART0 3.7% 12.4%
344
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ATmega169P
It is possible to calcu late t he typical cur rent co nsumption b ased on the n umber s from Tab le 29-2
on page 343 for other VCC and frequency settings than listed in Table 29-1 on page 343.
29.3.0.1 Example 1
Calculate the expected current consumption in idle mode with USART0, TIMER1, a nd SPI
enabled at V CC = 3.0V and F = 1 M Hz. From Table 29-2 on page 343, second column, we see
that we need t o add 1 2.4% for the USART 0, 10 .8% fo r the SPI, and 18. 6% for the TI MER1 mod-
ule. Reading from Figure 29-6 on page 341, we find that the idle current consumption is ~0.18
mA at VCC = 3.0V and F = 1 MHz. The total current consumption in idle mode with USART0,
TIMER1, and SPI enabled, gives:
29.4 Power-down Supply Current
Figure 29-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
PRSPI 3.2% 10.8%
PRTIM1 5.6% 18.6%
PRLCD 12.5% 41.7%
Table 29-2. Additional Current Consumption (percentage) in Active and Idle mode
PRR bit
Additional Current consumption
compared to Active with external clock
(see Figure 29-1 on page 338 and
Figure 29-2 on page 339)
Additional Current consumption
compared to Idle with external clock
(see Figure 29-6 on page 341 and
Figure 29-7 on page 341)
ICCtotal 0.18mA 1 0.124 0.108 0.186+++()•0.26mA≈≈
85°C
-40°C
25°C
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
CC
(V)
I
CC
(µ A)
345
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ATmega169P
Figure 29-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
29.5 Power-save Supply Current
Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled)
The differential current consumption between Power-save with WD disabled and 32 kHz TOSC
represents the cur rent drawn by Timer/Counter2.
WATCHDOG TIMER ENABLED
0
2
4
6
8
10
12
14
16
18
20
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
I
CC
(µA)
85
°
C
25
°
C
-40
°
C
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
CC
(V)
I
CC
(µA)
85°C
25°C
-40°C
346
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ATmega169P
29.6 Standby Supply Current
Figure 29-14. Standby Supply Current vs. VCC (32 kHz Watch Crystal, Watchdog Timer
Disabled)
Figure 29-15. Standby Supply Current vs. VCC (455 kHz Resonator, Watchd og Timer Disabled)
85°C
25°C
-40°C
0.00
0.50
1.00
1.50
2.00
2.50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
CC
(V)
I
CC
(µ A)
0
10
20
30
40
50
60
70
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (µA)
347
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Figure 29-16. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer Disabled)
Figure 29-17. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer Disabled)
0
10
20
30
40
50
60
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
I
CC
(µA)
0
10
20
30
40
50
60
70
80
90
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(µA)
348
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ATmega169P
Figure 29-18. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled)
Figure 29-19. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer Disabled)
0
10
20
30
40
50
60
70
80
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
I
CC
(µA)
0
20
40
60
80
100
120
140
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
I
CC
(µA)
349
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ATmega169P
Figure 29-20. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled)
Figure 29-21. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer Disabled)
0
20
40
60
80
100
120
140
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
ICC (µA)
0
20
40
60
80
100
120
140
160
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(µA)
350
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ATmega169P
Figure 29-22. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled)
29.7 Pin Pull-up
Figure 29-23. I/O Pin Pull-up Resistor Current vs. In put Voltage (VCC = 5V)
0
20
40
60
80
100
120
140
160
180
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(µA)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V
0
20
40
60
80
100
120
140
160
012345
V
IO
(V)
I
IO
(µA)
85
°C
25
°C
-40
°C
351
8018P–AVR–08/10
ATmega169P
Figure 29-24. I/O Pin Pull-up Resistor Current vs. In put Voltage (VCC = 2.7V)
Figure 29-25. I/O Pin Pull-up Resistor Current vs. In put Voltage (VCC = 1.8V)
0
10
20
30
40
50
60
70
80
90
0 0.5 1 1.5 2 2.5 3
V
IO
(V)
IIO (µA)
85°C 25°C
-40°C
0
10
20
30
40
50
60
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OP
(V)
I
OP
85
°C
25
°C
-40
°C
(µA)
352
8018P–AVR–08/10
ATmega169P
Figure 29-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
Figure 29-27. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
Vcc = 5V
0
20
40
60
80
100
120
012345
V
RESET
(V)
I
RESET
(µA)
-40
°C
25
°C
85
°C
0
10
20
30
40
50
60
70
0 0.5 1 1.5 2 2.5 3
V
RESET
(V)
I
RESET
(µA)
-40°C 25°C
85°C
353
8018P–AVR–08/10
ATmega169P
Figure 29-28. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
29.8 Pin Driver Strength
Figure 29-29. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC =5V)
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VRESET (V)
I
RESET
(µA)
-40°C
25°C
85°C
0
10
20
30
40
50
60
70
01234
5 6
V
OH
(V)
I
OH
(mA)
85
°C
25
°C
-40
°C
354
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ATmega169P
Figure 29-30. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC =2.7V)
Figure 29-31. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC =1.8V)
Vcc = 2.7V
0
5
10
15
20
25
0 0.5 1 1.5 2 2.5 3
VOH (V)
IOH (mA)
85°C
25°C
-40°C
Vcc = 1.8V
0
1
2
3
4
5
6
7
8
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OH
(V)
I
OH
(mA)
85°C
25°C
-40°C
355
8018P–AVR–08/10
ATmega169P
Figure 29-32. I/O Pin Source Current vs. Outp ut Volta ge, P ort B (VCC= 5V)
Figure 29-33. I/O Pin Source Current vs. Outp ut Volta ge, P ort B (VCC = 2.7V)
0
10
20
30
40
50
60
70
80
01234
V
OH
(V)
I
OH
(mA)
85°C
25°C
-40°C
Vcc = 2.7V
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3
V
OH
(V)
I
OH
(mA)
85
°C
25
°C
-40
°C
356
8018P–AVR–08/10
ATmega169P
Figure 29-34. I/O Pin Source Current vs. Outp ut Volta ge, P ort B (VCC = 1.8V)
Figure 29-35. I/O Pin Sink Current vs. Output Voltage , Ports A, C, D , E, F, G (VCC = 5V)
Vcc = 1.8V
0
1
2
3
4
5
6
7
8
9
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOH (V)
I
OH
(mA)
85
°C
25
°C
-40
°C
0
5
10
15
20
25
30
35
40
45
50
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OL
(V)
I
OL
(mA)
85
°C
25
°C
-40
°C
357
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ATmega169P
Figure 29-36. I/O Pin Sink Current vs. Output Voltage , Ports A, C, D , E, F, G (VCC = 2.7V)
Figure 29-37. I/O Pin Sink Current vs. Output Voltage , Ports A, C, D , E, F, G (VCC = 1.8V)
0
2
4
6
8
10
12
14
16
18
20
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OL
(V)
IOL (mA)
85°C
25°C
-40°C
0
1
2
3
4
5
6
7
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OL
(V)
I
OL
(mA)
85
°C
25
°C
-40
°C
358
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ATmega169P
Figure 29-38. I/O Pin Sink Current vs. Output Volta ge, Por t B (V CC = 5V)
Figure 29-39. I/O Pin Sink Current vs. Output Volta ge, Por t B (V CC = 2.7V)
0
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OL
(V)
I
OL
(mA)
85
°C
25
°C
-40
°C
0
5
10
15
20
25
30
35
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OL
(V)
I
OL
(mA)
85°C
25°C
-40°C
359
8018P–AVR–08/10
ATmega169P
Figure 29-40. I/O Pin Sink Current vs. Output Volta ge, Por t B (V CC = 1.8V)
29.9 Pin Thresholds and Hysteresis
Figure 29-41. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”)
0
2
4
6
8
10
12
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V
OL
(V)
I
OL
(m A)
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85°
C
25°
C
-40°
C
360
8018P–AVR–08/10
ATmega169P
Figure 29-42. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”)
Figure 29-43. I/O Pin Input Hysteresis vs. VCC
VIL, I/O PIN READ AS '0'
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85
°C
25
°C
-40
°C
0
0.1
0.2
0.3
0.4
0.5
0.6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Input hysteresis ( V)
85°C
25°C
-40°C
361
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ATmega169P
Figure 29-44. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”)
Figure 29-45. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”)
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85°C
25°C
-40°C
RESET INPUT THRESHOLD VOLTAGE vs. V
CC
VIL, RESET PIN READ AS '0'
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85°C
25°C
-40°C
362
8018P–AVR–08/10
ATmega169P
Figure 29-46. Reset Input Pin Hysteresis vs. VCC
29.10 BOD Thresholds and Analog Comparator Offset
Figure 29-47. BOD Thresholds vs. Temp er at ur e (BO D Le vel is 4.3 V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Input hysteresis ( V)
85
°C
25
°C
-40
°C
4
4.1
4.2
4.3
4.4
4.5
4.6
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (°C)
Threshold (V)
Rising V
CC
Falling V
CC
363
8018P–AVR–08/10
ATmega169P
Figure 29-48. BOD Thresholds vs. Temp er at ur e (BO D Le vel is 2.7 V)
Figure 29-49. BOD Thresholds vs. Temp er at ur e (BO D Le vel is 1.8 V)
BODLEVEL IS 2.7V
2.4
2.5
2.6
2.7
2.8
2.9
3
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (°C)
Threshold (V)
Rising V
CC
Falling V
CC
BODLEVEL IS 1.8V
1.5
1.6
1.7
1.8
1.9
2
2.1
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (°C)
Threshold (V)
Rising V
CC
Falling V
CC
364
8018P–AVR–08/10
ATmega169P
Figure 29-50. Bandgap Volt age vs. VCC
Figure 29-51. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)
CC
1.08
1.09
1.1
1.11
1.12
1.13
1.14
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Bandgap Voltage ( V)
85
°C
25
°C
-40
°C
CC
-0.004
-0.002
0
0.002
0.004
0.006
0.008
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Common Mode Voltage (V)
Comparator Offset Voltage (V)
85°C
25°C
-40°C
365
8018P–AVR–08/10
ATmega169P
Figure 29-52. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC =2.7V)
29.11 Internal Oscillator Speed
Figure 29-53. Oscillator Current vs. VCC (32 kHz Watch Crystal)
CC
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003
0 0.5 1 1.5 2 2.5 3
Common Mode Voltage (V)
Comparator Offset Voltage ( V)
85
°C
25
°C
-40
°C
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
CC
(V)
ICC (µ A)
85°C
25°C
-40°C
366
8018P–AVR–08/10
ATmega169P
Figure 29-54. Watchdog Oscillator Frequency vs. VCC
Figure 29-55. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
800
850
900
950
1000
1050
1100
1150
1200
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
F
RC
(kHz)
85°C
25°C
-40°C
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
7.2
7.4
7.6
7.8
8
8.2
8.4
8.6
8.8
-60 -40 -20 0 20 40 60 80 100
T
a
(°C)
F
RC
(MHz)
5.5V
4.0V
2.7V
1.8V
367
8018P–AVR–08/10
ATmega169P
Figure 29-56. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
Figure 29-57. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value
6
6.5
7
7.5
8
8.5
9
9.5
10
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
F
RC
(MHz)
85°
C
25°
C
-40°
C
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
85°C
25°C
-40°C
4
6
8
10
12
14
16
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
F
RC
(MHz)
368
8018P–AVR–08/10
ATmega169P
29.12 Current Consumption of Peripheral Units
Figure 29-58. Brownout Detector Current vs. VCC
Figure 29-59. ADC Current vs. VCC (AREF = AVCC)
0
5
10
15
20
25
30
1.5 2 2.5 33.544.555.5
V
CC
(V)
I
CC
(µA)
25°C
85°C
-40°C
CC
0
50
100
150
200
250
300
350
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (µA)
85°
C
25°
C
-40°
C
369
8018P–AVR–08/10
ATmega169P
Figure 29-60. AREF External Referenc e Cu rr en t vs. V CC
The differential current consumption between Power-save with WD disabled and 32 kHz TOSC
represents the cur rent drawn by Timer/Counter2.
Figure 29-61. Watchdog Timer Current vs. VCC
CC
0
20
40
60
80
100
120
140
160
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
AREF
(µA)
85°
C
25°
C
-40°
C
0
2
4
6
8
10
12
14
16
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
I
CC
(µA)
85°C
25°C
-40°C
370
8018P–AVR–08/10
ATmega169P
Figure 29-62. Analog Comparator Current vs. VCC
Figure 29-63. Programming Current vs. VCC
0
20
40
60
80
100
120
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
ICC (µA)
85°C
25°C
-40°C
0
5
10
15
20
25
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
ICC (mA)
85°C
25°C
-40°
C
371
8018P–AVR–08/10
ATmega169P
29.13 Current Consumption in Reset and Reset Pulsewidth
Figure 29-64. Reset Supply Current vs. VCC (0.1 MHz - 1.0 MHz, Excluding Current Through
The Reset Pull-up)
Figure 29-65. Reset Supply Current vs. VCC (1 MHz - 20 MHz, Excluding Current Through The
Reset Pull-up)
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
I
CC
(mA)
5.5V
4.5V
4.0V
3.3V
2.7V
1.8V
5.0V
0
0.5
1
1.5
2
2.5
3
3.5
02468101214161820
Frequency (MHz)
I
CC
(mA)
5.5V
4.5V
4.0V
3.3V
2.7V
1.8V
5.0V
372
8018P–AVR–08/10
ATmega169P
Figure 29-66. Minimum Reset Pulse Widt h vs. VCC
0
500
1000
1500
2000
2500
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Pulsewidth (ns)
85°C
25°C
-40°C
373
8018P–AVR–08/10
ATmega169P
30. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved ––––––––
(0xFE) LCDDR18 ––––––– SEG324 251
(0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 251
(0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 251
(0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 251
(0xFA) Reserved ––––––––
(0xF9) LCDDR13 ––––––– SEG224 251
(0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 251
(0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 251
(0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 251
(0xF5) Reserved ––––––––
(0xF4) LCDDR8 ––––––– SEG124 251
(0xF3) LCDDR7 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 251
(0xF2) LCDDR6 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 251
(0xF1) LCDDR5 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 251
(0xF0) Reserved ––––––––
(0xEF) LCDDR3 ––––––– SEG024 251
(0xEE) LCDDR2 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 251
(0xED) LCDDR1 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG09 SEG008 251
(0xEC) LCDDR0 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 251
(0xEB) Reserved ––––––––
(0xEA) Reserved ––––––––
(0xE9) Reserved ––––––––
(0xE8) Reserved ––––––––
(0xE7) LCDCCR LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 250
(0xE6) LCDFRR –LCDPS2 LCDPS1 LCDPS0 –LCDCD2 LCDCD1 LCDCD0 248
(0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 –LCDPM2 LCDPM1 LCDPM0 247
(0xE4) LCDCRA LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL 246
(0xE3) Reserved ––––––––
(0xE2) Reserved ––––––––
(0xE1) Reserved ––––––––
(0xE0) Reserved ––––––––
(0xDF) Reserved ––––––––
(0xDE) Reserved ––––––––
(0xDD) Reserved ––––––––
(0xDC) Reserved ––––––––
(0xDB) Reserved ––––––––
(0xDA) Reserved ––––––––
(0xD9) Reserved ––––––––
(0xD8) Reserved ––––––––
(0xD7) Reserved ––––––––
(0xD6) Reserved ––––––––
(0xD5) Reserved ––––––––
(0xD4) Reserved ––––––––
(0xD3) Reserved ––––––––
(0xD2) Reserved ––––––––
(0xD1) Reserved ––––––––
(0xD0) Reserved ––––––––
(0xCF) Reserved ––––––––
(0xCE) Reserved ––––––––
(0xCD) Reserved ––––––––
(0xCC) Reserved ––––––––
(0xCB) Reserved ––––––––
(0xCA) Reserved ––––––––
(0xC9) Reserved ––––––––
(0xC8) Reserved ––––––––
(0xC7) Reserved ––––––––
(0xC6) UDR0 USART0 I/O Data Register 194
(0xC5) UBRRH0 USART0 Baud Rate Register High 198
(0xC4) UBRRL0 USART0 Baud Rate Register Low 198
(0xC3) Reserved ––––––––
(0xC2) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 194
(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 194
(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 194
374
8018P–AVR–08/10
ATmega169P
(0xBF) Reserved ––––––––
(0xBE) Reserved ––––––––
(0xBD) Reserved ––––––––
(0xBC) Reserved ––––––––
(0xBB) Reserved ––––––––
(0xBA) USIDR USI Data Register 207
(0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 207
(0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 208
(0xB7) Reserved – ––––––
(0xB6) ASSR – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB 156
(0xB5) Reserved ––––––––
(0xB4) Reserved ––––––––
(0xB3) OCR2A Timer/Counter2 Output Compare Register A 155
(0xB2) TCNT2 Timer/Counter2 (8-bit) 155
(0xB1) Reserved ––––––––
(0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 153
(0xAF) Reserved ––––––––
(0xAE) Reserved ––––––––
(0xAD) Reserved ––––––––
(0xAC) Reserved ––––––––
(0xAB) Reserved ––––––––
(0xAA) Reserved ––––––––
(0xA9) Reserved ––––––––
(0xA8) Reserved ––––––––
(0xA7) Reserved ––––––––
(0xA6) Reserved ––––––––
(0xA5) Reserved ––––––––
(0xA4) Reserved ––––––––
(0xA3) Reserved ––––––––
(0xA2) Reserved ––––––––
(0xA1) Reserved ––––––––
(0xA0) Reserved ––––––––
(0x9F) Reserved ––––––––
(0x9E) Reserved ––––––––
(0x9D) Reserved ––––––––
(0x9C) Reserved ––––––––
(0x9B) Reserved ––––––––
(0x9A) Reserved ––––––––
(0x99) Reserved ––––––––
(0x98) Reserved ––––––––
(0x97) Reserved ––––––––
(0x96) Reserved ––––––––
(0x95) Reserved ––––––––
(0x94) Reserved ––––––––
(0x93) Reserved ––––––––
(0x92) Reserved ––––––––
(0x91) Reserved ––––––––
(0x90) Reserved ––––––––
(0x8F) Reserved ––––––––
(0x8E) Reserved ––––––––
(0x8D) Reserved ––––––––
(0x8C) Reserved ––––––––
(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 132
(0x8A) O CR1BL Timer/Counter1 - Output Compare Register B Low Byte 132
(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 132
(0x88) OCR1AL Timer/Counter1 - Output Compare Reg ister A Low Byte 132
(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 133
(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 133
(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 132
(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 132
(0x83) Reserved ––––––––
(0x82) TCCR1C FOC1A FOC1B ––––––131
(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 130
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 ––WGM11WGM10128
(0x7F) DIDR1 ––––––AIN1DAIN0D215
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 233
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
375
8018P–AVR–08/10
ATmega169P
(0x7D) Reserved ––––––––
(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 229
(0x7B) ADCSRB –ACME––– ADTS2 ADTS1 ADTS0 214, 233
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 231
(0x79) ADCH ADC Data Register High byte 232
(0x78) ADCL ADC Data Register Low byte 232
(0x77) Reserved ––––––––
(0x76) Reserved ––––––––
(0x75) Reserved ––––––––
(0x74) Reserved ––––––––
(0x73) Reserved ––––––––
(0x72) Reserved ––––––––
(0x71) Reserved ––––––––
(0x70) TIMSK2 –––––– OCIE2A TOIE2 156
(0x6F) TIMSK1 ––ICIE1–– OCIE1B OCIE1A TOIE1 133
(0x6E) TIMSK0 –––––– OCIE0A TOIE0 104
(0x6D) Reserved ––––––––
(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 63
(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 64
(0x6A) Reserved ––––––––
(0x69) EICRA ––––––ISC01ISC0062
(0x68) Reserved ––––––––
(0x67) Reserved ––––––––
(0x66) OSCCAL Oscillator Calibration Register 38
(0x65) Reserved ––––––––
(0x64) PRR – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC 45
(0x63) Reserved ––––––––
(0x62) Reserved ––––––––
(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 38
(0x60) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 54
0x3F (0x5F) SREG I T H S V N Z C 13
0x3E (0x5E) SPH ––––– SP10 SP9 SP8 13
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13
0x3C (0x5C) Reserved
0x3B (0x5B) Reserved
0x3A (0x5A) Reserved
0x39 (0x59) Reserved
0x38 (0x58) Reserved
0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 294
0x36 (0x56) Reserved ––––––––
0x35 (0x55) MCUCR JTD ––PUD–– IVSEL IVCE 60, 88, 279
0x34 (0x54) MCUSR – – – JTRF WDRF BORF EXTRF PORF 279
0x33 (0x53) SMCR –––– SM2 SM1 SM0 SE 45
0x32 (0x52) Reserved ––––––––
0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 258
0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 214
0x2F (0x4F) Reserved ––––––––
0x2E (0x4E) SPDR SPI Data Register 167
0x2D (0x4D) SPSR SPIF WCOL –––––SPI2X166
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 165
0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 28
0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 28
0x29 (0x49) Reserved ––––––––
0x28 (0x48) Reserved ––––––––
0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 104
0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 104
0x25 (0x45) Reserved ––––––––
0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 102
0x23 (0x43) GTCCR TSM – – – – – PSR2 PSR10 137, 157
0x22 (0x42) EEARH ––––––– EEAR8 28
0x21 (0x41) EEARL EEPROM Address Register Low Byte 28
0x20 (0x40) EEDR EEPROM Data Register 29
0x1F (0x3F) EECR –––– EERIE EEMWE EEWE EERE 29
0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 28
0x1D (0x3D) EIMSK PCIE1 PCIE0 –––––INT062
0x1C (0x3C) EIFR PCIF1 PCIF0 –––––INTF0 63
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
376
8018P–AVR–08/10
ATmega169P
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructio ns.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Statu s Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instru ctions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used .
0x1B (0x3B) Reserved ––––––––
0x1A (0x3A) Reserved ––––––––
0x19 (0x39) Reserved ––––––––
0x18 (0x38) Reserved ––––––––
0x17 (0x37) TIFR2 –––––– OCF2A TOV2 156
0x16 (0x36) TIFR1 ––ICF1–– OCF1B OCF1A TOV1 134
0x15 (0x35) TIFR0 –––––– OCF0A TOV0 105
0x14 (0x34) PORTG –– PORTG5PORTG4PORTG3PORTG2PORTG1PORTG0 90
0x13 (0x33) DDRG –– DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 90
0x12 (0x32) PING –– PING5 PING4 PING3 PING2 PING1 PING0 90
0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 P ORTF1 PORTF0 90
0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 90
0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 90
0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5PORTE4PORTE3PORTE2PORTE1PORTE0 89
0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 89
0x0C (0x2C) PINE PINE7 PINE6 PINE5PINE4PINE3PINE2PINE1PINE0 90
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 89
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 89
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 89
0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 89
0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 89
0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 89
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0 88
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 88
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 88
0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5PORTA4PORTA3PORTA2PORTA1PORTA0 88
0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 88
0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 88
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
377
8018P–AVR–08/10
ATmega169P
31. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immedia te to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or M i nus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd , Rr Mu ltiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multipl y Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Frac tional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Frac tional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
JMP k Direct Jump PC ← kNone3
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← ZNone3
CALL k Direct Subroutine Call PC ← kNone4
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,R r Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register wit h Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Fla g Set if (SREG(s) = 1) then PC←PC+k + 1 N one 1/2
BRBC s , k Branc h if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
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BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 N one 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 N one 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR R d Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← TNone1
SEC Set Carry C ← 1C1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1N1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1Z1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1I1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1S1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1V1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1T1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1H1
CLH Clear Half Carry Flag in SREG H ← 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← KNone1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+ 1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Ind ir e ct (Z ) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memo ry R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Lo ad Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 No n e 3
SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd, P In Port Rd ← PNone1
OUT P, Rr Out Port P ← Rr None 1
Mnemonics Operands Description Operation Flags #Clocks
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PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #Clocks
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32. Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive f or Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 331 and Figure 28-2 on page 33 2 .
Speed (MHz)(3) Power Supply Ordering Code Package(1)(2) Operation Range
8 1.8V - 5.5V ATmega169PV-8AU
ATmega169PV-8MU
ATmega169PV-8MCH
64A
64M1
64MC
Industrial
(-40°C to 85°C)
16 2.7V - 5.5V ATmega169P-16AU
ATmega169P-16MU
ATmega169P-16MCH
64A
64M1
64MC
Industrial
(-40°C to 85°C)
Package Type
64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1 64-pad, 9 × 9 × 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
64MC 64-lead (2-row Staggered), 7 × 7 × 1.0 mm body, 4.0 × 4.0 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
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33. Packaging Information
33.1 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
64A
10/5/2001
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
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33.2 64M1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
G
64M1
5/25/06
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
b 0.180.25 0.30
D
D2 5.20 5.40 5.60
8.90 9.00 9.10
8.90 9.00 9.10
E
E2 5.20 5.40 5.60
e 0.50 BSC
L0.35 0.40 0.45
Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D
E
Marked Pin# 1 ID
SEATING PLANE
A1
C
A
C
0.08
1
2
3
K 1.25 1.40 1.55
E2
D2
be
Pin #1 Corner
L
Pin #1
Tr i angle
Pin #1
Chamfer
(C 0.30)
Option A
Option B
Pin #1
Notch
(0.20 R)
Option C
K
K
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
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33.3 64MC
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 64MCZXC A
64MC, 64QFN (2-Row Staggered),
7 x 7 x 1.00 mm Body, 4.0 x 4.0 mm Exposed Pad,
Quad Flat No Lead Package
10/3/07
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
b 0.18 0.23 0.28
C 0.20 REF
D 6.90 7.00 7.10
D2 3.95 4.00 4.05
E 6.90 7.00 7.10
E2 3.95 4.00 4.05
eT – 0.65 –
eR – 0.65 –
K 0.20 – – (REF)
L 0.35 0.40 0.45
y 0.00 – 0.075
SIDE VIEW
TOP VIEW
BOTTOM VIEW
Note: 1. The terminal #1 ID is a Laser-marked Feature.
Pin 1 ID
D
EA1
A
y
C
eT/2
R0.20 0.40
B1
A1
B30
A34
b
A8
B7
eT
D2
B16
A18
B22
A25
E2
K(0.1) REF
B8
A9
(0.18) REF
L
B15
A17
L
eR
A26
B23
eT
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34. Errata
34.1 ATmega169P Rev. G
No known errata.
34.2 ATmega169P Rev. A to F
Not sampled.
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35. Datasheet Revision History
Please note that the referring page num bers in this section are referring to this document. The
referring re visio n in th is section are referring to the document revision.
35.1 Rev. 8018P 08/10
35.2 Rev. 8018O 10/09
35.3 Rev. 8018N 08/09
35.4 Rev. 8018M 07/09
35.5 Rev. L 08/08
35.6 Rev. K 06/08
1. Status changed to active
2. EEPROM minimum wait del ay, Table 27-15 on page 312, has been changed from 9.0
ms to 3.6 ms
3. Datasheet layout and technical t erminology updated
1. Changed datasheet status to “Mature”
2. Added Capacitance for Low-frequency Crystal Oscillator, Table 8-5 on page 33.
1. Updated ”Ordering Informa tion” on page 380, MCU r eplaced by MCH.
1. Updated the last page with new Atmel’s addresses.
1. Updated package information in ”Features” on page 1.
2. Added ”Pinout - DRQFN” on page 3:
• The Staggered QF N is named Dual Row QFN (DRQFN).
1. Updated package information in ”Featu res” on page 1.
2. Removed “Disclaimer” from section ”Pin Configurations” on page 2
3. Added ”64MC (DRQFN) Pinout ATmega169P” on page 3
4. Added ”Data Retention” on page 9.
5. Updated ”Stack Pointer” on page 13.
6. Updated ”Low-frequency Crystal Oscillator” on page 34.
7. Updated ”USART Register Description” on page 194, re gister descriptions and tables .
8. Updated ”UCSRnB – USART Control and Status Regist er n B” on page 195.
9. Updated VIL2 in ”DC Characteristics” on page 329, by removing 0.2VCC from the table .
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35.7 Rev. J 08/07
35.8 Rev. I 11/06
35.9 Rev. H 09/06
35.10 Rev. G 08/06
35.11 Rev. F 08/06
35.12 Rev. E 08/06
10. Replaced Figure 29-36 on page 357 by a correct one.
11. Updated ”Ordering Informa tion” on page 380.
12. Added ”64MC” on page 383 package to ”P ackaging Information” on page 381.
1. Updated ”Features” on page 1.
2. Added ”Minimizing Power Consumption” on page 237 in the LCD section.
3. Updated ”System and Reset Characteristics” on page 333.
1. Updated ”Low-frequency Crystal Oscillator” on page 34.
2. Updated Table 8-8 on page 35, Table 8-9 on page 35, Table 8-10 on page 35, Table
28-7 on page 336.
3. Up da te d no te in Table 28-7 on page 336.
1. All characterization data moved to ”Electrical Characteristics” on page 329.
2. Updated ”Calibrated Internal RC Oscillator” on page 32.
3. Updated ”System Control and Reset” on page 47.
4. Added note to Table 27-16 on page 314.
5. Updated ”LCD Controller Characteristics” on page 337 .
1. Updated ”LCD Controller Characteristics” on page 337 .
1. Updated ”DC Characteristics” on page 329.
2. Updated Table 13-19 on page 84.
1. Updated ”Low-frequency Crystal Oscillator” on page 34.
2. Updated ”Device Identification Register” on page 260.
3. Updated ”Signature Bytes” on page 299.
4. Added Table 27-6 on page 299.
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35.13 Rev. D 07/06
35.14 Rev. C 06/06
35.15 Rev. B 04/06
35.16 Rev. A 03/06
1. Updated ”Register Description for I/O-Ports” on page 88.
2. Updated ”Fast PWM Mode” on page 97.
3. Updated ”Fast PWM Mode” on page 120.
4. Updated Table 14-2 on page 102, Table 14-4 on page 103, Table 15-3 on page 129,
Table 15-4 on page 130, Table 17-2 on page 153 and Table 17-4 on page 154.
5 Updated ”UCSRnC – USART Control and Status Reg ister n C” on page 196.
6. Updated Features in ”USI – Universal Serial Interface” on page 199.
7. Added ”Clock speed considerations.” on page 206.
8. Updated Features in ”LCD Controller” on page 234.
9. Updated ”Register Summary” on page 373.
1. Up da te d typ os .
2. Updated ”Calibrated Internal RC Oscillator” on page 32.
3. Updated ”OSCCAL – Oscillator Calibration Register” on page 38.
4. Added Table 28-2 on page 332.
1. Updated ”Calibrated Internal RC Oscillator” on page 32.
1. Initial revision.
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Table of Contents
Features..................................................................................................... 1
1 Pin Configurations ................................................................................... 2
1.1Pinout - TQFP/QFN/MLF ...........................................................................................2
1.2Pinout - DRQFN ........................................................................................................3
2 Overview ................................................................................................... 4
2.1Block Diagram ...........................................................................................................4
2.2Pin Descr iptio n s .................. ... ................. ... ... ................ ... .... ................ ... ... ...............6
3 Resources ................................................................................................. 9
4 Data Retention .......................................................................................... 9
5 About Code Examples ........................................................................... 10
6 AVR CPU Core ........................................................................................11
6.1Introduction ....................................... ............................. ............................. .............11
6.2Architectural Overview .................. ... ... ................ .... ... ................ ... ... ................. ... ...11
6.3ALU – Arithm etic Lo gic Unit ....... ... ................ ... ... .... ................ ... ... ... .... ................ ...12
6.4Stack Pointer ...........................................................................................................13
6.5Instruction Execution Timing ...................................................................................14
6.6Reset and Interrupt Handling ..................................................................................15
6.7Status Register ........................................................................................................17
6.8General Purpose Register File ................................................................................18
7 AVR Memories ........................................................................................ 20
7.1In-Syste m Re pr og ra m ma b le Fla sh Prog r am Me mo ry ... ................ ... .... ................ ...20
7.2SRAM Data Memory ...............................................................................................21
7.3EEPROM Data Memory ..........................................................................................23
7.4I/O Memory ..............................................................................................................27
7.5General Purpose I/O Registers ...............................................................................28
7.6EEPROM Register Description ................................................................................28
8 System Clock and Clock Options ......................................................... 30
8.1Clock Systems and their Distribution .......................................................................30
8.2Clock Sources .........................................................................................................31
8.3Default Cloc k Source ........... ... .... ................ ... ... ................ .... ... ................ ... ... ..........32
8.4Calibrated Internal RC Oscillator .............................................................................32
8.5Crystal Oscillator .....................................................................................................33
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8.6Low-frequency Crystal Oscillator .............................................................................34
8.7External Clock .........................................................................................................36
8.8Timer/Counter Oscillator .........................................................................................37
8.9Clock Output Buffer .................................................................................................37
8.10System Clock Prescaler ........................................................................................37
8.11Registe r Descr iption ................. ... ... ................ ... .... ... ................ ... ... ................. ... ...38
9 Power Management and Sleep Modes ................................................. 40
9.1Sleep Modes ...........................................................................................................40
9.2Idle Mode .................................................................................................................41
9.3ADC Noise Redu ctio n Mod e ............... .... ... ... ... ... ................. ... ... ... ................ .... ... ...41
9.4Power -d ow n Mo d e ................. ................. ... ................ ... ... ................ .... ................ ...41
9.5Power-save Mode ...................................................................................................42
9.6Standby Mode .........................................................................................................42
9.7Power Reduction Register .......................................................................................42
9.8Minimizing Power Consumption ..............................................................................43
9.9Register Description ................................................................................................45
10 System Control and Reset .................................................................... 47
10.1Resetting the AVR .................................................................................................47
10.2Reset Sourc es ................... ... .... ................ ... ... ... ................. ... ... ... ................ .... ... ...47
10.3Internal Voltage Reference ....................................................................................51
10.4Watchdog Timer ....................................................................................................51
10.5Registe r Descr iption ................. ... ... ................ ... .... ... ................ ... ... ................. ... ...54
11 Interrupts ................................................................................................ 56
11.1Interrupt Vectors in ATmega169P .........................................................................56
11.2Moving Interrupts Between Application and Boot Space ......................................59
12 External Interrupts ................................................................................. 61
12.1Pin Change Interrupt Timing .................................................................................61
12.2Registe r Descr iption ................. ... ... ................ ... .... ... ................ ... ... ................. ... ...62
13 I/O-Ports .................................................................................................. 65
13.1Overview ...............................................................................................................65
13.2Ports as General Digital I/O ...................................................................................66
13.3Alternate Port Functions ........................................................................................71
13.4Registe r De scr ipt ion for I/O -Ports .......... ... ................ ... ... ................ .... ... ................88
14 8-bit Timer/Counter0 with PWM ............................................................ 91
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14.1Features ................................................................................................................91
14.2Overview ...............................................................................................................91
14.3Timer/Counter Clock Sources ...............................................................................92
14.4Counter Unit ..........................................................................................................92
14.5Output Com p ar e Unit .................. ... ................ ... .... ................ ... ................ ... .... ......93
14.6Compare Match Output Unit ..................................................................................95
14.7Modes of Operation ...............................................................................................96
14.8Timer/Counter Timing Diagrams .........................................................................100
14.98-bit Timer/Counter Register Description ............................................................102
15 16-bit Timer/Counter1 .......................................................................... 106
15.1Features ..............................................................................................................106
15.2Overview .............................................................................................................106
15.3Accessin g 16 -b it Reg isters ............. ... .... ... ................ ... ... .... ................ ... ... ... ........109
15.4Timer/Counter Clock Sources .............................................................................111
15.5Counter Unit ........................................................................................................112
15.6Input Capture Unit ...............................................................................................113
15.7Output Com p ar e Units .......... .... ... ... ... .... ................ ... ... ... ................ .... ... ..............115
15.8Compare Match Output Unit ................................................................................117
15.9Modes of Operation .............................................................................................118
15.10Timer/ C o unte r Tim i n g Diagrams .. ... .... ... ... ................ ... .... ................ ... ... ...........126
15.1116-bit Timer/Counter Register Description ........................................................128
16 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 135
16.1Prescaler Reset ...................................................................................................135
16.2Internal Clock Source ..........................................................................................135
16.3Extern al Cloc k Sou rce ....... ... .... ... ................ ... ... .... ................ ... ... ... ................. ... .135
16.4Registe r Descr iption ................. ... ... ................ ... .... ... ................ ... ... ................. ... .137
17 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 138
17.1Overview .............................................................................................................138
17.2Timer/Counter Clock Sources .............................................................................139
17.3Counter Unit ........................................................................................................139
17.4Output Com p ar e Unit .................. ... ................ ... .... ................ ... ................ ... .... ....14 0
17.5Compare Match Output Unit ................................................................................142
17.6Modes of Operation .............................................................................................143
17.7Timer/Counter Timing Diagrams .........................................................................148
17.8Asynchronous operation of the Timer/Counter ....................................................150
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17.9Timer/Counter Prescaler .....................................................................................152
17.108-bit Timer/Counter Register Description ..........................................................153
18 SPI – Serial Peripheral Interface ......................................................... 158
18.1Features ..............................................................................................................158
18.2Overview .............................................................................................................158
18.3SS Pin Functionality ....... ... ... .... ... ... ................ ... .... ... ................ ... ... .... ................ .163
18.4Data Modes .........................................................................................................164
18.5Registe r Descr iption ................. ... ... ................ ... .... ... ................ ... ... ................. ... .165
19 USART ................................................................................................... 168
19.1Features ..............................................................................................................168
19.2Overview .............................................................................................................168
19.3Clock Generation .................................................................................................170
19.4Frame Forma ts ..... ... .... ... ... ... .... ................ ... ... ... ................. ... ... ................ ... .... ... .173
19.5USART Initialization ............................................................................................175
19.6Data Transmission – The USART Transmitter ....................................................177
19.7Data Recep tio n – Th e USART Re ceiver ............... ... ... ... .... ... ................ ... ... .... ... .180
19.8Asynchronous Data Reception ............................................................................185
19.9Multi-processor Communication Mode ................................................................188
19.10Examples of Baud Rate Setting ........................................................................190
19.11USART Re gist er Desc rip tio n ..... ... ................ ... .... ... ... ................ ... .... ... ... ...........194
20 USI – Universal Serial Interface .......................................................... 199
20.1Overview .............................................................................................................199
20.2Functional Descriptions .......................................................................................200
20.3Alternative USI Usage .........................................................................................206
20.4USI Register Descriptions ...................................................................................207
21 AC - Analog Comparator ..................................................................... 212
21.1Analog Comparator Multiplexed Input .................................................................213
21.2Analog Comparator Register Description ............................................................214
22 ADC - Analog to Digital Converter ..................................................... 216
22.1Features ..............................................................................................................216
22.2Overview .............................................................................................................216
22.3Operatio n ..................... .......................... ......................... .......................... ...........21 7
22.4Startin g a Con ve rs ion ..................... ... .... ................ ... ................ ... ... ................. ... .218
22.5Prescaling and Conversion Timing ......................................................................219
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22.6Changing Channel or Reference Selection .........................................................221
22.7ADC Noise Canceler ...........................................................................................222
22.8ADC Conversion Result ......................................................................................227
22.9ADC Register Description ...................................................................................229
23 LCD Controller ..................................................................................... 234
23.1Features ..............................................................................................................234
23.2Overview .............................................................................................................234
23.3Mode of Operation ...............................................................................................237
23.4LCD Usage ........ ... ................ .... ... ... ................ ... .... ................ ... ... ... ................. ... .242
23.5LCD Register Desc rip tio n ..... ................. ... ... ... ................ .... ... ... ... ................ .... ... .246
24 JTAG Interface and On-chip Debug System ..................................... 252
24.1Overview .............................................................................................................252
24.2TAP – Test Access Port ......................................................................................253
24.3TAP Controller .....................................................................................................255
24.4Using the Boundary-scan Chain ..........................................................................256
24.5Using the On-chip Debug System .......................................................................256
24.6On-chi p De bug Spe c if ic JTAG Ins tru ct ion s ....... .... ... ... ... ................ .... ... ... ... ........257
24.7On-chi p De bu g Re lat ed Regi ste r in I/O Memo ry ................ ... ................ ... ... .... ....25 8
24.8Using the JTAG Programming Capabilities .........................................................258
24.9Bibliograp hy .................................... ............................. ............................. ........... 258
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259
25.1Features ..............................................................................................................259
25.2System Overview ................................................................................................259
25.3Data Registers .....................................................................................................260
25.4Boundary-scan Specific JTAG Instructions .........................................................261
25.5Boundar y- sca n Ch ain ........ ... ................. ... ... ... ................ .... ... ... ................ ... .... ....26 2
25.6Boundar y- sca n Or de r ........................ .... ................ ... ... ................ ... ................. ... .272
25.7Boundary-scan Description Language Files ........................................................278
25.8Boundar y- sca n Re lat ed Reg iste r in I/O Mem o ry ...... ... ................ ... .... ... ..............279
26 Boot Loader Support – Read-While-Write Self-Programming ......... 280
26.1Features ..............................................................................................................280
26.2Overview .............................................................................................................280
26.3Application and Boot Loader Flash Sections .......................................................280
26.4Read-While-Write and No Read-While-Write Flash Sections ..............................281
26.5Boot Loader Lock Bits .........................................................................................284
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26.6Entering the Boo t Lo a de r Pro gram ........... ... ... ... .... ................ ... ... ................ .... ... .285
26.7Addressin g th e Fla sh Dur ing Self- Pro gr am m i n g ...... ... ... .... ... ... ................ ... .... ... .286
26.8Self-Pro gr a mm in g th e Flash .............. ................ .... ... ................ ... ... .... ................ .287
26.9Registe r Descr iption ................. ... ... ................ ... .... ... ................ ... ... ................. ... .294
27 Memory Programming ......................................................................... 296
27.1Program And Data Memory Lock Bits .................................................................296
27.2Fuse Bits . .... ... ... ................ ... .... ... ................ ... ... .... ................ ... ... ................ .... ... .297
27.3Signature Bytes ...................................................................................................299
27.4Calibratio n Byte ........... ... ... ................ .... ... ... ................ ... .... ................ ... ... ... ........299
27.5Page Size ............................................................................................................299
27.6Parallel Programming Parameters, Pin Mapping, and Commands .....................299
27.7Parallel Programming ..........................................................................................302
27.8Serial Downloading .............................................................................................310
27.9Programming via the JTAG Interface ..................................................................316
28 Electrical Characteristics .................................................................... 329
28.1Absolute Ma xim u m Ra tin gs* ............. .... ................ ... ... ... .... ................ ... ... ... ........329
28.2DC Characteristics ..............................................................................................329
28.3Speed Grades .....................................................................................................331
28.4Clock Characteristics ...........................................................................................332
28.5System and Reset Characteristics ......................................................................333
28.6SPI Timing Characteristics ..................................................................................334
28.7ADC Characteristics – Preliminary Data ..............................................................336
28.8LCD Contro ller Char a cte rist ics . ... ................ ... ... .... ... ................ ... ... .... ................ .337
29 Typical Characteristics ........................................................................ 338
29.1Active Supply Current ..........................................................................................338
29.2Idle Supply Current ..............................................................................................341
29.3Supply Curr en t of I/O mo du les .................... ... ... ................. ... ................ ... ... ........34 3
29.4Power-down Supply Current ...............................................................................344
29.5Power-save Supply Current ................................................................................345
29.6Standby Sup p l y Cur re nt . ... ... .... ... ... ................ ... .... ... ................ ... ... ................. ... .346
29.7Pin Pull-up ...........................................................................................................350
29.8Pin Driver Strength ..............................................................................................353
29.9Pin Thresholds and Hysteresis ............................................................................359
29.10BOD Thresholds and Analog Comparator Offset ..............................................362
29.11Internal Oscillator Speed .... .... ... ... ... .... ... ... ... ... .... ..............................................365
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29.12Current Consumption of Peripheral Units ..........................................................368
29.13Current Consumption in Reset and Reset Pulsewidth ......................................371
30 Register Summary ............................................................................... 373
31 Instruction Set Summary .................................................................... 377
32 Ordering Information ........................................................................... 380
33 Packaging Information ........................................................................ 381
33.164A ......................................................................................................................381
33.264M1 ...................................................................................................................382
33.364MC ................................................................................................................... 383
34 Errata ..................................................................................................... 384
34.1ATmega169P Rev. G ..........................................................................................384
34.2ATmega169P Rev. A to F ...................................................................................384
35 Datasheet Revision History ................................................................ 385
35.1Rev. 8018P 08/10 ................................................................................................385
35.2Rev. 8018O 10/09 ...............................................................................................385
35.3Rev. 8018N 08/09 ...............................................................................................385
35.4Rev. 8018M 07/09 ...............................................................................................385
35.5Rev. L 08/08 ........................................................................................................385
35.6Rev. K 06/08 ........................................................................................................385
35.7Rev. J 08/07 ........................................................................................................386
35.8Rev. I 11/06 .........................................................................................................386
35.9Rev. H 09/06 .......................................................................................................386
35.10Rev. G 08 /0 6 ............. ... ... ... .... ... ................ ... ... ................. ... ... ................ ... .... ....3 8 6
35.11Rev. F 08 /0 6 .................... ... ................. ... ................ ... ................ ... ................. ... .386
35.12Rev. E 08/ 06 .............................. ... ... ................ .... ... ................ ... ... ................. ... .386
35.13Rev. D 07/ 06 ................... ... .... ... ... ... ................ .... ... ................ ... ................ .... ... .387
35.14Rev. C 06/ 06 ................... ... .... ... ... ... ................ .... ... ................ ... ................ .... ... .387
35.15Rev. B 04/ 06 .............................. ... ... ................ .... ... ................ ... ... ................. ... .387
35.16Rev. A 03/ 06 .............................. ... ... ................ .... ... ................ ... ... ................. ... .387
Table of Contents....................................................................................... i
8018O–AVR–10/09
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