MAAL/VI Low Power, 3% Digit A/D Converter _General Description The Maxim 1CL7126 is a monolithic analog to digital converter with very high input impedance. On-board active components include segment drivers, segment decoders, voltage reference and a clock circuit. The ICL7126 directly drives a non-multiplexed liquid crystal (LCD) display, requiring no external display drive circuitry. Significantly reduced power consumption makes the ICL7126 a superior device, especially for portable systems. Versatility and accuracy are inherent features of this converter. The dual-slope conversion technique auto- matically rejects interference signals common in indus- trial environments. The true differential input and reference are particularly useful when making ratio- metric measurements (ohms or bridge transducers), and the zero-integrator phase in Maxim's ICL7126 eliminates overrange hangover and hysteresis effects. The Zero Integrator phase also allows the use of larger auto zero capacitors reducing noise further. Finally, this device offers high accuracy by lowering rollover error to less than one count and zero reading drift to less than 1uV/C. _ ss tC CA pptiications These devices can be used in a wide range of digital panel meter applications. Most applications, however, invoive the measurement and display of analog data: ee _ Features improved 2nd Source! (See 3rd page for Maxim Advantage). @ Power dissipation guaranteed less than 1mW-9V battery life 3000 hours typical @ Guaranteed first reading recovery from overrange Zero Input Gives Zero Reading Drives LCD Displays Directly Low Noise (15.V p-p) without hysteresis or over- range hangover @ True Differential Reference and Input @ Monolithic, Low Power CMOS _ ___._. __._ Ordering information PART TEMP. RANGE PACKAGE ICL7126CPL 0C to +70G 40 Lead Plastic DIP ICL7126CJL 0C to +70C 40 Lead CERDIP 3 44 Lead Plastic ICL7126CQH OC to +70C Chip Carrier ICL7126C/D 0C to +70C Dice ____..____ Typical Operating Circuit | | | LCD Pressure Conductance \ Voltage Current Display Resistance Speed Temperature Material Thickness - (LILtLi 5 san Ty CO) _ ss __:tiCCiRin Configuration INPUT H 1 MAxIA | iCL7126 e v* osc 1 y = ov ot OSC 2 REF C1 osc 3 = rs 8! TEST TH Al REF HI FA REF LO Gt CREF f1 Crer TO ANALOG D2 ICL7126 COMMON COMMON (P32) c2 IN HI 1< B2 iN LO 10'S a2 A/Z F2 BUFF E2 (NT FULL SCALE VREF D3 v : (NPUT 1 83 G2(TENS) 2.000 V 7.000 V 100'S F3 C3 200.0 mV. 100.0 mv E3 A3 100'S ~~ 1000'S-AB4 [a G3__| POL Gq BP (MINUS SIGN) See 1CL7106 for 44 Lead PLCC Pin Configuration | { Detailed Circuit DiagramFigure 1 & 2 ) The Maxim Advantage signifies an upgraded quality level. At no additional cost we offer a second-source device that is subject to the following: guaranteed performance over temperature along with tighter test specifications on many key parameters; and device enhancements, when needed, that result in improved performance without changing the functionality. MAXIM Maxim integrated Products 1 92KZTOIICL7126 Low Power, 3% Digit A/D Converter ABSOLUTE MAXIMUM RATINGS Power Dissipation (Note 2) Cerdip Package 2.0... . ccc cee eee 1000mW Supply Voltage (V7 toV) ..... eee 15V Plastic Package ....... cece eee eee s00mw Analog Input Voltage (either input)(Note 1)....... Vttov- Operating Temperature Range ......... 0C to +70C Reference Input Voltage (either input)........... V+ toV Storage Temperature Range ........ -65C to +160C Clock Input... 6.60... cece eee eee TEST toVt Lead Temperature (Soldering, 60sec.) ........ +300C Note 1: Input voltages may exceed the supply voltages, provided the input current is limited to + 100uA. Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ote 3, 7) PARAMETER CONDITIONS MIN TYP MAX UNITS Zero Input Reading Vin = 0.0V 000.0 + 000.0 + 000.0 Digital Reading Full-Scale = 200.0mV Ratiometric Reading Vin = Vrer, Veer = 100mV 999 3999/1000 1000 Digital Reading Rotl-Over Error (Difference in Vin = + Vin = 200.0mV -1 +0.2 +1 Counts reading for equal positive and negative reading near full-scale) Linearity (Max. deviation from Full-Scale = 200mV -1 +0.02 +1 Counts best straight line fit) or Full-Scale = 2,.000V Common-Mode Rejection Ratio Vom = 1, Vin = OV 50 uViV {Note 4) Full-Scale = 200.0mV Noise (Pk-Pk value not exceeded Viy = OV, Full-Scale = 200.0mV 15 pV 95% of time) Leakage Current @ !nput Vin = OV 1 10 pA Zero Reading Drift Vin = OV, OC int REFLO 26 i - | osc aSCy asc, i 39738 cose [40 ! i MAXIM ICL7126 Rose TO ANALOG COMMON (P32! AM 580 ki! 50 pF FULL SCALE VREE INPUT 200.0 mV 100.0 mv Figure 1. Maxim I1CL7126 Typical Operating Circuit Clock Frequency 16kHz (1 reading/sec) Analog Section Figure 3 shows the Block Diagram of the Analog Section for the ICL7126. Each measurement cycle is divided into four phases: 1. Auto-Zero (A-Z) 2. Signal Integrate (INT) 3. Reference De-Integrate (Dl) 4. Zero Integrator (ZI) Auto-Zero Phase Three events occur during auto-zero. The inputs, IN-HI and IN-LO, are disconnected from the pins and internally shorted to analog common. The reference capacitor is charged to the reference voltage. And lastly, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the comparator, buffer amplifier and integrator. The inherent noise of the system determines the A-Z accuracy. Signal Integrate Phase The internal input high (IN-HI) and input low (IN-LO) are connected to the external pins, the internal short is re- moved and the auto-zero loop is opened. The converter then integrates the differential voltage between IN-HI and IN-LO for a fixed time. This differential voltage can be within a wide common-mode range (within one volt of either supply). If, however, the input signal has no return with respect to the converter power supply, IN-LO can be tied to analog common to establish the correct common- mode voltage. The polarity of the integrated signa! is de- termined at the end of this phase. ott LCD : | Display wf hy 33 Cher CREF t) } tM n af FL OW INH 2.19 | SEGMENT t ANALOG 9.01 uF 2225 a) - om INPUT - 327 no rope 2 BP 32] common 1 BUFF 240 180k ke + =sv | 29 F442 36 VREF i 0.047 uF ce 04 7uF AEF HI) fm 10:1 27 6 INT REF LO 26 loscy osc3 osc. MAXIAA 39 [38 cose [40 ICL7126 Bose ate TO ANALOG AW COMMON (P32) ~ SO pF 180 kW FULL SCALE VREF INPUT 200.0 mv 100.0 mv Figure 2. Maxim ICL7126 Typical Operating Circuit Clock Frequency 48kHz (3 readings/sec) Reference De-integrate IN-HI is connected across the previously charged refer- ence capacitor and IN-LO is internally connected to ana- log common. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The input signal determines the time required for the output to re- turn to zero. The digital reading displayed is: 1000 YIN. VREF Zero Integrator Phase Input low is shorted to analog COMMON and the refer- ence capacitor is charged to the reference voltage. A feedback loop is closed around the system to input high, causing the integrator output to return to zero. This phase normally lasts between 11 and 140 clock pulses but is extended to 740 clock pulses after a heavy over range conversion. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common-mode error is a roll-over voltage. This is caused by the reference capacitor losing or gaining charge to stray capacitance on its nodes. The reference capacitor can gain charge (increase voltage) if there is a large common-mode voltage. This is the result of a posi- tive signal de-integration. In contrast, the reference ca- pacitor will lose charge (decrease voltage) when de-inte- grating a negative input signal. Rollover error is caused by this difference in reference for positive or negative input voltages. This error can be held to less than half a count for the worst-case condition by selecting a refer- ence capacitor that is large enough in comparison to the stray capacitance. (See component value selection.) MAXAILVILow Power, 3% Digit A/D Converter COMPARATOR a a INTEGRATOR * REF HI maxim |? BR von ZENER on Tr js 1 priTat REFLO a ICL7126 | SECTION Ve MAXIM ly REE HI A ICL7126 REF LO is HEPERERCE comnn MAXIM " ICL7126 Figure 3. Analog Section ICL7126 Differential Input Differential voltages anywhere within the common- mode range of the input amplifier can be accepted by the input (specifically from 1V below the positive supply to 1.5V above the negative supply). The system has a CMRR of 86dB (typ) in this range. Care must be exercised, however, to ensure that the integrator output does not saturate, since the in- tegrator follows the common-mode voltage. A large positive common-mode voltage with a near full-scale negative differential input voltage is a worst-case condition. When most of the integrator output swing has been used up by the positive common-mode voltage, the negative input signal drives the inte- grator more positive. The integrator swing can bere- duced to less than the recommended 2V full-scale swing with no loss of accuracy in these critical appli- cations. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog Common The primary purpose of this pin is to set the common- mode voltage for battery operation. This is useful for any system where the input signals are floating with respect to the power supply. A voltage of approximately 2.8V less than the positive supply is set by this pin. The Analog Common has some of the attributes of a reference volt- age. If the total supply voltage is large enough to cause the zener to regulate (>7V), the common voltage will have a low output impedance (approximately 150), a temperature coefficient of typically 80 ppm/C and a low voltage coefficient (.001%). During auto-zero and reference integrate the internal in- put low is connected to Analog Common. If IN-LO is dif- ferent from Analog-Common, a common-mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. In some applications, however, IN-LO will be set at a fixed known voltage (e.g., power supply common). Whenever possible Analog Common should be tied to the same point, thus removing the com- mon-mode voltage from the converter. The same holds true for the reference voltage. If convenient, the refer- ence should be referenced to analog common as shown in Figure 4B. This will remove the common-mode voltage from the reference system. MIAXI/VI Figure 4. Using an External Reterence Analog common is internally tied to an N-channel FET that can sink 500 nA or more of current. This will hold the analog common voltage 2.8V below the positive supply (when a source is trying to pull the common line positive). There is only 1 A of source current, however, so com- mon may easily be tied to a more negative voltage, thus over-riding the internal reference. Test Two functions are performed by the test pin. The first is using this pin as the negative supply on the 7126. This is useful for externally generated segment drivers or any other annunciators the user may want to include on the LCD. This pin is coupled to the internally generated digi- tal supply through a 5002 resistor. This application is illustrated in Figures 5 & 6. A lamp test is the second function. All segments will be turned on and the display should read 1888, when TEST is pulled high (V +). Caution: In the lamp test mode, the segments have a constant de voltage (no square wave). This can burn the LCD (display) if left in this mode for several minutes. | woe ICL7126 Figure 6. Exclusive OR Gate for Decimal Point Drive 92ILZTOIICL7126 Low Power, 3% Digit A/D Converter ot op meyp (Eb | x TYPICQL SEGMER GUTPUT SEGRENT GJTPUT INTERNAL DIGITAL GROUND PsecMent~ P7stouent DECUDE DECane TO SWITCH DRIVERS FROM COMPAHAT OH GUTPUT ___4 or osc 1 }ac 39 38 cern CHYStaL OSC 2 Ose 3 cxtunvar og CSO ATOR TO TEST HN INTERNAL DIGITAL GROUND | v ra aie LOGIC CONTROL 37 PA 5 Vin Wo feo 7 | 20 v MAXIM 1CL7126 Figure 7 1CL7126 Digital Section .. .___..__. .______ Digital Section The digital section for the 1CL7126 is illustrated in Figure 7 In Figure 7, an internal digital ground is generated from a 6V zener diode and a large Pchannel source follower. This supply is made stiff in effort to absorb the large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is calculated by dividing the clock frequency by 800. For example, with a clock frequency of 48kHz (3 readings per second), the backplane will be a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude. Note that these are out-of-phase when the BP is On and in-phase when OFF. Negligible dc voltage exists across the segments in either case. The polarity indication is on for negative analog inputs, for the ICL7126. If desired IN-HI and IN-LO can be reversed giving a on for positive analog inputs. System Timing The clocking circuitry for the 1CL7126 is illustrated in Figure 7. Three approaches can be used: 1. Acrystal between pins 39 and 40. 2. An external oscillator connected to pin 40. 3. An RC oscillator using all three pins. The decade counters are driven by the clock freq uency which is divided by four. This frequency is then further divided to form the four convert-cycle phases, namely: signal integrate (1000 counts), reference de-integrate (0 to 2000 counts), auto-zero (260 to 2989 counts) and zero integrator (11 to 740). The signal integration should be a multiple of 60Hz to achieve a maximum rejection of 60Hz pickup. Os- cillator frequencies of 331/3kHz, 40kHz, 48kHz, 60kHz, 80khZ, 120kHz, 240kHz, etc., should be selected. Simi- larly, for SOHz rejection, oscillator frequencies of 200kHz, 100kHz, 662/skHz, 50kHz, 40kHz, etc., are appropriate. Note that 40kHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and 440Hz). Auto-zero receives the unused portion of reference deintegrate for signals less than full-scale. A complete measurement cycle is 4,000 counts (16,000) clock pulses), independent of input voltage. As an example, an oscillator frequency of 16kHz would be used to obtain one reading per second. MAKINLow Power, 3% Digit A/D Converter _____... Component Value Selection Auto-Zero Capacitor The noise of the system is influenced by the auto-zero capacitor. For a 2V scale, a 0.1uF capacitor is adequate. While the Maxim ICL7126 will operate with a 0.33uF capacitor, a 0.47uF capacitor is recommended for the 200mV full scale where noise rejection is very impor- tant. Due to the Z! phase, noise can be reduced by using a larger auto-zero capacitor without causing hysteresis or overrange hangover problems. Reference Capacitor For most applications, a 0.1uF capacitor is acceptable. However, a large value is needed to prevent roll over error where a large common-mode voltage exists {i.e., the REF-LO pin is not at analog common) anda 200mV scale is used. Generally, the roll over error will be held to half a count by using a 1.0uF capacitor. Integrating Capacitor To ensure that the integrator will not saturate (approxi- mately 0.3V from either supply), an appropriate integrat- ing capacitor must be selected. A nominal +2V full- scale integrator swing is acceptable when the analog common is used as a reference. The nominal value for CINT is 0.15uF at one reading per second. (16kHz clock). This value should be changed in inverse pro- portion to maintain the same output swing if a different oscillator frequency is used. The integrating capacitor must have low dielectric ab- sorption to minimize linearity errors. Polypropylene capacitors are recommended for this application. Integrating Resistor The integrator and the buffer amplifier both have a class A output stage with 6A of quiescent current and can supply 1A of drive current with negligible non- linearity. The integrating resistor should be large enough to keep the amplifiers in the linear region over the entire input voltage range. The resistor value, however, should be low enough that undue leakage requirements are not placed on the PC boards. Fora 200mV scale, a 180k resistor is recommended; (2V scale/1.8MEGQ). Reference Voltage An analog input voltage of Vin equal to 2 (VReF) is required to generate full scale output of 2000 counts. Thus, for 2V and 200mV scales, Vaer should equal 1V and 100mV respectively. However, there will exist a scale factor other than the unity between the input voltage and the digital reading in many applications where the A/D is connected to a transducer. As an example, the designer may like to have a full scale reading in a weighing system when the voltage from the transducer is 0.682V. The designer should use the input voltage directly and select Vref at 0.341V instead of dividing the input down to 200mvV. A suitable value of the integrating resistor would be 330k. This provides for a slightly quieter system and avoids a divider network on the input. Another advantage of this system occurs when the digital reading of zero is desired for Vin # zero. Examples are temperature and weighing systems with variable tare. By connecting the voltage transducer between Vin positive and common, and the variable (or fixed) offset voltage between common and Vin negative, the offset rating can be conveniently generated. Oscillator Components A 50pF capacitor is recommended for all ranges of frequency and the resistor is selected from the equa- tion f ~ 0.45/RC. For 48kHz clock (3 readings/second), R = 180kQ, for 16kHz, R = 560k. Typical Applications TO PIN 1 wo tH SET VREF OSC 1 180 ka OSC 2 1.000 Test PvP REF hi Pp / 240 kan REF LO P_ ANA AMA * c REF ae F 250ka CREF Ger COMMON [/}4 maxia INH P-J reL7126 = IN LO FF 010 HF, = Aqz 1.8 MO 4k, BUFF 5.01 uF INT +_| - 0.047 uF vy Oe 1MQ TO DISPLAY we UUUU 8p [- TO BACKPLANE 21 TO PIN 1 SET VREF 100.0 mv / kO 27kn +5V 1.2V MAXIM ICL7126 nes TO DISPLAY 10 BACKPLANE 21 Figure 8. Recommended Component Values for 2.000V Full-Scale, 3 Read- ings/Sec. For 1 reading/sec, change CINT, ROSC to values of Figure 1. MAXI/VI Figure 9. 7126 Operated from Single +5V Supply. An external reference must be used in this application. since the voltage between V and Vis insufficient for correct operation of the internal reference. 92IZTOIICL7126 Low Power, 3% Digit A/D Converter ve TO PIN 1 TO PIN 1 om 40 oa 40 osc 1 osc > OSC 2 OSC 2 p wr } SILICON NPN osc 3 Bstgr OSC 3 Pscarl MPS 3704 test A Test B | OR SIMILAR REF HI REF HI PY __aopen,, M2 | Sto0kn REF LO . rer Lo B NAS CREF CREF Pe 9 1p | 200k. 470 Ka ] a C REF t cRrer Par OTH WY AMA ty COMMON 2 COMMON 1} 5 INH s INH >_,_1 MAXIM N.C Epa dT INLC B 0.47nF rel76 he B Bata 9 gure F380 ka Konak . . ZEROS, Nt B-d m Bd ADJUST AXxXivE yO FS e2 ICL7126 Go A 3 e a t ALL (TO DISPLAY a ALB (70 DISPLAY S5 = S3p BP P}+ TO BACKPLANE BP [}> TO BACKPLANE _ Qt * Values depend on clock frequency. See Figure 1 & 2. * Values depend on clock frequency. See Figure 1 & 2. Figure 10. 7126 Measuring Ratiometric Values of Quad Load Cell. The Figure 11. 7126 used as a Digital Centigrade Thermometer. A silicon diode- resistor values within the bridge are determined by the desired sensitivity, connected transistor has a temperature coefficient of about -2mViC/. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. Chip Topography 1CL7126 D3 E> Fp Ay By Cy Dy fy G Fy 15 14:13:12 1110 9 6 J 6 0157 OSC: TEST REF HI REF LG a ae 26 27 28 29 30 3132 33 34 INT A? INH Cy. v BuR RO INLU | CUMNUK EC, Sai 0130 (3.3Umm) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _ SMAXAKISVI