UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
HIGH-SPEED PWM CONTROLLER
FEATURES
DImproved Versions of the UC3823/UC3825
PWMs
DCompatible with Voltage-Mode or
Current-Mode Control Methods
DPractical Operation at Switching Frequencies
to 1 MHz
D50-ns Propagation Delay to Output
DHigh-Current Dual Totem Pole Outputs
(2-A Peak)
DTrimmed Oscillator Discharge Current
DLow 100-μA Startup Current
DPulse-by-Pulse Current Limiting Comparator
DLatched Overcurrent Comparator With Full
Cycle Restart
DESCRIPTION
The UC3823A and UC3823B and the UC3825A and
UC3825B family of PWM controllers are improved
versions of the standard UC3823 and UC3825 family.
Performance enhancements have been made to several
of the circuit blocks. Error amplifier gain bandwidth product
is 12 MHz, while input offset voltage is 2 mV. Current limit
threshold is assured to a tolerance of 5%. Oscillator
discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%.
Startup supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to actively
sink current during UVLO at no expense to the startup
current specification. In addition each output is capable of
2-A peak currents during transitions.
BLOCK DIAGRAM
4
5
6
7
3
2
1
OSC
CLK/LEB
RT
CT
RAMP
EAOUT
NI
INV
8
9
15
SS
ILIM
VCC
1.25 V
10GND
(60%)
1.0 V
E/A
1.2 V
0.2 V
OVER CURRENT
CURRENT
LIMIT
R
SD
5 V
SOFT−START COMPLETE
R
SD
FAULT LATCH
RESTART
DELAY
T
13
11
14
VC
12
PWM
LATCH
9mA
250mA
R
S
*
RESTART
DELAY
LATCH
VREF
5.1 V
ON/OFF
UVLO
4 V
INTERNAL
BIAS
16
OUTA
OUTB
PGND
5.1 VREF
”B” 16V/10V
”A” 9.2V/8.4V
PWM COMPARATOR
UDG−02091
VREF GOOD
* On the UC1823A version, toggles Q and Q are always low.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright © 2004 −2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a
high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state.
In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the
functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A
and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A
and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current
limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions
have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.
Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for
detailed technical and applications information.
ORDERING INFORMATION
UVLO
TA
MAXIMUM 9.2 V / 8.4 V 16 V / 10 V
T
A
MAXIMUM
DUTY CYCLE SOIC−16(1)
(DW)
PDIP−16
(N)
PLCC−20(1)
(Q)
SOIC−16
(DW)
PDIP−16
(N)
PLCC−20(1)
(Q)
40°C to 85°C
< 100% UC2823ADW UC2823AN UC2823AQ UC2823BDW UC2823BN −
−40°C to 85°C< 50% UC2825ADW UC2825AN UC2825AQ UC2825BDW UC2825BN −
0°C to 70°C
< 100% UC3823ADW UC3823AN UC3823AQ UC3823BDW UC3823BN −
−0°C to 70°C< 50% UC3825ADW UC3825AN UC3825AQ UC3825BDW UC3825BN UC3825BQ
(1) The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000
devices per reel for the Q package and 2000 devices per reel for the DW package.
UVLO
TA
MAXIMUM 9.2 V / 8.4 V
T
A
MAXIMUM
DUTY CYCLE CDIP−16
(J)
LCCC−20
(L)
55°C to 125°C
< 100% UC1823AJ, UC1823AJ883B, UC1823AJQMLV UC1823AL, UC1823AL883B
−55°C to 125°C< 50% UC1825AJ, UC1825AJ883B, UC1825AJQMLV UC1825AL, UC1825AL883B, UC1825ALQMLV
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
DW, J, OR N PACKAGES
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
OUTB
VC
NC
PGND
OUTA
EAOUT
CLK/LEB
NC
RT
CT
Q OR L PACKAGES
(TOP VIEW)
NI
INV
NC
ILIM
GND
VREF
VCC
RAMP
SS
NC
NC = no connection
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
3
TERMINAL FUNCTIONS
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME J or DW Q or L
I/O
DESCRIPTION
CLK/LEB 4 5 O Output of the internal oscillator
CT 6 8 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should
be connected to the device ground using minimal trace length.
EAOUT 3 4 O Output of the error amplifier for compensation
GND 10 13 −Analog ground return pin
ILIM 9 12 I Input to the current limit comparator
INV 1 2 I Inverting input to the error amplifier
NI 2 3 I Non-inverting input to the error amplifier
OUTA 11 14 O High current totem pole output A of the on-chip drive stage.
OUTB 14 18 O High current totem pole output B of the on-chip drive stage.
PGND 12 15 −Ground return pin for the output driver stage
RAMP 7 9 I
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RT 5 7 I Timing resistor connection pin for oscillator frequency programming
SS 8 10 I Soft-start input pin which also doubles as the maximum duty cycle clamp.
VC 13 17 −Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor with minimal trace lengths.
VCC 15 19 −Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low
ESL capacitor with minimal trace lengths
VREF 16 20 O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor and minimal trace length to the ground plane.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
VIN Supply voltage, VC, VCC 22 V
IOSource or sink current, DC OUTA, OUTB 0.5 A
IOSource or sink current, pulse (0.5 μs) OUTA, OUTB 2.2 A
Analog inputs
INV, NI, RAMP −0.3 V to 7 V
Analog inputs ILIM, SS −0.3 V to 6 V
Power ground PGND ±0.2 V
Outputs OUTA, OUTB limits PGND −0.3 V to VC +0.3 V
ICLK Clock output current CLK/LEB −5 mA
IO(EA) Error amplifier output current EAOUT 5 mA
ISS Soft-start sink current SS 20 mA
IOSC Oscillator charging current RT −5 mA
TJOperating virtual junction temperature range −55°C to 150°C
Tstg Storage temperature −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds −55C°C to 150°C
tSTG Storage temperature −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds 300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
4
ELECTRICAL CHARACTERISTICS
TA = −55°C to 125°C for the UC1823A/UC1825A, TA = −40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x,
RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE, VREF
VOOuput voltage range TJ = 25°C, IO = 1 mA 5.05 5.1 5.15 V
Line regulation 12 V ≤ VCC ≤ 20 V 2 15
mV
Load regulation 1 mA ≤ IO ≤ 10 mA 5 20 mV
Total output variation Line, load, temperature 5.03 5.17 V
Temperature stability(1) T(min) < TA < T(max) 0.2 0.4 mV/°C
Output noise voltage(1) 10 Hz < f < 10 kHz 50 μVRMS
Long term stability(1) TJ = 125°C, 1000 hours 5 25 mV
Short circuit current VREF = 0 V 30 60 90 mA
OSCILLATOR
f
Initial accuracy(1)
TJ = 25°C 375 400 425 kHz
fOSC Initial accuracy(1)
RT = 6.6 kΩ, CT = 220 pF, TA = 25°C 0.9 1 1.1 MHz
Total variation(1)
Line, temperature 350 450 kHz
Total variation(1)
RT = 6.6 kΩ, CT = 220 pF, 0.85 1.15 MHz
Voltage stability 12 V < VCC < 20 V 1%
Temperature stability(1) T(min) < TA < T(max) +/−5%
High-level output voltage, clock 3.7 4
Low-level output voltage, clock 0 0.2
Ramp peak 2.6 2.8 3 V
Ramp valley 0.7 1 1.25
V
Ramp valley-to-peak 1.6 1.8 2
IOSC Oscillator discharge current RT = OPEN, VCT = 2 V 9 10 11 mA
ERROR AMPLIFIER
Input offset voltage 2 10 mV
Input bias current 0.6 3
A
Input offset current 0.1 1 μA
Open loop gain 1 V < VO < 4 V 60 95
CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 dB
PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110
dB
IO(sink) Output sink current VEAOUT = 1 V 1 2.5
mA
IO(src) Output source current VEAOUT = 4 V −1.3 −0.5 mA
High-level output voltage IEAOUT = −0.5 mA 4.5 4.7 5
V
Low-level output voltage IEAOUT = −1 mA 0 0.5 1 V
Gain bandwidth product f = 200 kHz 6 12 Mhz
Slew rate(1) 6 9 V/μs
(1) Ensured by design. Not production tested.
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
5
ELECTRICAL CHARACTERISTICS
TA = −55°C to 125°C for the UC1823A/UC1825A, TA = −40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x,
RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PWM COMPARATOR
IBIAS Bias current, RAMP VRAMP = 0 V −1−8μA
Minimum duty cycle 0%
Maximum duty cycle 85%
tLEB Leading edge blanking time RLEB = 2 kΩ, CLEB = 470 pF 300 375 450 ns
RLEB Leading edge blanking resistance VCLK/LEB = 3 V 8.5 10.0 11.5 kΩ
VZDC Zero dc threshold voltage, EAOUT VRAMP = 0 V 1.10 1.25 1.4 V
tDELAY Delay-to-output time(1) VEAOUT = 2.1 V, VILIM = 0 V to 2 V step 50 80 ns
CURRENT LIMIT / START SEQUENCE / FAULT
ISS Soft-start charge current VSS= 2.5 V 8 14 20 μA
VSS Full soft-start threshold voltage 4.3 5 V
IDSCH Restart discharge current VSS= 2.5 V 100 250 350 μA
ISS Restart threshold voltage 0.3 0.5 V
IBIAS ILIM bias current VILIM = 0 V to 2 V step 15 μA
ICL Current limit threshold voltage 0.95 1 1.05
V
Overcurrent threshold voltage 1.14 1.2 1.26 V
tdDelay-to-output time, ILIM(1) VILIM = 0 V to 2 V step 50 80 ns
OUTPUT
Low level output saturation voltage
IOUT = 20 mA 0.25 0.4
Low-level output saturation voltage IOUT = 200 mA 1.2 2.2
V
High level output saturation voltage
IOUT = 20 mA 1.9 2.9 V
High-level output saturation voltage IOUT = 200 mA 2 3
tr,
tfRise/fall time(1) CL = 1 nF 20 45 ns
UNDERVOLTAGE LOCKOUT (UVLO)
UC2823B, UC2825B, UC3825B, UC3825B 16 17
Start threshold voltage UC1823A, UC1825A, UC2823A, UC2825A
UC3825A, UC3825A 8.4 9.2 9.6
Stop threshold voltage UC2823B, UC2825B, UC3825B, UC3825B 9 10 V
OVLO h
y
steresis
UC1823A, UC1825A, UC2823A, UC2825A
UC3825A, UC3825A 0.4 0.8 1.2
V
OVLO hysteresis
UC2823B, UC2825B, UC3825B, UC3825B 5 6 7
SUPPLY CURRENT
Isu Startup current VC = VCC = VTH(start) − 0.5 V 100 300 μA
ICC Input current 28 36 mA
(1) Ensured by design. Not production tested.
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
6
APPLICATION INFORMATION
The oscillator of the UC3823A, UC3823B, UC3825A, and UC3825B is a saw tooth. The rising edge is governed by a current
controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for
the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based
on the desired frequency (RT) and DMAX. The design equations are:
RT+3V
(10 mA) ǒ1*DMAXǓCT+ǒ1.6 DMAXǓ
ǒRT fǓ
Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended.
UDG−95102
Figure 1. Oscillator
10 M
1 M
100 k
10 k
1 k 10 k 100 k
Figure 2
RT − Timing Resistance − W
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
f − Frequency − Hz
Figure 3
1 k 10 k
70
75
80
85
90
95
100
100 k
DMAX − Maximum Duty Cycle − %
RT − Timing Resistance − W
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
(1)
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
7
LEADING EDGE BLANKING
The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The
UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less
than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off.
Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.
On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM
comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse.
Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the
pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not
require any filtering as result of leading edge blanking.
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and
the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy,
an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%.
The design equation is:
tLEB +0.5 ǒRø10 kWǓ C
Values of R less than 2 kΩ should not be used.
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold,
the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults
without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this
reason, some noise filtering may be required on the ILIM pin.
UDG−95105
Figure 4. Leading Edge Blanking Operational Waveforms
(2)
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
8
UVLO, SOFT-START AND FAULT MANAGEMENT
Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier
output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output follows until closed
loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged
by a 250-μA current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At
this point the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not
discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions.
UDG−95106
Figure 5. Soft-Start and Fault Waveforms
ACTIVE LOW OUTPUTS DURING UVLO
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate.
Figure 6. Output Voltage vs Output Current
UDG−95108 UDG−95106
Figure 7. Output V and I During UVLO
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
9
CONTROL METHODS
UDG−95109
UDG−95110
Current Mode Voltage Mode
.
Figure 8. Control Methods
SYNCHRONIZATION
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free
running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width
should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin
can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming
synchronizing signal.
Figure 9. General Oscillator Synchronization
UDG−95111 UDG−95113
Figure 10. Two Unit Interface
UDG−95112
Figure 11. Operational Waveforms
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
10
HIGH CURRENT OUTPUTS
Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak current into a
capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC)
and power ground (PGND) pins help decouple the device’s analog circuitry from the high-power gate drive noise. The use
of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND
are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive
load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT
USE standard silicon diodes.
Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B devices. These
can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each output for a combined peak
current of 4 A.
UDG−95114
Figure 12. Power MOSFET Drive Circuit
GROUND PLANES
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the
chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents
associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can
be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high
di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high
frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection
for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode
to both VCC and PGND. Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low
ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be
bypassed to the signal ground plane.
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
11
UDG−95115
Figure 13. Ground Planes Diagram
OPEN LOOP TEST CIRCUIT
This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any
wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly
recommended.
UDG−95116
Figure 14. Open Loop Test Circuit Schematic
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC2823ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC2825ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3823ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3823BDWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3825ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3825BDWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2823ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC2825ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3823ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3823BDWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3825ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3825BDWTR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated