STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Arm(R) Cortex(R)-M7 32b MCU+FPU, 462DMIPS, up to 2MB Flash/ 512+16+4KB RAM, USB OTG HS/FS, 28 com IF, LCD, DSI Datasheet - production data Features * Core: Arm(R) 32-bit Cortex(R)-M7 CPU with DPFPU, ART AcceleratorTM and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. * Memories - Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write - SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories * Dual mode Quad-SPI * Graphics - Chrom-ART AcceleratorTM (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface - Hardware JPEG codec - LCD-TFT controller supporting up to XGA resolution - MIPI(R) DSI host controller supporting up to 720p 30 Hz resolution * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - Dedicated USB power - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration September 2017 This is information on a product in full production. &"'! LQFP100 (14 x 14 mm) UFBGA176 (10 x 10 mm) WLCSP180 LQFP144 (20 x 20 mm) (0.4 mm pitch) LQFP176 (24 x 24 mm) TFBGA216 (13 x 13 mm) TFBGA100 (8 x 8 mm) LQFP208 (28 x 28 mm) * Low-power - Sleep, Stop and Standby modes - VBAT supply for RTC, 32x32 bit backup registers + 4 Kbytes backup SRAM * 3x12-bit, 2.4 MSPS ADC: up to 24 channels * Digital filters for sigma delta modulator (DFSDM), 8 channels / 4 filters * 2x12-bit D/A converters * General-purpose DMA: 16-stream DMA controller with FIFOs and burst support * Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer * Debug mode - SWD & JTAG interfaces - Cortex(R)-M7 Trace MacrocellTM * Up to 168 I/O ports with interrupt capability - Up to 164 fast I/Os up to 108 MHz - Up to 166 5 V-tolerant I/Os DocID029041 Rev 6 1/255 www.st.com STM32F765xx STM32F767xx STM32F768Ax STM32F769xx * Up to 28 communication interfaces - Up to 4 I2C interfaces (SMBus/PMBus) - Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) - Up to 6 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2S for audio - 2 x SAIs (serial audio interface) - 3 x CANs (2.0B Active) and 2x SDMMCs - SPDIFRX interface - HDMI-CEC - MDIO slave interface * Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII * 8- to 14-bit camera interface up to 54 Mbyte/s * True random number generator * CRC calculation unit * RTC: subsecond accuracy, hardware calendar * 96-bit unique ID Table 1. Device summary Reference Part number STM32F765xx STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG STM32F767xx STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI STM32F768Ax STM32F768AI STM32F769xx STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, STM32F769NG, STM32F769NI 2/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Arm(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21 2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.11 Chrom-ART AcceleratorTM (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25 2.13 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.19 2.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35 2.20 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35 2.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID029041 Rev 6 3/255 6 Contents STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 42 2.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 43 2.27 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.28 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.30 Audio and LCD PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.31 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 45 2.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 45 2.33 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 46 2.35 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 46 2.36 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 48 2.39 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.40 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.41 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.42 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 49 2.43 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.44 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.45 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.46 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.47 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5 Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 115 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 115 5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 115 5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 145 5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 156 5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DocID029041 Rev 6 5/255 6 Contents 6 7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 213 5.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 214 5.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 216 5.3.35 DFSDM timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 219 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1 LQFP100 14x 14 mm, low-profile quad flat package information . . . . . . 221 6.2 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.3 LQFP144 20 x 20 mm, low-profile quad flat package information . . . . . 228 6.4 LQFP176 24 x 24 mm, low-profile quad flat package information . . . . . 232 6.5 LQFP208 28 x 28 mm low-profile quad flat package information . . . . . . 236 6.6 WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.7 UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 6.8 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 252 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 6/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 114 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 115 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 115 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode), regulator ON . . . . . . . . . . . . . . . . . . . . . 122 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Typical and maximum current consumption in Run mode, code with data processing DocID029041 Rev 6 7/255 10 List of tables Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. 8/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 126 Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 127 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 127 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 128 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 129 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory programming (dual bank configuration nDBANK=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 168 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 168 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 189 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 190 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 194 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 198 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 203 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 DFSDM measured timing 1.71-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 220 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 220 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 222 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 128. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 227 DocID029041 Rev 6 9/255 10 List of tables STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 131. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 132. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 133. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 134. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 245 Table 136. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 137. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 248 Table 138. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Table 139. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 140. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 252 Table 141. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 10/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx block diagram . . . . 19 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 34 STM32F76xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32F76xxx TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32F76xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32F76xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32F769xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32F769Ax/STM32F768Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32F76xxx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32F769xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32F76xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32F76xxx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32F769xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 150 MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 150 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 170 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 170 DocID029041 Rev 6 11/255 13 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. 12/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 186 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 192 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 194 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 197 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 203 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 207 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 207 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 221 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 TFBGA100, 8 x 8 x 0.8mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 228 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. List of figures LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 232 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 236 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 DocID029041 Rev 6 13/255 13 Description 1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are based on the high-performance Arm(R) Cortex(R)-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex(R)-M7 core features a floating point unit (FPU) which supports Arm(R) double-precision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices incorporate high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces: * Up to four I2Cs * Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. * Four USARTs plus four UARTs * An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI) * Three CANs * Two SAI serial audio interfaces * Two SDMMC host interfaces * Ethernet and camera interfaces * LCD-TFT display controller * Chrom-ART AcceleratorTM * SPDIFRX interface * HDMI-CEC Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices operate in the -40 to +105 C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices offer devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. 14/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description These features make the STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances * Mobile applications, Internet of Things * Wearable devices: smartwatches The following table lists the peripherals available on each part number. DocID029041 Rev 6 15/255 53 STM32F 765Vx Peripherals Flash memory in Kbytes SRAM in Kbytes 1024 2048 STM32F767 /769Vx 1024 STM32F 765Zx STM32F767 /769Zx STM32F 769Ax 2048 1024 2048 1024 2048 1024 2048 Instruction 16 Backup 4 STM32F767 /769Bx STM32F 765Nx 1024 2048 STM32F767 /769Nx 1024 2048 Yes Yes No Yes 10 Advancedcontrol 2 Basic 2 Low-power 1 SPI / I2S Yes 4/3 (simplex)(2) 6/3 (simplex)(2) I2C 4 USART/UART 4/4 USB OTG FS Yes USB OTG HS Yes CAN 3 SAI 2 SPDIFRX 4 inputs SDMMC1 Yes SDMMC2 Yes(3) Camera interface Yes Host(4) No No Yes Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DocID029041 Rev 6 Generalpurpose Random number generator LCD-TFT STM32F 765Bx Yes(1) Ethernet MIPI-DSI STM32F767 /769Ix 1024 2048 1024 2048 1024 2048 1024 2048 512(368+16+128) Quad-SPI Communication interfaces 2048 STM32F 765Ix System FMC memory controller Timers STM32F 768Ax Description 16/255 Table 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts Peripherals STM32F 765Vx STM32F767 /769Vx STM32F 765Zx STM32F767 /769Zx STM32F 769Ax STM32F 768Ax Chrom-ART AcceleratorTM (DMA2D) JPEG codec GPIOs No Yes No 82 Yes 114 129 STM32F 765Bx STM32F767 /769Bx STM32F 765Nx STM32F767 /769Nx No Yes No Yes No Yes 140 132 168 159 168 159 Yes (4 filters) 12-bit ADC 3 16 24 Yes 2 12-bit DAC Number of channels 216 MHz(5) Maximum CPU frequency DocID029041 Rev 6 1.7 to 3.6 V(6) Operating voltage Ambient temperatures: -40 to +85 C /-40 to +105 C Operating temperatures Package STM32F767 /769Ix Yes DFSDM1 Number of channels STM32F 765Ix Junction temperature: -40 to + 125 C LQFP100 TFBGA100 LQFP144 WLCSP180 UFBGA176(7) LQFP176 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. LQFP208 TFBGA216 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts (continued) 3. SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 4. DSI host interface is only available on STM32F769x sales types. 5. 216 MHz maximum frequency for - 40C to + 85C ambient temperature range (200 MHz maximum frequency for - 40C to + 105C ambient temperature range). 6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF). 7. UFBGA176 is not available for STM32F769x sales types. Description 17/255 Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Full compatibility throughout the family The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package 3& 9'' 966$ 95() 9''$ 3$:.83 3$ 3$ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 9'' 3% 9&$3 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3& 3% 3& 3$ 3$ 3$ 3$ 9'' 3$ 3& 966$ 95() 9''$ 3$:.83 3$ 3$ 3$ 966 670)[[[ 3LQVWRDUHQRWFRPSDWLEOH 9'' 966 9&$3 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3% 3& 3& 3$ 3$ 3$ 3$ 9'' 966 06Y9 The STM32F76x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are fully pin to pin compatible with STM32F4xx devices. 18/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description Figure 2. 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The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID029041 Rev 6 19/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2 Functional overview 2.1 Arm(R) Cortex(R)-M7 with FPU The Arm(R) Cortex(R)-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering an outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: - Six-stage dual-issue pipeline - Dynamic branch prediction - Harvard caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) - 64-bit AXI4 interface - 64-bit ITCM interface - 2x32-bit DTCM interfaces The processor supports the following memory interfaces: * Tightly Coupled Memory (TCM) interface. * Harvard instruction and data caches and AXI master (AXIM) interface. * Dedicated low-latency AHB-Lite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow an efficient signal processing and a complex algorithm execution. It supports single and double precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 2 shows the general block diagram of the STM32F76xxx family. Note: The Cortex(R)-M7 with FPU core is binary compatible with the Cortex(R)-M4 core. 2.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 20/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.3 Functional overview Embedded Flash memory The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. The Flash interface features: 2.4 * Single /or Dual bank operating modes, * Read-While-Write (RWW) in Dual bank mode. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.5 Embedded SRAM All the devices feature: * * System SRAM up to 512 Kbytes: - SRAM1 on AHB bus Matrix: 368 Kbytes - SRAM2 on AHB bus Matrix: 16 Kbytes - DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 128 Kbytes for critical real-time data. Instruction RAM (ITCM-RAM) 16 Kbytes: - It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines. The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. * 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. DocID029041 Rev 6 21/255 53 Functional overview 2.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx AXI-AHB bus matrix The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx system architecture is based on 2 sub-systems: * An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol: * - 3x AXI to 32-bit AHB bridges connected to AHB bus matrix - 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory A multi-AHB Bus-Matrix - The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. ,^ D ZZd Z D >d&dD h^,^D DW d,ZEdD ,W y/D .% ,'&DFKH 'W D h^Kd' >d&d D ,^ DDD DW/ ZD 'W D DDD /dD dD Figure 3. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB bus matrix architecture(1) dDZD < /dDZD < y/Z , Zd /dD , &>^, D ^D ^ZD < ^ZD < , W , &D D W W Y^W/ D^ 06Y9 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. 22/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.7 Functional overview DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and the transfer sizes between the source and the destination are independent. The DMA can be used with the main peripherals: * SPI and I2S * I2C * USART * General-purpose, basic and advanced-control timers TIMx * DAC * SDMMC * Camera interface (DCMI) * ADC * SAI * SPDIFRX * Quad-SPI * HDMI-CEC * JPEG codec * DFSDM1 DocID029041 Rev 6 23/255 53 Functional overview 2.8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: * The NOR/PSRAM memory controller * The NAND/memory controller * The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: * Interface with static-memory mapped devices including: - Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data * Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories * 8-,16-,32-bit data bus width * Independent Chip Select control for each memory bank * Independent configuration for each memory bank * Write FIFO * Read FIFO for SDRAM controller * The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.9 Quad-SPI memory interface (QUADSPI) All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: * Direct mode through registers * External Flash status register polling mode * Memory mapped mode. Up to 256 Mbytes external Flash are memory mapped, supporting 8, 16 and 32-bit access. Code execution is supported. The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate. 24/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.10 Functional overview LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 2.11 * 2 display layers with dedicated FIFO (64x32-bit) * Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer * Up to 8 input color formats selectable per layer * Flexible blending between two layers using alpha value (per pixel or constant) * Flexible programmable parameters for each layer * Color keying (transparency color) * Up to 4 programmable interrupt events Chrom-ART AcceleratorTM (DMA2D) The Chrom-Art AcceleratorTM (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: * Rectangle filling with a fixed color * Rectangle copy * Rectangle copy with pixel format conversion * Rectangle composition with blending and pixel format conversion Various image format codings are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 2.12 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)M7 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. DocID029041 Rev 6 25/255 53 Functional overview 2.13 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx JPEG codec (JPEG) The JPEG codec provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers. The JPEG codec main features: 2.14 * 8-bit/channel pixel depths * Single clock per pixel encoding and decoding * Support for JPEG header generation and parsing * Up to four programmable quantization tables * Fully programmable Huffman tables (two AC and two DC) * Fully programmable minimum coded unit (MCU) * Encode/decode support (non simultaneous) * Single clock Huffman coding and decoding * Two-channel interface: Pixel/Compress In, Pixel/Compressed Out * Stallable design * Support for single, greyscale component * Functionality to enable/disable header processing * Internal register interface * Fully synchronous design * Configured for high-speed decode mode External interrupt/event controller (EXTI) The external interrupt/event controller consists of 25 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines. 2.15 Clocks and startup On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. 26/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.16 Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: * All Flash address space mapped on ITCM or AXIM interface * All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface * The System memory bootloader The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to STM32 microcontroller system memory boot mode application note (AN2606) for details. 2.17 Note: Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. * * VDDSDMMC can be connected either to VDD or an external independent power supply (1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected: - During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - The VDDSDMMC rising and falling time rate specifications must be respected - In operating mode phase, VDDSDMMC could be lower or higher than VDD: All associated GPIOs powered by VDDSDMMC are operating between VDDSDMMC_MIN and VDDSDMMC_MAX. VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to DocID029041 Rev 6 27/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx disappear. The following conditions VDDUSB must be respected: - During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - The VDDUSB rising and falling time rate specifications must be respected (see Table 20 and Table 21) - In operating mode phase, VDDUSB could be lower or higher than VDD: - If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. - If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 4. VDDUSB connected to VDD power supply 9'' 9''B0$; 9'' 9''$ 9''86% 9''B0,1 3RZHURQ 2SHUDWLQJPRGH 3RZHUGRZQ WLPH 069 28/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 5. VDDUSB connected to external power supply 9''86%B0$; 86% IXQFWLRQDODUHD 9''86% 9''86%B0,1 86%QRQ IXQFWLRQDO DUHD 9'' 9''$ 86% QRQ IXQFWLRQDO DUHD 9''B0,1 2SHUDWLQJPRGH 3RZHURQ WLPH 3RZHUGRZQ 069 The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins: * VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY. This supply must be connected to global VDD. * The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally to VDD12DSI. * The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin. * The VSSDSI pin is an isolated supply ground used for DSI sub-system. * If the DSI functionality is not used at all, then: - The VDDDSI pin must be connected to global VDD. - The VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed. - The VSSDSI pin must be grounded. 2.18 Power supply supervisor 2.18.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through DocID029041 Rev 6 29/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 2.18.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF. Figure 6. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 1567 9'' $SSOLFDWLRQUHVHW VLJQDO 3'5B21 966 069 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 7). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD. All the packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. 30/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 2.19 Voltage regulator The regulator has four operating modes: * * 2.19.1 Regulator ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: * MR mode used in Run/sleep modes or in Stop modes - In Run/Sleep modes The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. - In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). DocID029041 Rev 6 31/255 53 Functional overview * STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: * - LPR operates in normal mode (default mode when LPR is ON) - LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. `-' means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 2.19.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In the regulator OFF mode, the following features are no more supported: 32/255 * PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. * As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. * The over-drive and under-drive modes are not available. * The Standby mode is not available. DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 8. Regulator OFF 9 ([WHUQDO9&$3BSRZHU $SSOLFDWLRQUHVHW VXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYH VLJQDORSWLRQDO ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL9 The following conditions must be respected: Note: * VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. * If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). * Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). * If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application. DocID029041 Rev 6 33/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization 9'' 3'5 RU9 9 0LQ9 9&$3B9&$3B WLPH 1567 3$ WLPH DLJ 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization 9'' 3'5 9RU9 9&$3B9&$3B 9 0LQ9 1567 WLPH 3$DVVHUWHGH[WHUQDOO\ WLPH DLH 1. This figure is valid whatever the internal reset mode (ON or OFF). 34/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.19.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF LQFP100 LQFP144, LQFP208 LQFP176, UFBGA176, TFBGA100, TFBGA216 WLCSP180 Yes Internal reset ON Internal reset OFF Yes No No Yes Yes Yes Yes BYPASS_REG set BYPASS_REG set PDR_ON set to VDD PDR_ON set to VSS to VDD to VSS Yes(1) 1. Available only on dedicated part number. Refer to Section 7: Ordering information. 2.20 Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. * Two programmable alarms. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. * 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. DocID029041 Rev 6 35/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx The RTC clock sources can be: * A 32.768 kHz external crystal (LSE) * An external resonator or oscillator(LSE) * The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) * The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.21 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): - Normal mode (default mode when MR or LPR is enabled) - Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and LPTIM1 asynchronous interrupt). Table 5. Voltage regulator modes in stop mode * Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering 36/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs. The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 2.22 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and the VBAT pin should be connected to VDD. 2.23 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. DocID029041 Rev 6 37/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 6. Timer feature comparison Max Max DMA Capture/ Complem interface timer request compare entary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Counter Counter Prescaler resolution type factor Advanced -control TIM1, TIM8 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 108 216 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Up Any integer between 1 and 65536 No 2 No 108 216 Up Any integer between 1 and 65536 No 1 No 108 216 Up Any integer between 1 and 65536 No 2 No 54 108/216 Up Any integer between 1 and 65536 No 1 No 54 108/216 Up Any integer between 1 and 65536 Yes 0 No 54 108/216 TIM2, TIM5 TIM3, TIM4 TIM9 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 38/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.23.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 2.23.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F76xxx devices (see Table 6 for differences). * TIM2, TIM3, TIM4, TIM5 The STM32F76xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 2.23.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. DocID029041 Rev 6 39/255 53 Functional overview 2.23.4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 2.23.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / one-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 2.23.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 2.23.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 40/255 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.24 Functional overview Inter-integrated circuit interface (I2C) The devices embed 4 I2C. Refer to table Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * I2C-bus specification and user manual rev. 5 compatibility: - Slave and master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Programmable analog and digital noise filters * 1-byte buffer with DMA capability Table 7. I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X 1. X: supported. DocID029041 Rev 6 41/255 53 Functional overview 2.25 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Universal synchronous/asynchronous receiver transmitters (USART) The devices embed USART. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART peripheral supports: * Full-duplex asynchronous communications * Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance * Dual clock domain allowing convenient baud rate programming independent from the PCLK reprogramming * A common programmable transmit and receive baud rate of up to 27 Mbit/s when the USART clock source is system clock frequency (max is 216 MHz) and oversampling by 8 is used. * Auto baud rate detection * Programmable data word length (7 or 8 or 9 bits) word length * Programmable data order with MSB-first or LSB-first shifting * Programmable parity (odd, even, no parity) * Configurable stop bits (1 or 1.5 or 2 stop bits) * Synchronous mode and clock output for synchronous communications * Single-wire half-duplex communications * Separate signal polarity control for transmission and reception * Swappable Tx/Rx pin configuration * Hardware flow control for modem and RS-485 transceiver * Multiprocessor communications * LIN master synchronous break send capability and LIN slave break detection capability * IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode * Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard ) * Support for Modbus communication Table 8 summarizes the implementation of all U(S)ARTs instances Table 8. USART implementation features(1) USART1/2/3/6 Data Length 42/255 UART4/5/7/8 7, 8 and 9 bits Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X - DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 2.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 54 Mbits/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.27 Serial audio interface (SAI) The devices embed two serial audio interfaces. The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC'97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. DocID029041 Rev 6 43/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SAI1 and SAI2 can be served by the DMA controller 2.28 SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main features of the SPDIFRX are the following: * Up to 4 inputs available * Automatic symbol rate detection * Maximum symbol rate: 12.288 MHz * Stereo stream from 32 to 192 kHz supported * Supports Audio IEC-60958 and IEC-61937, consumer applications * Parity bit management * Communication using DMA for audio samples * Communication using DMA for control and user channel information * Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 2.29 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 2.30 Audio and LCD PLL (PLLSAI) An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock. 44/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.31 Functional overview SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support the MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous. The SDMMC can be served by the DMA controller 2.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: * Supports 10 and 100 Mbit/s rates * Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors * Tagged MAC frame support (VLAN support) * Half-duplex (CSMA/CD) and full-duplex operation * MAC control sublayer (control frames) support * 32-bit CRC generation and removal * Several address filtering modes for physical and multicast address (multicast and group addresses) * 32-bit status code for each transmitted or received frame * Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. * Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input * Triggers interrupt when system time becomes greater than target time DocID029041 Rev 6 45/255 53 Functional overview 2.33 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Controller area network (bxCAN) The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2. 512 bytes of SRAM are dedicated for CAN3. 2.34 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: * Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints * 12 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Battery Charging Specification Revision 1.2 support * Internal FS OTG PHY support * HNP/SNP/IP inside (no need for any external resistor) For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.35 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed a USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 46/255 * Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 8 bidirectional endpoints * 16 host channels with periodic OUT support DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.36 Functional overview * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Battery Charging Specification Revision 1.2 support * Internal FS OTG PHY support * External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * for OTG/Host modes, a power switch is needed in case bus-powered devices are connected High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 2.37 Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbytes/s in 8-bit mode at 54 MHz. It features: * Programmable polarity for the input pixel clock and synchronization signals * Parallel data communication can be 8-, 10-, 12- or 14-bit * Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) * Supports continuous mode or snapshot (a single frame) mode * Capability to automatically crop the image DocID029041 Rev 6 47/255 53 Functional overview 2.38 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Management Data Input/Output (MDIO) slaves The devices embed a MDIO slave interface it includes the following features: * - 32 x 16-bit firmware read/write, MDIO read-only output data registers - 32 x 16-bit firmware read-only, MDIO write-only input data registers * Configurable slave (port) address * Independently maskable interrupts/events: * 2.39 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: - MDIO Register write - MDIO Register read - MDIO protocol error Able to operate in and wake up from STOP mode Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.40 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. A fast I/O handling allows a maximum I/O toggling up to 108 MHz. 2.41 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 48/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.42 Functional overview Digital filter for Sigma-Delta Modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface formats (to support various modulators). The DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: * * 8 multiplexed input digital serial channels: - Configurable SPI interface to connect various SD modulator(s) - Configurable Manchester coded 1 wire interface support - PDM (Pulse Density Modulation) microphone input support - Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - Clock output for SD modulator(s): 0..20 MHz Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): - * internal sources: device memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: - Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024) - integrator: oversampling ratio (1..256) * Up to 24-bit output data resolution, signed output data format * Automatic data offset correction (offset stored in register by user) * Continuous or single conversion * Start-of-conversion triggered by: * * - Software trigger - Internal timers - External events - Start-of-conversion synchronously with first digital filter module (DFSDM0) Analog watchdog feature: - Low value and high value data threshold registers - Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) - Input from final output data or from selected input digital serial channels - Continuous monitoring independently from standard conversion Short circuit detector to detect saturated analog input values (bottom and top range): - Up to 8-bit counter to detect 1..256 consecutive 0's or 1's on serial data stream - Monitoring continuously each input serial channel * Break signal generation on analog watchdog event or on short circuit detector event * Extremes detector: - Storage of minimum and maximum values of final conversion data DocID029041 Rev 6 49/255 53 Functional overview - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Refreshed by software * DMA capability to read the final conversion data * Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence * "regular" or "injected" conversions: - "regular" conversions can be requested at any time or even in continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority Table 9. DFSDM implementation DFSDM features Number of filters: x (DFSDM_FLTx) 4 Number of input transceivers/channels: y (DFSDM_CHy) 8 Internal ADC parallel input support - Number of external triggers (JEXTSEL size) ID register support 50/255 DFSDM1 32 - DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.43 Functional overview Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.44 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * Two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channel independent or simultaneous conversions * DMA capability for each channel * External triggers for conversion * Input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.45 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.46 Embedded Trace MacrocellTM The Arm embedded trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F76xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or DocID029041 Rev 6 51/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 2.47 DSI Host (DSIHOST) The DSI Host is a dedicated peripheral for interfacing with MIPI(R) DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. These interfaces are as follows: * * * LTDC interface: - Used to transmit information in Video mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI). - Through a customized for mode, this interface can be used to transmit information in full bandwidth in the Adapted Command mode (DBI). APB slave interface: - Allows the transmission of generic information in Command mode, and follows a proprietary register interface. - Can operate concurrently with either LTDC interface in either Video mode or Adapted Command mode. Video mode pattern generator: - Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli. The DSI Host main features: * Compliant with MIPI(R) Alliance standards * Interface with MIPI(R) D-PHY * Supports all commands defined in the MIPI(R) Alliance specification for DCS: Transmission of all Command mode packets through the APB interface - Transmission of commands in low-power and high-speed during Video mode * Supports up to two D-PHY data lanes * Bidirectional communication and escape mode support through data lane 0 * Supports non-continuous clock in D-PHY clock lane for additional power saving * Supports Ultra Low-power mode with PLL disabled * ECC and Checksum capabilities * Support for End of Transmission Packet (EoTp) * Fault recovery schemes * 3D transmission support * Configurable selection of system interfaces: * 52/255 - - AMBA APB for control and optional support for Generic and DCS commands - Video Mode interface through LTDC - Adapted Command mode interface through LTDC Independently programmable Virtual Channel ID in DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx - Video mode - Adapted Command mode - APB Slave Functional overview Video Mode interfaces features: * LTDC interface color coding mappings into 24-bit interface: - 16-bit RGB, configurations 1, 2, and 3 - 18-bit RGB, configurations 1 and 2 - 24-bit RGB * Programmable polarity of all LTDC interface signals * Maximum resolution is limited by available DSI physical link bandwidth: - Number of lanes: 2 - Maximum speed per lane: 500 Mbps1Gbps Adapted interface features Support for sending large amounts of data through the memory_write_start(WMS) and memory_write_continue(WMC) DCS commands * LTDC interface color coding mappings into 24-bit interface: - 16-bit RGB, configurations 1, 2, and 3 - 18-bit RGB, configurations 1 and 2 - 24-bit RGB Video mode pattern generator: * Vertical and horizontal color bar generation without LTDC stimuli * BER pattern without LTDC stimuli DocID029041 Rev 6 53/255 53 Pinouts and pin description 3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description s s^^ W W W W KKd W W W W W W W W W W W W W W W W W W Figure 11. STM32F76xxx LQFP100 pinout /4)3 s s^^ sW W W W W W W W W W W W W W W W W W W W W W W s^^ s W W W W W W W W W W W W W W W W W W W W sW s^^ s W W W W W sd WEd/dDW WK^/E WK^Khd s^^ s W,K^/E W,K^Khd EZ^d W W W W s^^ sZ& s Wt<hW W W W 06Y9 1. The above figure shows the package top view. 54/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 12. STM32F76xxx TFBGA100 pinout $ 3& 3& 3( % 3& 9%$7 & 3+ 3% 3% 3% 3% 3$ 3$ 3$ 3( 3% 3% 3' 3' 3& 3& 3$ 966 3( 3( 3% 3' 3' 3& 3$ 3$ 3+ 9'' 3( 3( %227 3' 3' 3' 3$ 3$ 1567 3& 3( 966 966 %<3$66 5(* 9&$3B 3' 3& 3& 3& 3& 3& 9'' 9'' 9''86% 3'5B21 9&$3B 3& 3& 966$ 3$ 3$ 3& 3% 3( 3( 3' 3' 3% + 9''$ 3$ 3$ 3& 3( 3( 3( 3' 3' 3% - 966 3$ 3$ 3% 3( 3( 3% 3% 3' 3' . 9'' 3$ 3$ 3% 3( 3( 3% 3% 3' 3' ' ( ) * 06Y9 1. The above figure shows the package top view. DocID029041 Rev 6 55/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13. STM32F76xxx LQFP144 pinout /4)3 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$53" 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 069 1. The above figure shows the package top view. 56/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 14. STM32F76xxx LQFP176 pinout /4)3ZLWKRXW'6, 0) 0) 0( 0( 0( 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$53" 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6$$ 633 0( 6#!0? 6$$ 0( 0( 0( 0( 0( 0( 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0( 0( 0! "90!33?2%' 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0# 0) 0) 0) 633 6$$ 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0( 0( -36 1. The above figure shows the package top view. DocID029041 Rev 6 57/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 15. STM32F769xx LQFP176 pinout /4)3ZLWK'6, 0) 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$53" 633 0' 0' 0' 0' 0' 0' 0' 633$3) $3)?$. $3)?$0 6$$$3) $3)?#+. $3)?#+0 633$3) $3)?$. $3)?$0 6#!0$3) 6$$$3) 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 6#!0? 6$$ 0( 0( 0" 0" 0" 0" 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0( 0( 0! "90!33?2%' 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0# 0) 0) 0) 633 6$$ 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0( 0( -36 1. The above figure shows the package top view. 58/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 16. STM32F769Ax/STM32F768Ax WLCSP180 ballout $ 1& 1& 3$-7&. 6:&/. 3' 3' 9''00& 3* 966 3% %227 966 1& 1& % 1& 9'' 3, 3& 3' 966 3* 9'' 3% 3( 9'' 3, 1& & 9&$3B 966 3, 3& 3' 3* 3* 3% 3( 3'5B21 3, 3( 9%$7 ' 3$ 3$-706 6:',2 3, 3& 3' 3' 3* 3%17567 3% 3, 3, 3( 3& ( 3& 3$ 3$ 3, 3+ 3' 3' 3%-7'2 75$&(6:2 3% 3( 3( 3& 26& B,1 3& 26&B 287 ) 966 9''86% 3& 3$ 3$ 3+ 3+ 3$-7', 3* 3( 3, 9'' 966 * 3* 3* 3* 3* 3* 3& 3& 3* 3, 3) 3) 3) + '6,B'3 '6,B'1 '6,B&.1 '6,B&.3 966'6, 9&$3'6, 3% 3* 3, 3) 3) 3) - '6,B'3 '6,B'1 9'''6, 3' 3% 3( 3% 3% 966 3$ 3$ 9'' 966 . 9'''6, 3' 3' 3+ 3% 3( 3) 3) 9'' 3+ 3) 3+ 26&B,1 3+ 26&B287 / 3' 3' 3' 3+ 3% 3( 3* 3) 3$ 3+ 1567 3& 3& 0 966 3' 3' 3+ 3+ 3( 3( 9'' 3$ 3$ 966$ 9''$ 3$:.83 1 1& 3% 3% 966 966 3( 3( 3* 3) 3$ 3+ 3+ 1& 3 1& 1& 3+ 9'' 9&$3B 3( 3( 3) 966 3% 3$ 1& 1& 06Y9 1. NC ball must not be connected to GND nor to VDD. 2. The above figure shows the package top view. DocID029041 Rev 6 59/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx >Y&W W/ W/ W/ W, W, W, s s^^ sW W W W W W W W W W W sh^ s^^ W' W' W' W' W' W' W' W< W< W< s^^ s W: W: W: W: W: W: W W s s^^ W W W W W W W W W W W W W W W s s^^ W W W W/ W: W: W: W: W: W& W& s^^ s W& W& W& W' W' W W W s^^ s W W W W W W W W sW s^^ s W: W, W, W, W, W, W, W, s W W W W W W sd W/ W W W W/ W/ W/ s^^ s W& W& W& W/ W/ W/ W& W& W& s^^ s W& W& W& W& W& W, W, EZ^d W W W W s s^^ sZ& s W W W W, W, W, W, W s^^ s W/ W/ W/ W/ s WZKE s^^ W W W W KKd W W W W W W' W< W< W< W< W< s s^^ W' W' W' W' W' W' W: W: W: W: W W s^DD s^^ W W W W W W W W W W W s W/ Figure 17. STM32F76xxx LQFP208 pinout 1. The above figure shows the package top view. 60/255 DocID029041 Rev 6 06Y9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description /4)3ZLWK'6, W/ W/ W/ W, W, W, s s^^ sW W W W W W W W W W W sh^ s^^ W' W' W' W' W' W' W' s^^^/ ^/E ^/W s^/ ^/<E ^/<W s^^^/ ^/E ^/W sW^/ s^/ W W s s^^ W W W W W W W W W W W W W W W s s^^ W W W W/ W: W: W: W: W: W& W& s^^ s W& W& W& W' W' W W W s^^ s W W W W W W W W sW s^^ s W: W, W, W, W, W, W, W, s W W W W W W sd W/ W W W W/ W/ W/ s^^ s W& W& W& W/ W/ W/ W& W& W& s^^ s W& W& W& W& W& W, W, EZ^d W W W W s s^^ sZ& s W W W W, W, W, W, W s^^ s W/ W/ W/ W/ s WZKE s^^ W W W W KKd W W W W W W' W< W< W< W< W< s s^^ W' W' W' W' W' W' W: W: W: W: W W s^DD s^^ W W W W W W W W W W W s W/ Figure 18. STM32F769xx LQFP208 pinout 06Y9 1. The above figure shows the package top view. DocID029041 Rev 6 61/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 19. STM32F76xxx UFBGA176 ballout ! 0% 0% " 0% # 0% 0% 0" 0" 0' 0' 0" 0% 0% 0" 0" 0" 0' 0' 6"!4 0) 0) 0) 6$$ 0" 0$ 0# 0! 0! 0! 0' 0' 0$ 0$ 0# 0# 0! 6$$ 3$--# 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! & 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$53" 0' 0# * .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' - 633! 0# 0# 0# 0# 0" 0' 633 633 0( 0( 0( 0$ 0$ . 62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 0$2?/. 6$$ "//4 633 633 6#!0? -36 1. The above figure shows the package top view. 62/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 20. STM32F76xxx TFBGA216 ballout ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* $ 0# 0& 0) 0) 0) 0) 0+ 0+ 0' % 0# 0& 0) 0) 0$2? /. "//4 6$$ 6$$ & 0# 633 0) 6$$ 6$$ 633 633 633 ' 0( 0& 0) 0) 6$$ 633 633 ( 0( 0& 0) 0( 6$$ 633 633 6$$ * .234 0& 0( 0( 6$$ 633 633 + 0& 0& 0& 0( 6$$ 633 633 633 633 0& 0& 0& 0# "90!33 633 2%' 6$$ 6$$ - 633! 0# 0# 0# 0" 0& 0' . 62%& 0! 0! 0! 0# 0& 0 62%& 0! 0! 0! 0# 2 6$$! 0! 0! 0" 0" , 0# 0! 0! 0! 0$ 0$ 0# 0# 0! 0$ 0$ 0$ 0) 0) 0! 0* 0$ 0$ 0( 0) 0! 6#!0 0( 0( 0) 0! 6$$ 0+ 0+ 0# 0! 6$$53" 0* 0+ 0# 0# 0* 0* 0' 0# 6$$ 0* 0* 0' 633 6$$ 0* 0$ 0" 6$$ 6$$ 6#!0 0$ 0" 0$ 0& 0* 0$ 0$ 0' 0' 0* 0' 0* 0% 0$ 0' 0' 0( 0( 0& 0* 0& 0% 0% 0% 0" 0( 0( 0* 0* 0% 0% 0% 0% 0% 0" 0" 6$$ 6$$ 3$--# 633 633 0' 0$ 0$ 0( 0( 0( 0" -36 1. The above figure shows the package top view. DocID029041 Rev 6 63/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 21. STM32F769xx TFBGA216 ballout ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* $ 0# 0& 0) 0) 0) 0) 0+ 0+ 0' % 0# 0& 0) 0) 0$2? /. "//4 6$$ 6$$ & 0# 633 0) 6$$ 6$$ 633 633 633 ' 0( 0& 0) 0) 6$$ 633 633 6$$53" 633$3) ( 0( 0& 0) 0( 6$$ 633 633 * .234 0& 0( 0( 6$$ 633 633 6$$ + 0& 0& 0& 0( 6$$ 633 633 633 633 633 0& 0& 0& 0# "90!33 633 2%' 6$$ 6$$ 6$$ 6$$ 6#!0 0$ 0" 0$ - 633! 0# 0# 0# 0" 0& 0' 0& 0* 0$ 0$ 0' 0' 0* . 62%& 0! 0! 0! 0# 0& 0' 0* 0% 0$ 0' 0' 0( 0( 0 62%& 0! 0! 0! 0# 0& 0* 0& 0% 0% 0% 0" 0( 0( 2 6$$! 0! 0! 0" 0" 0* 0* 0% 0% 0% 0% 0% 0" 0" , 0# 0! 0! 0! 0$ 0$ 0# 0# 0! 0$ 0$ 0$ 0) 0) 0! 0* 0$ 0$ 0( 0) 0! 0( 0( 0) 0! 0# 0! 6$$ 0# $3) 0# 6$$$3) $3)? #+0 $3)? #+. 0' 0# $3)? $0 $3)? $. 0' 6$$ 6#!0$3) 0$ 0" 6$$ 3$--# 6$$ 6#!0 633 633 6$$ $3)? $0 $3)? $. 0' 0$ 0$ 0( 0( 0( 0" -36 1. The above figure shows the package top view. 64/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 10. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT pin RST Bidirectional reset pin with weak pull-up resistor Pin type I/O structure Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions 1 A3 PE2 I/O FT - B3 2 2 A1 2 2 A2 F10 2 2 A2 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT TFBGA216 1 LQFP208 E10 LQFP176 A3 WLCSP180(1) 1 TFBGA216 1 LQFP208 A2 LQFP176 1 UFBGA176 1 LQFP144 A3 TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, ETH_MII_TXD3, FMC_A23, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure STM32F768Ax STM32F769xx Pin type STM32F765xx STM32F767xx Pin name (function after reset Pin Number DocID029041 Rev 6 Additional functions - - 65/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) D3 3 4 4 B1 B2 3 4 3 4 A1 B1 C12 D12 E3 5 5 B3 5 5 B2 - - - - - - G6 - - - - - - - F5 - B2 6 6 C1 6 6 C1 C13 - - - D2 7 7 C2 A2 7 7 D1 8 8 A1 8 8 E1 9 B1 9 9 F1 - - - - - - 3 4 5 4 A1 B1 PE4 PE5 PE6 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 3 FT FT Additional functions - TRACED1, SPI4_NSS, SAI1_FS_A, DFSDM1_DATIN3, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT - - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, DFSDM1_CKIN3, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT - - TRACED3, TIM1_BKIN2, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT - B2 - - G6 VSS S - - - - - - F5 VDD S - - - - 6 6 C1 VBAT S - - - - NC 7 7 C2 PI8 I/O FT (2) EVENTOUT RTC_TAMP2/ RTC_TS/ WKUP5 D1 D13 8 8 D1 PC13 I/O FT (2) EVENTOUT RTC_TAMP1/ RTC_TS/ RTC_OUT/ WKUP4 9 E1 E12 9 9 E1 PC14OSC32_IN I/O FT (2) (3) EVENTOUT OSC32_IN 10 10 F1 E13 10 10 F1 PC15OSC32_O UT I/O FT (2) (3) EVENTOUT OSC32_OUT - - - G5 - - - G5 VDD S - - - - - D3 11 11 E4 G10 11 11 E4 PI9 I/O FT - UART4_RX, CAN1_RX, FMC_D30, LCD_VSYNC, EVENTOUT - - - E3 12 12 D5 H10 12 12 D5 PI10 I/O FT - ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT - - - - E4 13 13 F3 F11 13 13 F3 PI11 I/O FT - LCD_G6, OTG_HS_ULPI_DIR, EVENTOUT WKUP6 - - - F2 14 14 F2 F13 14 14 F2 VSS S - - - - DocID029041 Rev 6 FT Alternate functions 5 66/255 E11 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 3 STM32F768Ax STM32F769xx Notes C3 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx - - - F3 15 15 F4 F12 15 15 F4 VDD S - - - - - - 10 E2 16 16 D2 G11 16 16 D2 PF0 I/O FT - I2C2_SDA, FMC_A0, EVENTOUT - - - 11 H3 17 17 E2 G12 17 17 E2 PF1 I/O FT - I2C2_SCL, FMC_A1, EVENTOUT - - - 12 H2 18 18 G2 G13 18 18 G2 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - - - 19 E3 NC - 19 E3 PI12 I/O FT - LCD_HSYNC, EVENTOUT - - - - - - 20 G3 NC - 20 G3 PI13 I/O FT - LCD_VSYNC, EVENTOUT - - - - - - 21 H3 NC - 21 H3 PI14 I/O FT - LCD_CLK, EVENTOUT - - - 13 J2 19 22 H2 H11 19 22 H2 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9 - - 14 J3 20 23 J2 H12 20 23 J2 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14 - - 15 K3 21 24 K3 H13 21 24 K3 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15 C2 10 16 G2 22 25 H6 J13 22 25 H6 VSS S - - - - D2 11 17 G3 23 26 H5 J12 23 26 H5 VDD S - - - - ADC3_IN4 Additional functions - - 18 K2 24 27 K2 NC 24 27 K2 PF6 I/O FT - TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, EVENTOUT - - 19 K1 25 28 K1 NC 25 28 K1 PF7 I/O FT - TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT ADC3_IN5 - - 20 L3 26 29 L3 NC 26 29 L3 PF8 I/O FT - SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_IN6 - - 21 L2 27 30 L2 NC 27 30 L2 PF9 I/O FT - SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT ADC3_IN7 - - 22 L1 28 31 L1 K11 28 31 L1 PF10 I/O FT - QUADSPI_CLK, DCMI_D11, LCD_DE, EVENTOUT ADC3_IN8 C1 12 23 G1 29 32 G1 K12 29 32 G1 PH0OSC_IN I/O FT (3) EVENTOUT OSC_IN DocID029041 Rev 6 67/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx D1 13 24 H1 30 33 H1 K13 30 33 H1 PH1OSC_OUT I/O FT (3) EVENTOUT OSC_OUT E1 14 25 J1 31 34 J1 L11 31 34 J1 NRST I/O RS T - - - - DFSDM1_CKIN0, DFSDM1_DATIN4, SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, LCD_R5, EVENTOUT ADC1_IN10, ADC2_IN10, ADC3_IN10 - TRACED0, DFSDM1_DATIN0, SPI2_MOSI/I2S2_SD, SAI1_SD_A, DFSDM1_CKIN4, ETH_MDC, MDIOS_MDC, EVENTOUT ADC1_IN11, ADC2_IN11, ADC3_IN11, RTC_TAMP3/ WKUP3 - DFSDM1_CKIN1, SPI2_MISO, DFSDM1_CKOUT, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT ADC1_IN12, ADC2_IN12, ADC3_IN12 ADC1_IN13, ADC2_IN13, ADC3_IN13 - F1 F2 E2 15 16 17 26 27 28 M2 M3 M4 32 33 34 35 36 37 M2 M3 M4 L12 L13 NC 32 33 34 35 36 37 M2 M3 M4 PC0 PC1 PC2 I/O I/O I/O FT FT FT F3 18 29 M5 35 38 L4 NC 35 38 L4 PC3 I/O FT - DFSDM1_DATIN1, SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT - - 30 - 36 39 J5 - 36 39 J5 VDD S - - - Additional functions - - - - - - J6 - - - J6 VSS S - - - - G1 19 31 M1 37 40 M1 M11 37 40 M1 VSSA S - - - - - - - N1 - - N1 - - - N1 VREF- S - - - - - 20 32 P1 38 41 P1 - 38 41 P1 VREF+ S - - - - H1 21 33 R1 39 42 R1 M12 39 42 R1 VDDA S - - - - (4) TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI2_SD_B, ETH_MII_CRS, EVENTOUT ADC1_IN0, ADC2_IN0, ADC3_IN0, WKUP1 G2 22 68/255 34 N3 40 43 N3 M13 40 43 N3 PA0WKUP I/O DocID029041 Rev 6 FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) J2 23 24 36 N2 P2 41 42 44 45 N2 P2 J11 J10 41 42 44 45 N2 P2 PA1 PA2 I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 35 STM32F768Ax STM32F769xx FT FT Notes H2 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_ REF_CLK, LCD_R2, EVENTOUT ADC1_IN1, ADC2_IN1, ADC3_IN1 - TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, SAI2_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT ADC1_IN2, ADC2_IN2, ADC3_IN2, WKUP2 - - - - F4 43 46 K4 L10 43 46 K4 PH2 I/O FT - LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT - - - G4 44 47 J4 K10 44 47 J4 PH3 I/O FT - QUADSPI_BK2_IO1, SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT - - - - H4 45 48 H4 N12 45 48 H4 PH4 I/O FT - I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, LCD_G4, EVENTOUT - - - - J4 46 49 J3 N11 46 49 J3 PH5 I/O FT - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT - ADC1_IN3, ADC2_IN3, ADC3_IN3 PA3 I/O FT - TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT K6 VSS S - - - - I FT - - - S - - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT ADC1_IN4, ADC2_IN4, DAC_OUT1 K2 25 37 R2 47 50 R2 M10 47 50 R2 J1 26 38 - - 51 K6 J9 - 51 E6 - - L4 48 - L5 -(5) 48 - L5 BYPASS_ REG K1 27 39 K4 49 52 K5 K9 49 52 K5 VDD G3 28 40 N4 50 53 N4 L9 50 53 N4 PA4 I/O DocID029041 Rev 6 TTa 69/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) J3 29 30 42 P4 P3 51 52 54 55 P4 P3 P11 N10 51 52 54 55 P4 P3 PA5 PA6 I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 41 STM32F768Ax STM32F769xx TTa FT Notes H3 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, OTG_HS_ULPI_CK, LCD_R4, EVENTOUT ADC1_IN5, ADC2_IN5, DAC_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, SPI6_MISO, TIM13_CH1, MDIOS_MDC, DCMI_PIXCLK, LCD_G2, EVENTOUT ADC1_IN6, ADC2_IN6 ADC1_IN7, ADC2_IN7 K3 31 43 R3 53 56 R3 M9 53 56 R3 PA7 I/O FT - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, SPI6_MOSI, TIM14_CH1, ETH_MII_RX_DV/ETH_RMII_C RS_DV, FMC_SDNWE, EVENTOUT G4 32 44 N5 54 57 N5 NC 54 57 N5 PC4 I/O FT - DFSDM1_CKIN2, I2S1_MCK, SPDIF_RX2, ETH_MII_RXD0/ETH_RMII_RX D0, FMC_SDNE0, EVENTOUT ADC1_IN14, ADC2_IN14 ADC1_IN15, ADC2_IN15 H4 33 45 P5 55 58 P5 NC 55 58 P5 PC5 I/O FT - DFSDM1_DATIN2, SPDIF_RX3, ETH_MII_RXD1/ETH_RMII_RX D1, FMC_SDCKE0, EVENTOUT - - - - - 59 L7 - - 59 L7 VDD S - - - - - - - - - 60 L6 - - 60 L6 VSS S - - - - - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, DFSDM1_CKOUT, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, EVENTOUT ADC1_IN8, ADC2_IN8 - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, EVENTOUT ADC1_IN9, ADC2_IN9 J4 K4 34 35 70/255 46 47 R5 R4 56 57 61 62 R5 R4 P10 J8 56 57 61 62 R5 R4 PB0 PB1 I/O I/O DocID029041 Rev 6 FT FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx G5 36 48 M6 58 63 M5 J7 58 63 M5 PB2 I/O FT - SAI1_SD_A, SPI3_MOSI/I2S3_SD, QUADSPI_CLK, DFSDM1_CKIN1, EVENTOUT - - - - - - 64 G4 NC - 64 G4 PI15 I/O FT - LCD_G2, LCD_R0, EVENTOUT - - - - - - 65 R6 NC - 65 R6 PJ0 I/O FT - LCD_R7, LCD_R1, EVENTOUT - - - - - - 66 R7 NC - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT - - - - - - 67 P7 NC - 67 P7 PJ2 I/O FT - DSI_TE, LCD_R3, EVENTOUT - - - - - - 68 N8 NC - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT - - - - - - 69 M9 NC - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT - - - 49 R6 59 70 P8 N9 59 70 P8 PF11 I/O FT - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT - - - 50 P6 60 71 M6 K7 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT - - - 51 M8 61 72 K7 P9 61 72 K7 VSS S - - - - - - 52 N8 62 73 L8 M8 62 73 L8 VDD S - - - - - - 53 N6 63 74 N6 L8 63 74 N6 PF13 I/O FT - I2C4_SMBA, DFSDM1_DATIN6, FMC_A7, EVENTOUT - - - 54 R7 64 75 P6 K8 64 75 P6 PF14 I/O FT - I2C4_SCL, DFSDM1_CKIN6, FMC_A8, EVENTOUT - - - 55 P7 65 76 M8 P8 65 76 M8 PF15 I/O FT - I2C4_SDA, FMC_A9, EVENTOUT - - - 56 N7 66 77 N7 N8 66 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT - - - 57 M7 67 78 M7 L7 67 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT - - - H5 37 58 R8 68 79 R8 M7 68 79 R8 PE7 I/O FT - TIM1_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4, EVENTOUT J5 38 59 P8 69 80 N9 N7 69 80 N9 PE8 I/O FT - TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, QUADSPI_BK2_IO1, FMC_D5, EVENTOUT DocID029041 Rev 6 Additional functions 71/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx K5 39 60 P9 70 81 P9 P7 70 81 P9 PE9 I/O FT - TIM1_CH1, DFSDM1_CKOUT, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6, EVENTOUT - - - 61 M9 71 82 K8 - 71 82 K8 VSS S - - - - - - 62 N9 72 83 L9 - 72 83 L9 VDD S - - - - - Additional functions G6 40 63 R9 73 84 R9 J6 73 84 R9 PE10 I/O FT - TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7, EVENTOUT H6 41 64 P10 74 85 P10 K6 74 85 P10 PE11 I/O FT - TIM1_CH2, SPI4_NSS, DFSDM1_CKIN4, SAI2_SD_B, FMC_D8, LCD_G3, EVENTOUT - J6 42 65 R10 75 86 R10 L6 75 86 R10 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, DFSDM1_DATIN5, SAI2_SCK_B, FMC_D9, LCD_B4, EVENTOUT - K6 43 66 N11 76 87 R12 P6 76 87 R12 PE13 I/O FT - TIM1_CH3, SPI4_MISO, DFSDM1_CKIN5, SAI2_FS_B, FMC_D10, LCD_DE, EVENTOUT - G7 44 67 P11 77 88 P11 N6 77 88 P11 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11, LCD_CLK, EVENTOUT - H7 45 68 R11 78 89 R11 M6 78 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12, LCD_R7, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - J7 46 72/255 69 R12 79 90 P12 K5 79 90 P12 PB10 I/O DocID029041 Rev 6 FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) 91 R13 PB11 I/O FT - F8 48 71 M10 81 92 L11 P5 81 92 L11 VCAP_1 S - - - - - 49 - - - 93 K9 N5 - 93 K9 VSS S - - - - - 50 72 N10 82 94 L10 P4 82 94 L10 VDD S - - - - - - - - - 95 M14 NC - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT - - - - M11 83 96 P13 NC 83 96 P13 PH6 I/O FT - I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT - - - - N12 84 97 N13 NC 84 97 N13 PH7 I/O FT - I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT - - - - M12 85 98 P14 M5 - 98 P14 PH8 I/O FT - I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT - - - - M13 86 99 N14 K4 - 99 N14 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT - - - - L13 87 100 P15 L4 - 100 P15 PH10 I/O FT - TIM5_CH1, I2C4_SMBA, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT - - - - L12 88 101 N15 M4 - 101 N15 PH11 I/O FT - TIM5_CH2, I2C4_SCL, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT - - - - K12 89 102 M15 P3 - 102 M15 PH12 I/O FT - TIM5_CH3, I2C4_SDA, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT - - - - H12 90 - K10 N4 - - K10 VSS S - - - - - - - J12 91 103 K11 - - 103 K11 VDD S - - - - TFBGA216 80 LQFP208 L5 LQFP176 R13 WLCSP180(1) 91 TFBGA216 80 LQFP208 R13 LQFP176 70 UFBGA176 47 LQFP144 K7 TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_T X_EN, DSI_TE, LCD_G5, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure STM32F768Ax STM32F769xx Pin type STM32F765xx STM32F767xx Pin name (function after reset Pin Number DocID029041 Rev 6 Additional functions - 73/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) J8 H10 51 52 53 74 75 P12 P13 R14 92 93 94 104 105 106 L13 K14 R14 H8 J5 N3 85 86 87 104 105 106 L13 K14 R14 PB12 PB13 PB14 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 73 STM32F768Ax STM32F769xx FT FT FT Notes K8 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, UART5_RX, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TX D0, OTG_HS_ID, EVENTOUT - - TIM1_CH1N, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS, UART5_TX, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TX D1, EVENTOUT OTG_HS_VB US - TIM1_CH2N, TIM8_CH2N, USART1_TX, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS, UART4_RTS, TIM12_CH1, SDMMC2_D0, OTG_HS_DM, EVENTOUT - - G10 54 76 R15 95 107 R15 N2 88 107 R15 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, UART4_CTS, TIM12_CH2, SDMMC2_D1, OTG_HS_DP, EVENTOUT K9 55 77 P15 96 108 L15 M3 89 108 L15 PD8 I/O FT - DFSDM1_CKIN3, USART3_TX, SPDIF_RX1, FMC_D13, EVENTOUT - J9 56 78 P14 97 109 L14 L3 90 109 L14 PD9 I/O FT - DFSDM1_DATIN3, USART3_RX, FMC_D14, EVENTOUT - H9 57 79 N15 98 110 K15 M2 91 110 K15 PD10 I/O FT - DFSDM1_CKOUT, USART3_CK, FMC_D15, LCD_B3, EVENTOUT - - I2C4_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT - G9 58 74/255 80 N14 99 111 N10 K3 92 111 N10 PD11 I/O DocID029041 Rev 6 FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) 59 N13 100 112 M10 J4 93 112 M10 PD12 I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 81 STM32F768Ax STM32F769xx FT Notes K10 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM4_CH1, LPTIM1_IN1, I2C4_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, EVENTOUT - - J10 60 82 M15 101 113 M11 L2 94 113 M11 PD13 I/O FT - TIM4_CH2, LPTIM1_OUT, I2C4_SDA, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - - 83 - 102 114 J10 M1 95 114 J10 VSS S - - - - - - 84 J13 103 115 J11 - 96 115 J11 VDD S - - - - H8 61 85 M14 104 116 L12 L1 97 116 L12 PD14 I/O FT - TIM4_CH3, UART8_CTS, FMC_D0, EVENTOUT - G8 62 86 L14 105 117 K13 K2 98 117 K13 PD15 I/O FT - TIM4_CH4, UART8_RTS, FMC_D1, EVENTOUT - - - - - - 118 K12 - - - - PJ6 I/O FT - LCD_R7, EVENTOUT - - - - - - 119 J12 - - - - PJ7 I/O FT - LCD_G0, EVENTOUT - - - - - - 120 H12 - - - - PJ8 I/O FT - LCD_G1, EVENTOUT - - - - - - 121 J13 - - - - PJ9 I/O FT - LCD_G2, EVENTOUT - - - - - - 122 H13 - - - - PJ10 I/O FT - LCD_G3, EVENTOUT - - - - - - 123 G12 - - - - PJ11 I/O FT - LCD_G4, EVENTOUT - - - - - - 124 H11 - - - - VDD S - - - - - - - - - - - K1 99 118 H11 VDDDSI S - - - - - - - - - 125 H10 - - - H10 VSS S - - - - - - - - - - - H6 100 119 K12 VCAPDSI S - - - - - - - - - - - J3 - - G13 VDD12DSI S - - - - - - - - - - - J1 101 120 J12 DSI_D0P I/O - - - - - - - - - - - J2 102 121 J13 DSI_D0N I/O - - - - - - - - - - - H5 103 122 G12 VSSDSI S - - - - - - - - - - - H4 104 123 H12 DSI_CKP I/O - - - - DocID029041 Rev 6 75/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes - - - - - - - H3 105 124 H13 DSI_CKN I/O - - - - - - - - - - - - 106 125 - VDD12DSI S - - - - - - - - - - - H1 107 126 F12 DSI_D1P I/O - - - - - - - - - - - H2 108 127 F13 DSI_D1N I/O - - - - - - - - - - - - 109 128 - VSSDSI S - - - - - - - - - 126 G13 - - - - PK0 I/O FT - LCD_G5, EVENTOUT - - - - - - 127 F12 - - - - PK1 I/O FT - LCD_G6, EVENTOUT - - - - - - 128 F13 - - - - PK2 I/O FT - LCD_G7, EVENTOUT - - - 87 L15 106 129 M13 H9 110 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT - - - 88 K15 107 130 M12 G9 111 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT - - - 89 K14 108 131 N12 G1 112 131 N12 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - - 90 K13 109 132 N11 G2 113 132 N11 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - - - 91 J15 110 133 J15 G3 114 133 J15 PG6 I/O FT - FMC_NE3, DCMI_D12, LCD_R7, EVENTOUT - - - 92 J14 111 134 J14 G4 115 134 J14 PG7 I/O FT - SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13, LCD_CLK, EVENTOUT - - - 93 H14 112 135 H14 G5 116 135 H14 PG8 I/O FT - SPI6_NSS, SPDIF_RX2, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, EVENTOUT - - - 94 G12 113 136 G10 F1 117 136 G10 VSS S - - - - F6 - 95 H13 114 137 G11 F2 118 137 G11 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, DFSDM1_CKIN3, USART6_TX, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0, LCD_HSYNC, EVENTOUT - F10 63 76/255 96 H15 115 138 H15 G6 LQFP176 LQFP144 UFBGA176 Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx 119 138 H15 PC6 I/O DocID029041 Rev 6 FT Additional functions STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) F9 E9 64 65 66 98 99 G15 G14 F14 116 117 118 139 140 141 G15 G14 F14 F3 G8 E1 120 139 121 140 122 141 G15 G14 F14 PC7 PC8 PC9 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 97 STM32F768Ax STM32F769xx FT FT FT Notes E10 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM3_CH2, TIM8_CH2, I2S3_MCK, DFSDM1_DATIN3, USART6_RX, FMC_NE1, SDMMC2_D7, SDMMC1_D7, DCMI_D1, LCD_G6, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, FMC_NE2/FMC_NCE, SDMMC1_D0, DCMI_D2, EVENTOUT - - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, LCD_G3, SDMMC1_D1, DCMI_D3, LCD_B2, EVENTOUT -- - D9 67 100 F15 119 142 F15 E2 123 142 F15 PA8 I/O FT - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, CAN3_RX, UART7_RX, LCD_B3, LCD_R6, EVENTOUT C9 68 101 E15 120 143 E15 F4 124 143 E15 PA9 I/O FT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, DCMI_D0, LCD_R5, EVENTOUT OTG_FS_VB US D10 69 102 D15 121 144 D15 F5 125 144 D15 PA10 I/O FT - TIM1_CH3, USART1_RX, LCD_B4, OTG_FS_ID, MDIOS_MDIO, DCMI_D1, LCD_B1, EVENTOUT - - TIM1_CH4, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS, CAN1_RX, OTG_FS_DM, LCD_R4, EVENTOUT - - TIM1_ETR, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS, SAI2_FS_B, CAN1_TX, OTG_FS_DP, LCD_R5, EVENTOUT - C10 B10 70 71 103 C15 104 B15 122 123 145 146 C15 B15 E3 D1 126 145 127 146 C15 B15 PA11 PA12 I/O I/O DocID029041 Rev 6 FT FT 77/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes A10 72 105 A15 124 147 A15 D2 128 147 A15 PA13(JTM S-SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - E7 73 106 F13 125 148 E11 C1 129 148 E11 VCAP_2 S - - - - E5 74 107 F12 126 149 F10 C2 130 149 F10 VSS S - - - - F5 75 108 G13 127 150 F11 B2 131 150 F11 VDD S - - - - LQFP176 LQFP144 UFBGA176 Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx Additional functions - - - E12 128 151 E12 F6 - 151 E12 PH13 I/O FT - TIM8_CH1N, UART4_TX, CAN1_TX, FMC_D21, LCD_G2, EVENTOUT - - - E13 129 152 E13 F7 - 152 E13 PH14 I/O FT - TIM8_CH2N, UART4_RX, CAN1_RX, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT - - - - D13 130 153 D13 E5 - 153 D13 PH15 I/O FT - TIM8_CH3N, FMC_D23, DCMI_D11, LCD_G4, EVENTOUT - - - - E14 131 154 E14 E4 132 154 E14 PI0 I/O FT - TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, DCMI_D13, LCD_G5, EVENTOUT - - - - D14 132 155 D14 B3 133 155 D14 PI1 I/O FT - TIM8_BKIN2, SPI2_SCK/I2S2_CK, FMC_D25, DCMI_D8, LCD_G6, EVENTOUT - - - - C14 133 156 C14 C3 156 C14 PI2 I/O FT - TIM8_CH4, SPI2_MISO, FMC_D26, DCMI_D9, LCD_G7, EVENTOUT - - - - C13 134 157 C13 D3 134 157 C13 PI3 I/O FT - TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, DCMI_D10, EVENTOUT - - - - D9 135 - F9 - 135 F9 VSS S - - - - - - - C9 136 158 E10 - 136 158 E10 VDD S - - - -- A9 76 109 A14 137 159 A14 A3 137 159 A14 PA14(JTC K-SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - 78/255 - - DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) B9 B8 77 78 79 111 112 A13 B14 B13 138 139 140 160 161 162 A13 B14 B13 F8 B4 C4 138 160 139 161 140 162 A13 B14 B13 PA15(JTDI ) PC10 PC11 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 110 STM32F768Ax STM32F769xx FT FT FT Notes A8 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS, CAN3_TX, UART7_TX, EVENTOUT - - DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, DCMI_D8, LCD_R2, EVENTOUT - - DFSDM1_DATIN5, SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, DCMI_D4, EVENTOUT - - C8 80 113 A12 141 163 A12 D4 141 163 A12 PC12 I/O FT - TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9, EVENTOUT D8 81 114 B12 142 164 B12 A4 142 164 B12 PD0 I/O FT - DFSDM1_CKIN6, DFSDM1_DATIN7, UART4_RX, CAN1_RX, FMC_D2, EVENTOUT - E8 82 115 C12 143 165 C12 D5 143 165 C12 PD1 I/O FT - DFSDM1_DATIN6, DFSDM1_CKIN7, UART4_TX, CAN1_TX, FMC_D3, EVENTOUT -- B7 83 116 D12 144 166 D12 D6 144 166 D12 PD2 I/O FT - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, DCMI_D11, EVENTOUT - - - C7 84 117 D11 145 167 C11 B5 145 167 C11 PD3 I/O FT - DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT D7 85 118 D10 146 168 D11 A5 146 168 D11 PD4 I/O FT - DFSDM1_CKIN0, USART2_RTS, FMC_NOE, EVENTOUT DocID029041 Rev 6 79/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes B6 86 119 C11 147 169 C10 C5 147 169 C10 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - 120 D8 148 170 F8 B6 148 170 F8 VSS S - - - - - - 121 C8 149 171 E9 A6 149 171 E9 VDDSDM MC S - - - - - DFSDM1_CKIN4, SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, DFSDM1_DATIN1, SDMMC2_CK, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT - - C6 87 122 B11 150 172 B11 E6 LQFP176 LQFP144 UFBGA176 Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx 150 172 B11 PD6 I/O FT Additional functions A11 PD7 I/O FT - DFSDM1_DATIN4, SPI1_MOSI/I2S1_SD, DFSDM1_CKIN1, USART2_CK, SPDIF_RX0, SDMMC2_CMD, FMC_NE1, EVENTOUT 174 B10 PJ12 I/O FT - LCD_G3, LCD_B0, EVENTOUT - 175 B9 PJ13 I/O FT - LCD_G4, LCD_B1, EVENTOUT - PJ14 I/O FT - LCD_B2, EVENTOUT - PJ15 I/O FT - LCD_B3, EVENTOUT - - D6 88 123 A11 151 173 A11 E7 151 173 - - - - - 174 B10 NC - - - - - - 175 B9 NC - - - - - - 176 C9 NC - 176 C9 - - - - - 177 D10 - - 177 D10 - - 124 C10 152 178 D9 C6 152 178 D9 PG9 I/O FT - SPI1_MISO, SPDIF_RX3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC, EVENTOUT - - 125 153 179 C8 A7 153 179 C8 PG10 I/O FT - SPI1_NSS/I2S1_WS, LCD_G3, SAI2_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2, LCD_B2, EVENTOUT - - SPI1_SCK/I2S1_CK, SPDIF_RX0, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_T X_EN, DCMI_D3, LCD_B3, EVENTOUT - - 80/255 - 126 B10 B9 154 180 B8 B7 154 180 B8 PG11 I/O DocID029041 Rev 6 FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) - - - 128 B8 A8 155 156 B3 B3 PG13 FT - - TRACED0, LPTIM1_OUT, SPI6_SCK, USART6_CTS, ETH_MII_TXD0/ETH_RMII_TX D0, FMC_A24, LCD_R0, EVENTOUT - - TRACED1, LPTIM1_ETR, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1/ETH_RMII_TX D1, FMC_A25, LCD_B0, EVENTOUT - D7 158 184 F7 A8 158 184 F7 VSS S - - - - C7 159 185 E8 B8 159 185 E8 VDD S - - - - - - - - - 186 D8 NC - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT - - - - - - 187 D7 NC - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT - - - - - - 188 C6 NC - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT - - - - - - 189 C5 NC - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT - - - - - - 190 C4 NC - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT - - - 132 B7 160 191 B7 F9 160 191 B7 PG15 I/O FT - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, CAN3_RX, UART7_RX, EVENTOUT - - NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, CAN3_TX, UART7_TX, EVENTOUT - A6 90 134 A9 162 193 A9 D8 162 193 A10 A9 PB3 (JTDO/ I/O TRACESW O) PB4(NJTR ST) I/O DocID029041 Rev 6 FT - 131 161 192 I/O I/O structure Pin type I/O FT 130 E8 PG14 I/O - A10 A4 PG12 - 192 157 183 TFBGA216 LQFP208 156 182 C7 - 161 NC LQFP176 WLCSP180(1) C7 155 181 - A10 A4 D7 LPTIM1_IN1, SPI6_MISO, SPDIF_RX1, USART6_RTS, LCD_B4, SDMMC2_D3, FMC_NE4, LCD_B1, EVENTOUT 129 133 183 TFBGA216 LQFP208 182 C7 Additional functions - 89 157 181 Alternate functions - A7 A7 LQFP176 UFBGA176 LQFP144 127 STM32F768Ax STM32F769xx Notes - LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number FT FT 81/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) B5 91 92 136 A6 B6 163 164 194 195 A8 B6 A9 B9 163 194 164 195 A8 B6 PB5 PB6 I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 135 STM32F768Ax STM32F769xx FT FT Notes C5 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - UART5_RX, TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, SPI6_MOSI, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, LCD_G7, EVENTOUT - - UART5_TX, TIM4_CH1, HDMI_CEC, I2C1_SCL, DFSDM1_DATIN5, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, I2C4_SCL, FMC_SDNE1, DCMI_D5, EVENTOUT - TIM4_CH2, I2C1_SDA, DFSDM1_CKIN5, USART1_RX, I2C4_SDA, FMC_NL, DCMI_VSYNC, EVENTOUT - A5 93 137 B5 165 196 B5 C8 165 196 B5 PB7 I/O FT - D5 94 138 D6 166 197 E6 A10 166 197 E6 BOOT0 I B - - VPP - I2C4_SCL, TIM4_CH3, TIM10_CH1, I2C1_SCL, DFSDM1_CKIN7, UART5_RX, CAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6, LCD_B6, EVENTOUT - - B4 95 139 A5 167 198 A7 E9 167 198 A7 PB8 I/O FT A4 96 140 B4 168 199 B4 D9 168 199 B4 PB9 I/O FT - I2C4_SDA, TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN7, UART5_TX, CAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7, LCD_B7, EVENTOUT D4 97 141 A4 169 200 A6 C9 169 200 A6 PE0 I/O FT - TIM4_ETR, LPTIM1_ETR, UART8_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT - C4 98 142 A3 170 201 A5 B10 170 201 A5 PE1 I/O FT - LPTIM1_IN2, UART8_TX, FMC_NBL1, DCMI_D3, EVENTOUT - 82/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number TFBGA216 Pin name (function after reset Pin type I/O structure Notes - - C10 171 203 E5 PDR_ON S - - - - E7 B11 172 204 E7 VDD S - - - - WLCSP180(1) - TFBGA216 - LQFP208 S LQFP176 VSS UFBGA176 F6 LQFP144 202 LQFP100 - TFBGA100 Alternate functions LQFP208 STM32F768Ax STM32F769xx LQFP176 STM32F765xx STM32F767xx E4 99 - D5 - 202 F6 A11 F7 - 143 C6 171 203 E5 100 144 C5 172 204 F4 Additional functions - - - D4 173 205 C3 D10 173 205 C3 PI4 I/O FT - TIM8_BKIN, SAI2_MCLK_A, FMC_NBL2, DCMI_D5, LCD_B4, EVENTOUT - - - - C4 174 206 D3 D11 174 206 D3 PI5 I/O FT - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, DCMI_VSYNC, LCD_B5, EVENTOUT - - - - C3 175 207 D6 C11 175 207 D6 PI6 I/O FT - TIM8_CH2, SAI2_SD_A, FMC_D28, DCMI_D6, LCD_B6, EVENTOUT - - - - C2 176 208 D4 B12 176 208 D4 PI7 I/O FT - TIM8_CH3, SAI2_FS_A, FMC_D29, DCMI_D7, LCD_B7, EVENTOUT - - - - F6 - - - - - - - VSS S - - - - - - - F7 - - - - - - - VSS S - - - - - - - F8 - - - - - - - VSS S - - - - - - - F9 - - - - - - - VSS S - - - - - - - F10 - - - - - - - VSS S - - - - - - - G6 - - - - - - - VSS S - - - - - - - G7 - - - - - - - VSS S - - - - - - - G8 - - - - - - - VSS S - - - - - - - G9 - - - - - - - VSS S - - - - - - - G10 - - - - - - - VSS S - - - - - - - H6 - - - - - - - VSS S - - - - - - - H7 - - - - - - - VSS S - - - - - - - H8 - - - - - - - VSS S - - - - - - - H9 - - - - - - - VSS S - - - - - - - H10 - - - - - - - VSS S - - - - - - - J6 - - - - - - - VSS S - - - - DocID029041 Rev 6 83/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx - - - J7 - - - - - - - VSS S - - - - - - - J8 - - - - - - - VSS S - - - - - - - J9 - - - - - - - VSS S - - - - - - - J10 - - - - - - - VSS S - - - - - - - K6 - - - - - - - VSS S - - - - - - - K7 - - - - - - - VSS S - - - - - - - K8 - - - - - - - VSS S - - - - - - - K9 - - - - - - - VSS S - - - - - - - K10 - - - - - - - VSS S - - - - Additional functions 1. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid an extra current consumption in low-power modes. list of pins: PI8, PI12, PI13, PI14, PF6, PF7, PF8, PF9, PC2, PC3, PC4, PC5, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PH6, PH7, PJ12, PJ13, PJ14, PJ15, PG14, PK3, PK4, PK5, PK6 and PK7. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 4. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low). 5. Internally connected to VDD or VSS depending on part number. 84/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 12. FMC pin definition Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF0 A0 - - A0 PF1 A1 - - A1 PF2 A2 - - A2 PF3 A3 - - A3 PF4 A4 - - A4 PF5 A5 - - A5 PF12 A6 - - A6 PF13 A7 - - A7 PF14 A8 - - A8 PF15 A9 - - A9 PG0 A10 - - A10 PG1 A11 - - A11 PG2 A12 - - A12 PG3 A13 - - - PG4 A14 - - BA0 PG5 A15 - - BA1 PD11 A16 A16 CLE - PD12 A17 A17 ALE - PD13 A18 A18 - - PE3 A19 A19 - - PE4 A20 A20 - - PE5 A21 A21 - - PE6 A22 A22 - - PE2 A23 A23 - - PG13 A24 A24 - - PG14 A25 A25 - - PD14 D0 DA0 D0 D0 PD15 D1 DA1 D1 D1 PD0 D2 DA2 D2 D2 PD1 D3 DA3 D3 D3 PE7 D4 DA4 D4 D4 PE8 D5 DA5 D5 D5 PE9 D6 DA6 D6 D6 PE10 D7 DA7 D7 D7 DocID029041 Rev 6 85/255 101 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 12. FMC pin definition (continued) 86/255 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PE11 D8 DA8 D8 D8 PE12 D9 DA9 D9 D9 PE13 D10 DA10 D10 D10 PE14 D11 DA11 D11 D11 PE15 D12 DA12 D12 D12 PD8 D13 DA13 D13 D13 PD9 D14 DA14 D14 D14 PD10 D15 DA15 D15 D15 PH8 D16 - - D16 PH9 D17 - - D17 PH10 D18 - - D18 PH11 D19 - - D19 PH12 D20 - - D20 PH13 D21 - - D21 PH14 D22 - - D22 PH15 D23 - - D23 PI0 D24 - - D24 PI1 D25 - - D25 PI2 D26 - - D26 PI3 D27 - - D27 PI6 D28 - - D28 PI7 D29 - - D29 PI9 D30 - - D30 PI10 D31 - - D31 PD7 NE1 NE1 - - PG6 NE3 - - - PG9 NE2 NE2 NCE - PG10 NE3 NE3 - - PG11 - - - - PG12 NE4 NE4 - - PD3 CLK CLK - - PD4 NOE NOE NOE - PD5 NWE NWE NWE - PD6 NWAIT NWAIT NWAIT - DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 12. FMC pin definition (continued) Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PB7 NADV NADV - - PF6 - - - - PF7 - - - - PF8 - - - - PF9 - - - - PF10 - - - - PG6 - - - - PG7 - - INT - PE0 NBL0 NBL0 - NBL0 PE1 NBL1 NBL1 - NBL1 PI4 NBL2 - - NBL2 PI5 NBL3 - - NBL3 PG8 - - - SDCLK PC0 - - - SDNWE PF11 - - - SDNRAS PG15 - - - SDNCAS PH2 - - - SDCKE0 PH3 - - - SDNE0 PH6 - - - SDNE1 PH7 - - - SDCKE1 PH5 - - - SDNWE PC2 - - - SDNE0 PC3 - - - SDCKE0 PC6 NWAIT NWAIT NWAIT - PB5 - - - SDCKE1 PB6 - - - SDNE1 DocID029041 Rev 6 87/255 101 AF0 AF1 AF2 AF3 AF4 I2C4/UA RT5/TIM 1/2 - TIM2_C H1/TIM2 _ETR TIM5_C H1 PA1 - TIM2_C H2 TIM5_C H2 - - PA2 - TIM2_C H3 TIM5_C H3 TIM9_CH 1 PA3 - TIM2_C H4 TIM5_C H4 PA4 - - PA5 - PA6 AF7 AF8 AF9 AF10 USART2 _CTS UART4_ TX - - - USART2 _RTS UART4_ RX QUADSP I_BK1_IO 3 - - - USART2 _TX SAI2_SC K_B - TIM9_CH 2 - - - USART2 _RX - LCD_B2 - - - SPI1_NS SPI3_NS S/I2S1_ S/I2S3_ WS WS USART2 _CK SPI6_NS S - - TIM2_C H1/TIM2 _ETR - TIM8_CH 1N - SPI1_SC K/I2S1_ CK - - SPI6_SC K - - TIM1_B KIN TIM3_C H1 TIM8_BKI N - SPI1_MI SO - - SPI6_MI SO PA7 - TIM1_C H1N TIM3_C H2 TIM8_CH 1N - SPI1_M OSI/I2S1 _SD - - PA8 MCO1 TIM1_C H1 - TIM8_BKI N2 I2C3_SC L - - PA9 - TIM1_C H2 - - I2C3_SM BA SPI2_SC K/I2S2_ CK PA10 - TIM1_C H3 - - - - DocID029041 Rev 6 Port A - AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD - PA0 TIM8_ET R I2C1/2/3/ 4/USART 1/CEC AF6 - AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS SAI2_SD_ ETH_MII_ B CRS - - - EVEN TOUT SAI2_MC K_B ETH_MII_ RX_CLK/ ETH_RMI I_REF_C LK - - LCD_R2 EVEN TOUT - ETH_MDI O MDIOS_ MDIO - LCD_R1 EVEN TOUT - - LCD_B5 EVEN TOUT - OTG_HS _SOF DCMI_H SYNC LCD_VS YNC EVEN TOUT OTG_HS_ ULPI_CK - - - LCD_R4 EVEN TOUT TIM13_C H1 - - MDIOS_ MDC DCMI_PI XCLK LCD_G2 EVEN TOUT SPI6_MO SI TIM14_C H1 - - - EVEN TOUT USART1 _CK - - OTG_FS_ SOF CAN3_R X UART7_ RX LCD_B3 LCD_R6 EVEN TOUT - USART1 _TX - - - - - DCMI_D 0 LCD_R5 EVEN TOUT - USART1 _RX - LCD_B4 OTG_FS_ ID - MDIOS_ MDIO DCMI_D 1 LCD_B1 EVEN TOUT OTG_HS_ ETH_MII_ ULPI_D0 COL ETH_MII_ RX_DV/E FMC_SD TH_RMII_ NWE CRS_DV STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SYS TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC Port AF5 Pinouts and pin description 88/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping AF0 Port Port A AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS DocID029041 Rev 6 I2C4/UA RT5/TIM 1/2 PA11 - TIM1_C H4 - - - SPI2_NS S/I2S2_ WS UART4_ RX USART1 _CTS - CAN1_R X OTG_FS_ DM - - - LCD_R4 EVEN TOUT PA12 - TIM1_ET R - - - SPI2_SC K/I2S2_ CK UART4_ TX USART1 _RTS SAI2_FS _B CAN1_T X OTG_FS_ DP - - - LCD_R5 EVEN TOUT PA13 JTMSSWDIO - - - - - - - - - - - - - - EVEN TOUT PA14 JTCKSWCLK - - - - - - - - - - - - - - EVEN TOUT PA15 JTDI TIM2_C H1/TIM2 _ETR - - HDMICEC SPI6_NS S UART4_ RTS - - CAN3_TX UART7_ TX - - EVEN TOUT PB0 - TIM1_C H2N TIM3_C H3 TIM8_CH 2N - - DFSDM1 _CKOUT - UART4_ CTS LCD_R3 OTG_HS_ ETH_MII_ ULPI_D1 RXD2 - - LCD_G1 EVEN TOUT PB1 - TIM1_C H3N TIM3_C H4 TIM8_CH 3N - - DFSDM1 _DATIN1 - - LCD_R6 OTG_HS_ ETH_MII_ ULPI_D2 RXD3 - - LCD_G0 EVEN TOUT PB2 - - - - - - SAI1_SD _A SPI3_MO SI/I2S3_ SD - QUADSP I_CLK DFSDM1_ CKIN1 - - - - EVEN TOUT PB3 JTDO/T RACES WO TIM2_C H2 - - - SPI1_SC SPI3_SC K/I2S1_ K/I2S3_ CK CK - SPI6_SC K - SDMMC2 _D2 CAN3_R X UART7_ RX - - EVEN TOUT PB4 NJTRST - TIM3_C H1 - - SPI1_MI SO SPI2_NS S/I2S2_ WS SPI6_MI SO - SDMMC2 _D3 CAN3_TX UART7_ TX - - EVEN TOUT PB5 - UART5_ RX TIM3_C H2 - I2C1_SM BA - SPI6_MO SI CAN2_R X OTG_HS_ ETH_PPS FMC_SD ULPI_D7 _OUT CKE1 DCMI_D 10 LCD_G7 EVEN TOUT PB6 - UART5_ TX TIM4_C H1 HDMICEC I2C1_SC L USART1 _TX - CAN2_T X QUADSPI _BK1_NC S DCMI_D 5 - EVEN TOUT Port B I2C1/2/3/ 4/USART 1/CEC SPI1_NS SPI3_NS S/I2S1_ S/I2S3_ WS WS SPI3_MI SO SPI1_M SPI3_M OSI/I2S1 OSI/I2S3 _SD _SD 89/255 - DFSDM1 _DATIN5 I2C4_SC L FMC_SD NE1 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 AF4 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC I2C1/2/3/ 4/USART 1/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PB7 - - TIM4_C H2 - I2C1_SD A - DFSDM1 _CKIN5 USART1 _RX - - - I2S4_SD A FMC_NL DCMI_V SYNC - EVEN TOUT PB8 - I2C4_SC L TIM4_C H3 TIM10_C H1 I2C1_SC L - DFSDM1 _CKIN7 UART5_ RX - CAN1_R X SDMMC2 _D4 ETH_MII_ TXD3 SDMMC _D4 DCMI_D 6 LCD_B6 EVEN TOUT PB9 - I2C4_SD A TIM4_C H4 TIM11_CH 1 I2C1_SD A SPI2_NS DFSDM1 UART5_T S/I2S2_ _DATIN7 X WS - CAN1_T X SDMMC2 _D5 I2C4_SM BA SDMMC _D5 DCMI_D 7 LCD_B7 EVEN TOUT PB10 - TIM2_C H3 - - I2C2_SC L SPI2_SC DFSDM1 K/I2S2_ _DATIN7 CK USART3 _TX - QUADSP I_BK1_N CS OTG_HS_ ETH_MII_ ULPI_D3 RX_ER - - LCD_G4 EVEN TOUT PB11 - TIM2_C H4 - - I2C2_SD A DFSDM1 _CKIN7 USART3 _RX - - ETH_MII_ OTG_HS_ TX_EN/E ULPI_D4 TH_RMII_ TX_EN - DSI_TE LCD_G5 EVEN TOUT PB12 - TIM1_B KIN - - I2C2_SM BA SPI2_NS DFSDM1 S/I2S2_ _DATIN1 WS USART3 _CK UART5_ RX CAN2_R X ETH_MII_ OTG_HS_ TXD0/ET OTG_HS ULPI_D5 H_RMII_T _ID XD0 - - EVEN TOUT PB13 - TIM1_C H1N - - - SPI2_SC DFSDM1 K/I2S2_ _CKIN1 CK USART3 _CTS UART5_T X CAN2_T X ETH_MII_ OTG_HS_ TXD1/ET ULPI_D6 H_RMII_T XD1 - - - EVEN TOUT PB14 - TIM1_C H2N - TIM8_CH 2N USART1_ TX SPI2_MI SO USART3 _RTS UART4_ RTS TIM12_C H1 SDMMC2 _D0 - OTG_HS _DM - - EVEN TOUT PB15 RTC_RE FIN TIM1_C H3N - TIM8_CH 3N SPI2_M USART1_ DFSDM1 OSI/I2S2 RX _CKIN2 _SD - UART4_ CTS TIM12_C H2 SDMMC2 _D1 - OTG_HS _DP - - EVEN TOUT Port B - DFSDM1 _DATIN2 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DocID029041 Rev 6 SYS Pinouts and pin description 90/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port DocID029041 Rev 6 Port C AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 SYS I2C4/UA RT5/TIM 1/2 PC0 - - - DFSDM1_ CKIN0 - PC1 TRACED 0 - - DFSDM1_ DATAIN0 PC2 - - - PC3 - - PC4 - PC5 I2C1/2/3/ 4/USART 1/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS - SAI2_FS _B - OTG_HS_ ULPI_ST P - FMC_SD NWE - LCD_R5 EVEN TOUT - SPI2_M SAI1_SD OSI/I2S2 _A _SD - - - DFSDM1_ CKIN4 ETH_MD C MDIOS_ MDC - - EVEN TOUT DFSDM1_ CKIN1 - SPI2_MI SO DFSDM1 _CKOUT - - - OTG_HS_ ETH_MII_ FMC_SD ULPI_DIR TXD2 NE0 - - EVEN TOUT - DFSDM1_ DATAIN1 - SPI2_M OSI/I2S2 _SD - - - - OTG_HS_ ETH_MII_ FMC_SD ULPI_NX TX_CLK CKE0 T - - EVEN TOUT - - DFSDM1_ CKIN2 - I2S1_M CK - - SPDIF_R X2 - - ETH_MII_ RXD0/ET FMC_SD H_RMII_ NE0 RXD0 - - EVEN TOUT - - - DFSDM1_ DATAIN2 - - - - SPDIF_R X3 - - ETH_MII_ RXD1/ET FMC_SD H_RMII_ CKE0 RXD1 - - EVEN TOUT PC6 - - TIM3_C H1 TIM8_CH 1 - I2S2_M CK - DFSDM1 _CKIN3 USART6 _TX FMC_NW AIT SDMMC2 _D6 - SDMMC _D6 DCMI_D 0 LCD_HS YNC EVEN TOUT PC7 - - TIM3_C H2 TIM8_ CH2 - - I2S3_M CK DFSDM1 _DATAIN 3 USART6 _RX FMC_NE 1 SDMMC2 _D7 - SDMMC _D7 DCMI_D 1 LCD_G6 EVEN TOUT PC8 TRACED 1 - TIM3_C H3 TIM8_ CH3 - - - UART5_ RTS USART6 _CK FMC_NE 2/FMC_N CE - - SDMMC _D0 DCMI_D 2 - EVEN TOUT PC9 MCO2 - TIM3_C H4 TIM8_ CH4 I2C3_SD A I2S_CKI N - UART5_ CTS - QUADSP I_BK1_IO 0 LCD_G3 - SDMMC _D1 DCMI_D 3 LCD_B2 EVEN TOUT PC10 - - - DFSDM1_ CKIN5 - - SPI3_SC K/I2S3_ CK USART3 _TX - - SDMMC _D2 DCMI_D 8 LCD_R2 EVEN TOUT QUADSP UART4_T I_BK1_IO X 1 Pinouts and pin description 91/255 DFSDM1 _DATIN4 - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PC11 - - - DFSDM1_ DATAIN5 - - SPI3_MI SO USART3 _RX UART4_ RX QUADSP I_BK2_N CS - - SDMMC _D3 DCMI_D 4 - EVEN TOUT PC12 TRACED 3 - - - - - SPI3_M OSI/I2S3 _SD USART3 _CK UART5_T X - - - SDMMC _CK DCMI_D 9 - EVEN TOUT PC13 - - - - - - - - - - - - - - - EVEN TOUT PC14 - - - - - - - - - - - - - - - EVEN TOUT PC15 - - - - - - - - - - - - - - - EVEN TOUT PD0 - - - DFSDM1_ CKIN6 - - DFSDM1 _DATAIN 7 - UART4_ RX CAN1_R X - - FMC_D2 - - EVEN TOUT PD1 - - - DFSDM1_ DATAIN6 - - DFSDM1 _CKIN7 - UART4_T X CAN1_T X - - FMC_D3 - - EVEN TOUT PD2 TRACED 2 - TIM3_ET R - - - - - UART5_ RX - - - SDMMC _CMD DCMI_D 11 - EVEN TOUT PD3 - - - DFSDM1_ CKOUT - SPI2_SC DFSDM1 K/I2S2_ _DATAIN CK 0 USART2 _CTS - - - - FMC_CL K DCMI_D 5 LCD_G7 EVEN TOUT PD4 - - - - - - DFSDM1 _CKIN0 USART2 _RTS - - - - FMC_N OE - - EVEN TOUT PD5 - - - - - - - USART2 _TX - - - - FMC_N WE - - EVEN TOUT PD6 - - - DFSDM1_ CKIN4 - SPI3_M SAI1_SD OSI/I2S3 _A _SD USART2 _RX - - DFSDM1_ DATAIN1 SDMMC2 _CK FMC_N WAIT DCMI_D 10 LCD_B2 EVEN TOUT PD7 - - - DFSDM1_ DATAIN4 - SPI1_M DFSDM1 OSI/I2S1 _CKIN1 _SD USART2 _CK SPDIF_R X0 - - SDMMC2 _CMD FMC_NE 1 - - EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Port C DocID029041 Rev 6 Port D STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SYS Pinouts and pin description 92/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS DocID029041 Rev 6 I2C4/UA RT5/TIM 1/2 PD8 - - - DFSDM1_ CKIN3 - - - USART3 _TX SPDIF_R X1 - - - FMC_D1 3 - - EVEN TOUT PD9 - - - DFSDM1_ DATAIN3 - - - USART3 _RX - - - - FMC_D1 4 - - EVEN TOUT PD10 - - - DFSDM1_ CKOUT - - - USART3 _CK - - - - FMC_D1 5 - LCD_B3 EVEN TOUT PD11 - - - - I2C4_SM BA - - USART3 _CTS - QUADSP SAI2_SD_ I_BK1_IO A 0 - FMC_A1 6/FMC_ CLE - - EVEN TOUT PD12 - - TIM4_C H1 LPTIM1_I N1 I2C4_SC L - - USART3 _RTS - QUADSP SAI2_FS_ I_BK1_IO A 1 - FMC_A1 7/FMC_ ALE - - EVEN TOUT PD13 - - TIM4_C H2 LPTIM1_ OUT I2C4_SD A - - - - QUADSP I_BK1_IO 3 SAI2_SC K_A - FMC_A1 8 - - EVEN TOUT PD14 - - TIM4_C H3 - - - - - UART8_ CTS - - - FMC_D0 - - EVEN TOUT PD15 - - TIM4_C H4 - - - - - UART8_ RTS - - - FMC_D1 - - EVEN TOUT PE0 - - TIM4_ET LPTIM1_E R TR - - - - UART8_ Rx - SAI2_MC K_A - FMC_NB L0 DCMI_D 2 - EVEN TOUT PE1 - - - LPTIM1_I N2 - - - - UART8_T x - - - FMC_NB L1 DCMI_D 3 - EVEN TOUT PE2 TRACEC LK - - - - SPI4_SC K SAI1_M CLK_A - - QUADSP I_BK1_IO 2 - ETH_MII_ TXD3 FMC_A2 3 - - EVEN TOUT PE3 TRACED 0 - - - - - SAI1_SD _B - - - - - FMC_A1 9 - - EVEN TOUT Port D Port E I2C1/2/3/ 4/USART 1/CEC 93/255 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PE4 TRACED 1 - - - - SPI4_NS SAI1_FS S _A - - - DFSDM1_ DATAIN3 - FMC_A2 0 DCMI_D 4 LCD_B0 EVEN TOUT PE5 TRACED 2 - - TIM9_CH 1 - SPI4_MI SO SAI1_SC K_A - - - DFSDM1_ CKIN3 - FMC_A2 1 DCMI_D 6 LCD_G0 EVEN TOUT PE6 TRACED 3 TIM1_B KIN2 - TIM9_CH 2 - SPI4_M OSI SAI1_SD _A - - - SAI2_MC K_B - FMC_A2 2 DCMI_D 7 LCD_G1 EVEN TOUT PE7 - TIM1_ET R - - - - DFSDM1 _DATAIN 2 - UART7_ Rx - QUADSPI _BK2_IO0 - FMC_D4 - - EVEN TOUT PE8 - TIM1_C H1N - - - - DFSDM1 _CKIN2 - UART7_T x - QUADSPI _BK2_IO1 - FMC_D5 - - EVEN TOUT PE9 - TIM1_C H1 - - - - DFSDM1 _CKOUT - UART7_ RTS - QUADSPI _BK2_IO2 - FMC_D6 - - EVEN TOUT PE10 - TIM1_C H2N - - - - DFSDM1 _DATAIN 4 - UART7_ CTS - QUADSPI _BK2_IO3 - FMC_D7 - - EVEN TOUT PE11 - TIM1_C H2 - - - SPI4_NS DFSDM1 S _CKIN4 - - - SAI2_SD_ B - FMC_D8 - LCD_G3 EVEN TOUT PE12 - TIM1_C H3N - - - DFSDM1 SPI4_SC _DATAIN K 5 - - - SAI2_SC K_B - FMC_D9 - LCD_B4 EVEN TOUT PE13 - TIM1_C H3 - - - SPI4_MI SO DFSDM1 _CKIN5 - - - SAI2_FS_ B - FMC_D1 0 - LCD_DE EVEN TOUT PE14 - TIM1_C H4 - - - SPI4_M OSI - - - - SAI2_MC K_B - FMC_D1 1 - LCD_CL K EVEN TOUT PE15 - TIM1_B KIN - - - - - - - - - - FMC_D1 2 - LCD_R7 EVEN TOUT Port E I2C1/2/3/ 4/USART 1/CEC STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DocID029041 Rev 6 SYS Pinouts and pin description 94/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port DocID029041 Rev 6 Port F AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PF0 - - - - I2C2_SD A - - - - - - - FMC_A0 - - EVEN TOUT PF1 - - - - I2C2_SC L - - - - - - - FMC_A1 - - EVEN TOUT PF2 - - - - I2C2_SM BA - - - - - - - FMC_A2 - - EVEN TOUT PF3 - - - - - - - - - - - - FMC_A3 - - EVEN TOUT PF4 - - - - - - - - - - - - FMC_A4 - - EVEN TOUT PF5 - - - - - - - - - - - - FMC_A5 - - EVEN TOUT PF6 - - - TIM10_C H1 - SPI5_NS SAI1_SD S _B - UART7_ Rx QUADSP I_BK1_IO 3 - - - - - EVEN TOUT PF7 - - - TIM11_CH 1 - SPI5_SC K SAI1_M CLK_B - QUADSP UART7_T I_BK1_IO x 2 - - - - - EVEN TOUT PF8 - - - - - SPI5_MI SO SAI1_SC K_B - UART7_ RTS TIM13_C H1 QUADSPI _BK1_IO0 - - - - EVEN TOUT PF9 - - - - - SPI5_M OSI SAI1_FS _B - UART7_ CTS TIM14_C H1 QUADSPI _BK1_IO1 - - - - EVEN TOUT PF10 - - - - - - - - - QUADSP I_CLK - - - DCMI_D 11 LCD_DE EVEN TOUT PF11 - - - - - SPI5_M OSI - - - - SAI2_SD_ B - FMC_SD NRAS DCMI_D 12 - EVEN TOUT I2C1/2/3/ 4/USART 1/CEC 95/255 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PF12 - - - - - - - - - - - - FMC_A6 - - EVEN TOUT PF13 - - - - I2C4_SM BA - DFSDM1 _DATAIN 6 - - - - - FMC_A7 - - EVEN TOUT PF14 - - - - I2C4_SC L - DFSDM1 _CKIN6 - - - - - FMC_A8 - - EVEN TOUT PF15 - - - - I2C4_SD A - - - - - - - FMC_A9 - - EVEN TOUT PG0 - - - - - - - - - - - - FMC_A1 0 - - EVEN TOUT PG1 - - - - - - - - - - - - FMC_A1 1 - - EVEN TOUT PG2 - - - - - - - - - - - - FMC_A1 2 - - EVEN TOUT PG3 - - - - - - - - - - - - FMC_A1 3 - - EVEN TOUT PG4 - - - - - - - - - - - - FMC_A1 4/FMC_ BA0 - - EVEN TOUT PG5 - - - - - - - - - - - - FMC_A1 5/FMC_ BA1 - - EVEN TOUT PG6 - - - - - - - - - - - - FMC_NE 3 DCMI_D 12 LCD_R7 EVEN TOUT PG7 - - - - - - SAI1_M CLK_A - USART6 _CK - - - FMC_IN T DCMI_D 13 LCD_CL K EVEN TOUT I2C1/2/3/ 4/USART 1/CEC DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SYS Port F Port G AF4 Pinouts and pin description 96/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 DocID029041 Rev 6 AF11 AF12 PG8 - - - - - SPI6_NS S - SPDIF_R X2 USART6 _RTS PG9 - - - - - SPI1_MI SO - SPDIF_R X3 USART6 _RX PG10 - - - - - SPI1_NS S/I2S1_ WS - - - PG11 - - - - - SPI1_SC K/I2S1_ CK - SPDIF_R X0 PG12 - - - LPTIM1_I N1 - SPI6_MI SO - PG13 TRACED 0 - - LPTIM1_ OUT - SPI6_SC K PG14 TRACED 1 - - LPTIM1_E TR - PG15 - - - - - - - ETH_PPS FMC_SD _OUT CLK AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS - LCD_G7 EVEN TOUT QUADSP SAI2_FS_ I_BK2_IO B 2 SDMMC2 _D0 FMC_NE 2/FMC_ NCE DCMI_V SYNC - EVEN TOUT LCD_G3 SAI2_SD_ B SDMMC2 _D1 FMC_NE 3 DCMI_D 2 LCD_B2 EVEN TOUT - - SDMMC2 _D2 ETH_MII_ TX_EN/E TH_RMII_ TX_EN - DCMI_D 3 LCD_B3 EVEN TOUT SPDIF_R X1 USART6 _RTS LCD_B4 - SDMMC2 _D3 FMC_NE 4 - LCD_B1 EVEN TOUT - - USART6 _CTS - - ETH_MII_ TXD0/ET FMC_A2 H_RMII_T 4 XD0 - LCD_R0 EVEN TOUT SPI6_M OSI - - USART6 _TX QUADSP I_BK2_IO 3 - ETH_MII_ TXD1/ET FMC_A2 H_RMII_T 5 XD1 - LCD_B0 EVEN TOUT - - - USART6 _CTS - - DCMI_D 13 - EVEN TOUT - FMC_SD NCAS 97/255 Pinouts and pin description I2C4/UA RT5/TIM 1/2 Port G AF10 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD SYS I2C1/2/3/ 4/USART 1/CEC AF9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS SYS I2C4/UA RT5/TIM 1/2 PH0 - - - - - - - - - - - - - - - EVEN TOUT PH1 - - - - - - - - - - - - - - - EVEN TOUT PH2 - - - LPTIM1_I N2 - - - - - QUADSP I_BK2_IO 0 SAI2_SC K_B ETH_MII_ FMC_SD CRS CKE0 - LCD_R0 EVEN TOUT PH3 - - - - - - - - - QUADSP I_BK2_IO 1 SAI2_MC K_B ETH_MII_ FMC_SD COL NE0 - LCD_R1 EVEN TOUT PH4 - - - - I2C2_SC L - - - - LCD_G5 OTG_HS_ ULPI_NX T - - - LCD_G4 EVEN TOUT PH5 - - - - I2C2_SD A SPI5_NS S - - - - - - FMC_SD NWE - - EVEN TOUT PH6 - - - - I2C2_SM BA SPI5_SC K - - - TIM12_C H1 - ETH_MII_ FMC_SD RXD2 NE1 DCMI_D 8 - EVEN TOUT PH7 - - - - I2C3_SC L SPI5_MI SO - - - - - ETH_MII_ FMC_SD RXD3 CKE1 DCMI_D 9 - EVEN TOUT PH8 - - - - I2C3_SD A - - - - - - - FMC_D1 6 DCMI_H SYNC LCD_R2 EVEN TOUT PH9 - - - - I2C3_SM BA - - - - TIM12_C H2 - - FMC_D1 7 DCMI_D 0 LCD_R3 EVEN TOUT PH10 - - TIM5_C H1 - I2C4_SM BA - - - - - - - FMC_D1 8 DCMI_D 1 LCD_R4 EVEN TOUT PH11 - - TIM5_C H2 - I2C4_SC L - - - - - - - FMC_D1 9 DCMI_D 2 LCD_R5 EVEN TOUT PH12 - - TIM5_C H3 - I2C4_SD A - - - - - - - FMC_D2 0 DCMI_D 3 LCD_R6 EVEN TOUT PH13 - - - TIM8_CH 1N - - - - UART4_T X CAN1_T X - - FMC_D2 1 - LCD_G2 EVEN TOUT I2C1/2/3/ 4/USART 1/CEC STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DocID029041 Rev 6 Port H AF1 Pinouts and pin description 98/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PH14 - - - TIM8_CH 2N - - - - UART4_ RX CAN1_R X - - FMC_D2 2 DCMI_D 4 LCD_G3 EVEN TOUT PH15 - - - TIM8_CH 3N - - - - - - - - FMC_D2 3 DCMI_D 11 LCD_G4 EVEN TOUT PI0 - - TIM5_C H4 - - SPI2_NS S/I2S2_ WS - - - - - - FMC_D2 4 DCMI_D 13 LCD_G5 EVEN TOUT PI1 - - - TIM8_BKI N2 - SPI2_SC K/I2S2_ CK - - - - - - FMC_D2 5 DCMI_D 8 LCD_G6 EVEN TOUT PI2 - - - TIM8_CH 4 - SPI2_MI SO - - - - - - FMC_D2 6 DCMI_D 9 LCD_G7 EVEN TOUT PI3 - - - TIM8_ET R - SPI2_M OSI/I2S2 _SD - - - - - - FMC_D2 7 DCMI_D 10 - EVEN TOUT PI4 - - - TIM8_BKI N - - - - - - SAI2_MC K_A - FMC_NB L2 DCMI_D 5 LCD_B4 EVEN TOUT PI5 - - - TIM8_CH 1 - - - - - - SAI2_SC K_A - FMC_NB L3 DCMI_V SYNC LCD_B5 EVEN TOUT PI6 - - - TIM8_CH 2 - - - - - - SAI2_SD_ A - FMC_D2 8 DCMI_D 6 LCD_B6 EVEN TOUT PI7 - - - TIM8_CH 3 - - - - - - SAI2_FS_ A - FMC_D2 9 DCMI_D 7 LCD_B7 EVEN TOUT PI8 - - - - - - - - - - - - - - - EVEN TOUT PI9 - - - - - - - - UART4_ RX CAN1_R X - - FMC_D3 0 - LCD_VS YNC EVEN TOUT PI10 - - - - - - - - - - - ETH_MII_ RX_ER FMC_D3 1 - LCD_HS YNC EVEN TOUT PI11 - - - - - - - - - LCD_G6 OTG_HS_ ULPI_DIR - - - - EVEN TOUT I2C1/2/3/ 4/USART 1/CEC DocID029041 Rev 6 99/255 Pinouts and pin description SYS Port H Port I AF3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PI12 - - - - - - - - - - - - - - LCD_HS YNC EVEN TOUT PI13 - - - - - - - - - - - - - - LCD_VS YNC EVEN TOUT PI14 - - - - - - - - - - - - - - LCD_CL K EVEN TOUT PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0 EVEN TOUT PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1 EVEN TOUT PJ1 - - - - - - - - - - - - - - LCD_R2 EVEN TOUT PJ2 - - - - - - - - - - - - - DSI_TE LCD_R3 EVEN TOUT PJ3 - - - - - - - - - - - - - - LCD_R4 EVEN TOUT PJ4 - - - - - - - - - - - - - - LCD_R5 EVEN TOUT PJ5 - - - - - - - - - - - - - - LCD_R6 EVEN TOUT PJ6 - - - - - - - - - - - - - - LCD_R7 EVEN TOUT PJ7 - - - - - - - - - - - - - - LCD_G0 EVEN TOUT PJ8 - - - - - - - - - - - - - - LCD_G1 EVEN TOUT PJ9 - - - - - - - - - - - - - - LCD_G2 EVEN TOUT PJ10 - - - - - - - - - - - - - - LCD_G3 EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Port I DocID029041 Rev 6 Port J STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SYS Pinouts and pin description 100/255 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) AF0 Port Port J AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS DocID029041 Rev 6 I2C4/UA RT5/TIM 1/2 PJ11 - - - - - - - - - - - - - - LCD_G4 EVEN TOUT PJ12 - - - - - - - - - LCD_G3 - - - - LCD_B0 EVEN TOUT PJ13 - - - - - - - - - LCD_G4 - - - - LCD_B1 EVEN TOUT PJ14 - - - - - - - - - - - - - - LCD_B2 EVEN TOUT PJ15 - - - - - - - - - - - - - - LCD_B3 EVEN TOUT PK0 - - - - - - - - - - - - - - LCD_G5 EVEN TOUT PK1 - - - - - - - - - - - - - - LCD_G6 EVEN TOUT PK2 - - - - - - - - - - - - - - LCD_G7 EVEN TOUT PK3 - - - - - - - - - - - - - - LCD_B4 EVEN TOUT PK4 - - - - - - - - - - - - - - LCD_B5 EVEN TOUT PK5 - - - - - - - - - - - - - - LCD_B6 EVEN TOUT PK6 - - - - - - - - - - - - - - LCD_B7 EVEN TOUT PK7 - - - - - - - - - - - - - - LCD_DE EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Port K 101/255 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued) Memory mapping 4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping The memory map is shown in Figure 22. Figure 22. Memory map [)))))))) 5HVHUYHG [([)))))))) &RUWH[0LQWHUQDO SHULSKHUDOV [([())))) $+% [['))))))) 5HVHUYHG [&[))))))) [%)) $+% 0E\WH %ORFN &RUWH[0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [[))))))) [)))) [( ['))))))) 0E\WH %ORFN )0& [' [&))))))) $+% 0E\WH %ORFN )0& [& [))))))) [ [))))))) 0E\WH %ORFN 4XDG63,DQG )0&EDQN [ 5HVHUYHG [&[)))) [%)) 0E\WH %ORFN )0&EDQNWR EDQN [ [))))))) $3% 0E\WH %ORFN 3HULSKHUDOV [ [))))))) 0E\WH %ORFN 65$0 [ [))))))) 0E\WH %ORFN [ 5HVHUYHG [[))))))) 65$0.% [&[)))) 65$0.% [[%))) '7&0.% [[)))) 5HVHUYHG [)))[))))))) 2SWLRQ%\WHV [)))[)))) 5HVHUYHG [[))()))) 5HVHUYHG [ [[)))) [))) $3% )ODVKPHPRU\RQ$;,0LQWHUIDFH [[))))) 5HVHUYHG [[)))))) )ODVKPHPRU\RQ,7&0LQWHUIDFH [[))))) 5HVHUYHG 102/255 [[))))) 6\VWHPPHPRU\ [[('%) 5HVHUYHG [[))))) ,7&05$0 [[))) DocID029041 Rev 6 [ 06Y9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping Table 14. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses(1) Bus Boundary address - 0xE00F FFFF - 0xFFFF FFFF Reserved Cortex-M7 0xE000 0000 - 0xE00F FFFF Cortex-M7 internal peripherals 0xD000 0000 - 0xDFFF FFFF FMC bank 6 0xC000 0000 - 0xCFFF FFFF FMC bank 5 0xA000 2000 - 0xBFFF FFFF Reserved 0xA000 1000 - 0xA000 1FFF Quad-SPI control register 0xA000 0000- 0xA000 0FFF FMC control register 0x9000 0000 - 0x9FFF FFFF Quad-SPI 0x8000 0000 - 0x8FFF FFFF FMC bank 3 0x7000 0000 - 0x7FFF FFFF FMC bank 2 0x6000 0000 - 0x6FFF FFFF FMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved 0x5006 0800 - 0x5006 0BFF RNG 0x5005 2000 - 0x5005 FFFF Reserved 0x5005 1000 - 0x5005 1FFF JPEG codec 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS AHB3 - AHB2 DocID029041 Rev 6 Peripheral 103/255 106 Memory mapping STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 14. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses(1) (continued) Bus Boundary address Peripheral - 0x4008 0000- 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 BC00- 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Chrom-ART (DMA2D) 0x4002 9400 - 0x4002 AFFF Reserved 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF ETHERNET MAC 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF AHB1 104/255 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0X4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0X4002 3400 - 0X4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF GPIOK 0x4002 2400 - 0x4002 27FF GPIOJ 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0X4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping Table 14. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses(1) (continued) Bus Boundary address - 0x4001 7C00 - 0x4001 FFFF Reserved 0x4001 7800 - 0x4001 7BFF MDIOS 0x4001 7400 - 0x4001 77FF DFSDM1 0x4001 6C00 - 0x4001 73FF DSI Host 0x4001 6800 - 0x4001 6BFF LCD-TFT 0x4001 6000 - 0x4001 67FF Reserved 0x4001 5C00 - 0x4001 5FFF SAI2 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF SPI6 0x4001 5000 - 0x4001 53FF SPI5 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI4 0x4001 3000 - 0x4001 33FF SPI1/I2S1 0x4001 2C00 - 0x4001 2FFF SDMMC1 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1C00 - 0x4001 1FFF SDMMC2 0x4001 1800 - 0x4001 1BFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 APB2 DocID029041 Rev 6 Peripheral 105/255 106 Memory mapping STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 14. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses(1) (continued) Bus Boundary address - 0x4000 8000- 0x4000 FFFF Reserved 0x4000 7C00 - 0x4000 7FFF UART8 0x4000 7800 - 0x4000 7BFF UART7 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF HDMI-CEC 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF I2C4 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF SPDIFRX 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF CAN3 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF LPTIM1 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 APB1 1. The gray color is used for reserved Flash memory addresses. 106/255 DocID029041 Rev 6 Peripheral STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5 5.1 Electrical characteristics Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 23. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 24. Figure 23. Pin loading conditions Figure 24. Pin input voltage -#5PIN -#5PIN #P& 6). -36 DocID029041 Rev 6 -36 107/255 220 Electrical characteristics 5.1.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Power supply scheme Figure 25. STM32F769xx/STM32F779xx power supply scheme 9%$7 %DFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV EDFNXS5$0 287 *3 ,2V ,1 /HYHOVKLIWHU 3RZHUVZLWFK 9%$7 WR9 ,2 /RJLF 287 3*>@3'>@ ,1 i) 9'' 9''86% ,2 /RJLF .HUQHOORJLF &38 GLJLWDO 5$0 9&$3B 9&$3B 9'' iQ) i) /HYHOVKLIWHU 9''6'00& 9ROWDJH UHJXODWRU 966 )ODVKPHPRU\ %<3$66B5(* 9''86% Q) ) 27*)6 3+< 9'''6, 9&$3'6, 9'''6, ) 966'6, 3'5B21 9'' '6, 3+< 5HVHW FRQWUROOHU 9''$ 95() Q) ) '6, YROWDJH UHJXODWRU Q) ) 95() 95() $'& $QDORJ 5&V3// 966$ 06Y9 108/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 26. STM32F767xx/STM32F777xx power supply scheme 9 %$7 9 ''6'00& 287 3*>@3'>@ ,1 287 3$>@3%>@ 9 ''86% ,1 9''86% /HYHOVKLIWHU ,1 9 ''6'00& /HYHOVKLIWHU *3 ,2 V /HYHOVKLIWHU 287 Q) ) EDFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV EDFNXS5$0 3RZHUVZLWFK 9%$7 WR9 ,2 /RJLF ,2 /RJLF ,2 /RJLF Q) ) 27*)6 3+< i) 9 '' 9 '' iQ) i) .HUQHOORJLF &38 GLJLWDO 5$0 9 &$3B 9 &$3B 9ROWDJH UHJXODWRU 9 66 )ODVKPHPRU\ %<3$66B5(* 3'5B21 9 '' 9 ''$ 9 5() Q) ) 5HVHW FRQWUROOHU Q) ) 9 5() 9 5() $'& $QDORJ 5&V3// 9 66$ 06Y9 1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.18: Power supply supervisor and Section 2.19: Voltage regulator. 2. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. DocID029041 Rev 6 109/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 5.1.7 Current consumption measurement Figure 27. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics, Table 16: Current characteristics, and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand. Table 15. Voltage characteristics Symbol VDD-VSS VIN Ratings Min Max - 0.3 4.0 Input voltage on FT pins(3) VSS - 0.3 VDD+4.0 Input voltage on TTa pins VSS - 0.3 4.0 Input voltage on any other pin VSS - 0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins(4) - 50 External main supply voltage (including VDDA, VDD, VBAT, VDDUSB, VDDDSI (1) and VDDSDMMC)(2) Input voltage on BOOT pin |VDDx| |VSSX -VSS| VESD(HBM) 110/255 Electrostatic discharge voltage (human body model) DocID029041 Rev 6 see Section 5.3.18: Absolute maximum ratings (electrical sensitivity) Unit V mV - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Applicable only for STM32F7x9 sales types. 2. All main power (VDD, VDDA, VDDSDMMC, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 3. VIN maximum value must always be respected. Refer to Table 16 for the values of the maximum allowed injected current. 4. Include VREF- pin. Table 16. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source)(1) IVSS (1) IVDDUSB 420 Total current out of sum of all VSS_x ground lines (sink) -420 Total current into VDDUSB power line (source) 25 IVDDSDMMC Total current into VDDSDMMC power line (source) IVDD IVDDSDMMC IVSS IIO IIO IINJ(PIN) IINJ(PIN)(4) 60 Maximum current into each VDD_x power line (source)(1) 100 Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] 100 Maximum current out of each VSS_x ground line (sink) (1) -100 Output current sunk by any I/O and control pin 25 Output current sourced by any I/Os and control pin -25 Total output current sunk by sum of all I/O and control pins (2) 120 Total output current sunk by sum of all USB I/Os 25 Total output current sunk by sum of all SDMMC I/Os 120 Total output current sourced by sum of all I/Os and control pins except USB I/Os(2) -120 Injected current on FT, FTf, RST and B pins Unit (3) mA -5/+0 Injected current on TTa pins(4) 5 Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 15: Voltage characteristics for the values of the maximum allowed input voltage. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 17. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID029041 Rev 6 Value - 65 to +150 125 Unit C 111/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3 Operating conditions 5.3.1 General operating conditions Table 18. General operating conditions Symbol Conditions(1) Parameter Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01), Regulator ON, over-drive OFF fHCLK Internal AHB clock frequency Power Scale 2 (VOS[1:0] bits in PWR_CR register = 0x10), Regulator ON Power Scale 1 (VOS[1:0] bits in PWR_CR register= 0x11), Regulator ON fPCLK1 Internal APB1 clock frequency fPCLK2 Internal APB2 clock frequency VDD (4)(5) VDDA VDDUSB VBAT Analog operating voltage (ADC limited to 2.4 M samples) USB supply voltage (supply voltage for PA11,PA12, PB14 and PB15 pins) Backup operating voltage SDMMC2 supply voltage (supply VDDSDMMC voltage for PG[12:9] and PD6 pins) VDDDSI 112/255 DSI system operating Overdrive ON Overdrive OFF Overdrive ON Typ Max 0 - 144 - 168 - 180 - 180 - 216(2) - 45 Over-drive ON 0 - 54 Over-drive OFF 0 - 90 Over-drive ON 0 - 108 1.7(3) - 3.6 1.7(3) - 2.4 2.4 - 3.6 USB not used 1.7 3.3 3.6 USB used 3.0 - 3.6 1.65 - 3.6 1.7 - 3.6 1.7 - 3.6 Must be the same potential as VDD(6) It can be different from VDD - DocID029041 Rev 6 MHz 0 0 - Unit 0 Over-drive OFF Standard operating voltage Analog operating voltage (ADC limited to 1.2 M samples) Overdrive OFF Min - V STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 18. General operating conditions (continued) Symbol Min Typ Max Power Scale 3 ((VOS[1:0] bits in PWR_CR register = 0x01), 144 MHz HCLK max frequency 1.08 1.14 1.20 Power Scale 2 ((VOS[1:0] bits in PWR_CR register = 0x10), 168 MHz HCLK max frequency with over-drive OFF or 180 MHz with over-drive ON 1.20 1.26 1.32 Power Scale 1 ((VOS[1:0] bits in PWR_CR register = 0x11), 180 MHz HCLK max frequency with over-drive OFF or 216 MHz with over-drive ON 1.26 1.32 1.40 Regulator OFF: 1.2 V external voltage must be supplied from external regulator on VCAP_1/VCAP_2 pins(7) Max frequency 144 MHz 1.10 1.14 1.20 Max frequency 168MHz 1.20 1.26 1.32 Max frequency 180 MHz 1.26 1.32 1.38 Input voltage on RST and FT pins(8) 2 V VDD 3.6 V - 0.3 - 5.5 VDD 2 V - 0.3 - 5.2 Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins V12 VIN PD TA TJ Conditions(1) Parameter Unit V Input voltage on TTa pins - - 0.3 - VDDA+ 0.3 Input voltage on BOOT pin - 0 - 9 LQFP100 - - 465 WLCSP180 - - 641 LQFP144 - - 500 LQFP176 - - 526 UFBGA176 - - 513 LQFP208 - - 1053 TFBGA216 - - 690 TFBGA100 - - 552 Ambient temperature for 6 suffix Maximum power dissipation version Low power dissipation(10) - 40 - 85 - 40 - 105 Ambient temperature for 7 suffix Maximum power dissipation version Low power dissipation(10) - 40 - 105 - 40 - 125 6 suffix version - 40 - 105 7 suffix version - 40 - 125 Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(9) Junction temperature range mW C C C 1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V. 2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version). 3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 4. When the ADC is used, refer to Table 72: ADC characteristics. 5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. DocID029041 Rev 6 113/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 7. The over-drive mode is not supported when the internal regulator is OFF. 8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. Table 19. Limitations depending on the operating power supply range Maximum Flash Maximum HCLK memory access frequency vs Flash frequency with memory wait states no wait states (1)(2) (fFlashmax) Possible Flash memory operations Operating power supply range ADC operation VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz 180 MHz with 8 wait No I/O states and over-drive compensation OFF 8-bit erase and program operations only VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps 22 MHz 216 MHz with 9 wait No I/O states and over-drive compensation ON 16-bit erase and program operations VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps 24 MHz 216 MHz with 8 wait I/O compensation states and over-drive works ON 16-bit erase and program operations VDD = 2.7 to 3.6 V(4) Conversion time up to 2.4 Msps 30 MHz 216 MHz with 6 wait I/O compensation states and over-drive works ON 32-bit erase and program operations I/O operation 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a performance equivalent to 0-wait state program execution. 3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V. 5.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP1/VCAP2 pins. CEXT is specified in Table 20. Figure 28. External capacitor CEXT & (65 5/HDN 069 1. Legend: ESR is the equivalent series resistance. 114/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 20. VCAP1/VCAP2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F ESR ESR of external capacitor <2 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 21. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 5.3.4 Parameter Min Max VDD rise time rate 20 VDD fall time rate 20 Unit s/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 22. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 VDD fall time rate Power-down 20 VCAP_1 and VCAP_2 rise time rate Power-up 20 VCAP_1 and VCAP_2 fall time rate Power-down 20 Unit s/V 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below 1.08 V. 5.3.5 Reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. DocID029041 Rev 6 115/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 23. Reset and power control block characteristics Symbol VPVD Parameter Conditions Programmable voltage detector level selection VPVDhyst(1) PVD hysteresis VPOR/PDR Power-on/power-down reset threshold Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 V PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V PLS[2:0]=101 (falling edge) 2.65 2.84 2.92 V PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 V PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 V - 100 - mV Falling edge 1.60 1.68 1.76 V Rising edge 1.64 1.72 1.80 V - 40 - mV - VPDRhyst(1) PDR hysteresis 116/255 - VBOR1 Brownout level 1 threshold Falling edge 2.13 2.19 2.24 V Rising edge 2.23 2.29 2.33 V VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V Rising edge 2.53 2.59 2.63 V VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V Rising edge 2.85 2.92 2.97 V VBORhyst(1) BOR hysteresis - - 100 - mV TRSTTEMPO (1)(2) POR reset temporization - 0.5 1.5 3.0 ms IRUSH(1) InRush current on voltage regulator poweron (POR or wakeup from Standby) - - 160 250 mA ERUSH(1) InRush energy on voltage regulator power- VDD = 1.7 V, TA = 105 C, on (POR or wakeup IRUSH = 171 mA for 31 s from Standby) - - 5.4 C DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by design. 2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is read by the user application code. 5.3.6 Over-drive switching characteristics When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. The over-drive switching characteristics are given in Table 24. They are subject to general operating conditions for TA. Table 24. Over-drive switching characteristics(1) Symbol Tod_swen Tod_swdis Parameter Over_drive switch enable time Conditions Min Typ Max HSI - 45 - HSE max for 4 MHz and min for 26 MHz 45 - 100 External HSE 50 MHz - 40 - HSI - 20 - 20 - 80 - 15 - HSE max for 4 MHz Over_drive switch and min for 26 MHz. disable time External HSE 50 MHz Unit s 1. Guaranteed by design. 5.3.7 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 27: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. DocID029041 Rev 6 117/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in input mode with a static value at VDD or VSS (no load). * All peripherals are disabled except if it is explicitly mentioned. * The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 19: Limitations depending on the operating power supply range). * When the regulator is ON, the voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows: - Scale 3 for fHCLK 144 MHz - Scale 2 for 144 MHz < fHCLK 168 MHz - Scale 1 for 168 MHz < fHCLK 216 MHz. The over-drive is only ON at 216 MHz. * When the regulator is OFF, the V12 is provided externally as described in Table 18: General operating conditions: * The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. * External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz. * The typical current consumption values are obtained for 1.7 V VDD 3.6 V voltage range and for TA= 25 C unless otherwise specified. * The maximum values are obtained for 1.7 V VDD 3.6 V voltage range and a maximum ambient temperature (TA) unless otherwise specified. * For the voltage range 1.7 V VDD 3.6 V, the maximum frequency is 180 MHz. Table 25. Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ 216 193 221(4) 258(4) - 200 179 207 244 279 210(4) 238(4) (4) 180 159 168 142 156 187 211 144 122 135 167 190 60 49 55 81 103 25 23 28 54 76 216 95 107(4) 153(4) - 200 88 100 146 180 180 78 88(4) 122(4) 147(4) 168 70 78 109 133 144 60 68 99 123 60 24 29 55 76 25 12 16 42 63 1. Guaranteed by characterization results, unless otherwise specified. 118/255 Unit TA = 25 C TA = 85 C TA = 105 C DocID029041 Rev 6 176 mA STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 4. Guaranteed by test in production. Table 26. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 190 219 255 - 200 177 205 241 268 180 157 173 208 228 168 139 153 185 204 144 107 117 144 161 60 48 54 81 98 25 23 28 54 71 216 92 104 150 - 200 86 97 143 170 180 76 85 119 140 168 67 75 107 126 144 52 58 84 101 60 23 28 54 71 25 11 15 42 56 TA = 25 C TA = 85 C TA = 105 C mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. DocID029041 Rev 6 119/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 27. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 190 219 255 - 200 177 204 242 268 180 157 173 208 228 168 139 153 185 204 144 107 117 144 161 60 48 54 81 98 25 23 28 54 71 216 92 104 150 - 200 86 97 143 170 180 76 85 119 140 168 67 75 107 126 144 52 58 84 101 60 23 28 54 71 25 11 15 42 59 TA = 25 C TA = 85 C TA = 105 C mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 120/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 28. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 190 209 255 - 200 177 194 241 268 180 160 175 211 232 168 144 156 189 209 144 115 125 152 170 60 56 62 89 107 25 27 32 59 79 216 92 103 150 - 200 86 96 243 171 180 79 87 123 144 168 71 79 111 131 144 60 65 92 110 60 32 36 63 80 25 16 20 46 64 TA= 25 C TA=85 C TA=105 C mA 1. Guaranteed by characterization results, unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. DocID029041 Rev 6 121/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 29. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 176 194 240 - 200 164 181 227 255 180 149 163 198 220 168 133 145 178 198 144 106 116 143 161 60 54 60 87 105 25 27 31 58 76 216 77 88 135 - 200 72 82 129 157 180 67 75 110 131 168 60 67 99 120 144 50 56 83 101 60 29 34 60 78 25 15 19 45 63 TA= 25 C TA=85 C TA=105 C mA 1. Guaranteed by characterization results, unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 122/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 30. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) on ITCM interface (ART disabled), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 215 242 281 - 200 200 218 265 293 180 185 200 237 258 168 166 179 213 233 144 134 144 172 190 60 61 68 95 112 25 29 34 61 78 216 118 129 177 - 200 110 120 168 196 180 104 113 149 170 168 94 102 135 155 144 79 85 113 130 60 37 42 69 86 25 18 22 48 66 TA= 25 C TA=85 C TA=105 C mA 1. Guaranteed by characterization results, unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. DocID029041 Rev 6 123/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 31. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode) on ITCM interface (ART disabled), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 191 218 255 - 200 178 195 241 269 180 164 179 214 236 168 147 160 192 212 144 121 130 157 175 60 60 66 93 111 25 28 33 59 77 216 93 104 150 - 200 87 97 144 171 180 83 92 126 148 168 75 82 114 134 144 65 71 97 115 60 35 40 66 84 25 16 20 47 64 TA= 25 C TA=85 C TA=105 C mA 1. Guaranteed by characterization results, unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 124/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 32. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF Max(1) Symbol Parameter IDD12/ IDD Supply current in RUN mode from V12 and VDD supply Conditions All Peripherals Enabled(2)(3) All Peripherals Disabled(3) Typ fHCLK (MHz) TA= 25 C TA= 85 C Unit TA= 105 C IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD 180 152 1 167 2 200 2 220 2 168 136 1 148 2 179 2 198 2 144 105 1 115 2 141 2 158 2 60 47 1 53 2 79 2 96 2 25 22 1 27 2 53 2 70 2 180 74 1 83 2 116 2 136 2 168 65 1 73 2 104 2 123 2 144 50 1 57 2 83 2 100 2 60 22 1 27 2 53 2 70 2 25 10 1 14 2 41 2 58 2 mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. Table 33. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF Max(1) Symbol Parameter IDD12/ IDD Supply current in RUN mode from V12 and VDD supply Conditions All Peripherals Enabled(2)(3) All Peripherals Disabled(3) Typ fHCLK (MHz) TA= 25 C TA= 85 C TA= 105 C IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD 180 152 1 167 2 200 2 220 2 168 136 1 148 2 179 2 198 2 144 105 1 115 2 141 2 158 2 60 47 1 53 2 79 2 96 2 25 22 1 27 2 53 2 70 2 180 74 1 82 2 114 2 137 2 168 65 1 73 2 104 2 123 2 144 50 1 57 2 83 2 100 2 60 22 1 27 2 53 2 70 2 25 10 1 14 2 41 2 58 2 DocID029041 Rev 6 Unit mA 125/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. Table 34. Typical and maximum current consumption in Sleep mode, regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2) IDD Supply current in Sleep mode All peripherals disabled fHCLK (MHz) Typ Unit 216 128 144(3) 190(3) - 200 119 134 180 214 180 105 118(3) 153(3) 178(3) 168 93 105 136 156 144 72 80 107 124 60 33 39 65 82 25 17 21 47 65 216 18 25(3) 71(3) - 200 17 24 70 112 180 14 20(3) 54(3) 75(3) 168 13 18 49 69 144 10 14 40 58 60 6 10 36 53 25 4 8 34 51 TA = 25 C TA = 85 C TA = 105 C 1. Guaranteed by characterization results, unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. Guaranteed by test in production. 126/255 DocID029041 Rev 6 mA STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 35. Typical and maximum current consumption in Sleep mode, regulator OFF Max(1) Symbol IDD12/ IDD Parameter Supply current in RUN mode from V12 and VDD supply Conditions All Peripherals Enabled(2) All Peripherals Disabled Typ fHCLK (MHz) TA= 25 C TA= 85 C Unit TA= 105 C IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD 180 102 1 114 2 148 2 168 2 168 91 1 101 2 132 2 152 2 144 71 1 78 2 105 2 122 2 60 32 1 37 2 64 2 81 2 25 16 1 20 2 46 2 64 2 180 13 1 18 2 53 2 73 2 168 12 1 16 2 47 2 67 2 144 9 1 13 2 39 2 56 2 60 5 1 9 2 35 2 52 2 25 3 1 7 2 33 2 50 2 mA 1. Guaranteed by characterization results, unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. Table 36. Typical and maximum current consumptions in Stop mode Max(1) Typ Symbol IDD_STOP_NM (normal mode) Parameter VDD = 3.6 V Conditions Flash memory in Stop mode, Supply current in Stop all oscillators OFF, no IWDG mode, main regulator in Flash memory in Deep power Run mode down mode, all oscillators OFF Flash memory in Stop mode, all Supply current in Stop oscillators OFF, no IWDG mode, main regulator in Flash memory in Deep power Low-power mode down mode, all oscillators OFF, no IWDG Regulator in Run mode, Flash memory in Deep power down Supply current in Stop mode, all oscillators OFF, no IDD_STOP_UDM mode, main regulator in IWDG (under-drive Low voltage and underRegulator in Low-power mode, mode) drive modes Flash memory in Deep power down mode, all oscillators OFF, no IWDG Unit TA = 25 C TA = 25 C TA = TA = 85 C 105 C 0.55 3 18 27 0.5 3 18 27 0.42 2.5 15 24 0.37 2.5 15 24 0.18 1.2 6 10 0.13 1.1 6 10 mA 1. Data based on characterization, tested in production. DocID029041 Rev 6 127/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 37. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Max(2) TA = 25 C TA = 25 C Conditions VDD = VDD= VDD = 1.7 V 2.4 V 3.3 V TA = 85 C TA = 105 C VDD = 3.3 V Backup SRAM OFF, RTC and LSE OFF 1.1 1.9 2.4 5(3) 18(3) 38(3) Backup SRAM ON, RTC and LSE OFF 1.9 2.7 3.2 6(3) 23(3) 48(3) Backup SRAM OFF, RTC ON and LSE in low drive mode 1.7 2.7 3.5 7 26 55 Backup SRAM OFF, RTC ON and LSE in medium low drive mode 1.7 2.7 3.5 7 26 56 1.8 2.8 3.6 8 28 57 1.9 2.9 3.7 8 28 59 Backup SRAM ON, RTC ON and LSE in low drive mode 2.4 3.4 4.3 8 31 65 Backup SRAM ON, RTC ON and LSE in Medium low drive mode 2.4 3.5 4.3 8 31 65 Backup SRAM ON, RTC ON and LSE in Medium high drive mode 2.6 3.7 4.5 8 33 68 Backup SRAM ON, RTC ON and LSE in High drive mode 2.6 3.7 4.5 9 33 68 Backup SRAM OFF, RTC ON and LSE in medium high drive Supply current mode IDD_STBY in Standby Backup SRAM OFF, RTC ON mode and LSE in high drive mode Unit A 1. The typical current consumption values are given with PDR OFF (internal reset OFF). When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by additional 1.2 A. 2. Guaranteed by characterization results, unless otherwise specified. 3. Guaranteed by test in production. 128/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 38. Typical and maximum current consumptions in VBAT mode Symbol Parameter Typ Max(2) TA =25 C TA =85 C TA =105 C VBAT = VBAT= VBAT= 1.7 V 2.4 V 3.3 V VBAT = 3.6 V Conditions(1) Backup SRAM OFF, RTC and LSE OFF 0.03 0.04 0.04 0.2 0.4 Backup SRAM ON, RTC and LSE OFF 0.77 0.78 0.83 3.2 7.4 Backup SRAM OFF, RTC ON and LSE in low drive mode 0.62 0.8 1.13 4.4 10.2 Backup SRAM OFF, RTC ON and LSE in medium low drive mode 0.65 0.83 1.17 4.6 10.6 Backup SRAM OFF, RTC ON Supply current and LSE in medium high drive IDD_VBAT in VBAT mode mode 0.75 0.94 1.28 5.0 11.4 Backup SRAM OFF, RTC ON and LSE in high drive mode 0.9 1.08 1.43 5.5 12.8 Backup SRAM ON, RTC ON and LSE in low drive mode 1.35 1.54 1.91 7.3 17.2 Backup SRAM ON, RTC ON and LSE in Medium low drive mode 1.38 1.57 1.93 7.9 18.4 Backup SRAM ON, RTC ON and LSE in Medium high drive mode 1.53 1.73 2.11 8.0 18.7 Backup SRAM ON, RTC ON and LSE in High drive mode 1.67 1.87 2.26 9.0 21.0 Unit A 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization results. I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 66: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. DocID029041 Rev 6 129/255 220 Electrical characteristics Caution: STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 40: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. Table 39. Switching output I/O current consumption(1) I/O toggling Symbol Parameter Conditions CEXT = 0 pF C = CINT + CS + CEXT IDDIO I/O switching Current CEXT = 10 pF C = CINT + CS + CEXT 130/255 frequency (fsw) MHz Typ Typ VDD = 3.3 V VDD = 1.8 V 2 0.1 0.1 8 0.4 0.2 25 1.1 0.7 50 2.4 1.3 60 3.1 1.6 84 4.3 2.4 90 4.9 2.6 100 5.4 2.8 2 0.2 0.1 8 0.6 0.3 25 1.8 1.1 50 3.1 2.3 60 4.6 3.4 84 9.7 3.6 90 10.12 5.2 100 14.92 5.4 DocID029041 Rev 6 Unit mA STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 39. Switching output I/O current consumption(1) (continued) I/O toggling Symbol Parameter Conditions frequency (fsw) MHz Typ Typ VDD = 3.3 V VDD = 1.8 V 2 0.3 0.1 8 1.0 0.5 25 3.5 1.6 50 5.9 4.2 60 10.0 4.4 84 19.12 5.8 90 19.6 - 2 0.3 0.2 8 1.3 0.7 25 3.5 2.3 50 10.26 5.19 60 16.53 - CEXT = 22 pF C = CINT + CS + CEXT I/O switching Current IDDIO CEXT = 33 pF C = CINT + CS + CEXT Unit mA 1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF. On-chip peripheral current consumption The MCU is placed under the following conditions: * At startup, all I/O pins are in analog input configuration. * All peripherals are disabled unless otherwise mentioned. * I/O compensation cell enabled. * The ART/L1-cache is ON. * Scale 1 mode selected, internal digital voltage V12 = 1.32 V. * HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. The given value is calculated by measuring the difference of current consumption * - with all peripherals clocked off - with only one peripheral clocked on - fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2), fHCLK = 144 MHz (Scale 3) Ambient operating temperature is 25 C and VDD=3.3 V. DocID029041 Rev 6 131/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 40. Peripheral current consumption IDD(Typ)(1) Peripheral AHB1 (up to 216 MHz) AHB2 (up to 216 MHz) AHB3 (up to 216 MHz) Scale 2 Scale 3 GPIOA 2.9 2.8 2.2 GPIOB 3.0 2.9 2.2 GPIOC 2.9 2.8 2.2 GPIOD 3.1 3.0 2.3 GPIOE 3.1 3.0 2.3 GPIOF 2.9 2.8 2.2 GPIOG 2.9 2.8 2.2 GPIOH 3.1 3.1 2.4 GPIOI 3.0 2.9 2.2 GPIOJ 2.9 2.9 2.2 GPIOK 2.8 2.8 2.4 CRC 1.0 0.9 0.8 BKPSRAM 0.9 0.9 0.7 DMA1 3.17 x N + 11.63 3.08 x N + 11.39 DMA2 3.33 x N + 12.84 3.27 x N + 11.84 2.75 x N + 10.10 A/MHz 2.6 x N + 9.64 DMA2D 77.7 76.3 63.5 ETH_MAC ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 40.1 39.5 32.8 OTG_HS 58.5 57.4 48.1 OTG_HS+ULPI 58.5 57.4 48.1 DCMI 2.9 2.8 2.1 JPEG 74.8 73.4 61.9 RNG 6.7 6.7 5.4 USB_OTG_FS 32.4 31.9 26.7 FMC 18.6 18.2 15.1 A/MHz A/MHz QSPI Bus matrix(2) 132/255 Unit Scale 1 22.3 21.8 18.1 3.94 3.25 2.12 DocID029041 Rev 6 A/MHz STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 40. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral Scale 2 Scale 3 TIM2 19.1 18.7 14.7 TIM3 14.6 14.0 10.6 TIM4 15.4 14.7 11.4 TIM5 18.1 17.6 13.6 TIM6 3.1 2.7 1.4 TIM7 3.0 2.7 1.1 TIM12 8.1 7.8 5.6 TIM13 5.4 5.1 3.1 TIM14 5.6 5.3 3.3 LPTIM1 9.8 9.6 6.9 WWDG APB1 (up to 54 MHz) Unit Scale 1 1.9 1.6 1,4 (3) SPI2/I2S2 3.0 2.9 1.4 SPI3/I2S3(3) 3.0 3.3 1.4 SPDIFRX 2.4 2.0 1.7 USART2 12.6 12.7 9.2 USART3 12.4 12.4 9.4 UART4 10.7 10.9 8.1 UART5 10.7 10.7 8.1 I2C1 8.9 8.9 6.4 I2C2 8.3 8.2 6.1 I2C3 8.1 8.2 6.1 I2C4 8.0 8.2 5.8 CAN1 6.3 6.4 4.4 CAN2 5.7 5.8 3.9 CAN3 7.4 7.1 5.6 HDMI-CEC 2.2 1.8 1.4 PWR 1.3 0.9 0.8 DAC 4.8 4.2 3.6 UART7 10.4 10.4 7.8 UART8 11.1 11.3 8.3 (4) DocID029041 Rev 6 A/MHz 133/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 40. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral Scale 2 Scale 3 TIM1 24.1 23.8 19.6 TIM8 24.5 24.2 20.0 USART1 17.7 17.4 14.3 USART6 11.9 11.8 9.4 ADC1(5) 4.5 4.7 3.5 ADC2 (5) 4.5 4.7 3.3 ADC3 (5) 4.5 4.6 3.3 SDMMC1 8.4 8.3 6.9 SDMMC2 8.2 8.2 6.4 3.9 3.6 3.1 SPI4 3.9 3.6 3.1 SYSCFG 2.5 2.2 1.9 TIM9 8.0 8.0 6.2 TIM10 5.0 5.1 3.7 TIM11 6.9 6.9 5.3 SPI5 2.7 2.8 1.8 SPI6 3.1 3.2 2.2 SAI1 3.2 3.3 2.2 DFSDM1 10.9 10.7 9.0 SAI2 3.9 3.9 2.8 MDIO 7.1 7.0 5.8 LTDC 51.2 50.3 41.8 DSI 8.5 8.4 8.1 (3) SPI1/I2S1 APB2 (up to 108 MHz) Unit Scale 1 A/MHz 1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA. 2. The BusMatrix is automatically active when at least one master is ON. 3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register. 4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of 0.75 mA per DAC channel for the analog part. 5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 134/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.8 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 41 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 41. Low-power mode wakeup timings Symbol tWUSLEEP(2) Parameter Wakeup from Sleep Conditions Typ(1) Max(1) Unit - 13 13 CPU clock cycles 14 14.9 104.1 107.6 21.4 24.2 111.5 116.5 Main regulator is ON Main regulator is ON and Flash memory in Deep power down mode tWUSTOP(2) Wakeup from Stop mode with MR/LP regulator in normal mode Low power regulator is ON Low power regulator is ON and Flash memory in Deep power down mode tWUSTOP(2) Main regulator in under-drive mode (Flash memory in Deep power-down Wakeup from Stop mode mode) with MR/LP regulator in Low power regulator in under-drive Under-drive mode mode (Flash memory in Deep power-down mode ) tWUSTDBY Wakeup from Standby (2) mode s 107.4 113.2 112.7 120 Exit Standby mode on rising edge 308 313 Exit Standby mode on falling edge 307 313 1. Guaranteed by characterization results. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first DocID029041 Rev 6 135/255 220 Electrical characteristics 5.3.9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 66: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 29. The characteristics given in Table 42 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 18. Table 42. High-speed external user clock characteristics Symbol Parameter fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage VHSEL OSC_IN input pin low level voltage tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) Cin(HSE) Conditions - Typ Max Unit 1 - 50 MHz 0.7VDD - VDD VSS - 0.3VDD 5 - - V ns OSC_IN rise or fall time(1) - - 10 - - 5 - pF - 45 - 55 % VSS VIN VDD - - 1 A OSC_IN input capacitance(1) DuCy(HSE) Duty cycle IL Min OSC_IN Input leakage current 1. Guaranteed by design. Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 66: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 30. The characteristics given in Table 43 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 18. 136/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 43. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.3VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) DuCy(LSE) IL - V ns OSC32_IN input capacitance(1) - - 5 - pF Duty cycle - 30 - 70 % VSS VIN VDD - - 1 A OSC32_IN Input leakage current 1. Guaranteed by design. Figure 29. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR(3% TF(3% T7(3% T T7(3% 4(3% %XTERNAL CLOCKSOURCE F(3%?EXT /3#?). ), 34-& AI DocID029041 Rev 6 137/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 30. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU/6( WI/6( W:/6( 26&B,1 ,/ W:/6( W 7/6( I/6(BH[W ([WHUQDO FORFNVRXUFH 670) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 44. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 44. HSE 4-26 MHz oscillator characteristics(1) Symbol Parameter fOSC_IN RF IDD ACCHSE(2) Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - k VDD=3.3 V, ESR= 30 , CL=5 pF@25 MHz - 450 - VDD=3.3 V, ESR= 30 , CL=10 pF@25 MHz - 530 - - - 500 - 500 ppm Startup - - 1 mA/V VDD is stabilized - 2 - ms HSE current consumption HSE accuracy Gm_crit_max Maximum critical crystal gm tSU(HSE(3) Startup time A 1. Guaranteed by design. 2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is guaranteed by characterization results. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 138/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 31). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 31. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 %LDV FRQWUROOHG JDLQ 5) 26&B28 7 670) DL 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 45. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 45. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol IDD Parameter LSE current consumption Conditions Min Typ Max LSEDRV[1:0]=00 Low drive capability - 250 - LSEDRV[1:0]=10 Medium low drive capability - 300 - LSEDRV[1:0]=01 Medium high drive capability - 370 - LSEDRV[1:0]=11 High drive capability - 480 - DocID029041 Rev 6 Unit nA 139/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 45. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) (continued) Symbol Parameter Gm_crit_max Maximum critical crystal gm tSU(2) Conditions Min Typ Max LSEDRV[1:0]=00 Low drive capability - - 0.48 LSEDRV[1:0]=10 Medium low drive capability - - 0.75 LSEDRV[1:0]=01 Medium high drive capability - - 1.7 LSEDRV[1:0]=11 High drive capability - - 2.7 VDD is stabilized - 2 - start-up time Unit A/V s 1. Guaranteed by design. 2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 32. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV & / I /6( 26&B ,1 N+] UHVRQDWRU & / 5) 26&B 28 7 %LDV FRQWUROOHG JDLQ 670) DLD 140/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Internal clock source characteristics The parameters given in Table 46 and Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. High-speed internal (HSI) RC oscillator Table 46. HSI oscillator characteristics (1) Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % -8 - 4.5 % (3) ACCHSI TA = -40 to 105 C tsu(HSI)(2) IDD(HSI) (2) C(3) -4 - 4 % C(4) -1 - 1 % HSI oscillator startup time - - 2.2 4 s HSI oscillator power consumption - - 60 80 A Accuracy of the HSI oscillator TA = -10 to 85 TA = 25 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Factory calibrated, parts not soldered. Figure 33. ACCHSI versus temperature ,^/ 5.3.10 Electrical characteristics d D D d 06Y9 1. Guaranteed by characterization results. DocID029041 Rev 6 141/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Low-speed internal (LSI) RC oscillator Table 47. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) Parameter Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 s (3) LSI oscillator power consumption - 0.4 0.6 A IDD(LSI) 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design. Figure 34. LSI deviation versus temperature 1RUPDOL]HGGHYLDWLRQ D D d 7HPSHUDWXUH& 142/255 DocID029041 Rev 6 069 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.11 Electrical characteristics PLL characteristics The parameters given in Table 48 and Table 49 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 18. Table 48. Main PLL characteristics Symbol Parameter Conditions Min Typ Max fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10 fPLL_OUT PLL multiplier output clock - 24 - 216 fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75 fVCO_OUT PLL VCO output - 100 - 432 tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 - 25 - - 150 - - 15 - - 200 - RMS Cycle-to-cycle jitter System clock 216 MHz peak to peak RMS peak to peak Period Jitter Jitter(3) Unit MHz s ps Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization results. DocID029041 Rev 6 143/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 49. PLLI2S characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10 fPLLI2SP_OUT PLLI2S multiplier output clock for SPDIFRX - - - 216 fPLLI2SQ_OUT PLLI2S multiplier output clock for SAI - - - 216 fPLLI2SR_OUT PLLI2S multiplier output clock for I2S - - - 216 fVCO_OUT PLLI2S VCO output - 100 - 432 tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - - peak to peak - 280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA Unit Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master I2S clock jitter (3) Jitter MHz s 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design. 3. Value given with main PLL running. 4. Guaranteed by characterization results. Table 50. PLLISAI characteristics Symbol Parameter Conditions Min Typ Max fPLLSAI_IN PLLSAI input clock(1) - 0.95(2) 1 2.10 fPLLSAIP_OUT PLLSAI multiplier output clock for 48 MHz - - 48 75 fPLLSAIQ_OUT PLLSAI multiplier output clock for SAI - - - 216 fPLLSAIR_OUT PLLSAI multiplier output clock for LCD-TFT - - - 216 fVCO_OUT PLLSAI VCO output - 100 - 432 144/255 DocID029041 Rev 6 MHz STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 50. PLLISAI characteristics (continued) Symbol Parameter Min Typ Max VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - - peak to peak - 280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps FS clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLSAI)(4) PLLSAI power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLSAI)(4) PLLSAI power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA tLOCK Conditions PLLSAI lock time Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master SAI clock jitter (3) Jitter Unit s 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design. 3. Value given with main PLL running. 4. Guaranteed by characterization results. 5.3.12 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 62: EMI characteristics). It is available only on the main PLL. Table 51. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - - 2 15 -1 - 1. Guaranteed by design. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: DocID029041 Rev 6 145/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x PLLN ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x PLLN ) As a result: md quantized % = ( 250 x 126 x 100 x 5 ) ( ( 2 15 - 1 ) x 240 ) = 2.002%(peak) Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 35. PLL output clock waveforms in center spread mode &REQUENCY0,,?/54 MD & MD TMODE XTMODE 4IME AI 146/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 36. PLL output clock waveforms in down spread mode )UHTXHQF\3//B287 ) [PG WPRGH 7LPH [WPRGH DLE 5.3.13 MIPI D-PHY characteristics The parameters given in Table 52 and Table 53 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 18. Table 52. MIPI D-PHY characteristics(1) Symbol Parameter Conditions Min Typ Max Unit ns Hi-Speed Input/Output Characteristics UINST UI instantaneous - 2 - 12.5 VCMTX HS transmit common mode voltage - 150 200 250 |VCMTX| VCMTX mismatch when output is Differential-1 or Differential-0 - - - 5 |VOD| HS transmit differential voltage - 140 200 270 |VOD| VOD mismatch when output is Differential-1 or Differential-0 - - - 14 VOHHS HS output high voltage - - - 360 ZOS Single ended output impedance - 40 50 62.5 ZOS Single ended output impedance mismatch - - - 10 % 20%-80% rise and fall time - 100 - 0.35*UI ps tHSr & tHSf mV LP Receiver Input Characteristics VIL Logic 0 input voltage (not in ULP State) - - - 550 VIL-ULPS Logic 0 input voltage in ULP State - - - 300 VIH Input high level voltage - 880 - - Vhys Voltage hysteresis - 25 - - mV LP Emitter Output Characteristics DocID029041 Rev 6 147/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 52. MIPI D-PHY characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit VIL Output low level voltage - 1.1 1.2 1.2 V VIL-ULPS Output high level voltage - -50 - 50 mV VIH Output impedance of LP transmitter - 110 - - Vhys 15%-85% rise and fall time - - - 25 ns LP Contention Detector Characteristics VILCD Logic 0 contention threshold - - - 200 VIHCD Logic 0 contention threshold - 450 - - mV 1. Guaranteed based on test during characterization. Table 53. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1) Symbol Parameter Conditions Min Typ Max TLPX Transmitted length of any LowPower state period - 50 - - Time that the transmitter drives the Clock Lane LP-00 Line TCLK-PREPARE state immediately before the HS-0 Line state starting the HS transmission. - 38 - 95 TCLK-PREPARE Time that the transmitter drives + the HS-0 state prior to starting TCLK-ZERO the clock. - 300 - - Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. - 8 - - TCLK-PRE 148/255 DocID029041 Rev 6 Unit ns UI STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 53. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1) (continued) Symbol Parameter Conditions Min Typ Max TCLK-POST Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. - 62+52*UI - - TCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of an HS transmission burst. - 60 - - THS-PREPARE Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. - 40+4*UI - 85+6*UI THS-PREPARE + THS-ZERO THS-PREPARE+ Time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. - 145+10*UI - - THS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst. - Max (n*8*UI, 60+n*4*UI) - - THS-EXIT Time that the transmitter drives LP-11 following a HS burst. - 100 - - TREOT 30%-85% rise time and fall time - - - 35 TEOT Transmitted time interval from the start of THS-TRAIL or TCLK-TRAIL, to the start of the LP-11 state following a HS burst. - - - 105+ n*12UI Unit ns 1. Guaranteed based on test during characterization. DocID029041 Rev 6 149/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram 7&/.3267 7(27 9,/ &ORFN /DQH 7&/.75$,/ 7+6(;,7 7/3; 7&/.35(3$5( 7&/.=(52 7&/.35( 'DWD /DQH 7/3; 7+635(3$5( 9,/ 069 Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram &ORFN /DQH 'DWD /DQH 7/3; 7+635(3$5( /3 /3 7+6=(52 9,/ 75(27 /3 7(27 7+675$,/ 7+6(;,7 069 5.3.14 MIPI D-PHY PLL characteristics The parameters given in Table 54 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 18. Table 54. DSI-PLL characteristics(1) Symbol Conditions Min Typ Max PLL input clock - 4 - 100 fPLL_INFIN PFD input clock - 4 - 25 - 31.25 - 500 - 500 - 1000 - - - 200 fPLL_IN fPLL_OUT Parameter PLL multiplier output clock fVCO_OUT PLL VCO output tLOCK 150/255 PLL lock time DocID029041 Rev 6 Unit MHz s STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 54. DSI-PLL characteristics(1) (continued) Symbol IDD(PLL) Parameter PLL power consumption on VDD12 Conditions Min Typ Max fVCO_OUT = 500 MHz - 0.55 0.70 fVCO_OUT = 600 MHz - 0.65 0.80 fVCO_OUT = 1000 MHz - 0.95 1.20 Unit mA 1. Based on test during characterization. 5.3.15 MIPI D-PHY regulator characteristics The parameters given in Table 55 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 18. Table 55. DSI regulator characteristics(1) Symbol Conditions Min Typ Max Unit 1.2 V internal voltage on VDD12DSI - 1.15 1.20 1.30 V CEXT External capacitor on VCAPDSI - 1.1 2.2 3.3 F ESR External Serial Resistor - 0 25 600 m - 100 120 125 A Ultra Low Power Mode (Reg. ON + PLL OFF) - 290 600 Stop State (Reg. ON + PLL OFF) - 290 600 10 MHz escape clock (Reg. ON + PLL OFF) - 4.3 5.0 20 MHz escape clock (Reg. ON + PLL OFF) - 4.3 5.0 300 Mbps - 1 data lane (Reg. ON + PLL ON) - 8.0 8.8 300 Mbps - 2data lane (Reg. ON + PLL ON) - 11.4 12.5 500 Mbps - 1 data lane (Reg. ON + PLL ON) - 13.5 14.7 500 Mbps - 2data lane (Reg. ON + PLL ON) - 18.0 19.6 500 Mbps - 2data lane (Reg. ON + PLL ON) - 21.4 23.3 CEXT = 2.2 F - 110 - CEXT = 3.3 F - - 160 External capacitor load at start - 60 200 VDD12DSI Parameter IDDDSIREG Regulator power consumption IDDDSI IDDDSILP IDDDSIHS DSI system (regulator, PLL and D-PHY) current consumption on VDDDSI DSI system current consumption on VDDDSI in LP mode communication(2) DSI system (regulator, PLL and D-PHY) current consumption on VDDDSI in HS mode communication(3) DSI system (regulator, PLL and D-PHY) current consumption on VDDDSI in HS mode with CLK like payload tWAKEUP Startup delay IINRUSH Inrush current on VDDDSI A mA mA s mA 1. Based on test during characterization. 2. Values based on an average traffic in LP Command Mode. 3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode. DocID029041 Rev 6 151/255 220 Electrical characteristics 5.3.16 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 56. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 14 - Write / Erase 16-bit mode, VDD = 2.1 V - 17 - Write / Erase 32-bit mode, VDD = 3.3 V - 24 - Unit mA Table 57. Flash memory programming (single bank configuration nDBANK=1) Symbol tprog Parameter Word programming time tERASE32KB Sector (32 KB) erase time tERASE128KB Sector (128 KB) erase time tERASE256KB Sector (256 KB) erase time tME 152/255 Mass erase time Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 250 600 Program/erase parallelism (PSIZE) = x 32 - 200 500 Program/erase parallelism (PSIZE) = x 8 - 1100 2400 Program/erase parallelism (PSIZE) = x 16 - 800 1400 Program/erase parallelism (PSIZE) = x 32 - 500 1100 Program/erase parallelism (PSIZE) = x 8 - 2.1 4 Program/erase parallelism (PSIZE) = x 16 - 1.5 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 DocID029041 Rev 6 s ms ms s s STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 57. Flash memory programming (single bank configuration nDBANK=1) (continued) Symbol Vprog Parameter Programming voltage Min(1) Typ 32-bit program operation 2.7 - 3 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V Conditions Max(1) Unit 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 100K erase operations. Table 58. Flash memory programming (dual bank configuration nDBANK=0) Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Mass erase time Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 250 600 Program/erase parallelism (PSIZE) = x 32 - 200 500 Program/erase parallelism (PSIZE) = x 8 - 1100 2400 Program/erase parallelism (PSIZE) = x 16 - 800 1400 Program/erase parallelism (PSIZE) = x 32 - 500 1100 Program/erase parallelism (PSIZE) = x 8 - 2.1 4 Program/erase parallelism (PSIZE) = x 16 - 1.5 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 DocID029041 Rev 6 s ms ms s s 153/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 58. Flash memory programming (dual bank configuration nDBANK=0) (continued) Symbol Parameter tBE Bank erase time Vprog Programming voltage Min(1) Typ Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V Conditions Max(1) Unit s 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 100K erase operations. Table 59. Flash memory programming with VPP Symbol Parameter tprog Double word programming tERASE32KB Sector (32 KB) erase time tERASE128KB Sector (128 KB) erase time tERASE256KB Sector (256 KB) erase time tME Conditions Min(1) Typ Max(1) Unit - 16 100(2) s - 180 - - 450 - - 900 - - 6.9 - s TA = 0 to +40 C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.6 V VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 60. Flash memory endurance and data retention Value Symbol NEND tRET 154/255 Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle(2) at TA = 105 C 10 10 kcycles(2) at TA = 55 C 20 DocID029041 Rev 6 Unit kcycles Years STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 5.3.17 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 61. They are based on the EMS levels and classes defined in application note AN1709. Table 61. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, TA = +25 C, fHCLK = Voltage limits to be applied on any I/O pin to 216 MHz, conforms to IEC 61000induce a functional disturbance 4-2 2B VFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA =+25 C, fHCLK = 168 MHz, conforms to IEC 610004-2 5A As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) DocID029041 Rev 6 155/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 62. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 8/200 MHz VDD = 3.6 V, TA = 25 C, TFBGA216 package, conforming to IEC61967-2 ART/L1-cache ON, over-drive ON, all peripheral clocks enabled, clock dithering disabled. SEMI Peak level VDD = 3.6 V, TA = 25 C, TFBGA216 package, conforming to IEC61967-2 ART/L1-cache ON, over-drive ON, all peripheral clocks enabled, clock dithering enabled. 5.3.18 0.1 to 30 MHz 5 30 to 130 MHz 10 130 MHz to 1 GHz 18 1 GHz to 2 GHz 10 EMI Level 3.5 0.1 to 30 MHz 2 30 to 130 MHz 9 130 MHz to 1 GHz 14 1 GHz to 2 GHz 9 EMI Level 3 dBV - dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards. 156/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 63. ESD absolute maximum ratings Symbol Ratings VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Maximum Unit value(1) Conditions Class TA = +25 C conforming to ANSI/ESDA/JEDEC JS-001-2012 2 2000 TA = +25 C conforming to ANSI/ESD S5.3.12009, all packages except TFBGA100 3 250 TA = +25 C conforming to ANSI/ESD S5.3.12009, TFBGA100 package 4 500 V 1. Guaranteed by characterization results. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 64. Electrical sensitivities Symbol LU 5.3.19 Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, a current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of - 5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 65. DocID029041 Rev 6 157/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 65. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0, DSI_D0P, DSI_D0N, DSI_D1P, DSI_D1N, DSI_CKP, DSI_CKN pin -0 0 Injected current on NRST pin -0 NA(1) Injected current on PC0, PC2, PH1_OSCOUT pins -0 NA(1) Injected current on any other FT pin -5 NA(1) Injected current on any other pins -5 +5 Unit mA 1. Injection is not possible. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 5.3.20 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 66: I/O static characteristics are derived from tests performed under the conditions summarized in Table 18. All I/Os are CMOS and TTL compliant. Table 66. I/O static characteristics Symbol Parameter FT, TTa and NRST I/O input low level voltage VIL BOOT I/O input low level voltage FT, TTa and NRST I/O input high level voltage(5) VIH BOOT I/O input high level voltage FT, TTa and NRST I/O input hysteresis VHYS BOOT I/O input hysteresis 158/255 Conditions Min Typ 1.7 VVDD3.6 V - - 1.75 VVDD 3.6 V, - 40 CTA 105 C - - 1.7 VVDD 3.6 V, 0 CTA 105 C - 1.7 VVDD3.6 V 1.75 VVDD 3.6 V, - 40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C 1.7 VVDD3.6 V Max Unit 0.35VDD - 0.04(1) 0.3VDD(2) V 0.1VDD+0.1(1) 0.45VDD+0.3(1) 0.7VDD(2) - V 0.17VDD+0.7(1) - - 10%VDD(3) - - 1.75 VVDD 3.6 V, - 40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C DocID029041 Rev 6 V 0.1 - - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 66. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max VSS VIN VDD - - 1 VIN = 5 V - - 3 30 40 50 PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) 7 10 14 All pins except for PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) 30 40 50 7 10 14 - 5 - I/O input leakage current Ilkg (4) I/O FT input leakage current (5) RPU RPD CIO(8) Weak pull-up equivalent resistor(6) Weak pulldown equivalent resistor(7) All pins except for PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) A VIN = VSS k VIN = VDD PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) I/O pin capacitance Unit - pF 1. Guaranteed by design. 2. Tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 65: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 65: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 39. DocID029041 Rev 6 159/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 39. FT I/O input characteristics 9,/9,+9 '' 9 LQ P + 9, W HQ HP LU TX 26 0 & LQ U S LQ G H VW OD PX VL LJQ V 'H Q GR $UHDQRWGHWHUPLQHG % XOD QVLP VLJ Q'H HGR %DV 9'' D[ ,/P 9 WLRQV P 9,+ QV WLR 7H H DV Q LR FW X RG 77/UHTXLUHPHQW 9,+PLQ 9 '' 9 UH 77/UHTXLUHPHQW 9,/PD[ 9 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' 9''9 069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which can sink or source up to 3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 16). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 16). Output voltage levels Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. All I/Os are CMOS and TTL compliant. 160/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 67. Output voltage characteristics Symbol Parameter Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V VDD 3.6 V - 0.4 VDD - 0.4 - VDD - 0.4 - Output low level voltage for an I/O pin TTL port(2) IIO =+8mA 2.7 V VDD 3.6 V - 0.4 VOH (3) Output high level voltage for an I/O pin except PC14 TTL port(2) IIO =-8mA 2.7 V VDD 3.6 V 2.4 - VOL(1) Output low level voltage for an I/O pin IIO = +20 mA 2.7 V VDD 3.6 V - 1.3(4) VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -20 mA VDD -1.3(4) 2.7 V VDD 3.6 V VOL(1) Output low level voltage for an I/O pin IIO = +6 mA 1.8 V VDD 3.6 V VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -6 mA 1.8 V VDD 3.6 V VOL(1) Output low level voltage for an I/O pin IIO = +4 mA 1.7 V VDD 3.6V - 0.4(5) VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -4 mA 1.7 V VDD 3.6V VDD -0.4(5) - VOH(3) Output high level voltage for PC14 IIO = -1 mA 1.7 V VDD 3.6V VDD -0.4(5) - VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin except PC14 Unit CMOS port(2) IIO = -8 mA 2.7 V VDD 3.6 V V CMOS port(2) VOH(3) VOL (1) Output high level voltage for PC14 IIO = -2 mA 2.7 V VDD 3.6 V V - V 0.4(4) V VDD -0.4(4) - V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 16. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 16 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data. 5. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 40 and Table 68, respectively. DocID029041 Rev 6 161/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Unless otherwise specified, the parameters given in Table 68 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 68. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Maximum frequency (3) 00 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 01 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 10 tf(IO)out/ tr(IO)out 162/255 Output high to low level fall time and output low to high level rise time Conditions Min Typ Max CL = 50 pF, VDD 2.7 V - - 4 CL = 50 pF, VDD 1.7 V - - 2 CL = 10 pF, VDD 2.7 V - - 8 CL = 10 pF, VDD 1.8 V - - 4 CL = 10 pF, VDD 1.7 V - - 3 CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 CL = 50 pF, VDD 2.7 V - - 25 CL = 50 pF, VDD 1.8 V - - 12.5 CL = 50 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 50 CL = 10 pF, VDD 1.8 V - - 20 CL = 10 pF, VDD 1.7 V - - 12.5 CL = 50 pF, VDD 2.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 6 CL = 50 pF, VDD 1.7 V - - 20 CL = 10 pF, VDD 1.7 V - - 10 CL = 40 pF, VDD 2.7 V - - 50(4) CL = 10 pF, VDD 2.7 V - - 100(4) CL = 40 pF, VDD 1.7 V - - 25 CL = 10 pF, VDD 1.8 V - - 50 CL = 10 pF, VDD 1.7 V - - 42.5 CL = 40 pF, VDD 2.7 V - - 6 CL = 10 pF, VDD 2.7 V - - 4 CL = 40 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 1.7 V - - 6 DocID029041 Rev 6 Unit MHz ns MHz ns MHz ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 68. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD 2.7 V - - 100(4) CL = 30 pF, VDD 1.8 V - - 50 CL = 30 pF, VDD 1.7 V - - 42.5 CL = 10 pF, VDD 2.7 V - - 180(4) CL = 10 pF, VDD 1.8 V - - 100 CL = 10 pF, VDD 1.7 V - - 72.5 CL = 30 pF, VDD 2.7 V - - 4 CL = 30 pF, VDD 1.8 V - - 6 CL = 30 pF, VDD 1.7 V - - 7 CL = 10 pF, VDD 2.7 V - - 2.5 CL = 10 pF, VDD 1.8 V - - 3.5 CL = 10 pF, VDD 1.7 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller - Unit MHz ns ns 1. Guaranteed by design. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F76xxx and STM32F77xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 40. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 40. I/O AC characteristics definition (;7(51$/ 287387 21&/ WU,2 RXW WI,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH,2$&FKDUDFWHULVWLFV DocID029041 Rev 6 DLG 163/255 220 Electrical characteristics 5.3.21 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 66: I/O static characteristics). Unless otherwise specified, the parameters given in Table 69 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 69. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 k - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - s VF(NRST) (2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 41. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 1567 538 ,QWHUQDO5HVHW )LOWHU ) 670) DLF 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 69. Otherwise the reset is not taken into account by the device. 164/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.22 Electrical characteristics TIM timer characteristics The parameters given in Table 70 are guaranteed by design. Refer to Section 5.3.20: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 70. TIMx characteristics(1)(2) Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 216 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 100 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 216 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 x 65536 tTIMxCLK Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx. 5.3.23 RTC characteristics Table 71. RTC characteristics 5.3.24 Symbol Parameter Conditions - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register Min Max 4 - 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 72 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 18. Table 72. ADC characteristics Symbol VDDA VREF+ fADC Parameter Power supply Positive reference voltage ADC clock frequency Conditions VDDA -VREF+ < 1.2 V VDDA = 1.7(1) to 2.4 V VDDA = 2.4 to 3.6 V DocID029041 Rev 6 Min Typ Max Unit 1.7(1) - 3.6 V 1.7(1) - VDDA V 0.6 15 18 MHz 0.6 30 36 MHz 165/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 72. ADC characteristics (continued) Symbol fTRIG(2) VAIN RAIN(2) Parameter External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Min Typ Max Unit fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 k - 1.5 - 6 k - - 4 7 pF - - 0.100 s 1/fADC tlat(2) Injection trigger conversion latency fADC = 30 MHz - - - 3(5) tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 s - - - 2(5) 1/fADC tS(2) Sampling time fADC = 30 MHz 0.100 - 16 s - 3 - 480 1/fADC tSTAB(2) Power-up time - - 2 3 s fADC = 30 MHz 12-bit resolution 0.50 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.30 - 16.20 s tCONV(2) Total conversion time (including sampling time) 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Sampling rate fS(2) 166/255 (fADC = 36 MHz, and tS = 3 ADC cycles) 1/fADC 12-bit resolution Single ADC - - 2.4 Msps 12-bit resolution Interleave Dual ADC mode - - 4.5 Msps 12-bit resolution Interleave Triple ADC mode - - 7.2 Msps DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 72. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 A IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 72. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 73. ADC static accuracy at fADC = 18 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Typ Max(1) 3 4 2 3 1 3 1 2 2 3 Unit LSB 1. Guaranteed by characterization results. Table 74. ADC static accuracy at fADC = 30 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 k, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA -VREF < 1.2 V Typ Max(1) 2 5 1.5 2.5 1.5 4 1 2 1.5 3 Unit LSB 1. Guaranteed by characterization results. DocID029041 Rev 6 167/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 75. ADC static accuracy at fADC = 36 MHz Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(1) 4 7 2 3 3 6 2 3 3 6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Unit LSB 1. Guaranteed by characterization results. Table 76. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - 67 - 72 - dB 1. Guaranteed by characterization results. Table 77. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - - 70 - 72 - dB 1. Guaranteed by characterization results. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.20 does not affect the ADC accuracy. 168/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 42. ADC accuracy characteristics 6 $$! 6 2%& ;,3" )$%!, ORDEPENDINGONPACKAGE= %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AIC 1. See also Table 74. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 43. Typical connection diagram using the ADC 670) 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ,/$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 72 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DocID029041 Rev 6 169/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 44 or Figure 45, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA) 670) 95() )Q) 9''$ )Q) 966$95() DLE 1. VREF+ input is available on all packages except TFBGA100 whereas the VREF- s available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$ )Q) 95()966$ DLF 1. VREF+ input is available on all packages except TFBGA100 whereas the VREF- s available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. 170/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.25 Electrical characteristics Temperature sensor characteristics Table 78. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 - mV/C Voltage at 25 C - 0.76 - V tSTART(2) Startup time - 6 10 s TS_temp(2) ADC sampling time when reading the temperature (1 C accuracy) 10 - - s TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 79. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FF0 F44C - 0x1FF0 F44D TS_CAL2 TS ADC raw data acquired at temperature of 110 C, VDDA= 3.3 V 0x1FF0 F44E - 0x1FF0 F44F 5.3.26 VBAT monitoring characteristics Table 80. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - K Q Ratio on VBAT measurement - 4 - - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s Er(1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 5.3.27 Reference voltage The parameters given in Table 81 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 81. internal reference voltage Symbol VREFINT TS_vrefint(1) VREFINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V - 10 - - s VDD = 3V 10mV - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range DocID029041 Rev 6 171/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 81. internal reference voltage (continued) Symbol Parameter TCoeff(2) tSTART (2) Conditions Min Typ Max Unit Temperature coefficient - - 30 50 ppm/C Startup time - - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 82. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 5.3.28 Memory address Raw data acquired at temperature of 30 C VDDA = 3.3 V 0x1FF0 F44A - 0x1FF0 F44B DAC electrical characteristics Table 83. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 1.7(1) - 3.6 V VREF+ Reference supply voltage 1.7(1) - 3.6 V VSSA Ground 0 - 0 V - 5 - k - 25 - - Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum k resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Capacitive load - - 50 pF DAC_OUT Lower DAC_OUT voltage with buffer ON min(2) 0.2 - - V DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - - VDDA - 0.2 V DAC_OUT Lower DAC_OUT voltage with buffer OFF min(2) - 0.5 - mV - VREF+ - 1LSB V RLOAD (2) RO(2) CLOAD(2) Connected to Resistive load VSSA with buffer ON Connected to VDDA DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) 172/255 - DocID029041 Rev 6 VREF+ VDDA Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V It gives the maximum output excursion of the DAC. STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 83. DAC characteristics (continued) Symbol IVREF+(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) Min Typ Max - 170 240 Unit A Comments With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 A With no load, middle code (0x800) on the inputs - 475 625 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Differential non linearity Difference between two consecutive code-1LSB) - - 0.5 LSB Given for the DAC in 10-bit configuration. - - 2 LSB Given for the DAC in 12-bit configuration. - - 1 LSB Given for the DAC in 10-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - 4 LSB Given for the DAC in 12-bit configuration. - - 10 mV Given for the DAC in 12-bit configuration Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - 0.5 % Given for the DAC in 12-bit configuration - 3 6 s CLOAD 50 pF, RLOAD 5 k IDDA(4) DNL(4) Gain error(4) DAC DC VDDA current consumption in quiescent mode(3) Gain error Settling time (full scale: for a 10-bit input code transition between the lowest and the (4) tSETTLING highest input codes when DAC_OUT reaches final value 4LSB THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD 50 pF, RLOAD 5 k Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD 50 pF, RLOAD 5 k DocID029041 Rev 6 173/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 83. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - -67 -40 dB No RLOAD, CLOAD = 50 pF 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 46. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.29 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s. * Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0410 reference manual) and when the I2CCLK frequency is greater than the minimum shown in the table below: 174/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 84. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog filter ON DNF=0 8 Analog filter OFF DNF=1 9 Analog filter ON DNF=0 16 Analog filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: * The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. * The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: Tr(SDA/SCL)=0.8473xRpxCload Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 5.3.20: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 85 for the analog filter characteristics: Table 85. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 70(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered. DocID029041 Rev 6 175/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 86 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 86. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master mode SPI1,4,5,6 2.7VDD3.6 54(2) Master mode SPI1,4,5,6 1.71VDD3.6 27 Master transmitter mode SPI1,4,5,6 1.71VDD3.6 54 Slave receiver mode SPI1,4,5,6 1.71VDD3.6 54 - - MHz Slave mode transmitter/full duplex SPI1,4,5,6 2.7VDD3.6 50(3) Slave mode transmitter/full duplex SPI1,4,5,6 1.71VDD3.6 37(3) Master & Slave mode SPI2,3 1.71VDD3.6 27 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*TPLCK - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*TPLCK - - tw(SCKH) tw(SCKL) SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2 176/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 86. SPI dynamic characteristics(1) (continued) Symbol Conditions Min Typ Max Master mode 4 9(4) - - tsu(SI) Slave mode 4.5 - - th(MI) Master mode 3 0(4) - - Slave mode 2 - - tsu(MI) Parameter Data input setup time Data input hold time th(SI) ta(SO) Data output access time Slave mode 7 - 21 tdis(SO) Data output disable time Slave mode 5 - 12 Slave mode 2.7VDD3.6V - 6.5 10 Slave mode 1.71VDD3.6V - 6.5 13.5 tv(MO) Master mode - 2 6 th(SO) Slave mode 1.71VDD3.6V 4.5 - - Master mode 0 - - tv(SO) Data output valid time Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. 2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz. 3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having Tsu(MI)=0 while signal Duty(SCK)=50%. 4. Only for SPI6. Figure 47. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF6&. 6&.LQSXW WVX166 WK166 WZ6&.+ WU6&. &3+$ &32/ &3+$ &32/ WD62 WZ6&./ WY62 )LUVWELW287 0,62RXWSXW WK62 1H[WELWV287 WI6&. WGLV62 /DVWELW287 WK6, WVX6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 DocID029041 Rev 6 177/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 48. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW WF6&. WVX166 WZ6&.+ WD62 WZ6&./ WI6&. WK166 6&.LQSXW &3+$ &32/ &3+$ &32/ WY62 WK62 )LUVWELW287 0,62RXWSXW WVX6, WU6&. 1H[WELWV287 WGLV62 /DVWELW287 WK6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 49. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 178/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 87 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 87. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256x8K 256xFs(2) MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs 30 70 DCK I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 5 - th(WS) WS hold time Slave mode 2 - Master receiver 2.5 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) - 12 Master transmitter (after enable edge) - 3 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. The maximum value of 256xFs is 49.152 MHz (APB1 maximum frequency). Note: Refer to RM0410 reference manual I2S section for more details about the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DocID029041 Rev 6 179/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 50. I2S slave timing diagram (Philips protocol)(1) &.,QSXW WF&. &32/ &32/ WZ&.+ WK:6 WZ&./ :6LQSXW WY6'B67 WVX:6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW %LWQWUDQVPLW WVX6'B65 /6%UHFHLYH 6'UHFHLYH WK6'B67 /6%WUDQVPLW WK6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 069 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 51. I2S master timing diagram (Philips protocol)(1) WI&. WU&. &.RXWSXW WF&. &32/ WZ&.+ &32/ WY:6 WK:6 WZ&./ :6RXWSXW WY6'B07 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW 6'UHFHLYH /6%WUDQVPLW WK6'B05 WVX6'B05 /6%UHFHLYH %LWQWUDQVPLW WK6'B07 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 069 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 180/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics JATG/SWD characteristics Unless otherwise specified, the parameters given in Table 88 for JTAG/SWD are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C=30 pF * Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 88. Dynamics characteristics: JTAG characteristics Symbol Parameter Fpp 1/tc(TCK) Conditions Min Typ Max 2.7V <VDD< 3.6V - - 40 Unit MHz TCK clock frequency 1.71 <VDD< 3.6V - - 35 tw(TCKH) SCK high and low time - TPCLK - 1 TPCLK TPCLK + 1 tsu(TMS) TMS input setup time - 3 - - th(TMS) TMS input hold time - 0 - - tsu(TDI) TDI input setup time - 0.5 - - th(TDI) TDI input hold time - 2 - - 2.7V <VDD< 3.6V - 9 11 tov (TDO) TDO output valid time - 9 13 7.5 - - tw(TCKL) 1.71 <VDD< 3.6V toh(TDO) TDO output hold time - DocID029041 Rev 6 ns 181/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 89. Dynamics characteristics: SWD characteristics Symbol Parameter Fpp 1/tc(SWCLK) Conditions Min Typ Max 2.7V <VDD< 3.6V - - 80 - - 50 Unit MHz SWCLK clock frequency 1.71 <VDD< 3.6V tw(SWCLKH) SCK high and low time - TPCLK - 1 TPCLK TPCLK + 1 tsu(SWDIO) SWDIO input setup time - 3.5 - - th(SWDIO) SWDIO input hold time - 0 - - 2.7V <VDD< 3.6V - 11 12 - 11 16.5 9 - - tw(SWCLKL) tov (SWDIO) SWDIO output valid time 1.71 <VDD< 3.6V toh(SWDIO) ns SWDIO output hold time - JTAG/SWD timing diagrams Figure 52. JTAG timing diagram WF7&. 7&. WVX7067', WK7067', WZ7&./ WZ7&.+ 7',706 WRY7'2 WRK7'2 7'2 06Y9 182/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 53. SWD timing diagram WF6:&/. 6:&/. WVX6:',2 WK6:',2 WZ6:&/./ WZ6:&/.+ 6:',2 UHFHLYH WRY6:',2 WRK6:',2 6:',2 WUDQVPLW 06Y9 SAI characteristics: Unless otherwise specified, the parameters given in Table 90 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C=30 pF * Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 90. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK SAI Main clock output - 256 x 8K 256xFs MHz FCK SAI clock frequency(2) Master data: 32 bits - 128xFs(3) Slave data: 32 bits - 128xFs Master mode 2.7VDD3.6V - 15 Master mode 1.71VDD3.6V - 20 Slave mode 7 - Master mode 1 - Slave mode 1 - Master receiver 3 - Slave receiver 3.5 - Master receiver 5 - Slave receiver 1 - tv(FS) FS valid time tsu(FS) FS setup time th(FS) FS hold time tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) Data input setup time Data input hold time DocID029041 Rev 6 MHz ns 183/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 90. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_MT) tv(SD_MT)_A th(SD_A_MT) Parameter Data output valid time Data output hold time Data output valid time Data output hold time Conditions Min Max Slave transmitter (after enable edge) 2.7VDD3.6V - 12 Slave transmitter (after enable edge) 1.71VDD3.6V - 20 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 2.7VDD3.6V - 15 Master transmitter (after enable edge) 1.71VDD3.6V - 20 Master transmitter (after enable edge) 5 - Unit ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. 3. With FS=192kHz. Figure 54. SAI master timing waveforms F3#+ 3!)?3#+?8 TH&3 3!)?&3?8 OUTPUT TV&3 TH3$?-4 TV3$?-4 3!)?3$?8 TRANSMIT 3LOTN TSU3$?-2 3!)?3$?8 RECEIVE 3LOTN TH3$?-2 3LOTN -36 184/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 55. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW#+(?8 3!)?&3?8 INPUT TW#+,?8 TH&3 TSU&3 TH3$?34 TV3$?34 3!)?3$?8 TRANSMIT 3LOTN 3LOTN TSU3$?32 TH3$?32 3!)?3$?8 RECEIVE 3LOTN -36 USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 91. USB OTG full speed startup time Symbol tSTARTUP(1) Parameter Max Unit USB OTG full speed transceiver startup time 1 s 1. Guaranteed by design. Table 92. USB OTG full speed DC electrical characteristics Symbol Parameter Conditions USB OTG full speed VDDUSB transceiver operating voltage Input levels Output levels Min. (1) Typ. - 3.0(2) Max. (1) Unit - 3.6 V VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold - 1.3 - 2.0 VOL Static output level low RL of 1.5 k to 3.6 V(4) - - 0.3 2.8 - 3.6 VOH Static output level high RL of 15 k to DocID029041 Rev 6 VSS(4) V V 185/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 92. USB OTG full speed DC electrical characteristics (continued) Symbol Parameter PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) RPD Max. (1) Typ. 17 21 24 2.4 5.2 8 (1) Unit VIN = VDD PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) RPU Min. Conditions k PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.55 0.95 1.35 2.1 1. All the voltages are measured from the local ground potential. 2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range. 3. Guaranteed by design. 4. RL is the load connected on the USB OTG full speed drivers. Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state (floating input), not as alternate function. A typical 200 A current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled. Figure 56. USB OTG full speed timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 93. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol Parameter time(2) tr Rise tf Fall time(2) trfm Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Driving high or low 28 44 Rise/ fall time matching VCRS Output signal crossover voltage ZDRV Output driver impedance(3) 1. Guaranteed by design. 186/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. USB high speed (HS) characteristics Unless otherwise specified, the parameters given in Table 96 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 95 and VDD supply voltage conditions summarized in Table 94, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified * Capacitive load C = 20 pF, unless otherwise specified * Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Table 94. USB HS DC electrical characteristics Symbol Input level Parameter VDD USB OTG HS operating voltage Min.(1) Max.(1) Unit 1.7 3.6 V 1. All the voltages are measured from the local ground potential. Table 95. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit - fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 54 60 66 MHz FSTEADY Frequency (steady state) 500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 40 50 60 % DSTEADY Duty cycle (steady state) 500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition - - 1.4 ms Peripheral - - 5.6 Host - - - - - - tSTART_DEV tSTART_HOST tPREP Clock startup time after the de-assertion of SuspendM 8-bit 10% 8-bit 10% PHY preparation time after the first transition of the input clock ms s 1. Guaranteed by design. DocID029041 Rev 6 187/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 57. ULPI timing diagram #LOCK #ONTROL)N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA)N BIT T$# T$# #ONTROLOUT 5,0)?340 T$$ DATAOUT BIT AIC Table 96. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 2 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1.5 - - tSD Data in setup time - 2 - - tHD Data in hold time - 1 - - 2.7 V < VDD < 3.6 V, CL = 20 pF - 6.5 8 - - 1.7 V < VDD < 3.6 V, CL = 15 pF - 6.5 11 tDC/tDD Data/control output delay Unit ns 1. Guaranteed by characterization results. Ethernet characteristics Unless otherwise specified, the parameters given in Table 97, Table 98 and Table 99 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 20 pF * Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Table 97 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 58 shows the corresponding timing diagram. 188/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 58. Ethernet SMI timing diagram W0'& (7+B0'& WG0',2 (7+B0',22 WVX0',2 WK0',2 (7+B0',2, 069 Table 97. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol tMDC Parameter MDC cycle time(2.38 MHz) Min Typ Max 400 400 403 Td(MDIO) Write data valid time THCLK + 1 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - Unit THCLK + 1.5 THCLK + 3 ns 1. Guaranteed by characterization results. Table 98 gives the list of Ethernet MAC signals for the RMII and Figure 59 shows the corresponding timing diagram. Figure 59. Ethernet RMII timing diagram 50,,B5()B&/. WG7;(1 WG7;' 50,,B7;B(1 50,,B7;'>@ WVX5;' WVX&56 WLK5;' WLK&56 50,,B5;'>@ 50,,B&56B'9 DLE DocID029041 Rev 6 189/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 98. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 2 - - tsu(CRS) Carrier sense setup time 2 - - tih(CRS) Carrier sense hold time 2 - - td(TXEN) Transmit enable valid delay time 7.5 8 12 td(TXD) Transmit data valid delay time 7 7.5 12.5 Unit ns 1. Guaranteed by characterization results. Table 99 gives the list of Ethernet MAC signals for MII and Figure 59 shows the corresponding timing diagram. Figure 60. Ethernet MII timing diagram 0,,B5;B&/. WVX5;' WVX(5 WVX'9 WLK5;' WLK(5 WLK'9 0,,B5;'>@ 0,,B5;B'9 0,,B5;B(5 0,,B7;B&/. WG7;(1 WG7;' 0,,B7;B(1 0,,B7;'>@ AIB Table 99. Dynamics characteristics: Ethernet MAC signals for MII(1) 190/255 Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 2.5 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 0.5 - - tsu(ER) Error setup time 2.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 10 8 13 td(TXD) Transmit data valid delay time 9 7.5 13 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by characterization results. Table 100. MDIO Slave timing parameters Symbol Min Typ Max Unit Management Data clock - - 40 MHz td(MDIO) Management Data input/output output valid time 7 8 20 tsu(MDIO) Management Data input/output setup time 4 - - th(MDIO) Management Data input/output hold time 1 - - FsDC Parameter ns The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at least 1.5 times the MDC frequency: FPCLK2 1.5 * FMDC Figure 61. MDIO Slave timing diagram W0'& WG0',2 WVX0',2 WK0',2 06Y9 CAN (controller area network) interface Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). 5.3.30 FMC characteristics Unless otherwise specified, the parameters given in Table 101 to Table 114 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD DocID029041 Rev 6 191/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 62 through Figure 65 represent asynchronous waveforms and Table 101 through Table 108 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * Capcitive load CL = 30 pF In all timing tables, the THCLK is the HCLK clock period Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &-#?.% TV./%?.% T W./% T H.%?./% &-#?./% &-#?.7% TV!?.% &-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &-#?$;= T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 192/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 101. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK - 1 2 THCLK +1 0 0.5 2THCLK - 1 2THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time THCLK - 1 - tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK - 1 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - THCLK + 1 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 102. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1) Symbol Min Max FMC_NE low time 7THCLK +1 7THCLK +1 FMC_NWE low time 5THCLK -1 5THCLK +1 FMC_NWAIT low time THCLK -0.5 - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 - tw(NE) tw(NOE) tw(NWAIT) Parameter Unit ns 1. Guaranteed by characterization results. DocID029041 Rev 6 193/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW.% &-#?.%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TV!?.% &-#?!;= TH!?.7% !DDRESS TV",?.% &-#?.",;= TH",?.7% .", TV$ATA?.% TH$ATA?.7% $ATA &-#?$;= T V.!$6?.% &-#?.!$6 TW.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 103. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK - 1 3THCLK + 1 FMC_NEx low to FMC_NWE low THCLK - 1 THCLK + 0.5 THCLK - 1.5 THCLK + 0.5 THCLK - - 0 THCLK - 0.5 - - 0.5 THCLK - 0.5 - FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - THCLK + 1 tw(NADV) 1. Guaranteed by characterization results. 194/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 104. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) Min Max Unit 8THCLK - 1 8THCLK + 1 6THCLK - 1.5 6THCLK + 0.5 FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK - 1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK + 2 - ns 1. Guaranteed by characterization results. Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &-#? .% TV./%?.% T H.%?./% &-#?./% T W./% &-#?.7% TH!?./% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?./% &-#? .",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &-#? !$;= TSU$ATA?./% TH$ATA?./% $ATA !DDRESS TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 DocID029041 Rev 6 195/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 105. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Min Max 3THCLK - 1 3THCLK + 1 2THCLK 2THCLK + 0.5 THCLK - 1 THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time THCLK - 0.5 THCLK+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) THCLK + 0.5 - th(A_NOE) Address hold time after FMC_NOE high THCLK - 0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 0.5 tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time tsu(Data_NE) Data to FMC_NEx high setup time THCLK - 1 - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK - 1 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 106. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol tw(NE) tw(NOE) Parameter FMC_NE low time FMC_NWE low time Max 8THCLK - 1 8THCLK + 1 5THCLK - 1.5 5THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK + 1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid - 1. Guaranteed by characterization results. 196/255 Min DocID029041 Rev 6 4THCLK+ 1 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms TW.% &-#? .%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TH!?.7% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?.7% &-#? .",;= .", T V!?.% &-#? !$;= T V$ATA?.!$6 !DDRESS TH$ATA?.7% $ATA TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 107. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) Parameter Min Max Unit FMC_NE low time 4THCLK - 1 4THCLK + 1 FMC_NEx low to FMC_NWE low THCLK - 1 THCLK + 0.5 FMC_NWE low time 2THCLK - 0.5 2THCLK+ 0.5 FMC_NWE high to FMC_NE high hold time THCLK - 0.5 - FMC_NEx low to FMC_A valid - 0 FMC_NEx low to FMC_NADV low 0 0.5 THCLK THCLK+ 1 FMC_AD(adress) valid hold time after FMC_NADV high) THCLK - 0.5 - th(A_NWE) Address hold time after FMC_NWE high THCLK + 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK - 0.5 - tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FMC_NADV low time tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK + 0.5 - DocID029041 Rev 6 ns 197/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter FMC_NE low time FMC_NWE low time Min Max 9THCLK - 1 9THCLK + 1 Unit 7THCLK - 0.5 7THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK + 2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK - 1 - 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 66 through Figure 69 represent synchronous waveforms and Table 109 through Table 112 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable; * MemoryType = FMC_MemoryType_CRAM; * WriteBurst = FMC_WriteBurst_Enable; * CLKDivision = 1; * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM * CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified. In all the timing tables, the THCLK is the HCLK clock period. - For 2.7 VVDD3.6 V, maximum FMC_CLK = 100 MHz at CL=20 pF or 90 MHz at CL=30 pF (on FMC_CLK). - 198/255 For 1.71 VVDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK). DocID029041 Rev 6 ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 66. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+, .%X, &-#?.%X T D#,+, .!$6, TD#,+( .%X( TD#,+, .!$6( &-#?.!$6 TD#,+, !6 TD#,+( !)6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% T D#,+, !$6 &-#?!$;= TD#,+, !$)6 TSU!$6 #,+( !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 TH#,+( .7!)46 TH#,+( .7!)46 -36 DocID029041 Rev 6 199/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 109. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1. td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK - 0.5 - tw(CLK) td(CLKL-NExL) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 1.5 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 3.5 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. Guaranteed by characterization results. 200/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 67. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+( .%X( &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+( .7%( TD#,+, .7%, &-#?.7% TD#,+, !$)6 TD#,+, !$6 &-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+( .",( &-#?.", -36 DocID029041 Rev 6 201/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 110. Synchronous multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2 .5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 0.5 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. Guaranteed by characterization results. 202/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATALATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &-#?$;= TH#,+( $6 $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B $ TH#,+( .7!)46 TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 TH#,+( .7!)46 -36 Table 111. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) t(CLKL-NExL) td(CLKH-NExH) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 1.5 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 3.5 - 2 - 3.5 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high DocID029041 Rev 6 Unit ns 203/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. Figure 69. Synchronous non-multiplexed PSRAM write timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATALATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, .7%, TD#,+( .7%( &-#?.7% TD#,+, $ATA TD#,+, $ATA $ &-#?$;= $ &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TD#,+( .",( TH#,+( .7!)46 &-#?.", -36 204/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 112. Synchronous non-multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 1 - t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 1 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. NAND controller waveforms and timings Figure 70 through Figure 73 represent synchronous waveforms, and Table 113 and Table 114 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * COM.FMC_SetupTime = 0x01; * COM.FMC_WaitSetupTime = 0x03; * COM.FMC_HoldSetupTime = 0x02; * COM.FMC_HiZSetupTime = 0x01; * ATT.FMC_SetupTime = 0x01; * ATT.FMC_WaitSetupTime = 0x03; * ATT.FMC_HoldSetupTime = 0x02; * ATT.FMC_HiZSetupTime = 0x01; * Bank = FMC_Bank_NAND; * MemoryDataWidth = FMC_MemoryDataWidth_16b; * ECC = FMC_ECC_Enable; * ECCPageSize = FMC_ECCPageSize_512Bytes; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID029041 Rev 6 205/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 70. NAND controller waveforms for read access &-#?.#%X !,%&-#?! #,%&-#?! &-#?.7% TD!,% ./% TH./% !,% &-#?./%.2% TSU$ ./% TH./% $ &-#?$;= -36 Figure 71. NAND controller waveforms for write access &-#?.#%X !,%&-#?! #,%&-#?! TH.7% !,% TD!,% .7% &-#?.7% &-#?./%.2% TV.7% $ TH.7% $ &-#?$;= -36 206/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 72. NAND controller waveforms for common memory read access &-#?.#%X !,%&-#?! #,%&-#?! TH./% !,% TD!,% ./% &-#?.7% TW./% &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 Figure 73. NAND controller waveforms for common memory write access &-#?.#%X !,%&-#?! #,%&-#?! TD!,% ./% TW.7% TH./% !,% &-#?.7% &-#?. /% TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 Table 113. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max Unit 4THCLK - 0.5 4THCLK + 0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK + 1 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4THCLK - 2 - ns 1. Guaranteed by characterization results. DocID029041 Rev 6 207/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 114. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter Min Max Unit 4THCLK - 0.5 4THCLK + 0.5 FMC_NWE low width tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 - th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2THCLK - 1 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK - 1 - - 3THCLK + 1 2THCLK - 2 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid ns 1. Guaranteed by characterization results. SDRAM waveforms and timings * CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. - For 3.0 VVDD3.6 V, maximum FMC_SDCLK = 100 MHz at CL=20 pF (on FMC_SDCLK). - For 2.7 VVDD3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK). - For 1.71 VVDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on FMC_SDCLK). Figure 74. SDRAM read access waveforms (CL = 1) &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TD3$#,+,?.2!3 TH3$#,+,?.2!3 &-#?3$.2!3 TH3$#,+,?.#!3 TD3$#,+,?.#!3 &-#?3$.#!3 &-#?3$.7% TSU3$#,+(?$ATA &-#?$;= TH3$#,+(?$ATA $ATA $ATA $ATAI $ATAN -36 208/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 115. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 tsu(SDCLKH _Data) Data input setup time 1.5 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. Table 116. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 tsu(SDCLKH_Data) Data input setup time 0 - th(SDCLKH_Data) Data input hold time 4.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. DocID029041 Rev 6 209/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 75. SDRAM write access waveforms &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TH3$#,+,?.2!3 TD3$#,+,?.2!3 &-#?3$.2!3 TD3$#,+,?.#!3 TH3$#,+,?.#!3 TD3$#,+,?.7% TH3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD3$#,+,?$ATA $ATA &-#?$;= $ATA $ATAI $ATAN TH3$#,+,?$ATA TD3$#,+,?.", &-#?.",;= -36 Table 117. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - 1. Guaranteed by characterization results. 210/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 118. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 2.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. 5.3.31 Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 119 and Table 120 for Quad-SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 18: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 20 pF * Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics. Table 119. Quad-SPI characteristics in SDR mode(1) Symbol Fck1/t(CK) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 VVDD<3.6 V CL=20 pF - - 108 1.71 V<VDD<3.6 V CL=15 pF - DocID029041 Rev 6 Unit MHz - 100 211/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 119. Quad-SPI characteristics (continued)in SDR mode(1) (continued) Symbol Parameter Conditions Min Typ Max tw(CKH) tw(CKL) Quad-SPI clock high and low time - t(CK)/2 - 1 - t(CK)/2 t(CK)/2 - t(CK)/2 + 1 ts(IN) Data input setup time 0.5 - - th(IN) Data input hold time 3 - - tv(OUT) Data output valid time 2.7 V<VDD<3.6 V - 1.5 3.5 1.71 V<VDD<3.6 V - 1.5 2 th(OUT) Data output hold time - 0.5 - - - Unit ns 1. Guaranteed by characterization results. Table 120. Quad SPI characteristics in DDR mode(1) Symbol Fck1/t(CK) tw(CKH) tw(CKL) Parameter Quad-SPI clock frequency Data input setup time thr(IN), thf(IN) Data input hold time thr(OUT), thf(OUT) Min Typ Max 2.7 V<VDD<3.6 V CL=20 pF - - 80 1.8 V<VDD<3.6 V CL=15 pF - - 80 1.71 V<VDD<3.6 V CL=10 pF - - 80 t(CK)/2 - 1 - t(CK)/2 t(CK)/2 - t(CK)/2 +1 2.7 V<VDD<3.6 V 0.75 - - 1.71 V<VDD<2 V 0.5 - - 2.7 V<VDD<3.6 V 2 - - 1.71 V<VDD<2 V 3 - - 2.7 V<VDD<3.6 V - 8.5 10 1.71 V<VDD<3.6 V DHHC=0 - 8 12 DHHC=1 Pres=1, 2... - THCLK/2 + 1.5 THCLK/2 + 2.5 DHHC=0 7.5 - - DHHC=1 Pres=1, 2... THCLK/2 + 0.5 - - Quad-SPI clock high and low time ts(IN), tsf(IN) tvr(OUT), tvf(OUT) Conditions Data output valid time - Data output hold time 1. Guaranteed by characterization results. 212/255 DocID029041 Rev 6 Unit MH z ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 76. Quad-SPI timing diagram - SDR mode WU&. &ORFN W&. WZ&.+ WY287 WZ&./ WI&. WK287 'DWDRXWSXW ' ' WV,1 'DWDLQSXW ' ' WK,1 ' ' 06Y9 Figure 77. Quad-SPI timing diagram - DDR mode WU&. &ORFN W&. WYI287 'DWDRXWSXW WZ&.+ WKU287 ' WYU287 ' ' WZ&./ WKI287 ' WVI,1 WKI,1 'DWDLQSXW ' ' WI&. ' ' WVU,1 WKU,1 ' ' ' ' 06Y9 5.3.32 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 121 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 18, with the following configuration: * DCMI_PIXCLK polarity: falling * DCMI_VSYNC and DCMI_HSYNC polarity: high * Data formats: 14 bits Table 121. DCMI characteristics(1) Symbol Min Max Unit - 0.4 - - 54 MHz Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 - th(DATA) Data input hold time 0.5 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 2.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 3 - - Parameter Frequency ratio DCMI_PIXCLK/fHCLK DCMI_PIXCLK Pixel clock input DPixel ns 1. Guaranteed by characterization results. DocID029041 Rev 6 213/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 78. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WK+6<1& WVX+6<1& '&0,B+6<1& WK+6<1& WVX96<1& '&0,B96<1& WVX'$7$ WK'$7$ '$7$>@ 069 5.3.33 LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 122 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 18, with the following configuration: * LCD_CLK polarity: high * LCD_DE polarity: low * LCD_VSYNC and LCD_HSYNC polarity: high * Pixel formats: 24 bits Table 122. LTDC characteristics (1) Symbol Parameter Min Max Unit fCLK LTDC clock output frequency - 83 MHz DCLK LTDC clock output duty cycle 45 55 % tw(CLKH), tw(CLKL) Clock High time, low time tv(DATA) Data output valid time - 6 th(DATA) Data output hold time 0 ns tv(HSYNC), tv(VSYNC), tv(DE) HSYNC/VSYNC/DE output valid time - 3.5 th(HSYNC), th(VSYNC), th(DE) HSYNC/VSYNC/DE output hold time 0.5 - 1. Guaranteed by characterization results. 214/255 tw(CLK)/2-0.5 tw(CLK)/2+0.5 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 79. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY+6<1& WY+6<1& /&'B+6<1& WK'( WY'( /&'B'( WY'$7$ /&'B5>@ /&'B*>@ /&'B%>@ 1JYFM 1JYFM 1JYFM / WK'$7$ +6<1& +RUL]RQWDO ZLGWK EDFNSRUFK $FWLYHZLGWK +RUL]RQWDO EDFNSRUFK 2QHOLQH 069 Figure 80. LCD-TFT vertical timing diagram W&/. /&'B&/. WY96<1& WY96<1& /&'B96<1& /&'B5>@ /&'B*>@ /&'B%>@ -LINESDATA 96<1& 9HUWLFDO ZLGWK EDFNSRUFK $FWLYHZLGWK 9HUWLFDO EDFNSRUFK 2QHIUDPH 069 DocID029041 Rev 6 215/255 220 Electrical characteristics 5.3.34 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 123 for DFSDM are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30pF * Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM1_CKINx, DFSDM1_DATINx, DFSDM1_CKOUT for DFSDM1). Table 123. DFSDM measured timing 1.71-3.6V Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock 1.71 < VDD < 3.6 V - - fSYSCLK SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 1.71 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) fCKIN (1/TCKIN) Input clock frequency fCKOUT Output clock frequency 1.71 < VDD < 3.6 V - - 20 DuCyCKOUT Output clock frequency duty cycle 1.71 < VDD < 3.6 V 45 50 55 216/255 DocID029041 Rev 6 Unit MHz % STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 123. DFSDM measured timing 1.71-3.6V (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V 2 - - Unit ns th Data input hold time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V 3 - - TManchester Manchester data period (recovered clock period) Manchester mode (SITP[1:0]=2,3), Internal clock mode (SPICKSEL[1:0]0), 1.71 < VDD < 3.6 V (CKOUTDIV+1) * TDFSDMCLK - (2*CKOUTDIV) * TDFSDMCLK DocID029041 Rev 6 217/255 220 Electrical characteristics 5.3.35 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DFSDM timing diagrams ')6'0B&.,1\ ')6'0B'$7,1\ ')6'0B&.287 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 WVX WK 6,73 63,&.6(/ 63,&.6(/ 63,&.6(/ WVX ')6'0B'$7,1\ 63,WLPLQJ63,&.6(/ 63,WLPLQJ63,&.6(/ Figure 81. Channel transceiver timing diagrams WK WZO WZK 6,73 WVX WK 6,73 ')6'0B'$7,1\ 0DQFKHVWHUWLPLQJ 6,73 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD 069 218/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.36 Electrical characteristics SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 124 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Figure 82. SDIO high-speed mode Figure 83. SD default mode DocID029041 Rev 6 219/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 124. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =50 MHz 3.5 - - tIH Input hold time HS fpp =50 MHz 2.5 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =50 MHz - 11 12 tOH Output hold time HS fpp =50 MHz 9 - - ns CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =25 MHz 3.5 - - tIHD Input hold time SD fpp =25 MHz 2.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =25 MHz - 0.5 1.5 tOHD Output hold default time SD fpp =25 MHz 0 - - ns 1. Guaranteed by characterization results. Table 125. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS fpp =50 MHz 3 - - tIH Input hold time HS fpp =50 MHz 4 - - ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS fpp =50 MHz - 11 15.5 tOH Output hold time HS fpp =50 MHz 9.5 - - 1. Guaranteed by characterization results. 2. Cload = 20 pF. 220/255 DocID029041 Rev 6 ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. LQFP100 14x 14 mm, low-profile quad flat package information Figure 84. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline MM C ! ! 3%!4).'0,!.% # ! '!5'%0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B 6.1 E ,?-%?6 1. Drawing is not to scale. DocID029041 Rev 6 221/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 126. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 222/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Figure 85. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint AIC 1. Dimensions are expressed in millimeters. DocID029041 Rev 6 223/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP100 device making The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 86. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example 3URGXFWLGHQWLILFDWLRQ 45.' 7*5 5HYLVLRQFRGH 3 'DWHFRGH : 88 3LQLGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 224/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information GGG & Figure 87. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package outline 6($7,1* 3/$1( % $EDOO LQGH[ $EDOO DUHD LGHQWLILHU ' H $ $ $ & ' ) * ( $ % & ' ( ) * + . ( 6.2 Package information H $ %277209,(: E %$//6 HHH & $ % III & 7239,(: $4B0(B9 1. Drawing is not to scale. Table 127. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 DocID029041 Rev 6 225/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 127. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 88. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint 'SDG 'VP 1. Dimensions are expressed in millimeters. 226/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 128. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm TFBGA100 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 89. TFBGA100, 8 x 8 x 0.8mm thin fine-pitch ball grid array package top view example 3URGXFWLGHQWLILFDWLRQ 45.' 7*) 5HYLVLRQFRGH 3 'DWHFRGH %DOO$ LGHQWLILHU : 88 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 227/255 254 Package information 6.3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP144 20 x 20 mm, low-profile quad flat package information Figure 90. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'%0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. 228/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID029041 Rev 6 229/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 91. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. 230/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP144 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 92. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 3 45.';*5 : 88 3LQ LGHQWLILHU 'DWHFRGH -36 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 231/255 254 Package information 6.4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP176 24 x 24 mm, low-profile quad flat package information Figure 93. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline C ! ! ! # 3EATINGPLANE MM GAUGEPLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. 232/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 C 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - HD 25.900 - 26.100 1.0200 - 1.0276 HE 25.900 - 26.100 1.0200 - 1.0276 L 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - ZD - 1.250 - - 0.0492 - ZE - 1.250 - - 0.0492 - ccc - - 0.080 - - 0.0031 k 0 - 7 0 - 7 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID029041 Rev 6 233/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 94. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. 234/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP176 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example 3URGXFWLGHQWLILFDWLRQ 45.'**5 5HYLVLRQFRGH : 88 'DWHFRGH 3 3LQ LGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 235/255 254 Package information 6.5 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP208 28 x 28 mm low-profile quad flat package information Figure 96. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*(3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale. 236/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 131. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 -- - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1732 1.1811 1.1890 D1 27.800 28.000 28.200 1.0945 1.1024 1.1102 D3 - 25.500 - - 1.0039 - E 29.800 30.000 30.200 1.1732 1.1811 1.1890 E1 27.800 28.000 28.200 1.0945 1.1024 1.1102 E3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID029041 Rev 6 237/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 97. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint -36 1. Dimensions are expressed in millimeters. 238/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP208 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 98. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 45.'#*5 3LQ LGHQWLILHU 'DWHFRGH \HDUZHHN <:: 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 239/255 254 Package information 6.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale package information Figure 99. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package outline H ' ) $%$// /2&$7,21 * '(7$,/$ H ( $ 25,(17$7,21 5()(5(1&( H $ H 7239,(: $ $ %277209,(: 6,'(9,(: %803 6($7,1*3/$1( '(7$,/$ 527$7('R $*B:/&63B0(B9 1. Drawing is not to scale. 240/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 132. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3 - 0.025 - - 0.0010 - (2) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 5.502 5.537 5.572 0.2166 0.2180 0.2194 E 6.060 6.095 6.130 0.2386 0.2400 0.2413 e - 0.400 - - 0.0157 - e1 - 4.800 - - 0.1890 - e2 - 5.200 - - 0.2047 - F - 0.368 - - 0.0145 - G - 0.477 - - 0.0188 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - b 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. DocID029041 Rev 6 241/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 100. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP $*B:/&63B)3B9 1. Dimensions are expressed in millimeters. Table 133. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) 242/255 Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.1 mm DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information WLCSP180 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 101. WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package top view example 3URGXFWLGHQWLILFDWLRQ 45.'"*: 5HYLVLRQFRGH 'DWHFRGH : 88 3 %DOO$ LGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 243/255 254 Package information 6.7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid array package information Figure 102. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline & ^ $EDOO LGHQWLILHU $EDOO LQGH[ DUHD $ & & Z KddKDs/t EEDOOV dKWs/t HHH 0 & $ III 0 & Ds 1. Drawing is not to scale. Table 134. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3917 0.3937 0.3957 E 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 244/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Figure 103. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint 'SDG 'VP &Ws Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID029041 Rev 6 245/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx UFBGA 176+25 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 104. UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670) ,,. 'DWHFRGH %DOO$ LQGHQWLILHU < :: 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 246/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6.8 Package information TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package information Figure 105. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ ' H ; $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ' $ * ( ( H < 5 EEDOOV HHH 0 = < ; III 0 = %277209,(: 7239,(: $/B0(B9 1. Drawing is not to scale. Table 136. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 12.850 13.000 13.150 0.5118 0.5118 0.5177 D1 - 11.200 - - 0.4409 - E 12.850 13.000 13.150 0.5118 0.5118 0.5177 E1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - F - 0.900 - - 0.0354 - DocID029041 Rev 6 247/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 136. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max G - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 106. TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array package recommended footprint 'SDG 'VP $/B)3B9 Table 137. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA) Dimension 248/255 Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information TFBGA216 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 107. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package top view example 3URGXFWLGHQWLILFDWLRQ 45.' 5HYLVLRQFRGH /*) 3 %DOO$ LGHQWLILHU 'DWHFRGH : 88 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 249/255 254 Package information 6.9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 138. Package thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient TFBGA100 - 8 x 8 mm / 0.8 mm pitch 36.2 Thermal resistance junction-ambient WLCSP180 - 0.4 mm pitch 30 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm / 0.5 mm pitch 19 Thermal resistance junction-ambient UFBGA176 - 10x 10 mm / 0.5 mm pitch 39 Thermal resistance junction-ambient TFBGA216 - 13 x 13 mm / 0.8 mm pitch 29 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 250/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 7 Ordering information Ordering information Table 139. Ordering information scheme Example: STM32 F 76x V G T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 765= STM32F765xx, USB OTG FS/HS, camera interface, Ethernet 767= STM32F767xx, USB OTG FS/HS, camera interface, Ethernet, LCD-TFT 768 = STM32F768Ax, USB OTG FS/HS, camera interface, DSI host, WLCSP with internal regulator OFF 769= STM32F769xx, USB OTG FS/HS, camera interface, Ethernet, DSI host Pin count V = 100 pins Z = 144 pins I = 176 pins A = 180 pins B = 208 pins N = 216 pins Flash memory size G = 1024 Kbytes of Flash memory I = 2048 Kbytes of Flash memory Package T = LQFP K = UFBGA H = TFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DocID029041 Rev 6 251/255 254 Recommendations when using internal reset OFF Appendix A STM32F765xx STM32F767xx STM32F768Ax Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD * The over-drive mode is not supported Operating conditions Table 140. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz Maximum Flash memory access frequency with wait states (1)(2) 168 MHz with 8 wait states and over-drive OFF I/O operation Possible Flash memory operations 8-bit erase and - No I/O program compensation operations only 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from the Flash memory since the ART accelerator or L1cache allows to achieve a performance equivalent to 0-wait state program execution. 3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 2.18.1: Internal reset ON). 252/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Revision history Revision history Table 141. Document revision history Date Revision 21-Mar-2016 1 Initial release. 2 DFSDM replaced by DFSDM1 in: - Table 11: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions. - Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping. - Table 14: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses. - Section 5.3.34: Digital filter for Sigma-Delta Modulators (DFSDM) characteristics. Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts adding DFSDM1 features. Updated Table 40: Peripheral current consumption adding DFSDM1 current consumption. Updated cover in 2 pages. Update cover replacing for SPI `up to 50 Mbit/s' by `up to 54 Mbit/s'. 3 Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts GPIO number. Updated Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping adding CAN3_RX alternate function on PA8/AF11. 4 Updated Table 98: Dynamics characteristics: Ethernet MAC signals for RMII. Updated Table 72: ADC characteristics sampling rate. Updated all the notes removing `not tested in production'. Updated Figure 47: SPI timing diagram - slave mode and CPHA = 0 and Figure 48: SPI timing diagram - slave mode and CPHA = 1(1) with modified NSS timing waveforms (among other changes). Updated Table 122: LTDC characteristics clock output frequency at 65 MHz. Updated Section 5.2: Absolute maximum ratings. Updated Section 6: Package information adding information about other optional marking or inset/upset marks. 26-Apr-2016 06-May-2016 22-Dec-2016 Changes DocID029041 Rev 6 253/255 254 Revision history STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 141. Document revision history (continued) Date 09-Aug-2017 11-Sep-2017 254/255 Revision Changes 5 Updated note 1 below all the package device marking figures. Updated cover title. Updated Section 1: Description. Updated Section 2.47: DSI Host (DSIHOST) video mode interface features. Added Table 9: DFSDM implementation. Updated Figure 11: STM32F76xxx LQFP100 pinout pin 43 and pin 44. Updated Table 65: I/O current injection susceptibility note by `injection is not possible'. Updated Table 122: LTDC characteristics LTDC clock frequency at 83 MHz. Updated Table 72: ADC characteristics RADC min at 1.5 Kohm. Updated Figure 41: Recommended NRST pin protection note about the 0.1uF capacitor. Updated Table 83: DAC characteristics RLOAD feature. 6 Added TFBGA100 package: - Updated cover page. - Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts. - Updated Table 4: Regulator ON/OFF and internal reset ON/OFF availability. - Added Figure 12: STM32F76xxx TFBGA100 pinout. - Updated Table 11: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions. - Updated Table 18: General operating conditions. - Updated Table 63: ESD absolute maximum ratings. - Updated note below Figure 44: Power supply and reference decoupling (VREF+ not connected to VDDA). - Updated note below Figure 45: Power supply and reference decoupling (VREF+ connected to VDDA). - Added Section 6.2: TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information. - Updated Table 138: Package thermal characteristics. DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID029041 Rev 6 255/255 255