BRECIMNINASY fax id: 1103 CY7C1350 ic 3 cy, 128Kx36 Pipelined SRAM with NoBL Architecture Features + Pin compatible and functionally equivalentto ZBT de- vices IDT71V546, MT55L128L36P and MCM632Z736 + Supports 143-MHz bus operations with zero wait statesData is transferred on every clock . Internally self-timed output buffer control to eliminate the need to use OE Fully registered (inputs and outputs) for pipelined op- eration + Byte Write capability + 128K x 36 common I/O architecture e . Single 3.3V power supply + Fast Clock-to-output times 4.0 ns (for 143-MHz device) 4.2 ns (for 133-MHz device) 5.0 ns (for 100-MHz device) 7.0 ns (for 80-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes e . . Asynchronous output enable JEDEC-standard 100 TQFP package Burst Capability linear or interleaved burst order . . . Low standby power Functional Description The CY7C1350 is a 3.3V 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1350 is pindunctionally compatible to Z7BT SRAMs IDT71V546, MT55L128L36P and MCM632736. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previ- ous clock cycle. Maximum access delay from the clock rise is 4.0 ns (143-MHz device). Write operations are controlled by the four Byte Write Select (BWSj3.9)) and a Write Enable (WE) input. All writes are con- ducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE,, CEz, CE3) and an asynchronous output enable (OE) provide for easy bank selec- tion and output three-state control. In order to avoid bus con- tention, the output drivers are synchronously three-stated dur- ing the data portion of a write sequence. Logic Block Diagram CLK ADV/LE CONTROL and WRITE LOGIC UTPUT REGISTERS and LOGIC 128Kx36 MEMORY ARRAY Selection Guide 7C01350-143 | 7C1350-133 | 701350-100 | 7C1350-80 Maximum Access Time (ns) 4.0 42 5.0 7.0 Maximum Operating Current (mA) Commercial TBD TBD TBD TBD Maximum GMOS Standby Current (mA} Commercial TBD TBD TBD TBD NoBL is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation + 3901 NorthFirst Street + SanJose + CA95134 + 408-943-2600 March 4, 1998-Revised April 1998PASLANNASY CY7C1350 Pin Configuration 100-pin TQFP B exBVEEBER SSSR BRe2 2 ze NOOO ooo oo SSSR FFE RGR BF 6G 5 88 SB B w DP,-] 1 80 FE] DP, DQigs J 2 79 EQ DQ, DQ,, J 3 7389 DQ, Vppqh] 4 77 TF 7 Yopa Veg 5 76 [F] Veg DQi30 4 6 75] DOyg DQyg -J 7 74 [=] DQ,> DQ,, 777] 8 73;[1 0a, DQ,, _J 3 72 (1 DQ, Veg J 19 711 1 Veg Vppqg f 11 70 EI Vppg DQ2, 4 12 69 "1 DQ pa, J 13 CY7C1350 Do, Vpp 15 66 [1] Vop Vop H 16 65 Co] Vpp Ves 17 64 [] Ves DQ,, J 18 63 FE] Da; DQ,, J 19 62 1a, Vppa J 20 61 [1 Vppaq Veg | 21 60 [51 Veg DOQ,, 22 59 C7 DQ; DQ,, | 23 58] Da, DQz3 _} 24 57-1 DQ, DQ} 25 56{([] DQ, Vsgg | 26 55 [1 Ves Vppq _] 27 54 Vppe DQ,, 4 28 53 = DQ, DQ, 4 28 52 [-1 DQ, DP, _]} 30 51 fo DP, ne aneneoose &F FFP Ft a UHUUUUUYUU UU UUUUUUUUo we tate 22882282 if Ze 5 aa ao =Pin Definitions PASLANNASY CY7C1350 Pin Number | Name 0 Description 50 44, Ari6:0] Input- Address Inputs used to select one of the 131,072 address locations. Sampled at 81-82, 99, Synchronous the rising edge of the CLK. 100, 32-37 96-93 BWSi3.9 | Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the Synchronous | SRAM. Sampled on the rising edge of CLK. BWS, controls DQ)7.9) and DP, BWS, controls DQr15.a) and DPy, BWS2 controls DQjs3-16) and DP, 9 controls DQ)s1-24) and DP3. See Write Cycle description table for details. 88 WE Input- Write Enable Input, active LOW. Sampled onthe rising edge of CLK if CENis active Synchronous LOW. This signal must be asserted LOW to initiate a write sequence. 85 ADV/LD | Input- Advance/Load input used to advance the on-chip address counter or load a new Synchronous | address. When HIGH (and TEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. 8g CLK Input-Glock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. 98 CE, Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CEs, and CE; to select/deselect the device. 97 CEs Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous | conjunction with GE,,and GE, to select/deselect the device. 92 CTE3 Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous | conjunction with CE, and CE, to select/deselect the device. 86 OE Input- Output Enable, active LOW. Combined with the synchronous logic block inside the Asynchronous | device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. 87 CEN Input- Clock Enable Input, active LOW. When asserted LOW the clock signal is recog- Synchronous nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, TEN can be used to extend the previous cycle when required. 29-28, DQis1-0) | /O- Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that 25-22, Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained 19-18,13-12, in the memory location specified by Ajig-9] during the previous clock rise of the 9-6, 3-2, 79- read cycle. The direction of the pins is controlled by GE and the internal control 78, 75-72, logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, 69-68, 63-62 DQs1-9] are placed in a three-state condition. The outputs are automatically 59-56, 53-52 three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. 30, 1, 80 51 DPi3-9] /O- Bidirectional Data Parity /O lines. Functionally, these signals are identical to Synchronous DQrz1-9). During write sequences, DP, is controlled by BWSp, DP, is controlled by BWS,, Ps is controlled by BWS>2, and DP3 is controlled by BWS3.PASLANNASY CY7C1350 Pin Definitions (continued) Pin Number | Name 0 Description 31 MODE Input Strap pin | Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an inter- leaved burst order. 15,16,41,65, | Vpp Power Supply | Power supply inputs to the core of the device. Should be connected to 3.3V power 66, 91 supply. 4,11, 14,20, | Vope OQ Power Power supply for the /O circuitry. Should be connected to a 3.3V power supply. 27 ,54,61,70, Supply 77 5,10,17,21, | Vss Ground Ground for the device. Should be connected to ground of the system. 26,40,55,60, 64,67,71,76, 90 83, 84 NG - No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will be used for 256K and 512K depths respectively. 38, 39, 42,43 | DNU - Do Not Use pins. These pins should be left floating or tied to Vgs. Introduction Functional Overview The CY7C1350 is a synchronous-pipelined Burst SRAM de- signed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input regis- ters controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN}. If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tog) is 4.0 ns (143-MHz device). Accesses can be initiated by asserting all three chip enables (CE,, CE,, CE) active at the rising edge of the clock. If clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the sta- tus of the Write Enable (WE). BWS)3.9) can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE,, CEs, TE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects} are pipelined. ADV/LD should be driven LOW once the device has been de- selected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE,, CEs and CE3 are ALL asserted active, (3) the write enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs (Ag-Ay,) is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 4.0 ns (143 MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. GE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. Burst Read Accesses The GY7C1350 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use AO and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CTE,, CEs, and CE, are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to ApAj is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQj31.9) and DPi3.9). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ/31.9) and DP/3.9) (or a subset for byte write operations, see Write CyclePASLANNASY CY7C1350 Description Table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BWS)3.9) signals. The CY7C1350 provides byte write capabil- ity that is described in the Write Cycle Description table. As- serting the Write Enable input (WE) with the selected Byte Write Select (BWS)3.9)) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A Synchronous self-timed write mecha- nism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to sim- ple byte write operations. Because the CY7C1350 is a commen I/O device, data should not be driven inte the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before present- ing data to the DQja1:9) and DP/3.9) inputs. Doing so will Cycle Description Truth Table!' 2245< three-state the output drivers. As a safety precaution, DQ;a1:9] and DPy3.9) are automatically three-stated during the data por- tion of a write cycle, regardless of the state of OE. Burst Write Accesses The GY7C1350 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ad- dress, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE,, CEs, and CE3) and WE inputs are ig- nored and the burst counter is incremented. The correct BW8j3.9] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Address ADV/ Operation Used CE CEN LD WE | BWS, | CLK Comments Deselected External 1 0 L x x L-H Qs three-state following next rec- ognized clock Suspend - xX 1 xX x X L-H Clock ignored, all operations sus- pended Begin Read External 0 0 0 x L-H Address latched Begin Write External 0 0 0 Valid | LH Address latched, data presented two valid clocks later Burst Read Internal X 0 1 X X L-H Burst Read operation. Previous ac- Operation cess was a Read operation. Ad- dresses incremented internally in conjunction with the state of Mode. Burst Write Op- | Internal x 0 1 x Valid | L-H Burst Write operation. Previous ac- eration cess was a Write operation. Ad- dresses incremented internally in conjunction with the state of MODE. Bytes written are deter- mined by BWS)3.0) Notes: 1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS, = 0 signifies at least one Byte Write Select is active, BWS, = Valid signifies that the desired byte write selects are asserted, see Write Cycle description table for details. The BDO and DP pins are controll =1 inserts wait states. DoF oo po OE assumed LOW. Write is defined by WE and 3:9). See Write Cycle Description table for details. Ly the current cycle and the OE signal. Device will power-up deselected and the I/Os in a three-state condition, regardless of DE.PASLANNASY CY7C1350 Interleaved Burst Sequence Linear Burst Sequence First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax oo 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 Write Cycle Descriptions! ! Function WE BWS, BWS. BWS, BWS5) Read 1 X X X X Write No bytes written 0 1 1 1 1 Write Byte 0 (DQ)7.9) and DP9) 0 1 1 1 0 Write Byte 1 -(DQi15-a, and DP) 0 1 1 0 1 Write Bytes 1,0 0 1 1 0 0 Write Byte 2 (DQj23-16 and DP 3} 0 1 0 1 1 Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1,0 0 1 0 0 0 Write Byte 3 (DQ;31.24) and DP3) 0 0 1 1 1 Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1,0 0 0 1 0 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2,0 0 0 0 1 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write All Bytes 0 0 0 0 0PARSUAINARY CY7C1350 Maximum Ratings Current into Outputs (LOW)... eects 20 mA . . . . . Static Discharge Voltage 0... eeereenees 2001V (Above which the useful life may be impaired. For user quide- wer MIL-STD 883, Monod 3015) > lines, not tested. } Latch-Up C 200 mA Storage Temperature s.isscucsnensusesnnnnen 65C to +150C atch-Up Current... cee ceececteneeeeeenenteneee > m Ambient Temperature with Operating Range Power Applied... ee 08C to +125C Supply Voltage on V Relative to GND......... 0.5 to +4.6V Ambient pply g DD Range Temperature!! Vov/Yppe DC Voltage Applied to Outputs : in High Z Statell scssssanses wn 0.5V to Vppg + 0.5V Com 'l OG to +70C 3.3V + 5% DC Input VoltAG oo occceveevinn OSV tO Vppg + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Vop Power Supply Voltage 3.135 3.465 Vopa lO Supply Voltage 3.135 3.465 V Vou Output HIGH Voltage | Vpp = Min., log =4.0 mal! 2.4 v VoL Output LOW Voltage | Vpp = Min., lo, = 8.0 mAl 04 V Vin Input HIGH Voltage 2.0 Vpp + 0.3V Vv Vi Input LOW Voltage!*! 0.3 0.8 V lye Input Load Current GND <Vi<Vppe aa 5 HA Input Current of MODE -30 30 HA loz Ouiput Leakage GND < V/ Vopq, Output Disabled + 5 HA Current lec Vpp Operating Supply | Vop = Max., Iloy7 = 0 MA, 7.0 ns cycle, 143 MHz TBD mA f=f =f MAX ove 7.5 ns cycle, 133 MHz TBD mA 10.0 ns cycle, 1COMHz TBD mA 12.5 ns cycle, 80 MHz TBD mA Ispt Automatic CE Max. Vpp, Device Deselected, 7.0 ns cycle, 143 MHz 60 mA Power-Down Vin 2 Vin or Vin S Vie Current-TTL Inputs f=fmax = Moye 7.5 ns cycle, 133 MHz 50 mA 10.0 ns cycle, 1COMHz 40 mA 12.5 ns cycle, 80 MHz 35 mA Ispe Automatic CE Max. Vpp, Device Deselected, All speed grades TBD mA Power-Down Vin = 0.3V or Vin 2 Vopq 0.3V, Current-CMO8S Inputs |f=0 Isp3 Automatic CE Max. Vpp, Device Deselected, or | 7.0 ns cycle, 143 MHz 50 mA Power-Down Vin 0.3V or Vin = Vong 0.3V Current-CMOS Inputs | f = fmax = tHeye 7.5 ns cycle, 183 MHz 40 mA 10.0 ns cycle, 100 30 mA MHz 12.5 ns cycle, 80 MHz 25 mA Notes: 7. Minimum voltage equals -2.0V for pulse duration less than 20 ns. 8: T,, is the instant on case temperature. he load used for Vg}, and V., testing is shown in figure (b) of the A/C test conditions.PASLANNASY CY7C1350 Capacitance!'! Parameter Description Test Conditions Max. Unit Cw Input Capacitance Ta = 25C, f= 1 MHz, 6 pF : Vpp = 3.3V. Cok Clock Input Capacitance Vppa = 3.3V 6 pF Cio Input/Output Capacitance a pF AC Test Loads and Waveforms R-3170 3.3V a OUTPUT $_r [10] OUTPUT ALL INPUT PULSES Vv, = 1.5V i | INCLUDING Lk R, =500 3.0V 5 pF . + R=3519% GND JIG AND (a) SCOPE (b) 1350-2 Thermal Resistance Description Test Conditions Symbol TQFP Typ. Units Notes Thermal Resistance Still Air, soldered on a 4.25 x 1.125 inch, Qin 28 CW 13 (Junction to Ambient) 4-layer printed circuit board Thermal Resistance Qc 4 "CW 13 (Junction to Case)PASLANNASY CY7C1350 Switching Characteristics Over the Operating Range! -143 -133 -100 -80 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit teye Clock Cycle Time 7.0 75 10 12.5 ns tcy Glock HIGH 2.0 3.0 4.0 4.0 ns te Clock LOW 2.0 3.0 4.0 4.0 ns tas Address Set-Up Before CLK Rise 2.0 2.0 22 2.5 ns taH Address Hold After CLK Rise 0.5 0.5 0.5 1.0 ns teo Data Output Valid After CLK Rise 4.0 4.2 3.0 7.0 ns tpou Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns tcEnNs CEN Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns tcENH TEN Hold After CLK Rise 0.5 0.5 0.5 1.0 ns twes GW, BWS)3.9) Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns tweH GW, BWS)3.9) Hold After CLK Rise 0.5 0.5 0.5 1.0 ns taLs ADV/LD Set-Up Before CLK Rise 2.0 2.0 2.2 25 ns taLH ADV/LD Hold after CLK Rise 0.5 0.5 0.5 1.0 ns tos Data Input Set-Up Before CLK Rise 1.7 1.7 2.0 2.5 ns tou Data Input Hold After CLK Rise 0.5 0.5 0.5 1.0 ns tces Chip Enable Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns tceH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 1.0 ns tonz Clock to High-Z!!1.12-13-14] 15 135/15 1/35 115/35 1/15 | 50] ns toLz Clock to Low-Z!"1.12.13.14] 2.0 2.0 2.0 2.0 ns tEouzZ OE HIGH to Output High-Z!11.12.13.14] 4.0 4.2 5.0 7.0 | ns teoz OE LOW to Output Low-zl! 1.12.13.14] 0 0 0 0 ns teoy OE LOW to Output Valid!" 4.0 4.2 5.0 7.0 | ns Notes: 10. AG test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in part (a) of AC Test Loads. 11. toyz. toz tory teguz. and teoyz are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured+ 200 mV from steady-state voltage 12. Atany given voltage and temperature, tegyz is less than te, 7 andt, data bus. These specifications do not imply abus contention conditi to achieve High-Z prior ta Low-Z under the same system conditions. 13. Tested initially and after any design or process change that may affect these parameters. 14. This parameter is sampled and not 100% tested. is less than ty, z to eliminate bus contention between SRAMs when sharing the same ut reflect parameters guaranteed over worst case user conditions. Device is designedPASLANNASY CY7C1350 Switching Waveforms READ/WRITE/DESELECT Sequence Oo EB Q 5 Ee x Ww e kK i g e a g I 2 0 r g B WW iv < < t 4 I I o WW x ui uw > x id I iW x = oc x a wo uw) | | | | I ; io tu l CLK | | | +> | | | ickus todNH | tcH oh | eve | | | | CEN | | | ! | | | CEN HIGH bio aks all synchro 1, In/Out originally | tco | | deselected |! I The combination of WE & BWS)3.9) define a write cycle (see write cycle definition table). CE is the combination of GE,, CEs, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW. = DON'T CARE fj = UNDEFINED 10PASLANNASY CY7C1350 Switching Waveforms (continued) Burst Sequences & The combinatio oN ews gj define a write cycle CE is me sombin atio oes CEs and CE, Allc' onip er tobiee the device. Any chip enable can deselect the dev Write Adchess X, Dx stands for Data-in for ocation Xx Qx stands for Data-out for \ e write cycle definitio 1 rele) eed to be activ order to select e. RAx sta nde for Re ad Addre sX,WA stands for ocation X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS)3.q input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = DON'T CARE fj = UNDEFINED 11PASLANNASY CY7C1350 Switching Waveforms (continued) OE Timing O's Ordering Information Speed Package Operating (MHz) Ordering Code Name Package Type ange 143 CY7C1350-143AG A101 100-Lead (14x 20 x 1.4 mm) Thin Quad Flat Pack | Commercial 133 CY7C1350-133AC A101 100-Lead (14x 20 x 1.4 mm) Thin Quad Flat Pack | Commercial 100 CY7C1350-100AC A101 100-Lead (14x 20 x 1.4 mm) Thin Quad Flat Pack | Commercial 80 CY7C1350-80AC A101 100-Lead (14 x 20 x 1.4 mm} Thin Quad Flat Pack | Commercial Document #: 38-00690-A ZBT is a trademark of Integrated Device Technology. 12FRECIMINSSY CY7C1350 Package Diagram 100-Lead (14 x 20 x 1.4mm) Thin Quad Flatpack A101 DIMENSIONS ARE IN MILLIMETERS, j leooto2o 14004010 LAOH, 05 2002080 2000010 SEE DETAIL A O20 MAX, 160 MAX, i \ STAND-OFF 0.05 WIM [a.25 | : ni Mon, SEATING PLANE GAUGE PLANE wey Ne Oe Mh O50 WARK, Qe0f015 | *|p*- G20 HIN, Lao REF. = DETACL Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical componenis in life-support systems where a maliunction or failure may reasonably be expecied to resull in significant injury io the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that ihe manulacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.