TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 High-Performance Static CMOS Technology Dual 10-Bit Analog-to-Digital Conversion Includes the T320C2xLP Core CPU Module Object Compatible With the TMS320C2xx @ 28 Individually Programmable, Multiplexed Source Code Compatible With 1/O Pins TMS320C25 Phase-Locked-Loop (PLL)-Based Clock Upwardly Compatible With TMS320C5x Module 132-Pin Plastic Quad Flat Package @ Watchdog Timer Module (With Real-Time Interrupt) @ Serial Communications Interface (SCI) (PQ Suffix) 50-ns Instruction Cycle Time Industrial and Automotive Temperature Available Module Memory @ Serial Peripheral Interface (SPI) Module 544 Words x 16 Bits of On-Chip Six External Interrupts (Power Drive Data/Program Dual-Access RAM Protect, Reset, NMI, and Three Maskable 16K Words x 16 Bits of On-Chip Program Interrupts) ROM (C240)/Flash EEPROM (F240) @ Four Power-Down Modes for Low-Power 224K Words x 16 Bits of Total Memory Operation Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Scan-Based Emulation Space) @ Development Tools Available: Texas Instruments (TI) ANSI Event-Manager Module . . 12 Compare/Pulse-Width Modulation C Compiler, Assembler/Linker, and (PWM) Channels C-Source Debugger . Three 16-Bit General-Purpose Timers Scan-Based Self-Emulation (XDS510) With Six Modes, Including Continuous - Third-Party Digital Motor Control and Upand Up/Down Counting Fuzzy-Logic Development Support Three 16-Bit Full-Compare Units With Deadband Three 16-Bit Simple-Compare Units Four Capture Units (Two With Quadrature Encoder-Pulse Interface Capability) description The TMS320C240 and TMS320F 240 devices are the first members of a new family of DSP controllers based on the TMS320C2xx generation of 16-bit fixed-point digital signal processors (DSPs). Unless otherwise noted, the term x240 refers to both the TMS320C240 and the TMS320F240. Table 1 provides a comparison of the features of each device. The only difference between these two devices is the type of program memory: the C240 contains 16K words of ROM and the F240 contains 16K words of flash. This new family is optimized for digital motor/motion control applications. The DSP controllers combine the enhanced TMS320 architectural design of the C2xLP core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications. These peripherals include the event manager module, which provides general-purpose timers and compare registers to generate up to 12 PWM outputs, and a dual10-bit analog-to-digital converter (ADC), which can perform two simultaneous conversions within 6.1 us. See the functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Tl and XDS510 are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments 73 standard warranty. Production processing does not necessarily include testing of all parameters. EXAS Copyright 1998, Texas Instruments Incorporated INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 1TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Contents INTRODUCTION description ............... 000. teen teens PQ Package (Top View) .............00 00. c ccc cent e teen eee terminal functions ................. 2.00000. ccc eee functional block diagram ................ 0. cece tees architectural overview .............. 0.0 cece tte tenes system-level functions ............. 0.000. c cee device MeMory MAP...... 6... ees peripheral memory Map .......... 00 eee digital |/O and shared pin functions ................. 000020020 cece eee description of group! shared I/O pinS ............ 0.0. cece ee description of group2 shared I/O pinS ........... 00.0 eee digital /O control registers ............ 0000s device reset and interrupts ......... 0... cece eee FOSEt tenet teat eee eens hardware-generated interrupts ......... 0... cece eee external interruptS ........ 0... ett neees Clock generation ........ 00. cette teens low-POWEr MOCES ... 1... tenets functional block diagram of the TMS320x240 DSP CPU ............... *x240 DSP core CPU ............ 0. teens status and control registerS 60... knees central processing Unit ......... 0... tees input scaling shifter .... 0.0... eee multiplier 20... teen tt eee nee central arithmetic logic unit ......... 0... ec ees acCUMUIatOr .. 1.6 tte tne tenes auxiliary registers and auxiliary-register arithmetic unit (ARAU) ......... internal Memory ............. 0006. teen teen dual-access RAM (DARAM) ........... 0000: c cece eee eee ROM (TMS320C240 only) .......... 0.0020 c cece tenes flash EEPROM (TMS320F240 only) .............. 0000 cece eee eee flash Serial loader ....... 0... eect ett e tne es flash control mode register ........ 0.0... eee ees peripherals .......... 0... c ect ete eee external memory interface ....... 0.0... tees Noo = 13 13 13 15 16 16 18 18 18 19 20 26 27 29 30 33 33 34 34 34 36 37 37 37 37 38 38 38 38 39 39 wy TEXAS INSTRUMENTS 2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Contents DETAILED DESCRIPTION (continued) event-manager (EV) module ............ 00. c cece ees general-purpose (GP) timerS ..... 0.0... eee ees fullcompare UNiItS 6... eee programmable-deadband generator ................2.0000e eee Simple COMPArES .... 2... tenes compare/PWM waveform generation .............. 0.0: eee eee compare/PWMs characteristics .................-+2-+0eeee eee ee capture unit ........ 2.0.0.0 ett quadrature-encoder pulse (QEP) circuit ............... 0... analog-to-digital converter (ADC) module ....................02-25- serial peripheral interface (SPI) module .....................2..005. serial communications interface (SCI) module ...................... watchdog (WD) and real-time interrupt (RTI) module ................ scan-based emulation ............... 006.0 c eens TMS320x240 instruction set ............... 0.0... cece ee ees addressing modes ..............0 0.0 c eee eet eee repeat feature 2.0... cette eee instruction Set SUMMAarY ..... 0... 6c eens development support .............0. 000s device and development-support tool nomenclature ................ documentation support ..............0.0.... 000 eee ELECTRICAL SPECIFICATIONS absolute maximum ratings over operating free-air temperature range recommended operating conditions .................. 0.0 cere eee output current variation with output voltage: SPICE simulation results elec characteristics over recommended oper free-air temperature range signal transition levels ............... 00... ees timing parameter symbology .................. 5.00 cece ees general notes on timing parameters ................ 0.000. c eee eee Clock Options ............. 000. cee tenets timings with the PLL circuit disabled ..................02.00.00 cee ee external reference crystal with PLL-circuit-enabled clock option ......... timings with the PLL circuit enabled ..................02000 0. eee eee low-power mode timingS ............. 0.0.0. cece 40 40 42 42 42 42 42 42 43 43 45 47 49 51 51 51 51 52 58 59 60 61 61 62 62 63 65 65 66 66 67 67 69 Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Contents ELECTRICAL SPECIFICATIONS (continued) memory and parallel I/O interface readtimings ....................... 71 memory and parallel I/O interface write timings ...................... 73 /O timing variation with load capacitance: SPICE simulation results ... 75 READY timingS ........... 0.0.00 cece eet t eee 76 RS and PORESET timings ...............00.0 00.000 ccc cece cece neues 77 XF, BIO, and MP/MC timings ............0..0..00.0 00.0.0 c cece cece eee 79 PWM/CMP timings ...................0. 0.0 cect tees 80 capture and QEP timings .................... 0.00: cece cee ees 81 interrupt timingS ............. 006... teen eee 82 general-purpose input/output timings ............................--. 83 serial communications interface (SCI) I/O timings .................... 84 SPI master mode external timing parameters (clock phase = 0) ........ 85 SPI master mode external timing parameters (clock phase =1)........ 87 SPI slave mode external timing parameters (clock phase =0) ......... 89 SPI slave mode external timing parameters (clock phase =1) ......... 91 10-bit dual analog-to-digital converter (ADC) ......................... 93 ADC input pin circuit ...............0.0 00.00 94 flash EEPROM ............... 00.0000 c cece etc tt ett eeeeeees 96 programming operation ....... 0... teens 96 erase operation... 00... eee eee 96 flash-write operation... 00... tt tenes 96 register file compilation .............0... 000. c ccc eee 97 package drawing, PQ (S-PQFP-G***), PLASTIC QUAD FLATPACK ...... 104 wy TEXAS INSTRUMENTS 4 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PQ PACKAGE (TOP VIEW) PIT w/R {ir ] D6 16 NOD Ds (Ir D4 PIT Vss HI dvpp (Ir) ps (Il) b2 (Tt) D1 TTT] Do [IT] CVss PIT) CVpp (Il STRB BR RW TIT] Vss FI pvpp Pr] WE Ir] PS Pir) Is IT] DS CIT] Ais Tr] Ai4 IT] Ai3 [Ir] At2 rir) Ati /IT] Aio (Tr) Ag Ir) DVpp (It Vss (Tr) As IT] A7 (Ir) A REET HAT Seen oH ron ADR RREHRARKRNTR SLE b7 Cory | 18 QS tt cr] As bs Cory | 19 15 |r) Vss C-IT4 |} 20 114 | FT) AB DVpp C-IL4} 21 113 | FT Vss be (Ir | 22 iz |r += ze Dio [oI | 23 41{/fr 7 a D11 Coorg | 24 110 |r Ao Di2 (COI | 25 jo9 | (Ss TMRCLK/IOPB7 D13 (COI | 26 108 | {[1T]_- TMADIR/IOPBS D14 COI | 27 107 | 1C)_:s-T3PWM/T3CMP/IOPBS D15 [Cor | 28 jos |): T2PWM/T2CMP/IOPB4 Vgg CUE] | 29 105 | [1T]_s-T1PWM/TIGMP/IOPB3 TcK CCWIr}} 30 104 | C+ vss To! Cory | 31 jos |[AC Dvpp TRST Cory] 22 jo2 | Fr) Pwueycmpe/loPpB2 Ts CHIT] 33 TMS320C240 tot | [17s pwmarompsioPBt TDo Cr] 34 TMS320F240 100 | [Is Pwwv7/omP7/l0PBo RS CCIrg} 35 99 | 1C)-pwwe/cups READY C_IL]| 36 98 | FCS pwes/cmps MP/MG CIC] | 37 97 |r Ss pwmacmp4 EMUo CIC} } 38 96 | Cs pwa/cmp3 EMU1/OFF CX=IC} | 30 95 |r) pwmecmp2 NMI COIC} } 40 94 |) pwei/cmp1 PORESET CID] 41 93 | ~DVpp RESERVED CIC} | 42 g2 |r vss SCIRXD/IO CCoIry | 43 91 | $= aApcina/lopas3 SCITXD/O CZIL}} 44 90 | FAC) adcing/iopa2 SPISIMO/O COIL4 | 45 g9 | C $apcinio Vss Cor] | 46 g8 | = apcinit DVpp C-Il}} 47 87 |FAC) ~Vssa SPISOMIIO COIL4 | 48 86 |] ~Vperio SPICLK/IO C-IE} | 49 85 | FID VRerHi wbbist C-Ir} } 50 84 | Veca BEBSBEE BBBSSRPSBSBSESBBRERKRREKRRRRKRBBHB - a = = SIZES SESE2 S358 OS88 S85 RRR 2222 225555 bX 2 Bk e 889555955" 993388 885095 Qh 66 = SETSLEaAaF StFEACttce eegaag a. x x10 Z 92lsaGa4 Zz tatiaced ke 82 G@GS6 BE 23 a & << 5&6 t For the TMS320F240 devices, this pin is Vocp/WDDIS. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 5TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Terminal Functions TERMINAL NAME No. TYPEt DESCRIPTION EXTERNAL INTERFACE DATA/ADDRESS SIGNALS AO (LSB) 110 Al 111 A2 112 A3 114 A4 115 A5 116 A6 117 Parallel address bus AO [least significant bit (LSB)] through A15 [most significant bit (MSB)]. A15AO A7 118 O/Z are multiplexed to address external data/program memory or I/O. A15AO are placed in A& 119 high-impedance state when EMU1/OFF is active low and hold their previous states in power-down AQ 122 modes. A10 123 All 124 Al2 125 Al3 126 Al4 127 A15 (MSB) 128 DO (LSB) 9 D1 10 D2 11 D3 12 D4 15 D5 16 D6 17 Parallel data bus DO (LSB) through D15 (MSB). D15D0 are multiplexed to transfer data between the D7 18 VOIZ TMS320x240 and external data/program memory and I/O space (devices). D15D0 are placed in the D8 19 high-impedance state when not outputting, when in power-down mode, when reset (RS) is asserted, D9 22 or when EMU1/OFF is active low. D10 23 D1i1 24 D12 25 D13 26 D14 27 D15 (MSB) 28 EXTERNAL INTERFACE CONTROL SIGNALS DS 129 Data, program, and I/O space select signals. Ds, PS, andIS are always high unless low-level asserted PS 131 O/Z for communication to a particular external space. They are placed in the high-impedance state during IS 130 reset, power down, and when EMU1/OFF is active low. Data ready. READY indicates that an external device is prepared for the bus transaction to be READY 36 completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. _ Read/write signal. RW indicates transfer direction during communication to an external device. It is R/AW 4 O/Z normally in read mode (high), unless low level is asserted for performing a write operation. It is placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. STRB 6 Olz Strobe. STRB is always high unless asserted low to indicate an external bus cycle. It is placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. Write enable. The falling edge of WE indicates that the device is driving the external data bus WE 1 O/Z (D15D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I/O writes. WE goes in the high-impedance state following reset and when EMU1/OFF is active low. wR 132 Olz Write/read. w/R is an inverted form of R/W and can connect directly to the output enable of external devices. W/Ris placed in the high-impedance state following reset and when EMU 1/OFF is active low. tis input, O = output, Z = high impedance wy TEXAS INSTRUMENTS 6 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Terminal Functions (Continued) TERMINAL NAME NO. TyPet DESCRIPTION EXTERNAL INTERFACE CONTROL SIGNALS (CONTINUED) Bus request. BR is asserted during access of external global data memory space. BR can be BR 5 O/Z used to extend the data memory address space by up to 32K words. BR goes in the high-impedance state during reset, power down, and when EMU1/OFF is active low. Flash-programming voltage supply. If Vccp = 5 V, then WRITE/ERASE can be made to the ENTIRE on-chip flash memory blockthat is, for programming the flash. If Vccp = 0 V, then Wbopist 50 WRITE/ERASE of the flash memory is not allowed, thereby protecting the entire memory block from being overwritten. WDDIS also functions as a hardware watchdog disable. The watchdog timer is disabled when Vccp/WDDIS = 5 V and bit 6 in WDCR is set to 1. ADC INPUTS (UNSHARED) ADCIN2 74 | ADCIN3 75 | ADCIN4 76 | Analog inputs to the first ADC ADCINS5 77 | ADCING6 78 | ADCIN7 79 | ADCIN10 89 | ADCIN11 88 | ADCIN12 83 | Analog inputs to the second ADC ADCIN13 82 | ADCIN14 81 | ADCIN15 80 | BIT /O AND SHARED FUNCTIONS PINS Bidirectional digital I/O. ADCINO/IOPAO 72 0 Analog input to the first ADC. ADCINO/IOPAO is configured as a digital input by all device resets. Bidirectional digital I/O. ADCIN1/IOPA1 73 0 Analog input to the first ADC. ADCIN1/IOPA1 is configured as a digital input by all device resets. Bidirectional digital I/O. ADCIN9/IOPA2 90 0 Analog input to the second ADC. ADCIN9/IOPA2 is configured as a digital input by all device resets. Bidirectional digital I/O. ADCIN8/IOPA3 91 0 Analog input to the second ADC. ADCIN8/IOPAS3 is configured as a digital input by all device resets. Bidirectional digital I/O. Simple compare/PWM 1 output. The state of PWM7/CMP7/IOPBO is determined by the simple compare/PWM and the simple action control register (SACTR). It goes to the high-impedance state when unmasked PDPINT goes active low. PWM7/CMP7/IOPB0 is configured as a digital input by all device resets. Bidirectional digital I/O. Simple compare/PWM 2 output. The state of PWM8/CMP8/IOPB1 is determined by the simple compare/PWM and the SACTR. It goes to the high-impedance state when unmasked PDPINT goes active low. PWM8/CMP8/IOPB1 is configured as a digital input by all device resets. Bidirectional digital I/O. Simple compare/PWM 3 output. The state of PWM9/CMP9/IOPB2 is determined by the simple compare/PWM and SACTR. It goes to the high-impedance state when unmasked PDPINT goes active low. PWM9/CMP9/IOPBz2 is configured as a digital input by all device resets. PWM7/CMP7/IOPBO 100 VO/Z PWM8/CMP8/IOPB1 101 VO/Z PWM9/CMPY/IOPB2 102 VO/Z tis input, O = output, Z = high impedance + For the TMS320F 240 devices, this pin is VCCP/WDDIS- Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 7TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Terminal Functions (Continued) TERMINAL NAME No. TYPEt DESCRIPTION BIT /O AND SHARED FUNCTIONS PINS (CONTINUED) T1PWM/TiCMP/ Bidirectional digital 1/O. Timer 1 compare output. TIPWM/T1 CMP/IOPB3 goes to the high- IOPB3 105 VOlZ impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. T2PWM/T2CMP/ Bidirectional digital /O. Timer 2 compare output. T2PWM/T2CM P/IOPB4 goes to the high- IOPB4 106 VOlZ impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. T3PWM/T3CMP/ Bidirectional digital 1/O. Timer 3 compare output. T3PWM/T3CM P/OPBS goes to the high- IOPB5 107 VOlZ impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. Direction signal for the timers. Up-counting direction if TARDIR/IOPB6 TMRDIR/IOPB6 108 VO is low, down-counting direction if this pin is high. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. TMRCLK/IOPB7 109 VO External clock input for general-purpose timers. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. ADCSOC/IOPCO 63 VO External start of conversion input for ADC. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. CAP1/QEP 1/OPC4 67 VO Capture 1 or QEP 1 input. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. CAP2/QEP2/IOPC5 68 VO Capture 2 or QEP 2 input. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. CAP3/IOPC6 69 VO Capture 3 input. This pin is configured as a digital input by all device resets. Bidirectional digital I/O. CAP4/IOPC7 70 VO Capture 4 input. This pin is configured as a digital input by all device resets. Bidirectional digital 1/O. External flag output (latched software-programmable signal). XF is XF/IOPC2 65 VO used for signaling other processors in multiprocessing configurations or as a general-purpose output pin. This pin is configured as an external flag output by all device resets. __ Bidirectional digital I/O. Branch control input. BlOis polled by the BIOZ instruction. IfBIOis low, BIO/IOPC3 66 VO the CPU executes a branch. If BIO is not used , it should be pulled high. This pin is configured as a branch-conitrol input by all device resets. Bidirectional digital I/O. Clock output. Clock output is selected by the CLKSRC bits in the CLKOUTIOPC1 64 V0 SYSCR register. This pin is configured as a DSP clock output by a power-on reset. SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS SCI asynchronous serial port transmit data, or general-purpose bidirectional I/O. This pin is SCITXD/IO 44 vO configured as a digital input by all device resets. SCI asynchronous serial port receive data, or general-purpose bidirectional I/O. This pin is SCIRXD/IO 48 vO configured as a digital input by all device resets. tis input, O = output, Z = high impedance wy TEXAS INSTRUMENTS 8 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Terminal Functions (Continued) TERMINAL t DESCRIPTION NAME NO. TYPE SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS SPISIMO/IO 45 VO SPI slave in, master out , or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SPISOMI/IO 48 VO SPI slave out, master in, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SPICLK/IO 49 0 SPI clock, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SPISTE/IO 541 VO SPI slave transmit enable (optional), or general-purpose bidirectional I/O. This pinis configured as a digital input by all device resets. COMPARE SIGNALS PWM1/CMP1 94 Mave Ps oe Compare units compare or PWM outputs. The state of these pins is determined by the O/Z compare/PWM and the full action control register (ACTR). CMP1CMP6 go to the high- PWM4/CMP4 97 impedance state when unmasked PDPINT goes active low, and when reset (RS) is asserted PWM5/CMP5 98 P g PWM6/CMP6 99 INTERRUPT AND MISCELLANEOUS SIGNALS _ Reset input. RS causes the TMS320x240 to terminate execution and sets PC = 0. When RS RS 35 0 is brought to a high level, execution begins at location zero of program memory. RS affects (or sets to zero) various registers and status bits. MP/MG (microprocessor/microcomputer) select. If MP/MC is low, internal program memory is MP/MG 37 ie Ls : selected. If itis high, external program memory is selected. NMI 40 Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state of the INTM bit of the status register. NMI has programmable polarity. Power-on reset. PORESET causes the TMS320x240 to terminate execution and sets PC = 0. DBADLCET When PORESET is brought to a high level, execution begins at location zero of program PORESET 4 memory. PORESET affects (or sets to zero) the same registers and status bits as RS. In addi- tion, PORESET initializes the PLL control registers. XINT1 53 I External user interrupt no. 1 XINT2/O 5A VO External user interrupt no. 2. General-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. XINT3/O 55 VO External user interrupt no. 3. General-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. ee Maskable power-drive protection interrupt. If PDPINT is unmasked and it goes active low, the PDPINT 52 : : : vo timer compare outputs immediately go to the high-impedance state. CLOCK SIGNALS PLL oscillator output. XTAL2 is tied to one side of a reference crystal when the device is in PLL XTAL2 57 O mode (CLKMD[1:0] = 1x, CKCRO.7-6). This pin can be left unconnected in oscillator bypass mode \SScBYP < VIL). This pin goes in the high-impedance state when EMU1/OFF is active low. PLL oscillator input. XTAL1/CLKIN is tied to one side of a reference crystal in PLL mode XTAL1/CLKIN 58 VZ (CLKMD[1:0] = 1x, CKCRO.76), or is connected to an external clock source in oscillator bypass mode (OSCBYP < Vj,). OSCBYP 56 I Bypass oscillator if low Ti= input, O = output, Z = high impedance Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 9TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Terminal Functions (Continued) TERMINAL NAME No. TYPEt DESCRIPTION SUPPLY SIGNALS CVss 8 Digital core logic ground reference 3 14 20 29 46 59 a . Vss 61 Digital logic ground reference 71 92 104 113 120 VSSA 87 Analog ground reference 2 13 21 47 a . DVpp 62 Digital I/O logic supply voltage 93 103 121 7 CVpp 60 I Digital core logic supply voltage VCCA 84 | Analog supply voltage VREFHI 85 I ADC analog voltage reference high VREFLO 86 I ADC analog voltage reference low TEST SIGNALS IEEE standard test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The TCK 30 changes on test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test data register of the 'C2xx core on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. IEEE standard test data input (TDI). TDI is clocked into the selected register (instruction or data) on TDI 31 7 a rising edge of TCK. IEEE standard test data output (TDO). The contents of the selected register (instruction or data) are TDO 34 O/Z shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state when OFF is active low. IEEE standard test mode select. This serial control inputis clocked into the TAP controller on the rising TMS 33 | edge of TCK. tis input, O = output, Z = high impedance wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Terminal Functions (Continued) TERMINAL NAME NO. TYPEt DESCRIPTION TEST SIGNALS (CONTINUED) TRST 32 IEEE standard test reset. TRST, when active low, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. EMUO 38 VO/Z Emulator pin 0. When TRST is driven low, EMUO must be high for activation of the /OFF condition. When TRST is driven high, EMUO is used as an interrupt to or from the emulator system and is defined as input/output through the scan. EMU1/OFF 39 VO/Z Emulator pin 1/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output through JTAG scan. When TRST is driven low, this pin is configured as OFF. When EMU1/OFF is active low, it puts all output drivers in the high-impedance state. OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications); therefore, for OFF condition, the following conditions apply: TRST = low, EMUO = high, EMU1/OFF = low. RESERVED 42 Reserved for test. This pin has an internal pulldown and must be left unconnected for the F240. On the C240, this pin is a no connect. tis input, O = output, Z = high impedance Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 11TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 functional block diagram Memory Control Interrupts Initialization t The C240 device contains ROM; the F240 device contains Flash EEPROM. Data Bus | Test/ 7 y y Emulation [ 7 ROM or Flash DARAM DARAM EEPROMt Bo B1/B2 External 41 A A A +> Memory _> Program Bus v v v Interface A A v : Software C2xx >| wait-State Instruction CPU Generation Register Program 4 4 Controller Event Input ARAU Shifter Multiplier Manager Status/ General- 4 Control ALU TREG Purpose fear Registers Timers Auxiliary A lat PREG nid Registers ccumulator Compare 9 Unite Memory- Mapped Output Product Registers Shifter Shifter Capture/ 4 i i a Quadrature | Le gaep Encoder Vv Vv 4 Pulse (QEP) 4 PDPINT 4 > ===> Interrupts Clock System-Interface 20 _ <> ep D II /01 3 Module Module igital Input/Output -- /4- Reset A v Peripheral Bus A A A A Vv Y Vv Y Dual 10-Bit Serial- Serial- Analog- Peripheral Communications Watchdog to-Digital Interface Intertace Timer Converter fe f f? wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443description (continued) Table 1. Characteristics of the *x240 DSP Controllers TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 ON-CHIP MEMORY (WORDS) POWER CYCLE PACKAGE ore RAM ROM CEPR SUPPLY TIME TYPE (Vv) (ns) PIN COUNT DATA DATA/PROG PROG PROG TMS320C240 288 256 16K - 50 PQ 132-P TMS320F240 288 256 - 16K 50 PQ 132-P architectural overview The functional block diagram provides a high-level description of each component in the *x240 DSP controller. The TMS320x240 devices are composed of three main functional units: a *C2xx DSP core, internal memory, and peripherals. In addition to these three functional units, there are several system-level features of the x240 that are distributed. These system features include the memory map, device reset, interrupts, digital input/output (I/O), clock generation, and low-power operation. system-level functions device memory map The TMS320x240 implements three separate address spaces for program memory, data memory, and I/O. Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the top of the address range can be defined to be external global memory in increments of powers of two, as specified by the contents of the global memory allocation register (GREG). Access to global memory is arbitrated using the global memory bus request (BR) signal. On the x240, the first 96 (O5Fh) data memory locations are either allocated for memory-mapped registers or are reserved. This memory-mapped register space contains various control and status registers including those for the CPU. All the on-chip peripherals of the x240 device are mapped into data memory space. Access to these registers is made by the CPU instructions addressing their data-memory locations. Figure 1 shows the memory map. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 13TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 device memory map (continued) Program Program Data Hex Hex Hex oo00 Interrupts 0000 Interrupts 0000 | Memory-Mapped -Chi Registers and oo3F] __ - External) | 4 003F | _ _(Ore nip) Reserved 0040 0040 0080 On-Chip ROMT On-Chi (Flash EEPROM) D ARAM 8 5 (8 x 2K Segments) 3FFF 007F External 4000 0080 External Reserved FDFF FDFF 01FF FEOO | On-Chip DARAM BO FE00 | on-chip DARAM BO 0200 (CNF = 1) (CNF = 1) On-Chip DARAM Bo or or (CNF = 0) FEeFF| External (CNF = 0) FEFF| External (CNF = 0) or FFoo FFOoo Reserved (CNF = 1) Reserved Reserved O2FF FFFF 0300 FFFF TROM/Flash memory includes eran address range 0000h003Fh O3FF MP/MC = 1 MP/MC = 0 0400 Reserved Microprocessor Microcomputer 07FF Mode Mode 0800 IHlegal 6FFF 7000 Vo ee enera emery: lapped Registers soca (System, WD, ADC, SPI, SCI, Interrupts, 1/O) 73FF 7400 Peripheral External Memory-Mapped Registers (Event Manager) 743F FEFF 7440 Reserved 77FF FFOO 7800 Reserved Illegal FFOE 7FFF 8000 FFOF Flash Control External Mode Register FFFF FF10 Reserved FFFE FFFEF| Wait-state Generator Control Register Figure 1. TMS320x240 Memory Map wy TEXAS INSTRUMENTS 14 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443peripheral memory map TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 The TMS320x240 system and peripheral control register frame contains all the data, status, and control bits to operate the system and peripheral modules on the device (excluding the event manager). Hex 0000 005F 0060 007F 0080 O1FF 0200 02FF 0300 O3FF 0400 O7FF 0800 6FFF 7000 73FF 7400 743F 7440 77FF 7800 7FFF 8000 FFFF Reserved Interrupt-Mask Register Memory-Mapped Registers and Reserved Global-Memory Allocation Register Interrupt Flag Register On-Chip DARAM B2 Reserved Emulation Registers and Reserved Illegal On-Chip DARAM BO (CNF = 0) Reserved (CNF = 1) System Configuration and Control Registers Watchdog Timer and PLL Control Registers On-Chip DARAM B1 ADC SPI Reserved scl Illegal External-Interrupt Registers IHegal Illegal Peripheral Frame 1 Digital-I/O Control Registers Illegal Peripheral Frame 2 Reserved IHegal General-Purpose Timer Registers External Reserved Compare, PWM, and Deadband Registers Reserved Capture & QEP Registers Reserved Interrupt Mask, Vector and Flag Registers Reserved Figure 2. Peripheral Memory Map Hex 0000 0003 0004 0005 0006 0007 O05F 7000 700F 7010-701F 7020 -702F 7030 -703F 7040 -704F 7050 -705F 7060 -706F 7070-707F 7080 708F 7090709F 70A0-73FF 7400-740C 740D-7410 7411-741C 741D-741F 7420-7426 7427-742B 7420-7434 7435-743F wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 15TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 digital I/O and shared pin functions The C240 has a total of 28 pins shared between primary functions and I/Os. These pins are divided into two groups: @ Group1 Primary functions shared with I/Os belonging to dedicated I/O ports, Port A, Port B, and Port C. Group2 Primary functions belonging to peripheral modules which also have a built-in I/O feature as a secondary function (for example, SCI, SPI, external interrupts, and PLL clock modules). description of group? shared I/O pins The control structure for Group1 type shared I/O pins is shown in Figure 3. The only exception to this configuration is the CLKOUT/IOPC1 pin. In Figure 3, each pin has three bits that define its operation: @ Mux control bit this bit selects between the primary function (1) and I/O function (0) of the pin. @ 1/O direction bit if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines whether the pin is an input (0) or an output (1). @ |/Odata bit if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers. IOP Data Bit " (Read/Write) Primary Function In Out IOP DIR Bit 0 = Input \W 1 = Output Note: When the MUX control bit = 1, the primary function is selected in all cases except for the following pins: 1. XF/IOPC2 (0 = Primary Function) Te 2. BIONOPC3 (0 = Primary Function) od 1 MUX Control Bit - _ 0 = I/O Function 1 = Primary Function Primary . Function | Pin or I/O Pin Figure 3. Shared Pin Configuration A summary of Group1 pin configurations and associated bits is shown in Table 2. wy TEXAS INSTRUMENTS 16 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443description of group? shared I/O pins (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 2. Group1 Shared Pin Configurations MUX CONTROL PIN FUNCTION SELECTED VO PORT DATA AND DIRECTIONT PIN # REGISTER (name.bit #) (CRx.n = 1) (CRx.n = 0) REGISTER DATA BIT# DIRBIT# 72 OCRA.O ADCINO IOPAO PADATDIR 0 8 73 OCRA.1 ADCIN1 IOPA1 PADATDIR 1 9 90 OCRA.2 ADCIN9 IOPA2 PADATDIR 2 10 91 OCRA.3 ADCIN8 IOPA3 PADATDIR 3 11 100 OCRA.8 PWM7/CMP7 IOPBO PBDATDIR 0 8 101 OCRA.9 PWM8&/CMP8 IOPB1 PBDATDIR 1 9 102 OCRA.10 PWM9/CMP9 IOPB2 PBDATDIR 2 10 105 OCRA.11 TIPWM/T1CMP IOPB3 PBDATDIR 3 11 106 OCRA.12 T2PWM/T2CMP IOPB4 PBDATDIR 4 12 107 OCRA.13 T3PWM/T3CMP IOPBS PBDATDIR 5 13 108 OCRA.14 TMRDIR IOPB6 PBDATDIR 6 14 109 OCRA.15 TMRCLK IOPB7 PBDATDIR 7 15 63 OCRB.O ADCSOCG IOPCO PCDATDIR 0 8 64 SYSCR.7-6 00 IOPC1 PCDATDIR 1 9 01 WDCLK _ _ _ 10 SYSCLK _ _ _ 11 CPUCLK _ _ _ 65 OCRB.2 IOPC2 XF PCDATDIR 2 10 66 OCRB.3 IOPC3 BIO PCDATDIR 3 11 67 OCRB.4 CAP1/QEP1 IOPC4 PCDATDIR 4 12 68 OCRB.5 CAP2/QEP2 IOPC5 PCDATDIR 5 13 69 OCRB.6 CAP3 IOPC6 PCDATDIR 6 14 70 OCRB.7 CAP4 IOPC7 PCDATDIR 7 15 tT Valid only if the I/O function is selected on the pin. wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 17TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 description of group2 shared I/O pins Group2 shared pins belong to peripherals that have built-in general-purpose I/O capability. Control and configuration for these pins are achieved by setting the appropriate bits within the control and configuration registers of the peripherals. Table 3 lists the Group2 shared pins. Table 3. Group2 Shared Pin Configurations PIN # PRIMARY FUNCTION REGISTER ADDRESS PERIPHERAL MODULE 43 SCIRXD SCIPC2 705Eh Sc 44 SCITXD SCIPC2 705Eh Sc 45 SPISIMO SPIPC2 704Eh SPI 48 SPISOMI SPIPC2 704Eh SPI 49 SPICLK SPIPC1 704Dh SPI 51 SPISTE SPIPC1 704Dh SPI 54 XINT2 XINT2CR 7078h External Interrupts 55 XINT3 XINT3CR 707Ah External Interrupts digital I/O control registers Table 4 lists the registers available to the digital I/O module. As with other x240 peripherals, the registers are memory-mapped to the data space. Table 4. Addresses of Digital I/O Control Registers ADDRESS REGISTER NAME 7090h OCRA /(O mux control register A 7092h OCRB /O mux control register B 7098h PADATDIR I/O port A data and direction register 709Ah PBDATDIR I/O port B data and direction register 709Ch PCDATDIR I/O port C data and direction register device reset and interrupts The TMS320x240 software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The x240 recognizes three types of interrupt sources: Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any other executing functions. All maskable interrupts are disabled until the reset service routine enables them. @ Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two types: External interrupts are generated by one of five external pins corresponding to the interrupts XINT1, XINT2, XINT3, PDPINT, and NMI. The first four can be masked both by dedicated enable bits and by the CPUs interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI, which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can be locked out only by an already executing NMI or a reset. Peripheral interrupts are initiated internally by these on-chip peripheral modules: the event manager, SPI, SCI, watchdog/real-time interrupt (WD/RTI), and ADC. They can be masked both by enable bits for each event in each peripheral and by the CPUs IMR, which can mask each maskable interrupt line at the DSP core. wy TEXAS INSTRUMENTS 18 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 device reset and interrupts (continued) reset Software-generated interrupts for the x240 device include: The INTR instruction. This instruction allows initialization of any x240 interrupt with software. Its operand indicates to which interrupt vector location the CPU branches. This instruction globally disables maskable interrupts (sets the INTM bit to 1). The NMI instruction. This instruction forces a branch to interrupt vector location 24h, the same location used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI pin low or by executing an NMI instruction. This instruction globally disables maskable interrupts. The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. Anemulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction. The reset operation ensures an orderly startup sequence for the device. There are five possible causes of a reset, as shown in Figure 4. Three of these causes are internally generated; the other two causes, the RS and PORESET pins, are controlled externally. To Device Watchdog Timer Reset Reset Software-Generated Reset _L_s;~ Signal Illegal Address Reset > To Reset Out Reset (RS) Pin Active _ >i Power-On Reset (PORESET) Pin Active Figure 4. Reset Signals The five possible reset signals are generated as follows: Watchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an improper value is written to either the watchdog key register or the watchdog control register. (Note that when the device is powered on, the watchdog timer is automatically active.) Software-generated reset. This is implemented with the system control register (SYSCR). Clearing the RESETO bit (bit 14) or setting the RESET1 bit (bit 15) causes a system reset. Illegal address reset. The system and peripheral module control register frame address map contains unimplemented address locations in the ranges labeled illegal. Any access to an address located in the Illegal ranges generate an illegal-address reset. Reset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of as little as a few nanoseconds is usually effective; however, pulses of one SYSCLK cycle are necessary to ensure that the device recognizes the reset signal. Power-on reset pin active. To generate a power-on reset pulse on the PORESET pin, a low-level pulse of one SYSCLK cycle is necessary to ensure that the device recognizes the reset signal. Once a reset source is activated, the external RS pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the TMS320x240 device to reset external system components. Additionally, if a brown-out condition (Vgc < Vccmin for several microseconds causing PORESET to go low) occurs or the RS pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 19TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 reset (continued) The occurrence of a reset condition causes the TMS320x240 to terminate program execution and affects various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are affected by a reset are initialized to their reset state. In the case of a power-on reset, the PLL control registers are initialized to zero. The program needs to recognize power-on resets and configure the PLL for correct operation. After a reset, the program can check the power-on reset flag (PORST flag, SYSSR.15), the illegal address flag (ILLADR flag, SYSSR.12), the software reset flag (SWRST flag, SYSSR.10), and the watchdog reset flag (WDRST flag, SYSSR.9) to determine the source of the reset. A reset does not clear these flags. RS and PORESET must be held low until the clock signal is valid and Vcc is within the operating range. In addition, PORESET must be driven low when Vcc drops below the minimum operating voltage. hardware-generated interrupts All the hardware interrupt lines of the DSP core are given a priority rank from 1 to 10 (1 being highest). When more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets acknowledged first. The others are acknowledged in order after that. Of those ten lines, six are for maskable interrupt lines (INT1INT6) and one is for the nonmaskable interrupt (NMI) line. INT1INT6 and NMI have the priorities shown in Table 5. Table 5. Interrupt Priorities at the Level of the DSP Core PRIORITY AT THE INTERRUPT DSP CORE RESET TI RESERVEDT NMI INT1 INT2 INT3 INT4 INT5 INT6 Tl RESERVEDT 10 TTI Reserved means that the address space is reserved for Texas Instruments. OLOINTo!;/aTR/_ wo] rm] The inputs to these lines are controlled by the system module and the event manager as summarized in Table 6 and shown in Figure 5. Table 6. Interrupt Lines Controlled by the System Module and Event Manager PERIPHERAL INTERRUPT LINES INT1 System Module INT5 NMI INT6 INT2 Event Manager INT3 INT4 20 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 hardware-generated interrupts (continued) DSP Core Address Lines 51 IACK INT6 INT5 INT4 INT3 INT2 INT1 NMI Aa bob h A 5 Y Y NC NC NC | | Address IACK INT6 INT5 INT4 INT3 INT2 INT1 NMI INTC INTB INTA Lines 5-1 System Module Event Manager Figure 5. DSP Interrupt Structure At the level of the system module and the event manager, each of the maskable interrupt lines (INT1INT6) is connected to multiple maskable interrupt sources. Sources connected to interrupt line INT1 are called Level 4 interrupts; sources connected to interrupt line INT2 are called Level 2 interrupts; and so on. For each interrupt line, the multiple sources also have a set priority ranking. The source with the highest priority has its interrupt request responded to by the DSP core first. Figure 6 shows the sources and priority ranking for the interrupts controlled by the system module. For each interrupt chain, the interrupt source of highest priority is at the top. Priority decreases from the top of the chain to the bottom. Figure 7 shows the interrupt sources and priority ranking for the event manager interrupts. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 21TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 hardware-generated interrupts (continued) IACK = interrupt acknowledge IRQ = interrupt request Figure 6. System-Module Interrupt Structure To DSP INT6 To DSP INTS NC NC NC To DSP INT1 To DSP NMI INT6 INTS INT4 INT3 INT2 INT1 NMI System Module IRQ6 IACK6 IRQS IACKS5 IRQ4 IACK4 = IRQ3_sIACK3. IRQ2 IACK2 IACK1 |IACK_NMI v v | | | | | | Vv v NC NC NC NC NC NC SPI System-Module System-Modul Dual ADC External Interrupt ystem- Module I Interrupt External Interrupt nterrupt (low priority) XINT! NMI Priony (high priority) v v Vv System-Module scl System-Module External Interrupt Receiver External Interrupt XINT1 Interrupt XINT2 (low priority) (low priority) (high priority) v v Vv System-Module scl System-Module External Interrupt Transmitter External Interrupt XINT2 Interrupt XINT3 (low priority) (low priority) (high priority) y Vv System-Module External Interrupt Watchdog XINT3 Timer (low priority) Interrupt Vv SPI Interrupt (high priority) Vv scl Receiver Interrupt (high priority) Vv scl Transmitter Interrupt (high priority) Legend: NC = No connection 22 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443hardware-generated interrupts (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 To DSP INT4 To DSP INT3 To DSP INT2 INTC INTB INTA Event Manager IRQC IACKC IRQB IACKB IRQA IACKA v v v Capture 1 Timer 2 Power-Drive interru Vt Period Protection P Interrupt Interrupt v v vy Ti 2 Capture 2 Cc ompare Compare1 Interrupt Interrupt Interrupt Pp v v v Capture 3 Timer 2 Compare 2 Underflow Interrupt nterrupt Interrupt v v v Timer 2 Capture 4 Overtlow Compare 3 Interrupt Interrupt Interrupt P' v v Timer 3 Simple- Period Compare 1 Interrupt Interrupt v vy Legend: i i 9 IACK = Interrupt acknowledge Timer 3 Simple- IRQ = Interrupt request Compare Compare 2 Interrupt Interrupt v v Timer 3 Simple- Underflow Compare 3 Interrupt Interrupt v Vv Timer 3 Timer 1 Overflow Period Interrupt Interrupt v Timer 1 Compare Interrupt v Timer 1 Underflow Interrupt v Timer 1 Overflow Interrupt Figure 7. Event-Manager Interrupt Structure Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 23TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 hardware-generated interrupts (continued) Each of the interrupt sources has its own control register with a flag bit and an enable bit. When an interrupt request is received, the flag bit in the corresponding control register is set. If the enable bit is also set, a signal is sent to arbitration logic, which can simultaneously receive similar signals from one or more of the other control registers. The arbitration logic compares the priority level of competing interrupt requests, and it passes the interrupt of highest priority to the CPU. The corresponding flag is set in the interrupt flag register (IFR), indicating that the interrupt is pending. The CPU then must decide whether to acknowledge the request. Maskable hardware interrupts are acknowledged only after certain conditions are met: @ Priority is highest. When more than one hardware interrupt is requested at the same time, the x240 services them according to the set priority ranking. @ = INTM bit is 0. The interrupt mode (INTM) bit, bit 9 of status register STO, enables or disables all maskable interrupts: When INTM = 0, all unmasked interrupts are enabled. When INTM = 1, all unmasked interrupts are disabled. INTM is set to 1 automatically when the CPU acknowledges an interrupt (except when initiated by the TRAP instruction) and at reset. It can be set and cleared by software. @ IMRmaskbitis1. Eachofthe maskable interruptlines has a mask bit in the interrupt mask register (IMR). To unmask an interrupt line, set its IMR bit to 1. When the CPU acknowledges a maskable hardware interrupt, it jams the instruction bus with the INTR instruction. This instruction forces the PC to the appropriate address from which the CPU fetches the software vector. This vector leads to an interrupt service routine. Usually, the interrupt service routine reads the peripheral-vector-address offset from the peripheral-vector- address register (see Table 7) to branch to code that is meant for the specific interrupt source that initiated the interrupt request. The x240 includes a phantom-interrupt vector offset (0000h), which is a system interrupt integrity feature that allows a controlled exit from an improper interrupt sequence. If the CPU acknowledges a request from a peripheral when, in fact, no peripheral has requested an interrupt, the phantom-interrupt vector is read from the interrupt-vector register. Table 7 summarizes the interrupt sources, overall priority, vector address/offset, source, and function of each interrupt available on the TMS320x240. 24 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443hardware-generated interrupts (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 7. x240 Interrupt Locations and Priorities DSP-CORE PERIPHERAL PERIPHERAL *x240 INTERRUPT | OVERALL | INTERRUPT, VECTOR VECTOR MASKABLE? SOURCE FUNCTION NAME PRIORITY AND ADDRESS ADDRESS * | PERIPHERAL INTERRUPT ADDRESS OFFSET MODULE 1 RS External, system reset RS Highest 0000h N/A N Core, SD | (RESET) INT7 RESERVED 2 N/A N/A N DSP Core Emulator trap 0026h NMI 3 NMI N/A 0002h N C SD Ext | int t 0024h ore, xternal user interrup XINTI 4 0001h High-priority external user XINT2 5 001th Y SD intorruote XINT3 6 001Fh P SPIINT 7 INT1 0005h Y SPI High-priority SPI interrupt 0002h SYSIVR SCI receiver interrupt RXINT 8 (701Eh) 0006h Y Sc (high priority) P (System) ge Y TXINT 9 0007h Y Sci SCI transmitter interrupt (high priority) WDTINT 10 0010h Y WDT Watchdog timer interrupt PDPINT 11 0020h Y External Power-drive protection Int. CMP1INT 12 002i1h Y EV.CMP1 Full Compare 1 interrupt CMP2INT 13 0022h Y EV.CMP2 Full Compare 2 interrupt CMP3INT 14 0023h Y EV.CMP3 Full Compare 3 interrupt SCMP1INT 15 INT2 0024h Y EV.CMP4 Simple ompare ' 0004h P EVIVRA Simple compare 2 SCMP2INT 16 (Event (7432h) 0025h Y EV.CMP5 interrupt Manager Sim ple compare 3 SCMP3INT 17 Group A) 0026h Y EV.CMP6 | interrupt TPINT1 18 0027h Y EV.GPT1 Timer1 -period interrupt TCINT1 19 0028h Y EV.GPT1 Timer1-compare interrupt TUFINT1 20 0029h Y EV.GPT1 Timer1 -underflow interrupt TOFINT 1 21 002Ah Y EV.GPT1 Timer1-overflow interrupt TPINT2 22 002Bh Y EV.GPT2 Timer2-period interrupt TCINT2 23 002Ch Y EV.GPT2 Timer2-compare interrupt TUFINT2 24 oboen 002Dh Y EV.GPT2 Timer2-underflow interrupt TOFINT2 25 EVIVRB 002Eh Y EV.GPT2 Timer2-overflow interrupt TPINT3 26 (Event (7433h) 002Fh Y EV.GPT3 | Timer3-period interrupt TCINTS 27 Grown) 0030h Y EV.GPT3 Timer3-compare interrupt TUFINT3 28 003i1h Y EV.GPT3 Timer3-underflow interrupt TOFINT3 29 0032h Y EV.GPT3 Timer3-overflow interrupt CAPINT1 30 INT4 0033h Y EV.CAP 1 Capture 1 interrupt CAPINT2 31 0008h EVIVRC 0034h Y EV.CAP2 Capture 2 interrupt CAPINT3 32 (Event (7434h) 0035h Y EV.CAP3 _| Capture 3 interrupt Manager CAPINT4 33 Group C) 0036h Y EV.CAP4 Capture 4 interrupt Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 25TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 hardware-generated interrupts (continued) Table 7. x240 Interrupt Locations and Priorities (Continued) DSP-CORE PERIPHERAL PERIPHERAL *x240 INTERRUPT | OVERALL | INTERRUPT, VECTOR VECTOR MASKABLE? SOURCE FUNCTION NAME PRIORITY AND ADDRESS ADDRESS * | PERIPHERAL INTERRUPT ADDRESS OFFSET MODULE SPIINT 34 INT5 0005h Y SPI Low-priority SPI interrupt SYSIVR RXINT 35 (701Eh) 0006h Y SCI SCI receiver interrupt O00Ah (low priority) System itter i TXINT 36 (Sy ) 0007h Y Sci Scl transmitter interrupt (low priority) ADCINT 37 INT6 SYSIVR 0004h Y ADC Analog-to-digital interrupt XINT1 38 0001h Y _ XINT2 39 System) (701Eh) 001th Y external vow-prenly external XINT3 40 001Fh Y P P RESERVED 41 OOOEh N/A Y DSP Core Used for analysis TRAP N/A 0022h N/A N/A TRAP instruction vector external interrupts The x240 has five external interrupts. These interrupts include: XINT1. Type A interrupt. The XINT1 control register (at 7070h) provides control and status for this interrupt. XINT1 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose input pin. XINT1 can also be programmed to trigger an interrupt on either the rising or the falling edge. NMI. Type A interrupt. The NMI control register (at 7072h) provides control and status for this interrupt. NMI is anonmaskable external interrupt or a general-purpose input pin. NMI can also be programmed to trigger an interrupt on either the rising or the falling edge. XINT2. Type C interrupt. The XINT2 control register (at 7078h) provides control and status for this interrupt. XINT2 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a general-purpose I/O pin. XINT2 can also be programmed to trigger an interrupt on either the rising or the falling edge. XINTS3. Type C interrupt. The XINT3 control register (at 707Ah) provides control and status for this interrupt. XINT3 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose I/O pin. XINT3 can also be programmed to trigger an interrupt on either the rising or the falling edge. PDPINT. This interrupt is provided for safe operation of the power converter and motor drive. This maskable interrupt can put the timers and PWM output pins in the high-impedance state and inform the CPU in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. PDPINT is a Level 2 interrupt. 26 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 external interrupts (continued) Table 8 is a summary of the external interrupt capability of the x240. Table 8. External Interrupt Types and Functions EXTERNAL CONTROL CONTROL INTERRUPT CAN DO DIGITAL INTERRUPT REGISTER REGISTER TYPE NMI? VO PIN MASKABLE? NAME ADDRESS , XINT1 XINTICR 7070h A N Input onl Yes npur only (Level 1 or 6) NMI NMICR 7072h A Yes Input only No Yes XINT2 XINT2CR 7078h C No VO (Level 1 or 6) Yes XINT3 XINT3CR 707Ah C No VO (Level 1 or 6) Yes PDPINT EVIMRA 742Ch N/A N/A N/A (Level 2) clock generation The TMS320x240 has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The only external component necessary for this module is an external fundamental crystal, or oscillator. The PLL-based clock module provides two basic modes of operation: oscillator mode and clock-in mode. oscillator mode This mode allows the use of a 4-, 6-, or 8-MHz external reference crystal to provide the time base to the device. The internal oscillator circuitry is initialized by software to select the desired CPUCLK frequency, which can be the input clock frequency, the input clock frequency divided by 2 (default), or a clock frequency determined by the PLL. Clock-in mode This mode allows the internal crystal oscillator circuitry to be bypassed. The device clocks are generated from an external clock source input on the XTAL1/CLKIN pin. The device can be configured by software to operate on the input clock frequency, the input clock frequency divided by 2, or a clock frequency determined by the PLL. The x240 runs on two clock frequencies: the CPU clock (CPUCLK) frequency, and the system clock (SYSCLK) frequency. The CPU, memories, external memory interface, and event manager run at the CPUCLK frequency. Allother peripherals run at the SYSCLK frequency. The CPUCLK runs at 2x or 4x the frequency of the SYSCLK; for example, for 2x, CPUCLK = 20 MHz and SYSCLK = 10 MHz. There is also a clock for the watchdog timer, WDCLK. This clock has a nominal frequency of 16384 Hz (214 Hz) when XTAL1/CLKIN is a power of two or a sum of two powers of two; for example, 4194304 Hz (222 Hz), 6291456 (222 + 221 Hz), or 8388608 Hz (223 Hz). The clock module includes three external pins: 1. XTAL1/CLKIN clock source/crystal input 2. XTAL2 output to crystal 3. OSCBYP oscillator bypass For the external pins, if OSCBYP = Vjy, then the oscillator is enabled and if OSCBYP < Vj,, then the oscillator is bypassed and the device is in clock-in mode. In clock-in mode, an external TTL clock must be applied to the XTAL1/CLKIN pin. The XTAL2 pin can be left unconnected. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 27TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 clock generation (continued) OSCBYP Div 2 PLL divide-by-2 bit (CKCRI1 3) Synchronizing | CPUCLK roosts tpn rr Clock Switch XTAL1/CLKIN ' ' L C} -e] Div 2 ' = ose ; MUX ; ! Phase |} I yco be! Detector | XTAL2 1 1 ! ' Clock Mode Bits ' (CKCRO.7-6) ! Feedback ! ' Divider Div 1,2,3,4,5, .-. PLL multiply ratio \ org ' (CKCR1.2-0) 1 PLL 1 Clock Frequency and PLL Multiply Bits (CKCR1.74) | 1-MHz Clock Prescaler ACLK Watchdog Clock Prescaler -- WDCLK Prescale Bit (CKCRO.0) | SYSCLK Prescaler Div 2 or 4 SYSCLK Figure 8. PLL Clock Module Block Diagram 28 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443low-power modes TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 The TMS320x240 has four low-power modes (idle 1, idle 2, PLL power down, and oscillator power down). The low-power modes reduce the operating power by reducing or stopping the activity of various modules (by stopping their clocks). The two PLLPM bits of the clock module control register, CKCRO, select which of the low-power modes the device enters when executing an IDLE instruction. Reset or an unmasked interrupt from any source causes the device to exit from idle 1 low-power mode. A real-time interrupt from the watchdog timer module causes the device to exit from all low-power modes except oscillator power down. This is a wake-up interrupt. When enabled, reset or any of the four external interrupts (NMI, XINT1, XINT2, or XINT3) causes the device to exit from any of the low-power modes (idle 1, idle 2, PLL power down, and oscillator power down). The external interrupts are all wake-up interrupts. The maskable external interrupts (XINT1, XINT2, and XINT3) must be enabled individually and globally to bring the device out of a low-power mode properly. It is, therefore, important to ensure that the desired low-power-mode exit path is enabled before entering a low-power mode. Figure 9 shows the wake-up sequence from a power down. Table 9 summarizes the low-power modes. "signal Wake-up Signal Watchdog Timer to CPU |}__________ > and Real-Time Interrupt Module ----C-C 7 1 ni | 1 xINTA | XINT2 ! | XINT3 | | External-Interrupt Logic | rc------- =| Reset | | Signal | - | Reset Logic | LL J System Module Figure 9. Waking Up the Device From Power Down Table 9. Low-Power Modes POWER Pea CPUCLK | SYSCLK WDCLK PLL osc EXIT TYPICAL MODE CKCRO[2:3] STATUS STATUS STATUS STATUS STATUS CONDITION POWER Run XX On On On On On - 80 mA Idle 1 00 Off On On On On Any interrupt | 50 mA or reset Wake-up Idle 2 01 Off Off On On On interrupt or 7mA reset Wake-up PLL Power 10 Off Off On Off On interrupt or 1mA Down reset Wake-up OSC Power 1 Off Off Off Off Off interrupt or 400 pA Down reset 45 7 EXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 29TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 functional block diagram of the TMS320x240 DSP CPU Program Bus Data Bus PAR MSTACK Stack 8x16 FLASH EEPROM/ ROM Program Control (PCTRL) A15-AO 16 D15-Do Data Bus Data Bus ARO(16) AR1(16) 1 ARP(3) AR3(16) 3 ARA(16) 1 TREGO(16) ARB(3) AR6(16) 1 Multiplier 32 PSCALE (-6, 0, 1, 4) 32 32 CALU(32) Memory Map Register 32 IMR (16) IFR (16) GREG (1 DARAM DARAM BO (256 x 16) B2 (32 x 16) 32 C]ACCH(16) | ACCL(16) Bt x1 16 NOTES: A. Symbol descriptions appear in Table 10. B. For clarity the data and program buses are shown as single buses although they include address and data bits. wy TEXAS INSTRUMENTS 30 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 10. Legend for the F240 Internal Hardware Functional Block Diagram SYMBOL NAME DESCRIPTION ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift and rotate capabilities Auxiliary Register | An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs ARAU : : : Arithmetic Unit and outputs a: . These 16-bit registers are used as pointers to anywhere within the data space address range. They are AUX Auxiliary Registers operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). ARO can also be used REGS 0-7 : as an index value for AR updates of more than one and as a compare value to AR. __ Bus Request BR is asserted during access of the external global data memory space. READY is asserted to the device BR : q when the global data memory is available for the bus transaction. BR can be used to extend the data memory Signal address space by up to 32K words. Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit Cc Carry resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator shifts and rotates. Central Arithmetic 32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations ina CALU : : single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and Logic Unit : provides status results to PCTRL. If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM (DARAM) block BO is mapped to data space; otherwise, BO is mapped to program space. Blocks Bi and B2 DARAM Dual Access RAM are mapped to data memory space only, at addresses 030003FF and 0060-007F, respectively. Blocks 0 and 1 contain 256 words, while Block 2 contains 32 words. DP Data Memory The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct memory Page Pointer address of 16 bits. DP can be modified by the LST and LDP instructions. Global Memory GREG Allocation GREG specifies the size of the global data memory space. Register IMR Interrupt Mask IMR individually masks or enables the seven interrupts. Register IER Interrupt Flag The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable Register interrupts. INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available. Input Data-Scaling | 16 to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit ISCALE : abi . : : : : : Shifter output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. aa. 16 x 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either MPY Multiplier . : . : . signed or unsigned 2s-complement arithmetic multiply. MSTACK Micro Stack MSTACK provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space. MUX Multiplexer Multiplexes buses to a common input NPAR Next Program NPAR holds the program address to be driven out on the PAB on the next cycle. Address Register Output 16 to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization OSCALE Data-Scaling management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the Data-Write Data Shifter Bus (DWEB). PAR Program Address _ | PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory Register operations scheduled for the current bus cycle. PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential PC Program Counter : data-transfer operations. Program : : oo. sa: . PCTRL Controller PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 31TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 10. Legend for the F240 Internal Hardware Functional Block Diagram (Continued) SYMBOL NAME DESCRIPTION PREG Product Register 32-bit register holds results of 16 x 16 multiply. 0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the Product-Scalin additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down PSCALE Shifter 9 the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the 32-bit product shifter and from either the CALU or the Data-Write Data Bus (DWEB), and requires no cycle overhead. STACK Stack STACK is a block of memory used for storing return addresses for subroutines and interrupt-service a routines, or for storing data. The C20x stack is 16-bit wide and eight-level deep. TREG Temporary 16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count Register for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction. vy TEXAS 32 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 *x240 DSP core CPU The TMS320x240 devices use an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures program and data for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers between program memory and data memory. This architecture permits coefficients that are stored in program memory to be read in RAM, thereby eliminating the need for a separate coefficient that are ROM. This, coupled with a four-deep pipeline, allows the x240 devices to execute most instructions in a single cycle. status and control registers Two status registers, STO and ST1, contain the status of various conditions and modes. These registers can be stored into data memory and loaded from data memory, thereby allowing the status of the machine to be saved and restored for subroutines. The load status register (LST) instruction is used to write to STO and ST1. The store status register (SST) instruction is used to read from STO and ST1 except for the INTM bit, which is not affected by the LST instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Figure 10 shows the organization of status registers STO and ST1, indicating all status bits contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 11 lists status register field definitions. 15 1312 11 10 0 69)668lhCOUFhCUBC<CHKSs<S~<< BU hl sto | ARP | ov |ovm | 1 | intm | DP | 15 13#12 11 10 9 68 ~hU7lhClUmmUC<C SKC HOB 0 sT1 | ARB |cnF | Tc |sxm| c | 1 | 4 | 4 | 1 [| xF | 4 | 1 | PM f Figure 10. Status and Control Register Organization Table 11. Status Register Field Definitions FIELD FUNCTION Auxiliary register pointer buffer. When the ARP is loaded into STO, the old ARP value is copied to the ARB except during an LST instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP. Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed. Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these cases, the ADD can only set and the SUB only reset the carry bit, but cannot affect it otherwise. The single bit shift and rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch on the status of C. C is set to 1 on a reset. On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1 instructions. RS sets the CNF to 0. Data memory page pointer. The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS and IACK also set INTM. INTM has no effect on the unmaskable RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when a maskable interrupt trap is taken. Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instructions clear OV. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 33TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 status and control registers (continued) Table 11. Status Register Field Definitions (Continued) FIELD FUNCTION Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When setto 1, the accumulator OVM is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset this bit, respectively. LST can also be used to modify the OVM. PM Product shift mode. If these two bits are 00, the multipliers 32-bit product is loaded into the ALU with no shift. If PM =01, the PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, PREG output is left-shifted by four bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces aright shift of six bits, sign-extended. Note that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the SPM and LST #1 instructions. PM is cleared by RS. SXM Sign-extension mode bit. SXM = 1 produces sign extension on data as itis passed into the accumulator through the scaling shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM and reset by the CLRC SXM instructions, and can be loaded by the LST #1. SXM is set to 1 by reset. TC Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT or BITT is a 1, if aa compare condition tested by CMPR exists between AR (ARP) and ARO, if the exclusive-OR function of the two MSBs of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return instructions can execute based on the condition of TC. XF XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF and reset by the CLRC XF instructions. XF is set to 1 by reset. central processing unit The TMS320x240 central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. This section describes the CPU components and their functions. The functional block diagram shows the components of the CPU. input scaling shifter The TMS320x240 provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program or data space to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations. The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros; the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit (sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to the systems performance. multiplier The TMS320x240 devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. Two registers are associated with the multiplier: @ 16-bit temporary register (TREG) that holds one of the operands for the multiplier 32-bit product register (PREG) that holds the product Four product shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 12. 34 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 multiplier (continued) Table 12. PSCALE Product Shift Modes PM SHIFT DESCRIPTION 00 No shift Product feed to CALU or data bus with no shift 01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product 10 Left 4 when using the multiply by a 13-bit constant 11 Right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus). A multiplication also can be performed with a 13-bit immediate operand when using the MPY instruction. Then a product is obtained every two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining of the TREG load operations with CALU operations using the previous product. The pipeline operations that run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC (LTS). Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient addresses are generated by program address generation (PAGEN) logic, while the data addresses are generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes. The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product high) and SPL (store product low). Note: the transfer of PREG to either the CALU or data bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then, is loaded using the LPH instruction. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 35TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 central arithmetic logic unit The TMS3820x240 central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier. The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator. The TMS320x240 devices support floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to /subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized that is, floating-point to fixed-point conversion. They are also useful in execution of an automatic gain control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG. The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of STO. When the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. The value of the accumulator at saturation is O7FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Logical operations cannot result in overflow.) The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally based on any meaningful combination of these status bits. For overflow management, these conditions include the OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory. The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It also is useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. 36 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 central arithmetic logic unit (continued) Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset. accumulator The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of O to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16-31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0-15). When the post-scaling shifter is used on the low word, the LSBs are zero-filled. The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The x240 provides a register file containing eight auxiliary registers (AROAR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designating ARO through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers also can be stored in data memory or used as inputs to the CALU. The auxiliary register file (AROAR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by +1 or by the contents of the ARO register can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel. internal memory The TMS320x240 devices are configured with the following memory modules: @ Dual-access random-access memory (DARAM) @ Flash EEPROM (F240) @ Mask ROM (C240) dual-access RAM (DARAM) There are 544 words x 16 bits of DARAM on the x240 device. The x240 DARAM allows writes to and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (BO), block 1 (B1), and block 2 (B2). Block 1 contains 256 words and block 2 contains 32 words, and both blocks are located only in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program memory space. The SETC CMF (configure BO as data memory) and CLRC CNF (configure BO as program memory) instructions allow dynamic configuration of the memory maps through software. When using block 0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. When using on-chip RAM, or high-speed external memory, the x240 runs at full soeed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle coupled with the parallel nature of the *x240 Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 37TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 dual-access RAM (DARAM) (continued) architecture enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line can be used to interface the 'x240 to slower, less expensive external memory. Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system costs. ROM (TMS320C240 only) The C240 device contains 16K words of mask-programmable ROM located in program memory space. Customers can arrange to have this ROM programmed with contents unique to any particular application. The ROM is enabled or disabled by the state of the MP/MC control input upon resetting the device. The ROM occupies the lowest block of the program memory when enabled. When disabled, these addresses are located in the devices external program memory space. flash EEPROM (TMS320F240 only) Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is a nonvolatile memory type; however, it has the advantage of in-target reprogrammability. The TMS320F 240 incorporates one 16K x 16-bit flash EEPROM module in program space. This type of memory expands the capabilities of the TMS320F 240 in the areas of prototyping, early field-testing, and single-chip applications. Unlike most discrete flash memory, the F240 flash does not require a dedicated state machine, because the algorithms for programming and erasing the flash are executed by the DSP core. This enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming, the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V power supply. An erased bit in the TMS320F 240 flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash requires a block-erase of the entire 16K module; however, any combination of bits can be programmed. The following four algorithms are required for flash operations: clear, erase, flash-write, and program. For an explanation of these algorithms and a complete description of the flash EEPROM, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282), which is available during the 2nd quarter of 1998. flash serial loader The on-chip flash is shipped with a serial bootloader code programmed at the following addresses: 0x0000-0x00FFh. All other flash addresses are in an erased state. The serial bootloader can be used to program the on-chip Flash memory with users code. During the Flash programming sequence, the on-chip data RAM is used to load and execute the clear, erase, and program algorithms. See the TMS320F240 Serial Bootloader application report (currently located at ftp://ftp.ti.com/pub/tms320bbs/c24xfiles/f240boot.pdf to understand on-chip flash programming using the serial bootloader code. Look for further C2000 information using the DSP link at www.ti.com. flash control mode register The flash control mode register is located at I/O address FFOFN. This register offers two options: register access mode and array access mode. Register access mode gives access to the four control registers in the memory space decoded for the flash module. These registers are used to control erasing, programming, and testing of the flash array. Register access mode is enabled by activating an OUT command with dummy data. The OUT xxxx, FFOFh instruction makes the flash registers accessible for reads and/or writes. After executing OUT xxxx, FFOFh, the flash control registers are accessed in the memory space decoded for the flash module and the flash array cannot be accessed. The four registers are repeated every four address locations within the flash modules decoded range. 38 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 flash control mode register (continued) After completing all the necessary reads and/or writes to the control registers, an IN xxxx, FFOFh instruction (with dummy data) is executed to place the flash array back in array access mode. After executing the IN xxxx, FFOFh instruction, the flash array is accessed in the decoded space and the flash registers are not available. Switching between the register access mode and the array access mode is done by issuing the IN and OUT instructions. The memory content in these instructions (denoted by xxxx) is not relevant. Refer to the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282) for a detailed description of the flash programming algorithms. peripherals The integrated peripherals of the TMS320x240 are described in the following subsections: External memory interface Event manager (EV) Dual analog-to-digital converter (ADC) Serial peripheral interface (SPI) Serial communications interface (SCI) @ Watchdog timer (WD) external memory interface The TMS320x240 can address up to 64K words x 16 bits of memory or registers in each of the program, data, and I/O spaces. On-chip memory, when enabled, removes some of this off-chip range. In data space, the high 32K words can be mapped dynamically as either local or global using the GREG register. A data-memory access mapped as global asserts BR low (with timing similar to the address bus). The CPU of the TMS320x240 schedules a program fetch, data read, and data write on the same machine cycle. This is because, from on-chip memory, the CPU can execute all three of these operations in the same cycle. However, the external interface multiplexes the internal buses to one address and one data bus. The external interface sequences these operations to complete the data write first, then the data read, and finally the program read. The x240 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along with the PS, DS, and IS space-select signals allow addressing of 64K 16-bit words in program and I/O space. Due to the on-chip peripherals, external data space is addressable to 32K 16-bit words. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processors external address and data buses in the same manner as memory-mapped devices. The x240 external parallel interface provides control signals to facilitate interfacing to the device. The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. Interface to memory and I/O devices of varying speeds is accomplished by using the READY input. When transactions are made with slower devices, the x240 processor waits until the other device completes its function and signals the processor by way of the READY input. Once a ready indication is provided from the external device, execution continues. On the x240 device, the READY input must be driven (active high) to complete reads or writes to internal data I/O-memory-mapped registers and all external addresses. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 39TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 external memory interface (continued) The bus request (BR) signal is used in conjunction with the other x240 interface signals to arbitrate external global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted at the beginning of the access. When an external global-memory device receives the bus request, it responds by asserting the ready signal after the global-memory access is arbitrated and the global access is completed. The TMS320x240 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts, writes take two cycles. This allows the x240 to buffer the transition of the data bus from input to output (or output to input) by a half cycle. In most systems, TMS320x240 ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes. Wait states can be generated when accessing slower external resources. The wait states operate on machine-cycle boundaries and are initiated either by using the ready signal or using the software wait-state generator. Ready can be used to generate any number of wait states. event-manager (EV) module The event-manager module includes general-purpose (GP) timers, full compare units, capture units, and quadrature-encoder pulse (QEP) circuits. Figure 11 shows the functions of the event manager. general-purpose (GP) timers There are three GP timers on the TMS320x240. The GP timer x (for x = 1, 2, 3) includes: A 16-bit timer up-, up/down-counter, TxCNT for reads or writes A 16-bit timer-compare register (double-buffered with shadow register), TxCMPR for reads or writes A 16-bit timer-period register (double-buffered with shadow register), TxPR for reads or writes A 16-bit timer-control register, TxCON for reads or writes Selectable internal or external input clocks A programmable prescalar for internal or external clock inputs Control and interrupt logic for four maskable interrupts: underflow, overflow, timer compare, and period interrupts A timer-compare output pin with configurable active-low and active-high states, as well as forced-low and forced-high states. A selectable direction (TMRDIR) input pin (to count up or down when directional up-/down-count mode is selected) The GP timers can be operated independently or synchronized with each other. A 32-bit GP timer also can be configured using GP timer 2 and 3. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are two single and three continuous modes of operation for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler is used for each GP timer. The state of each GP timer/compare output is configurable by the general-purpose timer-control register (GPTCON). GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 1 or 2 for the simple compares to generate additional compare or PWMs, GP timer 2 or 3 for the capture units and the quadrature-pulse counting operations. Double buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed. 40 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443DSP core Data bus ADDR bus RESET _INT2, 3, 4 16 16 t 3 16 rr EV control registers and control logic Internal clock 2 es |} ADC start TMRCLK TMRDIR TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 16 6 TIPWM/T1CMP f GP timer 1 compare Output l logic 16 16 E GP timer 1 | 16 16 16 PWM1/CMP1 , 16 SVPWM 3 Dead 3 Output . Fullcompare units __pe] state P band == lo re : machine units 9 PWMG6/CMP6 } > 16 ; 3 Output T2PWM/T2CMP | GP timer 2 compare logic > 16 7 1 GP timer 2 | 16 16 i 16 } mux | 16 PWM7/CMP7 > K 6 Simple compare units Output PWM8/CMPS > logic PWM9/CMP9 > 16 GP timer 3 compare /_ > Sone, T3PWM/T3CMP > 16 To Control logic oy GP timer 3 | 16 Dir Clock 16 QEP [mux circuit 16 2 CAP1/QEP1 2 CAP2/QEP2 16 =e Capture units 2 CAP3, 4 Figure 11. Event-Manager Block Diagram Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 41TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 full compare units There are three full compare units on TMS320x240. These compare units use GP timer1 as the timebase and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. programmable-deadband generator The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband value (from 0 to 102 us) canbe programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register. simple compares TMS320x240 is equipped with three simple compares that can be used to generate three additional independent compare or high-precision PWM waveforms. GP timer1 or 2 can be selected as the timebase for the three simple compares. The states of the outputs of the three simple compares are configurable as low-active, high-active, forced-low, or forced-high independently. Simple compare registers are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. The state of the simple-compare outputs is configurable and changeable as needed by way of the double-buffered SACTR register. compare/PWM waveform generation Up to 12 compare and/or PWM waveforms (outputs) can be generated simultaneously by TMS320x240: three independent pairs (six outputs) by the three full compare units with programmable deadbands, three independent compares or PWMs (three outputs) by the simple compares, and three independent compare and PWMs (three outputs) by the GP-timer compares. compare/PWMs characteristics Characteristics of the compare/PWMs are as follow: 16-bit, 50-ns resolutions Programmable deadband for the PWM output pairs, from 0 to 102 us Minimum deadband width of 50 ns Change of the PWM carrier frequency for PWM frequency wobbling as needed Change of the PWM pulse widths within and after each PWM period as needed External maskable power and drive-protection interrupts Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms @ Minimized CPU overhead using auto-reload of the compare and period registers capture unit The capture unit provides a logging function for different events or transitions. The values of the GP timer 2 counter and/or GP timer 3 counter are captured and stored in the two-level first-in first-out (FIFO) stacks when selected transitions are detected on capture input pins, CAPx for x = 1, 2, 3, or 4. The capture unit of the TMS320x240 consists of four capture circuits. 42 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 capture unit (continued) The capture unit includes the following features: One 16-bit capture-control register, CAPCON, for reads or writes One 16-bit capture-FIFO status register, CAPFIFO, with eight MSBs for read-only operations, and eight LSBs for write-only operations Optional selection of GP timer 2 and/or GP timer 3 through two 16-bit multiplexers (MUXs). One MUX selects a GP timer for capture circuits 3 and 4, and the other MUX selects a GP timer for capture circuits 1 and 2. Four 16 bit x 2 FIFO stack registers, one two-level FIFO stack register per capture circuit. The top register of each stack is a read-only register, FIFOx, where x = 1, 2, 3, or 4. Four possible Schmitt-triggered capture-input pins (CAPx, x = 1 to 4) with one input pin per capture unit The input pins CAP1 and CAP2 also can be used as inputs to the QEP circuit. User-specified edge-detection mode at the input pins Four maskable interrupts/flags, CAPINTx, where x = 1, 2, 3, or 4 quadrature-encoder pulse (QEP) circuit Two capture inputs (CAP1 and CAP2) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2 or 3 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse). analog-to-digital converter (ADC) module A simplified functional block diagram of the ADC module is shown in Figure 12. The ADC module consists of two 10-bit ADCs with two built-in sample-and-hold (S/H) circuits. A total of 16 analog input channels is available on the TMS320x240. Eight analog inputs are provided for each ADC unit by way of an 8-to-1 analog multiplexer. Minimum total conversion time for each ADC unit is 6.1 ws. Total accuracy for each converter is +1.5 LSB. Reference voltage for the ADC module needs to be supplied externally through the two reference pins, VREFHI and VreF_o. The digital result is expressed as: Digital result= 1023 x Input Voltage VREFHI VREFLO Functions of the ADC module include: Two input channels (one for each ADC unit) that can be sampled and converted simultaneously Each ADC unit can perform single or continuous S/H and conversion operations. Two 2-level-deep FIFO result registers for ADC units 1 and 2 ADC module (both A/D converters) can start operation by software instruction, external signal transition on a device pin, or by event-manager events on each of the GP timer/compare output and the capture 4 pins. The ADC control register is double-buffered (with shadow register) and can be written to at any time. A new conversion of ADC can start immediately or when the previous conversion process is completed according to the control register bits. At the end of each conversion, an interrupt flag is set and an interrupt is generated if it is unmasked/enabled. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 43TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 analog-to-digital converter (ADC) module (continued) Internal Bus ADCO/O Sample 0 _ > and- > > ; ADC1/10 | Hold (S/H) | > Control Register Circuit ADC2 > a 10-Bit ADC 3 8/1 AID ADC 4 +4 MUX Converter ADC5 >, 4) ADC6 > ++ ADC7 >4 v Sample- ADC8IO , > ang. > > Control Register ADCIIO >, 4] Hold (S/H) bo] Circuit ADC 10 >> 10-Bit ADC 12. > MUX Converter ADC 13 >, 2) ADC 14 >, ++ ADC 15 +4 a External (I/O) Start Pin Control Logic Internal (EV Module) Start Signal > Single/Continues/Event Operations Interrupts Sleep Mode VREF > VREF Supply Voltage Program mock Let Control Register VREFH| VREFLO VSSA VcCcA Figure 12. Analog-to-Digital Converter Module wy TEXAS INSTRUMENTS 44 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 serial peripheral interface (SPI) module The TMS320x240 devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed synchronous serial-I/O port that allows a Serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include the following: Four external pins: SPISOMI: SPI slave-output/master-input pin, or general-purpose bidirectional I/O pin SPISIMO: SPI slave-input/master-output pin, or general-purpose bidirectional I/O pin SPISTE: SPI slave-transmit-enable pin, or general-purpose bidirectional I/O pin SPICLK: SPI serial-clock pin, or general-purpose bidirectional I/O pin Two operational modes: master and slave Baud rate: 125 different programmable rates / 2.5 Mbps at 10-MHz SYSCLK Data word format: one to eight data bits Four clocking schemes controlled by clock polarity and clock-phase bits include: Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operations (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. Ten SPI module control registers: Located in control register frame beginning at address 7040h. NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect. Figure 13 is a block diagram of the SPI in slave mode. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 45TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 serial peripheral Interface (SPI) module (continued) SPICCR.6 }-C SPICTL.3 )} SPIBUF.7-0 INT ENA SPIBUF OVERRUN SPI Priority Buffer Register SPISTS.7 O_ SPIPAIG 0 Level 4 To CPU o SPICTL.4 INT 8 ot Level 6 SPI INT INT SPI INT FLAG ENA SPISTS.6 o External _ (spiro) Connections SPICTL.O M M o SPIDAT S SPIPC2.74 Data Register ) Ss swi SPISIMO > M SPIDAT.7-0 Am A 4 J Pe | oo | Ss SPIPC2.3-0 O+.S swe | SPISOMI >> TALK me SPISTE SPICTL.1 4 a A SPIPC15 |) FUNCTIONS SPIPC1.74 WS o_}<sriste_> | State Control | | MASTER/SLAVEt = SPICHAR ( SPICCR.2-0 ects SPICTL.2 j2}i}o| sw3 v CLOCK CLOCK SPI BIT RATE s POLARITY PHASE SPIPC1.3-0 T The diagram is shown in the slave mode. +The SPISTE pin is shown as being disabled, meaning that data cannot be transmitted in this mode. Note that SW1, SW2, and SW3 are closed in this configuration. Figure 13. Four-Pin Serial Peripheral Interface Module Block Diagramt 46 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 serial communications interface (SCI) module The TMS320x240 devices include a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate (baud) is programmable to over 65000 different soeeds through a 16-bit baud-select register. Features of the SCI module include: Two external pins SCITXD: SCI transmit-output pin or general-purpose bidirectional I/O pin SCIRXD: SCI receive-input pin or general-purpose bidirectional 1/O pin Baud rate programmable to 64K different rates Up to 625 Kbps at 10-MHz SYSCLK Data word format One start bit - Data word length programmable from one to eight bits Optional even/odd/no parity bit One or two stop bits Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: idle-line and address bit Half- or full-duplex operation Double-buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR (monitoring four interrupt conditions) Separate enable bits for transmitter and receiver interrupts (except BRKDT) NRZ (non return-to-zero) format Eleven SCI module control registers located in the control register frame beginning at address 7050h NOTE: All registers in this module are 8-bit registers that are interfaced to the 16-bit peripheral bus. When a register is accessed, the register data is in the lower byte (70), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect. Figure 14 shows the SCI module block diagram. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 47TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 serial communications interface (SCI) module (continued) SCI TX Interrupt SCITXBUF. 7-0 DXAWAKE TXRDY TXINTENA | tyiy7 Transmitter-Data Frame Format and Mode (seicTL 1.3) Buffer Register > SCICTL2.7 o 1 SCICTL2.0 External Connections PARITY EVEN/ODD ENABLE 8 SCICTL2.6 v (sciccr.s| SCICCR.5) WUT SCIPC2.7-4 vy TX EMPTY TXSHF TXENA SCITXD Register OO > SCITXD > SCICTL1.1 [ (seicri1.1) SCIHBAUD. 15-8 (ScieTL 1.1) SCI PRIORITY LEVEL Baud Rat 1 Register | Level 2 Int. ~ . MSb 0 isbyte) CLOCK ENA Level 1 Int. fe SYSCLK SCI TX _ ( SCILBAUD. 7-0 ) LO -~O___ PRIORITY Baud Rate ( SCICTL1.4 ) SCIPRL6 Register 1 (LSbyte) Level 2 Int. -O leer 2 SCI RX PRIORITY SCIPRIL5 v SCIPC2.3-0 RXSHF SCIRXD Register ~< SCIRXD > RXWAKE SCIRXST.1 oo <_] RXENA RX ERR INT ENA SCICTL1.6 SCICTL1.0 {a} SCI RX Interrupt oO RXRDY_ RX/BK INT ENA SCIRXST.6 | Receiver-Data Buffer RX ERROR Register [ RX ERROR [FE[OE|PE, oO v BRKDT SCIRXST.5 RXINT l Figure 14. Serial Communications Interface (SCI) Module Block Diagram wy TEXAS INSTRUMENTS 48 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 watchdog (WD) and real-time interrupt (RTI) module The TMS320C240 device includes a watchdog (WD) timer and a real-time interrupt (RTI) module. The WD function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. The RTI function provides interrupts at programmable intervals. See Figure 15 for a block diagram of the WD/RTI module. The WD/RTI module features include the following: @ WD Timer Seven different WD overflow rates ranging from 15.63 ms to 1 $ A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and generates a system reset if an incorrect value is written to the register A WD flag (WD FLAG) that indicates whether the WD timer initiated a system reset WD check bits that initiate a system reset if an incorrect value is written to the WD control register (WDCR) @ Automatic activation of the WD timer, once system reset is released Three WD control registers located in control register frame beginning at address 7020h. @ Real-time interrupt (RTI): Interrupt generation at a programmable frequency of 1 to 4096 interrupts per second Interrupt or polled operation Two RTI control registers located in control register frame beginning at address 7020h. NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect. Figure 15 shows the WD/RTI block diagram. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 49TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 watchdog (WD) and real-time interrupt (RTI) module (continued) RTICNTR.7-0O wane CLR me 8-Bit Real-Time Counter M6384 = /2048 /512 111 RTICR.6 CLR 10 a 101 TL RITVENA INT Request pS D ato o_ > q 100 (Level 1 Only) O11 RTICR.2-0 CLR . 21110 INT Acknowledge 7-Bit 010 RTIPS C | Free- 001 RTICR.7 )clear Running | /32 ATI Fla 16-kHz Counter | 16 ooo RTI FLAG g WDCLK a 7B Tl System /4 D Q RTICR.7 Read Reset | | CLR 72 > CLR RTIFLAG ATIFlag RTICR.7 Clear RTIFLAG ATI Flag QS OO WDCNTR.7-0 0 = WD FLAG WDCR.6 S-Bit Watchdog | __y,_ Reset Flag WDDIS Counter One-Cycle | 5/257 CLR b> Delay A WDKEY.7-0 svat Bad Key =e _m Watchdog 554+AA Reset Key [|] Detector [G00d Key WDCHK2-0 Request Register WDCR.5-3 Bad WDCR Key 3 System Reset Re 1 (Constant Value) t Writing to bits WDCR.53 with anything but the correct pattern (101) generates a system reset. Figure 15. WD/RTI Module Block Diagram 50 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 scan-based emulation TMS320x240 devices use scan-based emulation for code- and hardware-development support. Serial scan interface is provided by the test-access port. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. TMS320x240 instruction set The x240 microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. Source code for the C1x and C2x DSPs is upwardly compatible with the x2xx devices. For maximum throughput, the next instruction is prefetched while the current one is being executed. Because the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory. addressing modes The TMS320x240 instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register. In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, each page containing 128 words. Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (ARO-AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for ARO through AR7, respectively. There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by adding or subtracting the contents of ARO, single-indirect addressing with no increment or decrement, and bit-reversed addressing [used in Fast Fourier Transforms (FFTs)] with increment or decrement. All operations are performed onthe current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and ARP can be modified. In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need to be stored or used more than once during the course of program execution (for example, initialization values or constants). The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case, operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand address or immediate value. repeat feature The repeat function can be used with instructions (as defined in Table 14) such as multiply/accumulates (MAC and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW). These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle instructions. For example, the table-read instruction can take three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 51TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 repeat feature (continued) The repeat counter (RPTC) is loaded with the addressed data-memory location if direct or indirect addressing is used, and with an 8-bit immediate value if short-immediate addressing is used. The RPTC register is loaded by the RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC is cleared by reset. Once a repeat instruction (RPT) is decoded, all interrupts, including NMI (but excluding reset), are masked until the completion of the repeat loop. instruction set summary This section summarizes the operation codes (opcodes) of the instruction set for the x240 digital signal processors. This instruction set is a superset of the C1x and C2x instruction sets. The instructions are arranged according to function and are alphabetized by mnemonic within each category. The symbols in Table 13 are used in the instruction set summary table (Table 14). The Tl C2xx assembler accepts C2x instructions. The number of words that an instruction occupies in program memory is specified in column 3 of Table 14. Several instructions specify two values separated by a slash mark (/) for the number of words. In these cases, different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies one word when the operand is a short-immediate value or two words if the operand is a long-immediate value. The number of cycles that an instruction requires to execute is also in column 3 of Table 14. All instructions are assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The cycle timings are for single-instruction execution, not for repeat mode. 52 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 instruction set summary (continued) Table 13. TMS320x240 Opcode Symbols SYMBOL DESCRIPTION A Address ACC Accumulator ACCB Accumulator buffer ARx Auxiliary register value (O7) BITx 4-bit field that specifies which bit to test for the BIT instruction BMAR Block-move address register DBMR Dynamic bit-manipulation register I Addressing-mode bit I Immediate operand value INTM Interrupt-mode flag bit INTR# Interrupt vector number K Constant PREG Product register PROG Program memory RPTC Repeat counter SHF, SHFT 3/4-bit shift value TC Test-control bit Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO. TP Meaning TP 00 BlOlow 01 TC=1 10 TC=0 11 None of the above conditions TREGn Temporary register n (n = 0, 1, or 2) 4-bit field representing the following conditions: Zz: ACC =0 L: ACC <0 V: Overflow C: Carry ZLvC A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 47) indicates the state of the conditions designated by the mask bits as being tested. For example, to test for ACC 2 0, the Z and L fields are set while the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate testing of the condition ACC =0, and the L field is reset to indicate testing of the condition ACC 2 0. The conditions possible with these 8 bits are shown in the BCND and CC instructions. To determine if the conditions are met, the 4-LSB bit mask is ANDed with the conditions. If any bits are set, the conditions are met. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 53TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 instruction set summary (continued) Table 14. TMS320x240 Instruction Set Summary OPCODE x240 DESCRIPTION WORDS/ MNEMONIC CYCLES | MSB LSB ABS Absolute value of accumulator 1/1 1011 1110 0000 0000 Add to accumulator with shift 1/1 0010 SHFT IADD RESS ADD Add to high accumulator 1/1 0110 0001 IADD RESS Add to accumulator short immediate 1/1 1011 1000 KKKK KKKK Add to accumulator long immediate with shift 2/2 1011 1111 1001 SHFT ADDG Add to accumulator with carry 1/1 0110 0000 IADD RESS ADDS Add to low accumulator with sign extension suppressed 1/1 0110 0010 IADD RESS ADDT Add to accumulator with shift specified by T register 1/1 0110 0011 IADD RESS ADRK Add to auxiliary register short immediate 1/1 0111. 1000 KKKK KKKK AND with accumulator 1/1 0110 1110 IADD RESS . . . . . 1011 1111 1011. SHFT AND AND immediate with accumulator with shift 2/2 46-Bit Constant 1011 1110 1000 0001 AND immediate with accumulator with shift of 16 2/2 : 16-Bit Constant APAG Add P register to accumulator 1/1 1011 1110 0000 0100 a 0111. 1001 IADD RESS B Branch unconditionally 2/4 Branch Address BACC Branch to address specified by accumulator 1/4 1011 1110 0010 0000 a. . 0111 1011. IADD RESS BANZ Branch on auxiliary register not zero 2/4/2 Branch Address . . 1110 0001 0000 0000 Branch if TC bit +0 2/4/2 Branch Address . . 1110 0010 0000 0000 Branch if TC bit = 0 2/4/2 Branch Address 1110 0011 0001 0001 Branch on carry 2/4/2 Branch Address . 1110 0011 1000 1100 Branch if accumulator > 0 2/4/2 Branch Address . 1110 0011 0000 0100 Branch if accumulator > 0 2/4/2 Branch Address BCND 1110 0000 0000 0000 Branch on I/O status low 2/4/3 Branch Address : 1110 0011 1100 1100 Branch if accumulator < 0 2/4/2 Branch Address 1110 0011 0100 0100 Branch if accumulator < 0 2/4/2 Branch Address 1110 0011 0000 0001 Branch on no carry 2/4/2 Branch Address 1110 0011 0000 0010 Branch if no overflow 2/4/2 Branch Address ag TEXAS 54 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443instruction set summary (continued) Table 14. TMS320x240 Instruction Set Summary (Continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 , OPCODE x240 DESCRIPTION WORDS! MNEMONIC CYCLES | mMsB LSB 1110 0011 0000 1000 Branch if accumulator + 0 2/4/2 Branch Address 1110 0011 0010 0010 BCND Branch on overflow 2/4/2 Branch Address 1110 0011 1000 1000 Branch if accumulator = 0 2/4/2 Branch Address BIT Test bit 1/1 0100 BITx JIADD RESS BITT Test bit specified by TREG 1/1 0110 = 1111 IADD RESS 1010 1000 IADD RESS Block move from data memory to data memory source immediate 2/3 Branch Address BLDDt 1010 1001 IADD RESS Block move from data memory to data memory destination immediate 2/3 Branch Address 1010 0101 JIADD RESS BLPD Block move from program memory to data memory 2/3 Branch Address CALA Call subroutine indirect 1/4 1011 1110 = 0011 0000 0111. #1010 IADD RESS CALL Call subroutine 2/4 Routine Address . ; 1110 10TP ZLVC ZLVC cc Conditional call subroutine 2/4/2 Routine Address Configure block as data memory 1/1 1011 1110 0100 0100 Enable interrupt 1/1 1011 1110 0100 0000 Reset carry bit 1/1 1011 1110 0100 1110 CLRC Reset overflow mode 1/1 1011 1110 0100 0010 Reset sign-extension mode 1/1 1011 1110 0100 0110 Reset test/control flag 1/1 1011 1110 0100 1010 Reset external flag 1/1 1011 1110 0100 1100 CMPL Complement accumulator 1/1 1011 1110 0000 0001 CMPR Compare auxiliary register with auxiliary register ARO 1/1 1011 1111 0100 Oi1CM DMOV Data move in data memory 1/1 0111 0111 IADD RESS IDLE Idle until interrupt 1/1 1011 1110 0010 0010 1010 =1111 IADD RESS IN Input data from port 2/2 16BIT I/O PORT ADRS INTR Software-interrupt 1/4 1011 1110 O11K KKKK Load accumulator with shift 1/1 0001 SHFT IADD- RESS 1011 1111 1000 SHFT LACG Load accumulator long immediate with shift 2/2 16-Bit Constant Zero low accumulator and load high accumulator 1/1 0110 1010 IADD RESS T In x240 devices, the BLDD instruction does not work with memory-mapped registers IMR, IFR, and GREG. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 55TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 instruction set summary (continued) Table 14. TMS320x240 Instruction Set Summary (Continued) , OPCODE MNEMONIC DESCRIPTION CYCLES MSB LSB Load accumulator immediate short 1/1 1011 1001 KKKK KKKK Zero accumulator 1/1 1011 1001 0000 0000 LACE Zero low accumulator and load high accumulator 1/1 0110 1010 IADD RESS Zero low accumulator and load low accumulator with no sign extension 1/1 0110 1001 IADD RESS LACT Load accumulator with shift specified by T register 1/1 0110 1011 JIADD RESS Load auxiliary register 1/2 0000. =OARx JIADD- RESS LAR Load auxiliary register short immediate 1/2 1011. OARx KKKK KKKK Load auxiliary register long immediate 2/2 ton mm 0000 MARK 16-Bit Constant LDP Load data-memory page pointer 1/2 0000 )=61101 IADD RESS Load data-memory page pointer immediate 1/2 1011. 110P AGEP- OINT LPH Load high-P register 1/1 0111. 0101 %JIADD RESS LST Load status register STO 1/2 0000 )=61110 IADD RESS Load status register ST1 1/2 0000) =61111 \IADD RESS LT Load TREG 1/1 0111. 0011 JIADD RESS LTA Load TREG and accumulate previous product 1/1 0111. 0000 IADD RESS LTD Load TREG, accumulate previous product, and move data 1/1 0111. 0010 IADD RESS LTP Load TREG and store P register in accumulator 1/1 0111. 0001 JIADD RESS LTS Load TREG and subtract previous product 1/1 0111. 0100 IADD RESS MAC Multiply and accumulate 2/3 FOTO 0070 FADD RESS 16-Bit Constant MACD Multiply and accumulate with data move 2/3 Toro 0017 TADD RES 16-Bit Constant MAR Load auxiliary register pointer 1/1 1000 =1011 1000 1ARx Modify auxiliary register 1/1 1000 1011 JIADD RESS MPY Multiply (with TREG, store product in P register) 1/1 0101 0100 IADD RESS Multiply immediate 1/1 110C KKKK KKKK KKKK MPYA Multiply and accumulate previous product 1/1 0101 0000 IADD' RESS MPYS Multiply and subtract previous product 1/1 0101 0001 IADD RESS MPYU Multiply unsigned 1/1 0101 0101 JIADD RESS NEG Negate accumulator 1/1 1011 1110 0000 0010 NMI Nonmaskable interrupt 1/4 1011 1110 =0101 0010 NOP No operation 1/1 1000 =1011 0000 =: 0000 NORM Normalize contents of accumulator 1/1 1010 0000 JIADD RESS OR with accumulator 1/1 0110 1101 JIADD RESS ; ; ; ; ; 1011 1111 1100 SHFT OR OR immediate with accumulator with shift 2/2 16-Bit Constant OR immediate with accumulator with shift of 16 2/2 ton M10 1000 0010 16-Bit Constant OUT Output data to port 2/3 toair VO vont hoe PAC Load accumulator with P register 1/1 1011 1110 0000 0011 i wo TEXAS 56 POST INSTRUMENTS | 443instruction set summary (continued) Table 14. TMS320x240 Instruction Set Summary (Continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 , OPCODE MN EMONIC DESCRIPTION CYCLES MSB LSB POP Pop top of stack to low accumulator 1/1 1011 1110 = 0071 0010 POPD Pop top of stack to data memory 1/1 1000 1010 IADD RESS PSHD Push data-memory value onto stack 1/1 0111 0110 IADD RESS PUSH Push low accumulator onto stack 1/1 1011 1110 = 0071 1100 RET Return from subroutine 1/4 1110 1111 0000 = =6.0000 RETC Conditional return from subroutine 1/4/2 1110 =611TP ZLVC ZLVC ROL Rotate accumulator left 1/1 1011 1110 0000 #1100 ROR Rotate accumulator right V1 1011 1110 0000 8 1101 RPT Repeat instruction as specified by data-memory value 1/1 0000) )=6_ 1011 +|IADD RESS Repeat instruction as specified by immediate value 1/1 1011 1011 KKKK KKKK SACH Store high accumulator with shift V1 1001 1SHF IADD RESS SACL Store low accumulator with shift 1/1 1001 OSHF IADD RESS SAR Store auxiliary register V1 1000 OARx IADD RESS SBRK Subtract from auxiliary register short immediate V1 0111 1100 KKKK KKKK Set carry bit 1/1 1011 1110 0100 1111 Configure block as program memory V1 1011 1110 0100 0101 Disable interrupt 1/1 1011 1110 0100 0001 SETC Set overflow mode 1/1 1011 1110 0100 0011 Set test/control flag V1 1011 1110 80100 1011 Set external flag XF V1 1011 1110 07100 1101 Set sign-extension mode V1 1011 1110 0100 0111 SFL Shift accumulator left 1/1 1011 1110 0000 1001 SFR Shift accumulator right V1 1011 1110 0000 1010 SPAG Subtract P register from accumulator V1 1011 1110 0000 0101 SPH Store high-P register V1 1000 81101 IADD RESS SPL Store low-P register V1 1000 1100 IADD RESS SPM Set P register output shift mode V1 1011 1111. IADD RESS SQRA Square and accumulate 1/1 0101 o010 IADD RESS SQRS Square and subtract previous product from accumulator 1/1 0101 0011 JIADD RESS Store status register STO V1 1000 1110 IADD RESS SST Store status register ST1 V1 1000 =61111 IADD RESS ; , 1010 1110 JIADD RESS SPLK Store long immediate to data memory 2/2 16-Bit Constant Subtract from accumulator long immediate with shift 2/2 ron mn to10 SHFT 16-Bit Constant SUB Subtract from accumulator with shift 1/1 0011 SHFT IADD RESS Subtract from high accumulator V1 0110 0101 IADD RESS Subtract from accumulator short immediate 1/1 1011 1010 KKKK KKKK Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 57TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 instruction set summary (continued) Table 14. TMS320x240 Instruction Set Summary (Continued) , OPCODE x240 DESCRIPTION WORDS/ MNEMONIC CYCLES | msB LSB SUBB Subtract from accumulator with borrow 1/1 0110 0100 IADD RESS SUBC Conditional subtract 1/1 0000 1010 IADD RESS SUBS Subtract from low accumulator with sign extension suppressed 1/1 0110 0110 IADD RESS SUBT Subtract from accumulator with shift specified by TREG 1/1 0110 =0111 IADD RESS TBLR Table read 1/3 1010 0110 JIADD RESS TBLW Table write 1/3 1010 =O111 IADD RESS TRAP Software interrupt 1/4 1011 1110 0101 0001 Exclusive-OR with accumulator 1/1 0110 1100 IADD RESS 1011 1111 1101. SHFT Exclusive-OR immediate with accumulator with shift 2/2 XOR 16-Bit Constant 1011 1110 1000 0011 Exclusive-OR immediate with accumulator with shift of 16 2/2 16-Bit Constant ZALR Zero low accumulator and load high accumulator with rounding 1/1 0110 1000 IADD RESS development support Texas Instruments offers an extensive line of development tools for the x240 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of *x240-based applications: Software Development Tools: Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler Hardware Development Tools: Emulator XDS510 (supports x240 multiprocessor system debug) The TMS320 Family Development Support Reference Guide (literature number SPRU011) contains information about development-support products for all TMS320 family member devices, including documentation. Refer to this document for further information about TMS320 documentation or any other TMS320 support products from Texas Instruments. An additional document, the 7MS320 Third Party Support Reference Guide (literature number SPRU052), contains information about TMS320-related products from other companies in the industry. To receive copies of TMS320 literature, contact the Literature Response Center at 800/477-8924. See Table 15 and Table 16 for complete listings of development-support tools for the x240. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. wy TEXAS INSTRUMENTS 58 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443development support (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 15. Development Support Tools DEVELOPMENT TOOL | PLATFORM | PART NUMBER Software Compiler/Assembler/Linker SPARC TMDS3242555-08 Compiler/Assembler/Linker PC-DOS TMDS3242855-02 Assembler/Linker PC-DOS, OS/2 TMDS3242850-02 C2xx Simulator PC-DOS, WIN TMDX324x851-02 C2xx Simulator SPARG TMDX324x55 1-09 Digital Filter Design Package PC-DOS DFDP C2xx Debugger/Emulation Software PC-DOS, OS/2, WIN TMDX324012xx C2xx Debugger/Emulation Software SPARC TMDX324062xx Hardware XDS510 XL Emulator PC-DOS, OS/2 TMDS00510 XDS510 WS Emulator SPARG TMDS00510WS Table 16. TMS320x240-Specific Development Tools DEVELOPMENT TOOL | PLATFORM | PART NUMBER Hardware C24x EVM | PC | TMDX326P 124x device and development-support tool nomenclature To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final devices electrical specifications TMP Final silicon die that conforms to the devices electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development support product that has not completed TI's internal qualification testing TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: Developmental product is intended for internal evaluation purposes. SPARC is a trademark of SPARC International, Inc. PC-DOS and OS/2 are trademarks of International Business Machines Corp. WIN is a trademark of Microsoft Corp. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 59TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 device and development-support tool nomenclature (continued) TMS devices and TMDS development-support tools have been fully characterized, and the quality and reliability of the device have been fully demonstrated. Tls standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate is still undefined. Only qualified production devices are to be used. Tl device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PN, PQ, and PZ) and temperature range (for example, L). Figure 16 provides a legend for reading the complete device name for any TMS320x2xx family member. TMS 320 (B) C 240 PQ (L) PREFIX | TEMPERATURE RANGE (DEFAULT: 0C TO 70C) TMX = Experimental device L = 0C to 70C TMP = Prototype device A = 40C to 85C TMS = Qualified device S = 40C to 125C Q 40C to 125C, Q 100 Fault Grading PACKAGE TYPEt PN = 80-pin plastic TQFP renee oo Famil PQ = 132-pin plastic bumpered QFP = amily PZ = 100-pin plastic TQFP BOOTLOADER OPTION DEVICE *C2xx DSP 209 TECHNOLOGY W___ 203 240 C = CMOS oA E = CMOS EPROM 242 F = Flash EEPROM F2xx DSP LC = Low-voltage CMOS (3.3 V) 206 VC= Low-voltage CMOS (3 V) 240 241 t TQFP = Thin Quad Flat Package 243 Figure 16. TMS320 Device Nomenclature documentation support Extensive documentation supports all of the TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete users guides for all devices and development-support tools; and hardware and software applications. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletinboard service (BBS) provides access to a wealth of information pertaining to the TMS320 family, including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323. Updated information on the TMS3820 DSP controllers can be found on the worldwide web at: http:/Avww.ti.com/dsps. 60 wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t Supply voltage range, Vopt .......---- cee teen tet eee e nett eeae -0.3Vto7V Input voltage range 0... tenet ett eee e eee -0.3Vto7V Output voltage range ..... 2... teen tet e nent eae -0.3Vto7V Operating free-air temperature range, Ta: Lversion .............. 0.00 c cece eee eee 0C to 70C AVEISION 1.0... ce eee -40C to 85C S, QversionS .......... 0.0... cee ee eee -40C to125C Storage temperature range, Tgig ..-.- 6-6 ees 55C to 150C Tt Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. t All voltage values are with respect to Vgg. recommended operating conditions MIN NOM MAX UNIT Vpp Supply voltage 4.5 5 5.5 Vv Vss Supply ground 0 Vv XTAL1/CLKIN 3 Vpp + 0.3 VIH High-level input voltage PORESET, NMI, RS, and TRST 28 Vpp + 0.3 Vv All other inputs 2 Vpp + 0.3 VIL Low-level input voltage ave 08 o7 Vv All other inputs -0.3 0.8 RS -19 IOH High-level output current, VoH = 2.4 V See complete listing of pin names] -16 mA All other outputs 23 RS 8 loL Low-level output current, VoL = 0.6 V See complete listing of pin names] 75 mA All other outputs 14.5 L version 0 70 TA Operating free-air temperature A version -40 85 C S, Q versions -40 125 Trp Credo on operating temperature, L, A, S, Q versions _40 85 C Oya Thermal resistance, junction-to-ambient 40 C/W jJc Thermal resistance, junction-to-case 9.9 CAN MIN value for C240 only TIOPA[O:3], SCIRXD/IO, SCITXD/IO, XINT2/1O, XINT3/IO, ADCSOC/IOPCO, TMRDIR/IOPB6, TMRCLK/OPB7 EMUO, EMU1/OFF Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 61TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 output current variation with output voltage: SPICE simulation results Condition: Temperature : 150C Voltage :4.5V Table 17. Typical Output Source Current vs. Output Voltage High 2.4V 3.0 V 3.5V 4.0V RS -19mA -16 mA -12mA -6 mA See complete listing of pin namest -16mA -13.5mA -9.5mA -5.0mA All other inputs 23 mA -18.5mA -13 mA -6.5mA T IOPA[O:3], SCIRXD/IO, SCITXD/IO, XINT2/IO, XINT3/O, ADCSOC/IOPCO, TMRDIR/IOPB6, TMRCLK/IOPB7 EMUO, EMU 1/OFF Table 18. Typical Output Sink Current vs. Output Voltage Low 0.6V 0.4V 0.2V RS 8mA 6mA 3mA See complete listing of pin namest 7.5mA 5mA 2.5mA All other i 145mA 10 mA 5.0mA tT IOPA[O:3], SCIRXD/IO, SCITXDAO, XINT2/IO, XINT3/lIO, ADCSOC/IOPCO, TMRDIR/IOPB6, TMRCLK/IOPB7 EMUO, EMU1/OFF electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX] UNIT VOH High-level output voltage 5-V operation, lo = MAX 2.4 Vv VoL Low-level output voltage 5-V operation, lo, = MAX 0.6 Vv TRST pin with internal pulldown -10 500 I Input current (V| = Vgs or Vpp) ical mull TMS, TCK, and TDI, 500 10 uA All other input pins -10 10 loz Output current, high-impedance state (off-state) |Vo=VppordV -5 LA Supply current, operating mode 5-V operation, te(GO) = 50 ns 80 Supply current, Idle 1 low-power mode 5-V operation, te(GO) = 50 ns 50 mA IDD | Supply current, Idle 2 low-power mode 5-V operation, te(GQ) = 50 ns 7 Supply current, PLL power-down mode 5-V operation, te(GO) = 50 ns 1 Supply current, OSC power-down mode 5-V operation, te(GO) = 50 ns 400 A Cj Input capacitance 15 pF Co Output capacitance 15 pF IDpp Flash programming supply current 5-V operation, te(o) = 50 ns 10 mA wy TEXAS INSTRUMENTS 62 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION yv'oL Tester Pin Electronics Output Under Test 1 | | | | | VLOAD | | | | | | -J4 Where: loL = 2mA (all outputs) IOH = 300A (all outputs) VLOAD = 1.5V CT = 110-pF typical load-circuit capacitance Figure 17. Test Load Circuit signal transition levels The data in this section is shown for the 5-V version (C2xx). Note that some of the signals use different reference voltages, see the recommended operating conditions table. TTL-output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.7 V. Figure 18 shows the TTL-level outputs. Figure 18. TTL-Level Outputs TTL-compatible output transition times are specified as follows: @ Fora high-to-low transition, the level at which the output is said to be no longer high is below 80% of the total voltage range and lower, and the level at which the output is said to be low is 20% of the total voltage range and lower. Fora /ow-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage range and higher, and the level at which the output is said to be high is 80% of the total voltage range and higher. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 63TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION Figure 19 shows the TTL-level inputs. a _2.0V f# - 90% 10% 0.7V Figure 19. TTL-Level Inputs TTL-compatible input transition times are specified as follows: Fora high-to-low transitionon an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower, and the level at which the input is said to be low is 10% of the total voltage range and lower. Fora low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher, and the level at which the input is said to be high is 90% of the total voltage range and higher. wy TEXAS INSTRUMENTS 64 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A A[15:0] MS Memory strobe pins is, DS, or PS Cl XTAL1/CLKIN R READY co CLKOUT/IOPC1 RD Read cycle or W/R D D[15:0] RS RS or PORESET INT NMI, XINT1, XINT2/IO, and XINT3/1O Ww Write cycle or WE Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time Vv Valid f fall time x Unknown, changing, or dont care level h hold time Z High impedance r rise time su setup time t transition time Vv valid time w pulse duration (width) general notes on timing parameters All output signals from the TMS320x240 devices (including CLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this data sheet. | XTAL1/CLKIN XTAL2 | XTAL1/CLKIN XTAL2 In| See Note B LL | | | L External C1 C2 . NC (see Note A) TL Crystal LT (see Note A) Clock Signal - (toggling 0-5 V) NOTES: A. For the values of C1 and C2, see the crystal manufacturers specification. B. Use this configuration in conjunction with OSCBYP pin pulled low. C. Texas Instruments encourages customers to submit samples of the device to the resonator/crystal vendor for full characterization. Figure 20. Recommended Crystal/Clock Connection Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 65TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 CLOCK OPTIONS clock options PARAMETER CLKMD[1:0] Clock-in mode, divide-by-2 00 Clock-in mode, divide-by-1 01 PLL enabled, divide-by-2 before PLL lock 10 PLL enabled, divide-by-1 before PLL lock 11 timings with the PLL circuit disabled PARAMETER TEST CONDITIONS MIN MAX | UNIT fy Input clock frequency, divide-by-2 mode Ta = 40C to 125C ot 40] MHz fy Input clock frequency, divide-by-1 mode Ta = 40C to 125C ot 20 | MHz Tt This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tec] approaching infinity. The device is characterized at frequencies approaching 0 Hz. switching characteristics over recommended operating conditions [H = 0.5 te(co)] (see Note 1 and Figure 21) PARAMETER CLOCK MODE MIN TYP MAX | UNIT ; CLKIN divide by 2 2tc(Cl) tT te(GPU) Cycle time, CPUCLK CLKIN divide by 1 te(Cl) ns CPUCLK divide by 2 2 te(SYS) Cycle time, SYSCLK SUGGS ~ zt er tas ; CLKIN divide by 2 2tc(Cl) tT te(CO) Cycle time, CLKOUT CLKIN divide by 1 te(Cl) t| td(CIH-CO) Delay time, XTAL1/CLKIN high to CLKOUT high/low 3 18 32 ns t(CO) Fall time, CLKOUT 5 ns tr(CO) Rise time, CLKOUT 5 ns tw(COL) Pulse duration, CLKOUT low H-10 H-6 H-1 ns tw(COH) Pulse duration, CLKOUT high H+0 H+4 H+8 ns Tt This device utilizes a fully static design and, therefore, can operate with input clock cycle time tec) approaching infinity. The device is characterized at frequencies approaching 0 Hz. + SYSCLK is initialized to divide-by-4 mode by any device reset. NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset. timing requirements over recommended operating conditions (See Figure 21) CLOCK-IN MODE MIN MAX | UNIT Divide by 2 25 tT te(Cl) Cycle time, XTAL1/CLKIN Divide by 1 50 + ns tCl) Fall time, XTAL1/CLKIN 5 ns trl) Rise time, XTAL1/CLKIN 5 ns tw(CIL) Pulse duration, XTAL1/CLKIN low as a percentage of tc/c}) 45 55 % tw(CIH) Pulse duration, XTAL1/CLKIN high as a percentage of te(Cl) 45 55 % Tt This device utilizes a fully static design and, therefore, can operate with input clock cycle time tec) approaching infinity. The device is characterized at frequencies approaching 0 Hz. wy TEXAS INSTRUMENTS 66 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 CLOCK OPTIONS (CONTINUED) >| inch le teen > j > wClH) et two) | | > ie tc) XTAL1/CLKIN NY KY | +> le tco) l i texco) | | | | > * tCo) w(COH) J# ot ta(CIH-CO) | t+ ._ twcoL) CLKOUT/IOPC1 | | Figure 21. External Divide-by-Two Clock Timings external reference crystal with PLL-circuit-enabled clock option The internal oscillator is enabled by connecting OSCBYP to Vpp and connecting acrystal across XTAL1/CLKIN and XTAL2 pins as shown in Figure 20. The crystal should be in either fundamental or overtone operation and parallel resonant, with an effective series resistance of 30 Q and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned-LC circuit. timings with the PLL circuit enabled PARAMETER calapenats RENCE MIN TYP MAX] UNIT 4 MHz fx Input clock frequency 6 MHz 6 MHz 8 MHz Ci, C2 Load capacitance 10 pF Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 67TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 switching characteristics over recommended operating conditions [H = 0.5 te(co)] (see Figure 22) PARAMETER CLOCK MODE MIN TYP MAX UNIT before PLL lock, ot CLKIN divide by 2 (Cl) T te(CPU) Cycle time, CPUCLK before PLL lock, ' ns CLKIN divide by 1 e(Cl) after PLL lock 50 CPUCLK divide by 2 2tc(CPU) t 1 Cycle ti SYSCLK ns c(SYS) ycle time, CPUCLK divide by 4+ 4te(CPU) te(CO) Cycle time, CLKOUT 50 t ns t(CO) Fall time, CLKOUT 5 ns tr(CO) Rise time, CLKOUT 5 ns tw(COL) Pulse duration, CLKOUT low H-10 H-6 H-1 ns tw(COH) Pulse duration, CLKOUT high H+0 H+4 H+8 ns before PLL lock. . ; 2000t, t Transition time, PLL synchronized after | CLKIN divide by 2 (Cl) ns P PLL enabled before PLL lock, 10008 CLKIN divide by 1 e(Cl) Tt This device utilizes a fully static design and, therefore, can operate with input clock cycle time tec) approaching infinity. The device is characterized at frequencies approaching 0 Hz. + SYSCLK is initialized to divide-by-4 mode by any device reset. timing requirements over recommended operating conditions (see Note 1 and Figure 22) EXTERNAL REFERENCE CRYSTAL MIN MAX | UNIT 4 MHz 250 t te(Cl) Cycle time, XTAL1/CLKIN 6 MHz 167 ns 8 MHz 125 tKCl) Fall time, XTAL1/CLKIN 5 ns tr(Cl) Rise time, XTAL1/CLKIN 5 ns tw(CIL) Pulse duration, XTAL1/CLKIN low as a percentage of tec) 40 60 % tw(CIH) Pulse duration, XTAL1/CLKIN high as a percentage of te(Cl) 40 60 % Tt This device utilizes a fully static design and, therefore, can operate with input clock cycle time tec) approaching infinity. The device is characterized at frequencies approaching 0 Hz. NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset. I te(cl) >| etc) | (ClH) ! > tcl tren i tw(CIL) pf XTAL1/CLKIN SJ XV }>+- tw(CoH) et lee [* tecoy > s |. #1 twcoL) i; i ff co) | | | | Figure 22. CLKIN-to-CLKOUT Timings for PLL Oscillator Mode, Multiply-by-5 Option With 4-MHz Crystal wy TEXAS INSTRUMENTS 68 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 low-power mode timings switching characteristics over recommended operating conditions [H = 0.5 te(cq)] (see Figure 23, Figure 24, Figure 25, and Figure 26) PARAMETER LOW-POWER MODES MIN TYP MAX | UNIT t Delay time, CLKOUT switching to Idle 1 and Idle 2 15 X te(CO) ns d(WAKE-A) program execution resume (see Note 1) | PLL or OSC power down 15 X tec) Delay time, Idle instruction executed to | Idle 2, PLL power down, OSC 'd(IDLE-COH) CLKOUT high (see Note 1) power down 500 ns td(WAKE-LOCK) synctronized (eee Note 1) to PLL PLL or OSC power down 100 us td(IDLE-OSc) oacilator power Instruction executed to OSC power down 60 us NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset. CT td(WAKE-A) _ AO-A15 x xX XX xX XxX. T oF ra 6 WAKE INT - \ Jf Figure 23. IDLE1 Entry and Exit Timings r td(IDLE-COH) 4 Ao-A15 __X__X& 1 x XXX | CLKOUT/OPC1 LD. LVKLVLIVNIN LN NS WAS VI VNSI NA NS NS NI NSN | | WAKE INT \ ! + tqwakE-a) 1 Figure 24, IDLE2 Entry and Exit Timings Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 69TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 low-power mode timings (continued) k td(WAKE-A) | | ao-ais_X x x XXX f_ ta(IDLE-CoH) ____ td(WAKE-LOCK) CLKOUTHOPC1 L\I\IN\ININININT IV NS VSI MSI | | iG al ( WAKE INT \L/J- Figure 25. PLL Power-Down Entry and Exit Timings ns td(WAKE-A) l A0-A15 x x Kx XX OX x . td(IDLE-OSC) | * tg(WAKE-LOCK) _ td(IDLE-COH) 4 | ra td(WAKE-OSC) | HY | WAKE INT \ 4 / Figure 26. OSC Power-Down Entry and Exit Timings wy TEXAS INSTRUMENTS 70 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 MEMORY AND PERIPHERAL INTERFACE TIMINGS memory and parallel I/O interface read timings switching characteristics over recommended operating conditions for a memory read @ 5 V [H = 0.5te(co)] (see Figure 27) PARAMETER MIN MAX | UNIT ta(CO-A)RD Delay time, CLKOUT/IOPC1 low to address valid 17 ns td(CO-SL)RD Delay time, CLKOUT/IOPC1 low to STRB low 10 ns td(CO-SH)RD Delay time, CLKOUT/IOPC1 low to STRB high 6 ns td(CO-ACTL)RD _ Delay time, CLKOUT/IOPC1 low to PS, DS, IS, and BR low 10] ns td(CO-ACTH)RD__ Delay time, CLKOUT/IOPC1 low to PS, DS, IS, and BR high 10] ns timing requirements over recommended operating conditions for a memory read @5V[H= 0.5tc(coylt (see Figure 27) MIN MAX UNIT ; ; 0 wait state 2H - 32 ta(A) Access time, from address valid to read data 1 wait state 4H 32 ns tsu(D-COL)RD _ Setup time, data read before CLKOUT/IOPC1 low 15 ns th(COL-D)RD Hold time, data read after CLKOUT/IOPC1 low 2 ns T All timings with respect to CLKOUT/IOPC1 assume CLKSRC[1:0] bits are set to select CPUCLK for output. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 71TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 MEMORY AND PERIPHERAL INTERFACE TIMINGS (CONTINUED) memory and parallel I/O interface read timings (continued) CLKOUTAOPC1 f Nf Nf NS td(CO-ACTH)RD >- td(CO-ACTL)RD | | Ps, 08.15, IN | PF or BR | ! ae ta(CO-A)RD rt td(CO-A)RD no-at x x x wk ON LOE jt tsu(D-COL)RD k tga) ! | at) a th(COL-D)RD DO-D15 ++ ta(co-si)RD |}>+ ta(Co-SH)RD STRB \ READY Figure 27. Memory Interface Read Timings wy TEXAS INSTRUMENTS 72 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443memory and parallel I/O interface write timings TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 MEMORY AND PERIPHERAL INTERFACE TIMINGS (CONTINUED) switching characteristics over recommended operating conditions for a memory write @5V[H=0. 5tecoylt (see Figure 28) PARAMETER MIN MAX | UNIT ta(CO-A)W Delay time, CLKOUT/IOPC1 high to address valid 17 ns td(CO-D) Delay time, CLKOUT/IOPC1 low to data bus driven 15 ns th(WH-A) Hold time, address valid after WE high H no ns tw(WH) Pulse duration, WE high 2H- 11 ns tw(WL) Pulse duration, WE low 2H- 11 td(CO-WL) Delay time, CLKOUT/IOPC1 low to WE low ns ta(CO-WH) Delay time, CLKOUT/IOPC1 low to WE high 9 ns tsu(D-WH) Setup time, write data valid before WE high 2H-8 ns thz(WH-D) High-impedance time, WE high to data bus Hi-Z 0 5 ns ta(CO-SL)W Delay time, CLKOUT/IOPC1 low to STRB low 10 ns td(CO-SH)W Delay time, CLKOUT/IOPC1 low to STRB high 6] ns tg(CO-ACTLW__ Delay time, CLKOUT/IOPC1 high to PS, DS, IS, and BR low 10 ns 100- -ACTH)W__ Delay time, CLKOUT/IOPC1 high to PS, DS, iS, and BR high 10 ns ta(CO- RWL) Delay time, CLKOUT/IOPC1 high to RW low 10 ns ta(CO-RWH) Delay time, CLKOUT/IOPC1 high to RW high 10 ns TAI timings with respect to CLKOUT/IOPC1 assume CLKSRC[1:0] bits are set to select CPUCLK for output. + MIN value for 'C240 only wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 73TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 MEMORY AND PERIPHERAL INTERFACE TIMINGS (CONTINUED) memory and parallel I/O interface write timings (continued) CLKOUT/IOPC1 \_ INS NS NS NSA NS | | | | t(CO-ACTH)W Kt ta(CO-ACTL)W | ! ( | | Ps, DS, IS, or BR | | ta(co-ayw <> | }>-_th(WH-A) | | po-ats x x Y td(CO-WH) ~>| I / | | \ | | | ta(co-RWL) 14 R/W \ __wY WR / 1+ ta(co-WL) | k tw(wH) >I | | ta(co-p) >| * | | | tsu(D-WH) | >) the(WH-D) Do-D15 ______ | td(CO-SL)W Da td(CO-SH)W STRB ny Gey A ey READY Figure 28. Memory Interface Write Timings wy TEXAS INSTRUMENTS 74 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 I/O timing variation with load capacitance: SPICE simulation results Condition: Temperature :-40 to 150C Capacitance :5-125pF Voltage :5.0V 2.2V 0.8V Figure 29. Rise and Fall Time Diagram Table 19. Timing Variation With Load Capacitance: [Vcc = 5 V, Von = 2.2 V, Vor = 0.8 VI] - 40C 27C 150C RISE FALL RISE FALL RISE FALL 5 pF 2.5 ns 3.6 ns 3.1 ns 4.5ns 4.3 ns 6.2 ns 25 pF 3.1 ns 4.6ns 4.0 ns 5.7 ns 5.6 ns 7.8ns 50 pF 3.9 ns 5.9 ns 5.0 ns 7.3ns 7.2 ns 9.9ns 75 pF 4.7 ns 7.3ns 6.1 ns 8.9ns 8.8 ns 11.7 ns 100 pF 5.4 ns 8.9ns 7.2ns 10.6 ns 10.5 ns 13.8 ns 125 pF 6.2 ns 10.4 ns 8.3 ns 12.2 ns 12.1 ns 15.8 ns Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 75TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 READY timings timing requirements over recommended operating conditions [H = 0.5te(coylt (see Figure 30) MIN MAX UNIT tsu(R-CO) Setup time, READY low before CLKOUT/IOPC1 high et ns th(CO-R) Hold time, READY low after CLKOUT/IOPC1 high 0 ns tv(R)ARD Valid time, READY after address valid on read at ans ns tyv(R)AW Valid time, READY after address valid on write bass ns tT The READY timings are based on one software wait state. At full speed operation, the x240 does not allow for single READY-based wait states. + MIN value for G240 only MAX values for 'C240 only | | | | | | __ _ /N | 1 N | J PS, DS, or IS | | | | | | | A0-A15 x | | | | 1 I | | ! | | | | wR \ WE | | | STRB \ | r k tsu(R-co) | | | | | i th(CO-R) ty(R)ARD +49 | Figure 30. READY Timings wy TEXAS INSTRUMENTS 76 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 RS and PORESET timings switching characteristics over recommended operating conditions for a reset [H = 0.5t,(co)] (see Figure 31 and Figure 32) PARAMETER MIN MAX | UNIT tw(RSL1) Pulse duration, RS lowt 8tc(SYS) ns ta(RS) Delay time, RS low to program address at reset vector 4H ns td(EX) Delay time, RS high to reset vector executed 32H ns t The parameter tw(RSL1) refers to the time RS is an output. timing requirements over recommended operating conditions for a reset [H = 0.5te(co)] (see Figure 31 and Figure 32) MIN MAX | UNIT tw(RSL) Pulse duration, RS or PORESET lowt 5 7 + The parameter tw(RSL) refers to the time RS is an input. PORESETt / Ret / t PORESET is required to be driven low during power up to ensure all clock/PLL registers are reset to a known state. + RS is a bidirectional (open-drain output) pin and can be optionally pulled low through an open-drain or open-collector drive circuit, or through a 2.7-kQ resistor in series with a totem pole drive circuit. If RS is left undriven, then a 20-kQ pullup resistor should be used. Figure 31. Reset Timings Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 77TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 RS and PORESET timings (continued) | - tw(RSL) PORESET \ / }*___-. twrst1) t | > i. ia(RS) lt taeEx) I | A0-A15 x x o000h X sooth X T RSis driven low by any device reset, which includes asserting PORESET, RS, access to an illegal address, execution of asoftware reset, or a watchdog timer reset. Figure 32. Power-On Reset Timings wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 XF, BIO, and MP/MC timings switching characteristics over recommended operating conditions [H = 0.5t.(co)] (see Figure 33) PARAMETER MIN MAX | UNIT td(XF) Delay time, CLKOUT high to XF high/low 11 ns timing requirements over recommended operating conditions [H = 0.5t.(co)] (see Figure 33) MIN MAX | UNIT 2H+ 16 ns tw(BIOL) Pulse duration, BIO low tw(MPMCV) Pulse duration, MP/MC validt 2H+ 24 ns t This is the minimum time the MP/MG pin needs to be stable in order to be recognized by internal logic; however, for proper operation, the user must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip. CLKOUT/IOPC1 LN FV J VK IJ VK IJ KIX | | | ta(XF) Tt | XF x twimpmcv)t -_+ MP/MC x Valid x tw(BIOL) 4 . VL t This is the minimum time the MP/MG pin needs to be stable in order to be recognized by internal logic; however, for proper operation, the user must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip. Figure 33. XF, BIO, and MP/MC Timings Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 79TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 TIMING EVENT MANAGER INTERFACE PWM/CMP timings PWM refers to PWM1/CMP1, PWM2/CMP2, PWM3/CMP3, PWM4/CMP4, PWM5/CMP5, PWM6/CMP6, T1PWM/T1CMP, T2PWM/T2CMP, T3PWM/T3CMP, PWM7/CMP7, PWM8/CMP8, and PWM9/CMP9. switching characteristics over recommended operating conditions for PWM timing [H = 0.5tg(o)] (see Figure 34) PARAMETER MIN MAX | UNIT ta(PWM)CO Delay time, CLKOUT high to PWM output switching 12 ns timing requirements over recommended operating conditions for PWM timing [H = 0.5t.(co)] (see Figure 35 and Figure 36) MIN MAX | UNIT 4H + 12 tw(TMRDIR) Pulse duration, TMRDIR low/high aH 4 id ns tw(TMRCLKL) Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time 40 60 % tw(TMRCLKH) Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time 40 60 % te(TMRGLK) Cycle time, TARCLK 4 x (CPU) Tt MIN value for C240 only CLKOUT/IOPC1 TN f \K J YK J VK J vy | | ta(PWM)CO }> PWM x Figure 34. PWM and Compare Output Timings <> tw(TMRCLKL) _+| tw(TMRCLKH) '* te(TMRCLK) | P| Figure 35. External Timer Clock Input Timings tw(TMRDIR) | TMRDIR EY ee > Figure 36. External Timer Direction Input Timings wy TEXAS INSTRUMENTS 80 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 capture and QEP timings CAP refers to CAP1/QEP1/IOPC4, CAP2/QEP2/IOPC5, CAP3/IOPC6, and CAP4/IOPC7. timing requirements over recommended operating conditions for CAP [H = 0.5tc(co)] (see Figure 37) MIN MAX | UNIT 4H +12 tw(CAP) Pulse duration, CAP input low/high 4H a ist ns Tt MIN value for 'C240 only | , 1 twcaP) i CAP x x Figure 37. Capture and QEP Input Timings Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 81TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 interrupt timings PWM refers to PWM1/CMP1, PWM2/CMP2, PWM3/CMP3, PWM4/CMP4, PWM5/CMP5, PWM6/CMP6, T1PWM/T1CMP, T2PWM/T2CMP, T3PWM/T3CMP, PWM7/CMP7, PWM8/CMP8, and PWM9/CMP9. INT refers to NMI, XINT1, XINT2/IO, and XINT3/IO. PDP refers to PDPINT. switching characteristics over recommended operating conditions for interrupts [H = 0.5t(co)] (see Figure 39) PARAMETER MIN MAX | UNIT ta(PWM)PDP Delay time, PDPINT low to PWM to high-impedance state 0 15 ns timing requirements over recommended operating conditions for interrupts [H = 0.5te(co)] (see Figure 38 and Figure 39) MIN MAX | UNIT Pulse duration, INT input low/high SYS) + 12 ns Pulse duration, PDPINT input low 2H+ 18 ns time, INT to interrupt-vector fetch ns tw(INT) _ Figure 38. External Interrupt Timings k +- tw(PDP) PDPINT \ V ta(PWM)PDP em a, Figure 39. Power-Drive Protection Interrupt Timings wy TEXAS INSTRUMENTS 82 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443general-purpose input/output timings TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 GPO refers to the digital output function of shared pins IOPAO-3, IOPBO7, IOPCO-7, XINT2/IO, XINT3/1O. GPI refers to the digital input function of shared pins IOPAO-3, IOPBO-7, IOPCO-7, XINT2/1O, XINT3/IO. switching characteristics over recommended operating conditions for a GPI/O [H = 0.5tg(o)] (see Figure 40) PARAMETER MIN MAX UNIT XINT2/1O, XINT3/IO, IOPB6, 33 td(GPO)CO Delay time, CLKOUT low to GPO low/high IOPB7, and |OPCO ns All other GPOs 25 timing requirements over recommended operating conditions for a GPI/O [H = 0.5tc(co)] (see Figure 41) MIN MAX | UNIT tw(GPl) Pulse duration, GP! high/low tc(SYS) + 12 ns CLKOUT/IOPC1 NS NS NS NS | ta(GPO)CO GPO x Figure 40. General-Purpose Output Timings t tw(GPl) I cpl -_, | lf Figure 41. General-Purpose Input Timings wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 83TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 SERIAL COMMUNICATIONS INTERFACE (SCI) I/O TIMINGS timing characteristics for SCI (see Note 2 and Figure 42) (BRR + 1) (BRR + 1) PARAMETER IS EVEN AND BRR =0 IS ODD AND BRR +0 UNIT MIN MAX MIN MAX te(SCC) Cycle time, SCICLK 16t, 65536t, 24t, 65535, ns tv(TXD) Valid time, SCITXD data te(SCC)70 te(SCC) +70 te(SCC)70 te(SCC)+ 70 ns tv(RXD) Valid time, SCIRXD data 16t, 24te ns NOTE 2: tg = system clock cycle time = 1/SYSCLK = tc(SYS) i _ ty(TxD) | | <n Oe AAAAAAAABALA AS ty(RXD) id TKKK KKK KKK KN) SCIRXD KKK KKK RKY Data Valid PERS Figure 42. SCI Timings wy TEXAS INSTRUMENTS 84 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443DSP CONTROLLERS TMS320C240, TMS320F240 (QHOOD!dS) 4 ALIYW1Od YOOTO ey} Aq peljosjuc s| peouesejes jeUBIS Y1OIdS ey} Jo eBpe eayoe ey (SAS)91 = yIOSAS/| = ew a[DX9 yoo]a Walshs = A+ paleald S| (ET LOIdS) W4 ASWHd MOOD eu} puk Jes s! (27LOIdS) WG SAVIS/YALSVW SUL | SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 su 02-1'0- W(9dS)%9 oz-W(OdS)%yz'0 (, = Ayejod yoo}9) YBIYy W1DIdS Jee PIIeA BLEP |WOSIdS Swit PIeA gNINOS-HOdS)A, 02-1'0- W(9dS)%9 02 -W(OdS)*162'9 (0 = Ayejod yo0}9) MO| W1OIldS JeYe PIA BIEP |WIOSIdS Swit plleA gN(INOS-19dS)4y su (, = Ayejod yoo}9) YyBIy HTDIdS S0Jeq |WOSIdS ew dnjes g(HOdS-INOS)Ns 0 0 (0 = Ayejod yo0}9) MO| M1OIdS B0J8q |WOSIdS ew, dnjes gNO19dS-INOS)ns, su 02-19'0+ W(9dS)%49 02 -W(OdS)2469 (L= Aqejod yoojo) YBIYy W1DIdS Jee PEA BLEP OWISIdS Swit PIeA gN(OWIS-HOdS)Ay 0221g'0+ WIOdS)%4'9 02 -W(9dS)246'9 (Q= Ayejod yoao}9) MO| W1OIldS JeYe PIIEA BIEP OWISIdS Swit PlleA gN(OWNIS-19dS)4y su " uF Ore 0} (| = Ayejod ya0/9) mo| ynolus "eu feed gOWNIST10d8)P) OF orm Ore 0} (0 = Ayejod yoojo) yBiy ynolug oun Kee gMOWISHOds)Py Ago+WOdS)I-q = g71G'9+ WIDdS)%19 02 -WIddS)4'9 (, = Ayrejod yoo) yBiy W714 uoleunp easing g(HOdS) "Pigg + WOdSig9 o2-A1G 0 NOdS igo o2-W(9dS)yg-9 (0 = Aqyejod 90/9) Mo] 101dS UoHesNp asind g1SdS)%y %go-WIOdS)%9 oZ-Ig' 0-WIOdS)%i-9 oZ-Wi9dS)1'9 (| = Aqyejod y90)9) Mo] 1O01dS UoHesNp asind gD dS) *" Paigg- WOdSig9 02-91: 0-NOdS%g9 oz-W(OdS)%4g9 (0 = Aqyejod y90)9) YBIY 1O1dS UoHEsNp asind SaSaST su #21 $s $y YWIDdS awit efoh5 W(OdS)} XVIN NIW NIW LINN < 4ugldS GNV dao sl (L + HYgIdS) NSHM Z HO O = HHaldS YO NAG SI (L + HHaIdS) NSHM (ev eunbi4 9as) 1(0 = aseyd 490)9) susjowesed Hulu) jeus9a}xe BpOW Ja}SEW! [dS s9]qe] BUIMO]]OJ BY} UI PSIs!] SI UONeWOJUI Bull] epOW Ja}ISeW | gS SYALANVEVd ONIWIL AGOW YALSVIN IdS 85 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 vy TEXASTMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION Wo te(SPC)M a | | l tw(SPCH)M >| le tyspciym | SPICLK (clock polarity = 0) | | | | ! | t tw(SPCL)m > + twspcHym >} | | | | | SPICLK NN YY N Sf (clock polarity = 1) | > td(SPCH-SIMO)M | d(SPCL-SIMO)M | _ '(SPCH-SIMO)M | | | tw(SPCL-SIMO)M YVYYY YY x) Y XXX XY SPH RRR SEA) tsu(SOMI-SPCL)M lq __y| | tsu(SOMI-SPCH)M tv(SPCL-SOMI)M | | | tv(SPCH-SOMI)M on EX Ra WABAAAAAAABABABALR LZ aS SPISTET \ tT The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until the SPI communication stream is complete. Figure 43. SPI Master Mode External Timings (Clock Phase = 0) wy TEXAS INSTRUMENTS 86 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443DSP CONTROLLERS TMS320C240, TMS320F240 (9 YOOIdS) WG ALINVIOd 4DO19 ey} Aq pay|osjuod s| pesuelejes eUuBIs y1O1dS eu} Jo eBpe enyoe aul g (SAS)91 = WIOSAS/ | = SUI] a[2A9 yooja Walshs = A+ JS SI (ETLOIdS) WG ASVHd MOOT eu} puke Jes SI (ZL O1dS) Hq SAVIS/HALSVWN OUL | SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 su 02 -W(OdS)%46'9 oz-W(OdS)%yz'0 (1 = Ayrejod y00)9) MO] MTOldS JeYE PIA BlEP |WIOSIdS SWI PIA gINOS-19dS)Ay 02 -W(OdS)%46'9 02 -W(OdS)*162'9 (0 = Ayejod yo0}9) YBIYy W1DIdS Jee PIIeA BLEP |WOSIdS Swit PIeA gN(INOS-HOdS)4y su (, = Ayejod yoo}9) MO| M1OIdS B0J8q |WOSIdS ew, dnjes gNO19dS-INOS)ns, 0 0 (0 = Ayejod yo0}9) YyBIy HTDIdS S0Jeq |WOSIdS ew dnjes g(HOdS-INOS)ns su ol- W(9d8)246'9 O/- W(OdS)2j6'9 (L= Aqejod yoojo) MO| W1OIldS JeYe PIIEA BIEP OWISIdS Swit PlleA gN(OWNIS-19dS)4y o7 WiodS)y'9 02 -W(OdS)2469 (Q= Ayejod yoao}9) YBIYy W1DIdS Jee PEA BLEP OWISIdS Swit PIeA gN(OWIS-HOdS)Ay su ol- W(9d8)246'9 O/- W(OdS)2j6'9 (1 = Ayrejod y00)9) MO] M1OldS 240J8q PIBA BYep OWISIdS ew dnies gNO9dS-ONIS)ns, o7 WiodS)y'9 02 -W(OdS)2469 (0 = Ayejod yo0}9) YBIYy W1DIdS 0j2q PEA BYep OWISIdS ew dnyes g(HOdS-ONIS)NS, ay | 280+ NOdSIg'0 oz-g'0+NOdS)%50 | WOdS);9 oz-WOdS)ig'o eu role leeinp tern gN(HOdS), Aso + W(OdS)2169 0/-I o+ W(OdS)219 W(OdS)2169 02 -WIOdS)219 (o = Ayejod yoo9) Mo] Y7DIdS Uolvesnp asind gD dS) 3'9-W(OdS)216-q = A1G'9Q -W(OdS)246'g | WIOdS)91g-g ~= gy -W(Od S469 (| = Aquejod yaojo) mo] yD dS uoNeunp esing gW19dS)y ST ag WIOdS)%169 97 -21g-0-WIOdS)21g'9 | WiodS%-9 gy -WlOdS)4-9 eu woke leeinp tern gN(HOdS), su $Z1 $s $1871. pw W1D1dS Swi a9A5 W(OdS)} XVI NII XVI NII LINN < 4ugldS GNV dao sl (L + HYgIdS) NSHM Z HO O = HHaldS YO NAG SI (L + HHaIdS) NSHM (pp eunbi4 99s) 1(L = aseyd 490)9) susjowesed Hulu) jeusa}xe BpOW Ja}SEW! [dS 87 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 vy TEXASTMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION | \_ te(spc)M __+! | | | {4 tw(SPCH)M > tw(SPCL)M | vw (clock polarity = 0) | | | SPICLK | ! | I | | | | | + tw(SPCL)M >| ( twspcH)m > | | SPICLK (clock polarity = 1) tsu(SIMO-SPCH)M +q tsu(SIMO-SPCL)M | t : Pet tigre suo YVYYYVY YY XX) XXXXKXK KKK) ; SPISIMO A Master Out Data is Valid KKK KA _Data Valid tsu(SOMI-SPCH)M __| | tsu(SOMI-SPCL)M , | t - | <> wispcttsomnm SPISOM QOQQ LYK _ Must Be Valid PRYQQYYYY SPISTET \ t The SPISTE signal mustbe active before the SPI communication stream starts; the SPISTE signal must remain active until the SPI communication stream is complete. Figure 44. SPI Master Mode External Timings (Clock Phase = 1) wy TEXAS INSTRUMENTS 88 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 SPI SLAVE MODE TIMING PARAMETERS Slave mode timing information is listed in the following tables. SPI slave mode external timing parameters (clock phase = 0)t (see Figure 45) MIN MAX UNIT tce(SPC)S Cycle time, SPICLK Btct ns tw(SPCH)SS Pulse duration, SPICLK high (clock polarity = 0) O0.5te(SPC)S70 _ 0.5tce(SPC)S tw(SPcLs Pulse duration, SPICLK low (clock polarity = 1) O0.5te(SPC)S70 _ 0.5tce(SPC)S ns tw(SPcLs Pulse duration, SPICLK low (clock polarity = 0) O0.5te(SPC)S70 _ 0.5tce(SPC)S tw(SPCH)sS Pulse duration, SPICLK high (clock polarity = 1) O0.5te(SPC)S70 _ 0.5tce(SPC)S ns ta(SPCH-Soml)s8 Delay time, SPICLK high (clock polarity = 0) to SPISOMI valid 0.375tc(SPC)S70 ta(SPCL-somns8 Delay time, SPICLK low (clock polarity = 1) to SPISOMI valid 0.375tc(SPC)S70 ns tv(SPCL-SOMI)S8 Valid time, SPISOMI data valid after SPICLK low (clock polarity =0) 0.75tc(SPC)S tv(SPCH-SOMI)S$ Valid time, SPISOMI data valid after SPICLK high (clock polarity =1) 0.75tc(SPC)S ns tsu(SIMO-SPCL)s8 Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0 tsu(SIMO-SPGH)SS Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0 ns tv(SPCL-SIMO)S8 Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5te(SPG)S tv(SPCH-SIMO)S8 Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S ns t The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. +t, = system clock cycle time = 1/SYSCLK = tc(SYS) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 89TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION a te(SPC)S _____+] | | + twisPcH)s >| i twsPct)s >| | SPICLK | | (clock polarity = 0) | | | | | | K tw(SPCL)s > le tw(SPCH)S >| | SPICLK \ SON (clock polarity = 1) | + td(SPCH-SOMI)S | td(SPCL-SOMI)S ty(SPCL-SOMI)S | | tv(SPCH-SOMI)S SPISOM RRVRRLK,_SPISOMDatate Vals KAKA SMES Lg su v(SPCL-SIMO)S | | tv(SPCH-SIMO)S vue SRN Eee LBAAAAAAAAAARS ABABA SPISTET \ t The SPISTE signal must be active before the SP] communication stream starts; the SPISTE signal mustremain active until the SPI communication stream is complete. Figure 45. SPI Slave Mode External Timing (Clock Phase = 0) wy TEXAS INSTRUMENTS 90 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 SPI slave mode external timing parameters (clock phase = 1)t (see Figure 46) MIN MAX UNIT te(SPC)S Cycle time, SPICLK tot ns tw(SPCH)SS Pulse duration, SPICLK high (clock polarity = 0) 0.5tce(SPC)S-70 0.5tc/SPC)S ns tw(SPcLs Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S-70 _0.5te(SPC)S tw(SPcLs Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S-70 _0.5te(SPC)S ns tw(SPCH)SS Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S-70 _0.5te(SPC)S tsu(SOMI-SPGH)SS Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125te(SPC)S ns tsu(SOMI-SPCL)SS Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125te(SPC)S tv(SPCH-SOMI)s$ Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0.75tc(SPC)S tv(SPCL-somiys Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0.75tc(SPC)S ns tsu(SIMO-SPGH)SS Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0 tsu(SIMO-SPCL)SS Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0 ns tv(SPCH-SIMO)S8 Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5te(SPG)S tv(SPCL-SIMO)S8 Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S ns tT The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set. tt. = system clock cycle time = 1/SYSCLK = te(SYS) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 91TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION | | k___ tespcys | | | | | | Ke twspcHys } twsPcL)s | | SPICLK | (clock polarity = 0) | | | | | | | | | | yl | | t | i W(SPCL)S P + twspcH)s > | (clock polarity = 1) tsu(SOMI-SPCH)S | tsu(SOMI-SPCL)S ni >| tv(SPCH-SOMI)S | | tW(SPCL-SOMI)S sPisoml YOR SISOM Baa Vals KR _Da Vai +_> jsu(SIMO-SPCH)S su(SIMO-SPCL)S_ | , tv(SPCH-SIMO)S | | | tW(SPCL-SIMO)S oo SX XRD SPISTET \ t The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until the SPI communication stream is complete. Figure 46. SPI Slave Mode External Timing (Clock Phase = 1) wy TEXAS INSTRUMENTS 92 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 10-bit dual analog-to-digital converter (ADC) The 10-bit dual ADC has a separate power bus for its analog circuitry. These pins are referred to as Vcca and Vasa. The purpose is to enhance ADC performance by preventing digital switching noise of the logic circuitry that can be present on Vgs and Vcc from coupling into the ADC analog stage. All ADC specifications are given with respect to Vesa unless otherwise noted. aC cr\0) 0) (0) 9 en 10-bit (1024 values) Monotonic .... 0... nen en tenet nent e eet e eens Assured Output conversion mode ..................0008- 000h to 3FFh (000h for V| < Vgsa; SFFh for Vj = Veca) recommended operating conditions MIN NOM MAX UNIT VCCA Analog supply voltage 4.5 5 5.5 Vv VSSA Analog ground 0 Vv VREFHI Analog supply reference sourcet VREFLO VCCA Vv VREFLO Analog ground reference sourcet VSSA VREFHI Vv Val Analog input voltage, ADCINO-ADCIN15 VSSA VOCA Vv t VREFHI and VREFLO must be stable, within +1/2 LSB of the required resolution, during the entire conversion time. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 93TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 operating characteristics over recommended operating condition rangest PARAMETER DESCRIPTION MIN MAX | UNIT converting 5 Veca =5.5V - non-converting 2 ICCA Analog supply current mA Vv -V =55V PLL or OSC power 1 CCA= YREFHI = - down lref Input charge current, VREFH| or VREFLO VCCA = VCCD = VREFHI = 5.5 V. VREFLO =O V 5 mA i iti non-samplin Cai Analog input capacitance Typical capacitive load on ey pF analog input pin sampling Za Analog Input source Impedance Analog input source impedance for conversions to 9 kQ remain within specifications. EDNL Differential nonlinearity error vintence between the actual step width andthe ideal | _ 1 15] LSB Maximum deviation from the best straight line through EINL Integral nonlinearity error the ADC transfer characteristics, excluding the +15] LSB quantization error ta(PU) Delay time, power-up to ADC valid Time to stabilize analog stage after power-up 10 ys T Absolute resolution =4.89 mV. AtVREFH|=5VandVREFLO=O0V.thisisoneLSB. As VREFH| decreases, VREFLOincreases, orboth, the LSBsizes decrease. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. The ADC module allows complete freedom in the design of the sources for the analog inputs. The period of the sample time is independent of the source impedance. The sample-and-hold period occurs in the first half-period of the ADC clock after the ADCIMSTART bit or the ADCSOC bit of the ADC control register 1 (ADCTRL1, bits 13 and 0, respectively) is set to 1. The conversion then occurs during the next six ADC clock cycles. The digital result registers are updated on the next ADC clock cycle once the conversion is completed. ADC input pin circuit One of the most common A/D application errors is inappropriate source impedance. In practice, minimum source impedance should be used to limit the error as well as minimize the required sampling time; however, the source impedance must be smaller than Za). A typical ADC input pin circuit is shown in Figure 47. +__ Requiv R1 VIN WN > Val (to ADCINx input) R1 = 9 ka typical Figure 47. Typical ADC Input Pin Circuit wy TEXAS INSTRUMENTS 94 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443ADC timing requirements (see Figure 48) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 MIN MAX | UNIT te(AD) Cycle time, ADC prescaled clock 1 us tw(SHC) Pulse duration, total sample/hold and conversion time (see Note 3) 6.1 us tw(SH) Pulse duration, sample and hold time te(AD) us tsu(SH) Setup time, analog input stable before sample/hold start 0 ns th(SH) Hold time, analog input stable after sample/hold complete 0 ns tw(C) Pulse duration, total conversion time 4.5tc(AD) us td(SOC-SH) Delay time, start of conversiont to beginning of sample and hold 3tc(SYS) ns td(EOC-FIFO) Delay time, end of conversion to data loaded into result FIFO 3tc(SYS) ns t Start of conversion is signaled by the ADCIMSTART bit or the ADCSOC bit set in software, the external start signal active (ADCSOC), or internal EVSOC signal active. NOTE 3: The total sample/hold and conversion time is determined by the summation of tq(SOC-SH): tw(SH)> tw(C): aNd td(EOC-FIFO). > tc(AD) Bit Converted | 9 8 7 6 5 4 3 2 1 0 ADC Clock | Lt LJ Ly LJ | Analog Input 11 >! tsu(SH) th(SH) | - tw(SH) | | Sample/Hold | 4 twc) Convert | Internal Start | ] jt ta(SOC-SH) Start of Convert tw(SHC) aA XFR to FIFO td(EOC-FIFO) i Figure 48. Analog-to-Digital Timing Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 95TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 flash EEPROM switching characteristics over recommended operating conditions *320F240 PARAMETER UNIT MIN TYP MAX Program-erase endurance 10K Cycles Program pulses per wordt 1 10 150 | Pulses Erase pulses per arrayt 1 20 1000 | Pulses Flash-write pulses per arrayt 1 20 6000 | Pulses tT These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282). timing requirements over recommended operating conditions *320F240 UNIT MIN MAX td(BUSY) Delay time, after mode deselect to stabilizationt 10 us td(RD-VERIFY) Delay time, verify read mode select to stabilizationt 10 us tT These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282). programming operation *320F240 PARAMETER UNIT MIN NOM MAX tw(PGM) Pulse duration, programming algorithmt 95 100 105 us td(PGM-MODE) Delay time, program mode select to stabilizationt 10 us t These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282). erase operation *320F240 PARAMETER UNIT MIN NOM MAX tw(ERASE) Pulse duration, erase algorithmt 6.65 7 7.35 ms td(ERASE-MODE) Delay time, erase mode select to stabilizationt 10 us tT These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282). flash-write operation *320F240 PARAMETER UNIT MIN NOM MAX tw(FLW) Pulse duration, flash-write algorithmt+ 13.3 14 14.7 ms td(F LW-MODE) Delay time, flash-write mode select to stabilization t+ 10 us tT These parameters are used in the flash programming algorithms. For a detailed description of the algorithms, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282). + Refer to the recommended operating conditions section for the flash programming operating temperature range when programming flash. wy TEXAS INSTRUMENTS 96 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443register file compilation TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 20 is a collection of all the programmable registers of the TMS320x240 (provided for a quick reference). ADDR 00004h 00005h o00006h 07018h 07019h 0701Ah 0701Bh to 0701Dh 0701Eh 0701Fh 07020h 07021h 07022h 07023h 07024h 07025h 07026h 07027h 07028h 07029h 0702Ah 0702Bh 0702Ch Table 20. Register File Compilation BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT9 BIT8 BIT7 BIT6 BITS BIT 4 BIT 3 BIT 2 BIT 1 BITO DATA MEMORY SPACE CPU STATUS REGISTERS ARP ov OVM 1 INTM DP(8) pp) | oP) | DPI) DP(4) DP(3) DP(2) DP(1) DP(0) ARB CNF TC SXM Cc 1 1 | 1 | 1 XF 1 1 PM GLOBAL MEMORY AND CPU INTERRUPT REGISTERS INT6 MASK | INTSMASK | INT4MASK | INT3MASK | INT2MASK | INT1 MASK Global Data Memory Configuration Bits (7-0) INT6FLAG | INTSFLAG | INT4FLAG | INT3FLAG | INT2FLAG | INTI FLAG SYSTEM CONFIGURATION REGISTERS RESET1 RESETO CLKSRC1 | CLKSRCO Reserved PORST ILLADR SWRST WDRST HPO VCCAOR VECRD Reserved 0 0 0 0 0 0 0 0 D7 D D5 D4 D3 D2 D1 Do Reserved WD/RTI CONTROL REGISTERS Reserved D7 | D6 | Ds D4 | 3 | D2 } Dt | Do Reserved D7 | D6 | Ds D4 | 3 | D2 } Dt | Do Reserved D7 | 6 } DS D4 | 3 | b2 Zz, | bo Reserved RTIFLAG | RTIENA | | | RTIPS2 | RTIPS1 | RTIPSO Reserved WDFLAG | wobDIS | wDCHK2 | wDCHKi | wDcHKo | wopse | wopsi | wopPso PLL CLOCK CONTROL REGISTERS Reserved CLKMD(1) }| CLKMD() | PLLOCK(1) | PLLOCK(O) | PLLPM(1) | PLLPM(o) | ACLKENA | PLLPS Reserved REG STO SsT1 IMR GREG IFR SYSCR SYSSR SYSIVR RTICNTR WDCNTR WDKEY RTICR WDCR CKCRO wy TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 97TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 register file compilation (continued) Table 20. Register File Compilation (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT9 BIT8 REG BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT 1 BITO PLL CLOCK CONTROL REGISTERS (CONTINUED) 0702Dh | CKINF(3) CKINF(2) CKINF(1) CKINF(0) PLLDIV(2) PLLFB(2) PLLFB(1) PLLFB(0) CKCR1 0702Eh to Reserved 07031h A-to-D MODULE CONTROL REGISTERS SUSPEND- | SUSPEND- ADCIM- ADCCON- o7032h SOFT FREE START ADC1EN ADC2EN RUN ADCINTEN | ADCINTFLAG ADCTRL ADCEOC ADC2CHSEL ADC1CHSEL ADCSOC 07033h Reserved _ _ = _ ADCEVSOC_ | ADCEXTSOC = 07034h ADCTRL2 ADCFIFO1 ADCFIFO2 ADCPSCALE 07035h Reserved Dg D8 D7 D6 D5 D4 D3 D2 07036h ADCFIFO1 D1 DO 0 0 0 0 0 0 07037h Reserved Dg D8 D7 D6 D5 D4 D3 D2 07038h ADCFIFO2 D1 DO 0 0 0 0 0 0 07039h to Reserved 0703Fh SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS SPISW CLOCK SPI SPI SPI 07040h RESET POLARITY a a a CHAR2 CHAR CHARO SPICCR OVERRUN CLOCK MASTER/ SPI INT 07041h INT ENA PHASE SLAVE TALK ENA SPICTL RECEIVER SPI INT 07042h | OVERRUN FLAG SPISTS 07043h Reserved SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT 07044h RATE 6 RATE 5 RATE 4 RATE 3 RATE 2 RATE 1 RATE 0 SPIBRR 07045h Reserved 07046h ERCVD7 ERCVD6 ERCVD5 ERCVD4 ERCVD3 ERCVD2 ERCVD1 ERCVDO SPIEMU 07047h RCVD7 RCVD6 RCVD5 RCVD4 RCVD3 RCVD2 RCVD1 RCVDO SPIBUF 07048h Reserved 07049h SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDATO SPIDAT 0704Ah to Reserved 0704Ch 0704Dh SPISTE SPISTE SPISTE SPISTE SPICLK SPICLK SPICLK SPICLK SPIPC1 DATA IN DATA OUT FUNCTION DATA DIR DATA IN DATA OUT FUNCTION DATA DIR o7o4eh | SPISIMO SPISIMO SPISIMO SPISIMO SPISOMI SPISOMI SPISOMI SPISOMI SPIPC? DATA IN DATA OUT FUNCTION DATA DIR DATA IN DATA OUT FUNCTION DATA DIR SPI SPI 0704F h PRIORITY ESPEN SPIPRI we 98 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443register file compilation (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 20. Register File Compilation (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT9 BIT8 REG BIT7 BIT6 BIT5 BIT 4 BIT3 BIT2 BIT 1 BITO SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS STOP EVEN/ODD PARITY ADDR/IDLE SCcl SCcl SCcl 07050h BITS PARITY ENABLE SCIENA MODE CHAR2 CHAR1 CHARO SCICCR 07051h _ a a SW RESET | CLOCK ENA TXWAKE SLEEP TXENA RXENA SCICTL1 BAUD15 07052h (MSB) BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 SCIHBAUD BAUDO 07053h BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 (LSB) SCILBAUD RX/BK TX 07054h TXRDY TX EMPTY _ _ _ _ INT ENA INT ENA SCICTL2 07055h | RX ERROR RXRDY BRKDT FE OE PE RXWAKE _ SCIRXST 07056h ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDTO SCIRXEMU 07057h RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDTO SCIRXBUF 07058h Reserved 07059h TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDTO SCITXBUF 0705Ah to Reserved 0705Dh 0705Eh SCITXD SCITXD SCITXD SCITXD SCIRXD SCIRXD SCIRXD SCIRXD Scipce DATA IN DATA OUT FUNCTION DATA DIR DATA IN DATA OUT FUNCTION DATA DIR SCITX SCIRX SCcl O705Fh _ PRIORITY | PRIORITY ESPEN _ _ _ _ SCIPRI 07060h to Reserved 0706Fh EXTERNAL INTERRUPT CONTROL REGISTERS XINT1 _ _ _ _ _ _ _ FLAG 07070h XINT1ICR _ XINT1 0 _ _ XINT1 XINT1 XINT1 PIN DATA POLARITY PRIORITY ENA 07071h Reserved NMI _ _ _ _ _ _ _ FLAG 07072h NMIGR _ NMI 1 _ _ NMI _ _ PIN DATA POLARITY 07073h to Reserved 07077h XINT2 _ _ _ _ _ _ _ FLAG 07078h XINT2CR _ XINT2 _ XINT2 XINT2 XINT2 XINT2 XINT2 PIN DATA DATA DIR DATA OUT POLARITY PRIORITY ENA 07079h Reserved we POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 99TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 register file compilation (continued) ADDR Table 20. Register File Compilation (Continued) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT9 BIT8 REG BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO XTERNAL INTERRUPT CONTROL REGISTERS (CONTINUED) XINT3 _ _ _ _ _ _ _ FLAG 0707Ah XINT3CR _ XINT3 _ XINT3 XINT3 XINT3 XINT3 XINT3 PIN DATA DATA DIR DATA OUT POLARITY PRIORITY ENA 0707Bh to Reserved 0708Fh DIGITAL /O CONTROL REGISTERS CRA.15 CRA.14 CRA.13 CRA.12 CRA.11 CRA.10 CRA9 CRA.8 07090h OCRA _ _ _ _ CRA.3 CRA.2 CRA.1 CRA.O 07091h Reserved 07092h = = vs vs so so ws ss OCRB CRB.7 CRB.6 CRB.5 CRB.4 CRB.3 CRB.2 CRB.1 CRB.O 07093h to Reserved 07097h _ _ _ _ A3DIR A2DIR A1DIR AODIR 07098h PADATDIR _ _ _ _ IOPA3 IOPA2 IOPA1 IOPAO 07099h Reserved B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR BODIR 0709Ah PBDATDIR IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPBO 0709Bh Reserved C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR CODIR 0709Ch PCDATDIR IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 lOPG2 IOPC1 IOPCO 0709Dh to Reserved 073FFh GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS T3STAT T2STAT T1ISTAT T3TOADG T2TOADG T1TOADG(1) 07400h GPTCON TITOADCG(O) | TCOMPOE T3PIN T2PIN T1PIN D15 D14 D13 D12 D11 D10 D9 D8 07401h TICNT D7 D6 D5 D4 D3 D2 D1 Do D15 D14 D13 D12 D11 D10 D9 D8 07402h T1CGMPR D7 D6 D5 D4 D3 D2 D1 Do D15 D14 D13 D12 D11 D10 D9 D8 07403h T1PR D7 D6 D5 D4 D3 D2 D1 Do FREE SOFT TMODE2 TMODE1 TMODEO TPS2 TPS1 TPSO 07404h TICON TSWT1 TENABLE TCLKS1 TCLKSO TCLD1 TCLDO TECMPR SELT1PR D15 D14 D13 D12 D11 D10 D9 D8 07405h T2CNT D7 D6 D5 D4 D3 D2 D1 Do D15 D14 D13 D12 D11 D10 D9 D8 07406h T2CMPR D7 D6 D5 D4 D3 D2 D1 Do we 100 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443register file compilation (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 20. Register File Compilation (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT9 BIT8 REG BIT7 BIT6 BITS BIT4 BIT3 BIT 2 BIT 1 BITO GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS (CONTINUED) D15 D14 Di3 Di2 Di1 D10 Dg D8 07407h T2PR D7 D D5 D4 D3 D2 D1 DO FREE SOFT TMODE2 TMODE1 TMODEO TPS2 TPS1 TPSO 07408h T2CON TSWT1 TENABLE TCLKS1 TCLKSO TCLD1 TCLDO TECMPR SELT1PR D15 D14 Di3 Di2 Di1 D10 Dg D8 07409h T3CNT D7 D6 D5 D4 D3 D2 D1 Do D15 D14 Di3 Di2 Di1 D10 Dg D8 0740Ah T3CMPR D7 D D5 D4 D3 D2 D1 DO D15 D14 Di3 Di2 Di1 D10 Dg D8 0740Bh T3PR D7 D D5 D4 D3 D2 D1 DO FREE SOFT TMODE2 TMODE1 TMODEO TPS2 TPS1 TPSO 0740Ch T3CON TSWT1 TENABLE TCLKS1 TCLKSO TCLD1 TCLDO TECMPR SELT1PR 0740Dh to Reserved 07410h FULL AND SIMPLE COMPARE UNIT REGISTERS CENABLE CLD1 CLDO SVENABLE ACTRLD1 ACTRLDO FCOMPOE SCOMPOE 07411h COMCON SELTMR SCLD1 SCLDO SACTRLD1 | SACTRLDO | SELCMP3 | SELCMP2 SELCMP1 07412h Reserved SVRDIR D2 D1 Do CMP6ACT1 CMP6ACTO | CMPSACT1 CMPSACTO 07413h ACTR CMP4ACT1 | CMP4ACTO | CMP3ACT1 | CMP3ACTO | CMP2ACT1 | CMP2ACTO | CMP1ACT1 | CMP1ACTO 07414h 7 7 SCMP3- SCMP3- SCMP2- SCMP2- SCMP1- scmP1- | SACTR ACT1 ACTO ACT1 ACTO ACT1 ACTO DBT7 DBT6 DBT5 DBT4 DBT3 DBT2 DBT1 DBTO 07415h DBTCON EDBT3 EDBT2 EDBT1 DBTPS1 DBTPSO 07416h Reserved D15 D14 Di3 Di2 Di1 D10 Dg D8 07417h CMPR1 D7 D6 D5 D4 D3 D2 D1 Do D15 D14 Di3 Di2 Di1 D10 Dg D8 07418h CMPR2 D7 D6 D5 D4 D3 D2 D1 Do D15 D14 Di3 Di2 Di1 D10 Dg D8 07419h CMPR3 D7 D6 D5 D4 D3 D2 D1 Do D15 D14 Di3 Di2 Di1 D10 Dg D8 0741Ah SCMPR1 D7 D6 D5 D4 D3 D2 D1 Do D15 D14 Di3 Di2 Di1 D10 Dg D8 0741Bh SCMPR2 D7 D6 D5 D4 D3 D2 D1 Do D15 D14 Di3 Di2 Di1 D10 Dg D8 0741Ch SCMPR3 D7 D6 D5 D4 D3 D2 D1 Do 0741Dh to Reserved 0741Fh i POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 101TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 register file compilation (continued) Table 20. Register File Compilation (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT8 REG BIT7 BIT6 BITS BIT 4 BIT3 BIT 2 BIT 1 BITO CAPTURE UNIT REGISTERS CAPRES CAPQEPN CAP3EN CAP4EN | CAP34TSEL | CAP12TSEL | CAP4TOADC 07420h CAPCON CAP1EDGE CAP2EDGE CAP3EDGE CAP4EDGE 07421h Reserved CAP4FIFO CAP3FIFO CAP2FIFO CAP1FIFO 07422h CAPFIFO CAPFIFO15 | CAPFIFO14 | CAPFIFO13 | CAPFIFO12 | CAPFIFO11 | CAPFIFO10 | CAPFIFO9 CAPFIFO8 D15 D14 D13 D12 D114 D10 D9 D8 07423h CAP1FIFO D7 D6 D5 D4 D3 D2 DI DO D15 D14 D13 D12 D114 D10 D9 D8 07424h CAP2FIFO D7 D6 D5 D4 D3 D2 DI DO D15 D14 D13 D12 D114 D10 D9 D8 07425h CAP3FIFO D7 D6 D5 D4 D3 D2 DI DO D15 D14 D13 D12 D114 D10 D9 D8 07426h CAP4FIFO D7 D6 D5 D4 D3 D2 DI DO 07427h to Reserved 0742Bh EVENT MANAGER (EV) INTERRUPT CONTROL REGISTERS 7 7 7 7 7 T1OFINT T1UFINT T1CINT ENA ENA ENA 0742Ch EVIMRA T1PINT SCMP3INT | SCMP2INT | SCMP1INT | CMP3INT CMP2INT CMP1INT PDPINT ENA ENA ENA ENA ENA ENA ENA ENA 0742Dh | T3O0FINT T3UFINT T3CINT T3PINT T2OFINT T2UFINT T2CINT T2PINT EVIMRB ENA ENA ENA ENA ENA ENA ENA ENA 0742Eh 7 7 7 7 CAP4INT CAPSINT CAP2INT CAPIINT = | EVIMRC ENA ENA ENA ENA 7 7 7 7 7 T1OFINT T1UFINT T1CINT FLAG FLAG FLAG 0742Fh EVIFRA T1PINT SCMP3INT | SCMP2INT ]| SCMP1INT | CMP3INT CMP2INT CMP1INT PDPINT FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG 07430h | T3OFINT T3UFINT T3CINT T3PINT T2OFINT T2UFINT T2CINT T2PINT EVIFRB FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG 07431h _ _ _ _ CAP4INT CAP3INT CAP2INT CAPIINT | EVIFRC FLAG FLAG FLAG FLAG 0 0 0 0 0 0 0 0 07432h EVIVRA 0 0 D5 D4 D3 D2 DI DO 0 0 0 0 0 0 0 0 07433h EVIVRB 0 0 D5 D4 D3 D2 DI DO 0 0 0 0 0 0 0 0 07434h EVIVRG 0 0 D5 D4 D3 D2 DI DO 07435h to Reserved 0743Fh i 102 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443register file compilation (continued) TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 Table 20. Register File Compilation (Continued) Appr | BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT9 BIT8 BIT7 BIT6 BITS BIT 4 BIT3 BIT2 BIT 1 BITO VO MEMORY SPACE FLASH CONTROL MODE REGISTERt OFFOFh a os = = oo ws a ws WAIT-STATE GENERATOR CONTROL REGISTER OFFFFh a oo oo a - = a oe AVIS Isws DSws PSWS t See the flash control mode register section. Wi TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 103TMS320C240, TMS320F 240 DSP CONTROLLERS SPRS042D OCTOBER 1996 REVISED NOVEMBER 1998 MECHANICAL DATA PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK 100 LEAD SHOWN 13 1100 89 88 0.012 (0,30) 0.008 (0,20) D3 SQ 0.006 (0,16) NOM 38 64 a 0.150 (3,81) 0.130 (3,30) 1 - ap Gage Plane D1 *D SQ 0.010 (0.25) 4 D2 SQ 0.020 (0,51) MIN 0-8 0.046 (1,17) 0.036 (0,91) Seating Plane | | 0.004 (0,10) y= _ 0.180 (4,57) MAX LEADS ** DIM 100 132 > MAX 0.890 (22,61) 1.090 (27,69) MIN 0.870 (22,10) 1.070 (27,18) Dr MAX 0.766 (19,46) 0.966 (24,54) MIN 0.734 (18,64) 0.934 (23,72) spe" MAX 0.912 (23,16) 1.112 (28,25) MIN 0.888 (22,56) 1.088 (27,64) "D3" NOM 0.600 (15,24) 0.800 (20,32) 4040045/C 11/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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