CY7C1071DV33
32-Mbit (2 M × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-12063 Rev. *I Revised October 17, 2011
32-Mbit (2 M × 16) Static RAM
Features
■High speed
❐tAA = 12 ns
■Low active power
❐ICC = 250 mA at 83.3 MHz
■Low Complementary Metal Oxide Semiconductor (CMOS)
standby power
❐ISB2 = 50 mA
■Operating voltages of 3.3 ± 0.3 V
■2.0 V data retention
■Automatic power down when deselected
■TTL compatible inputs and outputs
■Available in Pb-free 48-ball FBGA package
Functional Description
The CY7C1071DV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 16 bits. The input and output
pins (I/O0 through I/O15) are placed in a high impedance state
when:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH)
■Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH)
■The write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A20). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A20).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
IO0–IO7
ROW DECODER
SENSE AMPS
DATA IN DRIVERS
OE
IO8–IO15
WE
BLE
BHE
COLUMN DECODER
2M × 16
RAM ARRAY
CE
A(10:0)
A(20:11)
Logic Block Diagram
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Document Number: 001-12063 Rev. *I Page 2 of 14
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
DC Electrical Characteristics ..........................................4
Capacitance ...................................................................... 4
Thermal Resistance ..........................................................4
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 5
AC Switching Characteristics .........................................6
Switching Waveforms ......................................................7
Truth Table ......................................................................10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
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Selection Guide
Description -12 Unit
Maximum Access Time 12 ns
Maximum Operating Current 250 mA
Maximum CMOS Standby Current 50 mA
Pin Configuration
Figure 1. 48-ball FBGA [1]
WE
A11
A10
A6
A0
A3CE
IO10
IO8
IO9
A4
A5
IO11
IO13
IO12
IO14
IO15
VSS
A9
A8
OE
A7
IO0
BHE
NC
A17
A2
A1
BLE
IO2
IO1
IO3
IO4
IO5IO6
IO7
A15
A14
A13
A12
A20
A18 A19
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
Note
1. NC pins are not connected to the die.
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Document Number: 001-12063 Rev. *I Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC Relative to GND [2] ...............................–0.3 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [2] ................................. –0.5 V to VCC + 0.5 V
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch up Current .................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85C 3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -12 Unit
Min Max
VOH Output HIGH Voltage Min VCC, IOH = –4.0 mA 2.4 – V
VOL Output LOW Voltage Min VCC, IOL = 8.0 mA – 0.4 V
VIH [2] Input HIGH Voltage 2.0 VCC + 0.3 V
VIL [2] Input LOW Voltage –0.3 0.8 V
IIX Input Leakage Current GND < VIN < VCC –1 +1 A
IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A
ICC VCC Operating Supply Current VCC = Max, f = fmax = 1/tRC, IOUT = 0 mA
CMOS levels
–250mA
ISB1 Automatic CE Power Down Current –
TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL,
f = fmax
–60mA
ISB2 Automatic CE Power Down Current –
CMOS Inputs Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0,
VCC = VCC(max)
–50mA
Capacitance
Parameter[3] Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 16 pF
COUT I/O Capacitance 20 pF
Thermal Resistance
Parameter[3] Description Test Conditions 48-ball FBGA Unit
JA Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer printed
circuit board
24.72 C/W
JC Thermal Resistance
(Junction to Case)
5.79 C/W
Notes
2. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
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AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ Max Unit
VDR VCC for Data Retention 2 – – V
ICCDR Data Retention Current VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
––50mA
tCDR[5] Chip Deselect to Data Retention
Time
0––ns
tR[6] Operation Recovery Time tRC ––ns
Figure 3. Data Retention Waveform
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
3.3 V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE (b)
R1 317
R2
351
RISE TIME: FALL TIME:
> 1 V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= 1.5 V
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
HIGH-Z CHARACTERISTICS:
(a)
> 1 V/ns
3.0 V3.0 V
t
CDR
VDR >2 V
DATA RETENTION MODE
tR
CE
VCC
Notes
4. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD,
normal SRAM operation begins to include reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
5. Tested initially and after any design or process changes that may affect these parameters.
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
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AC Switching Characteristics
Over the Operating Range [7]
Parameter Description -12 Unit
Min Max
Read Cycle
tpower VCC(typ) to the first access [8] 100 – s
tRC Read Cycle Time 12 – ns
tAA Address to Data Valid – 12 ns
tOHA Data Hold from Address Change 3 – ns
tACE CE LOW to Data Valid – 12 ns
tDOE OE LOW to Data Valid – 7 ns
tLZOE OE LOW to Low Z [9] 1–ns
tHZOE OE HIGH to High Z [9] –7ns
tLZCE CE LOW to Low Z [9] 3–ns
tHZCE CE HIGH to High Z [9] –7ns
tPU CE LOW to Power Up [10] 0–ns
tPD CE HIGH to Power Down [10] –12ns
tDBE Byte Enable to Data Valid – 7 ns
tLZBE Byte Enable to Low Z [9] 1–ns
tHZBE Byte Disable to High Z [9] –7ns
Write Cycle [11, 12]
tWC Write Cycle Time 12 – ns
tSCE CE LOW to Write End 9 – ns
tAW Address Setup to Write End 9 – ns
tHA Address Hold from Write End 0 – ns
tSA Address Setup to Write Start 0 – ns
tPWE WE Pulse Width 9–ns
tSD Data Setup to Write End 7 – ns
tHD Data Hold from Write End 0 – ns
tLZWE WE HIGH to Low Z [9] 3–ns
tHZWE WE LOW to High Z [9] –7ns
tBW Byte Enable to End of Write 9 – ns
Notes
7. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read
cycle use output loading shown in part (a) of Figure 2 on page 5, unless specified otherwise.
8. tpower is the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed.
9. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured at
±200 mV from steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal memory write time is defined by the overlap of CE, WE = VIL. Chip enables must be active and WE and byte enables must be LOW to initiate a write,
and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that
terminates the write.
12. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled) [13, 14]
Figure 5. Read Cycle 2 (OE Controlled) [14, 15]
PREVIOUS DATA VALID
DATA OUT VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA I/O
50%
50%
DATA OUT VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
HIGH
IMPEDANCE
ICC
ISB
OE
CE
ADDRESS
DATA I/O
V
CC
SUPPLY
BHE
,
BLE
CURRENT
Notes
13. Device is continuously selected. OE, CE, BHE or BHE or both = VIL.
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
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Figure 6. Write Cycle 1 (CE Controlled) [16, 17]
Figure 7. Write Cycle 2 (WE Controlled, OE LOW) [16, 17]
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA
I/O
ADDRESS
CE
WE
BHE,BLE
DATA IN VALID
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA
I/O
ADDRESS
CE
WE
BHE,BLE
DATA IN VALID
Notes
16. Data I/O is high impedance if OE or BHE, BLE or both = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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Truth Table
CE OE WE BLE BHE I/O0–IO7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power-down Standby (ISB)
L L H L L Data Out Data Out Read All Bits Active (ICC)
L L H L H Data Out High Z Read Lower Bits Only Active (ICC)
L L H H L High Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write All Bits Active (ICC)
L X L L H Data In High Z Write Lower Bits Only Active (ICC)
L X L H L High Z Data In Write Upper Bits Only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
12 CY7C1071DV33-12BAXI 51-85191 48-ball FBGA (8 × 9.5 × 1.2 mm) (Pb-free) Industrial
Ordering Code Definitions
Temperature Range:
I = Industrial
Pb-free
Package Type:
BA = 48-ball FBGA
Speed: 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
07 = 32-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - 12 BA707 D IV331 X
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Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
FPBGA fine-pitch ball grid array
I/O input/output
OE output enable
SRAM static random access memory
TTL transistor-transistor logic
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mm millimeter
ms millisecond
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
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Document History Page
Document Title: CY7C1071DV33, 32-Mbit (2 M × 16) Static RAM
Document Number: 001-12063
REV. ECN NO. Submission
Date
Orig. of
Change Description of Change
** 605460 See ECN VKN New Data sheet
*A 1192183 See ECN VKN /
KKVTMP
Removed CE2 feature
Updated block diagram
Changed ICC spec from 160 mA to 225 mA
Changed CIN spec from 8 pF to 10 pF
Changed COUT spec from 10 pF to 12 pF
Changed tBW spec from 8 ns to 9 ns
*B 2711136 05/29/2009 VKN /
PYRS
Added 10 ns speed bin
In 12 ns speed bin, changed ISB1 from 70 to 60 mA and ISB2 from 60 to 50 mA
Changed CIN from 8 pF to 16 pF and COUT from 10 pF to 20 pF
Changed JA from 28.37 C/W to 24.72 C/W
Removed 119-Ball PBGA package
Added 48-Ball FBGA package
*C 2759408 09/03/2009 VKN /
AESA
Removed 10ns speed
Marked thermal specs as “TBD”
Changed tDOE, tHZOE, tHZCE, tDBE, tHZBE, tHZWE specs from 6 ns to 7ns
Added -12B2XI part (Dual CE option)
*D 2813370 11/23/2009 VKN Changed ICC spec from 225 mA to 250 mA.
*E 2925803 04/30/2010 VKN /
AESA
Converted from Preliminary to Final
Removed Dual CE option from the data sheet
Updated links in Sales, Solutions, and Legal Information
*F 3109063 12/13/2010 AJU Added Ordering Code Definitions.
*G 3132969 01/11/2011 AJU Added Acronyms and Units of Measure.
Changed all instances of IO to I/O.
Updated in new template.
*H 3268861 05/28/2011 AJU Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
*I 3411360 10/17/2011 TAVA Updated Features.
Updated DC Electrical Characteristics.
Updated Switching Waveforms.
Updated Package Diagram.
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Document Number: 001-12063 Rev. *I Revised October 17, 2011 Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1071DV33
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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