Low Gain Drift
Precision Instrumentation Amplifier
AD8228
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Easy to use
Pin strappable gains of 10 and 100
Wide power supply range: ±2.3 V to ±18 V
DC specifications (B Grade, G = 10)
2 ppm/°C gain drift
0.02% gain error
50 μV maximum input offset voltage
0.8 μV/°C maximum input offset drift
0.6 nA maximum input bias current
100 dB CMRR
AC specifications
650 kHz, –3 dB bandwidth (G = 10)
2 V/μs slew rate
Low noise
8 nV/√Hz, @ 1 kHz (G = 100)
0.3 μV p-p from 0.1 Hz to 10 Hz (G = 100)
APPLICATIONS
Weigh scales
Industrial process controls
Bridge amplifiers
Precision data acquisition systems
Medical instrumentation
Strain gages
Transducer interfaces
GENERAL DESCRIPTION
The AD8228 is a high performance instrumentation amplifier
with very high gain accuracy. Because all gain setting resistors
are internal and laser trimmed, gain accuracy and gain drift
are better than can be achieved with typical instrumentation
amplifiers.
Low voltage offset, low offset drift, low gain drift, high gain
accuracy, and high CMRR make this part an excellent choice
in applications that demand the best dc performance possible,
such as bridge signal conditioning.
CONNECTION DIAGRAM
8
7
6
5
1
2
3
4
–IN
G1
G2
+V
S
V
OUT
REF
–V
S
+
IN
TOP VIEW
(Not to Scale)
AD8228
07035-001
Figure 1.
Table 1. Instrumentation Amplifiers by Category
General
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624
1 Rail-to-rail output.
The AD8228 operates on both single and dual supplies. Because
the part can operate on supplies up to ±18 V, it is well suited for
applications where high common-mode input voltages are
encountered. The AD8228 is available in 8-lead MSOP and
SOIC packages.
Performance is specified over the entire industrial temperature
range of −40°C to +85°C for all grades. Furthermore, the AD8228
is operational from −40°C to +12C. For a pin-compatible ampli-
fier with similar specifications, but with a gain range of 1 to 1000,
see the AD8221.
AD8228
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Gain = 10 ....................................................................................... 3
Gain = 100 ..................................................................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 16
Architecture ................................................................................ 16
Setting the Gain .......................................................................... 16
Common-Mode Input Voltage Range..................................... 16
Reference Terminal .................................................................... 17
Layout .......................................................................................... 17
Input Protection ......................................................................... 18
Radio Frequency Interference (RFI) ........................................ 18
Applications Information.............................................................. 19
Differential Drive ....................................................................... 19
Precision Strain Gage................................................................. 19
Driving a Differential ADC ...................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
7/08—Revision 0: Initial Version
AD8228
Rev. 0 | Page 3 of 24
SPECIFICATIONS
GAIN = 10
VS = ±15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, all specifications referred to input, unless otherwise noted.
Table 2.
Conditions A Grade B Grade
Parameter (Gain = 10) Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
VCM = −10 V to +10 V 94 100 dB
CMRR at 2 kHz VCM = −10 V to +10 V 90 100 dB
NOISE VIN+ = VIN− = VREF = 0 V
Voltage Noise f = 1 kHz 15 15 nV/√Hz
f = 0.1 Hz to 10 Hz 0.5 0.5 μV p-p
Current Noise f = 1 kHz 40 40 fA/√Hz
f = 0.1 Hz to 10 Hz 6 6 pA p-p
VOLTAGE OFFSET Referred to input,
VS = ±5 V to ±15 V
Offset 90 50 μV
Over Temperature T = −40°C to +85°C 180 100 μV
Average TC T = −40°C to +85°C 1.5 0.8 μV/°C
Offset vs. Supply (PSR) 104 120 106 120 dB
INPUT CURRENT
Input Bias Current 0.5 1.5 0.4 0.6 nA
Over Temperature T = −40°C to +85°C 2.0 1 nA
Average TC T = −40°C to +85°C 1 1 pA/°C
Input Offset Current 0.2 0.6 0.1 0.4 nA
Over Temperature T = −40°C to +85°C 0.8 0.6 nA
Average TC T = −40°C to +85°C 1 1 pA/°C
REFERENCE INPUT
RIN 20 20
IIN V
IN+ = VIN− = VREF = 0 V 50 60 50 60 μA
Voltage Range −VS +VS −VS +VS V
Gain to Output 1 ± 0.0001 1 ± 0.0001 V/V
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth 650 650 kHz
Settling Time 0.01% 10 V step 6 6 μs
Settling Time 0.001% 10 V step 9 9 μs
Slew Rate 2 2.5 2 2.5 V/μs
GAIN VOUT = −10 V to +10 V
Gain Error 0.07 0.02 %
Gain Nonlinearity
RL = 10 kΩ 3 10 3 10 ppm
RL = 2 kΩ 3 10 3 10 ppm
Gain vs. Temperature 1 10 1 2 ppm/°C
INPUT
Input Impedance
Differential 100||2 100||2 GΩ||pF
Common Mode 100||2 100||2 GΩ||pF
Input Operating Voltage Range1VS = ±2.3 V to ±5 V −VS + 1.9 +VS − 1.1 −VS + 1.9 +VS 1.1 V
Over Temperature T =40°C to +85°C −VS + 2.0 +VS − 1.2 −VS + 2.0 +VS − 1.2 V
Input Operating Voltage Range1 V
S = ±5 V to ±18 V −VS + 1.9 +VS − 1.2 VS + 1.9 +VS − 1.2 V
Over Temperature T = −40°C to +85°C −VS + 2.0 +VS − 1.2 VS + 2.0 +VS − 1.2 V
AD8228
Rev. 0 | Page 4 of 24
Conditions A Grade B Grade
Parameter (Gain = 10) Min Typ Max Min Typ Max Unit
OUTPUT RL = 10 kΩ
Output Swing VS = ±2.3 V to ±5 V −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 V
Over Temperature T = −40°C to +85°C −VS + 1.4 +Vs − 1.3 −VS + 1.4 +VS − 1.3 V
Output Swing VS = ±5 V to ±18 V −VS + 1.2 +VS 1.4 −VS + 1.2 +VS − 1.4 V
Over Temperature T = –40°C to +85°C −VS + 1.6 +VS − 1.5 −VS + 1.6 +VS − 1.5 V
Short-Circuit Current 18 18 mA
POWER SUPPLY
Operating Range VS = ±2.3 V to ±18 V ±2.3 ±18 ±2.3 ±18 V
Quiescent Current 0.85 1 0.85 1 mA
Over Temperature T = −40°C to +85°C 1 1.2 1 1.2 mA
TEMPERATURE RANGE
Specified Performance −40 +85 −40 +85 °C
Operating Range2 −40 +125 −40 +125 °C
1 Operating near the input voltage range limit may reduce the available output range. See Figure 10 and Figure 11 for the input common-mode range vs. output
voltage.
2 See the Typical Performance Characteristics section for expected operation between 85°C to 125°C.
AD8228
Rev. 0 | Page 5 of 24
GAIN = 100
VS = ±15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, all specifications referred to input, unless otherwise noted.
Table 3.
Conditions A Grade B Grade
Parameter (Gain = 100) Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
VCM = −10 V to +10 V 114 120 dB
CMRR at 2 kHz VCM = −10 V to +10 V 100 105 dB
NOISE VIN+ = VIN− = VREF = 0 V
Voltage Noise f = 1 kHz 8 8 nV/√Hz
f = 0.1 Hz to 10 Hz 0.3 0.3 μV p-p
Current Noise f = 1 kHz 40 40 fA/√Hz
f = 0.1 Hz to 10 Hz 6 6 pA p-p
VOLTAGE OFFSET Referred to input,
VS = ±5 V to ±15 V
Offset 90 50 μV
Over Temperature T = −40°C to +85°C 140 80 μV
Average TC T = −40°C to +85°C 0.9 0.5 μV/°C
Offset vs. Supply (PSR) 118 140 124 140 dB
INPUT CURRENT
Input Bias Current 0.5 1.5 0.4 0.6 nA
Over Temperature T = −40°C to +85°C 2.0 1 nA
Average TC T = −40°C to +85°C 1 1 pA/°C
Input Offset Current 0.2 0.6 0.1 0.4 nA
Over Temperature T = −40°C to +85°C 0.8 0.6 nA
Average TC T = −40°C to +85°C 1 1 pA/°C
REFERENCE INPUT
RIN 20 20
IIN V
IN+ = VIN− = VREF = 0 V 50 60 50 60 μA
Voltage Range −VS +VS −VS +VS V
Gain to Output 1 ± 0.0001 1 ± 0.0001 V/V
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth 110 110 kHz
Settling Time 0.01% 10 V step 13 13 μs
Settling Time 0.001% 10 V step 15 15 μs
Slew Rate 2 2.5 2 2.5 V/μs
GAIN VOUT = −10 V to +10 V
Gain Error 0.1 0.05 %
Gain Nonlinearity
RL = 10 kΩ 5 15 5 15 ppm
RL = 2 kΩ 15 45 15 45 ppm
Gain vs. Temperature 1 10 1 2 ppm/°C
INPUT
Input Impedance
Differential 100||2 100||2 GΩ||pF
Common Mode 100||2 100||2 GΩ||pF
Input Operating Voltage Range1 V
S = ±2.3 V to ±5 V −VS + 1.9 +VS − 1.1 VS + 1.9 +VS − 1.1 V
Over Temperature T = −4C to +8C VS + 2.0 +VS − 1.2 −VS + 2.0 +VS − 1.2 V
Input Operating Voltage Range1 VS = ±5 V to ±18 V −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS 1.2 V
Over Temperature T =−40°C to +85°C −VS + 2.0 +VS − 1.2 −VS + 2.0 +VS 1.2 V
AD8228
Rev. 0 | Page 6 of 24
Conditions A Grade B Grade
Parameter (Gain = 100) Min Typ Max Min Typ Max Unit
OUTPUT RL = 10 kΩ
Output Swing VS = ±2.3 V to ±5 V −VS + 1.1 +VS − 1.2 VS + 1.1 +VS − 1.2 V
Over Temperature T = −40°C to +85°C −VS + 1.4 +Vs − 1.3 −VS + 1.4 +VS − 1.3 V
Output Swing VS = ±5 V to ±18 V −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS 1.4 V
Over Temperature T = −40°C to +85°C −VS + 1.6 +VS − 1.5 VS + 1.6 +VS 1.5 V
Short-Circuit Current 18 18 mA
POWER SUPPLY
Operating Range VS = ±2.3 V to ±18 V ±2.3 ±18 ±2.3 ±18 V
Quiescent Current 0.85 1 0.85 1 mA
Over Temperature T = −40°C to +85°C 1 1.2 1 1.2 mA
TEMPERATURE RANGE
Specified Performance −40 +85 −40 +85 °C
Operating Range2 −40 +125 −40 +125 °C
1 Operating near the input voltage range limit may reduce the available output range. See Figure 12 and Figure 13 for the input common-mode range vs. output
voltage.
2 See the Typical Performance Characteristics section for expected operation between 85°C to 125°C.
AD8228
Rev. 0 | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±VS
Storage Temperature Range −65°C to +150°C
Operating Temperature Range1 −40°C to +125°C
Maximum Junction Temperature 140°C
ESD
Human Body Model 2 kV
Charge Device Model 1 kV
1 Temperature range for specified performance is −40°C to +85°C. See the
Typical Performance Characteristics section for expected operation from
85°C to 125°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for a device in free air.
Table 5.
Package θJA Unit
8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W
8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W
ESD CAUTION
AD8228
Rev. 0 | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
7
6
5
1
2
3
4
–IN
G1
G2
+V
S
V
OUT
REF
–V
S
+IN
TOP VIEW
(Not to Scale)
AD8228
07035-004
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input.
2, 3 G1, G2 Gain Pins. Short together for a gain of 100. Leave unconnected for a gain of 10.
4 +IN Positive Input.
5 −VS Negative Supply.
6 REF Reference.
7 VOUT Output.
8 +VS Positive Supply.
AD8228
Rev. 0 | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
70
60
50
40
30
20
10
0
–100 –50 0 50 100
G10 SYSTEM V
OS
RTI @ 15V (µV)
HITS
07035-043
MEAN: –5.5
SD: 12.4
Figure 3. Typical Distribution of Input Offset Voltage (G = 10)
60
50
40
30
20
10
0
–1.5 –1.0 0.5 0 0.5 1.0 1.5
G10 SYSTEM V
OS
DRIFT RTI (µV)
HITS
07035-045
MEAN: –0.079
SD: 0.27
Figure 4. Typical Distribution of Input Offset Voltage Drift (G = 10)
80
60
40
20
0
–100 –50 0 50 100
G100 SYSTEM V
OS
RTI @ 15V (µV)
HITS
07035-046
MEAN: 7.1
SD: 10.1
Figure 5. Typical Distribution of Input Offset Voltage (G = 100)
100
80
60
40
20
0
–1.0 –0.5 0 0.5 1.0 1.5
G100 SYSTEM V
OS
DRIFT RTI (µV)
HITS
07035-047
MEAN: 0.20
SD: 0.12
Figure 6. Typical Distribution of Input Offset Voltage Drift (G = 100)
100
80
60
40
20
0
–3 –2 –1 0 1 2 3
CMRR G100 RTI (µV/V)
HITS
07035-048
MEAN: 0.29
SD: 0.27
Figure 7. Typical Distribution for CMR (G = 100)
100
120
80
60
40
20
0
1.5–0.5 0 0.5 1.0
NEG I
BIAS
CURRENTS ±15V (nA)
HITS
07035-049
MEAN: 0.42
SD: 0.08
Figure 8. Typical Distribution of Input Bias Current
AD8228
Rev. 0 | Page 10 of 24
80
60
40
20
0
–0.6 –0.4 –0.2 0 0.2 0.4 0.6
I
OS
@ 15V (nA)
HITS
07035-050
MEAN: –0.097
SD: 0.07
Figure 9. Typical Distribution of Input Offset Current
5
4
3
2
1
0
–1
–2
–3
–4
–5
–5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
07035-033
V
S
= ±5V
V
S
= ±2.5V
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
VS = ±2.5 V, ±5 V; G =10
15
10
5
0
–5
–10
–15
–15 –10 –5 0 5 10 15
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
07035-034
VS = ±15V
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
VS = ±15 V, G = 10
5
4
3
2
1
0
–1
–2
–3
–4
–5
–5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
07035-035
V
S
= ±5V
V
S
= ±2.5V
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
VS = ±2.5 V, ±5 V; G = 100
15
10
5
0
–5
–10
–15
–15 –10 –5 0 5 10 15
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
07035-036
VS = ±15V
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
VS = ±15 V, G = 100
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
–15 –10 –5 0 5 10 15
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (nA)
07035-051
+IN IBIAS, ±15V SUPPLIES
–IN IBIAS, ±15V SUPPLIES
+IN IBIAS, ±5V SUPPLIES
–IN IBIAS, ±5V SUPPLIES
Figure 14. Input Bias Current vs. Common-Mode Voltage
AD8228
Rev. 0 | Page 11 of 24
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.01 0.1 1 10
WARM-UP TIME (Minutes)
CHANGE IN INPUT OFFSET VOLTAGE (µV)
07035-002
Figure 15. Change in Input Offset Voltage vs. Warm-Up Time
3
2
1
0
–1
–2
–3
4
–4
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
INPUT BIAS CURRENT (nA)
07035-052
–IN I
BIAS
+IN I
BIAS
I
OS
Figure 16. Input Bias Current and Offset Current vs. Temperature
160
140
120
100
80
60
40
20
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
POSITIVE PSRR (dB)
07035-012
G = 100
G = 10
Figure 17. Positive PSRR vs. Frequency, RTI
160
140
120
100
80
60
40
20
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
NEGATIVE PSRR (dB)
07035-013
G = 100
G = 10
Figure 18. Negative PSRR vs. Frequency
70
60
50
40
30
20
10
0
–10
–20
–30
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
GAIN (dB)
07035-019
G = 100
G = 10
Figure 19. Gain vs. Frequency
150
100
50
0
–50
–100
–150
–45 –15 15 45 75 105–30 0 30 60 90 120 135
TEMPERATURE (°C)
GAIN ERROR (µV/V)
07035-007
G = 100
G = 10
Figure 20. Gain Error vs. Temperature
AD8228
Rev. 0 | Page 12 of 24
140
120
100
80
60
40
0 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
CMRR (dB)
07035-039
G = 100
G = 10
Figure 21. CMRR vs. Frequency, RTI
140
120
100
80
60
40
0 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
CMRR (dB)
07035-040
G = 100
G = 10
Figure 22. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
15
10
5
0
–5
–10
–15
20
–20
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
CMR (µV/V)
07035-008
Figure 23. CMR vs. Temperature
+
V
S
– 0
+V
S
– 0.4
+V
S
– 0.8
+V
S
– 1.2
+V
S
– 1.6
+V
S
– 2.0
–V
S
+ 2.0
–V
S
+ 1.6
–V
S
+ 1.2
–V
S
+ 0.8
–V
S
+ 0.4
–V
S
+ 0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
INPUT VOLTAGE LIMIT (V)
REFERRED TO SUPPLY VOLTAGES
07035-014
Figure 24. Input Voltage Limit vs. Supply Voltage
+
V
S
– 0
+V
S
– 0.4
+V
S
– 0.8
+V
S
– 1.2
+V
S
– 1.6
+V
S
– 2.0
–V
S
+ 2.0
–V
S
+ 1.6
–V
S
+ 1.2
–V
S
+ 0.8
–V
S
+ 0.4
–V
S
+ 0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE LIMIT (V)
REFERRED TO SUPPLY VOLTAGES
07035-015
R
L
= 10k
R
L
= 2k
R
L
= 10k
R
L
= 2k
Figure 25. Output Voltage Swing vs. Supply Voltage
30
25
20
15
10
5
0
1 10 100 1k 10k
LOAD RESISTANCE ()
OUTPUT VOLTAGE (V p-p)
07035-020
V
S
= ±15V
Figure 26. Output Voltage Swing vs. Load Resistance
AD8228
Rev. 0 | Page 13 of 24
+
V
S –0
–1
–2
–3
+3
+2
+1
–VS +0
0 1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGE
07035-021
Figure 27. Output Voltage Swing vs. Output Current, G = 1
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
07035-016
ERROR (10ppm/DIV)
Figure 28. Gain Nonlinearity, G = 10, RL = 10 kΩ
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
07035-029
ERROR (10ppm/DIV)
Figure 29. Gain Nonlinearity, G = 100, RL = 10 kΩ
1k
100
10
1
1 10 100 1k 10k 100k
FREQUENCY (Hz)
VOLTAGE NOISE RTI (nV/
Hz)
07035-022
G = 100
G = 10
Figure 30. Voltage Noise Spectral Density vs. Frequency
0.2µV/DIV 1s/DIV
07035-023
Figure 31. 0.1 Hz to 10 Hz RTI Voltage Noise, G=10
1000
100
10
1
1 10 100 1k 10k
FREQUENCY (Hz)
CURRENT NOISE (fA/ Hz)
07035-030
Figure 32. Current Noise Spectral Density vs. Frequency
AD8228
Rev. 0 | Page 14 of 24
0
7035-031
5pA/DIV
1s/DIV
Figure 33. 0.1 Hz to 10 Hz Current Noise
30
25
20
15
10
5
0
1k 10k 100k 1M
FREQUENCY (Hz)
OUTPUT VOLTAGE (V p-p)
07035-024
V
S
= ±15V
G = 10, 100
Figure 34. Large Signal Frequency Response
5V/DIV
0.002%/DIV
20µs/DIV
07035-025
Figure 35. Large Signal Pulse Response and Settling Time (G = 10)
5V/DIV
0.002%/DIV
20µs/DIV
07035-026
Figure 36. Large Signal Pulse Response and Settling Time (G = 100)
20mV/DIV
4µs/DIV
07035-027
Figure 37. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF
20mV/DIV
4µs/DIV
07035-028
Figure 38. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF
AD8228
Rev. 0 | Page 15 of 24
15105
OUTPUT VOLTAGE STEP SIZE (V p-p)
SETTLING TIME (µs)
07035-041
15
10
5
0
02
0
20.0
17.5
15.0
12.5
10.0
02015105
OUTPUT VOLTAGE STEP SIZE (V p-p)
SETTLING TIME (µs)
07035-042
0.001% SETTLING TIME
G = 10
R
L
= 10k
0.01% SETTLING TIME
0.001% SETTLING TIME
G = 100
R
L
= 10k
0.01% SETTLING TIME
Figure 39. Settling Time vs. Step Size, G = 10 Figure 40. Settling Time vs. Step Size, G = 100
AD8228
Rev. 0 | Page 16 of 24
THEORY OF OPERATION
C1 C2
II
I
B
COMPENSATIONI
B
COMPENSATION
V
BIAS
A1 A2
A3
R4
489
G1 G2
GAIN
SET
R3
4.889k
R2
22k
R1
22k
V1 V2
+V
S
+V
S
–V
S
+V
S
–V
S
Q1 Q2
600
–V
S
–IN
+V
S
600
–V
S
+IN
+V
S
–V
S
10k
10k
10k
10k
+V
S
–V
S
OUTPUT
REF
07035-018
Figure 41. Simplified Schematic
ARCHITECTURE
The AD8228 is based on the classic three op amp topology. This
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Figure 41 shows a simplified schematic
of the AD8228.
The first stage is composed of the A1 and A2 amplifiers, the Q1
and Q2 input transistors, and the R1 through R4 resistors. The
feedback loop of A1, R1, and Q1 ensures that the V1 voltage is
a constant diode drop below in the negative input voltage.
Similarly, V2 is kept a constant diode drop below the positive
input. Therefore, a replica of the differential input voltage is
placed across either R3 (when the gain pins are left open) or
R3||R4 (when the gain pins are shorted). The current that flows
across this resistance must also flow through the R1 and R2
resistors, creating a gained differential signal between the A2
and A1 outputs. Note that, in addition to a gained differential
signal, the original common-mode signal, shifted a diode drop
down, is also still present.
The second stage is a difference amplifier, composed of A3 and
four 10 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The AD8228 does not depend on external resistors. Much of the
dc performance of precision circuits depends on the accuracy and
matching of resistors. The resistors on the AD8228 are laid out to
be tightly matched. The resistors of each part are laser trimmed
and tested for their matching accuracy. Because of this trimming
and testing, the AD8228 can guarantee high accuracy for speci-
fications such as gain drift, common-mode rejection (CMRR),
and gain error.
SETTING THE GAIN
The AD8228 can be configured for a gain of 10 or 100 with no
external components. Leave Pin 2 and Pin 3 open for a gain of 10;
short Pin 2 and Pin 3 together for a gain of 100 (see Figure 42).
07035-003
AD8228
1
2
3
4
8
5
6
7
+V
S
–V
S
REF
–IN
+IN
AD8228
1
2
3
4
8
5
6
7
+V
S
–V
S
REF
V
OUT
V
OUT
–IN
+IN
G = 10
PIN 2 AND PIN 3 OPEN
G = 100
PIN 2 AND PIN 3 SHORTED
Figure 42. Setting the Gain
The transfer function with Pin 2 and Pin 3 open is
VOUT = 10 × (VIN+VIN−) + VREF
The transfer function with Pin 2 and Pin 3 shorted is
VOUT = 100 × (VIN+VIN−) + VREF
COMMON-MODE INPUT VOLTAGE RANGE
The three op amp architecture of the AD8228 applies gain and
then removes the common-mode voltage. Therefore, internal
nodes in the AD8228 experience a combination of both the
gained signal and the common-mode signal. This combined
signal can be limited by the voltage supplies even when the
individual input and output signals are not. Figure 10 through
Figure 13 show the allowable common-mode input voltage
ranges for various output voltages and supply voltages.
AD8228
Rev. 0 | Page 17 of 24
REFERENCE TERMINAL
The output voltage of the AD8228 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-shift
the output so that the AD8228 can drive a single-supply ADC. The
REF pin is protected with ESD diodes and should not exceed
either +VS or −VS by more than 0.3 V.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 41, the reference
terminal, REF, is at one end of a 10 k resistor. Additional imped-
ance at the REF terminal adds to this 10 k resistor and results
in amplification of the signal connected to the positive input.
The amplification from the additional RREF can be computed by
(
)
REF
REF
R
R
+
+×
k20
k102
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
INCORRECT
V
CORRECT
AD8228
OP1177
+
V
07035-005
REF
AD8228
REF
Figure 43. Driving the Reference
LAYOUT
The AD8228 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8228 pins are arranged in a logical
manner to aid in this task.
8
7
6
5
1
2
3
4
–IN
G1
G2
+V
S
V
OUT
REF
–V
S
+IN
TOP VIEW
(Not to Scale)
AD8228
07035-044
Figure 44. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
The AD8228 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances such
as line noise and its associated harmonics. The AD8228 pinout
was designed so that the board designer can take full advantage
of this performance with a well-implemented layout.
Poor layout can cause some of the common-mode signal to be
converted to a differential signal before it reaches the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, input source impedance and capacitance of each
path should be closely matched. Additional source resistance in
the input path (for example, for input protection) should be placed
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect
CMRR over frequency. If the board design has a component at
the gain setting pins (for example, a switch or jumper), the part
should be chosen so that the parasitic capacitance is as small as
possible.
Power Supplies
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect perform-
ance. See the PSRR performance curves in Figure 17 and Figure 18
for more information.
A 0.1 µF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 45, a 10 µF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
AD8228
+
V
S
+IN
–IN
LOAD
REF
0.1µF 10µF
0.1µF 10µF
–VS
VOUT
07035-006
Figure 45. Supply Decoupling, REF, and Output Referred to Local Ground
AD8228
Rev. 0 | Page 18 of 24
References
The output voltage of the AD8228 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
Input Bias Current Return Path
The input bias current of the AD8228 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 46.
THERMOCOUPLE
+V
S
REF
–V
S
AD8228
CAPACITIVELY COUPLED
+V
S
REF
C
C
–V
S
AD8228
TRANSFORMER
+V
S
REF
–V
S
AD8228
INCORRECT
CAPACITIVELY COUPLED
+V
S
REF
C
R
R
C
–V
S
AD8228
1
f
HIGH-PASS
= 2πRC
THERMOCOUPLE
+V
S
REF
–V
S
10M
AD8228
TRANSFORMER
+V
S
REF
–V
S
AD8228
CORRECT
07035-009
Figure 46. Creating an IBIAS Path
INPUT PROTECTION
All terminals of the AD8228 are protected against ESD (1 kV,
human body model). In addition, the input structure allows for
dc overload conditions of about 3.5 V beyond the supplies.
Input Voltages Beyond the Rails
For larger input voltages, an external resistor should be used in
series with each input to limit current during overload conditions.
The AD8228 can safely handle a continuous 6 mA current. The
limiting resistor can be computed from
600
mA6
SUPPLY
IN
LIMIT
VV
R
For applications where the AD8228 encounters extreme overload
voltages, such as cardiac defibrillators, external series resistors
and low leakage diode clamps such as the BAV199L, the FJH1100s,
or the SP720 should be used.
Large Differential Voltages When G = 100
When operating at a gain of 100, large differential input voltages
can cause more than 6 mA of current to flow into the inputs.
This condition occurs when the voltage between +IN and –IN
exceeds 5 V. This is true for differential voltages of either polarity.
The maximum allowed differential voltage can be increased by
adding an input protection resistor in series with each input.
The value of each protection resistor should be
RPROTECT = (VDIFF_MAX − 5 V)/6 mA
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instru-
mentation amplifier, as shown in Figure 47. The filter limits the
input signal bandwidth, according to the following relationship:
FilterFrequencyDIFF = )2(π2
1
CD CCR +
FilterFrequencyCM =
CRCπ2
1
where CD 10 CC.
R
R
AD8228
+15V
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–15V
C
D
C
C
C
C
10nF
1nF
1nF
07035-010
4.02k
4.02k
Figure 47. RFI Suppression
CD affects the difference signal, and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the R × CC
at the negative input degrades the CMRR of the AD8228. By using
a value of CD one magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
AD8228
Rev. 0 | Page 19 of 24
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE
Figure 48 shows how to configure the AD8228 for differential
output. The advantage of this circuit is that the dc differential
accuracy depends on the AD8228 and not on the op amp or the
resistors. This circuit takes advantage of the precise control the
AD8228 has of its output voltage relative to the reference voltage.
The ideal equation for the differential output is as follows:
VDIFF_OUT = VOUT+VOUT− = Gain × (VIN+VIN−)
Op amp dc performance and resistor matching determine the
dc common-mode output accuracy. However, because common-
mode errors are likely to be rejected by the next device in the
signal chain, these errors typically have little effect on overall
system accuracy. The ideal equation for the common-mode
output is as follows:
VCM_OUT = 2
+ +OUTOUT VV = VREF
For best ac performance, an op amp with at least 3 MHz gain
bandwidth product and 2 V/µs slew rate is recommended.
+IN
–IN
REF
AD8228
V
REF
10k
+
AD8641
+OUT
–OUT
07035-017
10k
Figure 48. Differential Output Using an Op Amp
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8228
make it an excellent candidate for bridge measurements. As shown
in Figure 49, the bridge can be connected directly to the inputs
of the amplifier.
5
V
2.5V
07035-011
10µF 0.1µF
AD8228
+IN
–IN
350
350350
350
+
Figure 49. Precision Strain Gage
DRIVING A DIFFERENTIAL ADC
Figure 50 shows how the AD8228 can be used to drive a
differential ADC. The AD8228 is configured with an op amp and
two resistors for differential drive. The 510  resistors and 2200
pF capacitors isolate the instrumentation amplifier from the
switching transients produced by the switched capacitor front
end of a typical SAR converter. These components between the
ADC and the amplifier also create a filter at 142 kHz, which
provides antialiasing and noise filtering. The advantage of this
configuration is that it uses less power than a dedicated ADC
driver: the AD8641 typically consumes 200 µA, and the current
through the two 10 kΩ resistors is 250 µA at full output voltage.
With the AD7688, this configuration gives excellent dc perform-
ance and a THD of 71 dB (10 kHz input). For applications that
need better distortion performance, a dedicated ADC driver, such
as the ADA4941-1 or ADA4922-1, is recommended.
07035-032
IN+ VDDREF
GND
AD7688
IN–
0.1µF
+5V
ADR435
GND
V
IN
V
OUT
0.1µF
+8
V
0.1µF 10µF
X5R
10k
10k
0.1µF
510
0.1µF
510
0.1µF
0.1µF
AD8228
+
IN
IN REF
+8V
–8V
0.1µF
0.1µF
–8V
+8V
AD8641
10k
10k
Figure 50. Driving a Differential ADC
AD8228
Rev. 0 | Page 20 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
AD8228
Rev. 0 | Page 21 of 24
ORDERING GUIDE
Model Temperature Range Package Description PackageOption Branding
AD8228ARMZ1–40°C to +85°C 8-Lead MSOP RM-8 Y16
AD8228ARMZ-RL1–40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y16
AD8228ARMZ-R71–40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y16
AD8228ARZ1–40°C to +85°C 8-Lead SOIC_N R-8
AD8228ARZ-RL1–40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8228ARZ-R71–40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8228BRMZ1–40°C to +85°C 8-Lead MSOP RM-8 Y1M
AD8228BRMZ-RL1–40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1M
AD8228BRMZ-R71–40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1M
AD8228BRZ1–40°C to +85°C 8-Lead SOIC_N R-8
AD8228BRZ-RL1–40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8228ARZ-R71–40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1 Z = RoHS Compliant Part.
AD8228
Rev. 0 | Page 22 of 24
NOTES
AD8228
Rev. 0 | Page 23 of 24
NOTES
AD8228
Rev. 0 | Page 24 of 24
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07035-0-7/08(0)