DATEL, Inc., Mansfi eld, MA 02048 (USA) • Tel: (508)339-3000, (800)233-2765 F ax: (508)339-6356 • Email: sales@datel.com • Internet: www.datel.com
12-BIT
MASTER
REGISTER
DATA
BUFFER
LEVEL
SHIFTER
UPPER
4-BIT
DECODER
SLAVE
REGISTER
8 LSBs
CURRENT
CELLS
15
SWITCHED
CURRENT
CELLS
REF CELL
OVER-RIDEABLE
VOLTAGE
REFERENCE
25
+
–
BIT 1 (MSB) 28
BIT 2 1
BIT 3 2
BIT 4 3
BIT 5 4
BIT 6 5
BIT 7 6
BIT 8 7
BIT 9 8
BIT 10 9
BIT 11 10
BIT 12 (LSB) 11
LATCH ENABLE 26
22
REF GND
23
+5V SUPPLY
12, 21
–5.2V
DIGITAL
SUPPLY
13
AGND
20
REF OUT
19
CTRL IN
15, 25
–5.2V
ANALOG
SUPPLY
27
DGND
24
R SET
R/2R
NETWORK
14 I OUT
16 I OUT
17 REF IN
18 CTRL OUT
FEATURES
• 100MHz conversion rate
• Low power , 650mW, typical
• Low glitch energy, 3.0pV-s
• Excellent dynamic specifi cations
• TTL/CMOS compatible inputs
• 20ns settling time
GENERAL DESCRIPTION
The DAC-S is a 12-bit, ultra high speed, current output
digital-to-analog converter. This TTL/CMOS compatible device
converts at a rate of 100MHz and features a 3.0pV-s glitch
energy and excellent frequency domain specifi cations.
The DAC-S develops complementary current outputs of 0 to
–20.48mA and can directly drive 50 Ohm loads. The excellent
dynamic specifi cations (to Nyquist at fOUT=2.02MHz) include
an SFDR of –85dB. Static performance includes maximum
over temperature specifi cations of ±.1.75LSB and ±1.5LSB for
integral and differential nonlinearity, respectively.
The DAC-S achieves low power and high speed performance
from an advanced BiCMOS process. The architecture employs
an R/2R resistor network and a segmented switching current
cell arrangement to reduce glitch. Laser trimming assures that
12-bit linearity is achieved and maintained over the transfer
curve. It also incorporates a 12-bit input data register and
bandgap voltage reference with a buffer amplifi er.
The DAC-S runs on +5V and –5.2V supplies and dissipates a
maximum of 802mW. It is available in a 28-pin CLCC package
1 D2 28 D1 (MSB)
2 D3 27 DGND
3 D4 26 LATCH ENABLE
4 D5 25 ANALOG VEE
5 D6 24 RSET
6 D7 23 DIGITAL VCC
7 D8 22 REF GND
8 D9 21 DIGITAL VEE
9 D10 20 REFOUT
10 D11 19 CTRLIN
11 D12 (LSB) 18 CTRLOUT
12 DIGITAL VEE 17 REFIN
13 AGND 16 IOUT
14 IOUT 15 ANALOG VEE
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION PIN FUNCTION
Figure 1. DAC-S Functional Block Diagram
PRELIMINARY PRODUCT DATA
12-Bit 100MHz
D/A Converter
DAC-S
with an operating temperature range of –55 to+125°C (DAC-
SMC has a 0 to+70°C operating temperature range).
DAC-S
2
FUNCTIONAL SPECIFICATIONS
(TA = See specifi cation table, –5.2V (A) Supply = –5.2V (D) Supply = – 4.94 to –5.46V, +5V Supply = 4.75 to 5.25V, VREF = Internal, RL = 50 Ohms and fs = 100MHz unless
otherwise specifi ed.)
Resolution 12 — — 12 — — Bits
Logic Levels
Logic "1" +2.0 — — +2.0 — — Volts
Logic "0" — — +0.8 — — +0.8 Volts
Logic Loading "1" — — 400 — — 400 µA
Logic Loading "0" — — 700 — — 700 µA
Digital Input Capacitance, CIN — 3.0 15 — 3.0 15 pF
TIMING CHARACTERISTICS
Data Setup Tim, TSU 3 2 — 3 2 — ns
Data Hold Time, THLD 0.5 0.25 — 0.5 0.25 — ns
Propagation Delay Time, tPD — 4.5 7 — 4.5 7 ns
CLOCK Pulse Width, TPW1, TPW2 3 — — 3 — — ns
STATIC PERFORMANCE
Integral Nonlinearity ➀ — ±0.75 ±1.0 — ±1.0 ±1.75 LSB
Differential Nonlinearity — ±0.5 ±.75 — 0.5 ±1 LSB
Offset Error — 0.5 5 — 5 5 µA
Gain Error ➁ — 3 10 — 3 10 %
DYNAMIC PERFORMANCE
Conversion Rate ➂ 100 — — 100 — — MHz
Output Voltage Settling Time, tSET
Full Scale Step to ±1LSB — 11 13 — 12 15 ns
Full Scale Step to ±0.5LSB — 20 22 — 20 22 ns
Glitch Area
Singlet (Peak) — 2 10 — 2 10 pV-s
Doublet (Net) — 3 — — 3 — pV-s
Output Slew Rate 900 1000 — 900 1000 — V/µs
Output Rise Time 625 675 — 625 675 — ps
Output Fall Time 425 470 — 425 470 — ps
Differential Gain — 0.15 — — 0.15 — %
Differential Phase — 0.07 — — 0.07 — Deg
Spurious Free Dynamic Range, SFDR
fCLK=10MSPS, fOUT=1.23MHz — — — — 85 82 dB
fCLK=20MSPS, fOUT=5.055MHz — — — — 77 74 dB
fCLK=40MSPS, fOUT=16 MHz — — — — 75 71 dB
fCLK=50MSPS, fOUT= 10.1MHz — — — — 80 76 dB
fCLK=80MSPS, fOUT= 5.1MHz — — — — 78 75 dB
fCLK=100MSPS, fOUT=10.1MHz — — — — 79 75 dB
Throughput rate 100 — — 100 — — MSPS
+5V Digital Supply +5.5 Volts
–5.2V Digital Supply –5.5 Volts
–5.2V Analog Supply –5.5 Volts
Digital Input Voltages – 0.5 to +5V Supply level Volts
Internal Reference Output Current ±2.5 mA
Voltage from CTRL IN to 2.5 to 0 Volts
–5.2V (A) Supply
CTRL OUT Output Current ±2.5 mA
Reference Input Voltage Range –5.2V (A) Supply Level to –3.7 Volts
Analog Output Current, IOUT 30 mA
Lead Temperature (10 seconds) 300 °C
Operating Temperature Range
DAC-SMC 0 — +70 °C
DAC-S –55 — +125 °C
Storage Temperature Range –65 — +150 °C
Thermal Resistance, θja 24 (°C/W)
Junction Temperature — — +150 °C
Package Type 28 Pin CLCC
PARAMETERS LIMITS UNITS PARAMETER MIN. TYP. MAX. UNITS
PHYSICAL/ENVIRONMENTALABSOLUTE MAXIMUM RATING
MIN. TYP. MAX. MIN. TYP. MAX. UNITS
DIGITAL INPUTS
DAC-SMC DAC-S
3
DAC-S
DYNAMIC PERFORMANCE (Cont.) MIN. TYP. MAX. MIN. TYP. MAX. UNITS
Footnotes:
➀ Best fi t straight line.
➁ Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (1.28mA typ.). Ideally the ratio should be 16.
➂ Clock frequency range is from DC to the guaranteed minimum conversion rate.
➃ Dynamic Range must be limited to a 1V swing within the compliance range.
TECHNICAL NOTES
Clock Termination
The internal 12-bit register is updated on the rising edge of
the Latch Enable (pin 26). To minimize refl ections and noise
at high clock speeds proper termination techniques should be
used. In the PCB layout the clock runs should be kept as short
as possible and have minimal loading. The PCB should employ
a controlled characteristic line impedance (Z0) of 50 Ohms. A
shunt termination resistor, equal to Z0, should be placed as
close to the CLOCK pin as possible, see Figure 2. The rise,
fall and propagation delay times will be effected by the shunt
termination resistor.
DIGITAL INPUTS
The DAC-S is TTL/CMOS compatible. Data is latched by a
Master register.
OUTPUTS
The outputs IOUT (pin 14) and IOUT (pin 16) are complementary
current outputs. Current is steered to either IOUT or IOUT in
proportion to the input code. The sum of the two currents is
ANALOG OUTPUT
Full Scale Output Current — –20.48 — — –20.48 — mA
Output Voltage Compliance ➃ –1.25 — +3.0 –1.25 — +3.0 Volts
INTERNAL REFERENCE/AMPLIFIER
Reference Voltage, VREF –1.27 –1.23 –1.17 –1.27 –1.23 –1.17 Volts
Reference Voltage Drift — 50 100 — 175 100 µV/°C
Reference Current Sink/Source Capability –125 +50 –125 — +50 µA
Reference Load Regulation (IREF = 0 to –125µA) — 50 — — 50 — µV
Reference Input (CTRL IN) Impedance — 12 — 10 12 — kOhms
Reference Input (CTRL IN)
Multiplying Bandwidth
(100mV sine wave, to -3dB loss at IOUT) 50 75 — 50 75 — MHz
Input Impedance at REF OUT 3 5 — 3 5 — kOhms
Amplifi er Large Signal Bandwidth
(4V p-p sine wave input, to slew rate limit) 1 3 — 1 3 — MHz
Amplifi er Small Signal Bandwidth
(1V p-p sine wave input, to –3dB loss) 4 10 — 4 10 — MHz
POWER REQUIREMENTS
Power Supply Ranges
+5V Supply +4.75 — +5.25 +4.75 — +5.25 Volts
–5.2V Supplies – 4.94 — –5.46 – 4.94 — –5.46 Volts
Power Supply Currents
+5V Supply — 13 20 — 13 20 mA
–5.2V Digital Supply — 70 85 — 70 95 mA
–5.2V Analog Supply — 42 50 — 42 50 mA
Power Dissipation — 650 800 — 650 800 mW
Power Supply Rejection (±5% variation) — 5 10 — 5 10 µA/V
always equal to the full scale current minus one LSB. SeeTable
1. The output can be converted to a voltage through a load
resistor, typically 50 Ohms. Both current outputs should have
the same load resistance value. See Figure 2. The output
voltage generated is:
VOUT = IOUT (ROUT || 227 Ohms)
where 227 Ohms is the nominal DAC output resistance.
1111 1111 1111 –20.48 0
1000 0000 0000 –10.24 –10.24
0000 0000 0000 0 –20.48
INPUT CODE
LSB
Table 1. Input Coding Table
IOUT (mA) IOUT (mA)
DAC-SMC
0 TO 0 C DAC-S
55 TO 125C
DAC-S
4
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12 (LSB)
26 LATCH ENABLE
27 DGND
12, 21 –5.2V (D)
28
1
2
3
4
5
6
7
8
9
10
11
50
–5.2V (D)
0.1µF 0.01µF
REF IN 17
CTRL OUT 18
REF OUT 20
I OUT 14
I OUT 16
R SET 24
AGND 13
–5.2V (A) 15, 25
0.1µF
–5.2V (A)
D/A OUT
50
50
976
–5.2V (A)
0.1µF0.01µF
DAC-S
19
CTRL IN
POWER SUPPLIES
In order to reduce power supply noise separate –5.2V analog
and digital power supplies should be used. The power supply
lines should be bypassed with 0.1µF and 0.01µF ceramic
capacitors placed as close to the –5.2V analog pins (15, 25)
and digital pins (12, 21) as possible. The analog and digital
power supply ground returns should be connected at one point
as close to the power source as possible. The +5V supply
pin (23) should be bypassed with a 0.1µF ceramic capacitor
connected as close to the pin as possible. See Figure 2.
Figure 2. Typical Connection Diagram
REFERENCE
The internal reference is a –1.23V, typical, bandgap voltage
reference. The internal reference is connected to REFOUT (pin
20) and the internal control amplifi er. CTRLOUT (pin 18) should
be connected to CTRLIN (pin 19) and to the –5.2V Analog
Supply (pins 15 and 25) through a 0.1uF ceramic capacitor.
This reduces switching noise and improves output settling time.
The Full Scale Output Current, IOUT (pin 14) and IOUT (pin 16),
is adjustable up to –20.48mA full-scale and controlled by the
REFOUT (pin 20) voltage and the RSET (pin 24) resistor through
the following equation:
Full Scale IOUT = (REFOUT Voltage/RSET Resistance) x 16
The internal reference (REFOUT) may be over-riddn with a more
precise external (–1.23V) reference, capable of delivering up
to 2mA, to provide better over temperature performance. The
reference should be applied to CTRLIN (pin 19).
5
DAC-S
Figure 3b. Full Scale Settling Time Diagram
Figure 3a. Timing Diagram
CLOCK
DATA IN
T
PW1
I
OUT
50%
t
PD
t
SET
t
HLD
T
PW2
t
SU
½ LSB
CHANGE
½ LSB
CHANGE
t
SU
t
HLD
t
SU
t
HLD
t
PD
t
SET
t
SET
t
PD
50%
CLOCK
DATA
IN
±1/2 LSB ERROR BAND
IOUT
tSET
tPD
6
DAC-S
Figure 5d. Typical DNL
Figure 5a. Typical Power Dissipation Over Temperature Figure 5b. Offset Current Over temperature
Figure 5c. Typical INL
Figure 5e. Spurious Free Dynamic Range = 70.5dB Figure 5f. Spurious Free Dynamic range = 70dB
680
640
600
560
–50 –30 –10 10 30 50 70 90
Clock Frequency Does Not
Alter Power Dissipation
Temperature
mW
28
24
20
16
12
– 40 –20 0 40 60 80 100
20
Temperature
µA
0 600 1200 1800 2400 3000 3600 4200
1.5
0.5
–0.5
1.5
Code
LSB
Code
LSB
400 1000 1600 2200 2800 3400 4000
10dB/
0.8
0.4
0.0
–0.4
–0.8
C
S
FO =2.02MHz
FC = 100MHz
C
S
Start Frequency 500 kHz Stop Frequency 40MHz
FO =2.02MHz
FC = 80MHz
10dB/
Start Frequency 500 kHz Stop Frequency 50MHz
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
Internet: www.datel.com E-mail: sales@datel.com
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do
not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.
®® DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
Internet: www.datel-europe.com E-mail: datel.ltd@datel.com
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01
Internet: www.datel-europe.com E-mail: datel.sarl@datel.com
DATEL GmbH München, Germany Tel: 89-544334-0
Internet: www.datel-europe.com E-mail: datel.gmbh@datel.com
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-6354-2025
Internet: www.datel-co.jp E-mail: salestko@datel.co.jp, salesosa@datel.co.jp
DATEL China Shanghai, China Tel: 011-86-51317131
E-mail: davidx@datel.com
ISO 9001 REGISTERED DS-0439 Preliminary 4/04
DAC-S
ORDERING INFORMATION
MODEL OPERATING TEMPERATURE RANGE PACKAGE
DAC-SMC 0 TO +70°C 28-Pin CLCC
DAC-S –55 TO +125°C 28-Pin CLCC
A
B
C
D
E
F
G
MECHANICAL DIMENSIONS INCHES (mm)
DAC-S
12-Bit 100MHz D/A Converter
A 0.300
B 0.466
C 0.450
D 0.090
E 0.420
F 0.050
G 0.055
SYMBOL INCHES
