AMENDMENT a Advanced CMOS Memory Products Micro 1991 Data Book Handbook Devices Publication: Am27C256 PID# 08007F/1 Amend this data sheet to add information on the TSOP Page 2-40 package that is now available for this product. NL CONNECTION DIAGRAM TSOP Packages OF 10 32 (2 NC Avy CJ 2 31 (2 Aso Ao (1 3 30 (2 CE As CJ 4 29 [D7 Ais CI 5 28 [J De nc CJ 6 27 (0 Ds Avs C] 7 26 [] Da Vec CJ 8 270256 25 (J) Da Veep CC 9 Standard Pinout 24 (2 Vss nc C] 10 23 [2 De Av2 CJ 11 22D, A7 (] 12 21 [3 Do Ag C] 13 20 as As Cy 14 19 Ao Ag CC 15 18 Ay A3 Cj 16 17 (9 po ORDERING INFORMATION OTP Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following elements: Lt OPTIONAL PROCESSING Blank = Standard processing ~~ AM27C256 _-90, P c TEMPERATURE RANGE C = Commercial (0 to +70C) | = Industrial (40C to +85C} PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TS 032) SPEED OPTION See Product Selector Guide and DEVICE NUMBER/DESCRIPTION Valid Combinations Am27C256 32K x 8-Bit CAOS OTP EPROM SS Valid Combinations Valld Combinations Valid Combinations list configurations planned to be AM27C256-90 JC, PC, EC supported in volume for this device. Consult the lo- AM27G256-120 cal AMD sales Office to confirm avallability of specific valid combinations or to check on newly release AM27256-150 were EC combinations, and to obtain additional data on AM27C256-200 , AMD's standard military grade products. AM27C256-255 Publication# 07606 Rav. c Amendment/1 Me tesue Date; January 1992 a enaal AMD AMENDMENT PHYSICAL DIMENSIONS TS 032 1.27 MAX O 5 0.40 0.60 ian 10 16262A BU 50 8/2791 cde CMOS Memory ProductsPublication: Am27C040 PID# 14971B/1 Pages 2-199, 2-202, 2-208 AMENDMENT Amo Zl Amend data sheet to add 170 speed version for military. PRODUCT SELECTOR GUIDE Family Part No. Am27C040 Ordering Part Number Veco +5% . -95 -125 ~155 -255 Voc + 10% -90 -120 ~150 -170 -200 -250 Max. Access Time (ns) 90 120 150 170 200 250 CE (E) Access Time (ns) 90 120 150 170 200 250 GE (G) Access Time (ns) 40 50 65 65 75 100 ORDERING INFORMATION Military APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) is formed by a combination of: AM27C040 =150 / f LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 32-Pin Ceramic DIP (CDV032) U = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) DEVICE CLASS B= Class B DEVICE NUMBER Am27C040 SPEED OPTION See Product Selector Guide and Valid Combinations 4 Megabit (512K x 8) CMOS UV EPROM Valid Combinations AM27C040-150 AM27C040-170 AM27C040-200 AM27C040-250 {BXA, /BUA For other Surface Mount Package options, contact NVD Military Marketing. Valid Combinatlons Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check newly-released combinations. Group A Tests Group A tests consist of Subgroups 1,2,3,7,8,9,10,11. CMOS Memory Products 3al AMD SWITCHING CHARACTERISTICS over operating range unless otherwise specified. (Notes 1, 3, and 4) (for APL Products, Group A, Subgroups 9, 10, and 11 are tested unless otherwise noted) AMENDMENT Parameter Am27C040 Symbols Parameter Test -90, | -120,] -150, 255, JEDEC) Standard Description Canditions -95 | -125| -155| 170 200 | -250 | Unit tavav tacc Address to CE=OEL=Vil Min. - - - - - - ns Output Delay Max 90 120 150 170 200 250 tELav tce Chip Enable to OEqVit Min. - - - - - - ns Output Delay Max 90 120 150 170 200 250 teLav toe Output Enable to CE=Vit Min. - - - - - ~ ns Output Delay Max 40 50 65 65 75 100 tEHQz tDF Chip Enable HIGH or Min. _ 0 0 0 0 0 iGHaz | (Note 2) | Output Enable HIGH, ns whichever comes 6 first, to Output Float Max 30 40 50 50 60 0 TAXQX 10H Output Hold from Min. 0 0 0 0 0 0 Addresses, CE, or OF, ns whichever occurred first Max - - - - - - Note: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. . This parameter is only sampled, not 100% tested. 2 3. Caution: The Am27C040 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. 4 . QOutupt Load: 1 TTL gate and Ci = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 to 2.4 V Timing Measurement Reference Level Inputs: 0.8 ta 2.0V Outputs: 0.8 to 2.0 V CMOS Memory ProductsPublications: Am7200 PID# 10804E/1 Pages 6-15, 6-17; Am7201 PID# 10175F/1 Pages 6-30, 6-32 AMENDMENT AMD al For -50, -65 Speed options: Decreased Parameter twiz, Write Pulse High to Data Bus at Low Z, from 15 ns to 10 ns. Decreased Parameter traiz, Read Pulse Low to Data Bus at Low Z, from 10 ns to 5ns. For -80 Speed option: Decreased Parameter twiz, Write Pulse High to Data Bus at Low Z, from 20 ns to 10 ns. Decreased Parameter taiz, Read Pulse Low to Data Bus at Low Z, from 10 ns to 5 ns. The following parameters and waveforms (see pages 7 and 8) have been added: AC SPECIFICATIONS Commercial and Military COM MIL COM/MIL Parameter Description Figure} -25 | -35 -40 | -50 -65 | -80 |Units tWwPF Write Pulse Width after FF High Min. 8 25 35 40 50 65 80 ns tAPE Read Pulse Width after EF High Min. 9 25 35 40 50 65 80 ns taTS Retransmit Setup Time (Note 1) Min. 7 25 35 40 50 65 80 ns txot ReadMrite to XO Low Max A 25 35 40 50 65 80 | ns txOH ReadMrite to XO High Max A 25 35 40 50 65 80 | ns ma XI Pulse Width (Note 1) Min. B 25 35 40 50 65 80 ns txIR XI Recovery Time (Note 1) Min. B 10 10 10 10 10 10 | ns txIs XI Setup Time Min. B 10 10 10 10 15 15 | ns Note: 1. Values are guaranteed by design and are not currently tested. CMOS Memory Products 5oN amp AMENDMENT Publications: Am7202A PID# 15491A/1 Pages 6-47, 6-49 Am7203A PID# 15492A/1 Pages 6-64, 6-66 Am7204A PID# 14430B/1 Pages 6-81, 6-83 For 15 Speed option: Increased Parameter twer, Write Low to Full Flag Low, from 22 ns to 24 ns. Increased Parameter twer, Write High to Empty Flag High, from 22 ns to 24 ns. increased Parameter tarr, Read High to Full Flag High, from 22 ns to 24 ns. Increased Parameter trer, Read Low to Empty Flag Low, from 22 ns to 24 ns. Increased Parameter tat, Retransmit Pulse Width, from 20 ns to 35 ns. Increased Parameter trtc, Retransmit Cycle Time, from 30 ns to 45 ns. For -25 Speed option: Increased Parameter tat, Retransmit Pulse Width, from 25 ns to 35 ns. Increased Parameter tatc, Retransmit Cycle Time, from 35 ns to 45 ns. For -50 Speed option: Decreased Parameter twiz, Write Pulse High to Data Bus at Low Z, from 15 ns to 10 ns. Decreased Parameter triz, Read Pulse Low to Data Bus at Low Z, from 10 ns to 5 ns. The following parameters and waveforms (see pages 6 and 7) have been added: AC SPECIFICATIONS Commercial and Military COM MIL Parameter Description Figure] -15 | ~25 | -35 | -50 -30 | -50 [Units twPF Write Pulse Width after FF High Min. 8 15 25 35 50 30 50 ns {APE Read Pulse Width after EF High Min. 9 15 25 35 50 30 50 ns taTS Retransmit Setup Time (Note 1) Min. 7 15 25 35 50 30 50 ns txou ReadMrite to XO Low Max. A 25 25 35 50 30 50 | ns txOH Read/Write to XO High Max. A 25 25 35 50 30 50 | ns tx! XI Pulse Width (Note 1) Min. B 15 25 35 50 30 50 ns xin XI Recovery Time (Note 1) Min. B 10 10 10 10 10 10 | as txis Xi Setup Time Min. B 10 10 10 10 15 15 | ns Note: 1. Values are guaranteed by design and are not currently tested. 6 CMOS Memory ProductsAMENDMENT Publication: Am7205A PID#14191B/1 Page 6-97 AMD Ll For 15 Speed option: increased Parameter twrr, Write Low to Full Flag Low, from 22 ns to 24 ns. increased Parameter twer, Write High to Empty Flag High, from 22 ns to 24 ns. Increased Parameter tree, Read High to Full Flag High, from 22 ns to 24 ns. Increased Parameter trer, Read Low to Empty Flag Low, from 22 ns to 24 ns. Increased Parameter tat, Retransmit Pulse Width, from 20 ns to 25 ns. Increased Parameter tatc, Retransmit Cycle Time, from 40 ns to 45 ns. Increased Parameter ter., Reset to Empty Flag Low, from 25 ns to 30 ns. The following parameters and waveforms (see pages 7 and 8) have been added: AC SPECIFICATIONS Commercial COM Parameter Description Figure -15 -25 -35 Units twPr Write Pulse Width after FF High Min. 8 15 25 35 ns tRPE Read Pulse Width atter EF High Min. 9 15 25 35 ns ATS Ratransmit Setup Time (Note 1) Min. 7 15 25 35 ns txoL ReadMrite to XO Low Max. A 25 25 35 ns txon ReadMrite to XO High Max. A 25 25 35 ns tx) XI] Pulse Width (Note 1) Min. B 15 25 35 ns txiA XI Recovery Time (Note 1) Min. B 10 10 10 ns txis XI Setup Time Min. B 10 10 10 ns Note: 1. Values are guaranteed by design and are not currently tested. SWITCHING WAVEFORMS Write to last Read from last location location WwW XO 15589-003B Figure A. XO Delay from Clock CMOS Memory Preducts 7of AMD AMENDMENT txt | bur m tf txIs ~ Write to 1st location (xis Read from 1st location R 15589-004B Figure B. 1st Clock Pulse Delay from Xi ?_. tat FURT \ t tats {ATR R NL / trTc Note: 14430-0108 EF, HF and FF may change state during Retransmit as a result of the offset of the read and write pointers, but the flags will be valid at trtc. Figure 7. Retransmit Timing 8 CMOS Memory ProductsAMENDMENT AMo Zl Publications: The following changes have been implemented to the AC 67C401113 67C402/23 PID#10998C/1 Page 6-103; Specifications for both of these datasheets: 67C4033 PID# 10684A/1 Page 6-111 Change Change from: 10: 10 MHz tiRH Shift in J to 50 ns max 55 ns max Input Ready HIGH tsi Shift in HIGH time 14 ns min 16 ns min tsit Shift in LOW time 25 ns min 30 ns min tsou Shift out LOW time 25 ns min 30 ns min topH Output Ready pulse HIGH 14 ns min 16 ns min 15 MHz tiAH Shift in 1 to 50 ns max 55 ns max Input Ready HIGH torL Shift Out T 45 ns max 47 ns max Output Ready LOW torH Shift Out 1 41 ns max 47 ns max Output Ready HIGH tons Output Data Shift (next word) 30 ns max 33 ns max tstH Shift in HIGH time 14 ns min 16 ns min tsiL Shift in LOW time 25 ns min 30 ns min tsor Shift out LOW time 25 ns min 30 ns min toPH Output Ready pulse HIGH 14 ns min 16 ns min CMOS Memory Products 9Sales Offices North American ALABAMA (205) 882-9122 ARIZONA... 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(216) 899-9370 (414) 789-9393 Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics. The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative. The company assumes no responsibility for the use of any circuits described herein. RECYCLED & RECYCLABLE Tel: (408) 732-2400 + TWX: 910-339-9280 TELEX: 34-6306 TOLL FREE: (800) 538-8450 al Advanced Micro Devices, inc. 901 Thampson Place, P.O. Box 3463, Sunnyvale, CA 94088, USA i APPLICATIONS HOTLINE & LITERATURE ORDERING + TOLL FREE: (800) 222-9323 1992 Advanced Micro Devices, inc. 120/02 + (408) 749-5703 WCP-26M-2/92-0 Printed in USA lal